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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity and_nghdl is
+ port (e : in std_logic_vector(0 downto 0);
+ f : in std_logic_vector(0 downto 0);
+ g : out std_logic_vector(0 downto 0));
+ end and_nghdl;
+
+ architecture rtl of and_nghdl is
+ begin
+
+ g <= e and f;
+
+ end rtl;