Samples of VHDL code added for testing

1 files changed, 15 insertions, 0 deletions

diff --git a/VHDL/or_nghdl.vhdl b/VHDL/or_nghdl.vhdl
new file mode 100644
index 0000000..92e36a8
--- /dev/null
+++ b/VHDL/or_nghdl.vhdl
@@ -0,0 +1,15 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity or_nghdl is
+       port (x : in  std_logic_vector(0 downto 0); 
+             y : in  std_logic_vector(0 downto 0);
+             z : out std_logic_vector(0 downto 0)); 
+     end or_nghdl;
+     
+     architecture rtl of or_nghdl is
+     begin
+        
+        z <= x or y;
+        
+     end rtl;