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authorAmbikeshwar2016-05-25 14:21:10 +0530
committerAmbikeshwar2016-05-25 14:21:10 +0530
commit10ffe344f141a49496b85cc780ffe85d7f084219 (patch)
treefafeaaa6b9d3588632f9599f6f438e47340c199e /Netlist/inverter.vhdl
parentb503d66fcc1e26be28b58cccf888e43f99d35ae2 (diff)
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Sample netlist addedHEADmaster
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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity inverter is
+ port ( i: in std_logic_vector(0 downto 0);
+ o: out std_logic_vector(0 downto 0));
+end inverter;
+
+architecture inverter_beh of inverter is
+begin
+ o <= not i;
+end architecture;
+
+