Sample netlist addedHEADmaster

13 files changed, 539 insertions, 0 deletions

diff --git a/Netlist/2-bit-inverter.cir b/Netlist/2-bit-inverter.cir
new file mode 100644
index 0000000..82b9330
--- /dev/null
+++ b/Netlist/2-bit-inverter.cir
@@ -0,0 +1,36 @@
+* analysis type *
+.tran 1n 100n
+*
+* input sources *
+v1 100 0 DC PWL ( 0n 0.0 5n 0.0 5.1n 2.0 10n 0.0 10.1n 2.0 15n 2.0 15.1n 2.0 20n 0 20.1n 2.0 25n 2.0 25.1n 2.0 30n 2.0 30.1n 2.0
+               + 40n 0.0 50n 0.0 50.1n 2.0 60n 2.0 60.1n 0.0 70n 0.0 70.1n 2.0 80n 2.0 80.1n 0.0 90n 0.0 100n 2.0)
+
+v2 200 0 DC PWL ( 0n 2.0 5n 2.0 5.1n 0.0 10n 0.0 10.1n 2.0 15n 2.0 15.1n 0.0 20n 0 20.1n 2.0 25n 2.0 25.1n 0.0 30n 2.0 30.1n 2.0
+               + 40n 0.0 50n 0.0 50.1n 2.0 60n 2.0 60.1n 0.0 70n 0.0 70.1n 2.0 80n 2.0 80.1n 0.0 90n 0.0 100n 2.0)
+
+* resistors to ground *
+r1 100 0 1k
+r2 200 0 1k
+
+rload1 300 0 10k
+*rload2 400 0 10k
+*
+* adc_bridge blocks *
+aconverter1 [100 200]  [1 2] adc_bridge1
+
+.model adc_bridge1 adc_bridge ( in_low =0.3 in_high =0.7
++ rise_delay =1.0e-12 fall_delay =1.0e-12)
+
+ainverter [1] [10]  inv1
+and1 [2] [10] [11] and_gate
+.model inv1 inverter(instance_id = 101 rise_delay = 1.0e-12 fall_delay = 1.0e-12 stop_time=90e-9)
+.model and_gate and_nghdl(instance_id = 110 rise_delay = 1.0e-12 fall_delay = 1.0e-12 stop_time=90e-9)
+
+aconverter2 [11] [30] dac_bridge1
+
+.model dac_bridge1 dac_bridge( out_low=0.25 out_high=5.0 
++out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) 
+
+.end
+ 
+
diff --git a/Netlist/Flipflop.cir b/Netlist/Flipflop.cir
new file mode 100644
index 0000000..b514ac3
--- /dev/null
+++ b/Netlist/Flipflop.cir
@@ -0,0 +1,40 @@
+* analysis type *
+.tran 1ns 100ns 0ns
+
+* 
+* input sources *
+*V1 100 0 DC 5
+
+*V2 200 0 PWL ( 0n 2.0 0.00000000005n 0 5n 0.0 5.00000000005n 2.0 10n 2.0 10.00000000005n 0.0 15n 0.0 15.00000000005n 2.0 20n 2 20.00000000005n 0.0 25n 0.0 25.00000000005n 2.0 30n 2.0 30.00000000005n 0.0 40n 0.0 40.00000000005n 2.0 50n 2.0 50.00000000005n 0.0 60n 0.0 60.00000000005n 2.0 70n 2.0 70.00000000005n 0.0 80n 0.0 80.00000000005n 2.0 90n 2.0 90.00000000005n 0.0 100n 0.0 100.00000000005n 2.0)
+
+*V3 300 0 DC 0
+
+V1 100 0 PULSE (2 0 0 .0000001ns 0.0000001ns 10ns 20ns)
+V2 200 0 PULSE (2 0 0 .0000001ns 0.0000001ns 50ns 100ns)
+V3 300 0 PULSE (2 0 0 .0000001ns 0.0000001ns 30ns 60ns)
+* resistors to ground *
+r1 100 0 1Meg
+r2 200 0 1Meg
+r3 300 0 1Meg
+
+rload1 400 0 1Meg
+
+*
+* adc_bridge blocks *
+aconverter1 [100 200 300]  [1 2 3] adc_bridge1
+
+.model adc_bridge1 adc_bridge ( in_low =0.3 in_high =0.7
++ rise_delay =1.0e-12 fall_delay =1.0e-12)
+
+a3 [1] [2] [3] [4] ff
+
+.model ff flipflop(instance_id = 13 rise_delay = 1.0e-12 fall_delay = 1.0e-12 stop_time= 90.0e-9)
+
+* dac_bridge blocks *
+aconverter2 [4] [400] dac_bridge1
+
+.model dac_bridge1 dac_bridge( out_low=0.25 out_high=5.0 
++out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) 
+
+.end
+
diff --git a/Netlist/Flipflop2.cir b/Netlist/Flipflop2.cir
new file mode 100644
index 0000000..06e2581
--- /dev/null
+++ b/Netlist/Flipflop2.cir
@@ -0,0 +1,40 @@
+* analysis type *
+.tran 1ns 100ns 0ns
+
+* 
+* input sources *
+*V1 100 0 DC 5
+
+*V2 200 0 PWL ( 0n 2.0 0.00000000005n 0 5n 0.0 5.00000000005n 2.0 10n 2.0 10.00000000005n 0.0 15n 0.0 15.00000000005n 2.0 20n 2 20.00000000005n 0.0 25n 0.0 25.00000000005n 2.0 30n 2.0 30.00000000005n 0.0 40n 0.0 40.00000000005n 2.0 50n 2.0 50.00000000005n 0.0 60n 0.0 60.00000000005n 2.0 70n 2.0 70.00000000005n 0.0 80n 0.0 80.00000000005n 2.0 90n 2.0 90.00000000005n 0.0 100n 0.0 100.00000000005n 2.0)
+
+*V3 300 0 DC 0
+
+V1 100 0 PULSE (2 0 0 .0000001ns 0.0000001ns 10ns 20ns)
+V2 200 0 PULSE (2 0 0 .0000001ns 0.0000001ns 50ns 100ns)
+V3 300 0 PULSE (2 0 0 .0000001ns 0.0000001ns 30ns 60ns)
+* resistors to ground *
+r1 100 0 1Meg
+r2 200 0 1Meg
+r3 300 0 1Meg
+
+rload1 400 0 1Meg
+
+*
+* adc_bridge blocks *
+aconverter1 [100 200 300]  [1 2 3] adc_bridge1
+
+.model adc_bridge1 adc_bridge ( in_low =0.3 in_high =0.7
++ rise_delay =1.0e-12 fall_delay =1.0e-12)
+
+a3 [1] [2] [3] [4] ff
+a4 [1] [2] [4] [5] ff
+.model ff flipflop(instance_id = 13 rise_delay = 1.0e-12 fall_delay = 1.0e-12 stop_time= 90.0e-9)
+*.model ff1 flipflop(instance_id = 14 rise_delay = 1.0e-12 fall_delay = 1.0e-12 stop_time= 80.0e-9)
+* dac_bridge blocks *
+aconverter2 [5] [400] dac_bridge1
+
+.model dac_bridge1 dac_bridge( out_low=0.25 out_high=5.0 
++out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) 
+
+.end
+
diff --git a/Netlist/Flipflop_inv.cir b/Netlist/Flipflop_inv.cir
new file mode 100644
index 0000000..40c4092
--- /dev/null
+++ b/Netlist/Flipflop_inv.cir
@@ -0,0 +1,41 @@
+* analysis type *
+.tran 1ns 100ns 0ns
+
+* 
+* input sources *
+*V1 100 0 DC 5
+
+*V2 200 0 PWL ( 0n 2.0 0.00000000005n 0 5n 0.0 5.00000000005n 2.0 10n 2.0 10.00000000005n 0.0 15n 0.0 15.00000000005n 2.0 20n 2 20.00000000005n 0.0 25n 0.0 25.00000000005n 2.0 30n 2.0 30.00000000005n 0.0 40n 0.0 40.00000000005n 2.0 50n 2.0 50.00000000005n 0.0 60n 0.0 60.00000000005n 2.0 70n 2.0 70.00000000005n 0.0 80n 0.0 80.00000000005n 2.0 90n 2.0 90.00000000005n 0.0 100n 0.0 100.00000000005n 2.0)
+
+*V3 300 0 DC 0
+
+V1 100 0 PULSE (2 0 0 .0000001ns 0.0000001ns 10ns 20ns)
+V2 200 0 PULSE (0 2 0 .0000001ns 0.0000001ns 20ns 40ns)
+V3 300 0 PULSE (2 0 0 .0000001ns 0.0000001ns 50ns 100ns)
+* resistors to ground *
+r1 100 0 1Meg
+r2 200 0 1Meg
+r3 300 0 1Meg
+
+rload1 400 0 1Meg
+
+*
+* adc_bridge blocks *
+aconverter1 [100 200 300]  [1 2 3] adc_bridge1
+
+.model adc_bridge1 adc_bridge ( in_low =0.3 in_high =0.7
++ rise_delay =1.0e-12 fall_delay =1.0e-12)
+
+a3 [1] [2] [3] [4] ff
+
+a4 [4] [5] inv
+.model ff flipflop(instance_id = 13 rise_delay = 1.0e-12 fall_delay = 1.0e-12 stop_time= 90.0e-9)
+.model inv inverter(instance_id = 14 rise_delay = 1.0e-12 fall_delay = 1.0e-12 stop_time= 90.0e-9)
+* dac_bridge blocks *
+aconverter2 [4] [400] dac_bridge1
+
+.model dac_bridge1 dac_bridge( out_low=0.25 out_high=5.0 
++out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) 
+
+.end
+
diff --git a/Netlist/counter.cir b/Netlist/counter.cir
new file mode 100644
index 0000000..b182aea
--- /dev/null
+++ b/Netlist/counter.cir
@@ -0,0 +1,39 @@
+* analysis type *
+.tran 1us 200us 0us
+
+* 
+* input sources *
+*V1 100 0 PWL ( 0u 0 0.0000000005u 5.0 10u 5.0 10.00000000005u 0.0 20u 0.0 20.00000000005u 0.0 30u 0.0 30.00000000005u 0.0 40u 0.0 40.00000000005u 0.0 50u 0.0 50.00000000005u 0.0 60u 0.0 60.00000000005u 0.0 70u 0.0 70.00000000005u 0.0 80u 0.0 80.00000000005u 0.0 90u 0.0 90.00000000005u 0.0 100u 0.0)
+*V1 100 0 DC 2.0
+*V2 200 0 PWL ( 0u 2.0 0.00000000005u 0 5u 0.0 5.00000000005u 2.0 10u 2.0 10.00000000005u 0.0 15u 0.0 15.00000000005u 2.0 20u 2 20.00000000005u 0.0 25u 0.0 25.00000000005u 2.0 30u 2.0 30.00000000005u 0.0 40u 0.0 40.00000000005u 2.0 50u 2.0 50.00000000005u 0.0 60u 0.0 60.00000000005u 2.0 70u 2.0 70.00000000005u 0.0 80u 0.0 80.00000000005u 2.0 90u 2.0 90.00000000005u 0.0 100u 0.0 100.00000000005u 2.0)
+V1 200 0 PULSE (2 0 0 .0000001ns 0.0000001ns 70us 140us)
+V2 100 0 PULSE (2 0 0 .0000001ns 0.0000001ns 10us 20us)
+
+
+* resistors to ground *
+r1 100 0 1Meg
+r2 200 0 1Meg
+
+rload1 300 0 1Meg
+rload2 400 0 1Meg
+rload3 500 0 1Meg
+rload4 600 0 1Meg
+
+*
+* adc_bridge blocks *
+aconverter1 [100 200]  [1 2] adc_bridge1
+
+.model adc_bridge1 adc_bridge ( in_low =0.3 in_high =0.7
++ rise_delay =1.0e-12 fall_delay =1.0e-12)
+
+ac1 [1] [2] [3 4 5 6] count1
+
+.model count1 counter(rise_delay = 1.0e-7 fall_delay = 1.0e-7 stop_time= 190.0e-6)
+
+* dac_bridge blocks *
+aconverter2 [3 4 5 6] [300 400 500 600] dac_bridge1
+
+.model dac_bridge1 dac_bridge( out_low=0.25 out_high=5.0 
++out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) 
+
+.end
diff --git a/Netlist/counter_mod.cir b/Netlist/counter_mod.cir
new file mode 100644
index 0000000..6f2f0e4
--- /dev/null
+++ b/Netlist/counter_mod.cir
@@ -0,0 +1,42 @@
+* analysis type *
+.tran 1us 200us 0us
+
+* 
+* input sources *
+*V1 100 0 PWL ( 0u 0 0.0000000005u 5.0 10u 5.0 10.00000000005u 0.0 20u 0.0 20.00000000005u 0.0 30u 0.0 30.00000000005u 0.0 40u 0.0 40.00000000005u 0.0 50u 0.0 50.00000000005u 0.0 60u 0.0 60.00000000005u 0.0 70u 0.0 70.00000000005u 0.0 80u 0.0 80.00000000005u 0.0 90u 0.0 90.00000000005u 0.0 100u 0.0)
+*V1 100 0 DC 2.0
+*V2 200 0 PWL ( 0u 2.0 0.00000000005u 0 5u 0.0 5.00000000005u 2.0 10u 2.0 10.00000000005u 0.0 15u 0.0 15.00000000005u 2.0 20u 2 20.00000000005u 0.0 25u 0.0 25.00000000005u 2.0 30u 2.0 30.00000000005u 0.0 40u 0.0 40.00000000005u 2.0 50u 2.0 50.00000000005u 0.0 60u 0.0 60.00000000005u 2.0 70u 2.0 70.00000000005u 0.0 80u 0.0 80.00000000005u 2.0 90u 2.0 90.00000000005u 0.0 100u 0.0 100.00000000005u 2.0)
+V1 200 0 PULSE (2 0 0 .0000001ns 0.0000001ns 70us 140us)
+V2 100 0 PULSE (2 0 0 .0000001ns 0.0000001ns 10us 20us)
+
+
+* resistors to ground *
+r1 100 0 1Meg
+r2 200 0 1Meg
+
+*rload1 300 0 1Meg
+rload2 400 0 1Meg
+rload3 500 0 1Meg
+*rload4 600 0 1Meg
+
+*
+* adc_bridge blocks *
+aconverter1 [100 200]  [1 2] adc_bridge1
+
+.model adc_bridge1 adc_bridge ( in_low =0.3 in_high =0.7
++ rise_delay =1.0e-12 fall_delay =1.0e-12)
+
+ac1 [1] [2] [3 4 5 6] count1
+ac2 [3] [4] [34] and
+ac3 [5] [6] [56] or
+.model and and_nghdl(instance_id=11 rise_delay = 1.0e-7 fall_delay = 1.0e-7 stop_time= 190.0e-6) 
+.model or or_nghdl(instance_id=12 rise_delay = 1.0e-7 fall_delay = 1.0e-7 stop_time= 190.0e-6)
+.model count1 counter(instance_id=10 rise_delay = 1.0e-7 fall_delay = 1.0e-7 stop_time= 190.0e-6)
+
+* dac_bridge blocks *
+aconverter2 [34 56] [400 500] dac_bridge1
+
+.model dac_bridge1 dac_bridge( out_low=0.25 out_high=5.0 
++out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9) 
+
+.end
diff --git a/Netlist/inverter.vhdl b/Netlist/inverter.vhdl
new file mode 100644
index 0000000..b9641fd
--- /dev/null
+++ b/Netlist/inverter.vhdl
@@ -0,0 +1,14 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity inverter is
+    port ( i: in std_logic_vector(0 downto 0);
+           o: out std_logic_vector(0 downto 0));
+end inverter;
+
+architecture inverter_beh of inverter is
+begin
+    o <= not i;
+end architecture;
+
+
diff --git a/Netlist/op-amp-inv.cir b/Netlist/op-amp-inv.cir
new file mode 100644
index 0000000..ceb40c0
--- /dev/null
+++ b/Netlist/op-amp-inv.cir
@@ -0,0 +1,39 @@
+*Including the predefined op-amp subcircuit file
+.include ua741.txt
+*Connections as mentioned in subcircuit file
+
+.tran 1n 100n 0
+x1 1 2 3 4 5 UA741
+R1 an1 2 1k
+R2 an2 1 1k
+R3 5 2 2k
+R4 1 0 2k
+R5 5 out 1k
+R6 out 0 1k
+
+vin1 in1_an 0 PULSE (2 0 0 .0000001ns 0.0000001ns 50ns 100ns)
+vin2 in2_an 0 PULSE (2 0 0 .0000001ns 0.0000001ns 10ns 20ns)
+
+rin1 in1_an 0 1Meg
+rin2 in2_an 0 1Meg
+a1 [in1] [in2] [dg1] and_gate
+.model and_gate and_nghdl(instance_id = 12 rise_delay = 1.0e-10 fall_delay = 1.0e-10 stop_time=90n)
+.model or_gate or_nghdl(instance_id = 11 rise_delay = 1.0e-10 fall_delay = 1.0e-10 stop_time=90n)
+.model inv1 inverter(instance_id = 101 rise_delay = 1.0e-10 fall_delay = 1.0e-10 stop_time=90n)
+a2 [in1] [in2] [dg2] or_gate
+a3 [out] [dig_out] adc
+ainv [dig_out] [out_main] inv1
+*adc_bridge
+aconverter1 [in1_an in2_an] [in1 in2] adc
+*dac_bridge
+aconverter2 [dg1 dg2] [an1 an2] dac
+.model adc adc_bridge ( in_low =0.5 in_high =1.0
++                   rise_delay =1.0e-10 fall_delay =1.0e-10)
+.model dac dac_bridge(out_low = 0.0 out_high = 2.0 out_undef = 1.0
++                      input_load = 5.0e-14 t_rise = 1.0e-10 t_fall = 1.0e-10)
+
+
+vcc 3 0 dc 15v
+vee 4 0 dc -15v
+*Giving a sinusoidal input
+.end
diff --git a/Netlist/op-amp.cir b/Netlist/op-amp.cir
new file mode 100644
index 0000000..46a33ce
--- /dev/null
+++ b/Netlist/op-amp.cir
@@ -0,0 +1,37 @@
+*Including the predefined op-amp subcircuit file
+.include ua741.txt
+*Connections as mentioned in subcircuit file
+
+.tran 1n 100n 0
+x1 1 2 3 4 5 UA741
+R1 an1 2 1k
+R2 an2 1 1k
+R3 5 2 2k
+R4 1 0 2k
+R5 5 out 1k
+R6 out 0 1k
+
+vin1 in1_an 0 PULSE (2 0 0 .0000001ns 0.0000001ns 50ns 100ns)
+vin2 in2_an 0 PULSE (2 0 0 .0000001ns 0.0000001ns 10ns 20ns)
+
+rin1 in1_an 0 1Meg
+rin2 in2_an 0 1Meg
+a1 [in1] [in2] [dg1] and_gate
+.model and_gate and_nghdl(instance_id = 12 rise_delay = 1.0e-10 fall_delay = 1.0e-10 stop_time=90n)
+.model or_gate or_nghdl(instance_id = 11 rise_delay = 1.0e-10 fall_delay = 1.0e-10 stop_time=90n)
+a2 [in1] [in2] [dg2] or_gate
+
+*adc_bridge
+aconverter1 [in1_an in2_an] [in1 in2] adc
+*dac_bridge
+aconverter2 [dg1 dg2] [an1 an2] dac
+.model adc adc_bridge ( in_low =0.5 in_high =1.0
++                   rise_delay =1.0e-10 fall_delay =1.0e-10)
+.model dac dac_bridge(out_low = 0.0 out_high = 2.0 out_undef = 1.0
++                      input_load = 5.0e-14 t_rise = 1.0e-10 t_fall = 1.0e-10)
+
+
+vcc 3 0 dc 15v
+vee 4 0 dc -15v
+*Giving a sinusoidal input
+.end
diff --git a/Netlist/test2.cir b/Netlist/test2.cir
new file mode 100644
index 0000000..9f9f33a
--- /dev/null
+++ b/Netlist/test2.cir
@@ -0,0 +1,55 @@
+
+*** input sources ***
+
+*v1 100 0 DC PWL ( 0n 0.0 5n 0.0 5.1n 2.0 10n 2.0 10.1n 2.0 15n 2.0 15.1n 0.0 20.0n 0.0 20.1n 2.0 25n 2.0 25.1n 0.0 30n 0.0 30.1n 2.0
+*		+40.0 2.0 40.1n 0.0 50n 0.0 50.1n 2.0 60n 2.0 60.1n 0.0 70n 0.0 70.1n 2.0 80n 2.0 80.1n 0.0 90n 0.0 100n 0.0)
+
+*v2 200 0 DC PWL (0n 2.0 5n 2.0 10n 2.0 15n 2.0 15.1n 0.0 20n 0.0 25n 0.0 30n 0.0 30.1n 2.0 40n 2.0 40.1n 0.0 45n 0.0 45.1n 2.0 
+*		+ 50n 2.0 50.1n 0.0 60.0n 0.0 70n 0.0 80n 0.0 90n 0.0 95n 0.0 95.1n 2.0 100n 2.0)
+
+vin1 100 0 PULSE (5 0 0 .0000001ns 0.0000001ns 50ns 100ns)
+vin2 200 0 PULSE (5 0 0 .0000001ns 0.0000001ns 10ns 20ns)
+vin3 300 0 PULSE (5 0 0 .0000001ns 0.0000001ns 20ns 40ns)
+vin4 400 0 PULSE (5 0 0 .0000001ns 0.0000001ns 30ns 60ns)
+
+Vvdd vdd 0 DC 2.0
+
+*** resistors to ground ***
+r1 100 0 1k
+r2 200 0 1k
+r3 300 0 1k
+r4 400 0 1k
+
+*
+*** adc_bridge blocks ***
+aconverter1 [100 200 300 400] [1 2 3 4] adc
+
+aor1 [1] [2] [12] or1
+and1 [3] [4] [34] and_gate
+axor [12] [34]  [1234] axors
+adac1 [1234] [out]  dac
+
+*************model***********
+
+.model axors myxor(instance_id = 112 rise_delay = 1.0e-10 fall_delay = 1.0e-10 stop_time=90n)
+.model and_gate and_nghdl(instance_id = 14 rise_delay = 1.0e-10 fall_delay = 1.0e-10 stop_time=90n)
+
+.model or1 or_nghdl(instance_id = 11 rise_delay = 1.0e-10 fall_delay = 1.0e-10 stop_time=90n)
+
+.model adc adc_bridge ( in_low =0.5 in_high =1.0
++                   rise_delay =1.0e-10 fall_delay =1.0e-10)
+.model dac dac_bridge(out_low = 0.0 out_high = 2.0 out_undef = 1.0
++                      input_load = 5.0e-14 t_rise = 1.0e-10
++                      t_fall = 1.0e-10)
+
+
+.end
+
+
+
+.CONTROL
+
+option noopalter
+tran .1n 100n
+.ENDC
+
diff --git a/Netlist/test4.cir b/Netlist/test4.cir
new file mode 100644
index 0000000..008a4e3
--- /dev/null
+++ b/Netlist/test4.cir
@@ -0,0 +1,56 @@
+
+*** input sources ***
+
+*v1 100 0 DC PWL ( 0n 0.0 5n 0.0 5.1n 2.0 10n 2.0 10.1n 2.0 15n 2.0 15.1n 0.0 20.0n 0.0 20.1n 2.0 25n 2.0 25.1n 0.0 30n 0.0 30.1n 2.0
+*		+40.0 2.0 40.1n 0.0 50n 0.0 50.1n 2.0 60n 2.0 60.1n 0.0 70n 0.0 70.1n 2.0 80n 2.0 80.1n 0.0 90n 0.0 100n 0.0)
+
+*v2 200 0 DC PWL (0n 2.0 5n 2.0 10n 2.0 15n 2.0 15.1n 0.0 20n 0.0 25n 0.0 30n 0.0 30.1n 2.0 40n 2.0 40.1n 0.0 45n 0.0 45.1n 2.0 
+*		+ 50n 2.0 50.1n 0.0 60.0n 0.0 70n 0.0 80n 0.0 90n 0.0 95n 0.0 95.1n 2.0 100n 2.0)
+
+vin1 100 0 PULSE (5 0 0 .0000001ns 0.0000001ns 50ns 100ns)
+vin2 200 0 PULSE (5 0 0 .0000001ns 0.0000001ns 10ns 20ns)
+vin3 300 0 PULSE (5 0 0 .0000001ns 0.0000001ns 20ns 40ns)
+vin4 400 0 PULSE (5 0 0 .0000001ns 0.0000001ns 30ns 60ns)
+
+Vvdd vdd 0 DC 2.0
+
+*** resistors to ground ***
+r1 100 0 1k
+r2 200 0 1k
+r3 300 0 1k
+r4 400 0 1k
+
+*
+*** adc_bridge blocks ***
+aconverter1 [100 200 300 400] [1 2 3 4] adc
+
+aor1 [1] [2] [12] or1
+and1 [3] [4] [34] and_gate
+axor [34] [12]  [1234] axors
+*ainv [1234] [12345] inv1
+adac1 [1234] [out]  dac
+
+*************model***********
+
+.model axors myxor(instance_id = 12 rise_delay = 1.0e-10 fall_delay = 1.0e-10 stop_time=90n)
+.model and_gate and_nghdl(instance_id = 11 rise_delay = 1.0e-10 fall_delay = 1.0e-10 stop_time=90n)
+*.model inv1 inverter(instance_id = 13 rise_delay = 1.0e-10 fall_delay = 1.0e-10 stop_time=80n)
+.model or1 or_nghdl(instance_id = 14 rise_delay = 1.0e-10 fall_delay = 1.0e-10 stop_time=90n)
+
+.model adc adc_bridge ( in_low =0.5 in_high =1.0
++                   rise_delay =1.0e-10 fall_delay =1.0e-10)
+.model dac dac_bridge(out_low = 0.0 out_high = 2.0 out_undef = 1.0
++                      input_load = 5.0e-14 t_rise = 1.0e-10
++                      t_fall = 1.0e-10)
+
+
+.end
+
+
+
+.CONTROL
+
+option noopalter
+tran .1n 100n
+.ENDC
+
diff --git a/Netlist/test5.cir b/Netlist/test5.cir
new file mode 100644
index 0000000..b49754b
--- /dev/null
+++ b/Netlist/test5.cir
@@ -0,0 +1,56 @@
+
+*** input sources ***
+
+*v1 100 0 DC PWL ( 0n 0.0 5n 0.0 5.1n 2.0 10n 2.0 10.1n 2.0 15n 2.0 15.1n 0.0 20.0n 0.0 20.1n 2.0 25n 2.0 25.1n 0.0 30n 0.0 30.1n 2.0
+*		+40.0 2.0 40.1n 0.0 50n 0.0 50.1n 2.0 60n 2.0 60.1n 0.0 70n 0.0 70.1n 2.0 80n 2.0 80.1n 0.0 90n 0.0 100n 0.0)
+
+*v2 200 0 DC PWL (0n 2.0 5n 2.0 10n 2.0 15n 2.0 15.1n 0.0 20n 0.0 25n 0.0 30n 0.0 30.1n 2.0 40n 2.0 40.1n 0.0 45n 0.0 45.1n 2.0 
+*		+ 50n 2.0 50.1n 0.0 60.0n 0.0 70n 0.0 80n 0.0 90n 0.0 95n 0.0 95.1n 2.0 100n 2.0)
+
+vin1 100 0 PULSE (5 0 0 .0000001ns 0.0000001ns 50ns 100ns)
+vin2 200 0 PULSE (5 0 0 .0000001ns 0.0000001ns 10ns 20ns)
+vin3 300 0 PULSE (5 0 0 .0000001ns 0.0000001ns 20ns 40ns)
+vin4 400 0 PULSE (5 0 0 .0000001ns 0.0000001ns 30ns 60ns)
+
+Vvdd vdd 0 DC 2.0
+
+*** resistors to ground ***
+r1 100 0 1k
+r2 200 0 1k
+r3 300 0 1k
+r4 400 0 1k
+
+*
+*** adc_bridge blocks ***
+aconverter1 [100 200 300 400] [1 2 3 4] adc
+
+aor1 [1] [2] [12] or1
+and1 [3] [4] [34] and_gate
+axor [34] [12]  [1234] axors
+ainv [1234] [12345] inv1
+adac1 [12345] [out]  dac
+
+*************model***********
+
+.model axors myxor(instance_id = 112 rise_delay = 1.0e-10 fall_delay = 1.0e-10 stop_time=90n)
+.model and_gate and_nghdl(instance_id = 11 rise_delay = 1.0e-10 fall_delay = 1.0e-10 stop_time=90n)
+.model inv1 inverter(instance_id = 13 rise_delay = 1.0e-10 fall_delay = 1.0e-10 stop_time=80n)
+.model or1 or_nghdl(instance_id = 14 rise_delay = 1.0e-10 fall_delay = 1.0e-10 stop_time=90n)
+
+.model adc adc_bridge ( in_low =0.5 in_high =1.0
++                   rise_delay =1.0e-10 fall_delay =1.0e-10)
+.model dac dac_bridge(out_low = 0.0 out_high = 2.0 out_undef = 1.0
++                      input_load = 5.0e-14 t_rise = 1.0e-10
++                      t_fall = 1.0e-10)
+
+
+.end
+
+
+
+.CONTROL
+
+option noopalter
+tran .1n 100n
+.ENDC
+
diff --git a/Netlist/ua741.txt b/Netlist/ua741.txt
new file mode 100644
index 0000000..1f5d694
--- /dev/null
+++ b/Netlist/ua741.txt
@@ -0,0 +1,44 @@
+* Subcircuit for Lab 8 Prelab
+* UA741 OPERATIONAL AMPLIFIER "MACROMODEL" SUBCIRCUIT
+* CONNECTIONS:   NON-INVERTING INPUT
+*                | INVERTING INPUT
+*                | | POSITIVE POWER SUPPLY
+*                | | | NEGATIVE POWER SUPPLY
+*                | | | | OUTPUT
+*                | | | | |
+.SUBCKT UA741    1 2 3 4 5
+*
+  C1   11 12 4.664E-12
+  C2    6  7 20.00E-12
+  DC    5 53 DX
+  DE   54  5 DX
+  DLP  90 91 DX
+  DLN  92 90 DX
+  DP    4  3 DX
+  EGND 99  0 POLY(2) (3,0) (4,0) 0 .5 .5
+  FB    7 99 POLY(5) VB VC VE VLP VLN 0 10.61E6 -10E6 10E6 10E6 -10E6
+  GA 6  0 11 12 137.7E-6
+  GCM 0  6 10 99 2.574E-9
+  IEE  10  4 DC 10.16E-6
+  HLIM 90  0 VLIM 1K
+  Q1   11  2 13 QX
+  Q2   12  1 14 QX
+  R2    6  9 100.0E3
+  RC1   3 11 7.957E3
+  RC2   3 12 7.957E3
+  RE1  13 10 2.740E3
+  RE2  14 10 2.740E3
+  REE  10 99 19.69E6
+  RO1   8  5 150
+  RO2   7 99 150
+  RP    3  4 18.11E3
+  VB    9  0 DC 0
+  VC 3 53 DC 2.600
+  VE   54  4 DC 2.600
+  VLIM  7  8 DC 0
+  VLP  91  0 DC 25
+  VLN   0 92 DC 25
+.MODEL DX D(IS=800.0E-18)
+.MODEL QX NPN(IS=800.0E-18 BF=62.50)
+.ENDS
+