diff options
Diffstat (limited to 'qa/testcases')
| -rw-r--r-- | qa/testcases/test_000_qa_works.py | 17 | ||||
| -rw-r--r-- | qa/testcases/test_001_pcb_load.py | 48 | ||||
| -rw-r--r-- | qa/testcases/test_002_board_class.py | 132 |
3 files changed, 197 insertions, 0 deletions
diff --git a/qa/testcases/test_000_qa_works.py b/qa/testcases/test_000_qa_works.py new file mode 100644 index 0000000..3757c19 --- /dev/null +++ b/qa/testcases/test_000_qa_works.py @@ -0,0 +1,17 @@ +import unittest + +class TestQAWorks(unittest.TestCase): + + def setUp(self): + self.pcb = None + + def test_assert_true( self ): + self.assertTrue( True ) + + def test_assert_equal( self ): + self.assertEqual(2, 1+1) + + +if __name__ == '__main__': + unittest.main() +
\ No newline at end of file diff --git a/qa/testcases/test_001_pcb_load.py b/qa/testcases/test_001_pcb_load.py new file mode 100644 index 0000000..8e9aea9 --- /dev/null +++ b/qa/testcases/test_001_pcb_load.py @@ -0,0 +1,48 @@ +import code +import unittest +import pcbnew +import pdb + +class TestPCBLoad(unittest.TestCase): + + def setUp(self): + self.pcb = pcbnew.LoadBoard("data/complex_hierarchy.kicad_pcb") + + def test_pcb_load(self): + self.assertNotEqual(self.pcb,None) + + def test_pcb_track_count(self): + tracks = list(self.pcb.GetTracks()) + self.assertEqual(len(tracks),361) + + def test_pcb_modules(self): + modules = list(self.pcb.GetModules()) + self.assertEqual(len(modules), 72) + + def test_pcb_module_references(self): + board_refs = list(module.GetReference() for + module in self.pcb.GetModules()) + + known_refs = [u'P1', u'P3', u'C2', u'C1', u'D1', u'Q3', u'Q5', u'Q7', + u'Q6', u'Q1', u'Q2', u'Q4', u'Q8', u'P2', u'U1', u'U4', + u'P4', u'P5', u'P6', u'U3', u'R9', u'R15', u'RV1', u'RV2', + u'C3', u'C4', u'C5', u'C6', u'C7', u'C8', u'C9', u'D2', + u'D3', u'D4', u'D5', u'D6', u'D7', u'R3', u'R4', u'R5', + u'R6', u'R7', u'R8', u'R10', u'R11', u'R12', u'R13', + u'R14', u'R16', u'R17', u'R18', u'R19', u'R20', u'R21', + u'R22', u'MIRE', u'C10', u'C11', + u'U2', u'C14', u'C12', u'R23', u'R24', u'D9', u'D8', u'R25', + u'R26', u'R27', u'R28'] + + for ref in known_refs: + self.assertTrue(ref in board_refs) + + def test_pcb_netcount(self): + self.assertEqual(self.pcb.GetNetCount(),51) + + #def test_interactive(self): + # code.interact(local=locals()) + +if __name__ == '__main__': + unittest.main() +
\ No newline at end of file diff --git a/qa/testcases/test_002_board_class.py b/qa/testcases/test_002_board_class.py new file mode 100644 index 0000000..70c46d6 --- /dev/null +++ b/qa/testcases/test_002_board_class.py @@ -0,0 +1,132 @@ +import code +import unittest +import os +import pcbnew +import pdb +import tempfile + + +from pcbnew import * + + +BACK_COPPER = 'Back_Copper' +B_CU = 'B.Cu' +NEW_NAME = 'My_Fancy_Layer_Name' + + +class TestBoardClass(unittest.TestCase): + + def setUp(self): + self.pcb = LoadBoard("data/complex_hierarchy.kicad_pcb") + self.TITLE="Test Board" + self.COMMENT1="For load/save test" + self.FILENAME=tempfile.mktemp()+".kicad_pcb" + + def test_pcb_find_module(self): + module = self.pcb.FindModule('P1') + self.assertEqual(module.GetReference(),'P1') + + def test_pcb_get_track_count(self): + pcb = BOARD() + + self.assertEqual(pcb.GetNumSegmTrack(),0) + + track0 = TRACK(pcb) + pcb.Add(track0) + self.assertEqual(pcb.GetNumSegmTrack(),1) + + track1 = TRACK(pcb) + pcb.Add(track1) + self.assertEqual(pcb.GetNumSegmTrack(),2) + + def test_pcb_bounding_box(self): + pcb = BOARD() + track = TRACK(pcb) + pcb.Add(track) + + #track.SetStartEnd(wxPointMM(10.0, 10.0), + # wxPointMM(20.0, 30.0)) + + track.SetStart(wxPointMM(10.0, 10.0)) + track.SetEnd(wxPointMM(20.0, 30.0)) + + track.SetWidth(FromMM(0.5)) + + #!!! THIS FAILS? == 0.0 x 0.0 ?? + #height, width = ToMM(pcb.ComputeBoundingBox().GetSize()) + bounding_box = pcb.ComputeBoundingBox() + height, width = ToMM(bounding_box.GetSize()) + + clearance = ToMM(track.GetClearance()*2) + self.assertAlmostEqual(width, (30-10) + 0.5 + clearance, 2) + self.assertAlmostEqual(height, (20-10) + 0.5 + clearance, 2) + + def test_pcb_get_pad(self): + pcb = BOARD() + module = MODULE(pcb) + pcb.Add(module) + pad = D_PAD(module) + module.Add(pad) + + pad.SetShape(PAD_OVAL) + pad.SetSize(wxSizeMM(2.0, 3.0)) + pad.SetPosition(wxPointMM(0,0)) + + # easy case + p1 = pcb.GetPad(wxPointMM(0,0)) + + # top side + p2 = pcb.GetPad(wxPointMM(0.9,0.0)) + + # bottom side + p3 = pcb.GetPad(wxPointMM(0,1.4)) + + # TODO: get pad == p1 evaluated as true instead + # of relying in the internal C++ object pointer + self.assertEqual(pad.this, p1.this) + self.assertEqual(pad.this, p2.this) + self.assertEqual(pad.this, p3.this) + + def test_pcb_save_and_load(self): + pcb = BOARD() + pcb.GetTitleBlock().SetTitle(self.TITLE) + pcb.GetTitleBlock().SetComment1(self.COMMENT1) + result = SaveBoard(self.FILENAME,pcb) + self.assertTrue(result) + + pcb2 = LoadBoard(self.FILENAME) + self.assertNotEqual(pcb2,None) + + tb = pcb2.GetTitleBlock() + self.assertEqual(tb.GetTitle(),self.TITLE) + self.assertEqual(tb.GetComment1(),self.COMMENT1) + + os.remove(self.FILENAME) + + def test_pcb_layer_name_set_get(self): + pcb = BOARD() + pcb.SetLayerName(31, BACK_COPPER) + self.assertEqual(pcb.GetLayerName(31), BACK_COPPER) + + def test_pcb_layer_name_set_get(self): + pcb = BOARD() + pcb.SetLayerName(31, BACK_COPPER) + self.assertEqual(pcb.GetLayerName(31), BACK_COPPER) + + def test_pcb_layer_id_get(self): + pcb = BOARD() + b_cu_id = pcb.GetLayerID(B_CU) + pcb.SetLayerName(b_cu_id, NEW_NAME) + + # ensure we can get the ID for the new name + self.assertEqual(pcb.GetLayerID(NEW_NAME), b_cu_id) + + # ensure we can get to the ID via the STD name too + self.assertEqual(pcb.GetLayerID(B_CU), b_cu_id) + + #def test_interactive(self): + # code.interact(local=locals()) + +if __name__ == '__main__': + unittest.main() + |