diff options
Diffstat (limited to 'demos/test_pads_inside_pads')
5 files changed, 464 insertions, 0 deletions
diff --git a/demos/test_pads_inside_pads/test_pads_inside_pads-cache.lib b/demos/test_pads_inside_pads/test_pads_inside_pads-cache.lib new file mode 100644 index 0000000..7c107a8 --- /dev/null +++ b/demos/test_pads_inside_pads/test_pads_inside_pads-cache.lib @@ -0,0 +1,18 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# CONN_1 +# +DEF ~CONN_1 P 0 30 N N 1 F N +F0 "P" 80 0 40 H V L CNN +F1 "CONN_1" 0 55 30 H I C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 0 31 0 1 0 N +P 2 0 1 0 -30 0 -50 0 N +X 1 1 -150 0 100 R 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/demos/test_pads_inside_pads/test_pads_inside_pads.kicad_pcb b/demos/test_pads_inside_pads/test_pads_inside_pads.kicad_pcb new file mode 100644 index 0000000..e07d003 --- /dev/null +++ b/demos/test_pads_inside_pads/test_pads_inside_pads.kicad_pcb @@ -0,0 +1,195 @@ +(kicad_pcb (version 4) (host pcbnew "(2015-04-25 BZR 5623)-product") + + (general + (links 12) + (no_connects 0) + (area 79.121 35.179 111.052429 65.3542) + (thickness 1.6002) + (drawings 0) + (tracks 4) + (zones 0) + (modules 4) + (nets 3) + ) + + (page A4) + (layers + (0 Dessus signal) + (31 Dessous signal) + (32 B.Adhes user) + (33 F.Adhes user) + (34 B.Paste user) + (35 F.Paste user) + (36 B.SilkS user) + (37 F.SilkS user) + (38 B.Mask user) + (39 F.Mask user) + (40 Dwgs.User user) + (41 Cmts.User user) + (42 Eco1.User user) + (43 Eco2.User user) + (44 Edge.Cuts user) + ) + + (setup + (last_trace_width 0.2032) + (trace_clearance 0.254) + (zone_clearance 0.508) + (zone_45_only no) + (trace_min 0.2032) + (segment_width 0.381) + (edge_width 0.381) + (via_size 0.889) + (via_drill 0.635) + (via_min_size 0.889) + (via_min_drill 0.508) + (uvia_size 0.508) + (uvia_drill 0.127) + (uvias_allowed no) + (uvia_min_size 0.508) + (uvia_min_drill 0.127) + (pcb_text_width 0.3048) + (pcb_text_size 1.524 2.032) + (mod_edge_width 0.381) + (mod_text_size 1.524 1.524) + (mod_text_width 0.3048) + (pad_size 1.524 1.524) + (pad_drill 0.8128) + (pad_to_mask_clearance 0.254) + (aux_axis_origin 0 0) + (visible_elements 7FFFFFFF) + (pcbplotparams + (layerselection 0x00030_80000001) + (usegerberextensions true) + (excludeedgelayer true) + (linewidth 0.150000) + (plotframeref false) + (viasonmask false) + (mode 1) + (useauxorigin false) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15) + (hpglpenoverlay 0) + (psnegative false) + (psa4output false) + (plotreference true) + (plotvalue true) + (plotinvisibletext false) + (padsonsilk false) + (subtractmaskfromsilk false) + (outputformat 1) + (mirror false) + (drillshape 1) + (scaleselection 1) + (outputdirectory "")) + ) + + (net 0 "") + (net 1 /NET1) + (net 2 /NET2) + + (net_class Default "Ceci est la Netclass par défaut" + (clearance 0.254) + (trace_width 0.2032) + (via_dia 0.889) + (via_drill 0.635) + (uvia_dia 0.508) + (uvia_drill 0.127) + (add_net /NET1) + (add_net /NET2) + ) + + (module 1pin (layer Dessus) (tedit 553E7303) (tstamp 4EE505BA) + (at 89.535 45.593) + (descr "module 1 pin (ou trou mecanique de percage)") + (tags DEV) + (path /4EDF7CC5) + (fp_text reference P1 (at 0 -12) (layer F.SilkS) + (effects (font (size 1.016 1.016) (thickness 0.254))) + ) + (fp_text value CONN_1 (at 0 12) (layer F.SilkS) hide + (effects (font (size 1.016 1.016) (thickness 0.254))) + ) + (fp_line (start -11 -11) (end 11 -11) (layer F.SilkS) (width 0.15)) + (fp_line (start 11 -11) (end 11 11) (layer F.SilkS) (width 0.15)) + (fp_line (start 11 11) (end -11 11) (layer F.SilkS) (width 0.15)) + (fp_line (start -11 11) (end -11 -11) (layer F.SilkS) (width 0.15)) + (pad 1 smd rect (at 0 0) (size 20.32 20.32) (layers Dessus F.Paste F.Mask) + (net 2 /NET2)) + (pad 1 thru_hole circle (at -8.255 -7.62) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask F.SilkS) + (net 2 /NET2)) + (pad 1 thru_hole circle (at -3.81 -7.62) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask F.SilkS) + (net 2 /NET2)) + (pad 1 thru_hole circle (at 0 -7.62) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask F.SilkS) + (net 2 /NET2)) + (pad 1 thru_hole circle (at 3.81 -7.62) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask F.SilkS) + (net 2 /NET2)) + (pad 1 thru_hole circle (at 8.255 -7.62) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask F.SilkS) + (net 2 /NET2)) + (pad 1 thru_hole circle (at 8.255 -4.445) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask F.SilkS) + (net 2 /NET2)) + (pad 1 thru_hole circle (at 3.81 -4.445) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask F.SilkS) + (net 2 /NET2)) + (pad 1 thru_hole circle (at 0 -4.445) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask F.SilkS) + (net 2 /NET2)) + (pad 1 thru_hole circle (at -3.81 -4.445) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask F.SilkS) + (net 2 /NET2)) + (pad 1 thru_hole circle (at -8.255 -4.445) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask F.SilkS) + (net 2 /NET2)) + ) + + (module 1pin (layer Dessus) (tedit 200000) (tstamp 4EE505BC) + (at 107.696 45.593) + (descr "module 1 pin (ou trou mecanique de percage)") + (tags DEV) + (path /4EDF7CC0) + (fp_text reference P2 (at 0 -3.048) (layer F.SilkS) + (effects (font (size 1.016 1.016) (thickness 0.254))) + ) + (fp_text value CONN_1 (at 0 2.794) (layer F.SilkS) hide + (effects (font (size 1.016 1.016) (thickness 0.254))) + ) + (fp_circle (center 0 0) (end 0 -2.286) (layer F.SilkS) (width 0.381)) + (pad 1 thru_hole circle (at 0 0) (size 4.064 4.064) (drill 3.048) (layers *.Cu *.Mask F.SilkS) + (net 2 /NET2)) + ) + + (module 1pin (layer Dessus) (tedit 200000) (tstamp 4EE505BE) + (at 87.122 61.468) + (descr "module 1 pin (ou trou mecanique de percage)") + (tags DEV) + (path /4EE5056C) + (fp_text reference P3 (at 0 -3.048) (layer F.SilkS) + (effects (font (size 1.016 1.016) (thickness 0.254))) + ) + (fp_text value CONN_1 (at 0 2.794) (layer F.SilkS) hide + (effects (font (size 1.016 1.016) (thickness 0.254))) + ) + (fp_circle (center 0 0) (end 0 -2.286) (layer F.SilkS) (width 0.381)) + (pad 1 thru_hole circle (at 0 0) (size 4.064 4.064) (drill 3.048) (layers *.Cu *.Mask F.SilkS) + (net 1 /NET1)) + ) + + (module 1pin (layer Dessus) (tedit 4EE8A1D1) (tstamp 4EE505C0) + (at 107.061 61.468) + (descr "module 1 pin (ou trou mecanique de percage)") + (tags DEV) + (path /4EE5056D) + (fp_text reference P4 (at 0 -3.048) (layer F.SilkS) + (effects (font (size 1.016 1.016) (thickness 0.254))) + ) + (fp_text value CONN_1 (at 0 2.794) (layer F.SilkS) hide + (effects (font (size 1.016 1.016) (thickness 0.254))) + ) + (fp_circle (center 0 0) (end 0 -2.286) (layer F.SilkS) (width 0.381)) + (pad 1 thru_hole circle (at 0 0) (size 4.064 4.064) (drill 3.048) (layers *.Cu *.Mask F.SilkS) + (net 1 /NET1) (die_length 7.62)) + ) + + (segment (start 107.061 61.468) (end 87.122 61.468) (width 0.2032) (layer Dessous) (net 1)) + (segment (start 103.759 41.148) (end 107.696 45.085) (width 0.2032) (layer Dessous) (net 2)) + (segment (start 107.696 45.085) (end 107.696 45.593) (width 0.2032) (layer Dessous) (net 2)) + (segment (start 97.79 41.148) (end 103.759 41.148) (width 0.2032) (layer Dessous) (net 2)) + +) diff --git a/demos/test_pads_inside_pads/test_pads_inside_pads.net b/demos/test_pads_inside_pads/test_pads_inside_pads.net new file mode 100644 index 0000000..25e493a --- /dev/null +++ b/demos/test_pads_inside_pads/test_pads_inside_pads.net @@ -0,0 +1,44 @@ +(export (version D) + (design + (source F:/kicad-launchpad/testing/demos/test_pads_inside_pads/test_pads_inside_pads.sch) + (date "09/01/2014 15:29:02") + (tool "eeschema (2014-01-08 BZR 4616)-product")) + (components + (comp (ref P4) + (value CONN_1) + (libsource (lib conn) (part CONN_1)) + (sheetpath (names /) (tstamps /)) + (tstamp 4EE5056D)) + (comp (ref P3) + (value CONN_1) + (libsource (lib conn) (part CONN_1)) + (sheetpath (names /) (tstamps /)) + (tstamp 4EE5056C)) + (comp (ref P1) + (value CONN_1) + (libsource (lib conn) (part CONN_1)) + (sheetpath (names /) (tstamps /)) + (tstamp 4EDF7CC5)) + (comp (ref P2) + (value CONN_1) + (libsource (lib conn) (part CONN_1)) + (sheetpath (names /) (tstamps /)) + (tstamp 4EDF7CC0))) + (libparts + (libpart (lib conn) (part CONN_1) + (description "1 pin") + (fields + (field (name Reference) P) + (field (name Value) CONN_1)) + (pins + (pin (num 1) (name 1) (type passive))))) + (libraries + (library (logical conn) + (uri F:\kicad\share\library\conn.lib))) + (nets + (net (code 1) (name /NET1) + (node (ref P4) (pin 1)) + (node (ref P3) (pin 1))) + (net (code 2) (name /NET2) + (node (ref P1) (pin 1)) + (node (ref P2) (pin 1)))))
\ No newline at end of file diff --git a/demos/test_pads_inside_pads/test_pads_inside_pads.pro b/demos/test_pads_inside_pads/test_pads_inside_pads.pro new file mode 100644 index 0000000..96ac357 --- /dev/null +++ b/demos/test_pads_inside_pads/test_pads_inside_pads.pro @@ -0,0 +1,108 @@ +update=13/12/2011 11:04:14 +version=1 +last_client=pcbnew +[cvpcb] +version=1 +NetITyp=0 +NetIExt=.net +PkgIExt=.pkg +NetDir= +LibDir= +NetType=0 +[cvpcb/libraries] +EquName1=devcms +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +SimCmd= +UseNetN=0 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +[general] +version=1 +[pcbnew] +version=1 +PadDrlX=320 +PadDimH=600 +PadDimV=600 +BoardThickness=630 +TxtPcbV=800 +TxtPcbH=600 +TxtModV=600 +TxtModH=600 +TxtModW=120 +VEgarde=100 +DrawLar=150 +EdgeLar=150 +TxtLar=120 +MSegLar=150 +LastNetListRead= +[pcbnew/libraries] +LibDir= +LibName1=sockets +LibName2=connect +LibName3=discret +LibName4=pin_array +LibName5=divers +LibName6=libcms +LibName7=display +LibName8=valves +LibName9=led +LibName10=dip_sockets diff --git a/demos/test_pads_inside_pads/test_pads_inside_pads.sch b/demos/test_pads_inside_pads/test_pads_inside_pads.sch new file mode 100644 index 0000000..f193dc4 --- /dev/null +++ b/demos/test_pads_inside_pads/test_pads_inside_pads.sch @@ -0,0 +1,99 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:test_pads_inside_pads-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "19 dec 2011" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 4150 1750 3750 1750 +Wire Wire Line + 4150 1450 3750 1450 +Text Label 3850 1450 0 60 ~ 0 +NET1 +$Comp +L CONN_1 P4 +U 1 1 4EE5056D +P 4300 1450 +F 0 "P4" H 4380 1450 40 0000 L CNN +F 1 "CONN_1" H 4300 1505 30 0001 C CNN +F 2 "Connect:1pin" H 4300 1400 60 0000 C CNN +F 3 "" H 4300 1450 60 0001 C CNN + 1 4300 1450 + 1 0 0 -1 +$EndComp +$Comp +L CONN_1 P3 +U 1 1 4EE5056C +P 3600 1450 +F 0 "P3" H 3680 1450 40 0000 L CNN +F 1 "CONN_1" H 3600 1505 30 0001 C CNN +F 2 "Connect:1pin" H 3600 1500 60 0000 C CNN +F 3 "" H 3600 1450 60 0001 C CNN + 1 3600 1450 + -1 0 0 1 +$EndComp +$Comp +L CONN_1 P1 +U 1 1 4EDF7CC5 +P 3600 1750 +F 0 "P1" H 3680 1750 40 0000 L CNN +F 1 "CONN_1" H 3600 1805 30 0001 C CNN +F 2 "Connect:1pin" H 3600 1800 60 0000 C CNN +F 3 "" H 3600 1750 60 0001 C CNN + 1 3600 1750 + -1 0 0 1 +$EndComp +$Comp +L CONN_1 P2 +U 1 1 4EDF7CC0 +P 4300 1750 +F 0 "P2" H 4380 1750 40 0000 L CNN +F 1 "CONN_1" H 4300 1805 30 0001 C CNN +F 2 "Connect:1pin" H 4300 1700 60 0000 C CNN +F 3 "" H 4300 1750 60 0001 C CNN + 1 4300 1750 + 1 0 0 -1 +$EndComp +Text Label 3850 1750 0 60 ~ 0 +NET2 +$EndSCHEMATC |