index
:
FreeEDA/.git
master
Tool for circuit design, simulation, analysis and PCB design (previously known as Oscad)
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
OSCAD
/
report
/
presentation
Mode
Name
Size
-rw-r--r--
Makefile
1027
log
plain
-rw-r--r--
OSCAD.tex
4964
log
plain
-rw-r--r--
runlatex
39
log
plain