| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | analysis | 26 | logplain |
| -rw-r--r-- | simpleTTL-cache.bak | 3283 | logplain |
| -rw-r--r-- | simpleTTL-cache.lib | 3279 | logplain |
| -rw-r--r-- | simpleTTL.bak | 2945 | logplain |
| -rw-r--r-- | simpleTTL.cir | 414 | logplain |
| -rw-r--r-- | simpleTTL.cir.ckt | 496 | logplain |
| -rw-r--r-- | simpleTTL.cir.out | 537 | logplain |
| -rw-r--r-- | simpleTTL.pro | 1159 | logplain |
| -rw-r--r-- | simpleTTL.proj | 28 | logplain |
| -rw-r--r-- | simpleTTL.sch | 2776 | logplain |
 |
index : FreeEDA/.git | |
| Tool for circuit design, simulation, analysis and PCB design (previously known as Oscad) |
| summaryrefslogtreecommitdiff |