| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | analysis | 27 | logplain |
| -rw-r--r-- | example_8.4-cache.lib | 2003 | logplain |
| -rw-r--r-- | example_8.4.cir | 911 | logplain |
| -rw-r--r-- | example_8.4.cir.ckt | 909 | logplain |
| -rw-r--r-- | example_8.4.cir.out | 941 | logplain |
| -rw-r--r-- | example_8.4.pro | 1409 | logplain |
| -rw-r--r-- | example_8.4.proj | 30 | logplain |
| -rw-r--r-- | example_8.4.sch | 10456 | logplain |
 |
index : FreeEDA/.git | |
| Tool for circuit design, simulation, analysis and PCB design (previously known as Oscad) |
| summaryrefslogtreecommitdiff |