| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | analysis | 26 | logplain |
| -rw-r--r-- | example_3.8-cache.lib | 2003 | logplain |
| -rw-r--r-- | example_3.8.cir | 451 | logplain |
| -rw-r--r-- | example_3.8.cir.ckt | 286 | logplain |
| -rw-r--r-- | example_3.8.cir.out | 325 | logplain |
| -rw-r--r-- | example_3.8.pro | 1409 | logplain |
| -rw-r--r-- | example_3.8.proj | 30 | logplain |
| -rw-r--r-- | example_3.8.sch | 3189 | logplain |
 |
index : FreeEDA/.git | |
| Tool for circuit design, simulation, analysis and PCB design (previously known as Oscad) |
| summaryrefslogtreecommitdiff |