| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | analysis | 26 | logplain |
| -rw-r--r-- | example_3.20-cache.bak | 2019 | logplain |
| -rw-r--r-- | example_3.20-cache.lib | 2019 | logplain |
| -rw-r--r-- | example_3.20.bak | 3356 | logplain |
| -rw-r--r-- | example_3.20.cir | 437 | logplain |
| -rw-r--r-- | example_3.20.cir.ckt | 302 | logplain |
| -rw-r--r-- | example_3.20.cir.out | 340 | logplain |
| -rw-r--r-- | example_3.20.pro | 1410 | logplain |
| -rw-r--r-- | example_3.20.proj | 31 | logplain |
| -rw-r--r-- | example_3.20.sch | 3261 | logplain |
| -rw-r--r-- | npn.lib | 255 | logplain |
 |
index : FreeEDA/.git | |
| Tool for circuit design, simulation, analysis and PCB design (previously known as Oscad) |
| summaryrefslogtreecommitdiff |