| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | analysis | 27 | logplain |
| -rw-r--r-- | example_3.11-cache.lib | 2407 | logplain |
| -rw-r--r-- | example_3.11.cir | 576 | logplain |
| -rw-r--r-- | example_3.11.cir.ckt | 452 | logplain |
| -rw-r--r-- | example_3.11.cir.out | 488 | logplain |
| -rw-r--r-- | example_3.11.pro | 1409 | logplain |
| -rw-r--r-- | example_3.11.proj | 31 | logplain |
| -rw-r--r-- | example_3.11.sch | 5303 | logplain |
 |
index : FreeEDA/.git | |
| Tool for circuit design, simulation, analysis and PCB design (previously known as Oscad) |
| summaryrefslogtreecommitdiff |