| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | analysis | 27 | logplain |
| -rw-r--r-- | example_3.10-cache.lib | 2003 | logplain |
| -rw-r--r-- | example_3.10.cir | 474 | logplain |
| -rw-r--r-- | example_3.10.cir.ckt | 311 | logplain |
| -rw-r--r-- | example_3.10.cir.out | 350 | logplain |
| -rw-r--r-- | example_3.10.pro | 1409 | logplain |
| -rw-r--r-- | example_3.10.proj | 31 | logplain |
| -rw-r--r-- | example_3.10.sch | 3702 | logplain |
 |
index : FreeEDA/.git | |
| Tool for circuit design, simulation, analysis and PCB design (previously known as Oscad) |
| summaryrefslogtreecommitdiff |