| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | 1n4007.lib | 143 | logplain |
| -rw-r--r-- | analysis | 25 | logplain |
| -rw-r--r-- | example_2.1-cache.bak | 1790 | logplain |
| -rw-r--r-- | example_2.1-cache.lib | 1790 | logplain |
| -rw-r--r-- | example_2.1.bak | 2303 | logplain |
| -rw-r--r-- | example_2.1.brd | 3326 | logplain |
| -rw-r--r-- | example_2.1.cir | 402 | logplain |
| -rw-r--r-- | example_2.1.cir.ckt | 221 | logplain |
| -rw-r--r-- | example_2.1.cir.out | 262 | logplain |
| -rw-r--r-- | example_2.1.cmp | 551 | logplain |
| -rw-r--r-- | example_2.1.net | 599 | logplain |
| -rw-r--r-- | example_2.1.pro | 1481 | logplain |
| -rw-r--r-- | example_2.1.proj | 30 | logplain |
| -rw-r--r-- | example_2.1.sch | 2303 | logplain |
 |
index : FreeEDA/.git | |
| Tool for circuit design, simulation, analysis and PCB design (previously known as Oscad) |
| summaryrefslogtreecommitdiff |