| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | analysis | 3 | logplain |
| -rw-r--r-- | linear1-cache.bak | 1785 | logplain |
| -rw-r--r-- | linear1-cache.lib | 1785 | logplain |
| -rw-r--r-- | linear1.bak | 4116 | logplain |
| -rw-r--r-- | linear1.brd | 1721 | logplain |
| -rw-r--r-- | linear1.cir | 481 | logplain |
| -rw-r--r-- | linear1.cir.ckt | 264 | logplain |
| -rw-r--r-- | linear1.cir.ckt.sol | 600 | logplain |
| -rw-r--r-- | linear1.cir.out | 305 | logplain |
| -rw-r--r-- | linear1.cmp | 995 | logplain |
| -rw-r--r-- | linear1.net | 1138 | logplain |
| -rw-r--r-- | linear1.pro | 1110 | logplain |
| -rw-r--r-- | linear1.proj | 26 | logplain |
| -rw-r--r-- | linear1.sch | 4139 | logplain |
 |
index : FreeEDA/.git | |
| Tool for circuit design, simulation, analysis and PCB design (previously known as Oscad) |
| summaryrefslogtreecommitdiff |