| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | RC_ac-cache.bak | 1733 | logplain |
| -rw-r--r-- | RC_ac-cache.lib | 1733 | logplain |
| -rw-r--r-- | RC_ac.bak | 2345 | logplain |
| -rw-r--r-- | RC_ac.cir | 384 | logplain |
| -rw-r--r-- | RC_ac.cir.ckt | 213 | logplain |
| -rw-r--r-- | RC_ac.cir.out | 259 | logplain |
| -rw-r--r-- | RC_ac.pro | 1407 | logplain |
| -rw-r--r-- | RC_ac.proj | 24 | logplain |
| -rw-r--r-- | RC_ac.sch | 2347 | logplain |
| -rw-r--r-- | analysis | 22 | logplain |
 |
index : FreeEDA/.git | |
| Tool for circuit design, simulation, analysis and PCB design (previously known as Oscad) |
| summaryrefslogtreecommitdiff |