| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | RC-cache.bak | 1737 | logplain |
| -rw-r--r-- | RC-cache.lib | 1737 | logplain |
| -rw-r--r-- | RC.bak | 2344 | logplain |
| -rw-r--r-- | RC.cir | 386 | logplain |
| -rw-r--r-- | RC.cir.ckt | 231 | logplain |
| -rw-r--r-- | RC.cir.out | 277 | logplain |
| -rw-r--r-- | RC.pro | 1407 | logplain |
| -rw-r--r-- | RC.proj | 21 | logplain |
| -rw-r--r-- | RC.sch | 2367 | logplain |
| -rw-r--r-- | analysis | 27 | logplain |
 |
index : FreeEDA/.git | |
| Tool for circuit design, simulation, analysis and PCB design (previously known as Oscad) |
| summaryrefslogtreecommitdiff |