diff options
Diffstat (limited to 'OSCAD/Examples/sedra_smith/chapter_3/example_3.13')
9 files changed, 660 insertions, 0 deletions
diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/analysis b/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/analysis new file mode 100644 index 0000000..11459c7 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/analysis @@ -0,0 +1 @@ +.dc v1 0e-00 12e-00 12e-03 diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13-cache.lib b/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13-cache.lib new file mode 100644 index 0000000..efa56af --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13-cache.lib @@ -0,0 +1,109 @@ +EESchema-LIBRARY Version 2.3 Date: Tuesday 16 April 2013 11:31:21 AM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# NPN +# +DEF NPN Q 0 0 Y Y 1 F N +F0 "Q" 0 -150 50 H V R CNN +F1 "NPN" 0 150 50 H V R CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 0 0 100 100 N +P 3 0 1 10 0 75 0 -75 0 -75 N +P 3 0 1 0 50 -50 0 0 0 0 N +P 3 0 1 0 90 -90 100 -100 100 -100 N +P 5 0 1 0 90 -90 70 -30 30 -70 90 -90 90 -90 F +X E 1 100 -200 100 U 40 40 1 1 P +X B 2 -200 0 200 R 40 40 1 1 I +X C 3 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.bak b/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.bak new file mode 100644 index 0000000..db1ff38 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.bak @@ -0,0 +1,210 @@ +EESchema Schematic File Version 2 date Tuesday 16 April 2013 11:16:49 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_3.10-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "15 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 5050 3350 4200 3350 +Wire Wire Line + 6850 2850 6850 1300 +Wire Wire Line + 6850 1300 4200 1300 +Wire Wire Line + 4200 1300 4200 2200 +Connection ~ 4200 3350 +Wire Wire Line + 4200 2700 4200 3800 +Wire Wire Line + 6850 3750 6850 5150 +Wire Wire Line + 5350 3550 5350 3750 +Wire Wire Line + 5350 2050 5350 2250 +Wire Wire Line + 5350 1550 5350 1300 +Wire Wire Line + 5350 2750 5350 3150 +Wire Wire Line + 5350 4250 5350 4400 +Wire Wire Line + 4200 4300 4200 5150 +Wire Wire Line + 4200 5150 6850 5150 +Connection ~ 5350 5150 +Connection ~ 5350 1300 +Wire Wire Line + 5350 5650 5350 4900 +Connection ~ 5350 5500 +Connection ~ 5350 3650 +Connection ~ 5350 2900 +Connection ~ 5000 3350 +$Comp +L VPLOT8_1 U2 +U 3 1 516C2B0C +P 5650 3650 +F 0 "U2" H 5500 3750 50 0000 C CNN +F 1 "VPLOT8_1" H 5800 3750 50 0000 C CNN + 3 5650 3650 + 0 1 1 0 +$EndComp +$Comp +L VPLOT8_1 U2 +U 2 1 516C2B05 +P 5650 2900 +F 0 "U2" H 5500 3000 50 0000 C CNN +F 1 "VPLOT8_1" H 5800 3000 50 0000 C CNN + 2 5650 2900 + 0 1 1 0 +$EndComp +$Comp +L VPLOT8_1 U2 +U 1 1 516C2AFE +P 5000 3050 +F 0 "U2" H 4850 3150 50 0000 C CNN +F 1 "VPLOT8_1" H 5150 3150 50 0000 C CNN + 1 5000 3050 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 516C2AB7 +P 5350 5500 +F 0 "#FLG01" H 5350 5770 30 0001 C CNN +F 1 "PWR_FLAG" H 5350 5730 30 0000 C CNN + 1 5350 5500 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 516C2AAB +P 5350 5650 +F 0 "#PWR02" H 5350 5650 30 0001 C CNN +F 1 "GND" H 5350 5580 30 0001 C CNN + 1 5350 5650 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 516C2A3E +P 4200 4050 +F 0 "R2" V 4280 4050 50 0000 C CNN +F 1 "50000" V 4200 4050 50 0000 C CNN + 1 4200 4050 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516C2A13 +P 4200 2450 +F 0 "R1" V 4280 2450 50 0000 C CNN +F 1 "100000" V 4200 2450 50 0000 C CNN + 1 4200 2450 + 1 0 0 -1 +$EndComp +$Comp +L R R4 +U 1 1 516C29D9 +P 5350 4650 +F 0 "R4" V 5430 4650 50 0000 C CNN +F 1 "3000" V 5350 4650 50 0000 C CNN + 1 5350 4650 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U4 +U 1 1 516C29CD +P 5350 4000 +F 0 "U4" H 5200 4100 50 0000 C CNN +F 1 "IPLOT" H 5500 4100 50 0000 C CNN + 1 5350 4000 + 0 1 1 0 +$EndComp +$Comp +L DC v1 +U 1 1 516C296E +P 6850 3300 +F 0 "v1" H 6650 3400 60 0000 C CNN +F 1 "15V" H 6650 3250 60 0000 C CNN +F 2 "R1" H 6550 3300 60 0000 C CNN + 1 6850 3300 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U3 +U 1 1 516C2958 +P 5350 2500 +F 0 "U3" H 5200 2600 50 0000 C CNN +F 1 "IPLOT" H 5500 2600 50 0000 C CNN + 1 5350 2500 + 0 1 1 0 +$EndComp +$Comp +L R R3 +U 1 1 516C293A +P 5350 1800 +F 0 "R3" V 5430 1800 50 0000 C CNN +F 1 "5000" V 5350 1800 50 0000 C CNN + 1 5350 1800 + 1 0 0 -1 +$EndComp +$Comp +L NPN Q1 +U 1 1 516C2934 +P 5250 3350 +F 0 "Q1" H 5250 3200 50 0000 R CNN +F 1 "NPN" H 5250 3500 50 0000 R CNN + 1 5250 3350 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.cir b/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.cir new file mode 100644 index 0000000..2015439 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.cir @@ -0,0 +1,17 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Tuesday 16 April 2013 11:31:17 AM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +R1 5 7 80000 +U2 7 2 1 VPLOT8_1 +R2 7 0 40000 +R4 4 0 3300 +U4 1 4 IPLOT +v1 5 0 12V +U3 6 2 IPLOT +R3 5 6 4000 +Q1 1 7 2 NPN + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.cir.ckt new file mode 100644 index 0000000..cc4fac4 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.cir.ckt @@ -0,0 +1,17 @@ +* eeschema netlist version 1.1 (spice format) creation date: tuesday 16 april 2013 11:31:17 am ist + +r1 5 7 80000 +* Plotting option vplot8_1 +r2 7 0 40000 +r4 4 0 3300 +V_u4 1 4 0 +v1 5 0 12v +V_u3 6 2 0 +r3 5 6 4000 +q1 2 7 1 npn + +.dc v1 0e-00 12e-00 12e-03 +.plot v(7) v(2) v(1) +.plot i(V_u4) +.plot i(V_u3) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.cir.out b/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.cir.out new file mode 100644 index 0000000..d5ce68a --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.cir.out @@ -0,0 +1,22 @@ +* eeschema netlist version 1.1 (spice format) creation date: tuesday 16 april 2013 11:31:17 am ist + +r1 5 7 80000 +* Plotting option vplot8_1 +r2 7 0 40000 +r4 4 0 3300 +V_u4 1 4 0 +v1 5 0 12v +V_u3 6 2 0 +r3 5 6 4000 +q1 2 7 1 npn + +.dc v1 0e-00 12e-00 12e-03 + +* Control Statements +.control +run +plot v(7) v(2) v(1) +plot i(V_u4) +plot i(V_u3) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.pro b/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.pro new file mode 100644 index 0000000..9ed7c71 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.pro @@ -0,0 +1,74 @@ +update=Tuesday 16 April 2013 11:12:52 AM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/holy/OSCAD/library/analogSpice +LibName32=/home/holy/OSCAD/library/analogXSpice +LibName33=/home/holy/OSCAD/library/convergenceAidSpice +LibName34=/home/holy/OSCAD/library/converterSpice +LibName35=/home/holy/OSCAD/library/digitalSpice +LibName36=/home/holy/OSCAD/library/digitalXSpice +LibName37=/home/holy/OSCAD/library/linearSpice +LibName38=/home/holy/OSCAD/library/measurementSpice +LibName39=/home/holy/OSCAD/library/portSpice +LibName40=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.proj b/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.proj new file mode 100644 index 0000000..a04af44 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.proj @@ -0,0 +1 @@ +schematicFile example_3.13.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.sch b/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.sch new file mode 100644 index 0000000..d0ef771 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_3/example_3.13/example_3.13.sch @@ -0,0 +1,209 @@ +EESchema Schematic File Version 2 date Tuesday 16 April 2013 11:31:21 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "16 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L R R1 +U 1 1 516CE8DE +P 4200 2450 +F 0 "R1" V 4280 2450 50 0000 C CNN +F 1 "80000" V 4200 2450 50 0000 C CNN + 1 4200 2450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5050 3350 4200 3350 +Wire Wire Line + 6850 2850 6850 1300 +Wire Wire Line + 6850 1300 4200 1300 +Wire Wire Line + 4200 1300 4200 2200 +Connection ~ 4200 3350 +Wire Wire Line + 4200 2700 4200 3800 +Wire Wire Line + 6850 3750 6850 5150 +Wire Wire Line + 5350 3550 5350 3750 +Wire Wire Line + 5350 2050 5350 2250 +Wire Wire Line + 5350 1550 5350 1300 +Wire Wire Line + 5350 2750 5350 3150 +Wire Wire Line + 5350 4250 5350 4400 +Wire Wire Line + 4200 4300 4200 5150 +Wire Wire Line + 4200 5150 6850 5150 +Connection ~ 5350 5150 +Connection ~ 5350 1300 +Wire Wire Line + 5350 5650 5350 4900 +Connection ~ 5350 5500 +Connection ~ 5350 3650 +Connection ~ 5350 2900 +Connection ~ 5000 3350 +$Comp +L VPLOT8_1 U2 +U 3 1 516C2B0C +P 5650 3650 +F 0 "U2" H 5500 3750 50 0000 C CNN +F 1 "VPLOT8_1" H 5800 3750 50 0000 C CNN + 3 5650 3650 + 0 1 1 0 +$EndComp +$Comp +L VPLOT8_1 U2 +U 2 1 516C2B05 +P 5650 2900 +F 0 "U2" H 5500 3000 50 0000 C CNN +F 1 "VPLOT8_1" H 5800 3000 50 0000 C CNN + 2 5650 2900 + 0 1 1 0 +$EndComp +$Comp +L VPLOT8_1 U2 +U 1 1 516C2AFE +P 5000 3050 +F 0 "U2" H 4850 3150 50 0000 C CNN +F 1 "VPLOT8_1" H 5150 3150 50 0000 C CNN + 1 5000 3050 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 516C2AB7 +P 5350 5500 +F 0 "#FLG01" H 5350 5770 30 0001 C CNN +F 1 "PWR_FLAG" H 5350 5730 30 0000 C CNN + 1 5350 5500 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 516C2AAB +P 5350 5650 +F 0 "#PWR02" H 5350 5650 30 0001 C CNN +F 1 "GND" H 5350 5580 30 0001 C CNN + 1 5350 5650 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 516C2A3E +P 4200 4050 +F 0 "R2" V 4280 4050 50 0000 C CNN +F 1 "40000" V 4200 4050 50 0000 C CNN + 1 4200 4050 + 1 0 0 -1 +$EndComp +$Comp +L R R4 +U 1 1 516C29D9 +P 5350 4650 +F 0 "R4" V 5430 4650 50 0000 C CNN +F 1 "3300" V 5350 4650 50 0000 C CNN + 1 5350 4650 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U4 +U 1 1 516C29CD +P 5350 4000 +F 0 "U4" H 5200 4100 50 0000 C CNN +F 1 "IPLOT" H 5500 4100 50 0000 C CNN + 1 5350 4000 + 0 1 1 0 +$EndComp +$Comp +L DC v1 +U 1 1 516C296E +P 6850 3300 +F 0 "v1" H 6650 3400 60 0000 C CNN +F 1 "12V" H 6650 3250 60 0000 C CNN +F 2 "R1" H 6550 3300 60 0000 C CNN + 1 6850 3300 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U3 +U 1 1 516C2958 +P 5350 2500 +F 0 "U3" H 5200 2600 50 0000 C CNN +F 1 "IPLOT" H 5500 2600 50 0000 C CNN + 1 5350 2500 + 0 1 1 0 +$EndComp +$Comp +L R R3 +U 1 1 516C293A +P 5350 1800 +F 0 "R3" V 5430 1800 50 0000 C CNN +F 1 "4000" V 5350 1800 50 0000 C CNN + 1 5350 1800 + 1 0 0 -1 +$EndComp +$Comp +L NPN Q1 +U 1 1 516C2934 +P 5250 3350 +F 0 "Q1" H 5250 3200 50 0000 R CNN +F 1 "NPN" H 5250 3500 50 0000 R CNN + 1 5250 3350 + 1 0 0 -1 +$EndComp +$EndSCHEMATC |