diff options
Diffstat (limited to 'OSCAD/Examples/sedra_smith/chapter_2/example_2.5')
11 files changed, 688 insertions, 0 deletions
diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/analysis b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/analysis new file mode 100644 index 0000000..0a70a74 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/analysis @@ -0,0 +1 @@ +.dc v1 0e-00 5e-00 1e-00 diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/diode.lib b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/diode.lib new file mode 100644 index 0000000..d5c42a7 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/diode.lib @@ -0,0 +1,4 @@ +.model diode D( Is=880.5E-18 Nbvl=14.976 Cjo=175p Rs=20 Isr=1.859n ++ Eg=1.11 M=.5516 Nbv=1.6989 N=1 Tbv1=-21.277u ++ Bv=8.1 Fc=.5 Ikf=0 Xti=3 Nr=2 ++ Vj=.65 Ibv=20.245m Ibvl=1.9556m )
\ No newline at end of file diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5-cache.bak b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5-cache.bak new file mode 100644 index 0000000..4dd86fe --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5-cache.bak @@ -0,0 +1,108 @@ +EESchema-LIBRARY Version 2.3 Date: Tuesday 14 May 2013 02:41:15 PM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# DIODE +# +DEF DIODE D 0 40 N N 1 F N +F0 "D" 0 100 40 H V C CNN +F1 "DIODE" 0 -100 40 H V C CNN +$FPLIST + D? + S* +$ENDFPLIST +DRAW +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -200 0 150 R 40 40 1 1 P +X K 2 200 0 150 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5-cache.lib b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5-cache.lib new file mode 100644 index 0000000..9adc092 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5-cache.lib @@ -0,0 +1,108 @@ +EESchema-LIBRARY Version 2.3 Date: Tuesday 21 May 2013 11:07:18 AM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# DIODE +# +DEF DIODE D 0 40 N N 1 F N +F0 "D" 0 100 40 H V C CNN +F1 "DIODE" 0 -100 40 H V C CNN +$FPLIST + D? + S* +$ENDFPLIST +DRAW +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -200 0 150 R 40 40 1 1 P +X K 2 200 0 150 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.bak b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.bak new file mode 100644 index 0000000..21d43d7 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.bak @@ -0,0 +1,164 @@ +EESchema Schematic File Version 2 date Tuesday 14 May 2013 02:41:15 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_2.5-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "14 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L DC v1 +U 1 1 5191FF90 +P 5000 3850 +F 0 "v1" H 4800 3950 60 0000 C CNN +F 1 "DC" H 4800 3800 60 0000 C CNN +F 2 "R1" H 4700 3850 60 0000 C CNN + 1 5000 3850 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 5190978A +P 6250 5300 +F 0 "#FLG01" H 6250 5570 30 0001 C CNN +F 1 "PWR_FLAG" H 6250 5530 30 0000 C CNN + 1 6250 5300 + 1 0 0 -1 +$EndComp +Connection ~ 6600 2100 +$Comp +L VPLOT8_1 U1 +U 1 1 51909775 +P 6600 1800 +F 0 "U1" H 6450 1900 50 0000 C CNN +F 1 "VPLOT8_1" H 6750 1900 50 0000 C CNN + 1 6600 1800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6250 5300 5000 5300 +Wire Wire Line + 6250 3300 6250 3350 +Wire Wire Line + 6250 4850 6250 5500 +Wire Wire Line + 6250 2350 6250 2100 +Connection ~ 6250 5300 +Connection ~ 6250 2100 +Wire Wire Line + 5250 2100 5000 2100 +Wire Wire Line + 5750 2100 6600 2100 +Connection ~ 6250 5300 +Wire Wire Line + 6250 2750 6250 2800 +Wire Wire Line + 5000 2100 5000 3400 +Wire Wire Line + 6250 4250 6250 4350 +Wire Wire Line + 5000 5300 5000 4300 +$Comp +L IPLOT U2 +U 1 1 519096FE +P 6250 4600 +F 0 "U2" H 6100 4700 50 0000 C CNN +F 1 "IPLOT" H 6400 4700 50 0000 C CNN + 1 6250 4600 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 519096A6 +P 6250 3050 +F 0 "R2" V 6330 3050 50 0000 C CNN +F 1 "20m" V 6250 3050 50 0000 C CNN + 1 6250 3050 + 1 0 0 -1 +$EndComp +$Comp +L DC v2 +U 1 1 5190969F +P 6250 3800 +F 0 "v2" H 6050 3900 60 0000 C CNN +F 1 "65m" H 6050 3750 60 0000 C CNN +F 2 "R1" H 5950 3800 60 0000 C CNN + 1 6250 3800 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516A928C +P 5500 2100 +F 0 "R1" V 5580 2100 50 0000 C CNN +F 1 "1000" V 5500 2100 50 0000 C CNN + 1 5500 2100 + 0 -1 -1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 5166AFB9 +P 6250 5500 +F 0 "#PWR02" H 6250 5500 30 0001 C CNN +F 1 "GND" H 6250 5430 30 0001 C CNN + 1 6250 5500 + 1 0 0 -1 +$EndComp +$Comp +L DIODE D1 +U 1 1 5166AF28 +P 6250 2550 +F 0 "D1" H 6250 2650 40 0000 C CNN +F 1 "DIODE" H 6250 2450 40 0000 C CNN + 1 6250 2550 + 0 1 1 0 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.cir b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.cir new file mode 100644 index 0000000..ab9de69 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.cir @@ -0,0 +1,15 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Tuesday 14 May 2013 02:41:09 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +v1 1 0 DC +U1 5 VPLOT8_1 +U2 4 0 IPLOT +R2 3 2 20m +v2 2 4 65m +R1 1 5 1000 +D1 5 3 DIODE + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.cir.ckt new file mode 100644 index 0000000..eb19daf --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.cir.ckt @@ -0,0 +1,15 @@ +* eeschema netlist version 1.1 (spice format) creation date: tuesday 14 may 2013 02:41:09 pm ist +.include diode.lib + +v1 1 0 dc 5 +* Plotting option vplot8_1 +V_u2 4 0 0 +r2 3 2 20m +v2 2 4 65m +r1 1 5 1000 +d1 5 3 diode + +.dc v1 0e-00 5e-00 1e-00 +.plot v(5) +.plot i(V_u2) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.cir.out b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.cir.out new file mode 100644 index 0000000..a3bbe2c --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.cir.out @@ -0,0 +1,20 @@ +* eeschema netlist version 1.1 (spice format) creation date: tuesday 14 may 2013 02:41:09 pm ist +.include diode.lib + +v1 1 0 dc 5 +* Plotting option vplot8_1 +V_u2 4 0 0 +r2 3 2 20m +v2 2 4 65m +r1 1 5 1000 +d1 5 3 diode + +.dc v1 0e-00 5e-00 1e-00 + +* Control Statements +.control +run +plot v(5) +plot i(V_u2) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.pro b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.pro new file mode 100644 index 0000000..8e9a0fd --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.pro @@ -0,0 +1,84 @@ +update=Monday 13 May 2013 01:04:04 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/ambikeshwar/OSCAD/library/analogSpice +LibName32=/home/ambikeshwar/OSCAD/library/analogXSpice +LibName33=/home/ambikeshwar/OSCAD/library/convergenceAidSpice +LibName34=/home/ambikeshwar/OSCAD/library/converterSpice +LibName35=/home/ambikeshwar/OSCAD/library/digitalSpice +LibName36=/home/ambikeshwar/OSCAD/library/digitalXSpice +LibName37=/home/ambikeshwar/OSCAD/library/linearSpice +LibName38=/home/ambikeshwar/OSCAD/library/measurementSpice +LibName39=/home/ambikeshwar/OSCAD/library/portSpice +LibName40=/home/ambikeshwar/OSCAD/library/sourcesSpice +LibName41=/home/holy/OSCAD/library/analogSpice +LibName42=/home/holy/OSCAD/library/analogXSpice +LibName43=/home/holy/OSCAD/library/convergenceAidSpice +LibName44=/home/holy/OSCAD/library/converterSpice +LibName45=/home/holy/OSCAD/library/digitalSpice +LibName46=/home/holy/OSCAD/library/digitalXSpice +LibName47=/home/holy/OSCAD/library/linearSpice +LibName48=/home/holy/OSCAD/library/measurementSpice +LibName49=/home/holy/OSCAD/library/portSpice +LibName50=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.proj b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.proj new file mode 100644 index 0000000..1148c23 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.proj @@ -0,0 +1 @@ +schematicFile example_2.5.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.sch b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.sch new file mode 100644 index 0000000..ff9da18 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.5/example_2.5.sch @@ -0,0 +1,168 @@ +EESchema Schematic File Version 2 date Tuesday 21 May 2013 11:07:18 AM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_2.5-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "21 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 6650 2050 0 90 Italic 18 +Vd +Text Notes 6450 3850 0 90 Italic 18 +Id +$Comp +L DC v1 +U 1 1 5191FF90 +P 5000 3850 +F 0 "v1" H 4800 3950 60 0000 C CNN +F 1 "DC" H 4800 3800 60 0000 C CNN +F 2 "R1" H 4700 3850 60 0000 C CNN + 1 5000 3850 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 5190978A +P 6250 5300 +F 0 "#FLG01" H 6250 5570 30 0001 C CNN +F 1 "PWR_FLAG" H 6250 5530 30 0000 C CNN + 1 6250 5300 + 1 0 0 -1 +$EndComp +Connection ~ 6600 2100 +$Comp +L VPLOT8_1 U1 +U 1 1 51909775 +P 6600 1800 +F 0 "U1" H 6450 1900 50 0000 C CNN +F 1 "VPLOT8_1" H 6750 1900 50 0000 C CNN + 1 6600 1800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6250 5300 5000 5300 +Wire Wire Line + 6250 3300 6250 3350 +Wire Wire Line + 6250 4850 6250 5500 +Wire Wire Line + 6250 2350 6250 2100 +Connection ~ 6250 5300 +Connection ~ 6250 2100 +Wire Wire Line + 5250 2100 5000 2100 +Wire Wire Line + 5750 2100 6600 2100 +Connection ~ 6250 5300 +Wire Wire Line + 6250 2750 6250 2800 +Wire Wire Line + 5000 2100 5000 3400 +Wire Wire Line + 6250 4250 6250 4350 +Wire Wire Line + 5000 5300 5000 4300 +$Comp +L IPLOT U2 +U 1 1 519096FE +P 6250 4600 +F 0 "U2" H 6100 4700 50 0000 C CNN +F 1 "IPLOT" H 6400 4700 50 0000 C CNN + 1 6250 4600 + 0 1 1 0 +$EndComp +$Comp +L R Rd +U 1 1 519096A6 +P 6250 3050 +F 0 "Rd" V 6330 3050 50 0000 C CNN +F 1 "20m" V 6250 3050 50 0000 C CNN + 1 6250 3050 + 1 0 0 -1 +$EndComp +$Comp +L DC v2 +U 1 1 5190969F +P 6250 3800 +F 0 "v2" H 6050 3900 60 0000 C CNN +F 1 "65m" H 6050 3750 60 0000 C CNN +F 2 "R1" H 5950 3800 60 0000 C CNN + 1 6250 3800 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 516A928C +P 5500 2100 +F 0 "R1" V 5580 2100 50 0000 C CNN +F 1 "1000" V 5500 2100 50 0000 C CNN + 1 5500 2100 + 0 -1 -1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 5166AFB9 +P 6250 5500 +F 0 "#PWR02" H 6250 5500 30 0001 C CNN +F 1 "GND" H 6250 5430 30 0001 C CNN + 1 6250 5500 + 1 0 0 -1 +$EndComp +$Comp +L DIODE D1 +U 1 1 5166AF28 +P 6250 2550 +F 0 "D1" H 6250 2650 40 0000 C CNN +F 1 "DIODE" H 6250 2450 40 0000 C CNN + 1 6250 2550 + 0 1 1 0 +$EndComp +$EndSCHEMATC |