14 files changed, 1178 insertions, 0 deletions

diff --git a/FreeEDA/Examples/linear2/analysis b/FreeEDA/Examples/linear2/analysis
new file mode 100644
index 0000000..162ad08
--- /dev/null
+++ b/FreeEDA/Examples/linear2/analysis
@@ -0,0 +1 @@
+.op
\ No newline at end of file
diff --git a/FreeEDA/Examples/linear2/linear2-cache.bak b/FreeEDA/Examples/linear2/linear2-cache.bak
new file mode 100644
index 0000000..df2206b
--- /dev/null
+++ b/FreeEDA/Examples/linear2/linear2-cache.bak
@@ -0,0 +1,89 @@
+EESchema-LIBRARY Version 2.3  Date: Monday 17 December 2012 11:32:27 AM IST
+#encoding utf-8
+#
+# CCVS
+#
+DEF CCVS H 0 40 Y Y 1 F N
+F0 "H" -200 100 50 H V C CNN
+F1 "CCVS" -200 -50 50 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+S -100 100 100 -100 0 1 0 N
+X + 1 -300 50 200 R 35 35 1 1 P
+X - 2 300 50 200 L 35 35 1 1 P
+X +c 3 -50 -200 100 U 35 35 1 1 P
+X -c 4 50 -200 100 U 35 35 1 1 P
+ENDDRAW
+ENDDEF
+#
+# dc
+#
+DEF dc v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "dc" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF ~GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 0 30 H I C CNN
+F1 "GND" 0 -70 30 H I C CNN
+DRAW
+P 4 0 1 0  -50 0  0 -50  50 0  -50 0 N
+X GND 1 0 0 0 U 30 30 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 270 30 H I C CNN
+F1 "PWR_FLAG" 0 230 30 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 20 20 0 0 w
+P 3 0 1 0  0 0  0 100  0 100 N
+P 5 0 1 0  0 100  -100 150  0 200  100 150  0 100 N
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "R" 0 0 50 V V C CNN
+$FPLIST
+ R?
+ SM0603
+ SM0805
+ R?-*
+$ENDFPLIST
+DRAW
+S -40 150 40 -150 0 1 12 N
+X ~ 1 0 250 100 D 60 60 1 1 P
+X ~ 2 0 -250 100 U 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# vprint1
+#
+DEF vprint1 U 0 40 Y Y 1 F N
+F0 "U" -150 100 50 H V C CNN
+F1 "vprint1" 150 100 50 H V C CNN
+DRAW
+C 0 0 100 0 0 0 N
+X + 1 0 -300 200 U 40 40 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/FreeEDA/Examples/linear2/linear2-cache.lib b/FreeEDA/Examples/linear2/linear2-cache.lib
new file mode 100644
index 0000000..79f9376
--- /dev/null
+++ b/FreeEDA/Examples/linear2/linear2-cache.lib
@@ -0,0 +1,89 @@
+EESchema-LIBRARY Version 2.3  Date: Monday 17 December 2012 11:32:49 AM IST
+#encoding utf-8
+#
+# CCVS
+#
+DEF CCVS H 0 40 Y Y 1 F N
+F0 "H" -200 100 50 H V C CNN
+F1 "CCVS" -200 -50 50 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+S -100 100 100 -100 0 1 0 N
+X + 1 -300 50 200 R 35 35 1 1 P
+X - 2 300 50 200 L 35 35 1 1 P
+X +c 3 -50 -200 100 U 35 35 1 1 P
+X -c 4 50 -200 100 U 35 35 1 1 P
+ENDDRAW
+ENDDEF
+#
+# dc
+#
+DEF dc v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "dc" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF ~GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 0 30 H I C CNN
+F1 "GND" 0 -70 30 H I C CNN
+DRAW
+P 4 0 1 0  -50 0  0 -50  50 0  -50 0 N
+X GND 1 0 0 0 U 30 30 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 270 30 H I C CNN
+F1 "PWR_FLAG" 0 230 30 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 20 20 0 0 w
+P 3 0 1 0  0 0  0 100  0 100 N
+P 5 0 1 0  0 100  -100 150  0 200  100 150  0 100 N
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "R" 0 0 50 V V C CNN
+$FPLIST
+ R?
+ SM0603
+ SM0805
+ R?-*
+$ENDFPLIST
+DRAW
+S -40 150 40 -150 0 1 12 N
+X ~ 1 0 250 100 D 60 60 1 1 P
+X ~ 2 0 -250 100 U 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# vprint1
+#
+DEF vprint1 U 0 40 Y Y 1 F N
+F0 "U" -150 100 50 H V C CNN
+F1 "vprint1" 150 100 50 H V C CNN
+DRAW
+C 0 0 100 0 0 0 N
+X + 1 0 -300 200 U 40 40 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/FreeEDA/Examples/linear2/linear2.bak b/FreeEDA/Examples/linear2/linear2.bak
new file mode 100644
index 0000000..e9d9386
--- /dev/null
+++ b/FreeEDA/Examples/linear2/linear2.bak
@@ -0,0 +1,181 @@
+EESchema Schematic File Version 2  date Monday 17 December 2012 11:32:27 AM IST
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:analogSpice
+LIBS:converterSpice
+LIBS:digitalSpice
+LIBS:linearSpice
+LIBS:measurementSpice
+LIBS:portSpice
+LIBS:sourcesSpice
+LIBS:linear2-cache
+EELAYER 25  0
+EELAYER END
+$Descr A4 11700 8267
+encoding utf-8
+Sheet 1 1
+Title ""
+Date "22 oct 2012"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+Connection ~ 6450 4000
+Wire Wire Line
+	6450 4000 6450 3800
+Connection ~ 6750 3000
+Wire Wire Line
+	6750 3000 6750 2850
+Connection ~ 6000 4000
+Wire Wire Line
+	6000 3800 6000 4000
+Connection ~ 5300 3000
+Wire Wire Line
+	5300 3300 5300 3000
+Wire Wire Line
+	6850 3800 6850 4000
+Wire Wire Line
+	6850 4000 4800 4000
+Wire Wire Line
+	4800 4000 4800 3950
+Wire Wire Line
+	5850 3000 6100 3000
+Wire Wire Line
+	4800 3050 4800 3000
+Wire Wire Line
+	4800 3000 5350 3000
+Wire Wire Line
+	6600 3000 6850 3000
+Wire Wire Line
+	6850 3000 6850 3200
+Wire Wire Line
+	5300 3800 5300 4000
+Connection ~ 5300 4000
+Wire Wire Line
+	6000 3000 6000 3150
+Connection ~ 6000 3000
+Wire Wire Line
+	5600 4000 5600 4150
+Connection ~ 5600 4000
+$Comp
+L PWR_FLAG #FLG01
+U 1 1 5069EA51
+P 6450 3800
+F 0 "#FLG01" H 6450 4070 30  0001 C CNN
+F 1 "PWR_FLAG" H 6450 4030 30  0000 C CNN
+	1    6450 3800
+	1    0    0    -1  
+$EndComp
+$Comp
+L GND #PWR02
+U 1 1 5069EA30
+P 5600 4150
+F 0 "#PWR02" H 5600 4150 30  0001 C CNN
+F 1 "GND" H 5600 4080 30  0001 C CNN
+	1    5600 4150
+	1    0    0    -1  
+$EndComp
+$Comp
+L VPRINT1 U1
+U 1 1 5069E9D3
+P 6750 2550
+F 0 "U1" H 6600 2650 50  0001 C CNN
+F 1 "VPRINT1" H 6900 2650 50  0000 C CNN
+	1    6750 2550
+	1    0    0    -1  
+$EndComp
+Text Label 6600 3550 0    60   ~ 0
+b
+Text Label 6600 3450 0    60   ~ 0
+a
+Text Label 6000 3300 0    60   ~ 0
+b
+Text Label 6000 3150 0    60   ~ 0
+a
+$Comp
+L R R4
+U 1 1 5069E7B0
+P 6350 3000
+F 0 "R4" V 6430 3000 50  0000 C CNN
+F 1 "0.1" V 6350 3000 50  0000 C CNN
+	1    6350 3000
+	0    1    1    0   
+$EndComp
+$Comp
+L R R1
+U 1 1 5069E7AC
+P 5300 3550
+F 0 "R1" V 5380 3550 50  0000 C CNN
+F 1 "0.2" V 5300 3550 50  0000 C CNN
+	1    5300 3550
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R2
+U 1 1 5069E7A9
+P 5600 3000
+F 0 "R2" V 5680 3000 50  0000 C CNN
+F 1 "0.1" V 5600 3000 50  0000 C CNN
+	1    5600 3000
+	0    1    1    0   
+$EndComp
+$Comp
+L R R3
+U 1 1 5069E7A6
+P 6000 3550
+F 0 "R3" V 6080 3550 50  0000 C CNN
+F 1 "0.2" V 6000 3550 50  0000 C CNN
+	1    6000 3550
+	1    0    0    -1  
+$EndComp
+$Comp
+L CCVS H1
+U 1 1 5069E78C
+P 6800 3500
+F 0 "H1" H 6600 3600 50  0000 C CNN
+F 1 "2" H 6600 3450 50  0000 C CNN
+	1    6800 3500
+	0    1    1    0   
+$EndComp
+$Comp
+L DC I1
+U 1 1 5069E6DB
+P 4800 3500
+F 0 "I1" H 4600 3600 60  0000 C CNN
+F 1 "1" H 4600 3450 60  0000 C CNN
+F 2 "R1" H 4500 3500 60  0000 C CNN
+	1    4800 3500
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/FreeEDA/Examples/linear2/linear2.brd b/FreeEDA/Examples/linear2/linear2.brd
new file mode 100644
index 0000000..ab9dee7
--- /dev/null
+++ b/FreeEDA/Examples/linear2/linear2.brd
@@ -0,0 +1,398 @@
+PCBNEW-BOARD Version 1 date Tuesday 02 October 2012 12:48:38 AM IST
+
+# Created by Pcbnew(2011-05-25)-stable
+
+$GENERAL
+encoding utf-8
+LayerCount 2
+Ly 1FFF8001
+EnabledLayers 1FFF8001
+Links 9
+NoConn 0
+Di 48825 32959 59875 43721
+Ndraw 0
+Ntrack 25
+Nzone 0
+BoardThickness 630
+Nmodule 6
+Nnets 6
+$EndGENERAL
+
+$SHEETDESCR
+Sheet A4 11700 8267
+Title ""
+Date "1 oct 2012"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndSHEETDESCR
+
+$SETUP
+InternalUnit 0.000100 INCH
+Layers 2
+Layer[0] Back signal
+Layer[15] Front signal
+TrackWidth 80
+TrackClearence 100
+ZoneClearence 200
+TrackMinWidth 80
+DrawSegmWidth 150
+EdgeSegmWidth 150
+ViaSize 350
+ViaDrill 250
+ViaMinSize 350
+ViaMinDrill 200
+MicroViaSize 200
+MicroViaDrill 50
+MicroViasAllowed 0
+MicroViaMinSize 200
+MicroViaMinDrill 50
+TextPcbWidth 120
+TextPcbSize 600 800
+EdgeModWidth 150
+TextModSize 600 600
+TextModWidth 120
+PadSize 600 600
+PadDrill 320
+Pad2MaskClearance 100
+AuxiliaryAxisOrg 0 0
+PcbPlotParams (pcbplotparams (layerselection 3178497) (usegerberextensions true) (excludeedgelayer true) (linewidth 60) (plotframeref false) (viasonmask false) (mode 1) (useauxorigin false) (hpglpennumber 1) (hpglpenspeed 20) (hpglpendiameter 15) (hpglpenoverlay 2) (pscolor true) (psnegative false) (psa4output false) (plotreference true) (plotvalue true) (plotothertext true) (plotinvisibletext false) (padsonsilk false) (subtractmaskfromsilk false) (outputformat 1) (mirror false) (drillshape 1) (scaleselection 1) (outputdirectory ""))
+$EndSETUP
+
+$EQUIPOT
+Na 0 ""
+St ~
+$EndEQUIPOT
+$EQUIPOT
+Na 1 "/a"
+St ~
+$EndEQUIPOT
+$EQUIPOT
+Na 2 "/b"
+St ~
+$EndEQUIPOT
+$EQUIPOT
+Na 3 "GND"
+St ~
+$EndEQUIPOT
+$EQUIPOT
+Na 4 "N-000004"
+St ~
+$EndEQUIPOT
+$EQUIPOT
+Na 5 "N-000005"
+St ~
+$EndEQUIPOT
+$NCLASS
+Name "Default"
+Desc "This is the default net class."
+Clearance 100
+TrackWidth 80
+ViaDia 350
+ViaDrill 250
+uViaDia 200
+uViaDrill 50
+AddNet ""
+AddNet "/a"
+AddNet "/b"
+AddNet "GND"
+AddNet "N-000004"
+AddNet "N-000005"
+$EndNCLASS
+$MODULE R3
+Po 58000 34500 0 15 00200000 5069EAF6 ~~
+Li R3
+Cd Resitance 3 pas
+Kw R
+Sc 5069EAF6
+AR /5069E7AC
+Op 0 A 0
+T0 0 0 550 500 0 80 N V 21 N "R1"
+T1 0 0 550 500 0 80 N I 21 N "0.2"
+DS -1500 0 -1300 0 120 21
+DS 1500 0 1300 0 120 21
+DS 1300 0 1300 -400 120 21
+DS 1300 -400 -1300 -400 120 21
+DS -1300 -400 -1300 400 120 21
+DS -1300 400 1300 400 120 21
+DS 1300 400 1300 0 120 21
+DS -1300 -200 -1100 -400 120 21
+$PAD
+Sh "1" C 550 550 0 0 0
+Dr 320 0 0
+At STD N 00E0FFFF
+Ne 4 "N-000004"
+Po -1500 0
+$EndPAD
+$PAD
+Sh "2" C 550 550 0 0 0
+Dr 320 0 0
+At STD N 00E0FFFF
+Ne 3 "GND"
+Po 1500 0
+$EndPAD
+$SHAPE3D
+Na "discret/resistor.wrl"
+Sc 0.300000 0.300000 0.300000
+Of 0.000000 0.000000 0.000000
+Ro 0.000000 0.000000 0.000000
+$EndSHAPE3D
+$EndMODULE  R3
+$MODULE R3
+Po 58000 39500 0 15 00200000 5069EAF8 ~~
+Li R3
+Cd Resitance 3 pas
+Kw R
+Sc 5069EAF8
+AR /5069E7A9
+Op 0 A 0
+T0 0 0 550 500 0 80 N V 21 N "R2"
+T1 0 0 550 500 0 80 N I 21 N "0.1"
+DS -1500 0 -1300 0 120 21
+DS 1500 0 1300 0 120 21
+DS 1300 0 1300 -400 120 21
+DS 1300 -400 -1300 -400 120 21
+DS -1300 -400 -1300 400 120 21
+DS -1300 400 1300 400 120 21
+DS 1300 400 1300 0 120 21
+DS -1300 -200 -1100 -400 120 21
+$PAD
+Sh "1" C 550 550 0 0 0
+Dr 320 0 0
+At STD N 00E0FFFF
+Ne 1 "/a"
+Po -1500 0
+$EndPAD
+$PAD
+Sh "2" C 550 550 0 0 0
+Dr 320 0 0
+At STD N 00E0FFFF
+Ne 4 "N-000004"
+Po 1500 0
+$EndPAD
+$SHAPE3D
+Na "discret/resistor.wrl"
+Sc 0.300000 0.300000 0.300000
+Of 0.000000 0.000000 0.000000
+Ro 0.000000 0.000000 0.000000
+$EndSHAPE3D
+$EndMODULE  R3
+$MODULE R3
+Po 58000 37000 0 15 00200000 5069EAFA ~~
+Li R3
+Cd Resitance 3 pas
+Kw R
+Sc 5069EAFA
+AR /5069E7A6
+Op 0 A 0
+T0 0 0 550 500 0 80 N V 21 N "R3"
+T1 0 0 550 500 0 80 N I 21 N "0.2"
+DS -1500 0 -1300 0 120 21
+DS 1500 0 1300 0 120 21
+DS 1300 0 1300 -400 120 21
+DS 1300 -400 -1300 -400 120 21
+DS -1300 -400 -1300 400 120 21
+DS -1300 400 1300 400 120 21
+DS 1300 400 1300 0 120 21
+DS -1300 -200 -1100 -400 120 21
+$PAD
+Sh "1" C 550 550 0 0 0
+Dr 320 0 0
+At STD N 00E0FFFF
+Ne 2 "/b"
+Po -1500 0
+$EndPAD
+$PAD
+Sh "2" C 550 550 0 0 0
+Dr 320 0 0
+At STD N 00E0FFFF
+Ne 3 "GND"
+Po 1500 0
+$EndPAD
+$SHAPE3D
+Na "discret/resistor.wrl"
+Sc 0.300000 0.300000 0.300000
+Of 0.000000 0.000000 0.000000
+Ro 0.000000 0.000000 0.000000
+$EndSHAPE3D
+$EndMODULE  R3
+$MODULE R3
+Po 58000 42500 0 15 00200000 5069EAFC ~~
+Li R3
+Cd Resitance 3 pas
+Kw R
+Sc 5069EAFC
+AR /5069E7B0
+Op 0 A 0
+T0 0 0 550 500 0 80 N V 21 N "R4"
+T1 0 0 550 500 0 80 N I 21 N "0.1"
+DS -1500 0 -1300 0 120 21
+DS 1500 0 1300 0 120 21
+DS 1300 0 1300 -400 120 21
+DS 1300 -400 -1300 -400 120 21
+DS -1300 -400 -1300 400 120 21
+DS -1300 400 1300 400 120 21
+DS 1300 400 1300 0 120 21
+DS -1300 -200 -1100 -400 120 21
+$PAD
+Sh "1" C 550 550 0 0 0
+Dr 320 0 0
+At STD N 00E0FFFF
+Ne 5 "N-000005"
+Po -1500 0
+$EndPAD
+$PAD
+Sh "2" C 550 550 0 0 0
+Dr 320 0 0
+At STD N 00E0FFFF
+Ne 1 "/a"
+Po 1500 0
+$EndPAD
+$SHAPE3D
+Na "discret/resistor.wrl"
+Sc 0.300000 0.300000 0.300000
+Of 0.000000 0.000000 0.000000
+Ro 0.000000 0.000000 0.000000
+$EndSHAPE3D
+$EndMODULE  R3
+$MODULE R1
+Po 52000 34000 0 15 00200000 5069EAFD ~~
+Li R1
+Cd Resistance verticale
+Kw R
+Sc 5069EAFD
+AR /5069E6DB
+Op A A 0
+T0 -400 1000 550 500 0 80 N V 21 N "I1"
+T1 -450 1000 550 500 0 80 N I 21 N "DC"
+DS -500 0 500 0 150 21
+DC -500 0 -250 500 150 21
+$PAD
+Sh "1" C 550 550 0 0 0
+Dr 320 0 0
+At STD N 00E0FFFF
+Ne 4 "N-000004"
+Po -500 0
+$EndPAD
+$PAD
+Sh "2" C 550 550 0 0 0
+Dr 320 0 0
+At STD N 00E0FFFF
+Ne 3 "GND"
+Po 500 0
+$EndPAD
+$SHAPE3D
+Na "discret/verti_resistor.wrl"
+Sc 1.000000 1.000000 1.000000
+Of 0.000000 0.000000 0.000000
+Ro 0.000000 0.000000 0.000000
+$EndSHAPE3D
+$EndMODULE  R1
+$MODULE bornier4
+Po 52000 39500 900 15 3EC0ED29 5069EAFE ~~
+Li bornier4
+Cd Bornier d'alimentation 4 pins
+Kw DEV
+Sc 5069EAFE
+AR /5069E78C
+Op 0 0 0
+T0 0 -2500 1030 629 900 120 N V 21 N "H1"
+T1 0 2000 600 600 900 120 N V 21 N "2"
+DS -4000 -1500 -4000 1500 120 21
+DS 4000 1500 4000 -1500 120 21
+DS 4000 1000 -4000 1000 120 21
+DS -4000 -1500 4000 -1500 120 21
+DS -4000 1500 4000 1500 120 21
+$PAD
+Sh "2" C 1500 1500 0 0 900
+Dr 600 0 0
+At STD N 00E0FFFF
+Ne 3 "GND"
+Po -1000 0
+$EndPAD
+$PAD
+Sh "3" C 1500 1500 0 0 900
+Dr 600 0 0
+At STD N 00E0FFFF
+Ne 1 "/a"
+Po 1000 0
+$EndPAD
+$PAD
+Sh "1" R 1500 1500 0 0 900
+Dr 600 0 0
+At STD N 00E0FFFF
+Ne 5 "N-000005"
+Po -3000 0
+$EndPAD
+$PAD
+Sh "4" C 1500 1500 0 0 900
+Dr 600 0 0
+At STD N 00E0FFFF
+Ne 2 "/b"
+Po 3000 0
+$EndPAD
+$SHAPE3D
+Na "device/bornier_4.wrl"
+Sc 1.000000 1.000000 1.000000
+Of 0.000000 0.000000 0.000000
+Ro 0.000000 0.000000 0.000000
+$EndSHAPE3D
+$EndMODULE  bornier4
+$TRACK
+Po 0 56500 39500 58000 39500 80 -1
+De 0 0 1 0 400000
+Po 0 59500 41000 59500 42500 80 -1
+De 0 0 1 0 800000
+Po 0 58000 39500 59500 41000 80 -1
+De 0 0 1 0 0
+Po 0 52000 38500 55500 38500 80 -1
+De 0 0 1 0 400000
+Po 0 55500 38500 56500 39500 80 -1
+De 0 0 1 0 800000
+Po 0 52000 36500 56000 36500 80 -1
+De 0 0 2 0 400000
+Po 0 56000 36500 56500 37000 80 -1
+De 0 0 2 0 800000
+Po 0 52000 40500 50500 39000 80 -1
+De 0 0 3 0 400000
+Po 0 52500 33500 52500 34000 80 -1
+De 0 0 3 0 800000
+Po 0 52000 33000 52500 33500 80 -1
+De 0 0 3 0 0
+Po 0 51000 33000 52000 33000 80 -1
+De 0 0 3 0 0
+Po 0 50500 33500 51000 33000 80 -1
+De 0 0 3 0 0
+Po 0 50500 39000 50500 33500 80 -1
+De 0 0 3 0 0
+Po 0 59500 34500 59500 37000 80 -1
+De 0 0 3 0 C00000
+Po 0 52500 34000 55000 34000 80 -1
+De 0 0 3 0 400000
+Po 0 58500 33500 59500 34500 80 -1
+De 0 0 3 0 800000
+Po 0 55500 33500 58500 33500 80 -1
+De 0 0 3 0 0
+Po 0 55000 34000 55500 33500 80 -1
+De 0 0 3 0 0
+Po 0 56500 34500 57500 34500 80 -1
+De 0 0 4 0 400000
+Po 0 58500 38500 59500 39500 80 -1
+De 0 0 4 0 800000
+Po 0 58500 35500 58500 38500 80 -1
+De 0 0 4 0 0
+Po 0 57500 34500 58500 35500 80 -1
+De 0 0 4 0 0
+Po 0 51500 34000 52000 34500 80 -1
+De 0 0 4 0 400000
+Po 0 52000 34500 56500 34500 80 -1
+De 0 0 4 0 800000
+Po 0 52000 42500 56500 42500 80 -1
+De 0 0 5 0 C00000
+$EndTRACK
+$ZONE
+$EndZONE
+$EndBOARD
diff --git a/FreeEDA/Examples/linear2/linear2.cir b/FreeEDA/Examples/linear2/linear2.cir
new file mode 100644
index 0000000..f3a43b2
--- /dev/null
+++ b/FreeEDA/Examples/linear2/linear2.cir
@@ -0,0 +1,15 @@
+* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:32:43 AM IST
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+*Sheet Name:/
+U1  5 VPRINT1		
+R4  5 2 0.1		
+R1  4 0 0.2		
+R2  2 4 0.1		
+R3  3 0 0.2		
+H1  5 0 2 3 2		
+I1  4 0 1		
+
+.end
diff --git a/FreeEDA/Examples/linear2/linear2.cir.ckt b/FreeEDA/Examples/linear2/linear2.cir.ckt
new file mode 100644
index 0000000..04d0eb4
--- /dev/null
+++ b/FreeEDA/Examples/linear2/linear2.cir.ckt
@@ -0,0 +1,15 @@
+* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:32:43 am ist

+

+* Printing option vprint1

+r4  5 2 0.1

+r1  4 0 0.2

+r2  2 4 0.1

+r3  3 0 0.2

+* h1

+i1  4 0 1

+Vh1 2 3 0

+h1 5 0 Vh1 2

+

+.op

+.print v(5)

+.end

diff --git a/FreeEDA/Examples/linear2/linear2.cir.ckt.sol b/FreeEDA/Examples/linear2/linear2.cir.ckt.sol
new file mode 100644
index 0000000..924ce9b
--- /dev/null
+++ b/FreeEDA/Examples/linear2/linear2.cir.ckt.sol
@@ -0,0 +1,9 @@
+Name	 Source	 Sink	       Voltage	       Current
+----------------------------------------------------------
+R	 5	 2	    0.0000000000    0.0000000000
+R	 4	 0	    0.0000000000    0.0000000000
+R	 2	 4	    0.0000000000    0.0000000000
+R	 3	 0	    0.0000000000    0.0000000000
+I	 4	 0	    0.0000000000    0.0000000000
+V	 2	 3	    0.0000000000    0.0000000000
+H	 5	 0	    0.0000000000    0.0000000000
diff --git a/FreeEDA/Examples/linear2/linear2.cir.out b/FreeEDA/Examples/linear2/linear2.cir.out
new file mode 100644
index 0000000..e0328e7
--- /dev/null
+++ b/FreeEDA/Examples/linear2/linear2.cir.out
@@ -0,0 +1,20 @@
+* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:32:43 am ist

+

+* Printing option vprint1

+r4  5 2 0.1

+r1  4 0 0.2

+r2  2 4 0.1

+r3  3 0 0.2

+* h1

+i1  4 0 1

+Vh1 2 3 0

+h1 5 0 Vh1 2

+

+.op

+

+* Control Statements 

+.control

+run

+print v(5)

+.endc

+.end

diff --git a/FreeEDA/Examples/linear2/linear2.cmp b/FreeEDA/Examples/linear2/linear2.cmp
new file mode 100644
index 0000000..3d50822
--- /dev/null
+++ b/FreeEDA/Examples/linear2/linear2.cmp
@@ -0,0 +1,45 @@
+Cmp-Mod V01 Created by CvPCB (2011-05-25)-stable date = Tuesday 02 October 2012 12:41:01 AM IST
+
+BeginCmp
+TimeStamp = /5069E78C;
+Reference = H1;
+ValeurCmp = 2;
+IdModule  = bornier4;
+EndCmp
+
+BeginCmp
+TimeStamp = /5069E6DB;
+Reference = I1;
+ValeurCmp = DC;
+IdModule  = R1;
+EndCmp
+
+BeginCmp
+TimeStamp = /5069E7AC;
+Reference = R1;
+ValeurCmp = 0.2;
+IdModule  = R3;
+EndCmp
+
+BeginCmp
+TimeStamp = /5069E7A9;
+Reference = R2;
+ValeurCmp = 0.1;
+IdModule  = R3;
+EndCmp
+
+BeginCmp
+TimeStamp = /5069E7A6;
+Reference = R3;
+ValeurCmp = 0.2;
+IdModule  = R3;
+EndCmp
+
+BeginCmp
+TimeStamp = /5069E7B0;
+Reference = R4;
+ValeurCmp = 0.1;
+IdModule  = R3;
+EndCmp
+
+EndListe
diff --git a/FreeEDA/Examples/linear2/linear2.net b/FreeEDA/Examples/linear2/linear2.net
new file mode 100644
index 0000000..11706cb
--- /dev/null
+++ b/FreeEDA/Examples/linear2/linear2.net
@@ -0,0 +1,63 @@
+# EESchema Netlist Version 1.1 created  Tuesday 02 October 2012 12:41:01 AM IST
+(
+ ( /5069E78C bornier4 H1 2
+  ( 1 N-000005 )
+  ( 2 GND )
+  ( 3 /a )
+  ( 4 /b )
+ )
+ ( /5069E6DB R1 I1 DC
+  ( 1 N-000004 )
+  ( 2 GND )
+ )
+ ( /5069E7AC R3 R1 0.2
+  ( 1 N-000004 )
+  ( 2 GND )
+ )
+ ( /5069E7A9 R3 R2 0.1
+  ( 1 /a )
+  ( 2 N-000004 )
+ )
+ ( /5069E7A6 R3 R3 0.2
+  ( 1 /b )
+  ( 2 GND )
+ )
+ ( /5069E7B0 R3 R4 0.1
+  ( 1 N-000005 )
+  ( 2 /a )
+ )
+)
+*
+{ Allowed footprints by component:
+$component H1
+ 1_pin
+$endlist
+$component I1
+ 1_pin
+$endlist
+$component R1
+ R?
+ SM0603
+ SM0805
+ R?-*
+$endlist
+$component R2
+ R?
+ SM0603
+ SM0805
+ R?-*
+$endlist
+$component R3
+ R?
+ SM0603
+ SM0805
+ R?-*
+$endlist
+$component R4
+ R?
+ SM0603
+ SM0805
+ R?-*
+$endlist
+$endfootprintlist
+}
diff --git a/FreeEDA/Examples/linear2/linear2.pro b/FreeEDA/Examples/linear2/linear2.pro
new file mode 100644
index 0000000..9452331
--- /dev/null
+++ b/FreeEDA/Examples/linear2/linear2.pro
@@ -0,0 +1,71 @@
+update=Monday 22 October 2012 04:17:19 PM IST
+last_client=eeschema
+[eeschema]
+version=1
+LibDir=/home/yogesh/FreeEDA/library
+NetFmt=1
+HPGLSpd=20
+HPGLDm=15
+HPGLNum=1
+offX_A4=0
+offY_A4=0
+offX_A3=0
+offY_A3=0
+offX_A2=0
+offY_A2=0
+offX_A1=0
+offY_A1=0
+offX_A0=0
+offY_A0=0
+offX_A=0
+offY_A=0
+offX_B=0
+offY_B=0
+offX_C=0
+offY_C=0
+offX_D=0
+offY_D=0
+offX_E=0
+offY_E=0
+RptD_X=0
+RptD_Y=100
+RptLab=1
+LabSize=60
+[eeschema/libraries]
+LibName1=power
+LibName2=device
+LibName3=transistors
+LibName4=conn
+LibName5=linear
+LibName6=regul
+LibName7=74xx
+LibName8=cmos4000
+LibName9=adc-dac
+LibName10=memory
+LibName11=xilinx
+LibName12=special
+LibName13=microcontrollers
+LibName14=dsp
+LibName15=microchip
+LibName16=analog_switches
+LibName17=motorola
+LibName18=texas
+LibName19=intel
+LibName20=audio
+LibName21=interface
+LibName22=digital-audio
+LibName23=philips
+LibName24=display
+LibName25=cypress
+LibName26=siliconi
+LibName27=opto
+LibName28=atmel
+LibName29=contrib
+LibName30=valves
+LibName31=analogSpice
+LibName32=converterSpice
+LibName33=digitalSpice
+LibName34=linearSpice
+LibName35=measurementSpice
+LibName36=portSpice
+LibName37=sourcesSpice
diff --git a/FreeEDA/Examples/linear2/linear2.proj b/FreeEDA/Examples/linear2/linear2.proj
new file mode 100644
index 0000000..8bb7fa3
--- /dev/null
+++ b/FreeEDA/Examples/linear2/linear2.proj
@@ -0,0 +1 @@
+schematicFile linear2.sch
diff --git a/FreeEDA/Examples/linear2/linear2.sch b/FreeEDA/Examples/linear2/linear2.sch
new file mode 100644
index 0000000..c85a06a
--- /dev/null
+++ b/FreeEDA/Examples/linear2/linear2.sch
@@ -0,0 +1,181 @@
+EESchema Schematic File Version 2  date Monday 17 December 2012 11:32:49 AM IST
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:analogSpice
+LIBS:converterSpice
+LIBS:digitalSpice
+LIBS:linearSpice
+LIBS:measurementSpice
+LIBS:portSpice
+LIBS:sourcesSpice
+LIBS:linear2-cache
+EELAYER 25  0
+EELAYER END
+$Descr A4 11700 8267
+encoding utf-8
+Sheet 1 1
+Title ""
+Date "22 oct 2012"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+Connection ~ 6450 4000
+Wire Wire Line
+	6450 4000 6450 3800
+Connection ~ 6750 3000
+Wire Wire Line
+	6750 3000 6750 2850
+Connection ~ 6000 4000
+Wire Wire Line
+	6000 3800 6000 4000
+Connection ~ 5300 3000
+Wire Wire Line
+	5300 3300 5300 3000
+Wire Wire Line
+	6850 3800 6850 4000
+Wire Wire Line
+	6850 4000 4800 4000
+Wire Wire Line
+	4800 4000 4800 3950
+Wire Wire Line
+	5850 3000 6100 3000
+Wire Wire Line
+	4800 3050 4800 3000
+Wire Wire Line
+	4800 3000 5350 3000
+Wire Wire Line
+	6600 3000 6850 3000
+Wire Wire Line
+	6850 3000 6850 3200
+Wire Wire Line
+	5300 3800 5300 4000
+Connection ~ 5300 4000
+Wire Wire Line
+	6000 3000 6000 3150
+Connection ~ 6000 3000
+Wire Wire Line
+	5600 4000 5600 4150
+Connection ~ 5600 4000
+$Comp
+L PWR_FLAG #FLG01
+U 1 1 5069EA51
+P 6450 3800
+F 0 "#FLG01" H 6450 4070 30  0001 C CNN
+F 1 "PWR_FLAG" H 6450 4030 30  0000 C CNN
+	1    6450 3800
+	1    0    0    -1  
+$EndComp
+$Comp
+L GND #PWR02
+U 1 1 5069EA30
+P 5600 4150
+F 0 "#PWR02" H 5600 4150 30  0001 C CNN
+F 1 "GND" H 5600 4080 30  0001 C CNN
+	1    5600 4150
+	1    0    0    -1  
+$EndComp
+$Comp
+L VPRINT1 U1
+U 1 1 5069E9D3
+P 6750 2550
+F 0 "U1" H 6600 2650 50  0001 C CNN
+F 1 "VPRINT1" H 6900 2650 50  0000 C CNN
+	1    6750 2550
+	1    0    0    -1  
+$EndComp
+Text Label 6600 3550 0    60   ~ 0
+b
+Text Label 6600 3450 0    60   ~ 0
+a
+Text Label 6000 3300 0    60   ~ 0
+b
+Text Label 6000 3150 0    60   ~ 0
+a
+$Comp
+L R R4
+U 1 1 5069E7B0
+P 6350 3000
+F 0 "R4" V 6430 3000 50  0000 C CNN
+F 1 "0.1" V 6350 3000 50  0000 C CNN
+	1    6350 3000
+	0    1    1    0   
+$EndComp
+$Comp
+L R R1
+U 1 1 5069E7AC
+P 5300 3550
+F 0 "R1" V 5380 3550 50  0000 C CNN
+F 1 "0.2" V 5300 3550 50  0000 C CNN
+	1    5300 3550
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R2
+U 1 1 5069E7A9
+P 5600 3000
+F 0 "R2" V 5680 3000 50  0000 C CNN
+F 1 "0.1" V 5600 3000 50  0000 C CNN
+	1    5600 3000
+	0    1    1    0   
+$EndComp
+$Comp
+L R R3
+U 1 1 5069E7A6
+P 6000 3550
+F 0 "R3" V 6080 3550 50  0000 C CNN
+F 1 "0.2" V 6000 3550 50  0000 C CNN
+	1    6000 3550
+	1    0    0    -1  
+$EndComp
+$Comp
+L CCVS H1
+U 1 1 5069E78C
+P 6800 3500
+F 0 "H1" H 6600 3600 50  0000 C CNN
+F 1 "2" H 6600 3450 50  0000 C CNN
+	1    6800 3500
+	0    1    1    0   
+$EndComp
+$Comp
+L DC I1
+U 1 1 5069E6DB
+P 4800 3500
+F 0 "I1" H 4600 3600 60  0000 C CNN
+F 1 "1" H 4600 3450 60  0000 C CNN
+F 2 "R1" H 4500 3500 60  0000 C CNN
+	1    4800 3500
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC