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author | Fahim | 2014-09-09 16:11:17 +0530 |
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committer | Fahim | 2014-09-09 16:11:17 +0530 |
commit | c632c1009c9e095135220c809d7c799841f160b3 (patch) | |
tree | 3be2def8313164c3bf32799714ba53a4a1326ed6 /OSCAD/Examples/simpleTTL/simpleTTL.bak | |
parent | e338c2a59389c22b8cca9a78d75e626ae779c405 (diff) | |
download | FreeEDA-c632c1009c9e095135220c809d7c799841f160b3.tar.gz FreeEDA-c632c1009c9e095135220c809d7c799841f160b3.tar.bz2 FreeEDA-c632c1009c9e095135220c809d7c799841f160b3.zip |
Subject: Changing all content and name of directory and file to FreeEDA
Description: The content of file,name of directory and file has been
changed in the below format.
1. Oscad to FreeEDA
2. OSCAD to FreeEDA
3. oscad to freeeda
Diffstat (limited to 'OSCAD/Examples/simpleTTL/simpleTTL.bak')
-rw-r--r-- | OSCAD/Examples/simpleTTL/simpleTTL.bak | 166 |
1 files changed, 0 insertions, 166 deletions
diff --git a/OSCAD/Examples/simpleTTL/simpleTTL.bak b/OSCAD/Examples/simpleTTL/simpleTTL.bak deleted file mode 100644 index 2bf0b11..0000000 --- a/OSCAD/Examples/simpleTTL/simpleTTL.bak +++ /dev/null @@ -1,166 +0,0 @@ -EESchema Schematic File Version 2 date Thursday 20 December 2012 12:04:47 AM IST -LIBS:power -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:analogSpice -LIBS:converterSpice -LIBS:digitalSpice -LIBS:linearSpice -LIBS:measurementSpice -LIBS:portSpice -LIBS:sourcesSpice -LIBS:digitalXSpice -LIBS:analogXSpice -LIBS:simpleTTL-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11700 8267 -encoding utf-8 -Sheet 1 1 -Title "" -Date "19 dec 2012" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Connection ~ 5550 3450 -Wire Wire Line - 5550 3300 5550 3600 -Wire Wire Line - 2950 4600 5550 4600 -Connection ~ 4500 4600 -Wire Wire Line - 4500 4300 4500 4600 -Wire Wire Line - 3700 4600 3700 4450 -Connection ~ 2950 4600 -Wire Wire Line - 2950 3350 4150 3350 -Wire Wire Line - 2950 4250 2950 4800 -Wire Wire Line - 3700 3550 4150 3550 -Connection ~ 3700 4600 -Wire Wire Line - 4550 2900 4550 3250 -Wire Wire Line - 3450 3350 3450 3250 -Connection ~ 3450 3350 -Wire Wire Line - 5550 3450 5350 3450 -Wire Wire Line - 5550 4600 5550 4100 -$Comp -L VPLOT8_1 U2 -U 2 1 50CEBA04 -P 5550 3000 -F 0 "U2" H 5400 3100 50 0000 C CNN -F 1 "VPLOT8_1" H 5700 3100 50 0000 C CNN - 2 5550 3000 - 1 0 0 -1 -$EndComp -$Comp -L VPLOT8_1 U2 -U 1 1 50CEBA01 -P 3450 2950 -F 0 "U2" H 3300 3050 50 0000 C CNN -F 1 "VPLOT8_1" H 3600 3050 50 0000 C CNN - 1 3450 2950 - 1 0 0 -1 -$EndComp -$Comp -L PWR_FLAG #FLG01 -U 1 1 50862FAD -P 4550 2900 -F 0 "#FLG01" H 4550 3170 30 0001 C CNN -F 1 "PWR_FLAG" H 4550 3130 30 0000 C CNN - 1 4550 2900 - 1 0 0 -1 -$EndComp -$Comp -L PWR_FLAG #FLG02 -U 1 1 50862FA6 -P 4500 4300 -F 0 "#FLG02" H 4500 4570 30 0001 C CNN -F 1 "PWR_FLAG" H 4500 4530 30 0000 C CNN - 1 4500 4300 - 1 0 0 -1 -$EndComp -$Comp -L R R1 -U 1 1 50862F73 -P 5550 3850 -F 0 "R1" V 5630 3850 50 0000 C CNN -F 1 "1000" V 5550 3850 50 0000 C CNN - 1 5550 3850 - 1 0 0 -1 -$EndComp -$Comp -L PULSE v1 -U 1 1 50862F55 -P 2950 3800 -F 0 "v1" H 2750 3900 60 0000 C CNN -F 1 "PULSE" H 2750 3750 60 0000 C CNN -F 2 "R1" H 2650 3800 60 0000 C CNN - 1 2950 3800 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR03 -U 1 1 50862CF3 -P 2950 4800 -F 0 "#PWR03" H 2950 4800 30 0001 C CNN -F 1 "GND" H 2950 4730 30 0001 C CNN - 1 2950 4800 - 1 0 0 -1 -$EndComp -$Comp -L DC v2 -U 1 1 50862BA3 -P 3700 4000 -F 0 "v2" H 3500 4100 60 0000 C CNN -F 1 "5" H 3500 3950 60 0000 C CNN -F 2 "R1" H 3400 4000 60 0000 C CNN - 1 3700 4000 - 1 0 0 -1 -$EndComp -$Comp -L 7400 U1 -U 3 1 50862B5B -P 4750 3450 -F 0 "U1" H 4750 3500 60 0000 C CNN -F 1 "7400" H 4750 3350 60 0000 C CNN - 3 4750 3450 - 1 0 0 -1 -$EndComp -$EndSCHEMATC |