initial commit

19 files changed, 1408 insertions, 0 deletions

diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/analysis b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/analysis
new file mode 100644
index 0000000..1665db7
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/analysis
@@ -0,0 +1 @@
+.dc  v1 0e-00 100e-03 100e-06
diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1-cache.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1-cache.bak
new file mode 100644
index 0000000..7a3e4b4
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1-cache.bak
@@ -0,0 +1,126 @@
+EESchema-LIBRARY Version 2.3  Date: Thursday 09 May 2013 05:04:50 PM IST
+#encoding utf-8
+#
+# GND
+#
+DEF ~GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 0 30 H I C CNN
+F1 "GND" 0 -70 30 H I C CNN
+DRAW
+P 4 0 1 0  -50 0  0 -50  50 0  -50 0 N
+X GND 1 0 0 0 U 30 30 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# iplot
+#
+DEF iplot U 0 20 Y Y 1 F N
+F0 "U" -150 100 50 H V C CNN
+F1 "iplot" 150 100 50 H V C CNN
+DRAW
+C 0 0 100 0 0 0 N
+X + 1 -250 0 150 R 30 30 1 1 I
+X - 2 250 0 150 L 30 30 1 1 I
+ENDDRAW
+ENDDEF
+#
+# LM741
+#
+DEF LM741 U 0 20 Y Y 1 F N
+F0 "U" 150 150 60 H V C CNN
+F1 "LM741" 150 250 60 H V C CNN
+DRAW
+P 4 0 1 0  -200 200  200 0  -200 -200  -200 200 N
+X ~ 1 0 -400 300 U 40 40 1 1 I
+X - 2 -500 -100 300 R 40 40 1 1 I
+X + 3 -500 100 300 R 40 40 1 1 I
+X V- 4 -100 -400 250 U 40 40 1 1 I
+X ~ 5 100 -400 350 U 40 40 1 1 I
+X ~ 6 500 0 300 L 40 40 1 1 O
+X V+ 7 -100 400 250 D 40 40 1 1 I
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 270 30 H I C CNN
+F1 "PWR_FLAG" 0 230 30 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 20 20 0 0 w
+P 3 0 1 0  0 0  0 100  0 100 N
+P 5 0 1 0  0 100  -100 150  0 200  100 150  0 100 N
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "R" 0 0 50 V V C CNN
+$FPLIST
+ R?
+ SM0603
+ SM0805
+ R?-*
+$ENDFPLIST
+DRAW
+S -40 150 40 -150 0 1 12 N
+X ~ 1 0 250 100 D 60 60 1 1 P
+X ~ 2 0 -250 100 U 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# sine
+#
+DEF sine v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "sine" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -50 0 50 1 1799 0 1 0 N 0 0 -100 0
+A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 0 1 1 I
+X - 2 0 -450 300 U 50 0 1 1 I
+ENDDRAW
+ENDDEF
+#
+# uA741
+#
+DEF uA741 X 0 20 Y Y 1 F N
+F0 "X" 150 150 60 H V C CNN
+F1 "uA741" 150 250 60 H V C CNN
+$FPLIST
+ DIP-8__300
+$ENDFPLIST
+DRAW
+P 4 0 1 0  -200 200  200 0  -200 -200  -200 200 N
+X - 2 -500 -100 300 R 40 40 1 1 I
+X + 3 -500 100 300 R 40 40 1 1 I
+X ~ 6 500 0 300 L 40 40 1 1 O
+ENDDRAW
+ENDDEF
+#
+# vplot8_1
+#
+DEF vplot8_1 U 0 40 Y Y 8 F N
+F0 "U" -150 100 50 H V C CNN
+F1 "vplot8_1" 150 100 50 H V C CNN
+DRAW
+C 0 0 100 0 0 0 N
+X + 1 0 -300 200 U 40 40 1 1 I
+X + 2 0 -300 200 U 40 40 2 1 I
+X + 3 0 -300 200 U 40 40 3 1 I
+X + 4 0 -300 200 U 40 40 4 1 I
+X + 5 0 -300 200 U 40 40 5 1 I
+X + 6 0 -300 200 U 40 40 6 1 I
+X + 7 0 -300 200 U 40 40 7 1 I
+X + 8 0 -300 200 U 40 40 8 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1-cache.lib b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1-cache.lib
new file mode 100644
index 0000000..5b4c901
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1-cache.lib
@@ -0,0 +1,109 @@
+EESchema-LIBRARY Version 2.3  Date: Monday 13 May 2013 10:18:21 AM IST
+#encoding utf-8
+#
+# GND
+#
+DEF ~GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 0 30 H I C CNN
+F1 "GND" 0 -70 30 H I C CNN
+DRAW
+P 4 0 1 0  -50 0  0 -50  50 0  -50 0 N
+X GND 1 0 0 0 U 30 30 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# iplot
+#
+DEF iplot U 0 20 Y Y 1 F N
+F0 "U" -150 100 50 H V C CNN
+F1 "iplot" 150 100 50 H V C CNN
+DRAW
+C 0 0 100 0 0 0 N
+X + 1 -250 0 150 R 30 30 1 1 I
+X - 2 250 0 150 L 30 30 1 1 I
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 270 30 H I C CNN
+F1 "PWR_FLAG" 0 230 30 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 20 20 0 0 w
+P 3 0 1 0  0 0  0 100  0 100 N
+P 5 0 1 0  0 100  -100 150  0 200  100 150  0 100 N
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "R" 0 0 50 V V C CNN
+$FPLIST
+ R?
+ SM0603
+ SM0805
+ R?-*
+$ENDFPLIST
+DRAW
+S -40 150 40 -150 0 1 12 N
+X ~ 1 0 250 100 D 60 60 1 1 P
+X ~ 2 0 -250 100 U 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# sine
+#
+DEF sine v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "sine" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -50 0 50 1 1799 0 1 0 N 0 0 -100 0
+A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 0 1 1 I
+X - 2 0 -450 300 U 50 0 1 1 I
+ENDDRAW
+ENDDEF
+#
+# uA741
+#
+DEF uA741 X 0 20 Y Y 1 F N
+F0 "X" 150 150 60 H V C CNN
+F1 "uA741" 150 250 60 H V C CNN
+$FPLIST
+ DIP-8__300
+$ENDFPLIST
+DRAW
+P 4 0 1 0  -200 200  200 0  -200 -200  -200 200 N
+X - 2 -500 -100 300 R 40 40 1 1 I
+X + 3 -500 100 300 R 40 40 1 1 I
+X ~ 6 500 0 300 L 40 40 1 1 O
+ENDDRAW
+ENDDEF
+#
+# vplot8_1
+#
+DEF vplot8_1 U 0 40 Y Y 8 F N
+F0 "U" -150 100 50 H V C CNN
+F1 "vplot8_1" 150 100 50 H V C CNN
+DRAW
+C 0 0 100 0 0 0 N
+X + 1 0 -300 200 U 40 40 1 1 I
+X + 2 0 -300 200 U 40 40 2 1 I
+X + 3 0 -300 200 U 40 40 3 1 I
+X + 4 0 -300 200 U 40 40 4 1 I
+X + 5 0 -300 200 U 40 40 5 1 I
+X + 6 0 -300 200 U 40 40 6 1 I
+X + 7 0 -300 200 U 40 40 7 1 I
+X + 8 0 -300 200 U 40 40 8 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.bak
new file mode 100644
index 0000000..abf9a53
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.bak
@@ -0,0 +1,181 @@
+EESchema Schematic File Version 2  date Thursday 09 May 2013 05:04:50 PM IST
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:analogSpice
+LIBS:analogXSpice
+LIBS:convergenceAidSpice
+LIBS:converterSpice
+LIBS:digitalSpice
+LIBS:digitalXSpice
+LIBS:linearSpice
+LIBS:measurementSpice
+LIBS:portSpice
+LIBS:sourcesSpice
+LIBS:example_5.1-cache
+EELAYER 25  0
+EELAYER END
+$Descr A4 11700 8267
+encoding utf-8
+Sheet 1 1
+Title ""
+Date "9 may 2013"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L LM741 U?
+U 1 1 518B89AE
+P 8800 3550
+F 0 "U?" H 8950 3700 60  0000 C CNN
+F 1 "LM741" H 8950 3800 60  0000 C CNN
+	1    8800 3550
+	1    0    0    -1  
+$EndComp
+$Comp
+L UA741 X?
+U 1 1 518B899E
+P 9050 2450
+F 0 "X?" H 9200 2600 60  0000 C CNN
+F 1 "UA741" H 9200 2700 60  0000 C CNN
+	1    9050 2450
+	1    0    0    -1  
+$EndComp
+$Comp
+L SINE v1
+U 1 1 516F84E1
+P 4050 3650
+F 0 "v1" H 3850 3750 60  0000 C CNN
+F 1 "SINE" H 3850 3600 60  0000 C CNN
+F 2 "R1" H 3750 3650 60  0000 C CNN
+	1    4050 3650
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	7150 3300 6350 3300
+Wire Wire Line
+	5300 2400 5300 3200
+Wire Wire Line
+	4750 3200 4650 3200
+Wire Wire Line
+	5350 4200 5350 3400
+Connection ~ 5300 3200
+Wire Wire Line
+	5350 3200 5250 3200
+Wire Wire Line
+	4150 3200 4050 3200
+Connection ~ 5350 4100
+Connection ~ 6350 3300
+Connection ~ 7050 3300
+Wire Wire Line
+	5350 4100 4050 4100
+Wire Wire Line
+	6900 2400 7050 2400
+Wire Wire Line
+	7050 2400 7050 3300
+Wire Wire Line
+	6400 2400 5800 2400
+$Comp
+L VPLOT8_1 U3
+U 1 1 516D117B
+P 7050 3600
+F 0 "U3" H 6900 3700 50  0000 C CNN
+F 1 "VPLOT8_1" H 7200 3700 50  0000 C CNN
+	1    7050 3600
+	-1   0    0    1   
+$EndComp
+$Comp
+L PWR_FLAG #FLG1
+U 1 1 516D1102
+P 5300 3200
+F 0 "#FLG1" H 5300 3470 30  0001 C CNN
+F 1 "PWR_FLAG" H 5300 3430 30  0000 C CNN
+	1    5300 3200
+	-1   0    0    1   
+$EndComp
+$Comp
+L IPLOT U1
+U 1 1 516D1019
+P 5000 3200
+F 0 "U1" H 4850 3300 50  0000 C CNN
+F 1 "IPLOT" H 5150 3300 50  0000 C CNN
+	1    5000 3200
+	1    0    0    -1  
+$EndComp
+$Comp
+L IPLOT U2
+U 1 1 516D0FEC
+P 5550 2400
+F 0 "U2" H 5400 2500 50  0000 C CNN
+F 1 "IPLOT" H 5700 2500 50  0000 C CNN
+	1    5550 2400
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R2
+U 1 1 516D0FE2
+P 6650 2400
+F 0 "R2" V 6730 2400 50  0000 C CNN
+F 1 "10000" V 6650 2400 50  0000 C CNN
+	1    6650 2400
+	0    1    1    0   
+$EndComp
+$Comp
+L GND #PWR1
+U 1 1 516D0F6B
+P 5350 4200
+F 0 "#PWR1" H 5350 4200 30  0001 C CNN
+F 1 "GND" H 5350 4130 30  0001 C CNN
+	1    5350 4200
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R1
+U 1 1 516D0F10
+P 4400 3200
+F 0 "R1" V 4480 3200 50  0000 C CNN
+F 1 "1000" V 4400 3200 50  0000 C CNN
+	1    4400 3200
+	0    1    1    0   
+$EndComp
+$Comp
+L UA741 X1
+U 1 1 516D0E60
+P 5850 3300
+F 0 "X1" H 6000 3450 60  0000 C CNN
+F 1 "UA741" H 6000 3550 60  0000 C CNN
+	1    5850 3300
+	1    0    0    1   
+$EndComp
+$EndSCHEMATC
diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.cir
new file mode 100644
index 0000000..d11b7e1
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.cir
@@ -0,0 +1,24 @@
+* EESchema Netlist Version 1.1 (Spice format) creation date: Thursday 18 April 2013 10:42:46 AM IST
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+*Sheet Name:/
+v1  4 0 PULSE		
+v2  11 0 10V		
+U3  8 3 VPLOT8_1		
+R5  13 3 10000		
+R4  0 13 10000		
+R3  1 11 10000		
+U5  8 2 IPLOT		
+Q2  1 1 2 NPN		
+X2  1 13 3 UA741		
+U4  10 8 IPLOT		
+Q1  10 0 9 NPN		
+U1  6 7 IPLOT		
+U2  7 9 IPLOT		
+R2  8 5 10000		
+R1  6 4 1000		
+X1  7 0 5 UA741		
+
+.end
diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.cir.ckt
new file mode 100644
index 0000000..db0e45e
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.cir.ckt
@@ -0,0 +1,16 @@
+* eeschema netlist version 1.1 (spice format) creation date: tuesday 16 april 2013 02:25:09 pm ist
+.include ua741.sub
+
+* Plotting option vplot8_1
+V_u1 6 5 0
+V_u2 5 4 0
+r2  1 4 100000
+v1  3 0 100m
+r1  6 3 1000
+x1  5 0 1 ua741
+
+.dc  v1 0e-00 100e-03 100e-06
+.plot v(1) 
+.plot i(V_u1)
+.plot i(V_u2)
+.end
diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.cir.out
new file mode 100644
index 0000000..d01be76
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.cir.out
@@ -0,0 +1,21 @@
+* eeschema netlist version 1.1 (spice format) creation date: tuesday 16 april 2013 02:25:09 pm ist
+.include ua741.sub
+
+* Plotting option vplot8_1
+V_u1 6 5 0
+V_u2 5 4 0
+r2  1 4 100000
+v1  3 0 100m
+r1  6 3 1000
+x1  5 0 1 ua741
+
+.dc  v1 0e-00 100e-03 100e-06
+
+* Control Statements 
+.control
+run
+plot v(1) 
+plot i(V_u1)
+plot i(V_u2)
+.endc
+.end
diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.net b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.net
new file mode 100644
index 0000000..6696e60
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.net
@@ -0,0 +1,76 @@
+# EESchema Netlist Version 1.1 created  Thursday 18 April 2013 11:00:24 AM IST
+(
+ ( /516F84E1 R1  v1 SINE {Lib=SINE}
+  (    1 N-000005 )
+  (    2 GND )
+ )
+ ( /516D117B $noname  U3 VPLOT8_1 {Lib=VPLOT8_1}
+  (    1 N-000004 )
+ )
+ ( /516D1019 $noname  U1 IPLOT {Lib=IPLOT}
+  (    1 N-000002 )
+  (    2 N-000003 )
+ )
+ ( /516D0FEC $noname  U2 IPLOT {Lib=IPLOT}
+  (    1 N-000003 )
+  (    2 N-000001 )
+ )
+ ( /516D0FE2 $noname  R2 10000 {Lib=R}
+  (    1 N-000004 )
+  (    2 N-000001 )
+ )
+ ( /516D0F10 $noname  R1 1000 {Lib=R}
+  (    1 N-000002 )
+  (    2 N-000005 )
+ )
+ ( /516D0E60 $noname  X1 UA741 {Lib=UA741}
+  (    2 N-000003 )
+  (    3 GND )
+  (    6 N-000004 )
+ )
+)
+*
+{ Allowed footprints by component:
+$component v1
+ 1_pin
+$endlist
+$component R2
+ R?
+ SM0603
+ SM0805
+ R?-*
+$endlist
+$component R1
+ R?
+ SM0603
+ SM0805
+ R?-*
+$endlist
+$component X1
+ DIP-8__300
+$endlist
+$endfootprintlist
+}
+{ Pin List by Nets
+Net 1 "" ""
+ R2 2
+ U2 2
+Net 2 "" ""
+ R1 1
+ U1 1
+Net 3 "" ""
+ X1 2
+ U2 1
+ U1 2
+Net 4 "" ""
+ U3 1
+ R2 1
+ X1 6
+Net 5 "" ""
+ v1 1
+ R1 2
+Net 6 "GND" "GND"
+ X1 3
+ v1 2
+}
+#End
diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.pro
new file mode 100644
index 0000000..2d33bde
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.pro
@@ -0,0 +1,74 @@
+update=Tuesday 16 April 2013 02:06:21 PM IST
+last_client=eeschema
+[eeschema]
+version=1
+LibDir=
+NetFmt=1
+HPGLSpd=20
+HPGLDm=15
+HPGLNum=1
+offX_A4=0
+offY_A4=0
+offX_A3=0
+offY_A3=0
+offX_A2=0
+offY_A2=0
+offX_A1=0
+offY_A1=0
+offX_A0=0
+offY_A0=0
+offX_A=0
+offY_A=0
+offX_B=0
+offY_B=0
+offX_C=0
+offY_C=0
+offX_D=0
+offY_D=0
+offX_E=0
+offY_E=0
+RptD_X=0
+RptD_Y=100
+RptLab=1
+LabSize=60
+[eeschema/libraries]
+LibName1=power
+LibName2=device
+LibName3=transistors
+LibName4=conn
+LibName5=linear
+LibName6=regul
+LibName7=74xx
+LibName8=cmos4000
+LibName9=adc-dac
+LibName10=memory
+LibName11=xilinx
+LibName12=special
+LibName13=microcontrollers
+LibName14=dsp
+LibName15=microchip
+LibName16=analog_switches
+LibName17=motorola
+LibName18=texas
+LibName19=intel
+LibName20=audio
+LibName21=interface
+LibName22=digital-audio
+LibName23=philips
+LibName24=display
+LibName25=cypress
+LibName26=siliconi
+LibName27=opto
+LibName28=atmel
+LibName29=contrib
+LibName30=valves
+LibName31=/home/holy/OSCAD/library/analogSpice
+LibName32=/home/holy/OSCAD/library/analogXSpice
+LibName33=/home/holy/OSCAD/library/convergenceAidSpice
+LibName34=/home/holy/OSCAD/library/converterSpice
+LibName35=/home/holy/OSCAD/library/digitalSpice
+LibName36=/home/holy/OSCAD/library/digitalXSpice
+LibName37=/home/holy/OSCAD/library/linearSpice
+LibName38=/home/holy/OSCAD/library/measurementSpice
+LibName39=/home/holy/OSCAD/library/portSpice
+LibName40=/home/holy/OSCAD/library/sourcesSpice
diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.proj b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.proj
new file mode 100644
index 0000000..fb6ad90
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.proj
@@ -0,0 +1 @@
+schematicFile example_5.1.sch
diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.sch
new file mode 100644
index 0000000..9267154
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/example_5.1.sch
@@ -0,0 +1,163 @@
+EESchema Schematic File Version 2  date Monday 13 May 2013 10:18:21 AM IST
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
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+LIBS:motorola
+LIBS:texas
+LIBS:intel
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+LIBS:interface
+LIBS:digital-audio
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+LIBS:digitalXSpice
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diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741-cache.lib b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741-cache.lib
new file mode 100644
index 0000000..e9ec641
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741-cache.lib
@@ -0,0 +1,63 @@
+EESchema-LIBRARY Version 2.3  Date: Tuesday 16 April 2013 02:55:26 PM IST
+#encoding utf-8
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+# C
+#
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+F1 "C" 50 -100 50 H V L CNN
+$FPLIST
+ SM*
+ C?
+ C1-1
+$ENDFPLIST
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+P 2 0 1 10  -100 -30  100 -30 N
+P 2 0 1 10  -100 30  100 30 N
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+X ~ 2 0 -200 170 U 40 40 1 1 P
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+F1 "GND" 0 -70 30 H I C CNN
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+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 270 30 H I C CNN
+F1 "PWR_FLAG" 0 230 30 H V C CNN
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+X pwr 1 0 0 0 U 20 20 0 0 w
+P 3 0 1 0  0 0  0 100  0 100 N
+P 5 0 1 0  0 100  -100 150  0 200  100 150  0 100 N
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+ENDDEF
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+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "R" 0 0 50 V V C CNN
+$FPLIST
+ R?
+ SM0603
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+S -40 150 40 -150 0 1 12 N
+X ~ 1 0 250 100 D 60 60 1 1 P
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+ENDDEF
+#
+#End Library
diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.bak b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.bak
new file mode 100644
index 0000000..6be9280
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.bak
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+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:analogSpice
+LIBS:converterSpice
+LIBS:digitalSpice
+LIBS:linearSpice
+LIBS:measurementSpice
+LIBS:portSpice
+LIBS:sourcesSpice
+LIBS:ua741-cache
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+EELAYER END
+$Descr A4 11700 8267
+encoding utf-8
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diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.cir b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.cir
new file mode 100644
index 0000000..de79742
--- /dev/null
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+* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:16:58 AM IST
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
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+*Sheet Name:/
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+Rin1  7 6 2e6		
+
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diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.cir.ckt
new file mode 100644
index 0000000..3661a9a
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.cir.ckt
@@ -0,0 +1,9 @@
+* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist
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diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.cir.out b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.cir.out
new file mode 100644
index 0000000..3661a9a
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.cir.out
@@ -0,0 +1,9 @@
+* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist
+
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diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.pro b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.pro
new file mode 100644
index 0000000..46bdf8d
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.pro
@@ -0,0 +1,82 @@
+update=Tuesday 16 April 2013 02:56:39 PM IST
+last_client=eeschema
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diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.sch b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.sch
new file mode 100644
index 0000000..7dfc5e1
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.sch
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+EESchema Schematic File Version 2  date Wednesday 19 December 2012 10:15:16 AM IST
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+LIBS:transistors
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+LIBS:measurementSpice
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+LIBS:sourcesSpice
+LIBS:analogXSpice
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+EELAYER END
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+encoding utf-8
+Sheet 1 1
+Title ""
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+P 3700 3400
+F 0 "#PWR02" H 3700 3400 30  0001 C CNN
+F 1 "GND" H 3700 3330 30  0001 C CNN
+	1    3700 3400
+	1    0    0    -1  
+$EndComp
+$Comp
+L VCVS Ein1
+U 1 1 50813D7C
+P 3650 2850
+F 0 "Ein1" H 3450 2950 50  0000 C CNN
+F 1 "100e3" H 3450 2800 50  0000 C CNN
+	1    3650 2850
+	0    1    1    0   
+$EndComp
+$Comp
+L R Rin1
+U 1 1 50813C57
+P 3000 2850
+F 0 "Rin1" V 3080 2850 50  0000 C CNN
+F 1 "2e6" V 3000 2850 50  0000 C CNN
+	1    3000 2850
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.sub b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.sub
new file mode 100644
index 0000000..1edba9f
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_5/example_5.1/ua741.sub
@@ -0,0 +1,11 @@
+* Subcircuit ua741
+.subckt ua741 6 7 3 
+* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist
+rout1  3 2 75
+eout1  2 0 1 0 1
+cbw1  1 0 31.85e-9
+rbw1  1 4 0.5e6
+ein1  4 0 7 6 100e3
+rin1  7 6 2e6
+
+.ends ua741
\ No newline at end of file