Subject: Changing all content and name of directory and file to FreeEDA

Description: The content of file,name of directory and file has been
changed in the below format.

1. Oscad to FreeEDA
2. OSCAD to FreeEDA
3. oscad to freeeda

12 files changed, 0 insertions, 819 deletions

diff --git a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/1n4007.lib b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/1n4007.lib
deleted file mode 100644
index 89d421d..0000000
--- a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/1n4007.lib
+++ /dev/null
@@ -1,2 +0,0 @@
-.model 1n4007 D( IS=7.02767e-09 RS=0.0341512 N=1.80803 EG=1.05743 XTI=5 BV=1000 IBV=5e-08 CJO=1E-11 
-+VJ=0.7 M=0.5 FC=0.5 TT=1E-07 KF=0 AF=1 )
diff --git a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/analysis b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/analysis
deleted file mode 100644
index f74e3c8..0000000
--- a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/analysis
+++ /dev/null
@@ -1 +0,0 @@
-.dc  v1 0e-00 10e-00 1e-00
diff --git a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/cd4007.txt b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/cd4007.txt
deleted file mode 100644
index 0552575..0000000
--- a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/cd4007.txt
+++ /dev/null
@@ -1,22 +0,0 @@
-* CD4007 NMOS and PMOS transistor SPICE models
-
-* Typical - Typical Condition
-
-.model mos_n NMOS 
-+ Level=1    Gamma= 0   Xj=0
-+ Tox=1200n  Phi=.6     Rs=0      Kp=111u  Vto=1.4    Lambda=0.01
-+ Rd=0       Cbd=2.0p   Cbs=2.0p  Pb=.8    Cgso=0.1p
-+ Cgdo=0.1p  Is=16.64p  N=1
-
-*The default W and L is 30 and 10 um respectively and AD and AS
-*should not be included.
-
-
-.model mos_p PMOS 
-+ Level=1    Gamma= 0   Xj=0
-+ Tox=1200n  Phi=.6     Rs=0      Kp=1u  Vto=-1.2   Lambda=0.04
-+ Rd=0       Cbd=4.0p   Cbs=4.0p  Pb=.8   Cgso=0.2p
-+ Cgdo=0.2p  Is=16.64p  N=1
-
-*The default W and L is 60 and 10 um respectively and AD and AS
-*should not be included.
diff --git a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5-cache.bak b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5-cache.bak
deleted file mode 100644
index 5cb1eee..0000000
--- a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5-cache.bak
+++ /dev/null
@@ -1,110 +0,0 @@
-EESchema-LIBRARY Version 2.3  Date: Thursday 16 May 2013 11:39:19 AM IST
-#encoding utf-8
-#
-# dc
-#
-DEF dc v 0 40 Y Y 1 F N
-F0 "v" -200 100 60 H V C CNN
-F1 "dc" -200 -50 60 H V C CNN
-F2 "R1" -300 0 60 H V C CNN
-$FPLIST
- 1_pin
-$ENDFPLIST
-DRAW
-C 0 0 150 0 1 0 N
-X + 1 0 450 300 D 50 50 1 1 P
-X - 2 0 -450 300 U 50 50 1 1 P
-ENDDRAW
-ENDDEF
-#
-# GND
-#
-DEF ~GND #PWR 0 0 Y Y 1 F P
-F0 "#PWR" 0 0 30 H I C CNN
-F1 "GND" 0 -70 30 H I C CNN
-DRAW
-P 4 0 1 0  -50 0  0 -50  50 0  -50 0 N
-X GND 1 0 0 0 U 30 30 1 1 W N
-ENDDRAW
-ENDDEF
-#
-# iplot
-#
-DEF iplot U 0 20 Y Y 1 F N
-F0 "U" -150 100 50 H V C CNN
-F1 "iplot" 150 100 50 H V C CNN
-DRAW
-C 0 0 100 0 0 0 N
-X + 1 -250 0 150 R 30 30 1 1 I
-X - 2 250 0 150 L 30 30 1 1 I
-ENDDRAW
-ENDDEF
-#
-# MOS_N
-#
-DEF MOS_N M 0 0 N Y 1 F N
-F0 "M" 10 170 60 H V R CNN
-F1 "MOS_N" 10 -150 60 H V R CNN
-ALIAS MOSFET_N
-DRAW
-P 2 0 1 8  -50 -100  -50 100 N
-P 2 0 1 10  0 -150  0 150 N
-P 2 0 1 0  100 -100  0 -100 N
-P 2 0 1 0  100 100  0 100 N
-P 3 0 1 8  100 -100  100 0  50 0 N
-P 5 0 1 8  50 30  50 -30  0 0  50 30  50 30 N
-X D D 100 200 100 D 40 40 1 1 P
-X G G -200 0 150 R 40 40 1 1 I
-X S S 100 -200 100 U 40 40 1 1 P
-ENDDRAW
-ENDDEF
-#
-# PWR_FLAG
-#
-DEF PWR_FLAG #FLG 0 0 N N 1 F P
-F0 "#FLG" 0 270 30 H I C CNN
-F1 "PWR_FLAG" 0 230 30 H V C CNN
-DRAW
-X pwr 1 0 0 0 U 20 20 0 0 w
-P 3 0 1 0  0 0  0 100  0 100 N
-P 5 0 1 0  0 100  -100 150  0 200  100 150  0 100 N
-ENDDRAW
-ENDDEF
-#
-# R
-#
-DEF R R 0 0 N Y 1 F N
-F0 "R" 80 0 50 V V C CNN
-F1 "R" 0 0 50 V V C CNN
-$FPLIST
- R?
- SM0603
- SM0805
- R?-*
-$ENDFPLIST
-DRAW
-S -40 150 40 -150 0 1 12 N
-X ~ 1 0 250 100 D 60 60 1 1 P
-X ~ 2 0 -250 100 U 60 60 1 1 P
-ENDDRAW
-ENDDEF
-#
-# vplot8_1
-#
-DEF vplot8_1 U 0 40 Y Y 8 F N
-F0 "U" -150 100 50 H V C CNN
-F1 "vplot8_1" 150 100 50 H V C CNN
-DRAW
-C 0 0 100 0 0 0 N
-X + 1 0 -300 200 U 40 40 1 1 I
-X + 2 0 -300 200 U 40 40 2 1 I
-X + 3 0 -300 200 U 40 40 3 1 I
-X + 4 0 -300 200 U 40 40 4 1 I
-X + 5 0 -300 200 U 40 40 5 1 I
-X + 6 0 -300 200 U 40 40 6 1 I
-X + 7 0 -300 200 U 40 40 7 1 I
-X + 8 0 -300 200 U 40 40 8 1 I
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5-cache.lib b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5-cache.lib
deleted file mode 100644
index df97081..0000000
--- a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5-cache.lib
+++ /dev/null
@@ -1,110 +0,0 @@
-EESchema-LIBRARY Version 2.3  Date: Thursday 16 May 2013 11:43:16 AM IST
-#encoding utf-8
-#
-# dc
-#
-DEF dc v 0 40 Y Y 1 F N
-F0 "v" -200 100 60 H V C CNN
-F1 "dc" -200 -50 60 H V C CNN
-F2 "R1" -300 0 60 H V C CNN
-$FPLIST
- 1_pin
-$ENDFPLIST
-DRAW
-C 0 0 150 0 1 0 N
-X + 1 0 450 300 D 50 50 1 1 P
-X - 2 0 -450 300 U 50 50 1 1 P
-ENDDRAW
-ENDDEF
-#
-# GND
-#
-DEF ~GND #PWR 0 0 Y Y 1 F P
-F0 "#PWR" 0 0 30 H I C CNN
-F1 "GND" 0 -70 30 H I C CNN
-DRAW
-P 4 0 1 0  -50 0  0 -50  50 0  -50 0 N
-X GND 1 0 0 0 U 30 30 1 1 W N
-ENDDRAW
-ENDDEF
-#
-# iplot
-#
-DEF iplot U 0 20 Y Y 1 F N
-F0 "U" -150 100 50 H V C CNN
-F1 "iplot" 150 100 50 H V C CNN
-DRAW
-C 0 0 100 0 0 0 N
-X + 1 -250 0 150 R 30 30 1 1 I
-X - 2 250 0 150 L 30 30 1 1 I
-ENDDRAW
-ENDDEF
-#
-# MOS_N
-#
-DEF MOS_N M 0 0 N Y 1 F N
-F0 "M" 10 170 60 H V R CNN
-F1 "MOS_N" 10 -150 60 H V R CNN
-ALIAS MOSFET_N
-DRAW
-P 2 0 1 8  -50 -100  -50 100 N
-P 2 0 1 10  0 -150  0 150 N
-P 2 0 1 0  100 -100  0 -100 N
-P 2 0 1 0  100 100  0 100 N
-P 3 0 1 8  100 -100  100 0  50 0 N
-P 5 0 1 8  50 30  50 -30  0 0  50 30  50 30 N
-X D D 100 200 100 D 40 40 1 1 P
-X G G -200 0 150 R 40 40 1 1 I
-X S S 100 -200 100 U 40 40 1 1 P
-ENDDRAW
-ENDDEF
-#
-# PWR_FLAG
-#
-DEF PWR_FLAG #FLG 0 0 N N 1 F P
-F0 "#FLG" 0 270 30 H I C CNN
-F1 "PWR_FLAG" 0 230 30 H V C CNN
-DRAW
-X pwr 1 0 0 0 U 20 20 0 0 w
-P 3 0 1 0  0 0  0 100  0 100 N
-P 5 0 1 0  0 100  -100 150  0 200  100 150  0 100 N
-ENDDRAW
-ENDDEF
-#
-# R
-#
-DEF R R 0 0 N Y 1 F N
-F0 "R" 80 0 50 V V C CNN
-F1 "R" 0 0 50 V V C CNN
-$FPLIST
- R?
- SM0603
- SM0805
- R?-*
-$ENDFPLIST
-DRAW
-S -40 150 40 -150 0 1 12 N
-X ~ 1 0 250 100 D 60 60 1 1 P
-X ~ 2 0 -250 100 U 60 60 1 1 P
-ENDDRAW
-ENDDEF
-#
-# vplot8_1
-#
-DEF vplot8_1 U 0 40 Y Y 8 F N
-F0 "U" -150 100 50 H V C CNN
-F1 "vplot8_1" 150 100 50 H V C CNN
-DRAW
-C 0 0 100 0 0 0 N
-X + 1 0 -300 200 U 40 40 1 1 I
-X + 2 0 -300 200 U 40 40 2 1 I
-X + 3 0 -300 200 U 40 40 3 1 I
-X + 4 0 -300 200 U 40 40 4 1 I
-X + 5 0 -300 200 U 40 40 5 1 I
-X + 6 0 -300 200 U 40 40 6 1 I
-X + 7 0 -300 200 U 40 40 7 1 I
-X + 8 0 -300 200 U 40 40 8 1 I
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.bak b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.bak
deleted file mode 100644
index c4bf9b0..0000000
--- a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.bak
+++ /dev/null
@@ -1,214 +0,0 @@
-EESchema Schematic File Version 2  date Thursday 16 May 2013 11:39:19 AM IST
-LIBS:power
-LIBS:device
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:special
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
-LIBS:analogSpice
-LIBS:analogXSpice
-LIBS:convergenceAidSpice
-LIBS:converterSpice
-LIBS:digitalSpice
-LIBS:digitalXSpice
-LIBS:linearSpice
-LIBS:measurementSpice
-LIBS:portSpice
-LIBS:sourcesSpice
-LIBS:example_4.5-cache
-EELAYER 25  0
-EELAYER END
-$Descr A4 11700 8267
-encoding utf-8
-Sheet 1 1
-Title ""
-Date "16 may 2013"
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-Connection ~ 6600 3650
-$Comp
-L VPLOT8_1 U4
-U 2 1 519477A9
-P 6900 3650
-F 0 "U4" H 6750 3750 50  0000 C CNN
-F 1 "VPLOT8_1" H 7050 3750 50  0000 C CNN
-	2    6900 3650
-	0    1    1    0   
-$EndComp
-Wire Wire Line
-	6600 4350 6600 4700
-Wire Wire Line
-	5800 5500 5800 5550
-Wire Wire Line
-	6600 2700 6600 3000
-Connection ~ 5800 5500
-Wire Wire Line
-	5000 2850 5000 850 
-Connection ~ 5700 850 
-Wire Wire Line
-	5000 850  6600 850 
-Connection ~ 5700 3200
-Wire Wire Line
-	5700 5500 5700 5200
-Wire Wire Line
-	5700 1200 5700 850 
-Wire Wire Line
-	6600 850  6600 1200
-Wire Wire Line
-	6600 5200 6600 5500
-Wire Wire Line
-	6300 3200 5700 3200
-Connection ~ 5700 3200
-Connection ~ 6600 2850
-Connection ~ 6600 850 
-Connection ~ 6600 5500
-Wire Wire Line
-	5700 4700 5700 1700
-Wire Wire Line
-	6600 5500 5000 5500
-Connection ~ 5700 5500
-Wire Wire Line
-	5000 5500 5000 3750
-Wire Wire Line
-	6600 1700 6600 2200
-Wire Wire Line
-	6600 3400 6600 3800
-$Comp
-L IPLOT U2
-U 1 1 51947793
-P 6600 4050
-F 0 "U2" H 6450 4150 50  0000 C CNN
-F 1 "IPLOT" H 6750 4150 50  0000 C CNN
-	1    6600 4050
-	0    1    1    0   
-$EndComp
-$Comp
-L IPLOT U1
-U 1 1 518B75C0
-P 6600 2450
-F 0 "U1" H 6450 2550 50  0000 C CNN
-F 1 "IPLOT" H 6750 2550 50  0000 C CNN
-	1    6600 2450
-	0    1    1    0   
-$EndComp
-$Comp
-L VPLOT8_1 U4
-U 1 1 518B74B3
-P 6000 3200
-F 0 "U4" H 5850 3300 50  0000 C CNN
-F 1 "VPLOT8_1" H 6150 3300 50  0000 C CNN
-	1    6000 3200
-	0    1    1    0   
-$EndComp
-$Comp
-L GND #PWR01
-U 1 1 517A3B91
-P 5800 5550
-F 0 "#PWR01" H 5800 5550 30  0001 C CNN
-F 1 "GND" H 5800 5480 30  0001 C CNN
-	1    5800 5550
-	1    0    0    -1  
-$EndComp
-$Comp
-L PWR_FLAG #FLG02
-U 1 1 517A3B8C
-P 5800 5500
-F 0 "#FLG02" H 5800 5770 30  0001 C CNN
-F 1 "PWR_FLAG" H 5800 5730 30  0000 C CNN
-	1    5800 5500
-	1    0    0    -1  
-$EndComp
-$Comp
-L DC v1
-U 1 1 517A3ABD
-P 5000 3300
-F 0 "v1" H 4800 3400 60  0000 C CNN
-F 1 "10" H 4800 3250 60  0000 C CNN
-F 2 "R1" H 4700 3300 60  0000 C CNN
-	1    5000 3300
-	1    0    0    -1  
-$EndComp
-$Comp
-L VPLOT8_1 U3
-U 1 1 516BA47D
-P 6900 2850
-F 0 "U3" H 6750 2950 50  0000 C CNN
-F 1 "VPLOT8_1" H 7050 2950 50  0000 C CNN
-	1    6900 2850
-	0    1    1    0   
-$EndComp
-$Comp
-L R R2
-U 1 1 5166F1C0
-P 5700 4950
-F 0 "R2" V 5780 4950 50  0000 C CNN
-F 1 "10M" V 5700 4950 50  0000 C CNN
-	1    5700 4950
-	1    0    0    -1  
-$EndComp
-$Comp
-L R R1
-U 1 1 5166F1AE
-P 5700 1450
-F 0 "R1" V 5780 1450 50  0000 C CNN
-F 1 "10M" V 5700 1450 50  0000 C CNN
-	1    5700 1450
-	1    0    0    -1  
-$EndComp
-$Comp
-L R R4
-U 1 1 5166F187
-P 6600 4950
-F 0 "R4" V 6680 4950 50  0000 C CNN
-F 1 "6k" V 6600 4950 50  0000 C CNN
-	1    6600 4950
-	1    0    0    -1  
-$EndComp
-$Comp
-L R R3
-U 1 1 5166F163
-P 6600 1450
-F 0 "R3" V 6680 1450 50  0000 C CNN
-F 1 "6k" V 6600 1450 50  0000 C CNN
-	1    6600 1450
-	1    0    0    -1  
-$EndComp
-$Comp
-L MOS_N M1
-U 1 1 5166F12C
-P 6500 3200
-F 0 "M1" H 6510 3370 60  0000 R CNN
-F 1 "MOS_N" H 6510 3050 60  0000 R CNN
-	1    6500 3200
-	1    0    0    -1  
-$EndComp
-$EndSCHEMATC
diff --git a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.cir b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.cir
deleted file mode 100644
index 4a904e0..0000000
--- a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.cir
+++ /dev/null
@@ -1,18 +0,0 @@
-* EESchema Netlist Version 1.1 (Spice format) creation date: Thursday 16 May 2013 11:43:12 AM IST
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-*Sheet Name:/
-U4  6 7 VPLOT8_1		
-U2  7 4 IPLOT		
-U1  5 1 IPLOT		
-v1  3 0 10		
-U3  1 VPLOT8_1		
-R2  6 0 10M		
-R1  3 6 10M		
-R4  4 0 6k		
-R3  3 5 6k		
-M1  1 6 7 MOS_N		
-
-.end
diff --git a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.cir.ckt
deleted file mode 100644
index 68ce4e1..0000000
--- a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.cir.ckt
+++ /dev/null
@@ -1,19 +0,0 @@
-* eeschema netlist version 1.1 (spice format) creation date: thursday 16 may 2013 11:43:12 am ist
-
-* Plotting option vplot8_1
-V_u2 7 4 0
-V_u1 5 1 0
-v1  3 0 10
-* Plotting option vplot8_1
-r2  6 0 10m
-r1  3 6 10m
-r4  4 0 6k
-r3  3 5 6k
-m1  1 6 7 mos_n
-
-.dc  v1 0e-00 10e-00 1e-00
-.plot v(6) v(7) 
-.plot i(V_u2)
-.plot i(V_u1)
-.plot v(1) 
-.end
diff --git a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.cir.out b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.cir.out
deleted file mode 100644
index b363435..0000000
--- a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.cir.out
+++ /dev/null
@@ -1,24 +0,0 @@
-* eeschema netlist version 1.1 (spice format) creation date: thursday 16 may 2013 11:43:12 am ist
-
-* Plotting option vplot8_1
-V_u2 7 4 0
-V_u1 5 1 0
-v1  3 0 10
-* Plotting option vplot8_1
-r2  6 0 10m
-r1  3 6 10m
-r4  4 0 6k
-r3  3 5 6k
-m1  1 6 7 mos_n
-
-.dc  v1 0e-00 10e-00 1e-00
-
-* Control Statements 
-.control
-run
-plot v(6) v(7) 
-plot i(V_u2)
-plot i(V_u1)
-plot v(1) 
-.endc
-.end
diff --git a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.pro b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.pro
deleted file mode 100644
index 2585a32..0000000
--- a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.pro
+++ /dev/null
@@ -1,84 +0,0 @@
-update=Tuesday 07 May 2013 02:38:55 PM IST
-last_client=eeschema
-[eeschema]
-version=1
-LibDir=
-NetFmt=1
-HPGLSpd=20
-HPGLDm=15
-HPGLNum=1
-offX_A4=0
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-RptD_X=0
-RptD_Y=100
-RptLab=1
-LabSize=60
-[eeschema/libraries]
-LibName1=power
-LibName2=device
-LibName3=transistors
-LibName4=conn
-LibName5=linear
-LibName6=regul
-LibName7=74xx
-LibName8=cmos4000
-LibName9=adc-dac
-LibName10=memory
-LibName11=xilinx
-LibName12=special
-LibName13=microcontrollers
-LibName14=dsp
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-LibName17=motorola
-LibName18=texas
-LibName19=intel
-LibName20=audio
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-LibName23=philips
-LibName24=display
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-LibName29=contrib
-LibName30=valves
-LibName31=/home/ambikeshwar/OSCAD/library/analogSpice
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-LibName33=/home/ambikeshwar/OSCAD/library/convergenceAidSpice
-LibName34=/home/ambikeshwar/OSCAD/library/converterSpice
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-LibName40=/home/ambikeshwar/OSCAD/library/sourcesSpice
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-LibName48=/home/holy/OSCAD/library/measurementSpice
-LibName49=/home/holy/OSCAD/library/portSpice
-LibName50=/home/holy/OSCAD/library/sourcesSpice
diff --git a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.proj b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.proj
deleted file mode 100644
index 2320ec1..0000000
--- a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.proj
+++ /dev/null
@@ -1 +0,0 @@
-schematicFile example_4.5.sch
diff --git a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.sch b/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.sch
deleted file mode 100644
index a1406f4..0000000
--- a/OSCAD/Examples/sedra_smith/chapter_4/example_4.5/example_4.5.sch
+++ /dev/null
@@ -1,214 +0,0 @@
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-LIBS:digitalXSpice
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