initial commit

11 files changed, 619 insertions, 0 deletions

diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/analysis b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/analysis
new file mode 100644
index 0000000..f481193
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/analysis
@@ -0,0 +1 @@
+.dc v1 0e-00 5e-00 50e-03
diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/diode.lib b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/diode.lib
new file mode 100644
index 0000000..f4b7c8a
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/diode.lib
@@ -0,0 +1,4 @@
+.model diode D( Vj=.65 Nbvl=14.976 Cjo=175p Rs=.20 Isr=1.859n 
++ Eg=1.11 M=.5516 Nbv=1.6989 N=1 Tbv1=-21.277u 
++ Bv=8.1 Fc=.5 Ikf=0 Nr=2 Ibv=20.245m 
++ Is=880.5E-18 Xti=3 Ibvl=1.9556m )
\ No newline at end of file
diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4-cache.bak b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4-cache.bak
new file mode 100644
index 0000000..f7ad596
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4-cache.bak
@@ -0,0 +1,105 @@
+EESchema-LIBRARY Version 2.3  Date: Friday 12 April 2013 03:08:39 PM IST
+#encoding utf-8
+#
+# dc
+#
+DEF dc v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "dc" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# DIODE
+#
+DEF DIODE D 0 40 N N 1 F N
+F0 "D" 0 100 40 H V C CNN
+F1 "DIODE" 0 -100 40 H V C CNN
+$FPLIST
+ D?
+ S*
+$ENDFPLIST
+DRAW
+P 2 0 1 6  50 50  50 -50 N
+P 3 0 1 0  -50 50  50 0  -50 -50 F
+X A 1 -200 0 150 R 40 40 1 1 P
+X K 2 200 0 150 L 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF ~GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 0 30 H I C CNN
+F1 "GND" 0 -70 30 H I C CNN
+DRAW
+P 4 0 1 0  -50 0  0 -50  50 0  -50 0 N
+X GND 1 0 0 0 U 30 30 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# iplot
+#
+DEF iplot U 0 20 Y Y 1 F N
+F0 "U" -150 100 50 H V C CNN
+F1 "iplot" 150 100 50 H V C CNN
+DRAW
+C 0 0 100 0 0 0 N
+X + 1 -250 0 150 R 30 30 1 1 I
+X - 2 250 0 150 L 30 30 1 1 I
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "R" 0 0 50 V V C CNN
+$FPLIST
+ R?
+ SM0603
+ SM0805
+ R?-*
+ SM1206
+$ENDFPLIST
+DRAW
+S -40 150 40 -150 0 1 12 N
+X ~ 1 0 250 100 D 60 60 1 1 P
+X ~ 2 0 -250 100 U 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# vplot8
+#
+DEF vplot8 U 0 40 Y Y 8 F N
+F0 "U" -150 100 50 H V C CNN
+F1 "vplot8" 150 100 50 H V C CNN
+DRAW
+C 0 0 100 0 0 0 N
+X + 1 -300 0 200 R 40 40 1 1 O
+X - 9 300 0 200 L 40 40 1 1 O
+X + 2 -300 0 200 R 40 40 2 1 O
+X - 10 300 0 200 L 40 40 2 1 O
+X + 3 -300 0 200 R 40 40 3 1 O
+X - 11 300 0 200 L 40 40 3 1 O
+X + 4 -300 0 200 R 40 40 4 1 O
+X - 12 300 0 200 L 40 40 4 1 O
+X + 5 -300 0 200 R 40 40 5 1 O
+X - 13 300 0 200 L 40 40 5 1 O
+X + 6 -300 0 200 R 40 40 6 1 O
+X - 14 300 0 200 L 40 40 6 1 O
+X + 7 -300 0 200 R 40 40 7 1 O
+X - 15 300 0 200 L 40 40 7 1 O
+X + 8 -300 0 200 R 40 40 8 1 O
+X - 16 300 0 200 L 40 40 8 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4-cache.lib b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4-cache.lib
new file mode 100644
index 0000000..1321f82
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4-cache.lib
@@ -0,0 +1,108 @@
+EESchema-LIBRARY Version 2.3  Date: Monday 13 May 2013 12:59:04 PM IST
+#encoding utf-8
+#
+# dc
+#
+DEF dc v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "dc" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# DIODE
+#
+DEF DIODE D 0 40 N N 1 F N
+F0 "D" 0 100 40 H V C CNN
+F1 "DIODE" 0 -100 40 H V C CNN
+$FPLIST
+ D?
+ S*
+$ENDFPLIST
+DRAW
+P 2 0 1 6  50 50  50 -50 N
+P 3 0 1 0  -50 50  50 0  -50 -50 F
+X A 1 -200 0 150 R 40 40 1 1 P
+X K 2 200 0 150 L 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF ~GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 0 30 H I C CNN
+F1 "GND" 0 -70 30 H I C CNN
+DRAW
+P 4 0 1 0  -50 0  0 -50  50 0  -50 0 N
+X GND 1 0 0 0 U 30 30 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# iplot
+#
+DEF iplot U 0 20 Y Y 1 F N
+F0 "U" -150 100 50 H V C CNN
+F1 "iplot" 150 100 50 H V C CNN
+DRAW
+C 0 0 100 0 0 0 N
+X + 1 -250 0 150 R 30 30 1 1 I
+X - 2 250 0 150 L 30 30 1 1 I
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 270 30 H I C CNN
+F1 "PWR_FLAG" 0 230 30 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 20 20 0 0 w
+P 3 0 1 0  0 0  0 100  0 100 N
+P 5 0 1 0  0 100  -100 150  0 200  100 150  0 100 N
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "R" 0 0 50 V V C CNN
+$FPLIST
+ R?
+ SM0603
+ SM0805
+ R?-*
+$ENDFPLIST
+DRAW
+S -40 150 40 -150 0 1 12 N
+X ~ 1 0 250 100 D 60 60 1 1 P
+X ~ 2 0 -250 100 U 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# vplot8_1
+#
+DEF vplot8_1 U 0 40 Y Y 8 F N
+F0 "U" -150 100 50 H V C CNN
+F1 "vplot8_1" 150 100 50 H V C CNN
+DRAW
+C 0 0 100 0 0 0 N
+X + 1 0 -300 200 U 40 40 1 1 I
+X + 2 0 -300 200 U 40 40 2 1 I
+X + 3 0 -300 200 U 40 40 3 1 I
+X + 4 0 -300 200 U 40 40 4 1 I
+X + 5 0 -300 200 U 40 40 5 1 I
+X + 6 0 -300 200 U 40 40 6 1 I
+X + 7 0 -300 200 U 40 40 7 1 I
+X + 8 0 -300 200 U 40 40 8 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.bak b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.bak
new file mode 100644
index 0000000..132334d
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.bak
@@ -0,0 +1,133 @@
+EESchema Schematic File Version 2  date Friday 12 April 2013 03:08:39 PM IST
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:analogSpice
+LIBS:analogXSpice
+LIBS:convergenceAidSpice
+LIBS:converterSpice
+LIBS:digitalSpice
+LIBS:digitalXSpice
+LIBS:linearSpice
+LIBS:measurementSpice
+LIBS:portSpice
+LIBS:sourcesSpice
+LIBS:example_2.4-cache
+EELAYER 25  0
+EELAYER END
+$Descr A4 11700 8267
+encoding utf-8
+Sheet 1 1
+Title ""
+Date "12 apr 2013"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+	4200 2850 4200 3200
+Wire Wire Line
+	5700 3200 5700 2850
+Wire Wire Line
+	5150 2850 6100 2850
+Connection ~ 5700 2850
+Wire Wire Line
+	6100 2850 6100 3050
+Wire Wire Line
+	5200 4100 5200 4650
+Connection ~ 5200 4100
+$Comp
+L IPLOT U2
+U 1 1 5167D5E8
+P 5500 3850
+F 0 "U2" H 5350 3950 50  0000 C CNN
+F 1 "IPLOT" H 5650 3950 50  0000 C CNN
+	1    5500 3850
+	0    1    1    0   
+$EndComp
+$Comp
+L GND #PWR01
+U 1 1 5166ABF9
+P 5200 4650
+F 0 "#PWR01" H 5200 4650 30  0001 C CNN
+F 1 "GND" H 5200 4580 30  0001 C CNN
+	1    5200 4650
+	1    0    0    -1  
+$EndComp
+$Comp
+L VPLOT8 U1
+U 1 1 5166A97D
+P 6100 3350
+F 0 "U1" H 5950 3450 50  0000 C CNN
+F 1 "VPLOT8" H 6250 3450 50  0000 C CNN
+	1    6100 3350
+	0    1    1    0   
+$EndComp
+$Comp
+L DIODE D1
+U 1 1 5166A924
+P 5700 3400
+F 0 "D1" H 5700 3500 40  0000 C CNN
+F 1 "DIODE" H 5700 3300 40  0000 C CNN
+	1    5700 3400
+	0    1    1    0   
+$EndComp
+$Comp
+L R R1
+U 1 1 5166A8EF
+P 4900 2850
+F 0 "R1" V 4980 2850 50  0000 C CNN
+F 1 "1000" V 4900 2850 50  0000 C CNN
+	1    4900 2850
+	0    -1   -1   0   
+$EndComp
+$Comp
+L DC v1
+U 1 1 5166A8CD
+P 4200 3650
+F 0 "v1" H 4000 3750 60  0000 C CNN
+F 1 "5V" H 4000 3600 60  0000 C CNN
+F 2 "R1" H 3900 3650 60  0000 C CNN
+	1    4200 3650
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.cir b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.cir
new file mode 100644
index 0000000..3731a3e
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.cir
@@ -0,0 +1,13 @@
+* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 13 May 2013 12:59:00 PM IST
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+*Sheet Name:/
+U1  2 VPLOT8_1		
+U2  3 0 IPLOT		
+D1  2 3 DIODE		
+R1  1 2 1000		
+v1  1 0 5V		
+
+.end
diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.cir.ckt
new file mode 100644
index 0000000..43a6aa9
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.cir.ckt
@@ -0,0 +1,13 @@
+* eeschema netlist version 1.1 (spice format) creation date: monday 13 may 2013 12:59:00 pm ist
+.include diode.lib
+
+* Plotting option vplot8_1
+V_u2 3 0 0
+d1  2 3 diode
+r1  1 2 1000
+v1  1 0 5v
+
+.dc v1 0e-00 5e-00 50e-03
+.plot v(2) 
+.plot i(V_u2)
+.end
diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.cir.out b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.cir.out
new file mode 100644
index 0000000..3ce4892
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.cir.out
@@ -0,0 +1,18 @@
+* eeschema netlist version 1.1 (spice format) creation date: monday 13 may 2013 12:59:00 pm ist
+.include diode.lib
+
+* Plotting option vplot8_1
+V_u2 3 0 0
+d1  2 3 diode
+r1  1 2 1000
+v1  1 0 5v
+
+.dc v1 0e-00 5e-00 50e-03
+
+* Control Statements 
+.control
+run
+plot v(2) 
+plot i(V_u2)
+.endc
+.end
diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.pro b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.pro
new file mode 100644
index 0000000..9718ce6
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.pro
@@ -0,0 +1,84 @@
+update=Monday 13 May 2013 12:58:14 PM IST
+last_client=eeschema
+[eeschema]
+version=1
+LibDir=
+NetFmt=1
+HPGLSpd=20
+HPGLDm=15
+HPGLNum=1
+offX_A4=0
+offY_A4=0
+offX_A3=0
+offY_A3=0
+offX_A2=0
+offY_A2=0
+offX_A1=0
+offY_A1=0
+offX_A0=0
+offY_A0=0
+offX_A=0
+offY_A=0
+offX_B=0
+offY_B=0
+offX_C=0
+offY_C=0
+offX_D=0
+offY_D=0
+offX_E=0
+offY_E=0
+RptD_X=0
+RptD_Y=100
+RptLab=1
+LabSize=60
+[eeschema/libraries]
+LibName1=power
+LibName2=device
+LibName3=transistors
+LibName4=conn
+LibName5=linear
+LibName6=regul
+LibName7=74xx
+LibName8=cmos4000
+LibName9=adc-dac
+LibName10=memory
+LibName11=xilinx
+LibName12=special
+LibName13=microcontrollers
+LibName14=dsp
+LibName15=microchip
+LibName16=analog_switches
+LibName17=motorola
+LibName18=texas
+LibName19=intel
+LibName20=audio
+LibName21=interface
+LibName22=digital-audio
+LibName23=philips
+LibName24=display
+LibName25=cypress
+LibName26=siliconi
+LibName27=opto
+LibName28=atmel
+LibName29=contrib
+LibName30=valves
+LibName31=/home/ambikeshwar/OSCAD/library/analogSpice
+LibName32=/home/ambikeshwar/OSCAD/library/analogXSpice
+LibName33=/home/ambikeshwar/OSCAD/library/convergenceAidSpice
+LibName34=/home/ambikeshwar/OSCAD/library/converterSpice
+LibName35=/home/ambikeshwar/OSCAD/library/digitalSpice
+LibName36=/home/ambikeshwar/OSCAD/library/digitalXSpice
+LibName37=/home/ambikeshwar/OSCAD/library/linearSpice
+LibName38=/home/ambikeshwar/OSCAD/library/measurementSpice
+LibName39=/home/ambikeshwar/OSCAD/library/portSpice
+LibName40=/home/ambikeshwar/OSCAD/library/sourcesSpice
+LibName41=/home/holy/OSCAD/library/analogSpice
+LibName42=/home/holy/OSCAD/library/analogXSpice
+LibName43=/home/holy/OSCAD/library/convergenceAidSpice
+LibName44=/home/holy/OSCAD/library/converterSpice
+LibName45=/home/holy/OSCAD/library/digitalSpice
+LibName46=/home/holy/OSCAD/library/digitalXSpice
+LibName47=/home/holy/OSCAD/library/linearSpice
+LibName48=/home/holy/OSCAD/library/measurementSpice
+LibName49=/home/holy/OSCAD/library/portSpice
+LibName50=/home/holy/OSCAD/library/sourcesSpice
diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.proj b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.proj
new file mode 100644
index 0000000..eb6337b
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.proj
@@ -0,0 +1 @@
+schematicFile example_2.4.sch
diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.sch b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.sch
new file mode 100644
index 0000000..7aac593
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.4/example_2.4.sch
@@ -0,0 +1,139 @@
+EESchema Schematic File Version 2  date Monday 13 May 2013 12:59:04 PM IST
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:analogSpice
+LIBS:analogXSpice
+LIBS:convergenceAidSpice
+LIBS:converterSpice
+LIBS:digitalSpice
+LIBS:digitalXSpice
+LIBS:linearSpice
+LIBS:measurementSpice
+LIBS:portSpice
+LIBS:sourcesSpice
+LIBS:example_2.4-cache
+EELAYER 25  0
+EELAYER END
+$Descr A4 11700 8267
+encoding utf-8
+Sheet 1 1
+Title ""
+Date "13 may 2013"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
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+Comment4 ""
+$EndDescr
+$Comp
+L PWR_FLAG #FLG01
+U 1 1 51909635
+P 5200 4200
+F 0 "#FLG01" H 5200 4470 30  0001 C CNN
+F 1 "PWR_FLAG" H 5200 4430 30  0000 C CNN
+	1    5200 4200
+	1    0    0    -1  
+$EndComp
+$Comp
+L VPLOT8_1 U1
+U 1 1 5190961B
+P 5700 2550
+F 0 "U1" H 5550 2650 50  0000 C CNN
+F 1 "VPLOT8_1" H 5850 2650 50  0000 C CNN
+	1    5700 2550
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5150 2850 5700 2850
+Wire Wire Line
+	5700 3600 5700 3700
+Connection ~ 5200 4200
+Wire Wire Line
+	5200 4200 5200 4750
+Connection ~ 5700 2850
+Wire Wire Line
+	5700 2850 5700 3200
+Wire Wire Line
+	4200 3200 4200 2850
+Wire Wire Line
+	4200 2850 4650 2850
+Wire Wire Line
+	4200 4100 4200 4200
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+U 1 1 5167D5E8
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+F 1 "IPLOT" H 5850 4050 50  0000 C CNN
+	1    5700 3950
+	0    1    1    0   
+$EndComp
+$Comp
+L GND #PWR02
+U 1 1 5166ABF9
+P 5200 4750
+F 0 "#PWR02" H 5200 4750 30  0001 C CNN
+F 1 "GND" H 5200 4680 30  0001 C CNN
+	1    5200 4750
+	1    0    0    -1  
+$EndComp
+$Comp
+L DIODE D1
+U 1 1 5166A924
+P 5700 3400
+F 0 "D1" H 5700 3500 40  0000 C CNN
+F 1 "DIODE" H 5700 3300 40  0000 C CNN
+	1    5700 3400
+	0    1    1    0   
+$EndComp
+$Comp
+L R R1
+U 1 1 5166A8EF
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+	1    4900 2850
+	0    -1   -1   0   
+$EndComp
+$Comp
+L DC v1
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+F 0 "v1" H 4000 3750 60  0000 C CNN
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+	1    4200 3650
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+$EndComp
+$EndSCHEMATC