initial commit

14 files changed, 854 insertions, 0 deletions

diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/1n4007.lib b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/1n4007.lib
new file mode 100644
index 0000000..89d421d
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/1n4007.lib
@@ -0,0 +1,2 @@
+.model 1n4007 D( IS=7.02767e-09 RS=0.0341512 N=1.80803 EG=1.05743 XTI=5 BV=1000 IBV=5e-08 CJO=1E-11 
++VJ=0.7 M=0.5 FC=0.5 TT=1E-07 KF=0 AF=1 )
diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/analysis b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/analysis
new file mode 100644
index 0000000..09ae223
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/analysis
@@ -0,0 +1 @@
+.tran 10e-03 1e-01 0e-00
diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1-cache.bak b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1-cache.bak
new file mode 100644
index 0000000..a47b560
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1-cache.bak
@@ -0,0 +1,108 @@
+EESchema-LIBRARY Version 2.3  Date: Tuesday 14 May 2013 11:21:47 AM IST
+#encoding utf-8
+#
+# dc
+#
+DEF dc v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "dc" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# DIODE
+#
+DEF DIODE D 0 40 N N 1 F N
+F0 "D" 0 100 40 H V C CNN
+F1 "DIODE" 0 -100 40 H V C CNN
+$FPLIST
+ D?
+ S*
+$ENDFPLIST
+DRAW
+P 2 0 1 6  50 50  50 -50 N
+P 3 0 1 0  -50 50  50 0  -50 -50 F
+X A 1 -200 0 150 R 40 40 1 1 P
+X K 2 200 0 150 L 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF ~GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 0 30 H I C CNN
+F1 "GND" 0 -70 30 H I C CNN
+DRAW
+P 4 0 1 0  -50 0  0 -50  50 0  -50 0 N
+X GND 1 0 0 0 U 30 30 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# iplot
+#
+DEF iplot U 0 20 Y Y 1 F N
+F0 "U" -150 100 50 H V C CNN
+F1 "iplot" 150 100 50 H V C CNN
+DRAW
+C 0 0 100 0 0 0 N
+X + 1 -250 0 150 R 30 30 1 1 I
+X - 2 250 0 150 L 30 30 1 1 I
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 270 30 H I C CNN
+F1 "PWR_FLAG" 0 230 30 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 20 20 0 0 w
+P 3 0 1 0  0 0  0 100  0 100 N
+P 5 0 1 0  0 100  -100 150  0 200  100 150  0 100 N
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "R" 0 0 50 V V C CNN
+$FPLIST
+ R?
+ SM0603
+ SM0805
+ R?-*
+$ENDFPLIST
+DRAW
+S -40 150 40 -150 0 1 12 N
+X ~ 1 0 250 100 D 60 60 1 1 P
+X ~ 2 0 -250 100 U 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# sine
+#
+DEF sine v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "sine" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -50 0 50 1 1799 0 1 0 N 0 0 -100 0
+A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 0 1 1 I
+X - 2 0 -450 300 U 50 0 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1-cache.lib b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1-cache.lib
new file mode 100644
index 0000000..6d1cabe
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1-cache.lib
@@ -0,0 +1,108 @@
+EESchema-LIBRARY Version 2.3  Date: Tuesday 14 May 2013 11:52:16 AM IST
+#encoding utf-8
+#
+# dc
+#
+DEF dc v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "dc" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# DIODE
+#
+DEF DIODE D 0 40 N N 1 F N
+F0 "D" 0 100 40 H V C CNN
+F1 "DIODE" 0 -100 40 H V C CNN
+$FPLIST
+ D?
+ S*
+$ENDFPLIST
+DRAW
+P 2 0 1 6  50 50  50 -50 N
+P 3 0 1 0  -50 50  50 0  -50 -50 F
+X A 1 -200 0 150 R 40 40 1 1 P
+X K 2 200 0 150 L 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF ~GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 0 30 H I C CNN
+F1 "GND" 0 -70 30 H I C CNN
+DRAW
+P 4 0 1 0  -50 0  0 -50  50 0  -50 0 N
+X GND 1 0 0 0 U 30 30 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# iplot
+#
+DEF iplot U 0 20 Y Y 1 F N
+F0 "U" -150 100 50 H V C CNN
+F1 "iplot" 150 100 50 H V C CNN
+DRAW
+C 0 0 100 0 0 0 N
+X + 1 -250 0 150 R 30 30 1 1 I
+X - 2 250 0 150 L 30 30 1 1 I
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 270 30 H I C CNN
+F1 "PWR_FLAG" 0 230 30 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 20 20 0 0 w
+P 3 0 1 0  0 0  0 100  0 100 N
+P 5 0 1 0  0 100  -100 150  0 200  100 150  0 100 N
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "R" 0 0 50 V V C CNN
+$FPLIST
+ R?
+ SM0603
+ SM0805
+ R?-*
+$ENDFPLIST
+DRAW
+S -40 150 40 -150 0 1 12 N
+X ~ 1 0 250 100 D 60 60 1 1 P
+X ~ 2 0 -250 100 U 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# sine
+#
+DEF sine v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "sine" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -50 0 50 1 1799 0 1 0 N 0 0 -100 0
+A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 0 1 1 I
+X - 2 0 -450 300 U 50 0 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.bak b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.bak
new file mode 100644
index 0000000..3314c60
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.bak
@@ -0,0 +1,133 @@
+EESchema Schematic File Version 2  date Tuesday 14 May 2013 11:21:47 AM IST
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:example_2.1-cache
+EELAYER 25  0
+EELAYER END
+$Descr A4 11700 8267
+encoding utf-8
+Sheet 1 1
+Title ""
+Date "14 may 2013"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+Connection ~ 5750 5050
+Wire Wire Line
+	5550 3150 5650 3150
+Wire Wire Line
+	5050 4550 5050 5050
+Wire Wire Line
+	6500 4900 6500 5050
+Wire Wire Line
+	6050 3150 6500 3150
+Wire Wire Line
+	5750 5050 5750 5800
+Connection ~ 5750 5550
+Connection ~ 6500 3150
+Wire Wire Line
+	6500 3150 6500 3350
+Wire Wire Line
+	6500 3850 6500 4000
+Wire Wire Line
+	5050 3150 5050 3650
+Wire Wire Line
+	6500 5050 5050 5050
+$Comp
+L DC v2
+U 1 1 516BA020
+P 6500 4450
+F 0 "v2" H 6300 4550 60  0000 C CNN
+F 1 "DC" H 6300 4400 60  0000 C CNN
+F 2 "R1" H 6200 4450 60  0000 C CNN
+	1    6500 4450
+	1    0    0    -1  
+$EndComp
+$Comp
+L PWR_FLAG #FLG01
+U 1 1 5167CC3A
+P 5750 5550
+F 0 "#FLG01" H 5750 5645 30  0001 C CNN
+F 1 "PWR_FLAG" H 5750 5730 30  0000 C CNN
+	1    5750 5550
+	1    0    0    -1  
+$EndComp
+$Comp
+L GND #PWR02
+U 1 1 5167CC15
+P 5750 5800
+F 0 "#PWR02" H 5750 5800 30  0001 C CNN
+F 1 "GND" H 5750 5730 30  0001 C CNN
+	1    5750 5800
+	1    0    0    -1  
+$EndComp
+$Comp
+L IPLOT U1
+U 1 1 5166A34A
+P 6500 3600
+F 0 "U1" H 6350 3700 50  0000 C CNN
+F 1 "IPLOT" H 6650 3700 50  0000 C CNN
+	1    6500 3600
+	0    1    1    0   
+$EndComp
+$Comp
+L DIODE D1
+U 1 1 5166A210
+P 5850 3150
+F 0 "D1" H 5850 3250 40  0000 C CNN
+F 1 "DIODE" H 5850 3050 40  0000 C CNN
+	1    5850 3150
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R1
+U 1 1 5166A1EB
+P 5300 3150
+F 0 "R1" V 5380 3150 50  0000 C CNN
+F 1 "100" V 5300 3150 50  0000 C CNN
+	1    5300 3150
+	0    -1   -1   0   
+$EndComp
+$Comp
+L SINE v1
+U 1 1 5166A1AC
+P 5050 4100
+F 0 "v1" H 4850 4200 60  0000 C CNN
+F 1 "SINE" H 4850 4050 60  0000 C CNN
+F 2 "R1" H 4750 4100 60  0000 C CNN
+	1    5050 4100
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.brd b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.brd
new file mode 100644
index 0000000..bf4bd89
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.brd
@@ -0,0 +1,172 @@
+PCBNEW-BOARD Version 1 date Friday 12 April 2013 02:43:29 PM IST
+
+# Created by Pcbnew(2012-apr-16-27)-stable
+
+$GENERAL
+encoding utf-8
+LayerCount 2
+Ly 1FFF8001
+EnabledLayers 1FFF8001
+Links 0
+NoConn 0
+Di 40424 25540 76751 39450
+Ndraw 0
+Ntrack 0
+Nzone 0
+BoardThickness 630
+Nmodule 2
+Nnets 4
+$EndGENERAL
+
+$SHEETDESCR
+Sheet A4 11700 8267
+Title ""
+Date "12 apr 2013"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndSHEETDESCR
+
+$SETUP
+InternalUnit 0.000100 INCH
+Layers 2
+Layer[0] Back signal
+Layer[15] Front signal
+TrackWidth 80
+TrackClearence 100
+ZoneClearence 200
+TrackMinWidth 80
+DrawSegmWidth 150
+EdgeSegmWidth 150
+ViaSize 350
+ViaDrill 250
+ViaMinSize 350
+ViaMinDrill 200
+MicroViaSize 200
+MicroViaDrill 50
+MicroViasAllowed 0
+MicroViaMinSize 200
+MicroViaMinDrill 50
+TextPcbWidth 120
+TextPcbSize 600 800
+EdgeModWidth 150
+TextModSize 600 600
+TextModWidth 120
+PadSize 600 600
+PadDrill 320
+Pad2MaskClearance 100
+AuxiliaryAxisOrg 0 0
+PcbPlotParams (pcbplotparams (layerselection 3178497) (usegerberextensions true) (excludeedgelayer true) (linewidth 60) (plotframeref false) (viasonmask false) (mode 1) (useauxorigin false) (hpglpennumber 1) (hpglpenspeed 20) (hpglpendiameter 15) (hpglpenoverlay 2) (pscolor true) (psnegative false) (psa4output false) (plotreference true) (plotvalue true) (plotothertext true) (plotinvisibletext false) (padsonsilk false) (subtractmaskfromsilk false) (outputformat 1) (mirror false) (drillshape 1) (scaleselection 1) (outputdirectory ""))
+$EndSETUP
+
+$EQUIPOT
+Na 0 ""
+St ~
+$EndEQUIPOT
+$EQUIPOT
+Na 1 "GND"
+St ~
+$EndEQUIPOT
+$EQUIPOT
+Na 2 "N-000018"
+St ~
+$EndEQUIPOT
+$EQUIPOT
+Na 3 "N-000019"
+St ~
+$EndEQUIPOT
+$NCLASS
+Name "Default"
+Desc "This is the default net class."
+Clearance 100
+TrackWidth 80
+ViaDia 350
+ViaDrill 250
+uViaDia 200
+uViaDrill 50
+AddNet ""
+AddNet "GND"
+AddNet "N-000018"
+AddNet "N-000019"
+$EndNCLASS
+$MODULE 1pin
+Po 41500 38000 0 15 00200000 5167CFD9 ~~
+Li 1pin
+Cd module 1 pin (ou trou mecanique de percage)
+Kw DEV
+Sc 5167CFD9
+AR 1pin
+Op 0 0 0
+T0 0 -1200 400 400 0 100 N V 21 N "1PIN"
+T1 0 1100 400 400 0 100 N I 21 N "P***"
+DC 0 0 0 -900 150 21
+$PAD
+Sh "1" C 1600 1600 0 0 0
+Dr 1200 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 0 0
+$EndPAD
+$EndMODULE  1pin
+$MODULE 3PIN_6mm
+Po 68000 29000 0 15 00200000 5167CFEC ~~
+Li 3PIN_6mm
+Cd module 2 pin (trou 6 mm)
+Kw DEV
+Sc 5167CFEC
+AR 
+Op 0 0 0
+T0 4000 -3000 600 600 0 120 N V 21 N "K1"
+T1 -3000 -3000 600 600 0 120 N V 21 N "CONN_3"
+DS -8500 -2500 8500 -2500 150 21
+DS 8500 -2500 8500 2500 150 21
+DS 8500 2500 -8500 2500 150 21
+DS -8500 2500 -8500 -2500 150 21
+$PAD
+Sh "1" C 4000 4000 0 0 0
+Dr 2400 0 0
+At STD N 00E0FFFF
+Ne 2 "N-000018"
+Po -5900 0
+$EndPAD
+$PAD
+Sh "3" C 4000 4000 0 0 0
+Dr 2400 0 0
+At STD N 00E0FFFF
+Ne 3 "N-000019"
+Po 5900 0
+$EndPAD
+$PAD
+Sh "2" C 4000 4000 0 0 0
+Dr 2400 0 0
+At STD N 00E0FFFF
+Ne 1 "GND"
+Po 0 0
+$EndPAD
+$SHAPE3D
+Na "device/douille_4mm(black).wrl"
+Sc 1.800000 1.800000 1.800000
+Of 0.000000 0.000000 0.000000
+Ro 0.000000 0.000000 0.000000
+$EndSHAPE3D
+$SHAPE3D
+Na "device/douille_4mm(red).wrl"
+Sc 1.800000 1.800000 1.800000
+Of -0.590000 0.000000 0.000000
+Ro 0.000000 0.000000 0.000000
+$EndSHAPE3D
+$SHAPE3D
+Na "device/douille_4mm(green).wrl"
+Sc 1.800000 1.800000 1.800000
+Of 0.590000 0.000000 0.000000
+Ro 0.000000 0.000000 0.000000
+$EndSHAPE3D
+$EndMODULE  3PIN_6mm
+$TRACK
+$EndTRACK
+$ZONE
+$EndZONE
+$EndBOARD
diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.cir b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.cir
new file mode 100644
index 0000000..16861f7
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.cir
@@ -0,0 +1,13 @@
+* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 15 April 2013 12:08:03 PM IST
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+*Sheet Name:/
+v2  1 0 DC		
+U1  3 1 IPLOT		
+D1  5 3 DIODE		
+R1  2 5 100		
+v1  2 0 SINE		
+
+.end
diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.cir.ckt
new file mode 100644
index 0000000..6d02b34
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.cir.ckt
@@ -0,0 +1,11 @@
+* eeschema netlist version 1.1 (spice format) creation date: monday 15 april 2013 12:08:03 pm ist
+
+v2  1 0 dc 12
+V_u1 3 1 0
+d1  5 3 diode
+r1  2 5 100
+v1  2 0 sine(0 24 50 0 0)
+
+.tran 10e-03 1e-01 0e-00
+.plot i(V_u1)
+.end
diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.cir.out b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.cir.out
new file mode 100644
index 0000000..52cc067
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.cir.out
@@ -0,0 +1,16 @@
+* eeschema netlist version 1.1 (spice format) creation date: monday 15 april 2013 12:08:03 pm ist
+
+v2  1 0 dc 12
+V_u1 3 1 0
+d1  5 3 diode
+r1  2 5 100
+v1  2 0 sine(0 24 50 0 0)
+
+.tran 10e-03 1e-01 0e-00
+
+* Control Statements 
+.control
+run
+plot i(V_u1)
+.endc
+.end
diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.cmp b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.cmp
new file mode 100644
index 0000000..779ff51
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.cmp
@@ -0,0 +1,38 @@
+Cmp-Mod V01 Created by CvPcb (2012-apr-16-27)-stable date = Friday 12 April 2013 02:41:23 PM IST
+
+BeginCmp
+TimeStamp = /5166A210;
+Reference = D1;
+ValeurCmp = DIODE;
+IdModule  = ;
+EndCmp
+
+BeginCmp
+TimeStamp = /5166A1EB;
+Reference = R1;
+ValeurCmp = 100;
+IdModule  = ;
+EndCmp
+
+BeginCmp
+TimeStamp = /5166A34A;
+Reference = U1;
+ValeurCmp = IPLOT;
+IdModule  = ;
+EndCmp
+
+BeginCmp
+TimeStamp = /5166A1AC;
+Reference = v1;
+ValeurCmp = SINE;
+IdModule  = R1;
+EndCmp
+
+BeginCmp
+TimeStamp = /5166A26E;
+Reference = v2;
+ValeurCmp = 12V;
+IdModule  = R1;
+EndCmp
+
+EndListe
diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.net b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.net
new file mode 100644
index 0000000..eeea8db
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.net
@@ -0,0 +1,44 @@
+# EESchema Netlist Version 1.1 created  Friday 12 April 2013 02:41:23 PM IST
+(
+ ( /5166A210 $noname$ D1 DIODE
+  ( 1 N-000002 )
+  ( 2 N-000004 )
+ )
+ ( /5166A1EB $noname$ R1 100
+  ( 1 N-000001 )
+  ( 2 N-000002 )
+ )
+ ( /5166A34A $noname$ U1 IPLOT
+  ( 1 N-000004 )
+  ( 2 N-000003 )
+ )
+ ( /5166A1AC R1 v1 SINE
+  ( 1 N-000001 )
+  ( 2 GND )
+ )
+ ( /5166A26E R1 v2 12V
+  ( 1 N-000003 )
+  ( 2 GND )
+ )
+)
+*
+{ Allowed footprints by component:
+$component D1
+ D?
+ S*
+$endlist
+$component R1
+ R?
+ SM0603
+ SM0805
+ R?-*
+ SM1206
+$endlist
+$component v1
+ 1_pin
+$endlist
+$component v2
+ 1_pin
+$endlist
+$endfootprintlist
+}
diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.pro b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.pro
new file mode 100644
index 0000000..f5826c2
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.pro
@@ -0,0 +1,74 @@
+update=Thursday 11 April 2013 05:12:20 PM IST
+last_client=eeschema
+[eeschema]
+version=1
+LibDir=
+NetFmt=1
+HPGLSpd=20
+HPGLDm=15
+HPGLNum=1
+offX_A4=0
+offY_A4=0
+offX_A3=0
+offY_A3=0
+offX_A2=0
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diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.proj b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.proj
new file mode 100644
index 0000000..3cb5076
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.proj
@@ -0,0 +1 @@
+schematicFile example_2.1.sch
diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.sch b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.sch
new file mode 100644
index 0000000..dfa5e1d
--- /dev/null
+++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.1/example_2.1.sch
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+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:example_2.1-cache
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+encoding utf-8
+Sheet 1 1
+Title ""
+Date "14 may 2013"
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