initial commit

14 files changed, 1080 insertions, 0 deletions

diff --git a/OSCAD/Examples/linear1/analysis b/OSCAD/Examples/linear1/analysis
new file mode 100644
index 0000000..162ad08
--- /dev/null
+++ b/OSCAD/Examples/linear1/analysis
@@ -0,0 +1 @@
+.op
\ No newline at end of file
diff --git a/OSCAD/Examples/linear1/linear1-cache.bak b/OSCAD/Examples/linear1/linear1-cache.bak
new file mode 100644
index 0000000..b2b47b7
--- /dev/null
+++ b/OSCAD/Examples/linear1/linear1-cache.bak
@@ -0,0 +1,106 @@
+EESchema-LIBRARY Version 2.3  Date: Monday 17 December 2012 11:21:41 AM IST
+#encoding utf-8
+#
+# dc
+#
+DEF dc v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "dc" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF ~GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 0 30 H I C CNN
+F1 "GND" 0 -70 30 H I C CNN
+DRAW
+P 4 0 1 0  -50 0  0 -50  50 0  -50 0 N
+X GND 1 0 0 0 U 30 30 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 270 30 H I C CNN
+F1 "PWR_FLAG" 0 230 30 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 20 20 0 0 w
+P 3 0 1 0  0 0  0 100  0 100 N
+P 5 0 1 0  0 100  -100 150  0 200  100 150  0 100 N
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "R" 0 0 50 V V C CNN
+$FPLIST
+ R?
+ SM0603
+ SM0805
+ R?-*
+$ENDFPLIST
+DRAW
+S -40 150 40 -150 0 1 12 N
+X ~ 1 0 250 100 D 60 60 1 1 P
+X ~ 2 0 -250 100 U 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# VCCS
+#
+DEF VCCS G 0 40 Y Y 1 F N
+F0 "G" -200 100 50 H V C CNN
+F1 "VCCS" -200 -50 50 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+S -100 100 100 -100 0 1 0 N
+X + 1 -300 50 200 R 35 35 1 1 P
+X - 2 300 50 200 L 35 35 1 1 P
+X +c 3 -50 -200 100 U 35 35 1 1 P
+X -c 4 50 -200 100 U 35 35 1 1 P
+ENDDRAW
+ENDDEF
+#
+# VCVS
+#
+DEF VCVS E 0 40 Y Y 1 F N
+F0 "E" -200 100 50 H V C CNN
+F1 "VCVS" -200 -50 50 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+S -100 100 100 -100 0 1 0 N
+X + 1 -300 50 200 R 35 35 1 1 P
+X - 2 300 50 200 L 35 35 1 1 P
+X +c 3 -50 -200 100 U 35 35 1 1 P
+X -c 4 50 -200 100 U 35 35 1 1 P
+ENDDRAW
+ENDDEF
+#
+# vprint1
+#
+DEF vprint1 U 0 40 Y Y 1 F N
+F0 "U" -150 100 50 H V C CNN
+F1 "vprint1" 150 100 50 H V C CNN
+DRAW
+C 0 0 100 0 0 0 N
+X + 1 0 -300 200 U 40 40 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/OSCAD/Examples/linear1/linear1-cache.lib b/OSCAD/Examples/linear1/linear1-cache.lib
new file mode 100644
index 0000000..55c3d03
--- /dev/null
+++ b/OSCAD/Examples/linear1/linear1-cache.lib
@@ -0,0 +1,106 @@
+EESchema-LIBRARY Version 2.3  Date: Monday 17 December 2012 11:24:11 AM IST
+#encoding utf-8
+#
+# dc
+#
+DEF dc v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "dc" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF ~GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 0 30 H I C CNN
+F1 "GND" 0 -70 30 H I C CNN
+DRAW
+P 4 0 1 0  -50 0  0 -50  50 0  -50 0 N
+X GND 1 0 0 0 U 30 30 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 270 30 H I C CNN
+F1 "PWR_FLAG" 0 230 30 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 20 20 0 0 w
+P 3 0 1 0  0 0  0 100  0 100 N
+P 5 0 1 0  0 100  -100 150  0 200  100 150  0 100 N
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "R" 0 0 50 V V C CNN
+$FPLIST
+ R?
+ SM0603
+ SM0805
+ R?-*
+$ENDFPLIST
+DRAW
+S -40 150 40 -150 0 1 12 N
+X ~ 1 0 250 100 D 60 60 1 1 P
+X ~ 2 0 -250 100 U 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# VCCS
+#
+DEF VCCS G 0 40 Y Y 1 F N
+F0 "G" -200 100 50 H V C CNN
+F1 "VCCS" -200 -50 50 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+S -100 100 100 -100 0 1 0 N
+X + 1 -300 50 200 R 35 35 1 1 P
+X - 2 300 50 200 L 35 35 1 1 P
+X +c 3 -50 -200 100 U 35 35 1 1 P
+X -c 4 50 -200 100 U 35 35 1 1 P
+ENDDRAW
+ENDDEF
+#
+# VCVS
+#
+DEF VCVS E 0 40 Y Y 1 F N
+F0 "E" -200 100 50 H V C CNN
+F1 "VCVS" -200 -50 50 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+S -100 100 100 -100 0 1 0 N
+X + 1 -300 50 200 R 35 35 1 1 P
+X - 2 300 50 200 L 35 35 1 1 P
+X +c 3 -50 -200 100 U 35 35 1 1 P
+X -c 4 50 -200 100 U 35 35 1 1 P
+ENDDRAW
+ENDDEF
+#
+# vprint1
+#
+DEF vprint1 U 0 40 Y Y 1 F N
+F0 "U" -150 100 50 H V C CNN
+F1 "vprint1" 150 100 50 H V C CNN
+DRAW
+C 0 0 100 0 0 0 N
+X + 1 0 -300 200 U 40 40 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/OSCAD/Examples/linear1/linear1.bak b/OSCAD/Examples/linear1/linear1.bak
new file mode 100644
index 0000000..2be3d0e
--- /dev/null
+++ b/OSCAD/Examples/linear1/linear1.bak
@@ -0,0 +1,233 @@
+EESchema Schematic File Version 2  date Monday 17 December 2012 11:21:41 AM IST
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:analogSpice
+LIBS:converterSpice
+LIBS:digitalSpice
+LIBS:linearSpice
+LIBS:measurementSpice
+LIBS:portSpice
+LIBS:sourcesSpice
+LIBS:linear1-cache
+EELAYER 25  0
+EELAYER END
+$Descr A4 11700 8267
+encoding utf-8
+Sheet 1 1
+Title ""
+Date "17 dec 2012"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+Wire Wire Line
+	6100 2500 5650 2500
+Wire Wire Line
+	5650 2500 5650 2900
+Connection ~ 5650 2900
+Wire Wire Line
+	5350 2900 5750 2900
+Connection ~ 6850 3800
+Wire Wire Line
+	6850 3800 6850 3600
+Connection ~ 7300 2900
+Wire Wire Line
+	7300 3000 7300 2500
+Connection ~ 6400 3800
+Wire Wire Line
+	6400 3500 6400 3800
+Connection ~ 5500 3800
+Wire Wire Line
+	7300 3500 7300 3800
+Wire Wire Line
+	7300 3800 3750 3800
+Connection ~ 4600 2900
+Wire Wire Line
+	4600 3000 4600 2900
+Connection ~ 6400 2900
+Wire Wire Line
+	6550 2900 6250 2900
+Wire Wire Line
+	4750 2900 4450 2900
+Wire Wire Line
+	3750 2900 3950 2900
+Wire Wire Line
+	6400 2900 6400 3000
+Wire Wire Line
+	7300 2900 7050 2900
+Wire Wire Line
+	4600 3500 4600 3800
+Connection ~ 4600 3800
+Wire Wire Line
+	5800 3800 5800 4000
+Connection ~ 5800 3800
+Wire Wire Line
+	7300 2500 6700 2500
+Wire Wire Line
+	7300 2750 7700 2750
+Connection ~ 7300 2750
+$Comp
+L VPRINT1 U1
+U 1 1 506964BE
+P 7700 2450
+F 0 "U1" H 7550 2550 50  0001 C CNN
+F 1 "VPRINT1" H 7850 2550 50  0000 C CNN
+	1    7700 2450
+	1    0    0    -1  
+$EndComp
+$Comp
+L PWR_FLAG #FLG01
+U 1 1 50695F5E
+P 6850 3600
+F 0 "#FLG01" H 6850 3870 30  0001 C CNN
+F 1 "PWR_FLAG" H 6850 3830 30  0000 C CNN
+	1    6850 3600
+	1    0    0    -1  
+$EndComp
+$Comp
+L GND #PWR02
+U 1 1 50695EE6
+P 5800 4000
+F 0 "#PWR02" H 5800 4000 30  0001 C CNN
+F 1 "GND" H 5800 3930 30  0001 C CNN
+	1    5800 4000
+	1    0    0    -1  
+$EndComp
+Text Label 6100 3800 0    60   ~ 0
+c
+Text Label 6350 2750 0    60   ~ 0
+c
+Text Label 6450 2750 0    60   ~ 0
+b
+Text Label 6550 2900 0    60   ~ 0
+b
+Text Label 5100 3150 0    60   ~ 0
+b
+Text Label 5000 3150 0    60   ~ 0
+a
+Text Label 7150 2900 0    60   ~ 0
+a
+$Comp
+L VCVS E1
+U 1 1 50695730
+P 5050 2950
+F 0 "E1" H 4850 3050 50  0000 C CNN
+F 1 "0.5" H 4850 2900 50  0000 C CNN
+	1    5050 2950
+	1    0    0    -1  
+$EndComp
+$Comp
+L DC I1
+U 1 1 506956A6
+P 5500 3350
+F 0 "I1" H 5300 3450 60  0000 C CNN
+F 1 "1" H 5300 3300 60  0000 C CNN
+F 2 "R1" H 5200 3350 60  0000 C CNN
+	1    5500 3350
+	-1   0    0    1   
+$EndComp
+$Comp
+L DC V1
+U 1 1 50695694
+P 3750 3350
+F 0 "V1" H 3550 3450 60  0000 C CNN
+F 1 "1" H 3550 3300 60  0000 C CNN
+F 2 "R1" H 3450 3350 60  0000 C CNN
+	1    3750 3350
+	1    0    0    -1  
+$EndComp
+$Comp
+L VCCS G1
+U 1 1 5069566A
+P 6400 2550
+F 0 "G1" H 6200 2650 50  0000 C CNN
+F 1 "0.5" H 6200 2500 50  0000 C CNN
+	1    6400 2550
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R6
+U 1 1 506955DC
+P 7300 3250
+F 0 "R6" V 7380 3250 50  0000 C CNN
+F 1 "1" V 7300 3250 50  0000 C CNN
+	1    7300 3250
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R3
+U 1 1 506955D8
+P 6400 3250
+F 0 "R3" V 6480 3250 50  0000 C CNN
+F 1 "1" V 6400 3250 50  0000 C CNN
+	1    6400 3250
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R5
+U 1 1 506955D1
+P 6800 2900
+F 0 "R5" V 6880 2900 50  0000 C CNN
+F 1 "0.5" V 6800 2900 50  0000 C CNN
+	1    6800 2900
+	0    1    1    0   
+$EndComp
+$Comp
+L R R4
+U 1 1 506955CC
+P 6000 2900
+F 0 "R4" V 6080 2900 50  0000 C CNN
+F 1 "1" V 6000 2900 50  0000 C CNN
+	1    6000 2900
+	0    1    1    0   
+$EndComp
+$Comp
+L R R2
+U 1 1 506955C7
+P 4600 3250
+F 0 "R2" V 4680 3250 50  0000 C CNN
+F 1 "1" V 4600 3250 50  0000 C CNN
+	1    4600 3250
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R1
+U 1 1 506955C2
+P 4200 2900
+F 0 "R1" V 4280 2900 50  0000 C CNN
+F 1 "1" V 4200 2900 50  0000 C CNN
+	1    4200 2900
+	0    1    1    0   
+$EndComp
+$EndSCHEMATC
diff --git a/OSCAD/Examples/linear1/linear1.brd b/OSCAD/Examples/linear1/linear1.brd
new file mode 100644
index 0000000..a04a203
--- /dev/null
+++ b/OSCAD/Examples/linear1/linear1.brd
@@ -0,0 +1,84 @@
+PCBNEW-BOARD Version 1 date Thursday 04 October 2012 03:56:07 PM IST
+
+# Created by Pcbnew(2011-05-25)-stable
+
+$GENERAL
+encoding utf-8
+LayerCount 2
+Ly 1FFF8001
+EnabledLayers 1FFF8001
+Links 0
+NoConn 0
+Di 0 0 117000 82670
+Ndraw 0
+Ntrack 0
+Nzone 0
+BoardThickness 630
+Nmodule 0
+Nnets 1
+$EndGENERAL
+
+$SHEETDESCR
+Sheet A4 11700 8267
+Title ""
+Date "4 oct 2012"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndSHEETDESCR
+
+$SETUP
+InternalUnit 0.000100 INCH
+Layers 2
+Layer[0] Back signal
+Layer[15] Front signal
+TrackWidth 80
+TrackClearence 100
+ZoneClearence 200
+TrackMinWidth 80
+DrawSegmWidth 150
+EdgeSegmWidth 150
+ViaSize 350
+ViaDrill 250
+ViaMinSize 350
+ViaMinDrill 200
+MicroViaSize 200
+MicroViaDrill 50
+MicroViasAllowed 0
+MicroViaMinSize 200
+MicroViaMinDrill 50
+TextPcbWidth 120
+TextPcbSize 600 800
+EdgeModWidth 150
+TextModSize 600 600
+TextModWidth 120
+PadSize 600 600
+PadDrill 320
+Pad2MaskClearance 100
+AuxiliaryAxisOrg 0 0
+PcbPlotParams (pcbplotparams (layerselection 3178497) (usegerberextensions true) (excludeedgelayer true) (linewidth 60) (plotframeref false) (viasonmask false) (mode 1) (useauxorigin false) (hpglpennumber 1) (hpglpenspeed 20) (hpglpendiameter 15) (hpglpenoverlay 2) (pscolor true) (psnegative false) (psa4output false) (plotreference true) (plotvalue true) (plotothertext true) (plotinvisibletext false) (padsonsilk false) (subtractmaskfromsilk false) (outputformat 1) (mirror false) (drillshape 1) (scaleselection 1) (outputdirectory ""))
+$EndSETUP
+
+$EQUIPOT
+Na 0 ""
+St ~
+$EndEQUIPOT
+$NCLASS
+Name "Default"
+Desc "This is the default net class."
+Clearance 100
+TrackWidth 80
+ViaDia 350
+ViaDrill 250
+uViaDia 200
+uViaDrill 50
+AddNet ""
+$EndNCLASS
+$TRACK
+$EndTRACK
+$ZONE
+$EndZONE
+$EndBOARD
diff --git a/OSCAD/Examples/linear1/linear1.cir b/OSCAD/Examples/linear1/linear1.cir
new file mode 100644
index 0000000..349f95a
--- /dev/null
+++ b/OSCAD/Examples/linear1/linear1.cir
@@ -0,0 +1,19 @@
+* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:24:34 AM IST
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+*Sheet Name:/
+U1  1 VPRINT1		
+E1  4 6 1 2 0.5		
+I1  0 6 1		
+V1  3 0 1		
+G1  6 1 0 2 0.5		
+R6  1 0 1		
+R3  2 0 1		
+R5  1 2 0.5		
+R4  2 6 1		
+R2  4 0 1		
+R1  4 3 1		
+
+.end
diff --git a/OSCAD/Examples/linear1/linear1.cir.ckt b/OSCAD/Examples/linear1/linear1.cir.ckt
new file mode 100644
index 0000000..6738a45
--- /dev/null
+++ b/OSCAD/Examples/linear1/linear1.cir.ckt
@@ -0,0 +1,17 @@
+* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:24:34 am ist
+
+* Printing option vprint1
+e1  4 6 1 2 0.5
+i1  0 6 1
+v1  3 0 1
+g1  6 1 0 2 0.5
+r6  1 0 1
+r3  2 0 1
+r5  1 2 0.5
+r4  2 6 1
+r2  4 0 1
+r1  4 3 1
+
+.op
+.print v(1)
+.end
diff --git a/OSCAD/Examples/linear1/linear1.cir.ckt.sol b/OSCAD/Examples/linear1/linear1.cir.ckt.sol
new file mode 100644
index 0000000..5727235
--- /dev/null
+++ b/OSCAD/Examples/linear1/linear1.cir.ckt.sol
@@ -0,0 +1,14 @@
+Name	 Source	 Sink	       Voltage	       Current
+----------------------------------------------------------
+E	 4	 6	    0.0000000000    0.0000000000
+I	 1	 2	    0.0000000000    0.0000000000
+I	 0	 6	   -0.0000000000    0.0000000000
+V	 3	 0	    0.0000000000    0.0000000000
+G	 6	 1	    0.0000000000   -0.0000000000
+I	 0	 2	   -0.0000000000    0.0000000000
+R	 1	 0	    0.0000000000    0.0000000000
+R	 2	 0	    0.0000000000    0.0000000000
+R	 1	 2	    0.0000000000    0.0000000000
+R	 2	 6	    0.0000000000    0.0000000000
+R	 4	 0	    0.0000000000    0.0000000000
+R	 4	 3	    0.0000000000    0.0000000000
diff --git a/OSCAD/Examples/linear1/linear1.cir.out b/OSCAD/Examples/linear1/linear1.cir.out
new file mode 100644
index 0000000..b996360
--- /dev/null
+++ b/OSCAD/Examples/linear1/linear1.cir.out
@@ -0,0 +1,22 @@
+* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:24:34 am ist
+
+* Printing option vprint1
+e1  4 6 1 2 0.5
+i1  0 6 1
+v1  3 0 1
+g1  6 1 0 2 0.5
+r6  1 0 1
+r3  2 0 1
+r5  1 2 0.5
+r4  2 6 1
+r2  4 0 1
+r1  4 3 1
+
+.op
+
+* Control Statements 
+.control
+run
+print v(1)
+.endc
+.end
diff --git a/OSCAD/Examples/linear1/linear1.cmp b/OSCAD/Examples/linear1/linear1.cmp
new file mode 100644
index 0000000..84671d7
--- /dev/null
+++ b/OSCAD/Examples/linear1/linear1.cmp
@@ -0,0 +1,73 @@
+Cmp-Mod V01 Created by CvPCB (2011-05-25)-stable date = Monday 22 October 2012 04:10:55 PM IST
+
+BeginCmp
+TimeStamp = /50695730;
+Reference = E1;
+ValeurCmp = 0.5;
+IdModule  = bornier4;
+EndCmp
+
+BeginCmp
+TimeStamp = /5069566A;
+Reference = G1;
+ValeurCmp = 0.5;
+IdModule  = bornier4;
+EndCmp
+
+BeginCmp
+TimeStamp = /506956A6;
+Reference = I1;
+ValeurCmp = DC;
+IdModule  = R1;
+EndCmp
+
+BeginCmp
+TimeStamp = /506955C2;
+Reference = R1;
+ValeurCmp = 1;
+IdModule  = R3;
+EndCmp
+
+BeginCmp
+TimeStamp = /506955C7;
+Reference = R2;
+ValeurCmp = 1;
+IdModule  = R3;
+EndCmp
+
+BeginCmp
+TimeStamp = /506955D8;
+Reference = R3;
+ValeurCmp = 1;
+IdModule  = R3;
+EndCmp
+
+BeginCmp
+TimeStamp = /506955CC;
+Reference = R4;
+ValeurCmp = 1;
+IdModule  = R3;
+EndCmp
+
+BeginCmp
+TimeStamp = /506955D1;
+Reference = R5;
+ValeurCmp = 0.5;
+IdModule  = R3;
+EndCmp
+
+BeginCmp
+TimeStamp = /506955DC;
+Reference = R6;
+ValeurCmp = 1;
+IdModule  = R3;
+EndCmp
+
+BeginCmp
+TimeStamp = /50695694;
+Reference = V1;
+ValeurCmp = DC;
+IdModule  = R1;
+EndCmp
+
+EndListe
diff --git a/OSCAD/Examples/linear1/linear1.net b/OSCAD/Examples/linear1/linear1.net
new file mode 100644
index 0000000..c615a65
--- /dev/null
+++ b/OSCAD/Examples/linear1/linear1.net
@@ -0,0 +1,99 @@
+# EESchema Netlist Version 1.1 created  Monday 22 October 2012 04:10:55 PM IST
+(
+ ( /50695730 bornier4 E1 0.5
+  ( 1 N-000005 )
+  ( 2 N-000006 )
+  ( 3 /a )
+  ( 4 /b )
+ )
+ ( /5069566A bornier4 G1 0.5
+  ( 1 N-000006 )
+  ( 2 /a )
+  ( 3 GND )
+  ( 4 /b )
+ )
+ ( /506956A6 R1 I1 DC
+  ( 1 GND )
+  ( 2 N-000006 )
+ )
+ ( /506955C2 R3 R1 1
+  ( 1 N-000005 )
+  ( 2 N-000004 )
+ )
+ ( /506955C7 R3 R2 1
+  ( 1 N-000005 )
+  ( 2 GND )
+ )
+ ( /506955D8 R3 R3 1
+  ( 1 /b )
+  ( 2 GND )
+ )
+ ( /506955CC R3 R4 1
+  ( 1 /b )
+  ( 2 N-000006 )
+ )
+ ( /506955D1 R3 R5 0.5
+  ( 1 /a )
+  ( 2 /b )
+ )
+ ( /506955DC R3 R6 1
+  ( 1 /a )
+  ( 2 GND )
+ )
+ ( /50695694 R1 V1 DC
+  ( 1 N-000004 )
+  ( 2 GND )
+ )
+)
+*
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