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| author | Jayaram Pai | 2014-05-19 11:02:57 +0530 |
|---|---|---|
| committer | Jayaram Pai | 2014-05-19 11:02:57 +0530 |
| commit | 8377256e7d90aa7ba1cb51f6164e99f81e2eb53c (patch) | |
| tree | 5afcc8e82d7f7d4f6fbff900520bd8f05eb343ca /OSCAD/Examples/RC_ac/RC_ac.cir.out | |
| download | FreeEDA-8377256e7d90aa7ba1cb51f6164e99f81e2eb53c.tar.gz FreeEDA-8377256e7d90aa7ba1cb51f6164e99f81e2eb53c.tar.bz2 FreeEDA-8377256e7d90aa7ba1cb51f6164e99f81e2eb53c.zip | |
initial commit
Diffstat (limited to 'OSCAD/Examples/RC_ac/RC_ac.cir.out')
| -rw-r--r-- | OSCAD/Examples/RC_ac/RC_ac.cir.out | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/OSCAD/Examples/RC_ac/RC_ac.cir.out b/OSCAD/Examples/RC_ac/RC_ac.cir.out new file mode 100644 index 0000000..ad45dbf --- /dev/null +++ b/OSCAD/Examples/RC_ac/RC_ac.cir.out @@ -0,0 +1,15 @@ +* eeschema netlist version 1.1 (spice format) creation date: friday 24 may 2013 01:58:56 pm ist
+
+* Plotting option vplot8_1
+v1 1 0 ac 2
+r1 3 1 1k
+c1 0 3 1u
+
+.ac lin 10 1Hz 10Meg
+
+* Control Statements
+.control
+run
+plot v(1) v(3)
+.endc
+.end
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