initial commit

13 files changed, 1862 insertions, 0 deletions

diff --git a/OSCAD/Examples/BasicGates/$savepcb.brd b/OSCAD/Examples/BasicGates/$savepcb.brd
new file mode 100644
index 0000000..c5b62f8
--- /dev/null
+++ b/OSCAD/Examples/BasicGates/$savepcb.brd
@@ -0,0 +1,84 @@
+PCBNEW-BOARD Version 1 date 6/7/2013 11:31:39 AM

+

+# Created by Pcbnew(2011-04-29 BZR 2986)-stable

+

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+Title ""

+Date "7 jun 2013"

+Rev ""

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diff --git a/OSCAD/Examples/BasicGates/BasicGates-cache.bak b/OSCAD/Examples/BasicGates/BasicGates-cache.bak
new file mode 100644
index 0000000..ba5e5f2
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+++ b/OSCAD/Examples/BasicGates/BasicGates-cache.bak
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+# pulse
+#
+DEF pulse v 0 40 Y Y 1 F N
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+F1 "pulse" -200 -50 60 H V C CNN
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+$FPLIST
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+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "R" 0 0 50 V V C CNN
+$FPLIST
+ R?
+ SM0603
+ SM0805
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+F0 "U" -150 100 50 H V C CNN
+F1 "vplot1" 150 100 50 H V C CNN
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diff --git a/OSCAD/Examples/BasicGates/BasicGates-cache.lib b/OSCAD/Examples/BasicGates/BasicGates-cache.lib
new file mode 100644
index 0000000..90be75b
--- /dev/null
+++ b/OSCAD/Examples/BasicGates/BasicGates-cache.lib
@@ -0,0 +1,331 @@
+EESchema-LIBRARY Version 2.3  Date: Sunday 09 December 2012 08:37:05 AM IST
+#encoding utf-8
+#
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+X ~ 5 -600 -100 370 R 60 60 2 2 I I
+X ~ 6 600 0 300 L 60 60 2 2 O I
+X ~ 8 600 0 300 L 60 60 3 2 O I
+X ~ 9 -600 100 370 R 60 60 3 2 I I
+X ~ 10 -600 -100 370 R 60 60 3 2 I I
+X ~ 11 600 0 300 L 60 60 4 2 O I
+X ~ 12 -600 100 370 R 60 60 4 2 I I
+X ~ 13 -600 -100 370 R 60 60 4 2 I I
+ENDDRAW
+ENDDEF
+#
+# 74LS32
+#
+DEF 74LS32 U 0 30 Y Y 4 F N
+F0 "U" 0 50 60 H V C CNN
+F1 "74LS32" 0 -50 60 H V C CNN
+DRAW
+X GND 7 -200 -200 0 U 40 40 0 0 W N
+X VCC 14 -200 200 0 U 40 40 0 0 W N
+A -470 0 262 495 -495 0 1 0 N -300 199 -300 -198
+A -2 126 326 -897 -225 0 1 0 N 0 -199 299 2
+A 4 -120 320 906 221 0 1 0 N 2 200 300 0
+P 2 0 1 0  -300 -200  0 -200 N
+P 2 0 1 0  -300 200  0 200 N
+X ~ 1 -600 100 370 R 60 60 1 1 I
+X ~ 2 -600 -100 370 R 60 60 1 1 I
+X ~ 3 600 0 300 L 60 60 1 1 O
+X ~ 4 -600 100 370 R 60 60 2 1 I
+X ~ 5 -600 -100 370 R 60 60 2 1 I
+X ~ 6 600 0 300 L 60 60 2 1 O
+X ~ 8 600 0 300 L 60 60 3 1 O
+X ~ 9 -600 100 370 R 60 60 3 1 I
+X ~ 10 -600 -100 370 R 60 60 3 1 I
+X ~ 11 600 0 300 L 60 60 4 1 O
+X ~ 12 -600 100 370 R 60 60 4 1 I
+X ~ 13 -600 -100 370 R 60 60 4 1 I
+A 100 0 200 896 -896 0 2 0 N 101 200 101 -199
+P 4 0 2 0  100 200  -300 200  -300 -200  100 -200 N
+X ~ 1 -600 100 300 R 60 60 1 2 I I
+X ~ 2 -600 -100 300 R 60 60 1 2 I I
+X ~ 3 600 0 300 L 60 60 1 2 O I
+X ~ 4 -600 100 300 R 60 60 2 2 I I
+X ~ 5 -600 -100 300 R 60 60 2 2 I I
+X ~ 6 600 0 300 L 60 60 2 2 O I
+X ~ 8 600 0 300 L 60 60 3 2 O I
+X ~ 9 -600 100 300 R 60 60 3 2 I I
+X ~ 10 -600 -100 300 R 60 60 3 2 I I
+X ~ 11 600 0 300 L 60 60 4 2 O I
+X ~ 12 -600 100 300 R 60 60 4 2 I I
+X ~ 13 -600 -100 300 R 60 60 4 2 I I
+ENDDRAW
+ENDDEF
+#
+# 74LS86
+#
+DEF 74LS86 U 0 30 Y N 4 F N
+F0 "U" 50 50 50 H V C CNN
+F1 "74LS86" 50 -50 40 H V C CNN
+ALIAS 74HC86
+DRAW
+X GND 7 -200 -200 0 U 40 40 0 0 W N
+X VCC 14 -200 200 0 D 40 40 0 0 W N
+A -470 0 262 495 -495 0 1 0 N -300 199 -300 -198
+A -396 -2 281 457 -451 0 1 0 N -200 199 -198 -200
+A -2 126 326 -897 -225 0 1 0 N 0 -199 299 2
+A 4 -120 320 906 221 0 1 0 N 2 200 300 0
+P 2 0 1 0  -200 -200  0 -200 N
+P 2 0 1 0  -200 200  0 200 N
+X IN1 1 -600 100 370 R 60 60 1 1 I
+X IN2 2 -600 -100 370 R 60 60 1 1 I
+X OUT 3 600 0 300 L 60 60 1 1 O
+X IN1 4 -600 100 370 R 60 60 2 1 I
+X IN2 5 -600 -100 370 R 60 60 2 1 I
+X OUT 6 600 0 300 L 60 60 2 1 O
+X OUT 8 600 0 300 L 60 60 3 1 O
+X IN1 9 -600 100 370 R 60 60 3 1 I
+X IN2 10 -600 -100 370 R 60 60 3 1 I
+X OUT 11 600 0 300 L 60 60 4 1 O
+X IN1 12 -600 100 370 R 60 60 4 1 I
+X IN2 13 -600 -100 370 R 60 60 4 1 I
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF ~GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 0 30 H I C CNN
+F1 "GND" 0 -70 30 H I C CNN
+DRAW
+P 4 0 1 0  -50 0  0 -50  50 0  -50 0 N
+X GND 1 0 0 0 U 30 30 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# pulse
+#
+DEF pulse v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "pulse" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -25 -450 501 928 871 0 1 0 N -50 50 0 50
+A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50
+A 75 600 551 -926 -873 0 1 0 N 50 50 100 50
+A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50
+A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50
+A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 270 30 H I C CNN
+F1 "PWR_FLAG" 0 230 30 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 20 20 0 0 w
+P 3 0 1 0  0 0  0 100  0 100 N
+P 5 0 1 0  0 100  -100 150  0 200  100 150  0 100 N
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "R" 0 0 50 V V C CNN
+$FPLIST
+ R?
+ SM0603
+ SM0805
+ R?-*
+$ENDFPLIST
+DRAW
+S -40 150 40 -150 0 1 12 N
+X ~ 1 0 250 100 D 60 60 1 1 P
+X ~ 2 0 -250 100 U 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# vplot8_1
+#
+DEF vplot8_1 U 0 40 Y Y 8 F N
+F0 "U" -150 100 50 H V C CNN
+F1 "vplot8_1" 150 100 50 H V C CNN
+DRAW
+C 0 0 100 0 0 0 N
+X + 1 0 -300 200 U 40 40 1 1 I
+X + 2 0 -300 200 U 40 40 2 1 I
+X + 3 0 -300 200 U 40 40 3 1 I
+X + 4 0 -300 200 U 40 40 4 1 I
+X + 5 0 -300 200 U 40 40 5 1 I
+X + 6 0 -300 200 U 40 40 6 1 I
+X + 7 0 -300 200 U 40 40 7 1 I
+X + 8 0 -300 200 U 40 40 8 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/OSCAD/Examples/BasicGates/BasicGates.bak b/OSCAD/Examples/BasicGates/BasicGates.bak
new file mode 100644
index 0000000..b0c177c
--- /dev/null
+++ b/OSCAD/Examples/BasicGates/BasicGates.bak
@@ -0,0 +1,347 @@
+EESchema Schematic File Version 2  date Sunday 09 December 2012 08:00:09 AM IST
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:analogSpice
+LIBS:converterSpice
+LIBS:digitalSpice
+LIBS:linearSpice
+LIBS:measurementSpice
+LIBS:portSpice
+LIBS:sourcesSpice
+LIBS:BasicGates-cache
+EELAYER 25  0
+EELAYER END
+$Descr A4 11700 8267
+encoding utf-8
+Sheet 1 1
+Title ""
+Date "30 oct 2012"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+Connection ~ 9700 3000
+Wire Wire Line
+	9700 3000 9700 2800
+Wire Wire Line
+	9900 3100 9900 3000
+Wire Wire Line
+	9900 3000 9100 3000
+Wire Wire Line
+	1700 3800 3750 3800
+Wire Wire Line
+	7900 3100 7850 3100
+Wire Wire Line
+	7850 3100 7850 3400
+Wire Wire Line
+	7850 3400 7750 3400
+Connection ~ 5300 2300
+Wire Wire Line
+	5300 2300 5300 3300
+Wire Wire Line
+	5300 3300 5500 3300
+Wire Wire Line
+	5100 3500 5500 3500
+Wire Wire Line
+	7900 2900 7350 2900
+Wire Wire Line
+	7350 2900 7350 2400
+Wire Wire Line
+	7350 2400 7000 2400
+Connection ~ 3750 2200
+Wire Wire Line
+	3900 3400 3750 3400
+Wire Wire Line
+	3750 3400 3750 2200
+Wire Wire Line
+	3850 2200 3650 2200
+Wire Wire Line
+	3650 2200 3650 1700
+Connection ~ 2400 1700
+Wire Wire Line
+	2400 1700 2400 1550
+Connection ~ 2250 1700
+Connection ~ 2000 2900
+Wire Wire Line
+	2000 2900 2000 2700
+Wire Wire Line
+	2250 3800 2250 4150
+Wire Wire Line
+	1700 3800 1700 3950
+Wire Wire Line
+	2250 2500 2250 2900
+Wire Wire Line
+	2250 2900 1750 2900
+Connection ~ 1700 5050
+Wire Wire Line
+	1700 5050 2250 5050
+Wire Wire Line
+	2250 5050 2250 4650
+Wire Wire Line
+	1700 4850 1700 5200
+Wire Wire Line
+	1750 1800 1750 1700
+Wire Wire Line
+	2250 1700 2250 2000
+Wire Wire Line
+	1750 3150 1750 2700
+Connection ~ 1750 2900
+Connection ~ 2250 3800
+Wire Wire Line
+	2400 3800 2400 3600
+Connection ~ 2400 3800
+Wire Wire Line
+	3900 3600 3750 3600
+Wire Wire Line
+	3750 3600 3750 3800
+Wire Wire Line
+	3500 3800 3500 2400
+Wire Wire Line
+	3500 2400 3850 2400
+Connection ~ 3500 3800
+Wire Wire Line
+	5050 2300 5800 2300
+Wire Wire Line
+	6200 2200 6200 1900
+Wire Wire Line
+	5800 2500 5200 2500
+Wire Wire Line
+	5200 2500 5200 3500
+Connection ~ 5200 3500
+Wire Wire Line
+	6700 3400 6850 3400
+Wire Wire Line
+	1750 1700 3650 1700
+Wire Wire Line
+	9900 3600 9900 3900
+Text Notes 9150 2850 0    60   ~ 0
+~A.B
+Text Notes 9050 2850 0    60   ~ 0
++
+Text Notes 8900 2850 0    60   ~ 0
+A.B
+Text Notes 8000 2300 0    60   ~ 0
+~B
+Text Notes 7900 2300 0    60   ~ 0
++
+Text Notes 7750 2300 0    60   ~ 0
+=~A
+Text Notes 7900 3650 0    60   ~ 0
+=A+B
+Text Notes 7850 3500 0    60   ~ 0
+A.B+A+B
+Text Notes 6450 3600 0    60   ~ 0
+~((A.B)+(A+B))
+Text Notes 7100 2300 0    60   ~ 0
+~((A.B).(A+B))
+$Comp
+L 74HC86 U12
+U 1 1 507253B2
+P 8500 3000
+F 0 "U12" H 8550 3050 50  0000 C CNN
+F 1 "74HC86" H 8550 2950 40  0000 C CNN
+	1    8500 3000
+	1    0    0    -1  
+$EndComp
+Text Notes 5150 3650 0    60   ~ 0
+A+B
+Text Notes 5100 2250 0    60   ~ 0
+A.B
+Text Notes 3600 3950 0    60   ~ 0
+B
+Text Notes 3500 1650 0    60   ~ 0
+A
+$Comp
+L 74LS32 U8
+U 1 1 50725446
+P 4500 3500
+F 0 "U8" H 4500 3550 60  0000 C CNN
+F 1 "74LS32" H 4500 3450 60  0000 C CNN
+	1    4500 3500
+	1    0    0    -1  
+$EndComp
+$Comp
+L 74LS08 U7
+U 1 1 50725428
+P 4450 2300
+F 0 "U7" H 4450 2350 60  0000 C CNN
+F 1 "74LS08" H 4450 2250 60  0000 C CNN
+	1    4450 2300
+	1    0    0    -1  
+$EndComp
+$Comp
+L 74HC02 U9
+U 1 1 50725415
+P 6100 3400
+F 0 "U9" H 6100 3450 60  0000 C CNN
+F 1 "74HC02" H 6150 3350 60  0000 C CNN
+	1    6100 3400
+	1    0    0    -1  
+$EndComp
+$Comp
+L 74HC04 U11
+U 1 1 507253DF
+P 7300 3400
+F 0 "U11" H 7450 3500 40  0000 C CNN
+F 1 "74HC04" H 7500 3300 40  0000 C CNN
+	1    7300 3400
+	1    0    0    -1  
+$EndComp
+$Comp
+L 7400 U10
+U 1 1 5072539F
+P 6400 2400
+F 0 "U10" H 6400 2450 60  0000 C CNN
+F 1 "7400" H 6400 2300 60  0000 C CNN
+	1    6400 2400
+	1    0    0    -1  
+$EndComp
+$Comp
+L GND #PWR01
+U 1 1 5072534B
+P 9900 3900
+F 0 "#PWR01" H 9900 3900 30  0001 C CNN
+F 1 "GND" H 9900 3830 30  0001 C CNN
+	1    9900 3900
+	1    0    0    -1  
+$EndComp
+$Comp
+L VPLOT1 U1
+U 1 1 50725278
+P 2400 1250
+F 0 "U1" H 2250 1350 50  0000 C CNN
+F 1 "VPLOT1" H 2550 1350 50  0000 C CNN
+	1    2400 1250
+	1    0    0    -1  
+$EndComp
+$Comp
+L PWR_FLAG #FLG02
+U 1 1 507251F2
+P 2000 2700
+F 0 "#FLG02" H 2000 2970 30  0001 C CNN
+F 1 "PWR_FLAG" H 2000 2930 30  0000 C CNN
+	1    2000 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L GND #PWR03
+U 1 1 507251E5
+P 1750 3150
+F 0 "#PWR03" H 1750 3150 30  0001 C CNN
+F 1 "GND" H 1750 3080 30  0001 C CNN
+	1    1750 3150
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R3
+U 1 1 507251A7
+P 2250 2250
+F 0 "R3" V 2330 2250 50  0000 C CNN
+F 1 "1000" V 2250 2250 50  0000 C CNN
+	1    2250 2250
+	1    0    0    -1  
+$EndComp
+$Comp
+L PULSE v2
+U 1 1 50725192
+P 1750 2250
+F 0 "v2" H 1550 2350 60  0000 C CNN
+F 1 "PULSE" H 1550 2200 60  0000 C CNN
+	1    1750 2250
+	1    0    0    -1  
+$EndComp
+$Comp
+L VPLOT1 U5
+U 1 1 50653344
+P 9700 2500
+F 0 "U5" H 9550 2600 50  0000 C CNN
+F 1 "VPLOT1" H 9850 2600 50  0000 C CNN
+	1    9700 2500
+	1    0    0    -1  
+$EndComp
+$Comp
+L PWR_FLAG #FLG04
+U 1 1 50653022
+P 6200 1900
+F 0 "#FLG04" H 6200 2170 30  0001 C CNN
+F 1 "PWR_FLAG" H 6200 2130 30  0000 C CNN
+	1    6200 1900
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R2
+U 1 1 50652FB6
+P 9900 3350
+F 0 "R2" V 9980 3350 50  0000 C CNN
+F 1 "1000" V 9900 3350 50  0000 C CNN
+	1    9900 3350
+	1    0    0    -1  
+$EndComp
+$Comp
+L VPLOT1 U2
+U 1 1 5061678B
+P 2400 3300
+F 0 "U2" H 2250 3400 50  0000 C CNN
+F 1 "VPLOT1" H 2550 3400 50  0000 C CNN
+	1    2400 3300
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R1
+U 1 1 505C9F25
+P 2250 4400
+F 0 "R1" V 2330 4400 50  0000 C CNN
+F 1 "1000" V 2250 4400 50  0000 C CNN
+	1    2250 4400
+	1    0    0    -1  
+$EndComp
+$Comp
+L GND #PWR05
+U 1 1 505C9EE8
+P 1700 5200
+F 0 "#PWR05" H 1700 5200 30  0001 C CNN
+F 1 "GND" H 1700 5130 30  0001 C CNN
+	1    1700 5200
+	1    0    0    -1  
+$EndComp
+$Comp
+L PULSE v1
+U 1 1 505C9ECF
+P 1700 4400
+F 0 "v1" H 1500 4500 60  0000 C CNN
+F 1 "PULSE" H 1500 4350 60  0000 C CNN
+	1    1700 4400
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/OSCAD/Examples/BasicGates/BasicGates.cir b/OSCAD/Examples/BasicGates/BasicGates.cir
new file mode 100644
index 0000000..839fbc6
--- /dev/null
+++ b/OSCAD/Examples/BasicGates/BasicGates.cir
@@ -0,0 +1,20 @@
+* EESchema Netlist Version 1.1 (Spice format) creation date: Sunday 09 December 2012 08:37:15 AM IST
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+*Sheet Name:/
+U1  8 4 9 VPLOT8_1		
+U12  5 6 9 0 3 74HC86		
+U8  8 4 10 0 3 74LS32		
+U7  8 4 2 0 3 74LS08		
+U9  7 2 10 0 3 74HC02		
+U11  7 6 0 3 74HC04		
+U10  2 10 5 0 3 7400		
+R3  8 0 1000		
+v2  8 0 PULSE		
+R2  9 0 1000		
+R1  4 0 1000		
+v1  4 0 PULSE		
+
+.end
diff --git a/OSCAD/Examples/BasicGates/BasicGates.cir.ckt b/OSCAD/Examples/BasicGates/BasicGates.cir.ckt
new file mode 100644
index 0000000..857c283
--- /dev/null
+++ b/OSCAD/Examples/BasicGates/BasicGates.cir.ckt
@@ -0,0 +1,59 @@
+* eeschema netlist version 1.1 (spice format) creation date: sunday 09 december 2012 08:37:15 am ist
+
+* Plotting option vplot8_1
+* 74hc86
+* 74ls32
+* 74ls08
+* 74hc02
+* 74hc04
+* 7400
+r3  8 0 1000
+v2  8 0 pulse(0 5 0 0 0 0.25e-6 0.5e-6)
+r2  9 0 1000
+r1  4 0 1000
+v1  4 0 pulse(0 5 0 0 0 0.125e-6 0.5e-6)
+a1 [5] [5_in]  u12adc
+a2 [6] [6_in]  u12adc
+a3 [5_in 6_in] 9_out u12
+a4 [9_out] [9]  u12dac
+.model u12 d_xor
+.model u12adc adc_bridge(in_low=0.8 in_high=2.0)
+.model u12dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9)
+a5 [8] [8_in]  u8adc
+a6 [4] [4_in]  u8adc
+a7 [8_in 4_in] 10_out u8
+a8 [10_out] [10]  u8dac
+.model u8 d_or
+.model u8adc adc_bridge(in_low=0.8 in_high=2.0)
+.model u8dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9)
+a9 [8] [8_in]  u7adc
+a10 [4] [4_in]  u7adc
+a11 [8_in 4_in] 2_out u7
+a12 [2_out] [2]  u7dac
+.model u7 d_and
+.model u7adc adc_bridge(in_low=0.8 in_high=2.0)
+.model u7dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9)
+a13 [2] [2_in]  u9adc
+a14 [10] [10_in]  u9adc
+a15 [2_in 10_in] 7_out u9
+a16 [7_out] [7]  u9dac
+.model u9 d_nor
+.model u9adc adc_bridge(in_low=0.8 in_high=2.0)
+.model u9dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9)
+a17 [7] [7_in]  u11adc
+a18 7_in 6_out u11
+a19 [6_out] [6]  u11dac
+.model u11 d_inverter
+.model u11adc adc_bridge(in_low=0.8 in_high=2.0)
+.model u11dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9)
+a20 [2] [2_in]  u10adc
+a21 [10] [10_in]  u10adc
+a22 [2_in 10_in] 5_out u10
+a23 [5_out] [5]  u10dac
+.model u10 d_nand
+.model u10adc adc_bridge(in_low=0.8 in_high=2.0)
+.model u10dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9)
+
+.tran  10e-09 1e-06 0e-00
+.plot .v(8) .v(4) .v(9) .
+.end
diff --git a/OSCAD/Examples/BasicGates/BasicGates.cir.out b/OSCAD/Examples/BasicGates/BasicGates.cir.out
new file mode 100644
index 0000000..4e7ccde
--- /dev/null
+++ b/OSCAD/Examples/BasicGates/BasicGates.cir.out
@@ -0,0 +1,64 @@
+* eeschema netlist version 1.1 (spice format) creation date: sunday 09 december 2012 08:37:15 am ist
+
+* Plotting option vplot8_1
+* 74hc86
+* 74ls32
+* 74ls08
+* 74hc02
+* 74hc04
+* 7400
+r3  8 0 1000
+v2  8 0 pulse(0 5 0 0 0 0.25e-6 0.5e-6)
+r2  9 0 1000
+r1  4 0 1000
+v1  4 0 pulse(0 5 0 0 0 0.125e-6 0.5e-6)
+a1 [5] [5_in]  u12adc
+a2 [6] [6_in]  u12adc
+a3 [5_in 6_in] 9_out u12
+a4 [9_out] [9]  u12dac
+.model u12 d_xor
+.model u12adc adc_bridge(in_low=0.8 in_high=2.0)
+.model u12dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9)
+a5 [8] [8_in]  u8adc
+a6 [4] [4_in]  u8adc
+a7 [8_in 4_in] 10_out u8
+a8 [10_out] [10]  u8dac
+.model u8 d_or
+.model u8adc adc_bridge(in_low=0.8 in_high=2.0)
+.model u8dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9)
+a9 [8] [8_in]  u7adc
+a10 [4] [4_in]  u7adc
+a11 [8_in 4_in] 2_out u7
+a12 [2_out] [2]  u7dac
+.model u7 d_and
+.model u7adc adc_bridge(in_low=0.8 in_high=2.0)
+.model u7dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9)
+a13 [2] [2_in]  u9adc
+a14 [10] [10_in]  u9adc
+a15 [2_in 10_in] 7_out u9
+a16 [7_out] [7]  u9dac
+.model u9 d_nor
+.model u9adc adc_bridge(in_low=0.8 in_high=2.0)
+.model u9dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9)
+a17 [7] [7_in]  u11adc
+a18 7_in 6_out u11
+a19 [6_out] [6]  u11dac
+.model u11 d_inverter
+.model u11adc adc_bridge(in_low=0.8 in_high=2.0)
+.model u11dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9)
+a20 [2] [2_in]  u10adc
+a21 [10] [10_in]  u10adc
+a22 [2_in 10_in] 5_out u10
+a23 [5_out] [5]  u10dac
+.model u10 d_nand
+.model u10adc adc_bridge(in_low=0.8 in_high=2.0)
+.model u10dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9)
+
+.tran  10e-09 1e-06 0e-00
+
+* Control Statements 
+.control
+run
+plot v(8) v(4) v(9) 
+.endc
+.end
diff --git a/OSCAD/Examples/BasicGates/BasicGates.cmp b/OSCAD/Examples/BasicGates/BasicGates.cmp
new file mode 100644
index 0000000..70877a7
--- /dev/null
+++ b/OSCAD/Examples/BasicGates/BasicGates.cmp
@@ -0,0 +1,101 @@
+Cmp-Mod V01 Created by CvPCB (2011-05-25)-stable date = Monday 22 October 2012 05:06:15 PM IST
+
+BeginCmp
+TimeStamp = /505C9F25;
+Reference = R1;
+ValeurCmp = 1000;
+IdModule  = R3;
+EndCmp
+
+BeginCmp
+TimeStamp = /50652FB6;
+Reference = R2;
+ValeurCmp = 1000;
+IdModule  = R3;
+EndCmp
+
+BeginCmp
+TimeStamp = /507251A7;
+Reference = R3;
+ValeurCmp = 1000;
+IdModule  = R3;
+EndCmp
+
+BeginCmp
+TimeStamp = /505FD8A0;
+Reference = U3;
+ValeurCmp = ADC;
+IdModule  = ;
+EndCmp
+
+BeginCmp
+TimeStamp = /505FDC21;
+Reference = U4;
+ValeurCmp = DAC;
+IdModule  = ;
+EndCmp
+
+BeginCmp
+TimeStamp = /50725212;
+Reference = U6;
+ValeurCmp = ADC;
+IdModule  = ;
+EndCmp
+
+BeginCmp
+TimeStamp = /50725428;
+Reference = U7;
+ValeurCmp = 74LS08;
+IdModule  = ;
+EndCmp
+
+BeginCmp
+TimeStamp = /50725446;
+Reference = U8;
+ValeurCmp = 74LS32;
+IdModule  = ;
+EndCmp
+
+BeginCmp
+TimeStamp = /50725415;
+Reference = U9;
+ValeurCmp = 74HC02;
+IdModule  = ;
+EndCmp
+
+BeginCmp
+TimeStamp = /5072539F;
+Reference = U10;
+ValeurCmp = 7400;
+IdModule  = ;
+EndCmp
+
+BeginCmp
+TimeStamp = /507253DF;
+Reference = U11;
+ValeurCmp = 74HC04;
+IdModule  = ;
+EndCmp
+
+BeginCmp
+TimeStamp = /507253B2;
+Reference = U12;
+ValeurCmp = 74HC86;
+IdModule  = ;
+EndCmp
+
+BeginCmp
+TimeStamp = /505C9ECF;
+Reference = v1;
+ValeurCmp = PULSE;
+IdModule  = ;
+EndCmp
+
+BeginCmp
+TimeStamp = /50725192;
+Reference = v2;
+ValeurCmp = PULSE;
+IdModule  = ;
+EndCmp
+
+EndListe
diff --git a/OSCAD/Examples/BasicGates/BasicGates.net b/OSCAD/Examples/BasicGates/BasicGates.net
new file mode 100644
index 0000000..e5b57d3
--- /dev/null
+++ b/OSCAD/Examples/BasicGates/BasicGates.net
@@ -0,0 +1,112 @@
+# EESchema Netlist Version 1.1 created  Monday 22 October 2012 05:06:15 PM IST
+(
+ ( /505C9F25 R3 R1 1000
+  ( 1 N-000006 )
+  ( 2 GND )
+ )
+ ( /50652FB6 R3 R2 1000
+  ( 1 N-000007 )
+  ( 2 GND )
+ )
+ ( /507251A7 R3 R3 1000
+  ( 1 N-000009 )
+  ( 2 GND )
+ )
+ ( /505FD8A0 $noname$ U3 ADC
+  ( 1 N-000006 )
+  ( 2 N-000005 )
+ )
+ ( /505FDC21 $noname$ U4 DAC
+  ( 1 N-000008 )
+  ( 2 N-000007 )
+ )
+ ( /50725212 $noname$ U6 ADC
+  ( 1 N-000009 )
+  ( 2 N-000011 )
+ )
+ ( /50725428 $noname$ U7 74LS08
+  ( 1 N-000011 )
+  ( 2 N-000005 )
+  ( 3 N-000003 )
+  ( 7 GND )
+  ( 14 VCC )
+ )
+ ( /50725446 $noname$ U8 74LS32
+  ( 1 N-000011 )
+  ( 2 N-000005 )
+  ( 3 N-000013 )
+  ( 7 GND )
+  ( 14 VCC )
+ )
+ ( /50725415 $noname$ U9 74HC02
+  ( 1 N-000004 )
+  ( 2 N-000003 )
+  ( 3 N-000013 )
+  ( 7 GND )
+  ( 14 VCC )
+ )
+ ( /5072539F $noname$ U10 7400
+  ( 1 N-000003 )
+  ( 2 N-000013 )
+  ( 3 N-000010 )
+  ( 7 GND )
+  ( 14 VCC )
+ )
+ ( /507253DF $noname$ U11 74HC04
+  ( 1 N-000004 )
+  ( 2 N-000012 )
+  ( 7 GND )
+  ( 14 VCC )
+ )
+ ( /507253B2 $noname$ U12 74HC86
+  ( 1 N-000010 )
+  ( 2 N-000012 )
+  ( 3 N-000008 )
+  ( 7 GND )
+  ( 14 VCC )
+ )
+ ( /505C9ECF $noname$ v1 PULSE
+  ( 1 N-000006 )
+  ( 2 GND )
+ )
+ ( /50725192 $noname$ v2 PULSE
+  ( 1 N-000009 )
+  ( 2 GND )
+ )
+)
+*
+{ Allowed footprints by component:
+$component R1
+ R?
+ SM0603
+ SM0805
+ R?-*
+$endlist
+$component R2
+ R?
+ SM0603
+ SM0805
+ R?-*
+$endlist
+$component R3
+ R?
+ SM0603
+ SM0805
+ R?-*
+$endlist
+$component U9
+ SO14*
+ 14DIP*
+$endlist
+$component U10
+ 14DIP300*
+ SO14*
+$endlist
+$component v1
+ 1_pin
+$endlist
+$component v2
+ 1_pin
+$endlist
+$endfootprintlist
+}
diff --git a/OSCAD/Examples/BasicGates/BasicGates.pro b/OSCAD/Examples/BasicGates/BasicGates.pro
new file mode 100644
index 0000000..067b52d
--- /dev/null
+++ b/OSCAD/Examples/BasicGates/BasicGates.pro
@@ -0,0 +1,71 @@
+update=Monday 22 October 2012 05:04:10 PM IST
+last_client=eeschema
+[eeschema]
+version=1
+LibDir=/home/yogesh/OSCAD/library
+NetFmt=1
+HPGLSpd=20
+HPGLDm=15
+HPGLNum=1
+offX_A4=0
+offY_A4=0
+offX_A3=0
+offY_A3=0
+offX_A2=0
+offY_A2=0
+offX_A1=0
+offY_A1=0
+offX_A0=0
+offY_A0=0
+offX_A=0
+offY_A=0
+offX_B=0
+offY_B=0
+offX_C=0
+offY_C=0
+offX_D=0
+offY_D=0
+offX_E=0
+offY_E=0
+RptD_X=0
+RptD_Y=100
+RptLab=1
+LabSize=60
+[eeschema/libraries]
+LibName1=power
+LibName2=device
+LibName3=transistors
+LibName4=conn
+LibName5=linear
+LibName6=regul
+LibName7=74xx
+LibName8=cmos4000
+LibName9=adc-dac
+LibName10=memory
+LibName11=xilinx
+LibName12=special
+LibName13=microcontrollers
+LibName14=dsp
+LibName15=microchip
+LibName16=analog_switches
+LibName17=motorola
+LibName18=texas
+LibName19=intel
+LibName20=audio
+LibName21=interface
+LibName22=digital-audio
+LibName23=philips
+LibName24=display
+LibName25=cypress
+LibName26=siliconi
+LibName27=opto
+LibName28=atmel
+LibName29=contrib
+LibName30=valves
+LibName31=analogSpice
+LibName32=converterSpice
+LibName33=digitalSpice
+LibName34=linearSpice
+LibName35=measurementSpice
+LibName36=portSpice
+LibName37=sourcesSpice
diff --git a/OSCAD/Examples/BasicGates/BasicGates.proj b/OSCAD/Examples/BasicGates/BasicGates.proj
new file mode 100644
index 0000000..f8a0441
--- /dev/null
+++ b/OSCAD/Examples/BasicGates/BasicGates.proj
@@ -0,0 +1 @@
+schematicFile BasicGates.sch
diff --git a/OSCAD/Examples/BasicGates/BasicGates.sch b/OSCAD/Examples/BasicGates/BasicGates.sch
new file mode 100644
index 0000000..050f6d4
--- /dev/null
+++ b/OSCAD/Examples/BasicGates/BasicGates.sch
@@ -0,0 +1,347 @@
+EESchema Schematic File Version 2  date Sunday 09 December 2012 08:37:05 AM IST
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:analogSpice
+LIBS:converterSpice
+LIBS:digitalSpice
+LIBS:linearSpice
+LIBS:measurementSpice
+LIBS:portSpice
+LIBS:sourcesSpice
+LIBS:BasicGates-cache
+EELAYER 25  0
+EELAYER END
+$Descr A4 11700 8267
+encoding utf-8
+Sheet 1 1
+Title ""
+Date "9 dec 2012"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L VPLOT8_1 U1
+U 3 1 50C3FFE2
+P 9700 2500
+F 0 "U1" H 9550 2600 50  0000 C CNN
+F 1 "VPLOT8_1" H 9850 2600 50  0000 C CNN
+	3    9700 2500
+	1    0    0    -1  
+$EndComp
+$Comp
+L VPLOT8_1 U1
+U 2 1 50C3FFDB
+P 2400 3300
+F 0 "U1" H 2250 3400 50  0000 C CNN
+F 1 "VPLOT8_1" H 2550 3400 50  0000 C CNN
+	2    2400 3300
+	1    0    0    -1  
+$EndComp
+$Comp
+L VPLOT8_1 U1
+U 1 1 50C3FFD3
+P 2400 1250
+F 0 "U1" H 2250 1350 50  0000 C CNN
+F 1 "VPLOT8_1" H 2550 1350 50  0000 C CNN
+	1    2400 1250
+	1    0    0    -1  
+$EndComp
+Connection ~ 9700 3000
+Wire Wire Line
+	9700 3000 9700 2800
+Wire Wire Line
+	9900 3100 9900 3000
+Wire Wire Line
+	9900 3000 9100 3000
+Wire Wire Line
+	1700 3800 3750 3800
+Wire Wire Line
+	7900 3100 7850 3100
+Wire Wire Line
+	7850 3100 7850 3400
+Wire Wire Line
+	7850 3400 7750 3400
+Connection ~ 5300 2300
+Wire Wire Line
+	5300 2300 5300 3300
+Wire Wire Line
+	5300 3300 5500 3300
+Wire Wire Line
+	5100 3500 5500 3500
+Wire Wire Line
+	7900 2900 7350 2900
+Wire Wire Line
+	7350 2900 7350 2400
+Wire Wire Line
+	7350 2400 7000 2400
+Connection ~ 3750 2200
+Wire Wire Line
+	3900 3400 3750 3400
+Wire Wire Line
+	3750 3400 3750 2200
+Wire Wire Line
+	3850 2200 3650 2200
+Wire Wire Line
+	3650 2200 3650 1700
+Connection ~ 2400 1700
+Wire Wire Line
+	2400 1700 2400 1550
+Connection ~ 2250 1700
+Connection ~ 2000 2900
+Wire Wire Line
+	2000 2900 2000 2700
+Wire Wire Line
+	2250 3800 2250 4150
+Wire Wire Line
+	1700 3800 1700 3950
+Wire Wire Line
+	2250 2500 2250 2900
+Wire Wire Line
+	2250 2900 1750 2900
+Connection ~ 1700 5050
+Wire Wire Line
+	1700 5050 2250 5050
+Wire Wire Line
+	2250 5050 2250 4650
+Wire Wire Line
+	1700 4850 1700 5200
+Wire Wire Line
+	1750 1800 1750 1700
+Wire Wire Line
+	2250 1700 2250 2000
+Wire Wire Line
+	1750 3150 1750 2700
+Connection ~ 1750 2900
+Connection ~ 2250 3800
+Wire Wire Line
+	2400 3800 2400 3600
+Connection ~ 2400 3800
+Wire Wire Line
+	3900 3600 3750 3600
+Wire Wire Line
+	3750 3600 3750 3800
+Wire Wire Line
+	3500 3800 3500 2400
+Wire Wire Line
+	3500 2400 3850 2400
+Connection ~ 3500 3800
+Wire Wire Line
+	5050 2300 5800 2300
+Wire Wire Line
+	6200 2200 6200 1900
+Wire Wire Line
+	5800 2500 5200 2500
+Wire Wire Line
+	5200 2500 5200 3500
+Connection ~ 5200 3500
+Wire Wire Line
+	6700 3400 6850 3400
+Wire Wire Line
+	1750 1700 3650 1700
+Wire Wire Line
+	9900 3600 9900 3900
+Text Notes 9150 2850 0    60   ~ 0
+~A.B
+Text Notes 9050 2850 0    60   ~ 0
++
+Text Notes 8900 2850 0    60   ~ 0
+A.B
+Text Notes 8000 2300 0    60   ~ 0
+~B
+Text Notes 7900 2300 0    60   ~ 0
++
+Text Notes 7750 2300 0    60   ~ 0
+=~A
+Text Notes 7900 3650 0    60   ~ 0
+=A+B
+Text Notes 7850 3500 0    60   ~ 0
+A.B+A+B
+Text Notes 6450 3600 0    60   ~ 0
+~((A.B)+(A+B))
+Text Notes 7100 2300 0    60   ~ 0
+~((A.B).(A+B))
+$Comp
+L 74HC86 U12
+U 1 1 507253B2
+P 8500 3000
+F 0 "U12" H 8550 3050 50  0000 C CNN
+F 1 "74HC86" H 8550 2950 40  0000 C CNN
+	1    8500 3000
+	1    0    0    -1  
+$EndComp
+Text Notes 5150 3650 0    60   ~ 0
+A+B
+Text Notes 5100 2250 0    60   ~ 0
+A.B
+Text Notes 3600 3950 0    60   ~ 0
+B
+Text Notes 3500 1650 0    60   ~ 0
+A
+$Comp
+L 74LS32 U8
+U 1 1 50725446
+P 4500 3500
+F 0 "U8" H 4500 3550 60  0000 C CNN
+F 1 "74LS32" H 4500 3450 60  0000 C CNN
+	1    4500 3500
+	1    0    0    -1  
+$EndComp
+$Comp
+L 74LS08 U7
+U 1 1 50725428
+P 4450 2300
+F 0 "U7" H 4450 2350 60  0000 C CNN
+F 1 "74LS08" H 4450 2250 60  0000 C CNN
+	1    4450 2300
+	1    0    0    -1  
+$EndComp
+$Comp
+L 74HC02 U9
+U 1 1 50725415
+P 6100 3400
+F 0 "U9" H 6100 3450 60  0000 C CNN
+F 1 "74HC02" H 6150 3350 60  0000 C CNN
+	1    6100 3400
+	1    0    0    -1  
+$EndComp
+$Comp
+L 74HC04 U11
+U 1 1 507253DF
+P 7300 3400
+F 0 "U11" H 7450 3500 40  0000 C CNN
+F 1 "74HC04" H 7500 3300 40  0000 C CNN
+	1    7300 3400
+	1    0    0    -1  
+$EndComp
+$Comp
+L 7400 U10
+U 1 1 5072539F
+P 6400 2400
+F 0 "U10" H 6400 2450 60  0000 C CNN
+F 1 "7400" H 6400 2300 60  0000 C CNN
+	1    6400 2400
+	1    0    0    -1  
+$EndComp
+$Comp
+L GND #PWR01
+U 1 1 5072534B
+P 9900 3900
+F 0 "#PWR01" H 9900 3900 30  0001 C CNN
+F 1 "GND" H 9900 3830 30  0001 C CNN
+	1    9900 3900
+	1    0    0    -1  
+$EndComp
+$Comp
+L PWR_FLAG #FLG02
+U 1 1 507251F2
+P 2000 2700
+F 0 "#FLG02" H 2000 2970 30  0001 C CNN
+F 1 "PWR_FLAG" H 2000 2930 30  0000 C CNN
+	1    2000 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L GND #PWR03
+U 1 1 507251E5
+P 1750 3150
+F 0 "#PWR03" H 1750 3150 30  0001 C CNN
+F 1 "GND" H 1750 3080 30  0001 C CNN
+	1    1750 3150
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R3
+U 1 1 507251A7
+P 2250 2250
+F 0 "R3" V 2330 2250 50  0000 C CNN
+F 1 "1000" V 2250 2250 50  0000 C CNN
+	1    2250 2250
+	1    0    0    -1  
+$EndComp
+$Comp
+L PULSE v2
+U 1 1 50725192
+P 1750 2250
+F 0 "v2" H 1550 2350 60  0000 C CNN
+F 1 "PULSE" H 1550 2200 60  0000 C CNN
+	1    1750 2250
+	1    0    0    -1  
+$EndComp
+$Comp
+L PWR_FLAG #FLG04
+U 1 1 50653022
+P 6200 1900
+F 0 "#FLG04" H 6200 2170 30  0001 C CNN
+F 1 "PWR_FLAG" H 6200 2130 30  0000 C CNN
+	1    6200 1900
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R2
+U 1 1 50652FB6
+P 9900 3350
+F 0 "R2" V 9980 3350 50  0000 C CNN
+F 1 "1000" V 9900 3350 50  0000 C CNN
+	1    9900 3350
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R1
+U 1 1 505C9F25
+P 2250 4400
+F 0 "R1" V 2330 4400 50  0000 C CNN
+F 1 "1000" V 2250 4400 50  0000 C CNN
+	1    2250 4400
+	1    0    0    -1  
+$EndComp
+$Comp
+L GND #PWR05
+U 1 1 505C9EE8
+P 1700 5200
+F 0 "#PWR05" H 1700 5200 30  0001 C CNN
+F 1 "GND" H 1700 5130 30  0001 C CNN
+	1    1700 5200
+	1    0    0    -1  
+$EndComp
+$Comp
+L PULSE v1
+U 1 1 505C9ECF
+P 1700 4400
+F 0 "v1" H 1500 4500 60  0000 C CNN
+F 1 "PULSE" H 1500 4350 60  0000 C CNN
+	1    1700 4400
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/OSCAD/Examples/BasicGates/analysis b/OSCAD/Examples/BasicGates/analysis
new file mode 100644
index 0000000..bf5e632
--- /dev/null
+++ b/OSCAD/Examples/BasicGates/analysis
@@ -0,0 +1 @@
+.tran  10e-09 1e-06 0e-00