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authorFahim2014-09-09 16:11:17 +0530
committerFahim2014-09-09 16:11:17 +0530
commitc632c1009c9e095135220c809d7c799841f160b3 (patch)
tree3be2def8313164c3bf32799714ba53a4a1326ed6 /FreeEDA/Examples/linear2/linear2.cmp
parente338c2a59389c22b8cca9a78d75e626ae779c405 (diff)
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Subject: Changing all content and name of directory and file to FreeEDA
Description: The content of file,name of directory and file has been changed in the below format. 1. Oscad to FreeEDA 2. OSCAD to FreeEDA 3. oscad to freeeda
Diffstat (limited to 'FreeEDA/Examples/linear2/linear2.cmp')
-rw-r--r--FreeEDA/Examples/linear2/linear2.cmp45
1 files changed, 45 insertions, 0 deletions
diff --git a/FreeEDA/Examples/linear2/linear2.cmp b/FreeEDA/Examples/linear2/linear2.cmp
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+++ b/FreeEDA/Examples/linear2/linear2.cmp
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+Cmp-Mod V01 Created by CvPCB (2011-05-25)-stable date = Tuesday 02 October 2012 12:41:01 AM IST
+
+BeginCmp
+TimeStamp = /5069E78C;
+Reference = H1;
+ValeurCmp = 2;
+IdModule = bornier4;
+EndCmp
+
+BeginCmp
+TimeStamp = /5069E6DB;
+Reference = I1;
+ValeurCmp = DC;
+IdModule = R1;
+EndCmp
+
+BeginCmp
+TimeStamp = /5069E7AC;
+Reference = R1;
+ValeurCmp = 0.2;
+IdModule = R3;
+EndCmp
+
+BeginCmp
+TimeStamp = /5069E7A9;
+Reference = R2;
+ValeurCmp = 0.1;
+IdModule = R3;
+EndCmp
+
+BeginCmp
+TimeStamp = /5069E7A6;
+Reference = R3;
+ValeurCmp = 0.2;
+IdModule = R3;
+EndCmp
+
+BeginCmp
+TimeStamp = /5069E7B0;
+Reference = R4;
+ValeurCmp = 0.1;
+IdModule = R3;
+EndCmp
+
+EndListe