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| author | Fahim | 2014-09-09 16:11:17 +0530 |
|---|---|---|
| committer | Fahim | 2014-09-09 16:11:17 +0530 |
| commit | c632c1009c9e095135220c809d7c799841f160b3 (patch) | |
| tree | 3be2def8313164c3bf32799714ba53a4a1326ed6 /FreeEDA/Examples/RC/RC.cir.out | |
| parent | e338c2a59389c22b8cca9a78d75e626ae779c405 (diff) | |
| download | FreeEDA-c632c1009c9e095135220c809d7c799841f160b3.tar.gz FreeEDA-c632c1009c9e095135220c809d7c799841f160b3.tar.bz2 FreeEDA-c632c1009c9e095135220c809d7c799841f160b3.zip | |
Subject: Changing all content and name of directory and file to FreeEDA
Description: The content of file,name of directory and file has been
changed in the below format.
1. Oscad to FreeEDA
2. OSCAD to FreeEDA
3. oscad to freeeda
Diffstat (limited to 'FreeEDA/Examples/RC/RC.cir.out')
| -rw-r--r-- | FreeEDA/Examples/RC/RC.cir.out | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/FreeEDA/Examples/RC/RC.cir.out b/FreeEDA/Examples/RC/RC.cir.out new file mode 100644 index 0000000..01e68ad --- /dev/null +++ b/FreeEDA/Examples/RC/RC.cir.out @@ -0,0 +1,15 @@ +* eeschema netlist version 1.1 (spice format) creation date: friday 24 may 2013 02:23:51 pm ist
+
+v1 1 0 sine(0 5 300 0 0)
+* Plotting option vplot8_1
+r1 3 1 1k
+c1 0 3 1u
+
+.tran 5e-03 30e-03 0e-00
+
+* Control Statements
+.control
+run
+plot v(1) v(3)
+.endc
+.end
|