diff options
Diffstat (limited to 'board/mx1ads')
| -rwxr-xr-x | board/mx1ads/Makefile | 48 | ||||
| -rwxr-xr-x | board/mx1ads/config.mk | 25 | ||||
| -rwxr-xr-x | board/mx1ads/lowlevel_init.S | 81 | ||||
| -rwxr-xr-x | board/mx1ads/mx1ads.c | 168 | ||||
| -rwxr-xr-x | board/mx1ads/syncflash.c | 322 | ||||
| -rwxr-xr-x | board/mx1ads/u-boot.lds | 58 |
6 files changed, 702 insertions, 0 deletions
diff --git a/board/mx1ads/Makefile b/board/mx1ads/Makefile new file mode 100755 index 0000000..3e805fe --- /dev/null +++ b/board/mx1ads/Makefile @@ -0,0 +1,48 @@ +# +# board/mx1ads/Makefile +# +# (c) Copyright 2004 +# Techware Information Technology, Inc. +# http://www.techware.com.tw/ +# +# Ming-Len Wu <minglen_wu@techware.com.tw> +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := mx1ads.o syncflash.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/mx1ads/config.mk b/board/mx1ads/config.mk new file mode 100755 index 0000000..f6ac40d --- /dev/null +++ b/board/mx1ads/config.mk @@ -0,0 +1,25 @@ +# +# board/mx1ads/config.mk +# +# (c) Copyright 2004 +# Techware Information Technology, Inc. +# http://www.techware.com.tw/ +# +# Ming-Len Wu <minglen_wu@techware.com.tw> +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +TEXT_BASE = 0x08400000 diff --git a/board/mx1ads/lowlevel_init.S b/board/mx1ads/lowlevel_init.S new file mode 100755 index 0000000..09c260d --- /dev/null +++ b/board/mx1ads/lowlevel_init.S @@ -0,0 +1,81 @@ +/* + * board/mx1ads/lowlevel_init.S + * + * (c) Copyright 2004 + * Techware Information Technology, Inc. + * http://www.techware.com.tw/ + * + * Ming-Len Wu <minglen_wu@techware.com.tw> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> + +#define SDCTL0 0x221000 +#define SDCTL1 0x221004 + + +_TEXT_BASE: + .word TEXT_BASE + +.globl lowlevel_init +lowlevel_init: +/* memory controller init */ + + ldr r1, =SDCTL0 + +/* Set Precharge Command */ + + ldr r3, =0x92120200 +/* ldr r3, =0x92120251 +*/ + str r3, [r1] + +/* Issue Precharge All Commad */ + ldr r3, =0x8200000 + ldr r2, [r3] + +/* Set AutoRefresh Command */ + ldr r3, =0xA2120200 + str r3, [r1] + +/* Issue AutoRefresh Command */ + ldr r3, =0x8000000 + ldr r2, [r3] + ldr r2, [r3] + ldr r2, [r3] + ldr r2, [r3] + ldr r2, [r3] + ldr r2, [r3] + ldr r2, [r3] + ldr r2, [r3] + +/* Set Mode Register */ + ldr r3, =0xB2120200 + str r3, [r1] + +/* Issue Mode Register Command */ + ldr r3, =0x08111800 /* Mode Register Value */ + ldr r2, [r3] + +/* Set Normal Mode */ + ldr r3, =0x82124200 + str r3, [r1] + +/* everything is fine now */ + mov pc, lr diff --git a/board/mx1ads/mx1ads.c b/board/mx1ads/mx1ads.c new file mode 100755 index 0000000..5c33ba3 --- /dev/null +++ b/board/mx1ads/mx1ads.c @@ -0,0 +1,168 @@ +/* + * board/mx1ads/mx1ads.c + * + * (c) Copyright 2004 + * Techware Information Technology, Inc. + * http://www.techware.com.tw/ + * + * Ming-Len Wu <minglen_wu@techware.com.tw> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +/*#include <mc9328.h>*/ +#include <asm/arch/imx-regs.h> + +/* ------------------------------------------------------------------------- */ + +#define FCLK_SPEED 1 + +#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */ +#define M_MDIV 0xC3 +#define M_PDIV 0x4 +#define M_SDIV 0x1 +#elif FCLK_SPEED==1 /* Fout = 202.8MHz */ +#define M_MDIV 0xA1 +#define M_PDIV 0x3 +#define M_SDIV 0x1 +#endif + +#define USB_CLOCK 1 + +#if USB_CLOCK==0 +#define U_M_MDIV 0xA1 +#define U_M_PDIV 0x3 +#define U_M_SDIV 0x1 +#elif USB_CLOCK==1 +#define U_M_MDIV 0x48 +#define U_M_PDIV 0x3 +#define U_M_SDIV 0x2 +#endif + +#if 0 + +static inline void delay (unsigned long loops) { + __asm__ volatile ("1:\n" + "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0" (loops)); +} + +#endif + +/* + * Miscellaneous platform dependent initialisations + */ + +void SetAsynchMode(void) { + __asm__ ( + "mrc p15,0,r0,c1,c0,0 \n" + "mov r2, #0xC0000000 \n" + "orr r0,r2,r0 \n" + "mcr p15,0,r0,c1,c0,0 \n" + ); +} + +static u32 mc9328sid; + +int board_init (void) { + + DECLARE_GLOBAL_DATA_PTR; + + volatile unsigned int tmp; + + mc9328sid = SIDR; + + GPCR = 0x000003AB; /* I/O pad driving strength */ + +/* MX1_CS1U = 0x00000A00; */ /* SRAM initialization */ +/* MX1_CS1L = 0x11110601; */ + + MPCTL0 = 0x04632410; /* setting for 150 MHz MCU PLL CLK */ + +/* set FCLK divider 1 (i.e. FCLK to MCU PLL CLK) and + * BCLK divider to 2 (i.e. BCLK to 48 MHz) + */ + CSCR = 0xAF000403; + + CSCR |= 0x00200000; /* Trigger the restart bit(bit 21) */ + CSCR &= 0xFFFF7FFF; /* Program PRESC bit(bit 15) to 0 to divide-by-1 */ + +/* setup cs4 for cs8900 ethernet */ + + CS4U = 0x00000F00; /* Initialize CS4 for CS8900 ethernet */ + CS4L = 0x00001501; + + GIUS(0) &= 0xFF3FFFFF; + GPR(0) &= 0xFF3FFFFF; + + tmp = *(unsigned int *)(0x1500000C); + tmp = *(unsigned int *)(0x1500000C); + + SetAsynchMode(); + + gd->bd->bi_arch_number = MACH_TYPE_MX1ADS; + + gd->bd->bi_boot_params = 0x08000100; /* adress of boot parameters */ + + icache_enable(); + dcache_enable(); + +/* set PERCLKs */ + PCDR = 0x00000055; /* set PERCLKS */ + +/* PERCLK3 is only used by SSI so the SSI driver can set it any value it likes + * PERCLK1 and PERCLK2 are shared so DO NOT change it in any other place + * all sources selected as normal interrupt + */ + +/* MX1_INTTYPEH = 0; + MX1_INTTYPEL = 0; +*/ + return 0; +} + +int board_late_init(void) { + + setenv("stdout", "serial"); + setenv("stderr", "serial"); + + switch (mc9328sid) { + case 0x0005901d : + printf ("MX1ADS board with MC9328 MX1 (0L44N), Silicon ID 0x%08x \n\n",mc9328sid); + break; + case 0x04d4c01d : + printf ("MX1ADS board with MC9328 MXL (1L45N), Silicon ID 0x%08x \n\n",mc9328sid); + break; + case 0x00d4c01d : + printf ("MX1ADS board with MC9328 MXL (2L45N), Silicon ID 0x%08x \n\n",mc9328sid); + break; + + default : + printf ("MX1ADS board with UNKNOWN MC9328 cpu, Silicon ID 0x%08x \n",mc9328sid); + break; + } + return 0; +} + +int dram_init (void) { + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} diff --git a/board/mx1ads/syncflash.c b/board/mx1ads/syncflash.c new file mode 100755 index 0000000..eb7fde5 --- /dev/null +++ b/board/mx1ads/syncflash.c @@ -0,0 +1,322 @@ +/* + * board/mx1ads/syncflash.c + * + * (c) Copyright 2004 + * Techware Information Technology, Inc. + * http://www.techware.com.tw/ + * + * Ming-Len Wu <minglen_wu@techware.com.tw> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +/*#include <mc9328.h>*/ +#include <asm/arch/imx-regs.h> + +typedef unsigned long * p_u32; + +/* 4Mx16x2 IAM=0 CSD1 */ + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* Following Setting is for CSD1 */ +#define SFCTL 0x00221004 +#define reg_SFCTL __REG(SFCTL) + +#define SYNCFLASH_A10 (0x00100000) + +#define CMD_NORMAL (0x81020300) /* Normal Mode */ +#define CMD_PREC (CMD_NORMAL + 0x10000000) /* Precharge Command */ +#define CMD_AUTO (CMD_NORMAL + 0x20000000) /* Auto Refresh Command */ +#define CMD_LMR (CMD_NORMAL + 0x30000000) /* Load Mode Register Command */ +#define CMD_LCR (CMD_NORMAL + 0x60000000) /* LCR Command */ +#define CMD_PROGRAM (CMD_NORMAL + 0x70000000) + +#define MODE_REG_VAL (CFG_FLASH_BASE+0x0008CC00) /* Cas Latency 3 */ + +/* LCR Command */ +#define LCR_READSTATUS (0x0001C000) /* 0x70 */ +#define LCR_ERASE_CONFIRM (0x00008000) /* 0x20 */ +#define LCR_ERASE_NVMODE (0x0000C000) /* 0x30 */ +#define LCR_PROG_NVMODE (0x00028000) /* 0xA0 */ +#define LCR_SR_CLEAR (0x00014000) /* 0x50 */ + +/* Get Status register */ +u32 SF_SR(void) { + u32 tmp,tmp1; + + reg_SFCTL = CMD_PROGRAM; + tmp = __REG(CFG_FLASH_BASE); + + reg_SFCTL = CMD_NORMAL; + + reg_SFCTL = CMD_LCR; /* Activate LCR Mode */ + tmp1 = __REG(CFG_FLASH_BASE + LCR_SR_CLEAR); + + return tmp; +} + +/* check if SyncFlash is ready */ +u8 SF_Ready(void) { + u32 tmp; + + tmp = SF_SR(); + + if ((tmp & 0x00800000) && (tmp & 0x001C0000)) { + printf ("SyncFlash Error code %08x\n",tmp); + }; + + if ((tmp & 0x00000080) && (tmp & 0x0000001C)) { + printf ("SyncFlash Error code %08x\n",tmp); + }; + + if (tmp == 0x00800080) /* Test Bit 7 of SR */ + return 1; + else + return 0; +} + +/* Issue the precharge all command */ +void SF_PrechargeAll(void) { + + u32 tmp; + + reg_SFCTL = CMD_PREC; /* Set Precharge Command */ + tmp = __REG(CFG_FLASH_BASE + SYNCFLASH_A10); /* Issue Precharge All Command */ +} + +/* set SyncFlash to normal mode */ +void SF_Normal(void) { + + SF_PrechargeAll(); + + reg_SFCTL = CMD_NORMAL; +} + +/* Erase SyncFlash */ +void SF_Erase(u32 RowAddress) { + u32 tmp; + + reg_SFCTL = CMD_NORMAL; + tmp = __REG(RowAddress); + + reg_SFCTL = CMD_PREC; + tmp = __REG(RowAddress); + + reg_SFCTL = CMD_LCR; /* Set LCR mode */ + __REG(RowAddress + LCR_ERASE_CONFIRM) = 0; /* Issue Erase Setup Command */ + + reg_SFCTL = CMD_NORMAL; /* return to Normal mode */ + __REG(RowAddress) = 0xD0D0D0D0; /* Confirm */ + + while(!SF_Ready()); +} + +void SF_NvmodeErase(void) { + SF_PrechargeAll(); + + reg_SFCTL = CMD_LCR; /* Set to LCR mode */ + __REG(CFG_FLASH_BASE + LCR_ERASE_NVMODE) = 0; /* Issue Erase Nvmode Reg Command */ + + reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */ + __REG(CFG_FLASH_BASE + LCR_ERASE_NVMODE) = 0xC0C0C0C0; /* Confirm */ + + while(!SF_Ready()); +} + +void SF_NvmodeWrite(void) { + SF_PrechargeAll(); + + reg_SFCTL = CMD_LCR; /* Set to LCR mode */ + __REG(CFG_FLASH_BASE+LCR_PROG_NVMODE) = 0; /* Issue Program Nvmode reg command */ + + reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */ + __REG(CFG_FLASH_BASE+LCR_PROG_NVMODE) = 0xC0C0C0C0; /* Confirm not needed */ +} + +/****************************************************************************************/ + +ulong flash_init(void) { + int i, j; + u32 tmp; + +/* Turn on CSD1 for negating RESETSF of SyncFLash */ + + reg_SFCTL |= 0x80000000; /* enable CSD1 for SyncFlash */ + udelay(200); + + reg_SFCTL = CMD_LMR; /* Set Load Mode Register Command */ + tmp = __REG(MODE_REG_VAL); /* Issue Load Mode Register Command */ + + SF_Normal(); + + i = 0; + + flash_info[i].flash_id = FLASH_MAN_MT | FLASH_MT28S4M16LC; + + flash_info[i].size = FLASH_BANK_SIZE; + flash_info[i].sector_count = CFG_MAX_FLASH_SECT; + + memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + + for (j = 0; j < flash_info[i].sector_count; j++) { + flash_info[i].start[j] = CFG_FLASH_BASE + j * 0x00100000; + } + + flash_protect(FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + monitor_flash_len - 1, + &flash_info[0]); + + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[0]); + + return FLASH_BANK_SIZE; +} + +void flash_print_info (flash_info_t *info) { + + int i; + + switch (info->flash_id & FLASH_VENDMASK) { + case (FLASH_MAN_MT & FLASH_VENDMASK): + printf("Micron: "); + break; + default: + printf("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case (FLASH_MT28S4M16LC & FLASH_TYPEMASK): + printf("2x FLASH_MT28S4M16LC (16MB Total)\n"); + break; + default: + printf("Unknown Chip Type\n"); + return; + break; + } + + printf(" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf(" Sector Start Addresses: "); + + for (i = 0; i < info->sector_count; i++) { + if ((i % 5) == 0) + printf ("\n "); + + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + + printf ("\n"); +} + +/*-----------------------------------------------------------------------*/ + +int flash_erase (flash_info_t *info, int s_first, int s_last) { + int iflag, cflag, prot, sect; + int rc = ERR_OK; + +/* first look for protection bits */ + + if (info->flash_id == FLASH_UNKNOWN) + return ERR_UNKNOWN_FLASH_TYPE; + + if ((s_first < 0) || (s_first > s_last)) + return ERR_INVAL; + + if ((info->flash_id & FLASH_VENDMASK) != (FLASH_MAN_MT & FLASH_VENDMASK)) + return ERR_UNKNOWN_FLASH_VENDOR; + + prot = 0; + + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) + prot++; + } + + if (prot) { + printf("protected!\n"); + return ERR_PROTECTED; + } +/* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + + cflag = icache_status(); + icache_disable(); + iflag = disable_interrupts(); + +/* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last && !ctrlc(); sect++) { + + printf("Erasing sector %2d ... ", sect); + +/* arm simple, non interrupt dependent timer */ + + reset_timer_masked(); + + SF_NvmodeErase(); + SF_NvmodeWrite(); + + SF_Erase(CFG_FLASH_BASE + (0x0100000 * sect)); + SF_Normal(); + + printf("ok.\n"); + } + + if (ctrlc()) + printf("User Interrupt!\n"); + + if (iflag) + enable_interrupts(); + + if (cflag) + icache_enable(); + + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash. + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) { + int i; + + for(i = 0; i < cnt; i += 4) { + + SF_PrechargeAll(); + + reg_SFCTL = CMD_PROGRAM; /* Enter SyncFlash Program mode */ + __REG(addr + i) = __REG((u32)src + i); + + while(!SF_Ready()); + } + + SF_Normal(); + + return ERR_OK; +} diff --git a/board/mx1ads/u-boot.lds b/board/mx1ads/u-boot.lds new file mode 100755 index 0000000..8438f99 --- /dev/null +++ b/board/mx1ads/u-boot.lds @@ -0,0 +1,58 @@ +/* + * board/mx1ads/u-boot.lds + * + * (c) Copyright 2004 + * Techware Information Technology, Inc. + * http://www.techware.com.tw/ + * + * Ming-Len Wu <minglen_wu@techware.com.tw> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm920t/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} |