1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
|
/*++
* linux/drivers/video/wmt/hw/wmt-vpp-reg.h
* WonderMedia video post processor (VPP) driver
*
* Copyright c 2014 WonderMedia Technologies, Inc.
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
* WonderMedia Technologies, Inc.
* 4F, 533, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C
--*/
#ifndef WMT_VPP_REG_H
#define WMT_VPP_REG_H
#define VPP_DAC_SEL_TV 1
#define VPP_DAC_SEL_VGA 0
struct vppm_base_regs {
unsigned int _00; /* 0x00 */
union {
unsigned int val;
struct {
unsigned int _0_7:8;
unsigned int govrh_pvbi:1;
unsigned int govrh_vbis:1;
unsigned int govrh_vbie:1;
unsigned int _11:1;
unsigned int govrh2_pvbi:1;
unsigned int govrh2_vbis:1;
unsigned int govrh2_vbie:1;
unsigned int _15:1;
unsigned int scl_pvbi:1;
unsigned int scl_vbis:1;
unsigned int scl_vbie:1;
unsigned int _19:1;
unsigned int ge_tg:1;
} b;
} int_sts; /* 0x4 */
union {
unsigned int val;
struct {
unsigned int _0_7:8;
unsigned int govrh_pvbi:1;
unsigned int govrh_vbis:1;
unsigned int govrh_vbie:1;
unsigned int _11:1;
unsigned int govrh2_pvbi:1;
unsigned int govrh2_vbis:1;
unsigned int govrh2_vbie:1;
unsigned int _15:1;
unsigned int scl_pvbi:1;
unsigned int scl_vbis:1;
unsigned int scl_vbie:1;
unsigned int _19:1;
unsigned int ge_tg:1;
} b;
} int_en; /* 0x8 */
unsigned int watch_sel; /* 0x0C */
union {
unsigned int val;
struct {
unsigned int scl:1;
unsigned int _1_7:7;
unsigned int vid:1;
unsigned int _9_15:7;
unsigned int ge:1;
} b;
} sw_reset1; /* 0x10 */
union {
unsigned int val;
struct {
unsigned int govrh:1;
unsigned int _1_3:3;
unsigned int lvds:1;
unsigned int _5_7:3;
unsigned int dvo:1;
unsigned int dvo2:1;
unsigned int _10_11:2;
unsigned int cec:1;
} b;
} sw_reset2; /* 0x14 */
unsigned int dac_sel; /* 0x18 */
union {
unsigned int val;
struct {
unsigned int hdmi:1;
unsigned int _1_7:7;
unsigned int ddc:1;
unsigned int _9_15:7;
unsigned int hdmi2:1;
} b;
} sw_reset3; /* 0x1C */
union {
unsigned int val;
struct {
unsigned int disable:1;
unsigned int _1_7:7;
unsigned int csi_act_lane_sel:1; /*0-lane 0/1,1-2/3*/
} b;
} sscg; /* 0x20 */
};
#define REG_VPP_BEGIN (VPP_BASE_ADDR + 0x00)
#define REG_VPP_END (VPP_BASE_ADDR + 0x28)
#ifndef VPPM_C
extern HW_REG struct vppm_base_regs *vppm_regs;
#endif
#endif /* WMT_VPP_REG_H */
|
