diff options
Diffstat (limited to 'drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e')
19 files changed, 10375 insertions, 0 deletions
diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/Hal8188EFWImg_CE.c b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/Hal8188EFWImg_CE.c new file mode 100755 index 00000000..815a357b --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/Hal8188EFWImg_CE.c @@ -0,0 +1,892 @@ +/******************************************************************************
+*
+* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms of version 2 of the GNU General Public License as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful, but WITHOUT
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+* more details.
+*
+* You should have received a copy of the GNU General Public License along with
+* this program; if not, write to the Free Software Foundation, Inc.,
+* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+*
+*
+******************************************************************************/
+#include "../odm_precomp.h"
+
+const u8 Rtl8188EFwImgArray[Rtl8188EFWImgArrayLength] = {
+0xE1, 0x88, 0x10, 0x00, 0x0B, 0x00, 0x01, 0x00, 0x01, 0x21, 0x11, 0x27, 0x30, 0x36, 0x00, 0x00,
+0x2D, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x02, 0x45, 0x4E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0xC1, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0xA1, 0xE6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x56, 0xF7, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0xC2, 0xAF, 0x80, 0xFE, 0x32, 0x12, 0x42, 0x04, 0x85, 0xD0, 0x0B, 0x75, 0xD0, 0x08, 0xAA, 0xE0,
+0xC2, 0x8C, 0xE5, 0x8A, 0x24, 0x67, 0xF5, 0x8A, 0xE5, 0x8C, 0x34, 0x79, 0xF5, 0x8C, 0xD2, 0x8C,
+0xEC, 0x24, 0x89, 0xF8, 0xE6, 0xBC, 0x03, 0x02, 0x74, 0xFF, 0xC3, 0x95, 0x81, 0xB4, 0x40, 0x00,
+0x40, 0xCE, 0x79, 0x04, 0x78, 0x80, 0x16, 0xE6, 0x08, 0x70, 0x0B, 0xC2, 0xAF, 0xE6, 0x30, 0xE1,
+0x03, 0x44, 0x18, 0xF6, 0xD2, 0xAF, 0x08, 0xD9, 0xED, 0xEA, 0x8B, 0xD0, 0x22, 0xE5, 0x0C, 0xFF,
+0x23, 0x24, 0x81, 0xF8, 0x0F, 0x08, 0x08, 0xBF, 0x04, 0x04, 0x7F, 0x00, 0x78, 0x81, 0xE6, 0x30,
+0xE4, 0xF2, 0x00, 0xE5, 0x0C, 0xC3, 0x9F, 0x50, 0x20, 0x05, 0x0C, 0x74, 0x88, 0x25, 0x0C, 0xF8,
+0xE6, 0xFD, 0xA6, 0x81, 0x08, 0xE6, 0xAE, 0x0C, 0xBE, 0x03, 0x02, 0x74, 0xFF, 0xCD, 0xF8, 0xE8,
+0x6D, 0x60, 0xE0, 0x08, 0xE6, 0xC0, 0xE0, 0x80, 0xF6, 0xE5, 0x0C, 0xD3, 0x9F, 0x40, 0x27, 0xE5,
+0x0C, 0x24, 0x89, 0xF8, 0xE6, 0xAE, 0x0C, 0xBE, 0x03, 0x02, 0x74, 0xFF, 0xFD, 0x18, 0xE6, 0xCD,
+0xF8, 0xE5, 0x81, 0x6D, 0x60, 0x06, 0xD0, 0xE0, 0xF6, 0x18, 0x80, 0xF5, 0xE5, 0x0C, 0x24, 0x88,
+0xC8, 0xF6, 0x15, 0x0C, 0x80, 0xD3, 0xE5, 0x0C, 0x23, 0x24, 0x81, 0xF8, 0x7F, 0x04, 0xC2, 0xAF,
+0xE6, 0x30, 0xE0, 0x03, 0x10, 0xE2, 0x0C, 0x7F, 0x00, 0x30, 0xE1, 0x07, 0x30, 0xE3, 0x04, 0x7F,
+0x08, 0x54, 0xF4, 0x54, 0x7C, 0xC6, 0xD2, 0xAF, 0x54, 0x80, 0x42, 0x07, 0x22, 0x78, 0x88, 0xA6,
+0x81, 0x74, 0x03, 0x60, 0x06, 0xFF, 0x08, 0x76, 0xFF, 0xDF, 0xFB, 0x7F, 0x04, 0xE4, 0x78, 0x80,
+0xF6, 0x08, 0xF6, 0x08, 0xDF, 0xFA, 0x78, 0x81, 0x76, 0x30, 0x90, 0x45, 0xDE, 0x74, 0x01, 0x93,
+0xC0, 0xE0, 0xE4, 0x93, 0xC0, 0xE0, 0x43, 0x89, 0x01, 0x75, 0x8A, 0x60, 0x75, 0x8C, 0x79, 0xD2,
+0x8C, 0xD2, 0xAF, 0x22, 0x03, 0xEF, 0xD3, 0x94, 0x03, 0x40, 0x03, 0x7F, 0xFF, 0x22, 0x74, 0x81,
+0x2F, 0x2F, 0xF8, 0xE6, 0x20, 0xE5, 0xF4, 0xC2, 0xAF, 0xE6, 0x44, 0x30, 0xF6, 0xD2, 0xAF, 0xAE,
+0x0C, 0xEE, 0xC3, 0x9F, 0x50, 0x21, 0x0E, 0x74, 0x88, 0x2E, 0xF8, 0xE6, 0xF9, 0x08, 0xE6, 0x18,
+0xBE, 0x03, 0x02, 0x74, 0xFF, 0xFD, 0xED, 0x69, 0x60, 0x09, 0x09, 0xE7, 0x19, 0x19, 0xF7, 0x09,
+0x09, 0x80, 0xF3, 0x16, 0x16, 0x80, 0xDA, 0xEE, 0xD3, 0x9F, 0x40, 0x04, 0x05, 0x81, 0x05, 0x81,
+0xEE, 0xD3, 0x9F, 0x40, 0x22, 0x74, 0x88, 0x2E, 0xF8, 0x08, 0xE6, 0xF9, 0xEE, 0xB5, 0x0C, 0x02,
+0xA9, 0x81, 0x18, 0x06, 0x06, 0xE6, 0xFD, 0xED, 0x69, 0x60, 0x09, 0x19, 0x19, 0xE7, 0x09, 0x09,
+0xF7, 0x19, 0x80, 0xF3, 0x1E, 0x80, 0xD9, 0xEF, 0x24, 0x88, 0xF8, 0xE6, 0x04, 0xF8, 0xEF, 0x2F,
+0x04, 0x90, 0x45, 0xDE, 0x93, 0xF6, 0x08, 0xEF, 0x2F, 0x93, 0xF6, 0x7F, 0x00, 0x22, 0xEF, 0xD3,
+0x94, 0x03, 0x40, 0x03, 0x7F, 0xFF, 0x22, 0xEF, 0x23, 0x24, 0x81, 0xF8, 0xE6, 0x30, 0xE5, 0xF4,
+0xC2, 0xAF, 0xE6, 0x54, 0x8C, 0xF6, 0xD2, 0xAF, 0xE5, 0x0C, 0xB5, 0x07, 0x0A, 0x74, 0x88, 0x2F,
+0xF8, 0xE6, 0xF5, 0x81, 0x02, 0x42, 0x4D, 0x50, 0x2E, 0x74, 0x89, 0x2F, 0xF8, 0xE6, 0xBF, 0x03,
+0x02, 0x74, 0xFF, 0xFD, 0x18, 0xE6, 0xF9, 0x74, 0x88, 0x2F, 0xF8, 0xFB, 0xE6, 0xFC, 0xE9, 0x6C,
+0x60, 0x08, 0xA8, 0x05, 0xE7, 0xF6, 0x1D, 0x19, 0x80, 0xF4, 0xA8, 0x03, 0xA6, 0x05, 0x1F, 0xE5,
+0x0C, 0xB5, 0x07, 0xE3, 0x7F, 0x00, 0x22, 0x74, 0x89, 0x2F, 0xF8, 0xE6, 0xFD, 0x18, 0x86, 0x01,
+0x0F, 0x74, 0x88, 0x2F, 0xF8, 0xA6, 0x01, 0x08, 0x86, 0x04, 0xE5, 0x0C, 0xB5, 0x07, 0x02, 0xAC,
+0x81, 0xED, 0x6C, 0x60, 0x08, 0x0D, 0x09, 0xA8, 0x05, 0xE6, 0xF7, 0x80, 0xF4, 0xE5, 0x0C, 0xB5,
+0x07, 0xDE, 0x89, 0x81, 0x7F, 0x00, 0x22, 0xEF, 0xD3, 0x94, 0x03, 0x40, 0x03, 0x7F, 0xFF, 0x22,
+0xEF, 0x23, 0x24, 0x81, 0xF8, 0xC2, 0xAF, 0xE6, 0x30, 0xE5, 0x05, 0x30, 0xE0, 0x02, 0xD2, 0xE4,
+0xD2, 0xE2, 0xC6, 0xD2, 0xAF, 0x7F, 0x00, 0x30, 0xE2, 0x01, 0x0F, 0x02, 0x42, 0x4C, 0x8F, 0xF0,
+0xE4, 0xFF, 0xFE, 0xE5, 0x0C, 0x23, 0x24, 0x80, 0xF8, 0xC2, 0xA9, 0x30, 0xF7, 0x0D, 0x7F, 0x08,
+0xE6, 0x60, 0x0B, 0x2D, 0xF6, 0x60, 0x30, 0x50, 0x2E, 0x80, 0x07, 0x30, 0xF1, 0x06, 0xED, 0xF6,
+0x60, 0x25, 0x7E, 0x02, 0x08, 0x30, 0xF0, 0x10, 0xC2, 0xAF, 0xE6, 0x10, 0xE7, 0x23, 0x0E, 0x30,
+0xE2, 0x0C, 0xD2, 0xAF, 0x7F, 0x04, 0x80, 0x12, 0xC2, 0xAF, 0xE6, 0x10, 0xE7, 0x13, 0x54, 0xEC,
+0x4E, 0xF6, 0xD2, 0xAF, 0x02, 0x42, 0x4D, 0x7F, 0x08, 0x08, 0xEF, 0x44, 0x83, 0xF4, 0xC2, 0xAF,
+0x56, 0xC6, 0xD2, 0xAF, 0x54, 0x80, 0x4F, 0xFF, 0x22, 0xC5, 0xF0, 0xF8, 0xA3, 0xE0, 0x28, 0xF0,
+0xC5, 0xF0, 0xF8, 0xE5, 0x82, 0x15, 0x82, 0x70, 0x02, 0x15, 0x83, 0xE0, 0x38, 0xF0, 0x22, 0xEF,
+0x5B, 0xFF, 0xEE, 0x5A, 0xFE, 0xED, 0x59, 0xFD, 0xEC, 0x58, 0xFC, 0x22, 0xEF, 0x4B, 0xFF, 0xEE,
+0x4A, 0xFE, 0xED, 0x49, 0xFD, 0xEC, 0x48, 0xFC, 0x22, 0xE0, 0xFC, 0xA3, 0xE0, 0xFD, 0xA3, 0xE0,
+0xFE, 0xA3, 0xE0, 0xFF, 0x22, 0xE2, 0xFC, 0x08, 0xE2, 0xFD, 0x08, 0xE2, 0xFE, 0x08, 0xE2, 0xFF,
+0x22, 0xE2, 0xFB, 0x08, 0xE2, 0xF9, 0x08, 0xE2, 0xFA, 0x08, 0xE2, 0xCB, 0xF8, 0x22, 0xEC, 0xF2,
+0x08, 0xED, 0xF2, 0x08, 0xEE, 0xF2, 0x08, 0xEF, 0xF2, 0x22, 0xA4, 0x25, 0x82, 0xF5, 0x82, 0xE5,
+0xF0, 0x35, 0x83, 0xF5, 0x83, 0x22, 0xE0, 0xFB, 0xA3, 0xE0, 0xFA, 0xA3, 0xE0, 0xF9, 0x22, 0xEB,
+0xF0, 0xA3, 0xEA, 0xF0, 0xA3, 0xE9, 0xF0, 0x22, 0xD0, 0x83, 0xD0, 0x82, 0xF8, 0xE4, 0x93, 0x70,
+0x12, 0x74, 0x01, 0x93, 0x70, 0x0D, 0xA3, 0xA3, 0x93, 0xF8, 0x74, 0x01, 0x93, 0xF5, 0x82, 0x88,
+0x83, 0xE4, 0x73, 0x74, 0x02, 0x93, 0x68, 0x60, 0xEF, 0xA3, 0xA3, 0xA3, 0x80, 0xDF, 0x02, 0x45,
+0x8C, 0x02, 0x42, 0xDD, 0xE4, 0x93, 0xA3, 0xF8, 0xE4, 0x93, 0xA3, 0x40, 0x03, 0xF6, 0x80, 0x01,
+0xF2, 0x08, 0xDF, 0xF4, 0x80, 0x29, 0xE4, 0x93, 0xA3, 0xF8, 0x54, 0x07, 0x24, 0x0C, 0xC8, 0xC3,
+0x33, 0xC4, 0x54, 0x0F, 0x44, 0x20, 0xC8, 0x83, 0x40, 0x04, 0xF4, 0x56, 0x80, 0x01, 0x46, 0xF6,
+0xDF, 0xE4, 0x80, 0x0B, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x90, 0x45, 0xD1, 0xE4,
+0x7E, 0x01, 0x93, 0x60, 0xBC, 0xA3, 0xFF, 0x54, 0x3F, 0x30, 0xE5, 0x09, 0x54, 0x1F, 0xFE, 0xE4,
+0x93, 0xA3, 0x60, 0x01, 0x0E, 0xCF, 0x54, 0xC0, 0x25, 0xE0, 0x60, 0xA8, 0x40, 0xB8, 0xE4, 0x93,
+0xA3, 0xFA, 0xE4, 0x93, 0xA3, 0xF8, 0xE4, 0x93, 0xA3, 0xC8, 0xC5, 0x82, 0xC8, 0xCA, 0xC5, 0x83,
+0xCA, 0xF0, 0xA3, 0xC8, 0xC5, 0x82, 0xC8, 0xCA, 0xC5, 0x83, 0xCA, 0xDF, 0xE9, 0xDE, 0xE7, 0x80,
+0xBE, 0x00, 0x41, 0x82, 0x09, 0x00, 0x41, 0x82, 0x0A, 0x00, 0x41, 0x82, 0x17, 0x00, 0x59, 0xE2,
+0x5C, 0x24, 0x5E, 0x5D, 0x5F, 0xA1, 0xC0, 0xE0, 0xC0, 0xF0, 0xC0, 0x83, 0xC0, 0x82, 0xC0, 0xD0,
+0x75, 0xD0, 0x00, 0xC0, 0x00, 0xC0, 0x01, 0xC0, 0x02, 0xC0, 0x03, 0xC0, 0x04, 0xC0, 0x05, 0xC0,
+0x06, 0xC0, 0x07, 0x90, 0x01, 0xC4, 0x74, 0xE6, 0xF0, 0x74, 0x45, 0xA3, 0xF0, 0xD1, 0x35, 0x74,
+0xE6, 0x04, 0x90, 0x01, 0xC4, 0xF0, 0x74, 0x45, 0xA3, 0xF0, 0xD0, 0x07, 0xD0, 0x06, 0xD0, 0x05,
+0xD0, 0x04, 0xD0, 0x03, 0xD0, 0x02, 0xD0, 0x01, 0xD0, 0x00, 0xD0, 0xD0, 0xD0, 0x82, 0xD0, 0x83,
+0xD0, 0xF0, 0xD0, 0xE0, 0x32, 0x90, 0x00, 0x54, 0xE0, 0x55, 0x35, 0xF5, 0x39, 0xA3, 0xE0, 0x55,
+0x36, 0xF5, 0x3A, 0xA3, 0xE0, 0x55, 0x37, 0xF5, 0x3B, 0xA3, 0xE0, 0x55, 0x38, 0xF5, 0x3C, 0xAD,
+0x39, 0x7F, 0x54, 0x12, 0x32, 0x1E, 0xAD, 0x3A, 0x7F, 0x55, 0x12, 0x32, 0x1E, 0xAD, 0x3B, 0x7F,
+0x56, 0x12, 0x32, 0x1E, 0xAD, 0x3C, 0x7F, 0x57, 0x12, 0x32, 0x1E, 0x53, 0x91, 0xEF, 0x22, 0xC0,
+0xE0, 0xC0, 0xF0, 0xC0, 0x83, 0xC0, 0x82, 0xC0, 0xD0, 0x75, 0xD0, 0x00, 0xC0, 0x00, 0xC0, 0x01,
+0xC0, 0x02, 0xC0, 0x03, 0xC0, 0x04, 0xC0, 0x05, 0xC0, 0x06, 0xC0, 0x07, 0x90, 0x01, 0xC4, 0x74,
+0x6F, 0xF0, 0x74, 0x46, 0xA3, 0xF0, 0x12, 0x6C, 0x78, 0xE5, 0x41, 0x30, 0xE4, 0x04, 0x7F, 0x02,
+0x91, 0x27, 0xE5, 0x41, 0x30, 0xE6, 0x03, 0x12, 0x6C, 0xD5, 0xE5, 0x43, 0x30, 0xE0, 0x03, 0x12,
+0x51, 0xC2, 0xE5, 0x43, 0x30, 0xE1, 0x03, 0x12, 0x4D, 0x0C, 0xE5, 0x43, 0x30, 0xE2, 0x03, 0x12,
+0x4C, 0xC1, 0xE5, 0x43, 0x30, 0xE3, 0x03, 0x12, 0x6C, 0xE2, 0xE5, 0x43, 0x30, 0xE4, 0x03, 0x12,
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+0xE0, 0x44, 0x08, 0xF0, 0x22, 0x12, 0x4E, 0xAB, 0xEF, 0x64, 0x01, 0x60, 0x08, 0x90, 0x01, 0xB8,
+0x74, 0x01, 0xF0, 0x80, 0x67, 0x90, 0x81, 0x2B, 0xE0, 0xFF, 0x54, 0x03, 0x60, 0x08, 0x90, 0x01,
+0xB8, 0x74, 0x02, 0xF0, 0x80, 0x56, 0x90, 0x81, 0x29, 0xE0, 0xFE, 0xE4, 0xC3, 0x9E, 0x50, 0x08,
+0x90, 0x01, 0xB8, 0x74, 0x04, 0xF0, 0x80, 0x44, 0xEF, 0x30, 0xE2, 0x08, 0x90, 0x01, 0xB8, 0x74,
+0x08, 0xF0, 0x80, 0x38, 0x90, 0x81, 0x2B, 0xE0, 0x30, 0xE4, 0x08, 0x90, 0x01, 0xB8, 0x74, 0x10,
+0xF0, 0x80, 0x29, 0x90, 0x81, 0x25, 0xE0, 0x13, 0x13, 0x54, 0x3F, 0x20, 0xE0, 0x08, 0x90, 0x01,
+0xB8, 0x74, 0x20, 0xF0, 0x80, 0x16, 0x90, 0x81, 0x3E, 0xE0, 0x60, 0x08, 0x90, 0x01, 0xB8, 0x74,
+0x80, 0xF0, 0x80, 0x08, 0x90, 0x01, 0xB8, 0xE4, 0xF0, 0x7F, 0x01, 0x22, 0x90, 0x01, 0xB9, 0x74,
+0x04, 0xF0, 0x7F, 0x00, 0x22, 0xEF, 0x60, 0x42, 0x90, 0x80, 0xDE, 0xE0, 0x64, 0x01, 0x70, 0x3A,
+0x90, 0x81, 0x25, 0xE0, 0x54, 0xFE, 0xF0, 0x90, 0x05, 0x22, 0x74, 0x0F, 0xF0, 0x90, 0x06, 0x04,
+0xE0, 0x54, 0xBF, 0xF0, 0xE4, 0xFF, 0x12, 0x4F, 0x0D, 0xBF, 0x01, 0x12, 0x90, 0x81, 0x24, 0xE0,
+0x44, 0x40, 0xF0, 0x90, 0x81, 0x2A, 0x74, 0x06, 0xF0, 0x90, 0x81, 0x23, 0xF0, 0x22, 0x90, 0x01,
+0xB9, 0x74, 0x01, 0xF0, 0x90, 0x01, 0xB8, 0x74, 0x08, 0xF0, 0x22, 0x90, 0x05, 0x22, 0x74, 0x6F,
+0xF0, 0x90, 0x05, 0x27, 0xE0, 0x54, 0xBF, 0xF0, 0x90, 0x81, 0x2A, 0x74, 0x02, 0xF0, 0x90, 0x81,
+0x23, 0xF0, 0x22, 0x12, 0x54, 0x65, 0x90, 0x81, 0x2A, 0x74, 0x0C, 0xF0, 0x90, 0x81, 0x23, 0xF0,
+0x22, 0x90, 0x81, 0x24, 0xE0, 0xFF, 0x13, 0x13, 0x54, 0x3F, 0x30, 0xE0, 0x11, 0xEF, 0x54, 0xFB,
+0xF0, 0x90, 0x81, 0x2B, 0xE0, 0x54, 0xFD, 0xF0, 0x54, 0x07, 0x70, 0x42, 0x80, 0x3D, 0x90, 0x81,
+0x30, 0xE0, 0x04, 0xF0, 0x90, 0x81, 0x2B, 0xE0, 0x54, 0xEF, 0xF0, 0x90, 0x81, 0x30, 0xE0, 0xFF,
+0xB4, 0x01, 0x02, 0x80, 0x04, 0xEF, 0xB4, 0x02, 0x06, 0x90, 0x05, 0x58, 0xE0, 0x04, 0xF0, 0x90,
+0x81, 0x38, 0xE0, 0xFF, 0x90, 0x81, 0x30, 0xE0, 0xD3, 0x9F, 0x40, 0x0F, 0x90, 0x80, 0xDE, 0xE0,
+0xB4, 0x01, 0x0B, 0x90, 0x81, 0x25, 0xE0, 0x54, 0xFB, 0xF0, 0x22, 0x12, 0x47, 0x2A, 0x22, 0x22,
+0x90, 0x05, 0x2B, 0xE0, 0x7F, 0x00, 0x30, 0xE7, 0x02, 0x7F, 0x01, 0x22, 0x90, 0x05, 0x22, 0x74,
+0xFF, 0xF0, 0x90, 0x05, 0x27, 0xE0, 0x44, 0x40, 0xF0, 0x90, 0x81, 0x22, 0x74, 0x03, 0xF0, 0x22,
+0x90, 0x05, 0x27, 0xE0, 0x44, 0x40, 0xF0, 0x12, 0x49, 0xDD, 0x90, 0x81, 0x22, 0x74, 0x02, 0xF0,
+0x22, 0x12, 0x49, 0xE3, 0x90, 0x81, 0x22, 0x74, 0x02, 0xF0, 0x22, 0x90, 0x05, 0x22, 0x74, 0x6F,
+0xF0, 0x90, 0x05, 0x27, 0xE0, 0x54, 0xBF, 0xF0, 0x90, 0x81, 0x22, 0x74, 0x04, 0xF0, 0x22, 0xAE,
+0x07, 0x12, 0x51, 0x73, 0xBF, 0x01, 0x12, 0x90, 0x81, 0x23, 0xE0, 0x64, 0x02, 0x60, 0x0A, 0xAF,
+0x06, 0x7D, 0x01, 0x12, 0x47, 0x3D, 0x7F, 0x01, 0x22, 0x7F, 0x00, 0x22, 0x90, 0x01, 0x57, 0xE0,
+0x60, 0x48, 0xE4, 0xF0, 0x90, 0x01, 0x3C, 0x74, 0x02, 0xF0, 0x90, 0x81, 0x24, 0xE0, 0xFF, 0x13,
+0x13, 0x54, 0x3F, 0x30, 0xE0, 0x0C, 0xEF, 0x54, 0xFB, 0xF0, 0x90, 0x81, 0x2B, 0xE0, 0x54, 0xFD,
+0xF0, 0x22, 0x90, 0x81, 0x30, 0xE0, 0x04, 0xF0, 0x90, 0x81, 0x2B, 0xE0, 0x54, 0xEF, 0xF0, 0x90,
+0x81, 0x38, 0xE0, 0xFF, 0x90, 0x81, 0x30, 0xE0, 0xD3, 0x9F, 0x40, 0x0E, 0x90, 0x80, 0xDE, 0xE0,
+0xB4, 0x01, 0x07, 0x90, 0x81, 0x25, 0xE0, 0x54, 0xFB, 0xF0, 0x22, 0x90, 0x80, 0x3F, 0xE0, 0xFF,
+0x7D, 0x01, 0x12, 0x6D, 0x69, 0x8E, 0x54, 0x8F, 0x55, 0xAD, 0x55, 0xAC, 0x54, 0xAF, 0x53, 0x12,
+0x4F, 0x82, 0xAF, 0x55, 0xAE, 0x54, 0x90, 0x04, 0x80, 0xE0, 0x54, 0x0F, 0xFD, 0xAC, 0x07, 0x74,
+0x11, 0x2C, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x44, 0x01, 0xF0, 0x74, 0x11, 0x2C,
+0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x54, 0xFB, 0xF0, 0xAC, 0x07, 0x74, 0x16, 0x2C,
+0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x44, 0xFA, 0xF0, 0x74, 0x15, 0x2C, 0xF5, 0x82,
+0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x44, 0x1F, 0xF0, 0xAC, 0x07, 0x74, 0x06, 0x2C, 0xF5, 0x82,
+0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x44, 0x0F, 0xF0, 0x90, 0x04, 0x53, 0xE4, 0xF0, 0x90, 0x04,
+0x52, 0xF0, 0x90, 0x04, 0x51, 0x74, 0xFF, 0xF0, 0x90, 0x04, 0x50, 0x74, 0xFD, 0xF0, 0x74, 0x14,
+0x2C, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x54, 0xC0, 0x4D, 0xFD, 0x74, 0x14, 0x2F,
+0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xED, 0xF0, 0x22, 0xAB, 0x07, 0xAA, 0x06, 0xED, 0x2B,
+0xFB, 0xE4, 0x3A, 0xFA, 0xC3, 0x90, 0x80, 0xDB, 0xE0, 0x9B, 0x90, 0x80, 0xDA, 0xE0, 0x9A, 0x50,
+0x13, 0xA3, 0xE0, 0x24, 0x01, 0xFF, 0x90, 0x80, 0xDA, 0xE0, 0x34, 0x00, 0xFE, 0xC3, 0xEB, 0x9F,
+0xFB, 0xEA, 0x9E, 0xFA, 0xEA, 0x90, 0xFD, 0x11, 0xF0, 0xAF, 0x03, 0x74, 0x00, 0x2F, 0xF5, 0x82,
+0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xE0, 0xFF, 0x22, 0x12, 0x1F, 0xA4, 0xFF, 0x54, 0x01, 0xFE, 0x90,
+0x81, 0x42, 0xE0, 0x54, 0xFE, 0x4E, 0xF0, 0xEF, 0xC3, 0x13, 0x30, 0xE0, 0x0A, 0x90, 0x00, 0x01,
+0x12, 0x1F, 0xBD, 0x90, 0x81, 0x43, 0xF0, 0x22, 0x90, 0x81, 0x45, 0xE0, 0x30, 0xE0, 0x2D, 0x90,
+0x81, 0x48, 0xE0, 0x04, 0xF0, 0xE0, 0xFF, 0x90, 0x81, 0x46, 0xE0, 0xB5, 0x07, 0x1E, 0x90, 0x06,
+0x92, 0xE0, 0x54, 0x1C, 0x70, 0x0B, 0x12, 0x4F, 0x0B, 0x90, 0x81, 0x49, 0xE0, 0x04, 0xF0, 0x80,
+0x06, 0x90, 0x06, 0x92, 0x74, 0x1C, 0xF0, 0xE4, 0x90, 0x81, 0x48, 0xF0, 0x22, 0x00, 0xBB, 0x8E,
+};
diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/Hal8188EFWImg_CE.h b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/Hal8188EFWImg_CE.h new file mode 100755 index 00000000..2328ec3c --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/Hal8188EFWImg_CE.h @@ -0,0 +1,29 @@ +/******************************************************************************
+*
+* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms of version 2 of the GNU General Public License as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful, but WITHOUT
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+* more details.
+*
+* You should have received a copy of the GNU General Public License along with
+* this program; if not, write to the Free Software Foundation, Inc.,
+* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+*
+*
+******************************************************************************/
+#ifndef __INC_HAL8188E_FW_IMG_H
+#define __INC_HAL8188E_FW_IMG_H
+
+//V10(1641)
+#define Rtl8188EFWImgArrayLength 13904
+
+extern const u8 Rtl8188EFwImgArray[Rtl8188EFWImgArrayLength];
+
+#endif //__INC_HAL8188E_FW_IMG_H
+
diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/Hal8188ERateAdaptive.c b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/Hal8188ERateAdaptive.c new file mode 100755 index 00000000..355d0afa --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/Hal8188ERateAdaptive.c @@ -0,0 +1,1105 @@ +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + RateAdaptive.c + +Abstract: + Implement Rate Adaptive functions for common operations. + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2011-08-12 Page Create. + +--*/ +#include "../odm_precomp.h" + +//#if( DM_ODM_SUPPORT_TYPE == ODM_MP) +//#include "Mp_Precomp.h" +//#endif + +#if (RATE_ADAPTIVE_SUPPORT == 1) +// Rate adaptive parameters + + +static u1Byte RETRY_PENALTY[PERENTRY][RETRYSIZE+1] = {{5,4,3,2,0,3},//92 , idx=0 + {6,5,4,3,0,4},//86 , idx=1 + {6,5,4,2,0,4},//81 , idx=2 + {8,7,6,4,0,6},//75 , idx=3 + {10,9,8,6,0,8},//71 , idx=4 + {10,9,8,4,0,8},//66 , idx=5 + {10,9,8,2,0,8},//62 , idx=6 + {10,9,8,0,0,8},//59 , idx=7 + {18,17,16,8,0,16},//53 , idx=8 + {26,25,24,16,0,24},//50 , idx=9 + {34,33,32,24,0,32},//47 , idx=0x0a + //{34,33,32,16,0,32},//43 , idx=0x0b + //{34,33,32,8,0,32},//40 , idx=0x0c + //{34,33,28,8,0,32},//37 , idx=0x0d + //{34,33,20,8,0,32},//32 , idx=0x0e + //{34,32,24,8,0,32},//26 , idx=0x0f + //{49,48,32,16,0,48},//20 , idx=0x10 + //{49,48,24,0,0,48},//17 , idx=0x11 + //{49,47,16,16,0,48},//15 , idx=0x12 + //{49,44,16,16,0,48},//12 , idx=0x13 + //{49,40,16,0,0,48},//9 , idx=0x14 + {34,31,28,20,0,32},//43 , idx=0x0b + {34,31,27,18,0,32},//40 , idx=0x0c + {34,31,26,16,0,32},//37 , idx=0x0d + {34,30,22,16,0,32},//32 , idx=0x0e + {34,30,24,16,0,32},//26 , idx=0x0f + {49,46,40,16,0,48},//20 , idx=0x10 + {49,45,32,0,0,48},//17 , idx=0x11 + {49,45,22,18,0,48},//15 , idx=0x12 + {49,40,24,16,0,48},//12 , idx=0x13 + {49,32,18,12,0,48},//9 , idx=0x14 + {49,22,18,14,0,48},//6 , idx=0x15 + {49,16,16,0,0,48}};//3 //3, idx=0x16 + +static u1Byte RETRY_PENALTY_UP[RETRYSIZE+1]={49,44,16,16,0,48}; // 12% for rate up + +static u1Byte PT_PENALTY[RETRYSIZE+1]={34,31,30,24,0,32}; + +#if 0 +static u1Byte RETRY_PENALTY_IDX[2][RATESIZE] = {{4,4,4,5,4,4,5,7,7,7,8,0x0a, // SS>TH + 4,4,4,4,6,0x0a,0x0b,0x0d, + 5,5,7,7,8,0x0b,0x0d,0x0f}, // 0329 R01 + {4,4,4,5,7,7,9,9,0x0c,0x0e,0x10,0x12, // SS<TH + 4,4,5,5,6,0x0a,0x11,0x13, + 9,9,9,9,0x0c,0x0e,0x11,0x13}}; +#endif + + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) +static u1Byte RETRY_PENALTY_IDX[2][RATESIZE] = {{4,4,4,5,4,4,5,7,7,7,8,0x0a, // SS>TH + 4,4,4,4,6,0x0a,0x0b,0x0d, + 5,5,7,7,8,0x0b,0x0d,0x0f}, // 0329 R01 + {0x0a,0x0a,0x0a,0x0a,0x0c,0x0c,0x0e,0x10,0x11,0x12,0x12,0x13, // SS<TH + 0x0e,0x0f,0x10,0x10,0x11,0x14,0x14,0x15, + 9,9,9,9,0x0c,0x0e,0x11,0x13}}; + +static u1Byte RETRY_PENALTY_UP_IDX[RATESIZE] = {0x10,0x10,0x10,0x10,0x11,0x11,0x12,0x12,0x12,0x13,0x13,0x14, // SS>TH + 0x13,0x13,0x14,0x14,0x15,0x15,0x15,0x15, + 0x11,0x11,0x12,0x13,0x13,0x13,0x14,0x15}; + +static u1Byte RSSI_THRESHOLD[RATESIZE] = {0,0,0,0, + 0,0,0,0,0,0x24,0x26,0x2a, + 0x13,0x15,0x17,0x18,0x1a,0x1c,0x1d,0x1f, + 0,0,0,0x1f,0x23,0x28,0x2a,0x2c}; +#else + +// wilson modify +static u1Byte RETRY_PENALTY_IDX[2][RATESIZE] = {{4,4,4,5,4,4,5,7,7,7,8,0x0a, // SS>TH + 4,4,4,4,6,0x0a,0x0b,0x0d, + 5,5,7,7,8,0x0b,0x0d,0x0f}, // 0329 R01 + {0x0a,0x0a,0x0b,0x0c,0x0a,0x0a,0x0b,0x0c,0x0d,0x10,0x13,0x14, // SS<TH + 0x0b,0x0c,0x0d,0x0e,0x0f,0x11,0x13,0x15, + 9,9,9,9,0x0c,0x0e,0x11,0x13}}; + +static u1Byte RETRY_PENALTY_UP_IDX[RATESIZE] = {0x0c,0x0d,0x0d,0x0f,0x0d,0x0e,0x0f,0x0f,0x10,0x12,0x13,0x14, // SS>TH + 0x0f,0x10,0x10,0x12,0x12,0x13,0x14,0x15, + 0x11,0x11,0x12,0x13,0x13,0x13,0x14,0x15}; + +static u1Byte RSSI_THRESHOLD[RATESIZE] = {0,0,0,0, + 0,0,0,0,0,0x24,0x26,0x2a, + 0x18,0x1a,0x1d,0x1f,0x21,0x27,0x29,0x2a, + 0,0,0,0x1f,0x23,0x28,0x2a,0x2c}; + +#endif + +/*static u1Byte RSSI_THRESHOLD[RATESIZE] = {0,0,0,0, + 0,0,0,0,0,0x24,0x26,0x2a, + 0x1a,0x1c,0x1e,0x21,0x24,0x2a,0x2b,0x2d, + 0,0,0,0x1f,0x23,0x28,0x2a,0x2c};*/ +static u2Byte N_THRESHOLD_HIGH[RATESIZE] = {4,4,8,16, + 24,36,48,72,96,144,192,216, + 60,80,100,160,240,400,560,640, + 300,320,480,720,1000,1200,1600,2000}; +static u2Byte N_THRESHOLD_LOW[RATESIZE] = {2,2,4,8, + 12,18,24,36,48,72,96,108, + 30,40,50,80,120,200,280,320, + 150,160,240,360,500,600,800,1000}; +static u1Byte TRYING_NECESSARY[RATESIZE] = {2,2,2,2, + 2,2,3,3,4,4,5,7, + 4,4,7,10,10,12,12,18, + 5,7,7,8,11,18,36,60}; // 0329 // 1207 +#if 0 +static u1Byte POOL_RETRY_TH[RATESIZE] = {30,30,30,30, + 30,30,25,25,20,15,15,10, + 30,25,25,20,15,10,10,10, + 30,25,25,20,15,10,10,10}; +#endif + +static u1Byte DROPING_NECESSARY[RATESIZE] = {1,1,1,1, + 1,2,3,4,5,6,7,8, + 1,2,3,4,5,6,7,8, + 5,6,7,8,9,10,11,12}; + + +static u4Byte INIT_RATE_FALLBACK_TABLE[16]={0x0f8ff015, // 0: 40M BGN mode + 0x0f8ff010, // 1: 40M GN mode + 0x0f8ff005, // 2: BN mode/ 40M BGN mode + 0x0f8ff000, // 3: N mode + 0x00000ff5, // 4: BG mode + 0x00000ff0, // 5: G mode + 0x0000000d, // 6: B mode + 0, // 7: + 0, // 8: + 0, // 9: + 0, // 10: + 0, // 11: + 0, // 12: + 0, // 13: + 0, // 14: + 0, // 15: + + }; +static u1Byte PendingForRateUpFail[5]={2,10,24,40,60}; +static u2Byte DynamicTxRPTTiming[6]={0x186a, 0x30d4, 0x493e, 0x61a8, 0x7a12 ,0x927c}; // 200ms-1200ms + +// End Rate adaptive parameters + +static void +odm_SetTxRPTTiming_8188E( + IN PDM_ODM_T pDM_Odm, + IN PODM_RA_INFO_T pRaInfo, + IN u1Byte extend + ) +{ + u1Byte idx = 0; + + for(idx=0; idx<5; idx++) + if(DynamicTxRPTTiming[idx] == pRaInfo->RptTime) + break; + + if (extend==0) // back to default timing + idx=0; //200ms + else if (extend==1) {// increase the timing + idx+=1; + if (idx>5) + idx=5; + } + else if (extend==2) {// decrease the timing + if(idx!=0) + idx-=1; + } + pRaInfo->RptTime=DynamicTxRPTTiming[idx]; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("pRaInfo->RptTime=0x%x\n", pRaInfo->RptTime)); +} + +static int +odm_RateDown_8188E( + IN PDM_ODM_T pDM_Odm, + IN PODM_RA_INFO_T pRaInfo + ) +{ + u1Byte RateID, LowestRate, HighestRate; + u1Byte i; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("=====>odm_RateDown_8188E()\n")); + if(NULL == pRaInfo) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("odm_RateDown_8188E(): pRaInfo is NULL\n")); + return -1; + } + RateID = pRaInfo->PreRate; + LowestRate = pRaInfo->LowestRate; + HighestRate = pRaInfo->HighestRate; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, + (" RateID=%d LowestRate=%d HighestRate=%d RateSGI=%d\n", + RateID, LowestRate, HighestRate, pRaInfo->RateSGI)); + if (RateID > HighestRate) + { + RateID=HighestRate; + } + else if(pRaInfo->RateSGI) + { + pRaInfo->RateSGI=0; + } + else if (RateID > LowestRate) + { + if (RateID > 0) + { + for (i=RateID-1; i>LowestRate;i--) + { + if (pRaInfo->RAUseRate & BIT(i)) + { + RateID=i; + goto RateDownFinish; + + } + } + } + } + else if (RateID <= LowestRate) + { + RateID = LowestRate; + } +RateDownFinish: + if (pRaInfo->RAWaitingCounter==1){ + pRaInfo->RAWaitingCounter+=1; + pRaInfo->RAPendingCounter+=1; + } + else if(pRaInfo->RAWaitingCounter==0){ + } + else{ + pRaInfo->RAWaitingCounter=0; + pRaInfo->RAPendingCounter=0; + } + + if(pRaInfo->RAPendingCounter>=4) + pRaInfo->RAPendingCounter=4; + + pRaInfo->DecisionRate=RateID; + odm_SetTxRPTTiming_8188E(pDM_Odm,pRaInfo, 2); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Rate down, RPT Timing default\n")); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("RAWaitingCounter %d, RAPendingCounter %d",pRaInfo->RAWaitingCounter,pRaInfo->RAPendingCounter)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Rate down to RateID %d RateSGI %d\n", RateID, pRaInfo->RateSGI)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("<=====odm_RateDown_8188E() \n")); + return 0; +} + +static int +odm_RateUp_8188E( + IN PDM_ODM_T pDM_Odm, + IN PODM_RA_INFO_T pRaInfo + ) +{ + u1Byte RateID, HighestRate; + u1Byte i; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("=====>odm_RateUp_8188E() \n")); + if(NULL == pRaInfo) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("odm_RateUp_8188E(): pRaInfo is NULL\n")); + return -1; + } + RateID = pRaInfo->PreRate; + HighestRate = pRaInfo->HighestRate; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, + (" RateID=%d HighestRate=%d\n", + RateID, HighestRate)); + if (pRaInfo->RAWaitingCounter==1){ + pRaInfo->RAWaitingCounter=0; + pRaInfo->RAPendingCounter=0; + } + else if (pRaInfo->RAWaitingCounter>1){ + pRaInfo->PreRssiStaRA=pRaInfo->RssiStaRA; + goto RateUpfinish; + } + odm_SetTxRPTTiming_8188E(pDM_Odm,pRaInfo, 0); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("odm_RateUp_8188E():Decrease RPT Timing\n")); + + if (RateID < HighestRate) + { + for (i=RateID+1; i<=HighestRate; i++) + { + if (pRaInfo->RAUseRate & BIT(i)) + { + RateID=i; + goto RateUpfinish; + } + } + } + else if(RateID == HighestRate) + { + if (pRaInfo->SGIEnable && (pRaInfo->RateSGI != 1)) + pRaInfo->RateSGI = 1; + else if((pRaInfo->SGIEnable) !=1 ) + pRaInfo->RateSGI = 0; + } + else //if((sta_info_ra->Decision_rate) > (sta_info_ra->Highest_rate)) + { + RateID = HighestRate; + + } +RateUpfinish: + //if(pRaInfo->RAWaitingCounter==10) + if(pRaInfo->RAWaitingCounter==(4+PendingForRateUpFail[pRaInfo->RAPendingCounter])) + pRaInfo->RAWaitingCounter=0; + else + pRaInfo->RAWaitingCounter++; + + pRaInfo->DecisionRate=RateID; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Rate up to RateID %d\n", RateID)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("RAWaitingCounter %d, RAPendingCounter %d",pRaInfo->RAWaitingCounter,pRaInfo->RAPendingCounter)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("<=====odm_RateUp_8188E() \n")); + return 0; +} + +static void odm_ResetRaCounter_8188E( IN PODM_RA_INFO_T pRaInfo){ + u1Byte RateID; + RateID=pRaInfo->DecisionRate; + pRaInfo->NscUp=(N_THRESHOLD_HIGH[RateID]+N_THRESHOLD_LOW[RateID])>>1; + pRaInfo->NscDown=(N_THRESHOLD_HIGH[RateID]+N_THRESHOLD_LOW[RateID])>>1; +} + +static void +odm_RateDecision_8188E( + IN PDM_ODM_T pDM_Odm, + IN PODM_RA_INFO_T pRaInfo + ) +{ + u1Byte RateID = 0, RtyPtID = 0, PenaltyID1 = 0, PenaltyID2 = 0; + //u4Byte pool_retry; + static u1Byte DynamicTxRPTTimingCounter=0; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("=====>odm_RateDecision_8188E() \n")); + + if (pRaInfo->Active && (pRaInfo->TOTAL > 0)) // STA used and data packet exits + { + if ( (pRaInfo->RssiStaRA<(pRaInfo->PreRssiStaRA-3))|| (pRaInfo->RssiStaRA>(pRaInfo->PreRssiStaRA+3))){ + pRaInfo->RAWaitingCounter=0; + pRaInfo->RAPendingCounter=0; + } + // Start RA decision + if (pRaInfo->PreRate > pRaInfo->HighestRate) + RateID = pRaInfo->HighestRate; + else + RateID = pRaInfo->PreRate; + if (pRaInfo->RssiStaRA > RSSI_THRESHOLD[RateID]) + RtyPtID=0; + else + RtyPtID=1; + PenaltyID1 = RETRY_PENALTY_IDX[RtyPtID][RateID]; //TODO by page + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, + (" NscDown init is %d\n", pRaInfo->NscDown)); + //pool_retry=pRaInfo->RTY[2]+pRaInfo->RTY[3]+pRaInfo->RTY[4]+pRaInfo->DROP; + pRaInfo->NscDown += pRaInfo->RTY[0] * RETRY_PENALTY[PenaltyID1][0]; + pRaInfo->NscDown += pRaInfo->RTY[1] * RETRY_PENALTY[PenaltyID1][1]; + pRaInfo->NscDown += pRaInfo->RTY[2] * RETRY_PENALTY[PenaltyID1][2]; + pRaInfo->NscDown += pRaInfo->RTY[3] * RETRY_PENALTY[PenaltyID1][3]; + pRaInfo->NscDown += pRaInfo->RTY[4] * RETRY_PENALTY[PenaltyID1][4]; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, + (" NscDown is %d, total*penalty[5] is %d\n", + pRaInfo->NscDown, (pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID1][5]))); + if (pRaInfo->NscDown > (pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID1][5])) + pRaInfo->NscDown -= pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID1][5]; + else + pRaInfo->NscDown=0; + + // rate up + PenaltyID2 = RETRY_PENALTY_UP_IDX[RateID]; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, + (" NscUp init is %d\n", pRaInfo->NscUp)); + pRaInfo->NscUp += pRaInfo->RTY[0] * RETRY_PENALTY[PenaltyID2][0]; + pRaInfo->NscUp += pRaInfo->RTY[1] * RETRY_PENALTY[PenaltyID2][1]; + pRaInfo->NscUp += pRaInfo->RTY[2] * RETRY_PENALTY[PenaltyID2][2]; + pRaInfo->NscUp += pRaInfo->RTY[3] * RETRY_PENALTY[PenaltyID2][3]; + pRaInfo->NscUp += pRaInfo->RTY[4] * RETRY_PENALTY[PenaltyID2][4]; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, + ("NscUp is %d, total*up[5] is %d\n", + pRaInfo->NscUp, (pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID2][5]))); + if (pRaInfo->NscUp > (pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID2][5])) + pRaInfo->NscUp -= pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID2][5]; + else + pRaInfo->NscUp = 0; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE|ODM_COMP_INIT, ODM_DBG_LOUD, + (" RssiStaRa= %d RtyPtID=%d PenaltyID1=0x%x PenaltyID2=0x%x RateID=%d NscDown=%d NscUp=%d SGI=%d\n", + pRaInfo->RssiStaRA,RtyPtID, PenaltyID1,PenaltyID2, RateID, pRaInfo->NscDown, pRaInfo->NscUp, pRaInfo->RateSGI)); + if ((pRaInfo->NscDown < N_THRESHOLD_LOW[RateID]) ||(pRaInfo->DROP>DROPING_NECESSARY[RateID])) + odm_RateDown_8188E(pDM_Odm,pRaInfo); + //else if ((pRaInfo->NscUp > N_THRESHOLD_HIGH[RateID])&&(pool_retry<POOL_RETRY_TH[RateID])) + else if (pRaInfo->NscUp > N_THRESHOLD_HIGH[RateID]) + odm_RateUp_8188E(pDM_Odm,pRaInfo); + + if(pRaInfo->DecisionRate > pRaInfo->HighestRate) + pRaInfo->DecisionRate = pRaInfo->HighestRate; + + if ((pRaInfo->DecisionRate)==(pRaInfo->PreRate)) + DynamicTxRPTTimingCounter+=1; + else + DynamicTxRPTTimingCounter=0; + + if (DynamicTxRPTTimingCounter>=4) { + odm_SetTxRPTTiming_8188E(pDM_Odm,pRaInfo, 1); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("<=====Rate don't change 4 times, Extend RPT Timing\n")); + DynamicTxRPTTimingCounter=0; + } + + pRaInfo->PreRate = pRaInfo->DecisionRate; //YJ,add,120120 + + odm_ResetRaCounter_8188E( pRaInfo); + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, ("<=====odm_RateDecision_8188E() \n")); +} + +static int +odm_ARFBRefresh_8188E( + IN PDM_ODM_T pDM_Odm, + IN PODM_RA_INFO_T pRaInfo + ) +{ // Wilson 2011/10/26 + u4Byte MaskFromReg; + s1Byte i; + + switch(pRaInfo->RateID){ + case RATR_INX_WIRELESS_NGB: + pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x0f8ff015; + break; + case RATR_INX_WIRELESS_NG: + pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x0f8ff010; + break; + case RATR_INX_WIRELESS_NB: + pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x0f8ff005; + break; + case RATR_INX_WIRELESS_N: + pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x0f8ff000; + break; + case RATR_INX_WIRELESS_GB: + pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x00000ff5; + break; + case RATR_INX_WIRELESS_G: + pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x00000ff0; + break; + case RATR_INX_WIRELESS_B: + pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x0000000d; + break; + case 12: + MaskFromReg=ODM_Read4Byte(pDM_Odm, REG_ARFR0); + pRaInfo->RAUseRate=(pRaInfo->RateMask)&MaskFromReg; + break; + case 13: + MaskFromReg=ODM_Read4Byte(pDM_Odm, REG_ARFR1); + pRaInfo->RAUseRate=(pRaInfo->RateMask)&MaskFromReg; + break; + case 14: + MaskFromReg=ODM_Read4Byte(pDM_Odm, REG_ARFR2); + pRaInfo->RAUseRate=(pRaInfo->RateMask)&MaskFromReg; + break; + case 15: + MaskFromReg=ODM_Read4Byte(pDM_Odm, REG_ARFR3); + pRaInfo->RAUseRate=(pRaInfo->RateMask)&MaskFromReg; + break; + + default: + pRaInfo->RAUseRate=(pRaInfo->RateMask); + break; + } + // Highest rate + if (pRaInfo->RAUseRate){ + for (i=RATESIZE;i>=0;i--) + { + if((pRaInfo->RAUseRate)&BIT(i)){ + pRaInfo->HighestRate=i; + break; + } + } + } + else{ + pRaInfo->HighestRate=0; + } + // Lowest rate + if (pRaInfo->RAUseRate){ + for (i=0;i<RATESIZE;i++) + { + if((pRaInfo->RAUseRate)&BIT(i)) + { + pRaInfo->LowestRate=i; + break; + } + } + } + else{ + pRaInfo->LowestRate=0; + } + +#if POWER_TRAINING_ACTIVE == 1 + if (pRaInfo->HighestRate >0x13) + pRaInfo->PTModeSS=3; + else if(pRaInfo->HighestRate >0x0b) + pRaInfo->PTModeSS=2; + else if(pRaInfo->HighestRate >0x0b) + pRaInfo->PTModeSS=1; + else + pRaInfo->PTModeSS=0; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, + ("ODM_ARFBRefresh_8188E(): PTModeSS=%d\n", pRaInfo->PTModeSS)); + +#endif + + if(pRaInfo->DecisionRate > pRaInfo->HighestRate) + pRaInfo->DecisionRate = pRaInfo->HighestRate; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, + ("ODM_ARFBRefresh_8188E(): RateID=%d RateMask=%8.8x RAUseRate=%8.8x HighestRate=%d,DecisionRate=%d \n", + pRaInfo->RateID, pRaInfo->RateMask, pRaInfo->RAUseRate, pRaInfo->HighestRate,pRaInfo->DecisionRate)); + return 0; +} + +#if POWER_TRAINING_ACTIVE == 1 +static void +odm_PTTryState_8188E( + IN PODM_RA_INFO_T pRaInfo + ) +{ + pRaInfo->PTTryState=0; + switch (pRaInfo->PTModeSS) + { + case 3: + if (pRaInfo->DecisionRate>=0x19) + pRaInfo->PTTryState=1; + break; + case 2: + if (pRaInfo->DecisionRate>=0x11) + pRaInfo->PTTryState=1; + break; + case 1: + if (pRaInfo->DecisionRate>=0x0a) + pRaInfo->PTTryState=1; + break; + case 0: + if (pRaInfo->DecisionRate>=0x03) + pRaInfo->PTTryState=1; + break; + default: + pRaInfo->PTTryState=0; + } + + if (pRaInfo->RssiStaRA<48) + { + pRaInfo->PTStage=0; + } + else if (pRaInfo->PTTryState==1) + { + if ((pRaInfo->PTStopCount>=10)||(pRaInfo->PTPreRssi>pRaInfo->RssiStaRA+5) + ||(pRaInfo->PTPreRssi<pRaInfo->RssiStaRA-5)||(pRaInfo->DecisionRate!=pRaInfo->PTPreRate)) + { + if (pRaInfo->PTStage==0) + pRaInfo->PTStage=1; + else if(pRaInfo->PTStage==1) + pRaInfo->PTStage=3; + else + pRaInfo->PTStage=5; + + pRaInfo->PTPreRssi=pRaInfo->RssiStaRA; + pRaInfo->PTStopCount=0; + + } + else{ + pRaInfo->RAstage=0; + pRaInfo->PTStopCount++; + } + } + else{ + pRaInfo->PTStage=0; + pRaInfo->RAstage=0; + } + pRaInfo->PTPreRate=pRaInfo->DecisionRate; +} + +static void +odm_PTDecision_8188E( + IN PODM_RA_INFO_T pRaInfo + ) +{ + u1Byte stage_BUF; + u1Byte j; + u1Byte temp_stage; + u4Byte numsc; + u4Byte num_total; + u1Byte stage_id; + + stage_BUF=pRaInfo->PTStage; + numsc = 0; + num_total= pRaInfo->TOTAL* PT_PENALTY[5]; + for(j=0;j<=4;j++) + { + numsc += pRaInfo->RTY[j] * PT_PENALTY[j]; + if(numsc>num_total) + break; + } + + j=j>>1; + temp_stage= (pRaInfo->PTStage +1)>>1; + if (temp_stage>j) + stage_id=temp_stage-j; + else + stage_id=0; + + pRaInfo->PTSmoothFactor=(pRaInfo->PTSmoothFactor>>1) + (pRaInfo->PTSmoothFactor>>2) + stage_id*16+2; + if (pRaInfo->PTSmoothFactor>192) + pRaInfo->PTSmoothFactor=192; + stage_id =pRaInfo->PTSmoothFactor>>6; + temp_stage=stage_id*2; + if (temp_stage!=0) + temp_stage-=1; + if (pRaInfo->DROP>3) + temp_stage=0; + pRaInfo->PTStage=temp_stage; + +} +#endif + +static VOID +odm_RATxRPTTimerSetting( + IN PDM_ODM_T pDM_Odm, + IN u2Byte minRptTime +) +{ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE,(" =====>odm_RATxRPTTimerSetting()\n")); + + + if(pDM_Odm->CurrminRptTime != minRptTime){ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, + (" CurrminRptTime =0x%04x minRptTime=0x%04x\n", pDM_Odm->CurrminRptTime, minRptTime)); + #if(DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_AP)) + ODM_RA_Set_TxRPT_Time(pDM_Odm,minRptTime); + #else + rtw_rpt_timer_cfg_cmd(pDM_Odm->Adapter,minRptTime); + #endif + pDM_Odm->CurrminRptTime = minRptTime; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE,(" <=====odm_RATxRPTTimerSetting()\n")); +} + + +VOID +ODM_RASupport_Init( + IN PDM_ODM_T pDM_Odm + ) +{ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("=====>ODM_RASupport_Init()\n")); + + // 2012/02/14 MH Be noticed, the init must be after IC type is recognized!!!!! + if (pDM_Odm->SupportICType == ODM_RTL8188E) + pDM_Odm->RaSupport88E = TRUE; + +} + + + +int +ODM_RAInfo_Init( + IN PDM_ODM_T pDM_Odm, + IN u1Byte MacID + ) +{ + PODM_RA_INFO_T pRaInfo = &pDM_Odm->RAInfo[MacID]; + #if 1 + u1Byte WirelessMode=0xFF; //invalid value + u1Byte max_rate_idx = 0x13; //MCS7 + if(pDM_Odm->pWirelessMode!=NULL){ + WirelessMode=*(pDM_Odm->pWirelessMode); + } + + if(WirelessMode != 0xFF ){ + if(WirelessMode & ODM_WM_N24G) + max_rate_idx = 0x13; + else if(WirelessMode & ODM_WM_G) + max_rate_idx = 0x0b; + else if(WirelessMode & ODM_WM_B) + max_rate_idx = 0x03; + } + + //printk("%s ==>WirelessMode:0x%08x ,max_raid_idx:0x%02x\n ",__FUNCTION__,WirelessMode,max_rate_idx); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, + ("ODM_RAInfo_Init(): WirelessMode:0x%08x ,max_raid_idx:0x%02x \n", + WirelessMode,max_rate_idx)); + + pRaInfo->DecisionRate = max_rate_idx; + pRaInfo->PreRate = max_rate_idx; + pRaInfo->HighestRate=max_rate_idx; + #else + pRaInfo->DecisionRate = 0x13; + pRaInfo->PreRate = 0x13; + pRaInfo->HighestRate= 0x13; + #endif + pRaInfo->LowestRate=0; + pRaInfo->RateID=0; + pRaInfo->RateMask=0xffffffff; + pRaInfo->RssiStaRA=0; + pRaInfo->PreRssiStaRA=0; + pRaInfo->SGIEnable=0; + pRaInfo->RAUseRate=0xffffffff; + pRaInfo->NscDown=(N_THRESHOLD_HIGH[0x13]+N_THRESHOLD_LOW[0x13])/2; + pRaInfo->NscUp=(N_THRESHOLD_HIGH[0x13]+N_THRESHOLD_LOW[0x13])/2; + pRaInfo->RateSGI=0; + pRaInfo->Active=1; //Active is not used at present. by page, 110819 + pRaInfo->RptTime = 0x927c; + pRaInfo->DROP=0; + pRaInfo->RTY[0]=0; + pRaInfo->RTY[1]=0; + pRaInfo->RTY[2]=0; + pRaInfo->RTY[3]=0; + pRaInfo->RTY[4]=0; + pRaInfo->TOTAL=0; + pRaInfo->RAWaitingCounter=0; + pRaInfo->RAPendingCounter=0; +#if POWER_TRAINING_ACTIVE == 1 + pRaInfo->PTActive=1; // Active when this STA is use + pRaInfo->PTTryState=0; + pRaInfo->PTStage=5; // Need to fill into HW_PWR_STATUS + pRaInfo->PTSmoothFactor=192; + pRaInfo->PTStopCount=0; + pRaInfo->PTPreRate=0; + pRaInfo->PTPreRssi=0; + pRaInfo->PTModeSS=0; + pRaInfo->RAstage=0; +#endif + return 0; +} + +int +ODM_RAInfo_Init_all( + IN PDM_ODM_T pDM_Odm + ) +{ + u1Byte MacID = 0; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("=====>\n")); + pDM_Odm->CurrminRptTime = 0; + + for(MacID=0; MacID<ODM_ASSOCIATE_ENTRY_NUM; MacID++) + ODM_RAInfo_Init(pDM_Odm,MacID); + + return 0; +} + + +u1Byte +ODM_RA_GetShortGI_8188E( + IN PDM_ODM_T pDM_Odm, + IN u1Byte MacID +) +{ + if((NULL == pDM_Odm) || (MacID >= ASSOCIATE_ENTRY_NUM)) + return 0; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, + ("MacID=%d SGI=%d\n", MacID, pDM_Odm->RAInfo[MacID].RateSGI)); + return pDM_Odm->RAInfo[MacID].RateSGI; +} + +u1Byte +ODM_RA_GetDecisionRate_8188E( + IN PDM_ODM_T pDM_Odm, + IN u1Byte MacID + ) +{ + u1Byte DecisionRate = 0; + + if((NULL == pDM_Odm) || (MacID >= ASSOCIATE_ENTRY_NUM)) + return 0; + DecisionRate = (pDM_Odm->RAInfo[MacID].DecisionRate); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, + (" MacID=%d DecisionRate=0x%x\n", MacID, DecisionRate)); + return DecisionRate; +} + +u1Byte +ODM_RA_GetHwPwrStatus_8188E( + IN PDM_ODM_T pDM_Odm, + IN u1Byte MacID + ) +{ + u1Byte PTStage = 5; + if((NULL == pDM_Odm) || (MacID >= ASSOCIATE_ENTRY_NUM)) + return 0; + PTStage = (pDM_Odm->RAInfo[MacID].PTStage); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, + ("MacID=%d PTStage=0x%x\n", MacID, PTStage)); + return PTStage; +} + +VOID +ODM_RA_UpdateRateInfo_8188E( + IN PDM_ODM_T pDM_Odm, + IN u1Byte MacID, + IN u1Byte RateID, + IN u4Byte RateMask, + IN u1Byte SGIEnable + ) +{ + PODM_RA_INFO_T pRaInfo = NULL; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, + ("MacID=%d RateID=0x%x RateMask=0x%x SGIEnable=%d\n", + MacID, RateID, RateMask, SGIEnable)); + if((NULL == pDM_Odm) || (MacID >= ASSOCIATE_ENTRY_NUM)) + return; + + pRaInfo = &(pDM_Odm->RAInfo[MacID]); + pRaInfo->RateID = RateID; + pRaInfo->RateMask = RateMask; + pRaInfo->SGIEnable = SGIEnable; + odm_ARFBRefresh_8188E(pDM_Odm, pRaInfo); +} + +VOID +ODM_RA_SetRSSI_8188E( + IN PDM_ODM_T pDM_Odm, + IN u1Byte MacID, + IN u1Byte Rssi + ) +{ + PODM_RA_INFO_T pRaInfo = NULL; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_TRACE, + (" MacID=%d Rssi=%d\n", MacID, Rssi)); + if((NULL == pDM_Odm) || (MacID >= ASSOCIATE_ENTRY_NUM)) + return; + + pRaInfo = &(pDM_Odm->RAInfo[MacID]); + pRaInfo->RssiStaRA = Rssi; +} + +VOID +ODM_RA_Set_TxRPT_Time( + IN PDM_ODM_T pDM_Odm, + IN u2Byte minRptTime + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP)) + if (minRptTime != 0xffff) +#endif + ODM_Write2Byte(pDM_Odm, REG_TX_RPT_TIME, minRptTime); +} + + +VOID +ODM_RA_TxRPT2Handle_8188E( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte TxRPT_Buf, + IN u2Byte TxRPT_Len, + IN u4Byte MacIDValidEntry0, + IN u4Byte MacIDValidEntry1 + ) +{ + PODM_RA_INFO_T pRAInfo = NULL; + u1Byte MacId = 0; + pu1Byte pBuffer = NULL; + u4Byte valid = 0, ItemNum = 0; + u2Byte minRptTime = 0x927c; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("=====>ODM_RA_TxRPT2Handle_8188E(): valid0=%d valid1=%d BufferLength=%d\n", + MacIDValidEntry0, MacIDValidEntry1, TxRPT_Len)); + + ItemNum = TxRPT_Len >> 3; + pBuffer = TxRPT_Buf; + + do + { + if(MacId >= ASSOCIATE_ENTRY_NUM) + valid = 0; + else if(MacId >= 32) + valid = (1<<(MacId-32)) & MacIDValidEntry1; + else + valid = (1<<MacId) & MacIDValidEntry0; + + pRAInfo = &(pDM_Odm->RAInfo[MacId]); + if(valid) + { + +#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE)) + pRAInfo->RTY[0] = (u2Byte)GET_TX_REPORT_TYPE1_RERTY_0(pBuffer); + pRAInfo->RTY[1] = (u2Byte)GET_TX_REPORT_TYPE1_RERTY_1(pBuffer); + pRAInfo->RTY[2] = (u2Byte)GET_TX_REPORT_TYPE1_RERTY_2(pBuffer); + pRAInfo->RTY[3] = (u2Byte)GET_TX_REPORT_TYPE1_RERTY_3(pBuffer); + pRAInfo->RTY[4] = (u2Byte)GET_TX_REPORT_TYPE1_RERTY_4(pBuffer); + pRAInfo->DROP = (u2Byte)GET_TX_REPORT_TYPE1_DROP_0(pBuffer); +#else + pRAInfo->RTY[0] = (unsigned short)(pBuffer[1] << 8 | pBuffer[0]); + pRAInfo->RTY[1] = pBuffer[2]; + pRAInfo->RTY[2] = pBuffer[3]; + pRAInfo->RTY[3] = pBuffer[4]; + pRAInfo->RTY[4] = pBuffer[5]; + pRAInfo->DROP = pBuffer[6]; +#endif + pRAInfo->TOTAL = pRAInfo->RTY[0] + \ + pRAInfo->RTY[1] + \ + pRAInfo->RTY[2] + \ + pRAInfo->RTY[3] + \ + pRAInfo->RTY[4] + \ + pRAInfo->DROP; + if(pRAInfo->TOTAL != 0) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, + ("macid=%d Total=%d R0=%d R1=%d R2=%d R3=%d R4=%d D0=%d valid0=%x valid1=%x\n", + MacId, + pRAInfo->TOTAL, + pRAInfo->RTY[0], + pRAInfo->RTY[1], + pRAInfo->RTY[2], + pRAInfo->RTY[3], + pRAInfo->RTY[4], + pRAInfo->DROP, + MacIDValidEntry0 , + MacIDValidEntry1)); +#if POWER_TRAINING_ACTIVE == 1 + if (pRAInfo->PTActive){ + if(pRAInfo->RAstage<5){ + odm_RateDecision_8188E(pDM_Odm,pRAInfo); + } + else if(pRAInfo->RAstage==5){ // Power training try state + odm_PTTryState_8188E(pRAInfo); + } + else {// RAstage==6 + odm_PTDecision_8188E(pRAInfo); + } + + // Stage_RA counter + if (pRAInfo->RAstage<=5) + pRAInfo->RAstage++; + else + pRAInfo->RAstage=0; + } + else{ + odm_RateDecision_8188E(pDM_Odm,pRAInfo); + } +#else + odm_RateDecision_8188E(pDM_Odm, pRAInfo); +#endif + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + extern void RTL8188E_SetStationTxRateInfo(PDM_ODM_T, PODM_RA_INFO_T, int); + RTL8188E_SetStationTxRateInfo(pDM_Odm, pRAInfo, MacId); +#ifdef DETECT_STA_EXISTANCE + void RTL8188E_DetectSTAExistance(PDM_ODM_T pDM_Odm, PODM_RA_INFO_T pRAInfo, int MacID); + RTL8188E_DetectSTAExistance(pDM_Odm, pRAInfo, MacId); +#endif +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, + ("macid=%d R0=%d R1=%d R2=%d R3=%d R4=%d drop=%d valid0=%x RateID=%d SGI=%d\n", + MacId, + pRAInfo->RTY[0], + pRAInfo->RTY[1], + pRAInfo->RTY[2], + pRAInfo->RTY[3], + pRAInfo->RTY[4], + pRAInfo->DROP, + MacIDValidEntry0, + pRAInfo->DecisionRate, + pRAInfo->RateSGI)); + } + else + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, (" TOTAL=0!!!!\n")); + } + + if(minRptTime > pRAInfo->RptTime) + minRptTime = pRAInfo->RptTime; + + pBuffer += TX_RPT2_ITEM_SIZE; + MacId++; + }while(MacId < ItemNum); + + odm_RATxRPTTimerSetting(pDM_Odm,minRptTime); + + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("<===== ODM_RA_TxRPT2Handle_8188E()\n")); +} + +#else + +static VOID +odm_RATxRPTTimerSetting( + IN PDM_ODM_T pDM_Odm, + IN u2Byte minRptTime +) +{ + return; +} + + +VOID +ODM_RASupport_Init( + IN PDM_ODM_T pDM_Odm + ) +{ + return; +} + +int +ODM_RAInfo_Init( + IN PDM_ODM_T pDM_Odm, + IN u1Byte MacID + ) +{ + return 0; +} + +int +ODM_RAInfo_Init_all( + IN PDM_ODM_T pDM_Odm + ) +{ + return 0; +} + +u1Byte +ODM_RA_GetShortGI_8188E( + IN PDM_ODM_T pDM_Odm, + IN u1Byte MacID + ) +{ + return 0; +} + +u1Byte +ODM_RA_GetDecisionRate_8188E( + IN PDM_ODM_T pDM_Odm, + IN u1Byte MacID + ) +{ + return 0; +} +u1Byte +ODM_RA_GetHwPwrStatus_8188E( + IN PDM_ODM_T pDM_Odm, + IN u1Byte MacID + ) +{ + return 0; +} + +VOID +ODM_RA_UpdateRateInfo_8188E( + IN PDM_ODM_T pDM_Odm, + IN u1Byte MacID, + IN u1Byte RateID, + IN u4Byte RateMask, + IN u1Byte SGIEnable + ) +{ + return; +} + +VOID +ODM_RA_SetRSSI_8188E( + IN PDM_ODM_T pDM_Odm, + IN u1Byte MacID, + IN u1Byte Rssi + ) +{ + return; +} + +VOID +ODM_RA_Set_TxRPT_Time( + IN PDM_ODM_T pDM_Odm, + IN u2Byte minRptTime + ) +{ + return; +} + +VOID +ODM_RA_TxRPT2Handle_8188E( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte TxRPT_Buf, + IN u2Byte TxRPT_Len, + IN u4Byte MacIDValidEntry0, + IN u4Byte MacIDValidEntry1 + ) +{ + return; +} + + +#endif + diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/Hal8188ERateAdaptive.h b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/Hal8188ERateAdaptive.h new file mode 100755 index 00000000..e7c1e125 --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/Hal8188ERateAdaptive.h @@ -0,0 +1,108 @@ +#ifndef __INC_RA_H
+#define __INC_RA_H
+/*++
+Copyright (c) Realtek Semiconductor Corp. All rights reserved.
+
+Module Name:
+ RateAdaptive.h
+
+Abstract:
+ Prototype of RA and related data structure.
+
+Major Change History:
+ When Who What
+ ---------- --------------- -------------------------------
+ 2011-08-12 Page Create.
+--*/
+
+// Rate adaptive define
+#define PERENTRY 23
+#define RETRYSIZE 5
+#define RATESIZE 28
+#define TX_RPT2_ITEM_SIZE 8
+
+#if (DM_ODM_SUPPORT_TYPE != ODM_MP)
+//
+// TX report 2 format in Rx desc
+//
+#define GET_TX_RPT2_DESC_PKT_LEN_88E(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 0, 9)
+#define GET_TX_RPT2_DESC_MACID_VALID_1_88E(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+16, 0, 32)
+#define GET_TX_RPT2_DESC_MACID_VALID_2_88E(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+20, 0, 32)
+
+#define GET_TX_REPORT_TYPE1_RERTY_0(__pAddr) LE_BITS_TO_4BYTE( __pAddr, 0, 16)
+#define GET_TX_REPORT_TYPE1_RERTY_1(__pAddr) LE_BITS_TO_1BYTE( __pAddr+2, 0, 8)
+#define GET_TX_REPORT_TYPE1_RERTY_2(__pAddr) LE_BITS_TO_1BYTE( __pAddr+3, 0, 8)
+#define GET_TX_REPORT_TYPE1_RERTY_3(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4, 0, 8)
+#define GET_TX_REPORT_TYPE1_RERTY_4(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4+1, 0, 8)
+#define GET_TX_REPORT_TYPE1_DROP_0(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4+2, 0, 8)
+#define GET_TX_REPORT_TYPE1_DROP_1(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4+3, 0, 8)
+#endif
+
+// End rate adaptive define
+
+VOID
+ODM_RASupport_Init(
+ IN PDM_ODM_T pDM_Odm
+ );
+
+int
+ODM_RAInfo_Init_all(
+ IN PDM_ODM_T pDM_Odm
+ );
+
+int
+ODM_RAInfo_Init(
+ IN PDM_ODM_T pDM_Odm,
+ IN u1Byte MacID
+ );
+
+u1Byte
+ODM_RA_GetShortGI_8188E(
+ IN PDM_ODM_T pDM_Odm,
+ IN u1Byte MacID
+ );
+
+u1Byte
+ODM_RA_GetDecisionRate_8188E(
+ IN PDM_ODM_T pDM_Odm,
+ IN u1Byte MacID
+ );
+
+u1Byte
+ODM_RA_GetHwPwrStatus_8188E(
+ IN PDM_ODM_T pDM_Odm,
+ IN u1Byte MacID
+ );
+VOID
+ODM_RA_UpdateRateInfo_8188E(
+ IN PDM_ODM_T pDM_Odm,
+ IN u1Byte MacID,
+ IN u1Byte RateID,
+ IN u4Byte RateMask,
+ IN u1Byte SGIEnable
+ );
+
+VOID
+ODM_RA_SetRSSI_8188E(
+ IN PDM_ODM_T pDM_Odm,
+ IN u1Byte MacID,
+ IN u1Byte Rssi
+ );
+
+VOID
+ODM_RA_TxRPT2Handle_8188E(
+ IN PDM_ODM_T pDM_Odm,
+ IN pu1Byte TxRPT_Buf,
+ IN u2Byte TxRPT_Len,
+ IN u4Byte MacIDValidEntry0,
+ IN u4Byte MacIDValidEntry1
+ );
+
+
+VOID
+ODM_RA_Set_TxRPT_Time(
+ IN PDM_ODM_T pDM_Odm,
+ IN u2Byte minRptTime
+ );
+#endif
+
diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/Hal8188EReg.h b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/Hal8188EReg.h new file mode 100755 index 00000000..a5086c9b --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/Hal8188EReg.h @@ -0,0 +1,47 @@ +/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+//============================================================
+// File Name: Hal8188EReg.h
+//
+// Description:
+//
+// This file is for RTL8188E register definition.
+//
+//
+//============================================================
+#ifndef __HAL_8188E_REG_H__
+#define __HAL_8188E_REG_H__
+
+//
+// Register Definition
+//
+#define TRX_ANTDIV_PATH 0x860
+#define RX_ANTDIV_PATH 0xb2c
+#define ODM_R_A_AGC_CORE1_8188E 0xc50
+
+
+//
+// Bitmap Definition
+//
+#define BIT_FA_RESET_8188E BIT0
+
+
+#endif
+
diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_BB.c b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_BB.c new file mode 100755 index 00000000..91f9af2e --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_BB.c @@ -0,0 +1,891 @@ +/******************************************************************************
+*
+* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms of version 2 of the GNU General Public License as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful, but WITHOUT
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+* more details.
+*
+* You should have received a copy of the GNU General Public License along with
+* this program; if not, write to the Free Software Foundation, Inc.,
+* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+*
+*
+******************************************************************************/
+
+#include "../odm_precomp.h"
+
+#ifdef CONFIG_IOL_IOREG_CFG
+#include <rtw_iol.h>
+#endif
+
+#if (RTL8188E_SUPPORT == 1)
+static BOOLEAN
+CheckCondition(
+ const u4Byte Condition,
+ const u4Byte Hex
+ )
+{
+ u4Byte _board = (Hex & 0x000000FF);
+ u4Byte _interface = (Hex & 0x0000FF00) >> 8;
+ u4Byte _platform = (Hex & 0x00FF0000) >> 16;
+ u4Byte cond = Condition;
+
+ if ( Condition == 0xCDCDCDCD )
+ return TRUE;
+
+ cond = Condition & 0x000000FF;
+ if ( (_board == cond) && cond != 0x00)
+ return FALSE;
+
+ cond = Condition & 0x0000FF00;
+ cond = cond >> 8;
+ if ( (_interface & cond) == 0 && cond != 0x07)
+ return FALSE;
+
+ cond = Condition & 0x00FF0000;
+ cond = cond >> 16;
+ if ( (_platform & cond) == 0 && cond != 0x0F)
+ return FALSE;
+ return TRUE;
+}
+
+
+/******************************************************************************
+* AGC_TAB_1T.TXT
+******************************************************************************/
+
+u4Byte Array_AGC_TAB_1T_8188E[] = {
+ 0xC78, 0xFB000001,
+ 0xC78, 0xFB010001,
+ 0xC78, 0xFB020001,
+ 0xC78, 0xFB030001,
+ 0xC78, 0xFB040001,
+ 0xC78, 0xFB050001,
+ 0xC78, 0xFA060001,
+ 0xC78, 0xF9070001,
+ 0xC78, 0xF8080001,
+ 0xC78, 0xF7090001,
+ 0xC78, 0xF60A0001,
+ 0xC78, 0xF50B0001,
+ 0xC78, 0xF40C0001,
+ 0xC78, 0xF30D0001,
+ 0xC78, 0xF20E0001,
+ 0xC78, 0xF10F0001,
+ 0xC78, 0xF0100001,
+ 0xC78, 0xEF110001,
+ 0xC78, 0xEE120001,
+ 0xC78, 0xED130001,
+ 0xC78, 0xEC140001,
+ 0xC78, 0xEB150001,
+ 0xC78, 0xEA160001,
+ 0xC78, 0xE9170001,
+ 0xC78, 0xE8180001,
+ 0xC78, 0xE7190001,
+ 0xC78, 0xE61A0001,
+ 0xC78, 0xE51B0001,
+ 0xC78, 0xE41C0001,
+ 0xC78, 0xE31D0001,
+ 0xC78, 0xE21E0001,
+ 0xC78, 0xE11F0001,
+ 0xC78, 0x8A200001,
+ 0xC78, 0x89210001,
+ 0xC78, 0x88220001,
+ 0xC78, 0x87230001,
+ 0xC78, 0x86240001,
+ 0xC78, 0x85250001,
+ 0xC78, 0x84260001,
+ 0xC78, 0x83270001,
+ 0xC78, 0x82280001,
+ 0xC78, 0x6B290001,
+ 0xC78, 0x6A2A0001,
+ 0xC78, 0x692B0001,
+ 0xC78, 0x682C0001,
+ 0xC78, 0x672D0001,
+ 0xC78, 0x662E0001,
+ 0xC78, 0x652F0001,
+ 0xC78, 0x64300001,
+ 0xC78, 0x63310001,
+ 0xC78, 0x62320001,
+ 0xC78, 0x61330001,
+ 0xC78, 0x46340001,
+ 0xC78, 0x45350001,
+ 0xC78, 0x44360001,
+ 0xC78, 0x43370001,
+ 0xC78, 0x42380001,
+ 0xC78, 0x41390001,
+ 0xC78, 0x403A0001,
+ 0xC78, 0x403B0001,
+ 0xC78, 0x403C0001,
+ 0xC78, 0x403D0001,
+ 0xC78, 0x403E0001,
+ 0xC78, 0x403F0001,
+ 0xC78, 0xFB400001,
+ 0xC78, 0xFB410001,
+ 0xC78, 0xFB420001,
+ 0xC78, 0xFB430001,
+ 0xC78, 0xFB440001,
+ 0xC78, 0xFB450001,
+ 0xC78, 0xFB460001,
+ 0xC78, 0xFB470001,
+ 0xC78, 0xFB480001,
+ 0xC78, 0xFA490001,
+ 0xC78, 0xF94A0001,
+ 0xC78, 0xF84B0001,
+ 0xC78, 0xF74C0001,
+ 0xC78, 0xF64D0001,
+ 0xC78, 0xF54E0001,
+ 0xC78, 0xF44F0001,
+ 0xC78, 0xF3500001,
+ 0xC78, 0xF2510001,
+ 0xC78, 0xF1520001,
+ 0xC78, 0xF0530001,
+ 0xC78, 0xEF540001,
+ 0xC78, 0xEE550001,
+ 0xC78, 0xED560001,
+ 0xC78, 0xEC570001,
+ 0xC78, 0xEB580001,
+ 0xC78, 0xEA590001,
+ 0xC78, 0xE95A0001,
+ 0xC78, 0xE85B0001,
+ 0xC78, 0xE75C0001,
+ 0xC78, 0xE65D0001,
+ 0xC78, 0xE55E0001,
+ 0xC78, 0xE45F0001,
+ 0xC78, 0xE3600001,
+ 0xC78, 0xE2610001,
+ 0xC78, 0xC3620001,
+ 0xC78, 0xC2630001,
+ 0xC78, 0xC1640001,
+ 0xC78, 0x8B650001,
+ 0xC78, 0x8A660001,
+ 0xC78, 0x89670001,
+ 0xC78, 0x88680001,
+ 0xC78, 0x87690001,
+ 0xC78, 0x866A0001,
+ 0xC78, 0x856B0001,
+ 0xC78, 0x846C0001,
+ 0xC78, 0x676D0001,
+ 0xC78, 0x666E0001,
+ 0xC78, 0x656F0001,
+ 0xC78, 0x64700001,
+ 0xC78, 0x63710001,
+ 0xC78, 0x62720001,
+ 0xC78, 0x61730001,
+ 0xC78, 0x60740001,
+ 0xC78, 0x46750001,
+ 0xC78, 0x45760001,
+ 0xC78, 0x44770001,
+ 0xC78, 0x43780001,
+ 0xC78, 0x42790001,
+ 0xC78, 0x417A0001,
+ 0xC78, 0x407B0001,
+ 0xC78, 0x407C0001,
+ 0xC78, 0x407D0001,
+ 0xC78, 0x407E0001,
+ 0xC78, 0x407F0001,
+};
+
+HAL_STATUS
+ODM_ReadAndConfig_AGC_TAB_1T_8188E(
+ IN PDM_ODM_T pDM_Odm
+ )
+{
+ #define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0)
+
+ u4Byte hex = 0;
+ u4Byte i = 0;
+ u2Byte count = 0;
+ pu4Byte ptr_array = NULL;
+ u1Byte platform = pDM_Odm->SupportPlatform;
+ u1Byte interfaceValue = pDM_Odm->SupportInterface;
+ u1Byte board = pDM_Odm->BoardType;
+ u4Byte ArrayLen = sizeof(Array_AGC_TAB_1T_8188E)/sizeof(u4Byte);
+ pu4Byte Array = Array_AGC_TAB_1T_8188E;
+ BOOLEAN biol = FALSE;
+#ifdef CONFIG_IOL_IOREG_CFG
+ PADAPTER Adapter = pDM_Odm->Adapter;
+ struct xmit_frame *pxmit_frame;
+ u8 bndy_cnt=1;
+#endif//#ifdef CONFIG_IOL_IOREG_CFG
+ HAL_STATUS rst =HAL_STATUS_SUCCESS;
+
+ hex += board;
+ hex += interfaceValue << 8;
+ hex += platform << 16;
+ hex += 0xFF000000;
+#ifdef CONFIG_IOL_IOREG_CFG
+ biol = rtw_IOL_applied(Adapter);
+
+ if(biol){
+ if((pxmit_frame= rtw_IOL_accquire_xmit_frame(Adapter)) == NULL){
+ printk("rtw_IOL_accquire_xmit_frame failed\n");
+ return HAL_STATUS_FAILURE;
+ }
+ }
+#endif//#ifdef CONFIG_IOL_IOREG_CFG
+
+ for (i = 0; i < ArrayLen; i += 2 )
+ {
+ u4Byte v1 = Array[i];
+ u4Byte v2 = Array[i+1];
+
+ // This (offset, data) pair meets the condition.
+ if ( v1 < 0xCDCDCDCD )
+ {
+ #ifdef CONFIG_IOL_IOREG_CFG
+ if(biol){
+ if(rtw_IOL_cmd_boundary_handle(pxmit_frame))
+ bndy_cnt++;
+ rtw_IOL_append_WD_cmd(pxmit_frame,(u2Byte)v1, v2,bMaskDWord);
+ }
+ else
+ #endif //#ifdef CONFIG_IOL_IOREG_CFG
+ {
+ odm_ConfigBB_AGC_8188E(pDM_Odm, v1, bMaskDWord, v2);
+ }
+ continue;
+ }
+ else
+ { // This line is the start line of branch.
+ if ( !CheckCondition(Array[i], hex) )
+ { // Discard the following (offset, data) pairs.
+ READ_NEXT_PAIR(v1, v2, i);
+ while ( v2 != 0xDEAD &&
+ v2 != 0xCDEF &&
+ v2 != 0xCDCD && i < ArrayLen -2)
+ {
+ READ_NEXT_PAIR(v1, v2, i);
+ }
+ i -= 2; // prevent from for-loop += 2
+ }
+ else // Configure matched pairs and skip to end of if-else.
+ {
+ READ_NEXT_PAIR(v1, v2, i);
+ while ( v2 != 0xDEAD &&
+ v2 != 0xCDEF &&
+ v2 != 0xCDCD && i < ArrayLen -2)
+ {
+ #ifdef CONFIG_IOL_IOREG_CFG
+ if(biol){
+ if(rtw_IOL_cmd_boundary_handle(pxmit_frame))
+ bndy_cnt++;
+ rtw_IOL_append_WD_cmd(pxmit_frame,(u2Byte)v1, v2,bMaskDWord);
+ }
+ else
+ #endif //#ifdef CONFIG_IOL_IOREG_CFG
+ {
+ odm_ConfigBB_AGC_8188E(pDM_Odm, v1, bMaskDWord, v2);
+ }
+ READ_NEXT_PAIR(v1, v2, i);
+ }
+
+ while (v2 != 0xDEAD && i < ArrayLen -2)
+ {
+ READ_NEXT_PAIR(v1, v2, i);
+ }
+
+ }
+ }
+ }
+#ifdef CONFIG_IOL_IOREG_CFG
+ if(biol){
+ //printk("==> %s, pktlen = %d,bndy_cnt = %d\n",__FUNCTION__,pxmit_frame->attrib.pktlen+4+32,bndy_cnt);
+ if(rtw_IOL_exec_cmds_sync(pDM_Odm->Adapter, pxmit_frame, 1000, bndy_cnt))
+ {
+ #ifdef CONFIG_IOL_IOREG_CFG_DBG
+ printk("~~~ %s Success !!! \n",__FUNCTION__);
+ {
+ //dump data from TX packet buffer
+ rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32);
+ }
+ #endif //CONFIG_IOL_IOREG_CFG_DBG
+
+ }
+ else{
+ printk("~~~ %s IOL_exec_cmds Failed !!! \n",__FUNCTION__);
+ #ifdef CONFIG_IOL_IOREG_CFG_DBG
+ {
+ //dump data from TX packet buffer
+ rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32);
+ }
+ #endif //CONFIG_IOL_IOREG_CFG_DBG
+
+ rst = HAL_STATUS_FAILURE;
+ }
+ }
+#endif //#ifdef CONFIG_IOL_IOREG_CFG
+ return rst;
+}
+
+/******************************************************************************
+* PHY_REG_1T.TXT
+******************************************************************************/
+
+u4Byte Array_PHY_REG_1T_8188E[] = {
+ 0x800, 0x80040000,
+ 0x804, 0x00000003,
+ 0x808, 0x0000FC00,
+ 0x80C, 0x0000000A,
+ 0x810, 0x10001331,
+ 0x814, 0x020C3D10,
+ 0x818, 0x02200385,
+ 0x81C, 0x00000000,
+ 0x820, 0x01000100,
+ 0x824, 0x00390204,
+ 0x828, 0x00000000,
+ 0x82C, 0x00000000,
+ 0x830, 0x00000000,
+ 0x834, 0x00000000,
+ 0x838, 0x00000000,
+ 0x83C, 0x00000000,
+ 0x840, 0x00010000,
+ 0x844, 0x00000000,
+ 0x848, 0x00000000,
+ 0x84C, 0x00000000,
+ 0x850, 0x00000000,
+ 0x854, 0x00000000,
+ 0x858, 0x569A11A9,
+ 0x85C, 0x01000014,
+ 0x860, 0x66F60110,
+ 0x864, 0x061F0649,
+ 0x868, 0x00000000,
+ 0x86C, 0x27272700,
+ 0x870, 0x07000760,
+ 0x874, 0x25004000,
+ 0x878, 0x00000808,
+ 0x87C, 0x00000000,
+ 0x880, 0xB0000C1C,
+ 0x884, 0x00000001,
+ 0x888, 0x00000000,
+ 0x88C, 0xCCC000C0,
+ 0x890, 0x00000800,
+ 0x894, 0xFFFFFFFE,
+ 0x898, 0x40302010,
+ 0x89C, 0x00706050,
+ 0x900, 0x00000000,
+ 0x904, 0x00000023,
+ 0x908, 0x00000000,
+ 0x90C, 0x81121111,
+ 0x910, 0x00000002,
+ 0x914, 0x00000201,
+ 0xA00, 0x00D047C8,
+ 0xA04, 0x80FF000C,
+ 0xA08, 0x8C838300,
+ 0xA0C, 0x2E7F120F,
+ 0xA10, 0x9500BB78,
+ 0xA14, 0x1114D028,
+ 0xA18, 0x00881117,
+ 0xA1C, 0x89140F00,
+ 0xA20, 0x1A1B0000,
+ 0xA24, 0x090E1317,
+ 0xA28, 0x00000204,
+ 0xA2C, 0x00D30000,
+ 0xA70, 0x101FBF00,
+ 0xA74, 0x00000007,
+ 0xA78, 0x00000900,
+ 0xA7C, 0x225B0606,
+ 0xA80, 0x218075B1,
+ 0xB2C, 0x80000000,
+ 0xC00, 0x48071D40,
+ 0xC04, 0x03A05611,
+ 0xC08, 0x000000E4,
+ 0xC0C, 0x6C6C6C6C,
+ 0xC10, 0x08800000,
+ 0xC14, 0x40000100,
+ 0xC18, 0x08800000,
+ 0xC1C, 0x40000100,
+ 0xC20, 0x00000000,
+ 0xC24, 0x00000000,
+ 0xC28, 0x00000000,
+ 0xC2C, 0x00000000,
+ 0xC30, 0x69E9AC47,
+ 0xC34, 0x469652AF,
+ 0xC38, 0x49795994,
+ 0xC3C, 0x0A97971C,
+ 0xC40, 0x1F7C403F,
+ 0xC44, 0x000100B7,
+ 0xC48, 0xEC020107,
+ 0xC4C, 0x007F037F,
+ 0xC50, 0x69553420,
+ 0xC54, 0x43BC0094,
+ 0xC58, 0x00013169,
+ 0xC5C, 0x00250492,
+ 0xC60, 0x00000000,
+ 0xC64, 0x7112848B,
+ 0xC68, 0x47C00BFF,
+ 0xC6C, 0x00000036,
+ 0xC70, 0x2C7F000D,
+ 0xC74, 0x020610DB,
+ 0xC78, 0x0000001F,
+ 0xC7C, 0x00B91612,
+ 0xC80, 0x390000E4,
+ 0xC84, 0x20F60000,
+ 0xC88, 0x40000100,
+ 0xC8C, 0x20200000,
+ 0xC90, 0x00091521,
+ 0xC94, 0x00000000,
+ 0xC98, 0x00121820,
+ 0xC9C, 0x00007F7F,
+ 0xCA0, 0x00000000,
+ 0xCA4, 0x000300A0,
+ 0xCA8, 0x00000000,
+ 0xCAC, 0x00000000,
+ 0xCB0, 0x00000000,
+ 0xCB4, 0x00000000,
+ 0xCB8, 0x00000000,
+ 0xCBC, 0x28000000,
+ 0xCC0, 0x00000000,
+ 0xCC4, 0x00000000,
+ 0xCC8, 0x00000000,
+ 0xCCC, 0x00000000,
+ 0xCD0, 0x00000000,
+ 0xCD4, 0x00000000,
+ 0xCD8, 0x64B22427,
+ 0xCDC, 0x00766932,
+ 0xCE0, 0x00222222,
+ 0xCE4, 0x00000000,
+ 0xCE8, 0x37644302,
+ 0xCEC, 0x2F97D40C,
+ 0xD00, 0x00000740,
+ 0xD04, 0x00020401,
+ 0xD08, 0x0000907F,
+ 0xD0C, 0x20010201,
+ 0xD10, 0xA0633333,
+ 0xD14, 0x3333BC43,
+ 0xD18, 0x7A8F5B6F,
+ 0xD2C, 0xCC979975,
+ 0xD30, 0x00000000,
+ 0xD34, 0x80608000,
+ 0xD38, 0x00000000,
+ 0xD3C, 0x00127353,
+ 0xD40, 0x00000000,
+ 0xD44, 0x00000000,
+ 0xD48, 0x00000000,
+ 0xD4C, 0x00000000,
+ 0xD50, 0x6437140A,
+ 0xD54, 0x00000000,
+ 0xD58, 0x00000282,
+ 0xD5C, 0x30032064,
+ 0xD60, 0x4653DE68,
+ 0xD64, 0x04518A3C,
+ 0xD68, 0x00002101,
+ 0xD6C, 0x2A201C16,
+ 0xD70, 0x1812362E,
+ 0xD74, 0x322C2220,
+ 0xD78, 0x000E3C24,
+ 0xE00, 0x2D2D2D2D,
+ 0xE04, 0x2D2D2D2D,
+ 0xE08, 0x0390272D,
+ 0xE10, 0x2D2D2D2D,
+ 0xE14, 0x2D2D2D2D,
+ 0xE18, 0x2D2D2D2D,
+ 0xE1C, 0x2D2D2D2D,
+ 0xE28, 0x00000000,
+ 0xE30, 0x1000DC1F,
+ 0xE34, 0x10008C1F,
+ 0xE38, 0x02140102,
+ 0xE3C, 0x681604C2,
+ 0xE40, 0x01007C00,
+ 0xE44, 0x01004800,
+ 0xE48, 0xFB000000,
+ 0xE4C, 0x000028D1,
+ 0xE50, 0x1000DC1F,
+ 0xE54, 0x10008C1F,
+ 0xE58, 0x02140102,
+ 0xE5C, 0x28160D05,
+ 0xE60, 0x00000008,
+ 0xE68, 0x001B25A4,
+ 0xE6C, 0x00C00014,
+ 0xE70, 0x00C00014,
+ 0xE74, 0x01000014,
+ 0xE78, 0x01000014,
+ 0xE7C, 0x01000014,
+ 0xE80, 0x01000014,
+ 0xE84, 0x00C00014,
+ 0xE88, 0x01000014,
+ 0xE8C, 0x00C00014,
+ 0xED0, 0x00C00014,
+ 0xED4, 0x00C00014,
+ 0xED8, 0x00C00014,
+ 0xEDC, 0x00000014,
+ 0xEE0, 0x00000014,
+ 0xEEC, 0x01C00014,
+ 0xF14, 0x00000003,
+ 0xF4C, 0x00000000,
+ 0xF00, 0x00000300,
+};
+
+
+HAL_STATUS
+ODM_ReadAndConfig_PHY_REG_1T_8188E(
+ IN PDM_ODM_T pDM_Odm
+ )
+{
+ #define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0)
+
+ u4Byte hex = 0;
+ u4Byte i = 0;
+ u2Byte count = 0;
+ pu4Byte ptr_array = NULL;
+ u1Byte platform = pDM_Odm->SupportPlatform;
+ u1Byte interfaceValue = pDM_Odm->SupportInterface;
+ u1Byte board = pDM_Odm->BoardType;
+ u4Byte ArrayLen = sizeof(Array_PHY_REG_1T_8188E)/sizeof(u4Byte);
+ pu4Byte Array = Array_PHY_REG_1T_8188E;
+ BOOLEAN biol = FALSE;
+#ifdef CONFIG_IOL_IOREG_CFG
+ PADAPTER Adapter = pDM_Odm->Adapter;
+ struct xmit_frame *pxmit_frame;
+ u8 bndy_cnt=1;
+ #ifdef CONFIG_IOL_IOREG_CFG_DBG
+ struct cmd_cmp cmpdata[ArrayLen];
+ u4Byte cmpdata_idx=0;
+ #endif
+#endif//#ifdef CONFIG_IOL_IOREG_CFG
+ HAL_STATUS rst =HAL_STATUS_SUCCESS;
+ hex += board;
+ hex += interfaceValue << 8;
+ hex += platform << 16;
+ hex += 0xFF000000;
+#ifdef CONFIG_IOL_IOREG_CFG
+ biol = rtw_IOL_applied(Adapter);
+
+ if(biol){
+ if((pxmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL)
+ {
+ printk("rtw_IOL_accquire_xmit_frame failed\n");
+ return HAL_STATUS_FAILURE;
+ }
+ }
+#endif//#ifdef CONFIG_IOL_IOREG_CFG
+
+ for (i = 0; i < ArrayLen; i += 2 )
+ {
+ u4Byte v1 = Array[i];
+ u4Byte v2 = Array[i+1];
+
+
+ // This (offset, data) pair meets the condition.
+ if ( v1 < 0xCDCDCDCD )
+ {
+ #ifdef CONFIG_IOL_IOREG_CFG
+ if(biol){
+ if(rtw_IOL_cmd_boundary_handle(pxmit_frame))
+ bndy_cnt++;
+
+
+ if (v1 == 0xfe){
+ rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,50);
+ }
+ else if (v1 == 0xfd){
+ rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,5);
+ }
+ else if (v1 == 0xfc){
+ rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,1);
+ }
+ else if (v1 == 0xfb){
+ rtw_IOL_append_DELAY_US_cmd(pxmit_frame,50);
+ }
+ else if (v1 == 0xfa){
+ rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 5);
+ }
+ else if (v1 == 0xf9){
+ rtw_IOL_append_DELAY_US_cmd(pxmit_frame,1);
+ }
+ else{
+ if (v1 == 0xa24)
+ pDM_Odm->RFCalibrateInfo.RegA24 = v2;
+
+ rtw_IOL_append_WD_cmd(pxmit_frame,(u2Byte)v1, v2,bMaskDWord);
+ #ifdef CONFIG_IOL_IOREG_CFG_DBG
+ cmpdata[cmpdata_idx].addr = v1;
+ cmpdata[cmpdata_idx].value= v2;
+ cmpdata_idx++;
+ #endif
+ }
+ }
+ else
+ #endif //#ifdef CONFIG_IOL_IOREG_CFG
+ {
+ odm_ConfigBB_PHY_8188E(pDM_Odm, v1, bMaskDWord, v2);
+ }
+ continue;
+ }
+ else
+ { // This line is the start line of branch.
+ if ( !CheckCondition(Array[i], hex) )
+ { // Discard the following (offset, data) pairs.
+ READ_NEXT_PAIR(v1, v2, i);
+ while (v2 != 0xDEAD &&
+ v2 != 0xCDEF &&
+ v2 != 0xCDCD && i < ArrayLen -2)
+ {
+ READ_NEXT_PAIR(v1, v2, i);
+ }
+ i -= 2; // prevent from for-loop += 2
+ }
+ else // Configure matched pairs and skip to end of if-else.
+ {
+ READ_NEXT_PAIR(v1, v2, i);
+ while (v2 != 0xDEAD &&
+ v2 != 0xCDEF &&
+ v2 != 0xCDCD && i < ArrayLen -2)
+ {
+ #ifdef CONFIG_IOL_IOREG_CFG
+ if(biol){
+ if(rtw_IOL_cmd_boundary_handle(pxmit_frame))
+ bndy_cnt++;
+ if (v1 == 0xfe){
+ rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,50);
+ }
+ else if (v1 == 0xfd){
+ rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,5);
+ }
+ else if (v1 == 0xfc){
+ rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,1);
+ }
+ else if (v1 == 0xfb){
+ rtw_IOL_append_DELAY_US_cmd(pxmit_frame,50);
+ }
+ else if (v1 == 0xfa){
+ rtw_IOL_append_DELAY_US_cmd(pxmit_frame,5);
+ }
+ else if (v1 == 0xf9){
+ rtw_IOL_append_DELAY_US_cmd(pxmit_frame,1);
+ }
+ else{
+ if (v1 == 0xa24)
+ pDM_Odm->RFCalibrateInfo.RegA24 = v2;
+
+ rtw_IOL_append_WD_cmd(pxmit_frame,(u2Byte)v1, v2,bMaskDWord);
+ #ifdef CONFIG_IOL_IOREG_CFG_DBG
+ cmpdata[cmpdata_idx].addr = v1;
+ cmpdata[cmpdata_idx].value= v2;
+ cmpdata_idx++;
+ #endif
+ }
+ }
+ else
+ #endif //#ifdef CONFIG_IOL_IOREG_CFG
+ {
+ odm_ConfigBB_PHY_8188E(pDM_Odm, v1, bMaskDWord, v2);
+ }
+ READ_NEXT_PAIR(v1, v2, i);
+ }
+
+ while (v2 != 0xDEAD && i < ArrayLen -2)
+ {
+ READ_NEXT_PAIR(v1, v2, i);
+ }
+
+ }
+ }
+ }
+#ifdef CONFIG_IOL_IOREG_CFG
+ if(biol){
+ //printk("==> %s, pktlen = %d,bndy_cnt = %d\n",__FUNCTION__,pxmit_frame->attrib.pktlen+4+32,bndy_cnt);
+ if(rtw_IOL_exec_cmds_sync(pDM_Odm->Adapter, pxmit_frame, 1000, bndy_cnt))
+ {
+ #ifdef CONFIG_IOL_IOREG_CFG_DBG
+ printk("~~~ %s IOL_exec_cmds Success !!! \n",__FUNCTION__);
+ {
+ u4Byte idx;
+ u4Byte cdata;
+ printk(" %s data compare => array_len:%d \n",__FUNCTION__,cmpdata_idx);
+ printk("### %s data compared !!###\n",__FUNCTION__);
+ for(idx=0;idx< cmpdata_idx;idx++)
+ {
+ cdata = ODM_Read4Byte(pDM_Odm, cmpdata[idx].addr);
+ if(cdata != cmpdata[idx].value){
+ printk(" addr:0x%04x, data:(0x%02x : 0x%02x) \n",
+ cmpdata[idx].addr,cmpdata[idx].value,cdata);
+ rst = HAL_STATUS_FAILURE;
+ }
+ }
+ printk("### %s data compared !!###\n",__FUNCTION__);
+ //if(rst == HAL_STATUS_FAILURE)
+ {//dump data from TX packet buffer
+ rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32);
+ }
+
+ }
+ #endif //CONFIG_IOL_IOREG_CFG_DBG
+
+ }
+ else{
+ rst = HAL_STATUS_FAILURE;
+ printk("~~~ IOL Config %s Failed !!! \n",__FUNCTION__);
+ #ifdef CONFIG_IOL_IOREG_CFG_DBG
+ {
+ //dump data from TX packet buffer
+ rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32);
+ }
+ #endif //CONFIG_IOL_IOREG_CFG_DBG
+ }
+ }
+#endif //#ifdef CONFIG_IOL_IOREG_CFG
+ return rst;
+}
+
+/******************************************************************************
+* PHY_REG_PG.TXT
+******************************************************************************/
+
+u4Byte Array_PHY_REG_PG_8188E[] = {
+ 0xE00, 0xFFFFFFFF, 0x06070809,
+ 0xE04, 0xFFFFFFFF, 0x02020405,
+ 0xE08, 0x0000FF00, 0x00000006,
+ 0x86C, 0xFFFFFF00, 0x00020400,
+ 0xE10, 0xFFFFFFFF, 0x08090A0B,
+ 0xE14, 0xFFFFFFFF, 0x01030607,
+ 0xE18, 0xFFFFFFFF, 0x08090A0B,
+ 0xE1C, 0xFFFFFFFF, 0x01030607,
+ 0xE00, 0xFFFFFFFF, 0x00000000,
+ 0xE04, 0xFFFFFFFF, 0x00000000,
+ 0xE08, 0x0000FF00, 0x00000000,
+ 0x86C, 0xFFFFFF00, 0x00000000,
+ 0xE10, 0xFFFFFFFF, 0x00000000,
+ 0xE14, 0xFFFFFFFF, 0x00000000,
+ 0xE18, 0xFFFFFFFF, 0x00000000,
+ 0xE1C, 0xFFFFFFFF, 0x00000000,
+ 0xE00, 0xFFFFFFFF, 0x02020202,
+ 0xE04, 0xFFFFFFFF, 0x00020202,
+ 0xE08, 0x0000FF00, 0x00000000,
+ 0x86C, 0xFFFFFF00, 0x00000000,
+ 0xE10, 0xFFFFFFFF, 0x04040404,
+ 0xE14, 0xFFFFFFFF, 0x00020404,
+ 0xE18, 0xFFFFFFFF, 0x00000000,
+ 0xE1C, 0xFFFFFFFF, 0x00000000,
+ 0xE00, 0xFFFFFFFF, 0x02020202,
+ 0xE04, 0xFFFFFFFF, 0x00020202,
+ 0xE08, 0x0000FF00, 0x00000000,
+ 0x86C, 0xFFFFFF00, 0x00000000,
+ 0xE10, 0xFFFFFFFF, 0x04040404,
+ 0xE14, 0xFFFFFFFF, 0x00020404,
+ 0xE18, 0xFFFFFFFF, 0x00000000,
+ 0xE1C, 0xFFFFFFFF, 0x00000000,
+ 0xE00, 0xFFFFFFFF, 0x00000000,
+ 0xE04, 0xFFFFFFFF, 0x00000000,
+ 0xE08, 0x0000FF00, 0x00000000,
+ 0x86C, 0xFFFFFF00, 0x00000000,
+ 0xE10, 0xFFFFFFFF, 0x00000000,
+ 0xE14, 0xFFFFFFFF, 0x00000000,
+ 0xE18, 0xFFFFFFFF, 0x00000000,
+ 0xE1C, 0xFFFFFFFF, 0x00000000,
+ 0xE00, 0xFFFFFFFF, 0x02020202,
+ 0xE04, 0xFFFFFFFF, 0x00020202,
+ 0xE08, 0x0000FF00, 0x00000000,
+ 0x86C, 0xFFFFFF00, 0x00000000,
+ 0xE10, 0xFFFFFFFF, 0x04040404,
+ 0xE14, 0xFFFFFFFF, 0x00020404,
+ 0xE18, 0xFFFFFFFF, 0x00000000,
+ 0xE1C, 0xFFFFFFFF, 0x00000000,
+ 0xE00, 0xFFFFFFFF, 0x00000000,
+ 0xE04, 0xFFFFFFFF, 0x00000000,
+ 0xE08, 0x0000FF00, 0x00000000,
+ 0x86C, 0xFFFFFF00, 0x00000000,
+ 0xE10, 0xFFFFFFFF, 0x00000000,
+ 0xE14, 0xFFFFFFFF, 0x00000000,
+ 0xE18, 0xFFFFFFFF, 0x00000000,
+ 0xE1C, 0xFFFFFFFF, 0x00000000,
+ 0xE00, 0xFFFFFFFF, 0x00000000,
+ 0xE04, 0xFFFFFFFF, 0x00000000,
+ 0xE08, 0x0000FF00, 0x00000000,
+ 0x86C, 0xFFFFFF00, 0x00000000,
+ 0xE10, 0xFFFFFFFF, 0x00000000,
+ 0xE14, 0xFFFFFFFF, 0x00000000,
+ 0xE18, 0xFFFFFFFF, 0x00000000,
+ 0xE1C, 0xFFFFFFFF, 0x00000000,
+ 0xE00, 0xFFFFFFFF, 0x00000000,
+ 0xE04, 0xFFFFFFFF, 0x00000000,
+ 0xE08, 0x0000FF00, 0x00000000,
+ 0x86C, 0xFFFFFF00, 0x00000000,
+ 0xE10, 0xFFFFFFFF, 0x00000000,
+ 0xE14, 0xFFFFFFFF, 0x00000000,
+ 0xE18, 0xFFFFFFFF, 0x00000000,
+ 0xE1C, 0xFFFFFFFF, 0x00000000,
+ 0xE00, 0xFFFFFFFF, 0x00000000,
+ 0xE04, 0xFFFFFFFF, 0x00000000,
+ 0xE08, 0x0000FF00, 0x00000000,
+ 0x86C, 0xFFFFFF00, 0x00000000,
+ 0xE10, 0xFFFFFFFF, 0x00000000,
+ 0xE14, 0xFFFFFFFF, 0x00000000,
+ 0xE18, 0xFFFFFFFF, 0x00000000,
+ 0xE1C, 0xFFFFFFFF, 0x00000000,
+ 0xE00, 0xFFFFFFFF, 0x00000000,
+ 0xE04, 0xFFFFFFFF, 0x00000000,
+ 0xE08, 0x0000FF00, 0x00000000,
+ 0x86C, 0xFFFFFF00, 0x00000000,
+ 0xE10, 0xFFFFFFFF, 0x00000000,
+ 0xE14, 0xFFFFFFFF, 0x00000000,
+ 0xE18, 0xFFFFFFFF, 0x00000000,
+ 0xE1C, 0xFFFFFFFF, 0x00000000,
+
+};
+
+void
+ODM_ReadAndConfig_PHY_REG_PG_8188E(
+ IN PDM_ODM_T pDM_Odm
+ )
+{
+ u4Byte hex = 0;
+ u4Byte i = 0;
+ u2Byte count = 0;
+ pu4Byte ptr_array = NULL;
+ u1Byte platform = pDM_Odm->SupportPlatform;
+ u1Byte interfaceValue = pDM_Odm->SupportInterface;
+ u1Byte board = pDM_Odm->BoardType;
+ u4Byte ArrayLen = sizeof(Array_PHY_REG_PG_8188E)/sizeof(u4Byte);
+ pu4Byte Array = Array_PHY_REG_PG_8188E;
+ BOOLEAN biol = FALSE;
+
+ hex += board;
+ hex += interfaceValue << 8;
+ hex += platform << 16;
+ hex += 0xFF000000;
+
+ for (i = 0; i < ArrayLen; i += 3 )
+ {
+ u4Byte v1 = Array[i];
+ u4Byte v2 = Array[i+1];
+ u4Byte v3 = Array[i+2];
+
+ // this line is a line of pure_body
+ if ( v1 < 0xCDCDCDCD )
+ {
+
+ odm_ConfigBB_PHY_REG_PG_8188E(pDM_Odm, v1, v2, v3);
+
+ continue;
+ }
+ else
+ { // this line is the start of branch
+ if ( !CheckCondition(Array[i], hex) )
+ { // don't need the hw_body
+ i += 2; // skip the pair of expression
+ v1 = Array[i];
+ v2 = Array[i+1];
+ v3 = Array[i+2];
+ while (v2 != 0xDEAD)
+ {
+ i += 3;
+ v1 = Array[i];
+ v2 = Array[i+1];
+ v3 = Array[i+1];
+ }
+ }
+ }
+ }
+
+}
+
+
+
+#endif // end of HWIMG_SUPPORT
+
diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_BB.h b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_BB.h new file mode 100755 index 00000000..1b92f29f --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_BB.h @@ -0,0 +1,56 @@ +/******************************************************************************
+*
+* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms of version 2 of the GNU General Public License as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful, but WITHOUT
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+* more details.
+*
+* You should have received a copy of the GNU General Public License along with
+* this program; if not, write to the Free Software Foundation, Inc.,
+* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+*
+*
+******************************************************************************/
+
+#if (RTL8188E_SUPPORT == 1)
+#ifndef __INC_BB_8188E_HW_IMG_H
+#define __INC_BB_8188E_HW_IMG_H
+
+//static BOOLEAN CheckCondition(const u4Byte Condition, const u4Byte Hex);
+
+/******************************************************************************
+* AGC_TAB_1T.TXT
+******************************************************************************/
+
+HAL_STATUS
+ODM_ReadAndConfig_AGC_TAB_1T_8188E(
+ IN PDM_ODM_T pDM_Odm
+);
+
+/******************************************************************************
+* PHY_REG_1T.TXT
+******************************************************************************/
+
+HAL_STATUS
+ODM_ReadAndConfig_PHY_REG_1T_8188E(
+ IN PDM_ODM_T pDM_Odm
+);
+
+/******************************************************************************
+* PHY_REG_PG.TXT
+******************************************************************************/
+
+void
+ODM_ReadAndConfig_PHY_REG_PG_8188E(
+ IN PDM_ODM_T pDM_Odm
+);
+
+#endif
+#endif // end of HWIMG_SUPPORT
+
diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_FW.c b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_FW.c new file mode 100755 index 00000000..a515df2d --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_FW.c @@ -0,0 +1,1077 @@ +/******************************************************************************
+*
+* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms of version 2 of the GNU General Public License as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful, but WITHOUT
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+* more details.
+*
+* You should have received a copy of the GNU General Public License along with
+* this program; if not, write to the Free Software Foundation, Inc.,
+* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+*
+*
+******************************************************************************/
+#if 0
+#include "Mp_Precomp.h"
+#endif
+#include "../odm_precomp.h"
+
+#if (RTL8188E_SUPPORT == 1)
+#if(DM_ODM_SUPPORT_TYPE & (ODM_AP))
+
+
+u1Byte Array_8188E_FW_AP[] = {
+
+};
+u4Byte ArrayLength_8188E_FW_AP = 0;
+
+
+void
+ODM_ReadFirmware_8188E_FW_AP(
+ IN PDM_ODM_T pDM_Odm,
+ OUT u1Byte *pFirmware,
+ OUT u4Byte *pFirmwareSize
+)
+{
+ ODM_MoveMemory(pDM_Odm, pFirmware, Array_8188E_FW_AP, ArrayLength_8188E_FW_AP);
+ *pFirmwareSize = ArrayLength_8188E_FW_AP;
+}
+
+
+#else
+
+#if 0
+u1Byte Array_8188E_FW_NIC[] = {
+
+};
+u4Byte ArrayLength_8188E_FW_NIC = 0;
+
+
+void
+ODM_ReadFirmware_8188E_FW_NIC(
+ IN PDM_ODM_T pDM_Odm,
+ OUT u1Byte *pFirmware,
+ OUT u4Byte *pFirmwareSize
+)
+{
+ ODM_MoveMemory(pDM_Odm, pFirmware, Array_8188E_FW_NIC, ArrayLength_8188E_FW_NIC);
+ *pFirmwareSize = ArrayLength_8188E_FW_NIC;
+}
+#endif
+
+const u8 Array_8188E_FW_WoWLAN[] = {
+0xE1, 0x88, 0x30, 0x00, 0x0B, 0x00, 0x01, 0x00, 0x01, 0x21, 0x11, 0x27, 0x74, 0x3D, 0x00, 0x00,
+0x2D, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x02, 0x48, 0xF7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x02, 0x4A, 0x3A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x02, 0x49, 0xB1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x4F, 0xDE, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0xE7, 0x09, 0xF6, 0x08, 0xDF, 0xFA, 0x80, 0x46, 0xE7, 0x09, 0xF2, 0x08, 0xDF, 0xFA, 0x80, 0x3E,
+0x88, 0x82, 0x8C, 0x83, 0xE7, 0x09, 0xF0, 0xA3, 0xDF, 0xFA, 0x80, 0x32, 0xE3, 0x09, 0xF6, 0x08,
+0xDF, 0xFA, 0x80, 0x78, 0xE3, 0x09, 0xF2, 0x08, 0xDF, 0xFA, 0x80, 0x70, 0x88, 0x82, 0x8C, 0x83,
+0xE3, 0x09, 0xF0, 0xA3, 0xDF, 0xFA, 0x80, 0x64, 0x89, 0x82, 0x8A, 0x83, 0xE0, 0xA3, 0xF6, 0x08,
+0xDF, 0xFA, 0x80, 0x58, 0x89, 0x82, 0x8A, 0x83, 0xE0, 0xA3, 0xF2, 0x08, 0xDF, 0xFA, 0x80, 0x4C,
+0x80, 0xD2, 0x80, 0xFA, 0x80, 0xC6, 0x80, 0xD4, 0x80, 0x69, 0x80, 0xF2, 0x80, 0x33, 0x80, 0x10,
+0x80, 0xA6, 0x80, 0xEA, 0x80, 0x9A, 0x80, 0xA8, 0x80, 0xDA, 0x80, 0xE2, 0x80, 0xCA, 0x80, 0x33,
+0x89, 0x82, 0x8A, 0x83, 0xEC, 0xFA, 0xE4, 0x93, 0xA3, 0xC8, 0xC5, 0x82, 0xC8, 0xCC, 0xC5, 0x83,
+0xCC, 0xF0, 0xA3, 0xC8, 0xC5, 0x82, 0xC8, 0xCC, 0xC5, 0x83, 0xCC, 0xDF, 0xE9, 0xDE, 0xE7, 0x80,
+0x0D, 0x89, 0x82, 0x8A, 0x83, 0xE4, 0x93, 0xA3, 0xF6, 0x08, 0xDF, 0xF9, 0xEC, 0xFA, 0xA9, 0xF0,
+0xED, 0xFB, 0x22, 0x89, 0x82, 0x8A, 0x83, 0xEC, 0xFA, 0xE0, 0xA3, 0xC8, 0xC5, 0x82, 0xC8, 0xCC,
+0xC5, 0x83, 0xCC, 0xF0, 0xA3, 0xC8, 0xC5, 0x82, 0xC8, 0xCC, 0xC5, 0x83, 0xCC, 0xDF, 0xEA, 0xDE,
+0xE8, 0x80, 0xDB, 0x89, 0x82, 0x8A, 0x83, 0xE4, 0x93, 0xA3, 0xF2, 0x08, 0xDF, 0xF9, 0x80, 0xCC,
+0x88, 0xF0, 0xEF, 0x60, 0x01, 0x0E, 0x4E, 0x60, 0xC3, 0x88, 0xF0, 0xED, 0x24, 0x02, 0xB4, 0x04,
+0x00, 0x50, 0xB9, 0xF5, 0x82, 0xEB, 0x24, 0x02, 0xB4, 0x04, 0x00, 0x50, 0xAF, 0x23, 0x23, 0x45,
+0x82, 0x23, 0x90, 0x42, 0x50, 0x73, 0xBB, 0x01, 0x09, 0x89, 0x82, 0x8A, 0x83, 0xF8, 0xE0, 0x28,
+0xF0, 0x22, 0x50, 0x03, 0x27, 0xF7, 0x22, 0xBB, 0xFE, 0x05, 0xF8, 0xE3, 0x28, 0xF3, 0x22, 0x8A,
+0x83, 0x89, 0x82, 0xF8, 0xE4, 0x93, 0x28, 0x22, 0xBB, 0x01, 0x0F, 0xF8, 0xE5, 0x82, 0x29, 0xF5,
+0x82, 0xE5, 0x83, 0x3A, 0xF5, 0x83, 0xE0, 0x28, 0xF0, 0x22, 0x50, 0x09, 0xC5, 0x82, 0x29, 0xF8,
+0xE5, 0x82, 0x26, 0xF6, 0x22, 0xBB, 0xFE, 0x09, 0xC5, 0x82, 0x29, 0xF8, 0xE2, 0x25, 0x82, 0xF2,
+0x22, 0xF8, 0xEA, 0x25, 0x83, 0xF5, 0x83, 0xE9, 0x93, 0x28, 0x22, 0xC5, 0xF0, 0xF8, 0xA3, 0xE0,
+0x28, 0xF0, 0xC5, 0xF0, 0xF8, 0xE5, 0x82, 0x15, 0x82, 0x70, 0x02, 0x15, 0x83, 0xE0, 0x38, 0xF0,
+0x22, 0xEF, 0x4B, 0xFF, 0xEE, 0x4A, 0xFE, 0xED, 0x49, 0xFD, 0xEC, 0x48, 0xFC, 0x22, 0xE0, 0xFC,
+0xA3, 0xE0, 0xFD, 0xA3, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0x22, 0xA4, 0x25, 0x82, 0xF5, 0x82, 0xE5,
+0xF0, 0x35, 0x83, 0xF5, 0x83, 0x22, 0xE0, 0xFB, 0xA3, 0xE0, 0xFA, 0xA3, 0xE0, 0xF9, 0x22, 0xEB,
+0xF0, 0xA3, 0xEA, 0xF0, 0xA3, 0xE9, 0xF0, 0x22, 0xBB, 0x01, 0x1A, 0x89, 0x82, 0x8A, 0x83, 0xD0,
+0xF0, 0xD0, 0xE0, 0xF8, 0xD0, 0xE0, 0xF9, 0xD0, 0xE0, 0xFA, 0xD0, 0xE0, 0xFB, 0xE8, 0xC0, 0xE0,
+0xC0, 0xF0, 0x02, 0x43, 0x8F, 0x50, 0x16, 0xE9, 0xF8, 0xD0, 0x83, 0xD0, 0x82, 0xD0, 0xE0, 0xF9,
+0xD0, 0xE0, 0xFA, 0xD0, 0xE0, 0xFB, 0xC0, 0x82, 0xC0, 0x83, 0x02, 0x46, 0x3C, 0xBB, 0xFE, 0x16,
+0xE9, 0xF8, 0xD0, 0x83, 0xD0, 0x82, 0xD0, 0xE0, 0xF9, 0xD0, 0xE0, 0xFA, 0xD0, 0xE0, 0xFB, 0xC0,
+0x82, 0xC0, 0x83, 0x02, 0x46, 0x45, 0x22, 0xBB, 0x01, 0x20, 0xE5, 0x82, 0x29, 0xF5, 0x82, 0xE5,
+0x83, 0x3A, 0xF5, 0x83, 0xD0, 0xF0, 0xD0, 0xE0, 0xF8, 0xD0, 0xE0, 0xF9, 0xD0, 0xE0, 0xFA, 0xD0,
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+0x7F, 0x01, 0x22, 0xED, 0xC3, 0x94, 0x06, 0x40, 0x69, 0x90, 0x83, 0x8A, 0x12, 0x43, 0x86, 0xE9,
+0x24, 0x02, 0xF9, 0xE4, 0x3A, 0xA8, 0x01, 0xFC, 0xAD, 0x03, 0x7B, 0x01, 0x7A, 0x83, 0x79, 0x4C,
+0x7E, 0x00, 0x7F, 0x04, 0x12, 0x45, 0xEC, 0xEF, 0x70, 0x48, 0x90, 0x83, 0x8A, 0x12, 0x43, 0x86,
+0x90, 0x00, 0x06, 0x12, 0x1F, 0xBD, 0x64, 0x01, 0x70, 0x38, 0x90, 0x00, 0x07, 0x12, 0x1F, 0xBD,
+0x70, 0x30, 0x90, 0x83, 0x8A, 0x12, 0x43, 0x86, 0xC0, 0x03, 0xC0, 0x02, 0xC0, 0x01, 0x90, 0x83,
+0x90, 0x12, 0x43, 0x86, 0x12, 0x43, 0x98, 0x90, 0x83, 0x8A, 0x12, 0x43, 0x86, 0x90, 0x00, 0x01,
+0x12, 0x1F, 0xBD, 0x24, 0x02, 0xFF, 0x90, 0x83, 0x90, 0x12, 0x43, 0x86, 0x90, 0x00, 0x03, 0x02,
+0x78, 0xB6, 0x90, 0x83, 0x8D, 0x12, 0x43, 0x86, 0xC0, 0x03, 0xC0, 0x02, 0xC0, 0x01, 0x90, 0x83,
+0x8A, 0x12, 0x43, 0x86, 0xE9, 0x24, 0x05, 0xF9, 0xE4, 0x3A, 0xFA, 0xC3, 0xD0, 0x82, 0xD0, 0x83,
+0xD0, 0xE0, 0xE9, 0x95, 0x82, 0xEA, 0x95, 0x83, 0x50, 0x53, 0x90, 0x83, 0x8A, 0x12, 0x43, 0x86,
+0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0xC3, 0x94, 0x14, 0x40, 0x42, 0x90, 0x83, 0x8A, 0x12, 0x43,
+0x86, 0xE9, 0x24, 0x02, 0xF9, 0xE4, 0x3A, 0xA8, 0x01, 0xFC, 0xAD, 0x03, 0x7B, 0x01, 0x7A, 0x83,
+0x79, 0x58, 0x7E, 0x00, 0x7F, 0x04, 0x12, 0x45, 0xEC, 0xEF, 0x70, 0x21, 0x90, 0x83, 0x8A, 0x12,
+0x43, 0x86, 0xE9, 0x24, 0x06, 0xF9, 0xE4, 0x3A, 0xFA, 0xC0, 0x03, 0xC0, 0x02, 0xC0, 0x01, 0x90,
+0x83, 0x90, 0x12, 0x43, 0x86, 0x90, 0x00, 0x08, 0x12, 0x43, 0xE7, 0x21, 0x2B, 0x90, 0x83, 0x8A,
+0x12, 0x43, 0x86, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0xD3, 0x94, 0x06, 0x40, 0x5E, 0x90, 0x83,
+0x8A, 0x12, 0x43, 0x86, 0xE9, 0x24, 0x02, 0xF9, 0xE4, 0x3A, 0xA8, 0x01, 0xFC, 0xAD, 0x03, 0x7B,
+0x01, 0x7A, 0x83, 0x79, 0x50, 0x7E, 0x00, 0x7F, 0x04, 0x12, 0x45, 0xEC, 0xEF, 0x70, 0x3D, 0x90,
+0x83, 0x8A, 0x12, 0x43, 0x86, 0xE9, 0x24, 0x06, 0xF9, 0xE4, 0x3A, 0xFA, 0xC0, 0x03, 0xC0, 0x02,
+0xC0, 0x01, 0x90, 0x83, 0x90, 0x12, 0x43, 0x86, 0x90, 0x00, 0x0B, 0x12, 0x43, 0xE7, 0x90, 0x83,
+0x8A, 0x12, 0x43, 0x86, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0x24, 0xFC, 0xFF, 0x90, 0x83, 0x90,
+0x12, 0x43, 0x86, 0x90, 0x00, 0x0E, 0xEF, 0x12, 0x1F, 0xFC, 0x80, 0x6F, 0x90, 0x83, 0x8A, 0x12,
+0x43, 0x86, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0xD3, 0x94, 0x06, 0x40, 0x5E, 0x90, 0x83, 0x8A,
+0x12, 0x43, 0x86, 0xE9, 0x24, 0x02, 0xF9, 0xE4, 0x3A, 0xA8, 0x01, 0xFC, 0xAD, 0x03, 0x7B, 0x01,
+0x7A, 0x83, 0x79, 0x54, 0x7E, 0x00, 0x7F, 0x04, 0x12, 0x45, 0xEC, 0xEF, 0x70, 0x3D, 0x90, 0x83,
+0x8A, 0x12, 0x43, 0x86, 0xE9, 0x24, 0x06, 0xF9, 0xE4, 0x3A, 0xFA, 0xC0, 0x03, 0xC0, 0x02, 0xC0,
+0x01, 0x90, 0x83, 0x90, 0x12, 0x43, 0x86, 0x90, 0x00, 0x0F, 0x12, 0x43, 0xE7, 0x90, 0x83, 0x8A,
+0x12, 0x43, 0x86, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0x24, 0xFC, 0xFF, 0x90, 0x83, 0x90, 0x12,
+0x43, 0x86, 0x90, 0x00, 0x12, 0xEF, 0x12, 0x1F, 0xFC, 0x80, 0x00, 0xE4, 0xFE, 0xFF, 0x22, 0x90,
+0x83, 0x3D, 0x12, 0x20, 0xCE, 0x90, 0x83, 0x3A, 0x12, 0x43, 0x8F, 0xE4, 0x90, 0x83, 0x4A, 0xF0,
+0xA3, 0xF0, 0x90, 0x83, 0x44, 0x12, 0x43, 0x8F, 0x90, 0x83, 0x3D, 0x12, 0x43, 0x6E, 0xE9, 0x2F,
+0xF9, 0xEA, 0x3E, 0xFA, 0xEB, 0x3D, 0xFB, 0x90, 0x83, 0x47, 0x12, 0x43, 0x8F, 0x90, 0x83, 0x47,
+0x12, 0x43, 0x86, 0xC0, 0x03, 0xC0, 0x02, 0xC0, 0x01, 0x90, 0x83, 0x44, 0x12, 0x43, 0x86, 0xE9,
+0x24, 0x01, 0xF9, 0xE4, 0x3A, 0xFA, 0xC3, 0xD0, 0x82, 0xD0, 0x83, 0xD0, 0xE0, 0xE9, 0x95, 0x82,
+0xEA, 0x95, 0x83, 0x40, 0x02, 0x41, 0xA7, 0x90, 0x83, 0x44, 0x12, 0x43, 0x86, 0x12, 0x1F, 0xA4,
+0xB4, 0xDD, 0x4E, 0x90, 0x83, 0x3D, 0x12, 0x43, 0x6E, 0x90, 0x83, 0x3A, 0x12, 0x43, 0x86, 0xE9,
+0x2F, 0xF9, 0xEA, 0x3E, 0xFA, 0xEB, 0x3D, 0xFB, 0xE9, 0x24, 0xFF, 0xF9, 0xEA, 0x34, 0xFF, 0xFA,
+0xC0, 0x03, 0xC0, 0x02, 0xC0, 0x01, 0x90, 0x83, 0x44, 0x12, 0x43, 0x86, 0xD0, 0x82, 0xD0, 0x83,
+0xD0, 0xE0, 0x6B, 0x70, 0x08, 0xE9, 0x65, 0x82, 0x70, 0x03, 0xEA, 0x65, 0x83, 0x70, 0x02, 0x41,
+0xA7, 0x90, 0x83, 0x44, 0x12, 0x43, 0x86, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0x70, 0x02, 0x41,
+0xA7, 0x90, 0x83, 0x47, 0x12, 0x43, 0x86, 0xC0, 0x03, 0xC0, 0x02, 0xC0, 0x01, 0x90, 0x83, 0x44,
+0x12, 0x43, 0x86, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0xFF, 0x7E, 0x00, 0xE9, 0x24, 0x02, 0xF9,
+0xE4, 0x3A, 0xFA, 0xE9, 0x2F, 0xF9, 0xEE, 0x3A, 0xFA, 0xD3, 0xD0, 0x82, 0xD0, 0x83, 0xD0, 0xE0,
+0xE9, 0x95, 0x82, 0xEA, 0x95, 0x83, 0x40, 0x02, 0x41, 0xA7, 0x90, 0x83, 0x44, 0x12, 0x43, 0x86,
+0x12, 0x1F, 0xA4, 0xFF, 0xB4, 0x30, 0x36, 0x90, 0x83, 0x44, 0x12, 0x43, 0x86, 0xC0, 0x03, 0xC0,
+0x02, 0xC0, 0x01, 0x90, 0x83, 0x41, 0x12, 0x43, 0x86, 0x90, 0x00, 0x04, 0x12, 0x43, 0xE7, 0x90,
+0x83, 0x44, 0x12, 0x43, 0x86, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0x24, 0x02, 0xFE, 0x90, 0x83,
+0x41, 0x12, 0x43, 0x86, 0x90, 0x00, 0x07, 0xEE, 0x12, 0x1F, 0xFC, 0x80, 0x2F, 0xEF, 0xB4, 0xDD,
+0x2B, 0x90, 0x83, 0x47, 0x12, 0x43, 0x86, 0x90, 0x83, 0x8D, 0x12, 0x43, 0x8F, 0x90, 0x83, 0x41,
+0x12, 0x43, 0x86, 0x90, 0x83, 0x90, 0x12, 0x43, 0x8F, 0x90, 0x83, 0x44, 0x12, 0x43, 0x86, 0x12,
+0x77, 0x50, 0x90, 0x83, 0x4A, 0xEE, 0xF0, 0xA3, 0xEF, 0xF0, 0x80, 0x1B, 0x90, 0x83, 0x44, 0x12,
+0x43, 0x86, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0x24, 0x02, 0xFF, 0xE4, 0x33, 0x90, 0x83, 0x45,
+0x8F, 0xF0, 0x12, 0x43, 0x4B, 0x21, 0x5D, 0x90, 0x83, 0x4A, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0x22,
+0x90, 0x82, 0xEE, 0x12, 0x43, 0x8F, 0x90, 0x82, 0xF4, 0xE0, 0x60, 0x02, 0x61, 0x84, 0x90, 0x82,
+0xF1, 0x12, 0x43, 0x86, 0x12, 0x1F, 0xA4, 0xF4, 0x60, 0x02, 0x61, 0x79, 0x12, 0x1F, 0xEA, 0x90,
+0x82, 0xF1, 0x12, 0x43, 0x86, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0xF4, 0x60, 0x02, 0x61, 0x69,
+0x90, 0x00, 0x01, 0x12, 0x1F, 0xFC, 0x90, 0x00, 0x02, 0x12, 0x1F, 0xBD, 0xF4, 0x70, 0x6F, 0x90,
+0x82, 0xF1, 0x12, 0x43, 0x86, 0x90, 0x00, 0x02, 0xE4, 0x12, 0x1F, 0xFC, 0x90, 0x00, 0x03, 0x12,
+0x1F, 0xBD, 0xF4, 0x70, 0x4E, 0x90, 0x82, 0xF1, 0x12, 0x43, 0x86, 0x90, 0x00, 0x03, 0xE4, 0x12,
+0x1F, 0xFC, 0x90, 0x00, 0x04, 0x12, 0x1F, 0xBD, 0xF4, 0x70, 0x2D, 0x90, 0x82, 0xF1, 0x12, 0x43,
+0x86, 0x90, 0x00, 0x04, 0xE4, 0x12, 0x1F, 0xFC, 0x90, 0x00, 0x05, 0x12, 0x1F, 0xBD, 0x90, 0x82,
+0xF1, 0xB4, 0xFF, 0x0C, 0x12, 0x43, 0x86, 0x90, 0x00, 0x05, 0xE4, 0x12, 0x1F, 0xFC, 0x80, 0x44,
+0x12, 0x43, 0x86, 0x90, 0x00, 0x05, 0x80, 0x2A, 0x90, 0x82, 0xF1, 0x12, 0x43, 0x86, 0x90, 0x00,
+0x04, 0x80, 0x1F, 0x90, 0x82, 0xF1, 0x12, 0x43, 0x86, 0x90, 0x00, 0x03, 0x80, 0x14, 0x90, 0x82,
+0xF1, 0x12, 0x43, 0x86, 0x90, 0x00, 0x02, 0x80, 0x09, 0x90, 0x82, 0xF1, 0x12, 0x43, 0x86, 0x90,
+0x00, 0x01, 0x74, 0x01, 0x12, 0x43, 0x18, 0x80, 0x0B, 0x90, 0x82, 0xF1, 0x12, 0x43, 0x86, 0x74,
+0x01, 0x12, 0x42, 0xF6, 0x90, 0x82, 0xF5, 0xE0, 0xFF, 0x64, 0x04, 0x60, 0x02, 0x81, 0x33, 0x90,
+0x82, 0xF1, 0x12, 0x43, 0x86, 0x12, 0x1F, 0xA4, 0xFE, 0x90, 0x82, 0xEE, 0x12, 0x43, 0x86, 0xEE,
+0x12, 0x1F, 0xEA, 0x90, 0x82, 0xF1, 0x12, 0x43, 0x86, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0xFE,
+0x90, 0x82, 0xEE, 0x12, 0x43, 0x86, 0x90, 0x00, 0x01, 0xEE, 0x12, 0x1F, 0xFC, 0x90, 0x00, 0x02,
+0xE4, 0x12, 0x1F, 0xFC, 0x90, 0x00, 0x03, 0x74, 0x20, 0x12, 0x1F, 0xFC, 0x90, 0x82, 0xF1, 0x12,
+0x43, 0x86, 0x90, 0x00, 0x02, 0x12, 0x1F, 0xBD, 0xFE, 0x90, 0x82, 0xEE, 0x12, 0x43, 0x86, 0x90,
+0x00, 0x04, 0xEE, 0x12, 0x1F, 0xFC, 0x90, 0x82, 0xF1, 0x12, 0x43, 0x86, 0x90, 0x00, 0x03, 0x12,
+0x1F, 0xBD, 0xFE, 0x90, 0x82, 0xEE, 0x12, 0x43, 0x86, 0x90, 0x00, 0x05, 0xEE, 0x12, 0x1F, 0xFC,
+0x90, 0x82, 0xF1, 0x12, 0x43, 0x86, 0x90, 0x00, 0x04, 0x12, 0x1F, 0xBD, 0xFE, 0x90, 0x82, 0xEE,
+0x12, 0x43, 0x86, 0x90, 0x00, 0x06, 0xEE, 0x12, 0x1F, 0xFC, 0x90, 0x82, 0xF1, 0x12, 0x43, 0x86,
+0x90, 0x00, 0x05, 0x12, 0x1F, 0xBD, 0xFE, 0x90, 0x82, 0xEE, 0x12, 0x43, 0x86, 0x90, 0x00, 0x07,
+0xEE, 0x81, 0xF3, 0xEF, 0x64, 0x02, 0x60, 0x02, 0x81, 0xF6, 0x90, 0x82, 0xF1, 0x12, 0x43, 0x86,
+0x12, 0x1F, 0xA4, 0xFF, 0x90, 0x82, 0xEE, 0x12, 0x43, 0x86, 0xEF, 0x12, 0x1F, 0xEA, 0x90, 0x82,
+0xF1, 0x12, 0x43, 0x86, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0x44, 0x20, 0x54, 0x7F, 0xFF, 0x90,
+0x82, 0xEE, 0x12, 0x43, 0x86, 0x90, 0x00, 0x01, 0xEF, 0x12, 0x1F, 0xFC, 0x90, 0x82, 0xF1, 0x12,
+0x43, 0x86, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0xFF, 0x90, 0x82, 0xEE, 0x12, 0x43, 0x86, 0x90,
+0x00, 0x02, 0xEF, 0x12, 0x1F, 0xFC, 0x90, 0x00, 0x03, 0x74, 0x20, 0x12, 0x1F, 0xFC, 0x90, 0x82,
+0xF1, 0x12, 0x43, 0x86, 0x90, 0x00, 0x02, 0x12, 0x1F, 0xBD, 0xFF, 0x90, 0x82, 0xEE, 0x12, 0x43,
+0x86, 0x90, 0x00, 0x04, 0xEF, 0x12, 0x1F, 0xFC, 0x90, 0x82, 0xF1, 0x12, 0x43, 0x86, 0x90, 0x00,
+0x03, 0x12, 0x1F, 0xBD, 0xFF, 0x90, 0x82, 0xEE, 0x12, 0x43, 0x86, 0x90, 0x00, 0x05, 0xEF, 0x12,
+0x1F, 0xFC, 0x90, 0x82, 0xF1, 0x12, 0x43, 0x86, 0x90, 0x00, 0x04, 0x12, 0x1F, 0xBD, 0xFF, 0x90,
+0x82, 0xEE, 0x12, 0x43, 0x86, 0x90, 0x00, 0x06, 0xEF, 0x12, 0x1F, 0xFC, 0x90, 0x82, 0xF1, 0x12,
+0x43, 0x86, 0x90, 0x00, 0x05, 0x12, 0x1F, 0xBD, 0xFF, 0x90, 0x82, 0xEE, 0x12, 0x43, 0x86, 0x90,
+0x00, 0x07, 0xEF, 0x12, 0x1F, 0xFC, 0x22, 0x90, 0x82, 0xF1, 0xED, 0xF0, 0x90, 0x82, 0xEE, 0x12,
+0x43, 0x8F, 0x90, 0x00, 0x03, 0x12, 0x1F, 0xBD, 0x90, 0x82, 0xF5, 0xF0, 0x90, 0x82, 0xEE, 0x12,
+0x43, 0x86, 0x8B, 0x13, 0x8A, 0x14, 0x89, 0x15, 0x75, 0x16, 0x03, 0x7B, 0x01, 0x7A, 0x82, 0x79,
+0xF2, 0x12, 0x2B, 0xED, 0x90, 0x82, 0xF1, 0xE0, 0x70, 0x46, 0xFF, 0x74, 0xF2, 0x2F, 0xF5, 0x82,
+0xE4, 0x34, 0x82, 0xF5, 0x83, 0xE0, 0xB4, 0xFF, 0x0E, 0x74, 0xF2, 0x2F, 0xF5, 0x82, 0xE4, 0x34,
+0x82, 0xF5, 0x83, 0xE4, 0xF0, 0x80, 0x0F, 0x74, 0xF2, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x82, 0xF5,
+0x83, 0xE0, 0x04, 0xF0, 0x80, 0x05, 0x0F, 0xEF, 0xB4, 0x03, 0xD0, 0x75, 0x13, 0x01, 0x75, 0x14,
+0x82, 0x75, 0x15, 0xF2, 0x75, 0x16, 0x03, 0x90, 0x82, 0xEE, 0x12, 0x43, 0x86, 0x12, 0x2B, 0xED,
+0x22, 0x00, 0x39, 0xD4,
+};
+#if 0
+u4Byte ArrayLength_8188E_FW_WoWLAN = 15764;
+
+
+void
+ODM_ReadFirmware_8188E_FW_WoWLAN(
+ IN PDM_ODM_T pDM_Odm,
+ OUT u1Byte *pFirmware,
+ OUT u4Byte *pFirmwareSize
+)
+{
+ ODM_MoveMemory(pDM_Odm, pFirmware, Array_8188E_FW_WoWLAN, ArrayLength_8188E_FW_WoWLAN);
+ *pFirmwareSize = ArrayLength_8188E_FW_WoWLAN;
+}
+
+#endif
+
+#endif // end of DM_ODM_SUPPORT_TYPE & (ODM_AP)
+
+
+#endif // end of HWIMG_SUPPORT
+
diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_FW.h b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_FW.h new file mode 100755 index 00000000..43f6ac07 --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_FW.h @@ -0,0 +1,65 @@ +/******************************************************************************
+*
+* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms of version 2 of the GNU General Public License as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful, but WITHOUT
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+* more details.
+*
+* You should have received a copy of the GNU General Public License along with
+* this program; if not, write to the Free Software Foundation, Inc.,
+* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+*
+*
+******************************************************************************/
+
+#if (RTL8188E_SUPPORT == 1)
+#ifndef __INC_FW_8188E_HW_IMG_H
+#define __INC_FW_8188E_HW_IMG_H
+
+
+/******************************************************************************
+* FW_AP.TXT
+******************************************************************************/
+#if(DM_ODM_SUPPORT_TYPE & (ODM_AP))
+void
+ODM_ReadFirmware_8188E_FW_AP(
+ IN PDM_ODM_T pDM_Odm,
+ OUT u1Byte *pFirmware,
+ OUT u4Byte *pFirmwareSize
+);
+
+#else
+/******************************************************************************
+* FW_NIC.TXT
+******************************************************************************/
+#if 0
+void
+ODM_ReadFirmware_8188E_FW_NIC(
+ IN PDM_ODM_T pDM_Odm,
+ OUT u1Byte *pFirmware,
+ OUT u4Byte *pFirmwareSize
+);
+#endif
+/******************************************************************************
+* FW_WoWLAN.TXT
+******************************************************************************/
+#if 0
+void
+ODM_ReadFirmware_8188E_FW_WoWLAN(
+ IN PDM_ODM_T pDM_Odm,
+ OUT u1Byte *pFirmware,
+ OUT u4Byte *pFirmwareSize
+);
+#endif
+#define ArrayLength_8188E_FW_WoWLAN 15764
+extern const u8 Array_8188E_FW_WoWLAN[ArrayLength_8188E_FW_WoWLAN];
+#endif
+
+#endif
+#endif // end of HWIMG_SUPPORT
diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_MAC.c b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_MAC.c new file mode 100755 index 00000000..ff800f98 --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_MAC.c @@ -0,0 +1,329 @@ +/******************************************************************************
+*
+* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms of version 2 of the GNU General Public License as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful, but WITHOUT
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+* more details.
+*
+* You should have received a copy of the GNU General Public License along with
+* this program; if not, write to the Free Software Foundation, Inc.,
+* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+*
+*
+******************************************************************************/
+
+#include "../odm_precomp.h"
+#ifdef CONFIG_IOL_IOREG_CFG
+#include <rtw_iol.h>
+#endif
+#if (RTL8188E_SUPPORT == 1)
+static BOOLEAN
+CheckCondition(
+ const u4Byte Condition,
+ const u4Byte Hex
+ )
+{
+ u4Byte _board = (Hex & 0x000000FF);
+ u4Byte _interface = (Hex & 0x0000FF00) >> 8;
+ u4Byte _platform = (Hex & 0x00FF0000) >> 16;
+ u4Byte cond = Condition;
+
+ if ( Condition == 0xCDCDCDCD )
+ return TRUE;
+
+ cond = Condition & 0x000000FF;
+ if ( (_board == cond) && cond != 0x00)
+ return FALSE;
+
+ cond = Condition & 0x0000FF00;
+ cond = cond >> 8;
+ if ( (_interface & cond) == 0 && cond != 0x07)
+ return FALSE;
+
+ cond = Condition & 0x00FF0000;
+ cond = cond >> 16;
+ if ( (_platform & cond) == 0 && cond != 0x0F)
+ return FALSE;
+ return TRUE;
+}
+
+
+/******************************************************************************
+* MAC_REG.TXT
+******************************************************************************/
+
+u4Byte Array_MAC_REG_8188E[] = {
+ 0x026, 0x00000041,
+ 0x027, 0x00000035,
+ 0x428, 0x0000000A,
+ 0x429, 0x00000010,
+ 0x430, 0x00000000,
+ 0x431, 0x00000001,
+ 0x432, 0x00000002,
+ 0x433, 0x00000004,
+ 0x434, 0x00000005,
+ 0x435, 0x00000006,
+ 0x436, 0x00000007,
+ 0x437, 0x00000008,
+ 0x438, 0x00000000,
+ 0x439, 0x00000000,
+ 0x43A, 0x00000001,
+ 0x43B, 0x00000002,
+ 0x43C, 0x00000004,
+ 0x43D, 0x00000005,
+ 0x43E, 0x00000006,
+ 0x43F, 0x00000007,
+ 0x440, 0x0000005D,
+ 0x441, 0x00000001,
+ 0x442, 0x00000000,
+ 0x444, 0x00000015,
+ 0x445, 0x000000F0,
+ 0x446, 0x0000000F,
+ 0x447, 0x00000000,
+ 0x458, 0x00000041,
+ 0x459, 0x000000A8,
+ 0x45A, 0x00000072,
+ 0x45B, 0x000000B9,
+ 0x460, 0x00000066,
+ 0x461, 0x00000066,
+ 0x480, 0x00000008,
+ 0x4C8, 0x000000FF,
+ 0x4C9, 0x00000008,
+ 0x4CC, 0x000000FF,
+ 0x4CD, 0x000000FF,
+ 0x4CE, 0x00000001,
+ 0x4D3, 0x00000001,
+ 0x500, 0x00000026,
+ 0x501, 0x000000A2,
+ 0x502, 0x0000002F,
+ 0x503, 0x00000000,
+ 0x504, 0x00000028,
+ 0x505, 0x000000A3,
+ 0x506, 0x0000005E,
+ 0x507, 0x00000000,
+ 0x508, 0x0000002B,
+ 0x509, 0x000000A4,
+ 0x50A, 0x0000005E,
+ 0x50B, 0x00000000,
+ 0x50C, 0x0000004F,
+ 0x50D, 0x000000A4,
+ 0x50E, 0x00000000,
+ 0x50F, 0x00000000,
+ 0x512, 0x0000001C,
+ 0x514, 0x0000000A,
+ 0x516, 0x0000000A,
+ 0x525, 0x0000004F,
+ 0x550, 0x00000010,
+ 0x551, 0x00000010,
+ 0x559, 0x00000002,
+ 0x55D, 0x000000FF,
+ 0x605, 0x00000030,
+ 0x608, 0x0000000E,
+ 0x609, 0x0000002A,
+ 0x620, 0x000000FF,
+ 0x621, 0x000000FF,
+ 0x622, 0x000000FF,
+ 0x623, 0x000000FF,
+ 0x624, 0x000000FF,
+ 0x625, 0x000000FF,
+ 0x626, 0x000000FF,
+ 0x627, 0x000000FF,
+ 0x652, 0x00000020,
+ 0x63C, 0x0000000A,
+ 0x63D, 0x0000000A,
+ 0x63E, 0x0000000E,
+ 0x63F, 0x0000000E,
+ 0x640, 0x00000040,
+ 0x66E, 0x00000005,
+ 0x700, 0x00000021,
+ 0x701, 0x00000043,
+ 0x702, 0x00000065,
+ 0x703, 0x00000087,
+ 0x708, 0x00000021,
+ 0x709, 0x00000043,
+ 0x70A, 0x00000065,
+ 0x70B, 0x00000087,
+};
+
+HAL_STATUS
+ODM_ReadAndConfig_MAC_REG_8188E(
+ IN PDM_ODM_T pDM_Odm
+ )
+{
+ #define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0)
+
+ u4Byte hex = 0;
+ u4Byte i = 0;
+ u2Byte count = 0;
+ pu4Byte ptr_array = NULL;
+ u1Byte platform = pDM_Odm->SupportPlatform;
+ u1Byte interfaceValue = pDM_Odm->SupportInterface;
+ u1Byte board = pDM_Odm->BoardType;
+ u4Byte ArrayLen = sizeof(Array_MAC_REG_8188E)/sizeof(u4Byte);
+ pu4Byte Array = Array_MAC_REG_8188E;
+ BOOLEAN biol = FALSE;
+
+#ifdef CONFIG_IOL_IOREG_CFG
+ PADAPTER Adapter = pDM_Odm->Adapter;
+ struct xmit_frame *pxmit_frame;
+ u8 bndy_cnt = 1;
+ #ifdef CONFIG_IOL_IOREG_CFG_DBG
+ struct cmd_cmp cmpdata[ArrayLen];
+ u4Byte cmpdata_idx=0;
+ #endif
+#endif //CONFIG_IOL_IOREG_CFG
+ HAL_STATUS rst =HAL_STATUS_SUCCESS;
+ hex += board;
+ hex += interfaceValue << 8;
+ hex += platform << 16;
+ hex += 0xFF000000;
+
+#ifdef CONFIG_IOL_IOREG_CFG
+ biol = rtw_IOL_applied(Adapter);
+
+ if(biol){
+ if((pxmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL)
+ {
+ printk("rtw_IOL_accquire_xmit_frame failed\n");
+ return HAL_STATUS_FAILURE;
+ }
+ }
+
+#endif //CONFIG_IOL_IOREG_CFG
+
+ for (i = 0; i < ArrayLen; i += 2 )
+ {
+ u4Byte v1 = Array[i];
+ u4Byte v2 = Array[i+1];
+
+ // This (offset, data) pair meets the condition.
+ if ( v1 < 0xCDCDCDCD )
+ {
+ #ifdef CONFIG_IOL_IOREG_CFG
+
+ if(biol){
+
+ if(rtw_IOL_cmd_boundary_handle(pxmit_frame))
+ bndy_cnt++;
+ rtw_IOL_append_WB_cmd(pxmit_frame,(u2Byte)v1, (u1Byte)v2,0xFF);
+ #ifdef CONFIG_IOL_IOREG_CFG_DBG
+ cmpdata[cmpdata_idx].addr = v1;
+ cmpdata[cmpdata_idx].value= v2;
+ cmpdata_idx++;
+ #endif
+ }
+ else
+ #endif //endif CONFIG_IOL_IOREG_CFG
+ {
+ odm_ConfigMAC_8188E(pDM_Odm, v1, (u1Byte)v2);
+ }
+ continue;
+ }
+ else
+ { // This line is the start line of branch.
+ if ( !CheckCondition(Array[i], hex) )
+ { // Discard the following (offset, data) pairs.
+ READ_NEXT_PAIR(v1, v2, i);
+ while ( v2 != 0xDEAD &&
+ v2 != 0xCDEF &&
+ v2 != 0xCDCD && i < ArrayLen -2)
+ {
+ READ_NEXT_PAIR(v1, v2, i);
+ }
+ i -= 2; // prevent from for-loop += 2
+ }
+ else // Configure matched pairs and skip to end of if-else.
+ {
+ READ_NEXT_PAIR(v1, v2, i);
+ while ( v2 != 0xDEAD &&
+ v2 != 0xCDEF &&
+ v2 != 0xCDCD && i < ArrayLen -2)
+ {
+ #ifdef CONFIG_IOL_IOREG_CFG
+ if(biol){
+ if(rtw_IOL_cmd_boundary_handle(pxmit_frame))
+ bndy_cnt++;
+ rtw_IOL_append_WB_cmd(pxmit_frame,(u2Byte)v1, (u1Byte)v2,0xFF);
+ #ifdef CONFIG_IOL_IOREG_CFG_DBG
+ cmpdata[cmpdata_idx].addr = v1;
+ cmpdata[cmpdata_idx].value= v2;
+ cmpdata_idx++;
+ #endif
+ }
+ else
+ #endif //#ifdef CONFIG_IOL_IOREG_CFG
+ {
+ odm_ConfigMAC_8188E(pDM_Odm, v1, (u1Byte)v2);
+ }
+
+ READ_NEXT_PAIR(v1, v2, i);
+ }
+
+ while (v2 != 0xDEAD && i < ArrayLen -2)
+ {
+ READ_NEXT_PAIR(v1, v2, i);
+ }
+
+ }
+ }
+ }
+
+#ifdef CONFIG_IOL_IOREG_CFG
+ if(biol){
+ //printk("==> %s, pktlen = %d,bndy_cnt = %d\n",__FUNCTION__,pxmit_frame->attrib.pktlen+4+32,bndy_cnt);
+
+ if(rtw_IOL_exec_cmds_sync(pDM_Odm->Adapter, pxmit_frame, 1000, bndy_cnt))
+ {
+ #ifdef CONFIG_IOL_IOREG_CFG_DBG
+ printk("~~~ IOL Config MAC Success !!! \n");
+ //compare writed data
+ {
+ u4Byte idx;
+ u1Byte cdata;
+ // HAL_STATUS_FAILURE;
+ printk(" MAC data compare => array_len:%d \n",cmpdata_idx);
+ for(idx=0;idx< cmpdata_idx;idx++)
+ {
+ cdata = ODM_Read1Byte(pDM_Odm, cmpdata[idx].addr);
+ if(cdata != cmpdata[idx].value){
+ printk("### MAC data compared failed !! addr:0x%04x, data:(0x%02x : 0x%02x) ###\n",
+ cmpdata[idx].addr,cmpdata[idx].value,cdata);
+ //rst = HAL_STATUS_FAILURE;
+ }
+ }
+
+
+ //dump data from TX packet buffer
+ //if(rst == HAL_STATUS_FAILURE)
+ {
+ rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32);
+ }
+
+ }
+ #endif //CONFIG_IOL_IOREG_CFG_DBG
+
+ }
+ else{
+ printk("~~~ MAC IOL_exec_cmds Failed !!! \n");
+ #ifdef CONFIG_IOL_IOREG_CFG_DBG
+ {
+ //dump data from TX packet buffer
+ rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32);
+ }
+ #endif //CONFIG_IOL_IOREG_CFG_DBG
+ rst = HAL_STATUS_FAILURE;
+ }
+
+ }
+#endif //#ifdef CONFIG_IOL_IOREG_CFG
+ return rst;
+}
+
+#endif // end of HWIMG_SUPPORT
+
diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_MAC.h b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_MAC.h new file mode 100755 index 00000000..e6f9cf7c --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_MAC.h @@ -0,0 +1,38 @@ +/******************************************************************************
+*
+* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms of version 2 of the GNU General Public License as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful, but WITHOUT
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+* more details.
+*
+* You should have received a copy of the GNU General Public License along with
+* this program; if not, write to the Free Software Foundation, Inc.,
+* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+*
+*
+******************************************************************************/
+
+#if (RTL8188E_SUPPORT == 1)
+#ifndef __INC_MAC_8188E_HW_IMG_H
+#define __INC_MAC_8188E_HW_IMG_H
+
+//static BOOLEAN CheckCondition(const u4Byte Condition, const u4Byte Hex);
+
+/******************************************************************************
+* MAC_REG.TXT
+******************************************************************************/
+
+HAL_STATUS
+ODM_ReadAndConfig_MAC_REG_8188E(
+ IN PDM_ODM_T pDM_Odm
+);
+
+#endif
+#endif // end of HWIMG_SUPPORT
+
diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_RF.c b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_RF.c new file mode 100755 index 00000000..fbe04d9f --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_RF.c @@ -0,0 +1,377 @@ +/******************************************************************************
+*
+* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms of version 2 of the GNU General Public License as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful, but WITHOUT
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+* more details.
+*
+* You should have received a copy of the GNU General Public License along with
+* this program; if not, write to the Free Software Foundation, Inc.,
+* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+*
+*
+******************************************************************************/
+
+#include "../odm_precomp.h"
+
+#ifdef CONFIG_IOL_IOREG_CFG
+#include <rtw_iol.h>
+#endif
+
+#if (RTL8188E_SUPPORT == 1)
+static BOOLEAN
+CheckCondition(
+ const u4Byte Condition,
+ const u4Byte Hex
+ )
+{
+ u4Byte _board = (Hex & 0x000000FF);
+ u4Byte _interface = (Hex & 0x0000FF00) >> 8;
+ u4Byte _platform = (Hex & 0x00FF0000) >> 16;
+ u4Byte cond = Condition;
+
+ if ( Condition == 0xCDCDCDCD )
+ return TRUE;
+
+ cond = Condition & 0x000000FF;
+ if ( (_board == cond) && cond != 0x00)
+ return FALSE;
+
+ cond = Condition & 0x0000FF00;
+ cond = cond >> 8;
+ if ( (_interface & cond) == 0 && cond != 0x07)
+ return FALSE;
+
+ cond = Condition & 0x00FF0000;
+ cond = cond >> 16;
+ if ( (_platform & cond) == 0 && cond != 0x0F)
+ return FALSE;
+ return TRUE;
+}
+
+
+/******************************************************************************
+* RadioA_1T.TXT
+******************************************************************************/
+
+u4Byte Array_RadioA_1T_8188E[] = {
+ 0x000, 0x00030000,
+ 0x008, 0x00084000,
+ 0x018, 0x00000407,
+ 0x019, 0x00000012,
+ 0x01E, 0x00080009,
+ 0x01F, 0x00000880,
+ 0x02F, 0x0001A060,
+ 0x03F, 0x00000000,
+ 0x042, 0x000060C0,
+ 0x057, 0x000D0000,
+ 0x058, 0x000BE180,
+ 0x067, 0x00001552,
+ 0x083, 0x00000000,
+ 0x0B0, 0x000FF8FC,
+ 0x0B1, 0x00054400,
+ 0x0B2, 0x000CCC19,
+ 0x0B4, 0x00043003,
+ 0x0B6, 0x0004953E,
+ 0x0B7, 0x0001C718,
+ 0x0B8, 0x000060FF,
+ 0x0B9, 0x00080001,
+ 0x0BA, 0x00040000,
+ 0x0BB, 0x00000400,
+ 0x0BF, 0x000C0000,
+ 0x0C2, 0x00002400,
+ 0x0C3, 0x00000009,
+ 0x0C4, 0x00040C91,
+ 0x0C5, 0x00099999,
+ 0x0C6, 0x000000A3,
+ 0x0C7, 0x00088820,
+ 0x0C8, 0x00076C06,
+ 0x0C9, 0x00000000,
+ 0x0CA, 0x00080000,
+ 0x0DF, 0x00000180,
+ 0x0EF, 0x000001A0,
+ 0x051, 0x0006B27D,
+ 0xFF0F041F, 0xABCD,
+ 0x052, 0x0007E4DD,
+ 0xCDCDCDCD, 0xCDCD,
+ 0x052, 0x0007E49D,
+ 0xFF0F041F, 0xDEAD,
+ 0x053, 0x00000073,
+ 0x056, 0x00051FF3,
+ 0x035, 0x00000086,
+ 0x035, 0x00000186,
+ 0x035, 0x00000286,
+ 0x036, 0x00001C25,
+ 0x036, 0x00009C25,
+ 0x036, 0x00011C25,
+ 0x036, 0x00019C25,
+ 0x0B6, 0x00048538,
+ 0x018, 0x00000C07,
+ 0x05A, 0x0004BD00,
+ 0x019, 0x000739D0,
+ 0x034, 0x0000ADF3,
+ 0x034, 0x00009DF0,
+ 0x034, 0x00008DED,
+ 0x034, 0x00007DEA,
+ 0x034, 0x00006DE7,
+ 0x034, 0x000054EE,
+ 0x034, 0x000044EB,
+ 0x034, 0x000034E8,
+ 0x034, 0x0000246B,
+ 0x034, 0x00001468,
+ 0x034, 0x0000006D,
+ 0x000, 0x00030159,
+ 0x084, 0x00068200,
+ 0x086, 0x000000CE,
+ 0x087, 0x00048A00,
+ 0x08E, 0x00065540,
+ 0x08F, 0x00088000,
+ 0x0EF, 0x000020A0,
+ 0x03B, 0x000F02B0,
+ 0x03B, 0x000EF7B0,
+ 0x03B, 0x000D4FB0,
+ 0x03B, 0x000CF060,
+ 0x03B, 0x000B0090,
+ 0x03B, 0x000A0080,
+ 0x03B, 0x00090080,
+ 0x03B, 0x0008F780,
+ 0x03B, 0x000722B0,
+ 0x03B, 0x0006F7B0,
+ 0x03B, 0x00054FB0,
+ 0x03B, 0x0004F060,
+ 0x03B, 0x00030090,
+ 0x03B, 0x00020080,
+ 0x03B, 0x00010080,
+ 0x03B, 0x0000F780,
+ 0x0EF, 0x000000A0,
+ 0x000, 0x00010159,
+ 0x018, 0x0000F407,
+ 0xFFE, 0x00000000,
+ 0xFFE, 0x00000000,
+ 0x01F, 0x00080003,
+ 0xFFE, 0x00000000,
+ 0xFFE, 0x00000000,
+ 0x01E, 0x00000001,
+ 0x01F, 0x00080000,
+ 0x000, 0x00033E60,
+};
+
+HAL_STATUS
+ODM_ReadAndConfig_RadioA_1T_8188E(
+ IN PDM_ODM_T pDM_Odm
+ )
+{
+ #define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0)
+
+ u4Byte hex = 0;
+ u4Byte i = 0;
+ u2Byte count = 0;
+ pu4Byte ptr_array = NULL;
+ u1Byte platform = pDM_Odm->SupportPlatform;
+ u1Byte interfaceValue = pDM_Odm->SupportInterface;
+ u1Byte board = pDM_Odm->BoardType;
+ u4Byte ArrayLen = sizeof(Array_RadioA_1T_8188E)/sizeof(u4Byte);
+ pu4Byte Array = Array_RadioA_1T_8188E;
+ BOOLEAN biol = FALSE;
+#ifdef CONFIG_IOL_IOREG_CFG
+ PADAPTER Adapter = pDM_Odm->Adapter;
+ struct xmit_frame *pxmit_frame;
+ u8 bndy_cnt = 1;
+ #ifdef CONFIG_IOL_IOREG_CFG_DBG
+ struct cmd_cmp cmpdata[ArrayLen];
+ u4Byte cmpdata_idx=0;
+ #endif
+#endif//#ifdef CONFIG_IOL_IOREG_CFG
+ HAL_STATUS rst =HAL_STATUS_SUCCESS;
+
+ hex += board;
+ hex += interfaceValue << 8;
+ hex += platform << 16;
+ hex += 0xFF000000;
+#ifdef CONFIG_IOL_IOREG_CFG
+ biol = rtw_IOL_applied(Adapter);
+
+ if(biol){
+ if((pxmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL)
+ {
+ printk("rtw_IOL_accquire_xmit_frame failed\n");
+ return HAL_STATUS_FAILURE;
+ }
+ }
+#endif//#ifdef CONFIG_IOL_IOREG_CFG
+
+ for (i = 0; i < ArrayLen; i += 2 )
+ {
+ u4Byte v1 = Array[i];
+ u4Byte v2 = Array[i+1];
+
+ // This (offset, data) pair meets the condition.
+ if ( v1 < 0xCDCDCDCD )
+ {
+ #ifdef CONFIG_IOL_IOREG_CFG
+ if(biol){
+ if(rtw_IOL_cmd_boundary_handle(pxmit_frame))
+ bndy_cnt++;
+
+ if(v1 == 0xffe)
+ {
+ rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,50);
+ }
+ else if (v1 == 0xfd){
+ rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,5);
+ }
+ else if (v1 == 0xfc){
+ rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,1);
+ }
+ else if (v1 == 0xfb){
+ rtw_IOL_append_DELAY_US_cmd(pxmit_frame,50);
+ }
+ else if (v1 == 0xfa){
+ rtw_IOL_append_DELAY_US_cmd(pxmit_frame,5);
+ }
+ else if (v1 == 0xf9){
+ rtw_IOL_append_DELAY_US_cmd(pxmit_frame,1);
+ }
+ else{
+ rtw_IOL_append_WRF_cmd(pxmit_frame, ODM_RF_PATH_A,(u2Byte)v1, v2,bRFRegOffsetMask) ;
+ #ifdef CONFIG_IOL_IOREG_CFG_DBG
+ cmpdata[cmpdata_idx].addr = v1;
+ cmpdata[cmpdata_idx].value= v2;
+ cmpdata_idx++;
+ #endif
+ }
+
+ }
+ else
+ #endif //#ifdef CONFIG_IOL_IOREG_CFG
+ {
+ odm_ConfigRF_RadioA_8188E(pDM_Odm, v1, v2);
+ }
+ continue;
+ }
+ else
+ { // This line is the start line of branch.
+ if ( !CheckCondition(Array[i], hex) )
+ { // Discard the following (offset, data) pairs.
+ READ_NEXT_PAIR(v1, v2, i);
+ while (v2 != 0xDEAD &&
+ v2 != 0xCDEF &&
+ v2 != 0xCDCD && i < ArrayLen -2)
+ {
+ READ_NEXT_PAIR(v1, v2, i);
+ }
+ i -= 2; // prevent from for-loop += 2
+ }
+ else // Configure matched pairs and skip to end of if-else.
+ {
+ READ_NEXT_PAIR(v1, v2, i);
+ while (v2 != 0xDEAD &&
+ v2 != 0xCDEF &&
+ v2 != 0xCDCD && i < ArrayLen -2)
+ {
+ #ifdef CONFIG_IOL_IOREG_CFG
+ if(biol){
+ if(rtw_IOL_cmd_boundary_handle(pxmit_frame))
+ bndy_cnt++;
+
+ if(v1 == 0xffe)
+ {
+ rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,50);
+ }
+ else if (v1 == 0xfd){
+ rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,5);
+ }
+ else if (v1 == 0xfc){
+ rtw_IOL_append_DELAY_MS_cmd(pxmit_frame,1);
+ }
+ else if (v1 == 0xfb){
+ rtw_IOL_append_DELAY_US_cmd(pxmit_frame,50);
+ }
+ else if (v1 == 0xfa){
+ rtw_IOL_append_DELAY_US_cmd(pxmit_frame,5);
+ }
+ else if (v1 == 0xf9){
+ rtw_IOL_append_DELAY_US_cmd(pxmit_frame,1);
+ }
+ else{
+ rtw_IOL_append_WRF_cmd(pxmit_frame, ODM_RF_PATH_A,(u2Byte)v1, v2,bRFRegOffsetMask) ;
+ #ifdef CONFIG_IOL_IOREG_CFG_DBG
+ cmpdata[cmpdata_idx].addr = v1;
+ cmpdata[cmpdata_idx].value= v2;
+ cmpdata_idx++;
+ #endif
+
+ }
+
+ }
+ else
+ #endif //#ifdef CONFIG_IOL_IOREG_CFG
+ {
+ odm_ConfigRF_RadioA_8188E(pDM_Odm, v1, v2);
+ }
+ READ_NEXT_PAIR(v1, v2, i);
+ }
+
+ while (v2 != 0xDEAD && i < ArrayLen -2)
+ {
+ READ_NEXT_PAIR(v1, v2, i);
+ }
+
+ }
+ }
+ }
+#ifdef CONFIG_IOL_IOREG_CFG
+ if(biol){
+ //printk("==> %s, pktlen = %d,bndy_cnt = %d\n",__FUNCTION__,pxmit_frame->attrib.pktlen+4+32,bndy_cnt);
+ if(rtw_IOL_exec_cmds_sync(pDM_Odm->Adapter, pxmit_frame, 1000, bndy_cnt))
+ {
+ #ifdef CONFIG_IOL_IOREG_CFG_DBG
+ printk("~~~ %s Success !!! \n",__FUNCTION__);
+ {
+ u4Byte idx;
+ u4Byte cdata;
+ printk(" %s data compare => array_len:%d \n",__FUNCTION__,cmpdata_idx);
+ printk("### %s data compared !!###\n",__FUNCTION__);
+ for(idx=0;idx< cmpdata_idx;idx++)
+ {
+ cdata = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A,cmpdata[idx].addr,bRFRegOffsetMask);
+ if(cdata != cmpdata[idx].value){
+ printk("addr:0x%04x, data:(0x%02x : 0x%02x) \n",
+ cmpdata[idx].addr,cmpdata[idx].value,cdata);
+ rst = HAL_STATUS_FAILURE;
+ }
+ }
+ printk("### %s data compared !!###\n",__FUNCTION__);
+ //if(rst == HAL_STATUS_FAILURE)
+ {//dump data from TX packet buffer
+ rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32);
+ }
+ }
+ #endif //CONFIG_IOL_IOREG_CFG_DBG
+
+ }
+ else{
+ rst = HAL_STATUS_FAILURE;
+ printk("~~~ IOL Config %s Failed !!! \n",__FUNCTION__);
+ #ifdef CONFIG_IOL_IOREG_CFG_DBG
+ {
+ //dump data from TX packet buffer
+ rtw_IOL_cmd_tx_pkt_buf_dump(pDM_Odm->Adapter,pxmit_frame->attrib.pktlen+32);
+ }
+ #endif //CONFIG_IOL_IOREG_CFG_DBG
+ }
+ }
+
+
+#endif //#ifdef CONFIG_IOL_IOREG_CFG
+ return rst;
+}
+
+#endif // end of HWIMG_SUPPORT
+
diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_RF.h b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_RF.h new file mode 100755 index 00000000..93ea0610 --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalHWImg8188E_RF.h @@ -0,0 +1,38 @@ +/******************************************************************************
+*
+* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms of version 2 of the GNU General Public License as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful, but WITHOUT
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+* more details.
+*
+* You should have received a copy of the GNU General Public License along with
+* this program; if not, write to the Free Software Foundation, Inc.,
+* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+*
+*
+******************************************************************************/
+
+#if (RTL8188E_SUPPORT == 1)
+#ifndef __INC_RF_8188E_HW_IMG_H
+#define __INC_RF_8188E_HW_IMG_H
+
+//static BOOLEAN CheckCondition(const u4Byte Condition, const u4Byte Hex);
+
+/******************************************************************************
+* RadioA_1T.TXT
+******************************************************************************/
+
+HAL_STATUS
+ODM_ReadAndConfig_RadioA_1T_8188E(
+ IN PDM_ODM_T pDM_Odm
+);
+
+#endif
+#endif // end of HWIMG_SUPPORT
+
diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalPhyRf_8188e.c b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalPhyRf_8188e.c new file mode 100755 index 00000000..d3e858ab --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalPhyRf_8188e.c @@ -0,0 +1,3500 @@ +
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+#include "../odm_precomp.h"
+
+
+
+/*---------------------------Define Local Constant---------------------------*/
+// 2010/04/25 MH Define the max tx power tracking tx agc power.
+#define ODM_TXPWRTRACK_MAX_IDX_88E 6
+
+/*---------------------------Define Local Constant---------------------------*/
+
+
+//3============================================================
+//3 Tx Power Tracking
+//3============================================================
+/*-----------------------------------------------------------------------------
+ * Function: ODM_TxPwrTrackAdjust88E()
+ *
+ * Overview: 88E we can not write 0xc80/c94/c4c/ 0xa2x. Instead of write TX agc.
+ * No matter OFDM & CCK use the same method.
+ *
+ * Input: NONE
+ *
+ * Output: NONE
+ *
+ * Return: NONE
+ *
+ * Revised History:
+ * When Who Remark
+ * 04/23/2012 MHC Create Version 0.
+ * 04/23/2012 MHC Adjust TX agc directly not throughput BB digital.
+ *
+ *---------------------------------------------------------------------------*/
+VOID
+ODM_TxPwrTrackAdjust88E(
+ PDM_ODM_T pDM_Odm,
+ u1Byte Type, // 0 = OFDM, 1 = CCK
+ pu1Byte pDirection, // 1 = +(increase) 2 = -(decrease)
+ pu4Byte pOutWriteVal // Tx tracking CCK/OFDM BB swing index adjust
+ )
+{
+ u1Byte pwr_value = 0;
+ //
+ // Tx power tracking BB swing table.
+ // The base index = 12. +((12-n)/2)dB 13~?? = decrease tx pwr by -((n-12)/2)dB
+ //
+ if (Type == 0) // For OFDM afjust
+ {
+ ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+ ("BbSwingIdxOfdm = %d BbSwingFlagOfdm=%d\n", pDM_Odm->BbSwingIdxOfdm, pDM_Odm->BbSwingFlagOfdm));
+
+ if (pDM_Odm->BbSwingIdxOfdm <= pDM_Odm->BbSwingIdxOfdmBase)
+ {
+ *pDirection = 1;
+ pwr_value = (pDM_Odm->BbSwingIdxOfdmBase - pDM_Odm->BbSwingIdxOfdm);
+ }
+ else
+ {
+ *pDirection = 2;
+ pwr_value = (pDM_Odm->BbSwingIdxOfdm - pDM_Odm->BbSwingIdxOfdmBase);
+ }
+
+ ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+ ("BbSwingIdxOfdm = %d BbSwingFlagOfdm=%d\n", pDM_Odm->BbSwingIdxOfdm, pDM_Odm->BbSwingFlagOfdm));
+
+ }
+ else if (Type == 1) // For CCK adjust.
+ {
+ ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
+ ("pDM_Odm->BbSwingIdxCck = %d pDM_Odm->BbSwingIdxCckBase = %d\n", pDM_Odm->BbSwingIdxCck, pDM_Odm->BbSwingIdxCckBase));
+
+ if (pDM_Odm->BbSwingIdxCck <= pDM_Odm->BbSwingIdxCckBase)
+ {
+ *pDirection = 1;
+ pwr_value = (pDM_Odm->BbSwingIdxCckBase - pDM_Odm->BbSwingIdxCck);
+ }
+ else
+ {
+ *pDirection = 2;
+ pwr_value = (pDM_Odm->BbSwingIdxCck - pDM_Odm->BbSwingIdxCckBase);
+ }
+ }
+
+ //
+ // 2012/04/25 MH According to Ed/Luke.Lees estimate for EVM the max tx power tracking
+ // need to be less than 6 power index for 88E.
+ //
+ if (pwr_value >= ODM_TXPWRTRACK_MAX_IDX_88E && *pDirection == 1)
+ pwr_value = ODM_TXPWRTRACK_MAX_IDX_88E;
+
+ *pOutWriteVal = pwr_value | (pwr_value<<8) | (pwr_value<<16) | (pwr_value<<24);
+
+} // ODM_TxPwrTrackAdjust88E
+
+
+/*-----------------------------------------------------------------------------
+ * Function: odm_TxPwrTrackSetPwr88E()
+ *
+ * Overview: 88E change all channel tx power accordign to flag.
+ * OFDM & CCK are all different.
+ *
+ * Input: NONE
+ *
+ * Output: NONE
+ *
+ * Return: NONE
+ *
+ * Revised History:
+ * When Who Remark
+ * 04/23/2012 MHC Create Version 0.
+ *
+ *---------------------------------------------------------------------------*/
+VOID
+odm_TxPwrTrackSetPwr88E(
+ PDM_ODM_T pDM_Odm
+ )
+{
+ if (pDM_Odm->BbSwingFlagOfdm == TRUE || pDM_Odm->BbSwingFlagCck == TRUE)
+ {
+ ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("odm_TxPwrTrackSetPwr88E CH=%d\n", *(pDM_Odm->pChannel)));
+#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE ))
+ PHY_SetTxPowerLevel8188E(pDM_Odm->Adapter, *(pDM_Odm->pChannel));
+#endif
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ PHY_RF6052SetCCKTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel));
+ PHY_RF6052SetOFDMTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel));
+#endif
+ pDM_Odm->BbSwingFlagOfdm = FALSE;
+ pDM_Odm->BbSwingFlagCck = FALSE;
+ }
+} // odm_TxPwrTrackSetPwr88E
+
+
+//091212 chiyokolin
+VOID
+odm_TXPowerTrackingCallback_ThermalMeter_8188E(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ IN PDM_ODM_T pDM_Odm
+#else
+ IN PADAPTER Adapter
+#endif
+ )
+{
+
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+ //PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
+#endif
+
+ u1Byte ThermalValue = 0, delta, delta_LCK, delta_IQK, offset;
+ u1Byte ThermalValue_AVG_count = 0;
+ u4Byte ThermalValue_AVG = 0;
+ s4Byte ele_A=0, ele_D, TempCCk, X, value32;
+ s4Byte Y, ele_C=0;
+ s1Byte OFDM_index[2], CCK_index=0, OFDM_index_old[2]={0,0}, CCK_index_old=0, index;
+ u4Byte i = 0, j = 0;
+ BOOLEAN is2T = FALSE;
+ BOOLEAN bInteralPA = FALSE;
+
+ u1Byte OFDM_min_index = 6, rf; //OFDM BB Swing should be less than +3.0dB, which is required by Arthur
+ u1Byte Indexforchannel = 0/*GetRightChnlPlaceforIQK(pHalData->CurrentChannel)*/;
+ s1Byte OFDM_index_mapping[2][index_mapping_NUM_88E] = {
+ {0, 0, 2, 3, 4, 4, //2.4G, decrease power
+ 5, 6, 7, 7, 8, 9,
+ 10, 10, 11}, // For lower temperature, 20120220 updated on 20120220.
+ {0, 0, -1, -2, -3, -4, //2.4G, increase power
+ -4, -4, -4, -5, -7, -8,
+ -9, -9, -10},
+ };
+ u1Byte Thermal_mapping[2][index_mapping_NUM_88E] = {
+ {0, 2, 4, 6, 8, 10, //2.4G, decrease power
+ 12, 14, 16, 18, 20, 22,
+ 24, 26, 27},
+ {0, 2, 4, 6, 8, 10, //2.4G,, increase power
+ 12, 14, 16, 18, 20, 22,
+ 25, 25, 25},
+ };
+ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
+ #endif
+ #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
+ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
+ #endif
+
+ // 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E.
+ odm_TxPwrTrackSetPwr88E(pDM_Odm);
+
+ pDM_Odm->RFCalibrateInfo.TXPowerTrackingCallbackCnt++; //cosa add for debug
+ pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = TRUE;
+
+#if (MP_DRIVER == 1)
+#if (DM_ODM_SUPPORT_TYPE == ODM_MP)
+ pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = pHalData->TxPowerTrackControl; // <Kordan> We should keep updating the control variable according to HalData.
+#endif
+
+ // <Kordan> RFCalibrateInfo.RegA24 will be initialized when ODM HW configuring, but MP configures with para files.
+ pDM_Odm->RFCalibrateInfo.RegA24 = 0x090e1317;
+#endif
+
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,("===>dm_TXPowerTrackingCallback_ThermalMeter_8188E txpowercontrol %d\n", pDM_Odm->RFCalibrateInfo.TxPowerTrackControl));
+
+ ThermalValue = (u1Byte)ODM_GetRFReg(pDM_Odm, RF_PATH_A, RF_T_METER_88E, 0xfc00); //0x42: RF Reg[15:10] 88E
+
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,("Readback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue, pHalData->EEPROMThermalMeter));
+
+ if(is2T)
+ rf = 2;
+ else
+ rf = 1;
+
+ if(ThermalValue)
+ {
+// if(!pHalData->ThermalValue)
+ {
+ //Query OFDM path A default setting
+ ele_D = ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord)&bMaskOFDM_D;
+ for(i=0; i<OFDM_TABLE_SIZE_92D; i++) //find the index
+ {
+ if(ele_D == (OFDMSwingTable[i]&bMaskOFDM_D))
+ {
+ OFDM_index_old[0] = (u1Byte)i;
+ pDM_Odm->BbSwingIdxOfdmBase = (u1Byte)i;
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,("Initial pathA ele_D reg0x%x = 0x%x, OFDM_index=0x%x\n",
+ rOFDM0_XATxIQImbalance, ele_D, OFDM_index_old[0]));
+ break;
+ }
+ }
+
+ //Query OFDM path B default setting
+ if(is2T)
+ {
+ ele_D = ODM_GetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord)&bMaskOFDM_D;
+ for(i=0; i<OFDM_TABLE_SIZE_92D; i++) //find the index
+ {
+ if(ele_D == (OFDMSwingTable[i]&bMaskOFDM_D))
+ {
+ OFDM_index_old[1] = (u1Byte)i;
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,("Initial pathB ele_D reg0x%x = 0x%x, OFDM_index=0x%x\n",
+ rOFDM0_XBTxIQImbalance, ele_D, OFDM_index_old[1]));
+ break;
+ }
+ }
+ }
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ CCK_index_old = get_CCK_swing_index(pDM_Odm->priv);
+#else
+ {
+ //Query CCK default setting From 0xa24
+ TempCCk = pDM_Odm->RFCalibrateInfo.RegA24;
+
+ for(i=0 ; i<CCK_TABLE_SIZE ; i++)
+ {
+ if(pDM_Odm->RFCalibrateInfo.bCCKinCH14)
+ {
+ if(ODM_CompareMemory(pDM_Odm,(void*)&TempCCk, (void*)&CCKSwingTable_Ch14[i][2], 4)==0)
+ {
+ CCK_index_old =(u1Byte) i;
+ pDM_Odm->BbSwingIdxCckBase = (u1Byte)i;
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,("Initial reg0x%x = 0x%x, CCK_index=0x%x, ch 14 %d\n",
+ rCCK0_TxFilter2, TempCCk, CCK_index_old, pDM_Odm->RFCalibrateInfo.bCCKinCH14));
+ break;
+ }
+ }
+ else
+ {
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,("RegA24: 0x%X, CCKSwingTable_Ch1_Ch13[%d][2]: CCKSwingTable_Ch1_Ch13[i][2]: 0x%X\n", TempCCk, i, CCKSwingTable_Ch1_Ch13[i][2]));
+ if(ODM_CompareMemory(pDM_Odm,(void*)&TempCCk, (void*)&CCKSwingTable_Ch1_Ch13[i][2], 4)==0)
+ {
+ CCK_index_old =(u1Byte) i;
+ pDM_Odm->BbSwingIdxCckBase = (u1Byte)i;
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,("Initial reg0x%x = 0x%x, CCK_index=0x%x, ch14 %d\n",
+ rCCK0_TxFilter2, TempCCk, CCK_index_old, pDM_Odm->RFCalibrateInfo.bCCKinCH14));
+ break;
+ }
+ }
+ }
+ }
+#endif
+
+ if(!pDM_Odm->RFCalibrateInfo.ThermalValue)
+ {
+#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE))
+ pDM_Odm->RFCalibrateInfo.ThermalValue = pHalData->EEPROMThermalMeter;
+#else
+ pDM_Odm->RFCalibrateInfo.ThermalValue = pDM_Odm->priv->pmib->dot11RFEntry.ther;
+#endif
+ pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = ThermalValue;
+ pDM_Odm->RFCalibrateInfo.ThermalValue_IQK = ThermalValue;
+
+ for(i = 0; i < rf; i++)
+ pDM_Odm->RFCalibrateInfo.OFDM_index[i] = OFDM_index_old[i];
+ pDM_Odm->RFCalibrateInfo.CCK_index = CCK_index_old;
+ }
+
+ if(pDM_Odm->RFCalibrateInfo.bReloadtxpowerindex)
+ {
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,("reload ofdm index for band switch\n"));
+ }
+
+ //calculate average thermal meter
+ {
+ pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index] = ThermalValue;
+ pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index++;
+ if(pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index == AVG_THERMAL_NUM_88E)
+ pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index = 0;
+
+ for(i = 0; i < AVG_THERMAL_NUM_88E; i++)
+ {
+ if(pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i])
+ {
+ ThermalValue_AVG += pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i];
+ ThermalValue_AVG_count++;
+ }
+ }
+
+ if(ThermalValue_AVG_count)
+ {
+ ThermalValue = (u1Byte)(ThermalValue_AVG / ThermalValue_AVG_count);
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,("AVG Thermal Meter = 0x%x \n", ThermalValue));
+ }
+ }
+ }
+
+ if(pDM_Odm->RFCalibrateInfo.bReloadtxpowerindex)
+ {
+#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE))
+ delta = ThermalValue > pHalData->EEPROMThermalMeter?(ThermalValue - pHalData->EEPROMThermalMeter):(pHalData->EEPROMThermalMeter - ThermalValue);
+#else
+ delta = (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther)?(ThermalValue - pDM_Odm->priv->pmib->dot11RFEntry.ther):(pDM_Odm->priv->pmib->dot11RFEntry.ther - ThermalValue);
+#endif
+ pDM_Odm->RFCalibrateInfo.bReloadtxpowerindex = FALSE;
+ pDM_Odm->RFCalibrateInfo.bDoneTxpower = FALSE;
+ }
+ else if(pDM_Odm->RFCalibrateInfo.bDoneTxpower)
+ {
+ delta = (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue)?(ThermalValue - pDM_Odm->RFCalibrateInfo.ThermalValue):(pDM_Odm->RFCalibrateInfo.ThermalValue - ThermalValue);
+ }
+ else
+ {
+#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE))
+ delta = ThermalValue > pHalData->EEPROMThermalMeter?(ThermalValue - pHalData->EEPROMThermalMeter):(pHalData->EEPROMThermalMeter - ThermalValue);
+#else
+ delta = (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther)?(ThermalValue - (pDM_Odm->priv->pmib->dot11RFEntry.ther)):((pDM_Odm->priv->pmib->dot11RFEntry.ther) - ThermalValue);
+#endif
+ }
+ delta_LCK = (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue_LCK)?(ThermalValue - pDM_Odm->RFCalibrateInfo.ThermalValue_LCK):(pDM_Odm->RFCalibrateInfo.ThermalValue_LCK - ThermalValue);
+ delta_IQK = (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue_IQK)?(ThermalValue - pDM_Odm->RFCalibrateInfo.ThermalValue_IQK):(pDM_Odm->RFCalibrateInfo.ThermalValue_IQK - ThermalValue);
+#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE))
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,("Readback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x delta 0x%x delta_LCK 0x%x delta_IQK 0x%x \n", ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue, pHalData->EEPROMThermalMeter, delta, delta_LCK, delta_IQK));
+#else
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,("Readback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x delta 0x%x delta_LCK 0x%x delta_IQK 0x%x \n", ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue, pDM_Odm->priv->pmib->dot11RFEntry.ther, delta, delta_LCK, delta_IQK));
+#endif
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,("pre thermal meter LCK 0x%x pre thermal meter IQK 0x%x delta_LCK_bound 0x%x delta_IQK_bound 0x%x\n", pDM_Odm->RFCalibrateInfo.ThermalValue_LCK, pDM_Odm->RFCalibrateInfo.ThermalValue_IQK, pDM_Odm->RFCalibrateInfo.Delta_LCK, pDM_Odm->RFCalibrateInfo.Delta_IQK));
+
+
+
+ //if((delta_LCK > pHalData->Delta_LCK) && (pHalData->Delta_LCK != 0))
+ if ((delta_LCK >= 8)) // Delta temperature is equal to or larger than 20 centigrade.
+ {
+ pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = ThermalValue;
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ PHY_LCCalibrate_8188E(Adapter);
+#else
+ PHY_LCCalibrate_8188E(pDM_Odm);
+#endif
+ }
+
+ if(delta > 0 && pDM_Odm->RFCalibrateInfo.TxPowerTrackControl)
+ {
+#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE))
+ delta = ThermalValue > pHalData->EEPROMThermalMeter?(ThermalValue - pHalData->EEPROMThermalMeter):(pHalData->EEPROMThermalMeter - ThermalValue);
+#else
+ delta = (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther)?(ThermalValue - pDM_Odm->priv->pmib->dot11RFEntry.ther):(pDM_Odm->priv->pmib->dot11RFEntry.ther - ThermalValue);
+#endif
+ //calculate new OFDM / CCK offset
+ {
+ {
+#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE))
+ if(ThermalValue > pHalData->EEPROMThermalMeter)
+#else
+ if(ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther)
+#endif
+ j = 1;
+ else
+ j = 0;
+
+ for(offset = 0; offset < index_mapping_NUM_88E; offset++)
+ {
+ if(delta < Thermal_mapping[j][offset])
+ {
+ if(offset != 0)
+ offset--;
+ break;
+ }
+ }
+ if(offset >= index_mapping_NUM_88E)
+ offset = index_mapping_NUM_88E-1;
+
+ index = OFDM_index_mapping[j][offset];
+
+ for(i = 0; i < rf; i++)
+ OFDM_index[i] = pDM_Odm->RFCalibrateInfo.OFDM_index[i] + OFDM_index_mapping[j][offset];
+ CCK_index = pDM_Odm->RFCalibrateInfo.CCK_index + OFDM_index_mapping[j][offset];
+ }
+
+ if(is2T)
+ {
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,("temp OFDM_A_index=0x%x, OFDM_B_index=0x%x, CCK_index=0x%x\n",
+ pDM_Odm->RFCalibrateInfo.OFDM_index[0], pDM_Odm->RFCalibrateInfo.OFDM_index[1], pDM_Odm->RFCalibrateInfo.CCK_index));
+ }
+ else
+ {
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,("temp OFDM_A_index=0x%x, CCK_index=0x%x\n",
+ pDM_Odm->RFCalibrateInfo.OFDM_index[0], pDM_Odm->RFCalibrateInfo.CCK_index));
+ }
+
+ for(i = 0; i < rf; i++)
+ {
+ if(OFDM_index[i] > OFDM_TABLE_SIZE_92D-1)
+ {
+ OFDM_index[i] = OFDM_TABLE_SIZE_92D-1;
+ }
+ else if (OFDM_index[i] < OFDM_min_index)
+ {
+ OFDM_index[i] = OFDM_min_index;
+ }
+ }
+
+ {
+ if(CCK_index > CCK_TABLE_SIZE-1)
+ CCK_index = CCK_TABLE_SIZE-1;
+ else if (CCK_index < 0)
+ CCK_index = 0;
+ }
+
+ if(is2T)
+ {
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,("new OFDM_A_index=0x%x, OFDM_B_index=0x%x, CCK_index=0x%x\n",
+ OFDM_index[0], OFDM_index[1], CCK_index));
+ }
+ else
+ {
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,("new OFDM_A_index=0x%x, CCK_index=0x%x\n",
+ OFDM_index[0], CCK_index));
+ }
+ }
+
+ //2 temporarily remove bNOPG
+ //Config by SwingTable
+ if(pDM_Odm->RFCalibrateInfo.TxPowerTrackControl /*&& !pHalData->bNOPG*/)
+ {
+ pDM_Odm->RFCalibrateInfo.bDoneTxpower = TRUE;
+
+ //Adujst OFDM Ant_A according to IQK result
+ ele_D = (OFDMSwingTable[(u1Byte)OFDM_index[0]] & 0xFFC00000)>>22;
+ X = pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][0];
+ Y = pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][1];
+
+ //
+ // Revse TX power table.
+ //
+ pDM_Odm->BbSwingIdxOfdm = (u1Byte)OFDM_index[0];
+ pDM_Odm->BbSwingIdxCck = (u1Byte)CCK_index;
+
+ //DbgPrint("pDM_Odm->BbSwingIdxOfdm = %d\n", pDM_Odm->BbSwingIdxOfdm);
+
+ if (pDM_Odm->BbSwingIdxOfdmCurrent != pDM_Odm->BbSwingIdxOfdm)
+ {
+ pDM_Odm->BbSwingIdxOfdmCurrent = pDM_Odm->BbSwingIdxOfdm;
+ pDM_Odm->BbSwingFlagOfdm = TRUE;
+ }
+
+ if (pDM_Odm->BbSwingIdxCckCurrent != pDM_Odm->BbSwingIdxCck)
+ {
+ pDM_Odm->BbSwingIdxCckCurrent = pDM_Odm->BbSwingIdxCck;
+ pDM_Odm->BbSwingFlagCck = TRUE;
+ }
+
+ if(X != 0)
+ {
+ if ((X & 0x00000200) != 0)
+ X = X | 0xFFFFFC00;
+ ele_A = ((X * ele_D)>>8)&0x000003FF;
+
+ //new element C = element D x Y
+ if ((Y & 0x00000200) != 0)
+ Y = Y | 0xFFFFFC00;
+ ele_C = ((Y * ele_D)>>8)&0x000003FF;
+
+ //
+ // 2012/04/23 MH According to Luke's suggestion, we can not write BB digital
+ // to increase TX power. Otherwise, EVM will be bad.
+ //
+#if 0
+ //wirte new elements A, C, D to regC80 and regC94, element B is always 0
+ value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A;
+ ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, value32);
+
+ value32 = (ele_C&0x000003C0)>>6;
+ ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, value32);
+
+ value32 = ((X * ele_D)>>7)&0x01;
+ ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, value32);
+#endif
+ }
+ else
+ {
+#if 0
+ ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable[(u1Byte)OFDM_index[0]]);
+ ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00);
+ ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, 0x00);
+#endif
+ }
+
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TxPwrTracking for path A: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x 0xe94 = 0x%x 0xe9c = 0x%x\n",
+ (u4Byte)X, (u4Byte)Y, (u4Byte)ele_A, (u4Byte)ele_C, (u4Byte)ele_D, (u4Byte)X, (u4Byte)Y));
+
+ {
+ //
+ // 2012/04/23 MH According to Luke's suggestion, we can not write BB digital
+ // to increase TX power. Otherwise, EVM will be bad.
+ //
+#if 0
+ //Adjust CCK according to IQK result
+ if(!pDM_Odm->RFCalibrateInfo.bCCKinCH14){
+ ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13[(u1Byte)CCK_index][0]);
+ ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13[(u1Byte)CCK_index][1]);
+ ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13[(u1Byte)CCK_index][2]);
+ ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13[(u1Byte)CCK_index][3]);
+ ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13[(u1Byte)CCK_index][4]);
+ ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13[(u1Byte)CCK_index][5]);
+ ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13[(u1Byte)CCK_index][6]);
+ ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13[(u1Byte)CCK_index][7]);
+ }
+ else{
+ ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14[(u1Byte)CCK_index][0]);
+ ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14[(u1Byte)CCK_index][1]);
+ ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14[(u1Byte)CCK_index][2]);
+ ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14[(u1Byte)CCK_index][3]);
+ ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14[(u1Byte)CCK_index][4]);
+ ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14[(u1Byte)CCK_index][5]);
+ ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14[(u1Byte)CCK_index][6]);
+ ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14[(u1Byte)CCK_index][7]);
+ }
+#endif
+ }
+
+ if(is2T)
+ {
+ ele_D = (OFDMSwingTable[(u1Byte)OFDM_index[1]] & 0xFFC00000)>>22;
+
+ //new element A = element D x X
+ X = pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][4];
+ Y = pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][5];
+
+ //if(X != 0 && pHalData->CurrentBandType92D == ODM_BAND_ON_2_4G)
+ if((X != 0) && (*(pDM_Odm->pBandType) == ODM_BAND_2_4G))
+
+ {
+ if ((X & 0x00000200) != 0) //consider minus
+ X = X | 0xFFFFFC00;
+ ele_A = ((X * ele_D)>>8)&0x000003FF;
+
+ //new element C = element D x Y
+ if ((Y & 0x00000200) != 0)
+ Y = Y | 0xFFFFFC00;
+ ele_C = ((Y * ele_D)>>8)&0x00003FF;
+
+ //wirte new elements A, C, D to regC88 and regC9C, element B is always 0
+ value32=(ele_D<<22)|((ele_C&0x3F)<<16) |ele_A;
+ ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, value32);
+
+ value32 = (ele_C&0x000003C0)>>6;
+ ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, value32);
+
+ value32 = ((X * ele_D)>>7)&0x01;
+ ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, value32);
+
+ }
+ else
+ {
+ ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable[(u1Byte)OFDM_index[1]]);
+ ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00);
+ ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, 0x00);
+ }
+
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TxPwrTracking path B: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x 0xeb4 = 0x%x 0xebc = 0x%x\n",
+ (u4Byte)X, (u4Byte)Y, (u4Byte)ele_A, (u4Byte)ele_C, (u4Byte)ele_D, (u4Byte)X, (u4Byte)Y));
+ }
+
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TxPwrTracking 0xc80 = 0x%x, 0xc94 = 0x%x RF 0x24 = 0x%x\n", ODM_GetBBReg(pDM_Odm, 0xc80, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xc94, bMaskDWord), ODM_GetRFReg(pDM_Odm, RF_PATH_A, 0x24, bRFRegOffsetMask)));
+ }
+ }
+
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+
+ // if((delta_IQK > pHalData->Delta_IQK) && (pHalData->Delta_IQK != 0))
+ if ((delta_IQK >= 8)) // Delta temperature is equal to or larger than 20 centigrade.
+ {
+ ODM_ResetIQKResult(pDM_Odm);
+
+#if(DM_ODM_SUPPORT_TYPE & ODM_MP)
+#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
+#if USE_WORKITEM
+ PlatformAcquireMutex(&pHalData->mxChnlBwControl);
+#else
+ PlatformAcquireSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK);
+#endif
+#elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
+ PlatformAcquireMutex(&pHalData->mxChnlBwControl);
+#endif
+#endif
+ pDM_Odm->RFCalibrateInfo.ThermalValue_IQK= ThermalValue;
+ PHY_IQCalibrate_8188E(Adapter, FALSE);
+
+#if(DM_ODM_SUPPORT_TYPE & ODM_MP)
+#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
+#if USE_WORKITEM
+ PlatformReleaseMutex(&pHalData->mxChnlBwControl);
+#else
+ PlatformReleaseSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK);
+#endif
+#elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
+ PlatformReleaseMutex(&pHalData->mxChnlBwControl);
+#endif
+#endif
+ }
+#endif
+ //update thermal meter value
+ if(pDM_Odm->RFCalibrateInfo.TxPowerTrackControl)
+ {
+ //Adapter->HalFunc.SetHalDefVarHandler(Adapter, HAL_DEF_THERMAL_VALUE, &ThermalValue);
+ pDM_Odm->RFCalibrateInfo.ThermalValue = ThermalValue;
+ }
+
+ }
+
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,("<===dm_TXPowerTrackingCallback_ThermalMeter_8188E\n"));
+
+ pDM_Odm->RFCalibrateInfo.TXPowercount = 0;
+
+}
+
+
+
+
+
+//1 7. IQK
+#define MAX_TOLERANCE 5
+#define IQK_DELAY_TIME 1 //ms
+
+u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK
+phy_PathA_IQK_8188E(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ IN PDM_ODM_T pDM_Odm,
+#else
+ IN PADAPTER pAdapter,
+#endif
+ IN BOOLEAN configPathB
+ )
+{
+ u4Byte regEAC, regE94, regE9C, regEA4;
+ u1Byte result = 0x00;
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
+ #endif
+ #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
+ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
+ #endif
+#endif
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK!\n"));
+
+ //1 Tx IQK
+ //path-A IQK setting
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A IQK setting!\n"));
+ ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c);
+ ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c);
+ ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x8214032a);
+ ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160000);
+
+ //LO calibration setting
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n"));
+ ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911);
+
+ //One shot, path A LOK & IQK
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n"));
+ ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
+ ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
+
+ // delay x ms
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E));
+ //PlatformStallExecution(IQK_DELAY_TIME_88E*1000);
+ ODM_delay_ms(IQK_DELAY_TIME_88E);
+
+ // Check failed
+ regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord);
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC));
+ regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord);
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x\n", regE94));
+ regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord);
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe9c = 0x%x\n", regE9C));
+ regEA4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord);
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x\n", regEA4));
+
+ if(!(regEAC & BIT28) &&
+ (((regE94 & 0x03FF0000)>>16) != 0x142) &&
+ (((regE9C & 0x03FF0000)>>16) != 0x42) )
+ result |= 0x01;
+ else //if Tx not OK, ignore Rx
+ return result;
+
+#if 0
+ if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK
+ (((regEA4 & 0x03FF0000)>>16) != 0x132) &&
+ (((regEAC & 0x03FF0000)>>16) != 0x36))
+ result |= 0x02;
+ else
+ RTPRINT(FINIT, INIT_IQK, ("Path A Rx IQK fail!!\n"));
+#endif
+
+ return result;
+
+
+ }
+
+u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK
+phy_PathA_RxIQK(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ IN PDM_ODM_T pDM_Odm,
+#else
+ IN PADAPTER pAdapter,
+#endif
+ IN BOOLEAN configPathB
+ )
+{
+ u4Byte regEAC, regE94, regE9C, regEA4, u4tmp;
+ u1Byte result = 0x00;
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
+ #endif
+ #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
+ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
+ #endif
+#endif
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK!\n"));
+
+ //1 Get TXIMR setting
+ //modify RXIQK mode table
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table!\n"));
+ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
+ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0 );
+ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000 );
+ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f );
+ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf117B );
+
+ //PA,PAD off
+ ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x980 );
+ ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x56, bRFRegOffsetMask, 0x51000 );
+
+ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80800000);
+
+ //IQK setting
+ ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00);
+ ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x81004800);
+
+ //path-A IQK setting
+ ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c);
+ ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c);
+ ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f);
+ ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160000);
+
+ //LO calibration setting
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n"));
+ ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911);
+
+ //One shot, path A LOK & IQK
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n"));
+ ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
+ ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
+
+ // delay x ms
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E));
+ //PlatformStallExecution(IQK_DELAY_TIME_88E*1000);
+ ODM_delay_ms(IQK_DELAY_TIME_88E);
+
+
+ // Check failed
+ regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord);
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC));
+ regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord);
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x\n", regE94));
+ regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord);
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe9c = 0x%x\n", regE9C));
+
+ if(!(regEAC & BIT28) &&
+ (((regE94 & 0x03FF0000)>>16) != 0x142) &&
+ (((regE9C & 0x03FF0000)>>16) != 0x42) )
+ {
+ result |= 0x01;
+ }
+ else
+ {
+ //reload RF 0xdf
+ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
+ ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180 );//if Tx not OK, ignore Rx
+ return result;
+ }
+
+ u4tmp = 0x80007C00 | (regE94&0x3FF0000) | ((regE9C&0x3FF0000) >> 16);
+ ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp);
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x \n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp));
+
+
+ //1 RX IQK
+ //modify RXIQK mode table
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table 2!\n"));
+ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
+ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0 );
+ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000 );
+ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f );
+ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ffa );
+ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80800000);
+
+ //IQK setting
+ ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800);
+
+ //path-A IQK setting
+ ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c);
+ ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c);
+ ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160c05);
+ ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160c1f);
+
+ //LO calibration setting
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n"));
+ ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911);
+
+ //One shot, path A LOK & IQK
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n"));
+ ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
+ ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
+
+ // delay x ms
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E));
+ //PlatformStallExecution(IQK_DELAY_TIME_88E*1000);
+ ODM_delay_ms(IQK_DELAY_TIME_88E);
+
+
+ // Check failed
+ regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord);
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC));
+ regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord);
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x\n", regE94));
+ regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord);
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe9c = 0x%x\n", regE9C));
+ regEA4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord);
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x\n", regEA4));
+
+ //reload RF 0xdf
+ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
+ ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180 );
+
+#if 0
+ if(!(regEAC & BIT28) &&
+ (((regE94 & 0x03FF0000)>>16) != 0x142) &&
+ (((regE9C & 0x03FF0000)>>16) != 0x42) )
+ result |= 0x01;
+ else //if Tx not OK, ignore Rx
+ return result;
+#endif
+
+ if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK
+ (((regEA4 & 0x03FF0000)>>16) != 0x132) &&
+ (((regEAC & 0x03FF0000)>>16) != 0x36))
+ result |= 0x02;
+ else
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK fail!!\n"));
+
+ return result;
+
+
+
+
+}
+
+u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK
+phy_PathB_IQK_8188E(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ IN PDM_ODM_T pDM_Odm
+#else
+ IN PADAPTER pAdapter
+#endif
+ )
+{
+ u4Byte regEAC, regEB4, regEBC, regEC4, regECC;
+ u1Byte result = 0x00;
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
+ #endif
+ #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
+ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
+ #endif
+#endif
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK!\n"));
+
+ //One shot, path B LOK & IQK
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n"));
+ ODM_SetBBReg(pDM_Odm, rIQK_AGC_Cont, bMaskDWord, 0x00000002);
+ ODM_SetBBReg(pDM_Odm, rIQK_AGC_Cont, bMaskDWord, 0x00000000);
+
+ // delay x ms
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_88E));
+ //PlatformStallExecution(IQK_DELAY_TIME_88E*1000);
+ ODM_delay_ms(IQK_DELAY_TIME_88E);
+
+ // Check failed
+ regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord);
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC));
+ regEB4 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord);
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeb4 = 0x%x\n", regEB4));
+ regEBC= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord);
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xebc = 0x%x\n", regEBC));
+ regEC4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_B_2, bMaskDWord);
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xec4 = 0x%x\n", regEC4));
+ regECC= ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_B_2, bMaskDWord);
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xecc = 0x%x\n", regECC));
+
+ if(!(regEAC & BIT31) &&
+ (((regEB4 & 0x03FF0000)>>16) != 0x142) &&
+ (((regEBC & 0x03FF0000)>>16) != 0x42))
+ result |= 0x01;
+ else
+ return result;
+
+ if(!(regEAC & BIT30) &&
+ (((regEC4 & 0x03FF0000)>>16) != 0x132) &&
+ (((regECC & 0x03FF0000)>>16) != 0x36))
+ result |= 0x02;
+ else
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK fail!!\n"));
+
+
+ return result;
+
+}
+
+VOID
+_PHY_PathAFillIQKMatrix(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ IN PDM_ODM_T pDM_Odm,
+#else
+ IN PADAPTER pAdapter,
+#endif
+ IN BOOLEAN bIQKOK,
+ IN s4Byte result[][8],
+ IN u1Byte final_candidate,
+ IN BOOLEAN bTxOnly
+ )
+{
+ u4Byte Oldval_0, X, TX0_A, reg;
+ s4Byte Y, TX0_C;
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
+ #endif
+ #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
+ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
+ #endif
+#endif
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed"));
+
+ if(final_candidate == 0xFF)
+ return;
+
+ else if(bIQKOK)
+ {
+ Oldval_0 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF;
+
+ X = result[final_candidate][0];
+ if ((X & 0x00000200) != 0)
+ X = X | 0xFFFFFC00;
+ TX0_A = (X * Oldval_0) >> 8;
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0));
+ ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A);
+
+ ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(31), ((X* Oldval_0>>7) & 0x1));
+
+ Y = result[final_candidate][1];
+ if ((Y & 0x00000200) != 0)
+ Y = Y | 0xFFFFFC00;
+
+
+ TX0_C = (Y * Oldval_0) >> 8;
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX = 0x%x\n", Y, TX0_C));
+ ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C&0x3C0)>>6));
+ ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C&0x3F));
+
+ ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(29), ((Y* Oldval_0>>7) & 0x1));
+
+ if(bTxOnly)
+ {
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("_PHY_PathAFillIQKMatrix only Tx OK\n"));
+ return;
+ }
+
+ reg = result[final_candidate][2];
+#if (DM_ODM_SUPPORT_TYPE==ODM_AP)
+ if( RTL_ABS(reg ,0x100) >= 16)
+ reg = 0x100;
+#endif
+ ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0x3FF, reg);
+
+ reg = result[final_candidate][3] & 0x3F;
+ ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0xFC00, reg);
+
+ reg = (result[final_candidate][3] >> 6) & 0xF;
+ ODM_SetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, 0xF0000000, reg);
+ }
+}
+
+VOID
+_PHY_PathBFillIQKMatrix(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ IN PDM_ODM_T pDM_Odm,
+#else
+ IN PADAPTER pAdapter,
+#endif
+ IN BOOLEAN bIQKOK,
+ IN s4Byte result[][8],
+ IN u1Byte final_candidate,
+ IN BOOLEAN bTxOnly //do Tx only
+ )
+{
+ u4Byte Oldval_1, X, TX1_A, reg;
+ s4Byte Y, TX1_C;
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
+ #endif
+ #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
+ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
+ #endif
+#endif
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed"));
+
+ if(final_candidate == 0xFF)
+ return;
+
+ else if(bIQKOK)
+ {
+ Oldval_1 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF;
+
+ X = result[final_candidate][4];
+ if ((X & 0x00000200) != 0)
+ X = X | 0xFFFFFC00;
+ TX1_A = (X * Oldval_1) >> 8;
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX1_A = 0x%x\n", X, TX1_A));
+ ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A);
+
+ ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(27), ((X* Oldval_1>>7) & 0x1));
+
+ Y = result[final_candidate][5];
+ if ((Y & 0x00000200) != 0)
+ Y = Y | 0xFFFFFC00;
+
+ TX1_C = (Y * Oldval_1) >> 8;
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C));
+ ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C&0x3C0)>>6));
+ ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C&0x3F));
+
+ ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(25), ((Y* Oldval_1>>7) & 0x1));
+
+ if(bTxOnly)
+ return;
+
+ reg = result[final_candidate][6];
+ ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0x3FF, reg);
+
+ reg = result[final_candidate][7] & 0x3F;
+ ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0xFC00, reg);
+
+ reg = (result[final_candidate][7] >> 6) & 0xF;
+ ODM_SetBBReg(pDM_Odm, rOFDM0_AGCRSSITable, 0x0000F000, reg);
+ }
+}
+
+//
+// 2011/07/26 MH Add an API for testing IQK fail case.
+//
+// MP Already declare in odm.c
+#if !(DM_ODM_SUPPORT_TYPE & ODM_MP)
+BOOLEAN
+ODM_CheckPowerStatus(
+ IN PADAPTER Adapter)
+{
+/*
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
+ RT_RF_POWER_STATE rtState;
+ PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
+
+ // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence.
+ if (pMgntInfo->init_adpt_in_progress == TRUE)
+ {
+ ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter"));
+ return TRUE;
+ }
+
+ //
+ // 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK.
+ //
+ Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState));
+ if(Adapter->bDriverStopped || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff)
+ {
+ ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to %d/%d/%d\n",
+ Adapter->bDriverStopped, Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState));
+ return FALSE;
+ }
+*/
+ return TRUE;
+}
+#endif
+
+VOID
+_PHY_SaveADDARegisters(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ IN PDM_ODM_T pDM_Odm,
+#else
+ IN PADAPTER pAdapter,
+#endif
+ IN pu4Byte ADDAReg,
+ IN pu4Byte ADDABackup,
+ IN u4Byte RegisterNum
+ )
+{
+ u4Byte i;
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
+ #endif
+ #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
+ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
+ #endif
+
+ if (ODM_CheckPowerStatus(pAdapter) == FALSE)
+ return;
+#endif
+
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save ADDA parameters.\n"));
+ for( i = 0 ; i < RegisterNum ; i++){
+ ADDABackup[i] = ODM_GetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord);
+ }
+}
+
+
+VOID
+_PHY_SaveMACRegisters(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ IN PDM_ODM_T pDM_Odm,
+#else
+ IN PADAPTER pAdapter,
+#endif
+ IN pu4Byte MACReg,
+ IN pu4Byte MACBackup
+ )
+{
+ u4Byte i;
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
+ #endif
+ #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
+ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
+ #endif
+#endif
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save MAC parameters.\n"));
+ for( i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){
+ MACBackup[i] = ODM_Read1Byte(pDM_Odm, MACReg[i]);
+ }
+ MACBackup[i] = ODM_Read4Byte(pDM_Odm, MACReg[i]);
+
+}
+
+
+VOID
+_PHY_ReloadADDARegisters(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ IN PDM_ODM_T pDM_Odm,
+#else
+ IN PADAPTER pAdapter,
+#endif
+ IN pu4Byte ADDAReg,
+ IN pu4Byte ADDABackup,
+ IN u4Byte RegiesterNum
+ )
+{
+ u4Byte i;
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
+ #endif
+ #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
+ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
+ #endif
+#endif
+
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload ADDA power saving parameters !\n"));
+ for(i = 0 ; i < RegiesterNum; i++)
+ {
+ ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, ADDABackup[i]);
+ }
+}
+
+VOID
+_PHY_ReloadMACRegisters(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ IN PDM_ODM_T pDM_Odm,
+#else
+ IN PADAPTER pAdapter,
+#endif
+ IN pu4Byte MACReg,
+ IN pu4Byte MACBackup
+ )
+{
+ u4Byte i;
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
+ #endif
+ #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
+ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
+ #endif
+#endif
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload MAC parameters !\n"));
+ for(i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){
+ ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)MACBackup[i]);
+ }
+ ODM_Write4Byte(pDM_Odm, MACReg[i], MACBackup[i]);
+}
+
+
+VOID
+_PHY_PathADDAOn(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ IN PDM_ODM_T pDM_Odm,
+#else
+ IN PADAPTER pAdapter,
+#endif
+ IN pu4Byte ADDAReg,
+ IN BOOLEAN isPathAOn,
+ IN BOOLEAN is2T
+ )
+{
+ u4Byte pathOn;
+ u4Byte i;
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
+ #endif
+ #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
+ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
+ #endif
+#endif
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("ADDA ON.\n"));
+
+ pathOn = isPathAOn ? 0x04db25a4 : 0x0b1b25a4;
+ if(FALSE == is2T){
+ pathOn = 0x0bdb25a0;
+ ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, 0x0b1b25a0);
+ }
+ else{
+ ODM_SetBBReg(pDM_Odm,ADDAReg[0], bMaskDWord, pathOn);
+ }
+
+ for( i = 1 ; i < IQK_ADDA_REG_NUM ; i++){
+ ODM_SetBBReg(pDM_Odm,ADDAReg[i], bMaskDWord, pathOn);
+ }
+
+}
+
+VOID
+_PHY_MACSettingCalibration(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ IN PDM_ODM_T pDM_Odm,
+#else
+ IN PADAPTER pAdapter,
+#endif
+ IN pu4Byte MACReg,
+ IN pu4Byte MACBackup
+ )
+{
+ u4Byte i = 0;
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
+ #endif
+ #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
+ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
+ #endif
+#endif
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("MAC settings for Calibration.\n"));
+
+ ODM_Write1Byte(pDM_Odm, MACReg[i], 0x3F);
+
+ for(i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++){
+ ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT3)));
+ }
+ ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT5)));
+
+}
+
+VOID
+_PHY_PathAStandBy(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ IN PDM_ODM_T pDM_Odm
+#else
+ IN PADAPTER pAdapter
+#endif
+ )
+{
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
+ #endif
+ #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
+ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
+ #endif
+#endif
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A standby mode!\n"));
+
+ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x0);
+ ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x00010000);
+ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80800000);
+}
+
+VOID
+_PHY_PIModeSwitch(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ IN PDM_ODM_T pDM_Odm,
+#else
+ IN PADAPTER pAdapter,
+#endif
+ IN BOOLEAN PIMode
+ )
+{
+ u4Byte mode;
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
+ #endif
+ #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
+ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
+ #endif
+#endif
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BB Switch to %s mode!\n", (PIMode ? "PI" : "SI")));
+
+ mode = PIMode ? 0x01000100 : 0x01000000;
+ ODM_SetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode);
+ ODM_SetBBReg(pDM_Odm, rFPGA0_XB_HSSIParameter1, bMaskDWord, mode);
+}
+
+BOOLEAN
+phy_SimularityCompare_8188E(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ IN PDM_ODM_T pDM_Odm,
+#else
+ IN PADAPTER pAdapter,
+#endif
+ IN s4Byte result[][8],
+ IN u1Byte c1,
+ IN u1Byte c2
+ )
+{
+ u4Byte i, j, diff, SimularityBitMap, bound = 0;
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
+ #endif
+ #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
+ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
+ #endif
+#endif
+ u1Byte final_candidate[2] = {0xFF, 0xFF}; //for path A and path B
+ BOOLEAN bResult = TRUE;
+ BOOLEAN is2T;
+ s4Byte tmp1 = 0,tmp2 = 0;
+
+ if( (pDM_Odm->RFType ==ODM_2T2R )||(pDM_Odm->RFType ==ODM_2T3R )||(pDM_Odm->RFType ==ODM_2T4R ))
+ is2T = TRUE;
+ else
+ is2T = FALSE;
+
+ if(is2T)
+ bound = 8;
+ else
+ bound = 4;
+
+
+
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> IQK:phy_SimularityCompare_8188E c1 %d c2 %d!!!\n", c1, c2));
+
+
+ SimularityBitMap = 0;
+
+ for( i = 0; i < bound; i++ )
+ {
+// diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] - result[c2][i]) : (result[c2][i] - result[c1][i]);
+ if((i==1) || (i==3) || (i==5) || (i==7))
+ {
+ if((result[c1][i]& 0x00000200) != 0)
+ tmp1 = result[c1][i] | 0xFFFFFC00;
+ else
+ tmp1 = result[c1][i];
+
+ if((result[c2][i]& 0x00000200) != 0)
+ tmp2 = result[c2][i] | 0xFFFFFC00;
+ else
+ tmp2 = result[c2][i];
+ }
+ else
+ {
+ tmp1 = result[c1][i];
+ tmp2 = result[c2][i];
+ }
+
+ diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
+
+ if (diff > MAX_TOLERANCE)
+ {
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:phy_SimularityCompare_8188E differnece overflow index %d compare1 0x%x compare2 0x%x!!!\n", i, result[c1][i], result[c2][i]));
+
+ if((i == 2 || i == 6) && !SimularityBitMap)
+ {
+ if(result[c1][i]+result[c1][i+1] == 0)
+ final_candidate[(i/4)] = c2;
+ else if (result[c2][i]+result[c2][i+1] == 0)
+ final_candidate[(i/4)] = c1;
+ else
+ SimularityBitMap = SimularityBitMap|(1<<i);
+ }
+ else
+ SimularityBitMap = SimularityBitMap|(1<<i);
+ }
+ }
+
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:phy_SimularityCompare_8188E SimularityBitMap %d !!!\n", SimularityBitMap));
+
+ if ( SimularityBitMap == 0)
+ {
+ for( i = 0; i < (bound/4); i++ )
+ {
+ if(final_candidate[i] != 0xFF)
+ {
+ for( j = i*4; j < (i+1)*4-2; j++)
+ result[3][j] = result[final_candidate[i]][j];
+ bResult = FALSE;
+ }
+ }
+ return bResult;
+ }
+ else
+ {
+
+ if (!(SimularityBitMap & 0x03)) //path A TX OK
+ {
+ for(i = 0; i < 2; i++)
+ result[3][i] = result[c1][i];
+ }
+
+ if (!(SimularityBitMap & 0x0c)) //path A RX OK
+ {
+ for(i = 2; i < 4; i++)
+ result[3][i] = result[c1][i];
+ }
+
+ if (!(SimularityBitMap & 0x30)) //path B TX OK
+ {
+ for(i = 4; i < 6; i++)
+ result[3][i] = result[c1][i];
+
+ }
+
+ if (!(SimularityBitMap & 0xc0)) //path B RX OK
+ {
+ for(i = 6; i < 8; i++)
+ result[3][i] = result[c1][i];
+ }
+
+ return FALSE;
+ }
+
+}
+
+
+
+VOID
+phy_IQCalibrate_8188E(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ IN PDM_ODM_T pDM_Odm,
+#else
+ IN PADAPTER pAdapter,
+#endif
+ IN s4Byte result[][8],
+ IN u1Byte t,
+ IN BOOLEAN is2T
+ )
+{
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
+ #endif
+ #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
+ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
+ #endif
+#endif
+ u4Byte i;
+ u1Byte PathAOK, PathBOK;
+ u4Byte ADDA_REG[IQK_ADDA_REG_NUM] = {
+ rFPGA0_XCD_SwitchControl, rBlue_Tooth,
+ rRx_Wait_CCA, rTx_CCK_RFON,
+ rTx_CCK_BBON, rTx_OFDM_RFON,
+ rTx_OFDM_BBON, rTx_To_Rx,
+ rTx_To_Tx, rRx_CCK,
+ rRx_OFDM, rRx_Wait_RIFS,
+ rRx_TO_Rx, rStandby,
+ rSleep, rPMPD_ANAEN };
+ u4Byte IQK_MAC_REG[IQK_MAC_REG_NUM] = {
+ REG_TXPAUSE, REG_BCN_CTRL,
+ REG_BCN_CTRL_1, REG_GPIO_MUXCFG};
+
+ //since 92C & 92D have the different define in IQK_BB_REG
+ u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
+ rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar,
+ rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB,
+ rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE,
+ rFPGA0_XB_RFInterfaceOE, rFPGA0_RFMOD
+ };
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
+ u4Byte retryCount = 2;
+#else
+#if MP_DRIVER
+ u4Byte retryCount = 9;
+#else
+ u4Byte retryCount = 2;
+#endif
+#endif
+if ( *(pDM_Odm->mp_mode) == 1)
+ retryCount = 9;
+else
+ retryCount = 2;
+ // Note: IQ calibration must be performed after loading
+ // PHY_REG.txt , and radio_a, radio_b.txt
+
+ //u4Byte bbvalue;
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
+#ifdef MP_TEST
+ if(pDM_Odm->priv->pshare->rf_ft_var.mp_specific)
+ retryCount = 9;
+#endif
+#endif
+
+
+ if(t==0)
+ {
+// bbvalue = ODM_GetBBReg(pDM_Odm, rFPGA0_RFMOD, bMaskDWord);
+// RTPRINT(FINIT, INIT_IQK, ("phy_IQCalibrate_8188E()==>0x%08x\n",bbvalue));
+
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t));
+
+ // Save ADDA parameters, turn Path A ADDA on
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ _PHY_SaveADDARegisters(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);
+ _PHY_SaveMACRegisters(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);
+ _PHY_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);
+#else
+ _PHY_SaveADDARegisters(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);
+ _PHY_SaveMACRegisters(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);
+ _PHY_SaveADDARegisters(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);
+#endif
+ }
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t));
+
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+
+ _PHY_PathADDAOn(pAdapter, ADDA_REG, TRUE, is2T);
+#else
+ _PHY_PathADDAOn(pDM_Odm, ADDA_REG, TRUE, is2T);
+#endif
+
+
+ if(t==0)
+ {
+ pDM_Odm->RFCalibrateInfo.bRfPiEnable = (u1Byte)ODM_GetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, BIT(8));
+ }
+
+ if(!pDM_Odm->RFCalibrateInfo.bRfPiEnable){
+ // Switch BB to PI mode to do IQ Calibration.
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ _PHY_PIModeSwitch(pAdapter, TRUE);
+#else
+ _PHY_PIModeSwitch(pDM_Odm, TRUE);
+#endif
+ }
+
+ //BB setting
+ ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0x00);
+ ODM_SetBBReg(pDM_Odm, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600);
+ ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4);
+ ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000);
+
+
+ ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01);
+ ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01);
+ ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00);
+ ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00);
+
+
+ if(is2T)
+ {
+ ODM_SetBBReg(pDM_Odm, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00010000);
+ ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00010000);
+ }
+
+ //MAC settings
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ _PHY_MACSettingCalibration(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);
+#else
+ _PHY_MACSettingCalibration(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);
+#endif
+
+
+ //Page B init
+ //AP or IQK
+ ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000);
+
+ if(is2T)
+ {
+ ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x0f600000);
+ }
+
+ // IQ calibration setting
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK setting!\n"));
+ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80800000);
+ ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00);
+ ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x81004800);
+
+ for(i = 0 ; i < retryCount ; i++){
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ PathAOK = phy_PathA_IQK_8188E(pAdapter, is2T);
+#else
+ PathAOK = phy_PathA_IQK_8188E(pDM_Odm, is2T);
+#endif
+// if(PathAOK == 0x03){
+ if(PathAOK == 0x01){
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Tx IQK Success!!\n"));
+ result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;
+ result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;
+ break;
+ }
+#if 0
+ else if (i == (retryCount-1) && PathAOK == 0x01) //Tx IQK OK
+ {
+ RTPRINT(FINIT, INIT_IQK, ("Path A IQK Only Tx Success!!\n"));
+
+ result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;
+ result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;
+ }
+#endif
+ }
+
+ for(i = 0 ; i < retryCount ; i++){
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ PathAOK = phy_PathA_RxIQK(pAdapter, is2T);
+#else
+ PathAOK = phy_PathA_RxIQK(pDM_Odm, is2T);
+#endif
+ if(PathAOK == 0x03){
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Success!!\n"));
+// result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;
+// result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;
+ result[t][2] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
+ result[t][3] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
+ break;
+ }
+ else
+ {
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Fail!!\n"));
+ }
+ }
+
+ if(0x00 == PathAOK){
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK failed!!\n"));
+ }
+
+ if(is2T){
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ _PHY_PathAStandBy(pAdapter);
+
+ // Turn Path B ADDA on
+ _PHY_PathADDAOn(pAdapter, ADDA_REG, FALSE, is2T);
+#else
+ _PHY_PathAStandBy(pDM_Odm);
+
+ // Turn Path B ADDA on
+ _PHY_PathADDAOn(pDM_Odm, ADDA_REG, FALSE, is2T);
+#endif
+
+ for(i = 0 ; i < retryCount ; i++){
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ PathBOK = phy_PathB_IQK_8188E(pAdapter);
+#else
+ PathBOK = phy_PathB_IQK_8188E(pDM_Odm);
+#endif
+ if(PathBOK == 0x03){
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK Success!!\n"));
+ result[t][4] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16;
+ result[t][5] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16;
+ result[t][6] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_B_2, bMaskDWord)&0x3FF0000)>>16;
+ result[t][7] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_B_2, bMaskDWord)&0x3FF0000)>>16;
+ break;
+ }
+ else if (i == (retryCount - 1) && PathBOK == 0x01) //Tx IQK OK
+ {
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Only Tx IQK Success!!\n"));
+ result[t][4] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16;
+ result[t][5] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16;
+ }
+ }
+
+ if(0x00 == PathBOK){
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK failed!!\n"));
+ }
+ }
+
+ //Back to BB mode, load original value
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Back to BB mode, load original value!\n"));
+ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0);
+
+ if(t!=0)
+ {
+ if(!pDM_Odm->RFCalibrateInfo.bRfPiEnable){
+ // Switch back BB to SI mode after finish IQ Calibration.
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ _PHY_PIModeSwitch(pAdapter, FALSE);
+#else
+ _PHY_PIModeSwitch(pDM_Odm, FALSE);
+#endif
+ }
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+
+ // Reload ADDA power saving parameters
+ _PHY_ReloadADDARegisters(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);
+
+ // Reload MAC parameters
+ _PHY_ReloadMACRegisters(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);
+
+ _PHY_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);
+#else
+ // Reload ADDA power saving parameters
+ _PHY_ReloadADDARegisters(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);
+
+ // Reload MAC parameters
+ _PHY_ReloadMACRegisters(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);
+
+ _PHY_ReloadADDARegisters(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);
+#endif
+
+
+ // Restore RX initial gain
+ ODM_SetBBReg(pDM_Odm, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00032ed3);
+ if(is2T){
+ ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00032ed3);
+ }
+
+ //load 0xe30 IQC default value
+ ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);
+ ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);
+
+
+ }
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_IQCalibrate_8188E() <==\n"));
+
+}
+
+
+VOID
+phy_LCCalibrate_8188E(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ IN PDM_ODM_T pDM_Odm,
+#else
+ IN PADAPTER pAdapter,
+#endif
+ IN BOOLEAN is2T
+ )
+{
+ u1Byte tmpReg;
+ u4Byte RF_Amode=0, RF_Bmode=0, LC_Cal;
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
+ #endif
+ #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
+ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
+ #endif
+#endif
+ //Check continuous TX and Packet TX
+ tmpReg = ODM_Read1Byte(pDM_Odm, 0xd03);
+
+ if((tmpReg&0x70) != 0) //Deal with contisuous TX case
+ ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg&0x8F); //disable all continuous TX
+ else // Deal with Packet TX case
+ ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); // block all queues
+
+ if((tmpReg&0x70) != 0)
+ {
+ //1. Read original RF mode
+ //Path-A
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ RF_Amode = PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_AC, bMask12Bits);
+
+ //Path-B
+ if(is2T)
+ RF_Bmode = PHY_QueryRFReg(pAdapter, RF_PATH_B, RF_AC, bMask12Bits);
+#else
+ RF_Amode = ODM_GetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bMask12Bits);
+
+ //Path-B
+ if(is2T)
+ RF_Bmode = ODM_GetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMask12Bits);
+#endif
+
+ //2. Set RF mode = standby mode
+ //Path-A
+ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&0x8FFFF)|0x10000);
+
+ //Path-B
+ if(is2T)
+ ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode&0x8FFFF)|0x10000);
+ }
+
+ //3. Read RF reg18
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ LC_Cal = PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_CHNLBW, bMask12Bits);
+#else
+ LC_Cal = ODM_GetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bMask12Bits);
+#endif
+
+ //4. Set LC calibration begin bit15
+ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000);
+
+ ODM_sleep_ms(100);
+
+
+ //Restore original situation
+ if((tmpReg&0x70) != 0) //Deal with contisuous TX case
+ {
+ //Path-A
+ ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg);
+ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bMask12Bits, RF_Amode);
+
+ //Path-B
+ if(is2T)
+ ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode);
+ }
+ else // Deal with Packet TX case
+ {
+ ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00);
+ }
+}
+
+//Analog Pre-distortion calibration
+#define APK_BB_REG_NUM 8
+#define APK_CURVE_REG_NUM 4
+#define PATH_NUM 2
+
+VOID
+phy_APCalibrate_8188E(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ IN PDM_ODM_T pDM_Odm,
+#else
+ IN PADAPTER pAdapter,
+#endif
+ IN s1Byte delta,
+ IN BOOLEAN is2T
+ )
+{
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
+ #endif
+ #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
+ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
+ #endif
+#endif
+ u4Byte regD[PATH_NUM];
+ u4Byte tmpReg, index, offset, apkbound;
+ u1Byte path, i, pathbound = PATH_NUM;
+ u4Byte BB_backup[APK_BB_REG_NUM];
+ u4Byte BB_REG[APK_BB_REG_NUM] = {
+ rFPGA1_TxBlock, rOFDM0_TRxPathEnable,
+ rFPGA0_RFMOD, rOFDM0_TRMuxPar,
+ rFPGA0_XCD_RFInterfaceSW, rFPGA0_XAB_RFInterfaceSW,
+ rFPGA0_XA_RFInterfaceOE, rFPGA0_XB_RFInterfaceOE };
+ u4Byte BB_AP_MODE[APK_BB_REG_NUM] = {
+ 0x00000020, 0x00a05430, 0x02040000,
+ 0x000800e4, 0x00204000 };
+ u4Byte BB_normal_AP_MODE[APK_BB_REG_NUM] = {
+ 0x00000020, 0x00a05430, 0x02040000,
+ 0x000800e4, 0x22204000 };
+
+ u4Byte AFE_backup[IQK_ADDA_REG_NUM];
+ u4Byte AFE_REG[IQK_ADDA_REG_NUM] = {
+ rFPGA0_XCD_SwitchControl, rBlue_Tooth,
+ rRx_Wait_CCA, rTx_CCK_RFON,
+ rTx_CCK_BBON, rTx_OFDM_RFON,
+ rTx_OFDM_BBON, rTx_To_Rx,
+ rTx_To_Tx, rRx_CCK,
+ rRx_OFDM, rRx_Wait_RIFS,
+ rRx_TO_Rx, rStandby,
+ rSleep, rPMPD_ANAEN };
+
+ u4Byte MAC_backup[IQK_MAC_REG_NUM];
+ u4Byte MAC_REG[IQK_MAC_REG_NUM] = {
+ REG_TXPAUSE, REG_BCN_CTRL,
+ REG_BCN_CTRL_1, REG_GPIO_MUXCFG};
+
+ u4Byte APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = {
+ {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c},
+ {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e}
+ };
+
+ u4Byte APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = {
+ {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, //path settings equal to path b settings
+ {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c}
+ };
+
+ u4Byte APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = {
+ {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d},
+ {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050}
+ };
+
+ u4Byte APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = {
+ {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, //path settings equal to path b settings
+ {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}
+ };
+
+ u4Byte AFE_on_off[PATH_NUM] = {
+ 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on
+
+ u4Byte APK_offset[PATH_NUM] = {
+ rConfig_AntA, rConfig_AntB};
+
+ u4Byte APK_normal_offset[PATH_NUM] = {
+ rConfig_Pmpd_AntA, rConfig_Pmpd_AntB};
+
+ u4Byte APK_value[PATH_NUM] = {
+ 0x92fc0000, 0x12fc0000};
+
+ u4Byte APK_normal_value[PATH_NUM] = {
+ 0x92680000, 0x12680000};
+
+ s1Byte APK_delta_mapping[APK_BB_REG_NUM][13] = {
+ {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
+ {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
+ {-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
+ {-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6},
+ {-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0}
+ };
+
+ u4Byte APK_normal_setting_value_1[13] = {
+ 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28,
+ 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3,
+ 0x12680000, 0x00880000, 0x00880000
+ };
+
+ u4Byte APK_normal_setting_value_2[16] = {
+ 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3,
+ 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025,
+ 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008,
+ 0x00050006
+ };
+
+ u4Byte APK_result[PATH_NUM][APK_BB_REG_NUM]; //val_1_1a, val_1_2a, val_2a, val_3a, val_4a
+// u4Byte AP_curve[PATH_NUM][APK_CURVE_REG_NUM];
+
+ s4Byte BB_offset, delta_V, delta_offset;
+
+#if MP_DRIVER == 1
+if ( *(pDM_Odm->mp_mode) == 1)
+{
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
+#else
+ PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx);
+#endif
+ pMptCtx->APK_bound[0] = 45;
+ pMptCtx->APK_bound[1] = 52;
+}
+#endif
+
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_APCalibrate_8188E() delta %d\n", delta));
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("AP Calibration for %s\n", (is2T ? "2T2R" : "1T1R")));
+ if(!is2T)
+ pathbound = 1;
+
+ //2 FOR NORMAL CHIP SETTINGS
+
+// Temporarily do not allow normal driver to do the following settings because these offset
+// and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal
+// will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the
+// root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31.
+//#if MP_DRIVER != 1
+if (*(pDM_Odm->mp_mode) != 1)
+ return;
+//#endif
+ //settings adjust for normal chip
+ for(index = 0; index < PATH_NUM; index ++)
+ {
+ APK_offset[index] = APK_normal_offset[index];
+ APK_value[index] = APK_normal_value[index];
+ AFE_on_off[index] = 0x6fdb25a4;
+ }
+
+ for(index = 0; index < APK_BB_REG_NUM; index ++)
+ {
+ for(path = 0; path < pathbound; path++)
+ {
+ APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index];
+ APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index];
+ }
+ BB_AP_MODE[index] = BB_normal_AP_MODE[index];
+ }
+
+ apkbound = 6;
+
+ //save BB default value
+ for(index = 0; index < APK_BB_REG_NUM ; index++)
+ {
+ if(index == 0) //skip
+ continue;
+ BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord);
+ }
+
+ //save MAC default value
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ _PHY_SaveMACRegisters(pAdapter, MAC_REG, MAC_backup);
+
+ //save AFE default value
+ _PHY_SaveADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
+#else
+ _PHY_SaveMACRegisters(pDM_Odm, MAC_REG, MAC_backup);
+
+ //save AFE default value
+ _PHY_SaveADDARegisters(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
+#endif
+
+ for(path = 0; path < pathbound; path++)
+ {
+
+
+ if(path == RF_PATH_A)
+ {
+ //path A APK
+ //load APK setting
+ //path-A
+ offset = rPdp_AntA;
+ for(index = 0; index < 11; index ++)
+ {
+ ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]);
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));
+
+ offset += 0x04;
+ }
+
+ ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000);
+
+ offset = rConfig_AntA;
+ for(; index < 13; index ++)
+ {
+ ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]);
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));
+
+ offset += 0x04;
+ }
+
+ //page-B1
+ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000);
+
+ //path A
+ offset = rPdp_AntA;
+ for(index = 0; index < 16; index++)
+ {
+ ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]);
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));
+
+ offset += 0x04;
+ }
+ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
+ }
+ else if(path == RF_PATH_B)
+ {
+ //path B APK
+ //load APK setting
+ //path-B
+ offset = rPdp_AntB;
+ for(index = 0; index < 10; index ++)
+ {
+ ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]);
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));
+
+ offset += 0x04;
+ }
+ ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x12680000);
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000);
+#else
+ PHY_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000);
+#endif
+
+ offset = rConfig_AntA;
+ index = 11;
+ for(; index < 13; index ++) //offset 0xb68, 0xb6c
+ {
+ ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]);
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));
+
+ offset += 0x04;
+ }
+
+ //page-B1
+ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000);
+
+ //path B
+ offset = 0xb60;
+ for(index = 0; index < 16; index++)
+ {
+ ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]);
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));
+
+ offset += 0x04;
+ }
+ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0);
+ }
+
+ //save RF default value
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ regD[path] = PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord);
+#else
+ regD[path] = ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord);
+#endif
+
+ //Path A AFE all on, path B AFE All off or vise versa
+ for(index = 0; index < IQK_ADDA_REG_NUM ; index++)
+ ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, AFE_on_off[path]);
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xe70 %x\n", ODM_GetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord)));
+
+ //BB to AP mode
+ if(path == 0)
+ {
+ for(index = 0; index < APK_BB_REG_NUM ; index++)
+ {
+
+ if(index == 0) //skip
+ continue;
+ else if (index < 5)
+ ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_AP_MODE[index]);
+ else if (BB_REG[index] == 0x870)
+ ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26);
+ else
+ ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x0);
+ }
+
+ ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);
+ ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);
+ }
+ else //path B
+ {
+ ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00);
+ ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00);
+
+ }
+
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x800 %x\n", ODM_GetBBReg(pDM_Odm, 0x800, bMaskDWord)));
+
+ //MAC settings
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ _PHY_MACSettingCalibration(pAdapter, MAC_REG, MAC_backup);
+#else
+ _PHY_MACSettingCalibration(pDM_Odm, MAC_REG, MAC_backup);
+#endif
+
+ if(path == RF_PATH_A) //Path B to standby mode
+ {
+ ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMaskDWord, 0x10000);
+ }
+ else //Path A to standby mode
+ {
+ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bMaskDWord, 0x10000);
+ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f);
+ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_MODE2, bMaskDWord, 0x20103);
+ }
+
+ delta_offset = ((delta+14)/2);
+ if(delta_offset < 0)
+ delta_offset = 0;
+ else if (delta_offset > 12)
+ delta_offset = 12;
+
+ //AP calibration
+ for(index = 0; index < APK_BB_REG_NUM; index++)
+ {
+ if(index != 1) //only DO PA11+PAD01001, AP RF setting
+ continue;
+
+ tmpReg = APK_RF_init_value[path][index];
+#if 1
+ if(!pDM_Odm->RFCalibrateInfo.bAPKThermalMeterIgnore)
+ {
+ BB_offset = (tmpReg & 0xF0000) >> 16;
+
+ if(!(tmpReg & BIT15)) //sign bit 0
+ {
+ BB_offset = -BB_offset;
+ }
+
+ delta_V = APK_delta_mapping[index][delta_offset];
+
+ BB_offset += delta_V;
+
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() APK index %d tmpReg 0x%x delta_V %d delta_offset %d\n", index, tmpReg, delta_V, delta_offset));
+
+ if(BB_offset < 0)
+ {
+ tmpReg = tmpReg & (~BIT15);
+ BB_offset = -BB_offset;
+ }
+ else
+ {
+ tmpReg = tmpReg | BIT15;
+ }
+ tmpReg = (tmpReg & 0xFFF0FFFF) | (BB_offset << 16);
+ }
+#endif
+
+ ODM_SetRFReg(pDM_Odm, path, RF_IPA_A, bMaskDWord, 0x8992e);
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", PHY_QueryRFReg(pAdapter, path, RF_IPA_A, bMaskDWord)));
+ ODM_SetRFReg(pDM_Odm, path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]);
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x0 %x\n", PHY_QueryRFReg(pAdapter, path, RF_AC, bMaskDWord)));
+ ODM_SetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord, tmpReg);
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord)));
+#else
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", ODM_GetRFReg(pDM_Odm, path, RF_IPA_A, bMaskDWord)));
+ ODM_SetRFReg(pDM_Odm, path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]);
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x0 %x\n", ODM_GetRFReg(pDM_Odm, path, RF_AC, bMaskDWord)));
+ ODM_SetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord, tmpReg);
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord)));
+#endif
+
+ // PA11+PAD01111, one shot
+ i = 0;
+ do
+ {
+ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80000000);
+ {
+ ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[0]);
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord)));
+ ODM_delay_ms(3);
+ ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[1]);
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord)));
+
+ ODM_delay_ms(20);
+ }
+ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
+
+ if(path == RF_PATH_A)
+ tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0x03E00000);
+ else
+ tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0xF8000000);
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xbd8[25:21] %x\n", tmpReg));
+
+
+ i++;
+ }
+ while(tmpReg > apkbound && i < 4);
+
+ APK_result[path][index] = tmpReg;
+ }
+ }
+
+ //reload MAC default value
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ _PHY_ReloadMACRegisters(pAdapter, MAC_REG, MAC_backup);
+#else
+ _PHY_ReloadMACRegisters(pDM_Odm, MAC_REG, MAC_backup);
+#endif
+
+ //reload BB default value
+ for(index = 0; index < APK_BB_REG_NUM ; index++)
+ {
+
+ if(index == 0) //skip
+ continue;
+ ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]);
+ }
+
+ //reload AFE default value
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ _PHY_ReloadADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
+#else
+ _PHY_ReloadADDARegisters(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
+#endif
+
+ //reload RF path default value
+ for(path = 0; path < pathbound; path++)
+ {
+ ODM_SetRFReg(pDM_Odm, path, 0xd, bMaskDWord, regD[path]);
+ if(path == RF_PATH_B)
+ {
+ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f);
+ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101);
+ }
+
+ //note no index == 0
+ if (APK_result[path][1] > 6)
+ APK_result[path][1] = 6;
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1]));
+ }
+
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\n"));
+
+
+ for(path = 0; path < pathbound; path++)
+ {
+ ODM_SetRFReg(pDM_Odm, path, 0x3, bMaskDWord,
+ ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1]));
+ if(path == RF_PATH_A)
+ ODM_SetRFReg(pDM_Odm, path, 0x4, bMaskDWord,
+ ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05));
+ else
+ ODM_SetRFReg(pDM_Odm, path, 0x4, bMaskDWord,
+ ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05));
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ if(!IS_HARDWARE_TYPE_8723A(pAdapter))
+ ODM_SetRFReg(pDM_Odm, path, RF_BS_PA_APSET_G9_G11, bMaskDWord,
+ ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08));
+#endif
+ }
+
+ pDM_Odm->RFCalibrateInfo.bAPKdone = TRUE;
+
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_APCalibrate_8188E()\n"));
+}
+
+
+
+#define DP_BB_REG_NUM 7
+#define DP_RF_REG_NUM 1
+#define DP_RETRY_LIMIT 10
+#define DP_PATH_NUM 2
+#define DP_DPK_NUM 3
+#define DP_DPK_VALUE_NUM 2
+
+
+
+
+
+VOID
+PHY_IQCalibrate_8188E(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ IN PDM_ODM_T pDM_Odm,
+#else
+ IN PADAPTER pAdapter,
+#endif
+ IN BOOLEAN bReCovery
+ )
+{
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+
+ #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
+ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
+ #else // (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
+ #endif
+
+ #if (MP_DRIVER == 1)
+ #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
+ PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx);
+ #else// (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
+ #endif
+ #endif//(MP_DRIVER == 1)
+#endif
+
+ s4Byte result[4][8]; //last is final result
+ u1Byte i, final_candidate, Indexforchannel;
+ u1Byte channelToIQK = 7;
+ BOOLEAN bPathAOK, bPathBOK;
+ s4Byte RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0;
+ BOOLEAN is12simular, is13simular, is23simular;
+ BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE;
+ u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
+ rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance,
+ rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable,
+ rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance,
+ rOFDM0_XCTxAFE, rOFDM0_XDTxAFE,
+ rOFDM0_RxIQExtAnta};
+ BOOLEAN is2T;
+
+ is2T = (pDM_Odm->RFType == ODM_2T2R)?TRUE:FALSE;
+#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE) )
+ if (ODM_CheckPowerStatus(pAdapter) == FALSE)
+ return;
+#else
+ prtl8192cd_priv priv = pDM_Odm->priv;
+
+#ifdef MP_TEST
+ if(priv->pshare->rf_ft_var.mp_specific)
+ {
+ if((OPMODE & WIFI_MP_CTX_PACKET) || (OPMODE & WIFI_MP_CTX_ST))
+ return;
+ }
+#endif
+
+ if(priv->pshare->IQK_88E_done)
+ bReCovery= 1;
+ priv->pshare->IQK_88E_done = 1;
+
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION))
+ {
+ return;
+ }
+#endif
+
+#if MP_DRIVER == 1
+if (*(pDM_Odm->mp_mode) == 1)
+{
+ bStartContTx = pMptCtx->bStartContTx;
+ bSingleTone = pMptCtx->bSingleTone;
+ bCarrierSuppression = pMptCtx->bCarrierSuppression;
+}
+#endif
+
+ // 20120213<Kordan> Turn on when continuous Tx to pass lab testing. (required by Edlu)
+ if(bSingleTone || bCarrierSuppression)
+ return;
+
+#if DISABLE_BB_RF
+ return;
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP))
+ if(bReCovery)
+#else//for ODM_MP
+ if(bReCovery && (!pAdapter->bInHctTest)) //YJ,add for PowerTest,120405
+#endif
+ {
+ ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("PHY_IQCalibrate_8188E: Return due to bReCovery!\n"));
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ _PHY_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9);
+#else
+ _PHY_ReloadADDARegisters(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9);
+#endif
+ return;
+ }
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Start!!!\n"));
+
+#if 0//Suggested by Edlu,120413
+
+ // IQK on channel 7, should switch back when completed.
+ //originChannel = pHalData->CurrentChannel;
+ originChannel = *(pDM_Odm->pChannel);
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_MP)
+ pAdapter->HalFunc.SwChnlByTimerHandler(pAdapter, channelToIQK);
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ pAdapter->HalFunc.set_channel_handler(pAdapter, channelToIQK);
+#endif
+
+#endif
+
+ for(i = 0; i < 8; i++)
+ {
+ result[0][i] = 0;
+ result[1][i] = 0;
+ result[2][i] = 0;
+ if((i==0) ||(i==2) || (i==4) || (i==6))
+ result[3][i] = 0x100;
+ else
+ result[3][i] = 0;
+ }
+ final_candidate = 0xff;
+ bPathAOK = FALSE;
+ bPathBOK = FALSE;
+ is12simular = FALSE;
+ is23simular = FALSE;
+ is13simular = FALSE;
+
+
+ //ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK !!!interface %d currentband %d ishardwareD %d \n", pDM_Odm->interfaceIndex, pHalData->CurrentBandType92D, IS_HARDWARE_TYPE_8192D(pAdapter)));
+// RT_TRACE(COMP_INIT,DBG_LOUD,("Acquire Mutex in IQCalibrate \n"));
+ for (i=0; i<3; i++)
+ {
+
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ phy_IQCalibrate_8188E(pAdapter, result, i, is2T);
+#else
+ phy_IQCalibrate_8188E(pDM_Odm, result, i, is2T);
+#endif
+
+
+ if(i == 1)
+ {
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ is12simular = phy_SimularityCompare_8188E(pAdapter, result, 0, 1);
+#else
+ is12simular = phy_SimularityCompare_8188E(pDM_Odm, result, 0, 1);
+#endif
+ if(is12simular)
+ {
+ final_candidate = 0;
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is12simular final_candidate is %x\n",final_candidate));
+ break;
+ }
+ }
+
+ if(i == 2)
+ {
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ is13simular = phy_SimularityCompare_8188E(pAdapter, result, 0, 2);
+#else
+ is13simular = phy_SimularityCompare_8188E(pDM_Odm, result, 0, 2);
+#endif
+ if(is13simular)
+ {
+ final_candidate = 0;
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is13simular final_candidate is %x\n",final_candidate));
+
+ break;
+ }
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ is23simular = phy_SimularityCompare_8188E(pAdapter, result, 1, 2);
+#else
+ is23simular = phy_SimularityCompare_8188E(pDM_Odm, result, 1, 2);
+#endif
+ if(is23simular)
+ {
+ final_candidate = 1;
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is23simular final_candidate is %x\n",final_candidate));
+ }
+ else
+ {
+ /*
+ for(i = 0; i < 8; i++)
+ RegTmp += result[3][i];
+
+ if(RegTmp != 0)
+ final_candidate = 3;
+ else
+ final_candidate = 0xFF;
+ */
+ final_candidate = 3;
+ }
+ }
+ }
+// RT_TRACE(COMP_INIT,DBG_LOUD,("Release Mutex in IQCalibrate \n"));
+
+ for (i=0; i<4; i++)
+ {
+ RegE94 = result[i][0];
+ RegE9C = result[i][1];
+ RegEA4 = result[i][2];
+ RegEAC = result[i][3];
+ RegEB4 = result[i][4];
+ RegEBC = result[i][5];
+ RegEC4 = result[i][6];
+ RegECC = result[i][7];
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC));
+ }
+
+ if(final_candidate != 0xff)
+ {
+ pDM_Odm->RFCalibrateInfo.RegE94 = RegE94 = result[final_candidate][0];
+ pDM_Odm->RFCalibrateInfo.RegE9C = RegE9C = result[final_candidate][1];
+ RegEA4 = result[final_candidate][2];
+ RegEAC = result[final_candidate][3];
+ pDM_Odm->RFCalibrateInfo.RegEB4 = RegEB4 = result[final_candidate][4];
+ pDM_Odm->RFCalibrateInfo.RegEBC = RegEBC = result[final_candidate][5];
+ RegEC4 = result[final_candidate][6];
+ RegECC = result[final_candidate][7];
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: final_candidate is %x\n",final_candidate));
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC));
+ bPathAOK = bPathBOK = TRUE;
+ }
+ else
+ {
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: FAIL use default value\n"));
+
+ pDM_Odm->RFCalibrateInfo.RegE94 = pDM_Odm->RFCalibrateInfo.RegEB4 = 0x100; //X default value
+ pDM_Odm->RFCalibrateInfo.RegE9C = pDM_Odm->RFCalibrateInfo.RegEBC = 0x0; //Y default value
+ }
+
+ if((RegE94 != 0)/*&&(RegEA4 != 0)*/)
+ {
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ _PHY_PathAFillIQKMatrix(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0));
+#else
+ _PHY_PathAFillIQKMatrix(pDM_Odm, bPathAOK, result, final_candidate, (RegEA4 == 0));
+#endif
+ }
+
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ if (is2T)
+ {
+ if((RegEB4 != 0)/*&&(RegEC4 != 0)*/)
+ {
+ _PHY_PathBFillIQKMatrix(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0));
+ }
+ }
+#endif
+
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ Indexforchannel = ODM_GetRightChnlPlaceforIQK(pHalData->CurrentChannel);
+#else
+ Indexforchannel = 0;
+#endif
+
+//To Fix BSOD when final_candidate is 0xff
+//by sherry 20120321
+ if(final_candidate < 4)
+ {
+ for(i = 0; i < IQK_Matrix_REG_NUM; i++)
+ pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][i] = result[final_candidate][i];
+ pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].bIQKDone = TRUE;
+ }
+ //RTPRINT(FINIT, INIT_IQK, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel));
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel));
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+
+ _PHY_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9);
+#else
+ _PHY_SaveADDARegisters(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, IQK_BB_REG_NUM);
+#endif
+
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK finished\n"));
+#if 0 //Suggested by Edlu,120413
+
+ #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
+ pAdapter->HalFunc.SwChnlByTimerHandler(pAdapter, originChannel);
+ #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ pAdapter->HalFunc.set_channel_handler(pAdapter, originChannel);
+ #endif
+
+#endif
+
+}
+
+
+VOID
+PHY_LCCalibrate_8188E(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ IN PDM_ODM_T pDM_Odm
+#else
+ IN PADAPTER pAdapter
+#endif
+ )
+{
+ BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE;
+ u4Byte timeout = 2000, timecount = 0;
+
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+
+ #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
+ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
+ #else // (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
+ #endif
+
+ #if (MP_DRIVER == 1)
+ #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
+ PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx);
+ #else// (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
+ #endif
+ #endif//(MP_DRIVER == 1)
+#endif
+
+
+
+
+#if MP_DRIVER == 1
+if (*(pDM_Odm->mp_mode) == 1)
+{
+ bStartContTx = pMptCtx->bStartContTx;
+ bSingleTone = pMptCtx->bSingleTone;
+ bCarrierSuppression = pMptCtx->bCarrierSuppression;
+}
+#endif
+
+
+#if DISABLE_BB_RF
+ return;
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION))
+ {
+ return;
+ }
+#endif
+ // 20120213<Kordan> Turn on when continuous Tx to pass lab testing. (required by Edlu)
+ if(bSingleTone || bCarrierSuppression)
+ return;
+
+ while(*(pDM_Odm->pbScanInProcess) && timecount < timeout)
+ {
+ ODM_delay_ms(50);
+ timecount += 50;
+ }
+
+ pDM_Odm->RFCalibrateInfo.bLCKInProgress = TRUE;
+
+ //ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Start!!!interface %d currentband %x delay %d ms\n", pDM_Odm->interfaceIndex, pHalData->CurrentBandType92D, timecount));
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+
+ if(pDM_Odm->RFType == ODM_2T2R)
+ {
+ phy_LCCalibrate_8188E(pAdapter, TRUE);
+ }
+ else
+#endif
+ {
+ // For 88C 1T1R
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ phy_LCCalibrate_8188E(pAdapter, FALSE);
+#else
+ phy_LCCalibrate_8188E(pDM_Odm, FALSE);
+#endif
+ }
+
+ pDM_Odm->RFCalibrateInfo.bLCKInProgress = FALSE;
+
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Finish!!!interface %d\n", pDM_Odm->InterfaceIndex));
+
+}
+
+VOID
+PHY_APCalibrate_8188E(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ IN PDM_ODM_T pDM_Odm,
+#else
+ IN PADAPTER pAdapter,
+#endif
+ IN s1Byte delta
+ )
+{
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
+ #endif
+ #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
+ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
+ #endif
+#endif
+#if DISABLE_BB_RF
+ return;
+#endif
+
+ return;
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION))
+ {
+ return;
+ }
+#endif
+
+#if FOR_BRAZIL_PRETEST != 1
+ if(pDM_Odm->RFCalibrateInfo.bAPKdone)
+#endif
+ return;
+
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ if(pDM_Odm->RFType == ODM_2T2R){
+ phy_APCalibrate_8188E(pAdapter, delta, TRUE);
+ }
+ else
+#endif
+ {
+ // For 88C 1T1R
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ phy_APCalibrate_8188E(pAdapter, delta, FALSE);
+#else
+ phy_APCalibrate_8188E(pDM_Odm, delta, FALSE);
+#endif
+ }
+}
+VOID phy_SetRFPathSwitch_8188E(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ IN PDM_ODM_T pDM_Odm,
+#else
+ IN PADAPTER pAdapter,
+#endif
+ IN BOOLEAN bMain,
+ IN BOOLEAN is2T
+ )
+{
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
+ #elif (DM_ODM_SUPPORT_TYPE == ODM_MP)
+ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
+ #endif
+
+ #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
+ if(!pAdapter->bHWInitReady)
+ #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ if(pAdapter->hw_init_completed == _FALSE)
+ #endif
+ {
+ u1Byte u1bTmp;
+ u1bTmp = ODM_Read1Byte(pDM_Odm, REG_LEDCFG2) | BIT7;
+ ODM_Write1Byte(pDM_Odm, REG_LEDCFG2, u1bTmp);
+ //ODM_SetBBReg(pDM_Odm, REG_LEDCFG0, BIT23, 0x01);
+ ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFParameter, BIT13, 0x01);
+ }
+
+#endif
+
+ if(is2T) //92C
+ {
+ if(bMain)
+ ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x1); //92C_Path_A
+ else
+ ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x2); //BT
+ }
+ else //88C
+ {
+
+ if(bMain)
+ ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x2); //Main
+ else
+ ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x1); //Aux
+ }
+}
+VOID PHY_SetRFPathSwitch_8188E(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ IN PDM_ODM_T pDM_Odm,
+#else
+ IN PADAPTER pAdapter,
+#endif
+ IN BOOLEAN bMain
+ )
+{
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
+ #endif
+ #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
+ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
+ #endif
+#endif
+
+
+#if DISABLE_BB_RF
+ return;
+#endif
+
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ if(pDM_Odm->RFType == ODM_2T2R)
+ {
+ phy_SetRFPathSwitch_8188E(pAdapter, bMain, TRUE);
+ }
+ else
+#endif
+ {
+ // For 88C 1T1R
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ phy_SetRFPathSwitch_8188E(pAdapter, bMain, FALSE);
+#else
+ phy_SetRFPathSwitch_8188E(pDM_Odm, bMain, FALSE);
+#endif
+ }
+}
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_MP)
+//digital predistortion
+VOID
+phy_DigitalPredistortion(
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ IN PADAPTER pAdapter,
+#else
+ IN PDM_ODM_T pDM_Odm,
+#endif
+ IN BOOLEAN is2T
+ )
+{
+#if ( RT_PLATFORM == PLATFORM_WINDOWS)
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
+ #endif
+ #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
+ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
+ #endif
+#endif
+
+ u4Byte tmpReg, tmpReg2, index, i;
+ u1Byte path, pathbound = PATH_NUM;
+ u4Byte AFE_backup[IQK_ADDA_REG_NUM];
+ u4Byte AFE_REG[IQK_ADDA_REG_NUM] = {
+ rFPGA0_XCD_SwitchControl, rBlue_Tooth,
+ rRx_Wait_CCA, rTx_CCK_RFON,
+ rTx_CCK_BBON, rTx_OFDM_RFON,
+ rTx_OFDM_BBON, rTx_To_Rx,
+ rTx_To_Tx, rRx_CCK,
+ rRx_OFDM, rRx_Wait_RIFS,
+ rRx_TO_Rx, rStandby,
+ rSleep, rPMPD_ANAEN };
+
+ u4Byte BB_backup[DP_BB_REG_NUM];
+ u4Byte BB_REG[DP_BB_REG_NUM] = {
+ rOFDM0_TRxPathEnable, rFPGA0_RFMOD,
+ rOFDM0_TRMuxPar, rFPGA0_XCD_RFInterfaceSW,
+ rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE,
+ rFPGA0_XB_RFInterfaceOE};
+ u4Byte BB_settings[DP_BB_REG_NUM] = {
+ 0x00a05430, 0x02040000, 0x000800e4, 0x22208000,
+ 0x0, 0x0, 0x0};
+
+ u4Byte RF_backup[DP_PATH_NUM][DP_RF_REG_NUM];
+ u4Byte RF_REG[DP_RF_REG_NUM] = {
+ RF_TXBIAS_A};
+
+ u4Byte MAC_backup[IQK_MAC_REG_NUM];
+ u4Byte MAC_REG[IQK_MAC_REG_NUM] = {
+ REG_TXPAUSE, REG_BCN_CTRL,
+ REG_BCN_CTRL_1, REG_GPIO_MUXCFG};
+
+ u4Byte Tx_AGC[DP_DPK_NUM][DP_DPK_VALUE_NUM] = {
+ {0x1e1e1e1e, 0x03901e1e},
+ {0x18181818, 0x03901818},
+ {0x0e0e0e0e, 0x03900e0e}
+ };
+
+ u4Byte AFE_on_off[PATH_NUM] = {
+ 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on
+
+ u1Byte RetryCount = 0;
+
+
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_DigitalPredistortion()\n"));
+
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_DigitalPredistortion for %s %s\n", (is2T ? "2T2R" : "1T1R")));
+
+ //save BB default value
+ for(index=0; index<DP_BB_REG_NUM; index++)
+ BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord);
+
+ //save MAC default value
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ _PHY_SaveMACRegisters(pAdapter, BB_REG, MAC_backup);
+#else
+ _PHY_SaveMACRegisters(pDM_Odm, BB_REG, MAC_backup);
+#endif
+
+ //save RF default value
+ for(path=0; path<DP_PATH_NUM; path++)
+ {
+ for(index=0; index<DP_RF_REG_NUM; index++)
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ RF_backup[path][index] = PHY_QueryRFReg(pAdapter, path, RF_REG[index], bMaskDWord);
+#else
+ RF_backup[path][index] = ODM_GetRFReg(pAdapter, path, RF_REG[index], bMaskDWord);
+#endif
+ }
+
+ //save AFE default value
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ _PHY_SaveADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
+#else
+ RF_backup[path][index] = ODM_GetRFReg(pAdapter, path, RF_REG[index], bMaskDWord);
+#endif
+
+ //Path A/B AFE all on
+ for(index = 0; index < IQK_ADDA_REG_NUM ; index++)
+ ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, 0x6fdb25a4);
+
+ //BB register setting
+ for(index = 0; index < DP_BB_REG_NUM; index++)
+ {
+ if(index < 4)
+ ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_settings[index]);
+ else if (index == 4)
+ ODM_SetBBReg(pDM_Odm,BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26);
+ else
+ ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x00);
+ }
+
+ //MAC register setting
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ _PHY_MACSettingCalibration(pAdapter, MAC_REG, MAC_backup);
+#else
+ _PHY_MACSettingCalibration(pDM_Odm, MAC_REG, MAC_backup);
+#endif
+
+ //PAGE-E IQC setting
+ ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);
+ ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);
+ ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00);
+ ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00);
+
+ //path_A DPK
+ //Path B to standby mode
+ ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMaskDWord, 0x10000);
+
+ // PA gain = 11 & PAD1 => tx_agc 1f ~11
+ // PA gain = 11 & PAD2 => tx_agc 10~0e
+ // PA gain = 01 => tx_agc 0b~0d
+ // PA gain = 00 => tx_agc 0a~00
+ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000);
+ ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f);
+ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
+
+ //do inner loopback DPK 3 times
+ for(i = 0; i < 3; i++)
+ {
+ //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07
+ for(index = 0; index < 3; index++)
+ ODM_SetBBReg(pDM_Odm, 0xe00+index*4, bMaskDWord, Tx_AGC[i][0]);
+ ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, Tx_AGC[i][1]);
+ for(index = 0; index < 4; index++)
+ ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, Tx_AGC[i][0]);
+
+ // PAGE_B for Path-A inner loopback DPK setting
+ ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02097098);
+ ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84);
+ ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87);
+ ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000);
+
+ //----send one shot signal----//
+ // Path A
+ ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x80047788);
+ ODM_delay_ms(1);
+ ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x00047788);
+ ODM_delay_ms(50);
+ }
+
+ //PA gain = 11 => tx_agc = 1a
+ for(index = 0; index < 3; index++)
+ ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, 0x34343434);
+ ODM_SetBBReg(pDM_Odm,0xe08+index*4, bMaskDWord, 0x03903434);
+ for(index = 0; index < 4; index++)
+ ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, 0x34343434);
+
+ //====================================
+ // PAGE_B for Path-A DPK setting
+ //====================================
+ // open inner loopback @ b00[19]:10 od 0xb00 0x01097018
+ ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02017098);
+ ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84);
+ ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87);
+ ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000);
+
+ //rf_lpbk_setup
+ //1.rf 00:5205a, rf 0d:0e52c
+ ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x0c, bMaskDWord, 0x8992b);
+ ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x0d, bMaskDWord, 0x0e52c);
+ ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x00, bMaskDWord, 0x5205a );
+
+ //----send one shot signal----//
+ // Path A
+ ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0);
+ ODM_delay_ms(1);
+ ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0);
+ ODM_delay_ms(50);
+
+ while(RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathAOK)
+ {
+ //----read back measurement results----//
+ ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c297018);
+ tmpReg = ODM_GetBBReg(pDM_Odm, 0xbe0, bMaskDWord);
+ ODM_delay_ms(10);
+ ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c29701f);
+ tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbe8, bMaskDWord);
+ ODM_delay_ms(10);
+
+ tmpReg = (tmpReg & bMaskHWord) >> 16;
+ tmpReg2 = (tmpReg2 & bMaskHWord) >> 16;
+ if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff )
+ {
+ ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02017098);
+
+ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80000000);
+ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
+ ODM_delay_ms(1);
+ ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0);
+ ODM_delay_ms(1);
+ ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0);
+ ODM_delay_ms(50);
+ RetryCount++;
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK RetryCount %d 0xbe0[31:16] %x 0xbe8[31:16] %x\n", RetryCount, tmpReg, tmpReg2));
+ }
+ else
+ {
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK Sucess\n"));
+ pDM_Odm->RFCalibrateInfo.bDPPathAOK = TRUE;
+ break;
+ }
+ }
+ RetryCount = 0;
+
+ //DPP path A
+ if(pDM_Odm->RFCalibrateInfo.bDPPathAOK)
+ {
+ // DP settings
+ ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x01017098);
+ ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x776d9f84);
+ ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87);
+ ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000);
+ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000);
+
+ for(i=rPdp_AntA; i<=0xb3c; i+=4)
+ {
+ ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000);
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A ofsset = 0x%x\n", i));
+ }
+
+ //pwsf
+ ODM_SetBBReg(pDM_Odm, 0xb40, bMaskDWord, 0x40404040);
+ ODM_SetBBReg(pDM_Odm, 0xb44, bMaskDWord, 0x28324040);
+ ODM_SetBBReg(pDM_Odm, 0xb48, bMaskDWord, 0x10141920);
+
+ for(i=0xb4c; i<=0xb5c; i+=4)
+ {
+ ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c);
+ }
+
+ //TX_AGC boundary
+ ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f);
+ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
+ }
+ else
+ {
+ ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x00000000);
+ ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x00000000);
+ }
+
+ //DPK path B
+ if(is2T)
+ {
+ //Path A to standby mode
+ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_AC, bMaskDWord, 0x10000);
+
+ // LUTs => tx_agc
+ // PA gain = 11 & PAD1, => tx_agc 1f ~11
+ // PA gain = 11 & PAD2, => tx_agc 10 ~0e
+ // PA gain = 01 => tx_agc 0b ~0d
+ // PA gain = 00 => tx_agc 0a ~00
+ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000);
+ ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f);
+ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
+
+ //do inner loopback DPK 3 times
+ for(i = 0; i < 3; i++)
+ {
+ //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07
+ for(index = 0; index < 4; index++)
+ ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, Tx_AGC[i][0]);
+ for(index = 0; index < 2; index++)
+ ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, Tx_AGC[i][0]);
+ for(index = 0; index < 2; index++)
+ ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, Tx_AGC[i][0]);
+
+ // PAGE_B for Path-A inner loopback DPK setting
+ ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02097098);
+ ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84);
+ ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87);
+ ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000);
+
+ //----send one shot signal----//
+ // Path B
+ ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntB, bMaskDWord, 0x80047788);
+ ODM_delay_ms(1);
+ ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x00047788);
+ ODM_delay_ms(50);
+ }
+
+ // PA gain = 11 => tx_agc = 1a
+ for(index = 0; index < 4; index++)
+ ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, 0x34343434);
+ for(index = 0; index < 2; index++)
+ ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, 0x34343434);
+ for(index = 0; index < 2; index++)
+ ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, 0x34343434);
+
+ // PAGE_B for Path-B DPK setting
+ ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098);
+ ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84);
+ ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87);
+ ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000);
+
+ // RF lpbk switches on
+ ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x0101000f);
+ ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x01120103);
+
+ //Path-B RF lpbk
+ ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x0c, bMaskDWord, 0x8992b);
+ ODM_SetRFReg(pDM_Odm, RF_PATH_B, 0x0d, bMaskDWord, 0x0e52c);
+ ODM_SetRFReg(pDM_Odm, RF_PATH_B, RF_AC, bMaskDWord, 0x5205a);
+
+ //----send one shot signal----//
+ ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0);
+ ODM_delay_ms(1);
+ ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0);
+ ODM_delay_ms(50);
+
+ while(RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathBOK)
+ {
+ //----read back measurement results----//
+ ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c297018);
+ tmpReg = ODM_GetBBReg(pDM_Odm, 0xbf0, bMaskDWord);
+ ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c29701f);
+ tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbf8, bMaskDWord);
+
+ tmpReg = (tmpReg & bMaskHWord) >> 16;
+ tmpReg2 = (tmpReg2 & bMaskHWord) >> 16;
+
+ if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff)
+ {
+ ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098);
+
+ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80000000);
+ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
+ ODM_delay_ms(1);
+ ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0);
+ ODM_delay_ms(1);
+ ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0);
+ ODM_delay_ms(50);
+ RetryCount++;
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK RetryCount %d 0xbf0[31:16] %x, 0xbf8[31:16] %x\n", RetryCount , tmpReg, tmpReg2));
+ }
+ else
+ {
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK Success\n"));
+ pDM_Odm->RFCalibrateInfo.bDPPathBOK = TRUE;
+ break;
+ }
+ }
+
+ //DPP path B
+ if(pDM_Odm->RFCalibrateInfo.bDPPathBOK)
+ {
+ // DP setting
+ // LUT by SRAM
+ ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x01017098);
+ ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x776d9f84);
+ ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87);
+ ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000);
+
+ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000);
+ for(i=0xb60; i<=0xb9c; i+=4)
+ {
+ ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000);
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B ofsset = 0x%x\n", i));
+ }
+
+ // PWSF
+ ODM_SetBBReg(pDM_Odm, 0xba0, bMaskDWord, 0x40404040);
+ ODM_SetBBReg(pDM_Odm, 0xba4, bMaskDWord, 0x28324050);
+ ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x0c141920);
+
+ for(i=0xbac; i<=0xbbc; i+=4)
+ {
+ ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c);
+ }
+
+ // tx_agc boundary
+ ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f);
+ ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
+
+ }
+ else
+ {
+ ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x00000000);
+ ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x00000000);
+ }
+ }
+
+ //reload BB default value
+ for(index=0; index<DP_BB_REG_NUM; index++)
+ ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]);
+
+ //reload RF default value
+ for(path = 0; path<DP_PATH_NUM; path++)
+ {
+ for( i = 0 ; i < DP_RF_REG_NUM ; i++){
+ ODM_SetRFReg(pDM_Odm, path, RF_REG[i], bMaskDWord, RF_backup[path][i]);
+ }
+ }
+ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); //standby mode
+ ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101); //RF lpbk switches off
+
+ //reload AFE default value
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ _PHY_ReloadADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
+
+ //reload MAC default value
+ _PHY_ReloadMACRegisters(pAdapter, MAC_REG, MAC_backup);
+#else
+ _PHY_ReloadADDARegisters(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
+
+ //reload MAC default value
+ _PHY_ReloadMACRegisters(pDM_Odm, MAC_REG, MAC_backup);
+#endif
+
+ pDM_Odm->RFCalibrateInfo.bDPdone = TRUE;
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_DigitalPredistortion()\n"));
+#endif
+}
+
+VOID
+PHY_DigitalPredistortion_8188E(
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ IN PADAPTER pAdapter
+#else
+ IN PDM_ODM_T pDM_Odm
+#endif
+ )
+{
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
+ #endif
+ #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
+ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
+ #endif
+#endif
+#if DISABLE_BB_RF
+ return;
+#endif
+
+ return;
+
+ if(pDM_Odm->RFCalibrateInfo.bDPdone)
+ return;
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+
+ if(pDM_Odm->RFType == ODM_2T2R){
+ phy_DigitalPredistortion(pAdapter, TRUE);
+ }
+ else
+#endif
+ {
+ // For 88C 1T1R
+ phy_DigitalPredistortion(pAdapter, FALSE);
+ }
+}
+
+
+
+//return value TRUE => Main; FALSE => Aux
+
+BOOLEAN phy_QueryRFPathSwitch_8188E(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ IN PDM_ODM_T pDM_Odm,
+#else
+ IN PADAPTER pAdapter,
+#endif
+ IN BOOLEAN is2T
+ )
+{
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
+ #endif
+ #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
+ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
+ #endif
+#endif
+ if(!pAdapter->bHWInitReady)
+ {
+ u1Byte u1bTmp;
+ u1bTmp = ODM_Read1Byte(pDM_Odm, REG_LEDCFG2) | BIT7;
+ ODM_Write1Byte(pDM_Odm, REG_LEDCFG2, u1bTmp);
+ //ODM_SetBBReg(pDM_Odm, REG_LEDCFG0, BIT23, 0x01);
+ ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFParameter, BIT13, 0x01);
+ }
+
+ if(is2T) //
+ {
+ if(ODM_GetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6) == 0x01)
+ return TRUE;
+ else
+ return FALSE;
+ }
+ else
+ {
+ if(ODM_GetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9) == 0x02)
+ return TRUE;
+ else
+ return FALSE;
+ }
+}
+
+
+
+//return value TRUE => Main; FALSE => Aux
+BOOLEAN PHY_QueryRFPathSwitch_8188E(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ IN PDM_ODM_T pDM_Odm
+#else
+ IN PADAPTER pAdapter
+#endif
+ )
+{
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+ #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
+ #endif
+ #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
+ PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
+ #endif
+#endif
+
+
+#if DISABLE_BB_RF
+ return TRUE;
+#endif
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+
+ //if(IS_92C_SERIAL( pHalData->VersionID)){
+ if(pDM_Odm->RFType == ODM_2T2R){
+ return phy_QueryRFPathSwitch_8188E(pAdapter, TRUE);
+ }
+ else
+#endif
+ {
+ // For 88C 1T1R
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ return phy_QueryRFPathSwitch_8188E(pAdapter, FALSE);
+#else
+ return phy_QueryRFPathSwitch_8188E(pDM_Odm, FALSE);
+#endif
+ }
+}
+#endif
diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalPhyRf_8188e.h b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalPhyRf_8188e.h new file mode 100755 index 00000000..6035ca50 --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/HalPhyRf_8188e.h @@ -0,0 +1,135 @@ +/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+#ifndef __HAL_PHY_RF_8188E_H__
+#define __HAL_PHY_RF_8188E_H__
+
+/*--------------------------Define Parameters-------------------------------*/
+#define IQK_DELAY_TIME_88E 10 //ms
+#define index_mapping_NUM_88E 15
+#define AVG_THERMAL_NUM_88E 4
+
+
+VOID
+ODM_TxPwrTrackAdjust88E(
+ PDM_ODM_T pDM_Odm,
+ u1Byte Type, // 0 = OFDM, 1 = CCK
+ pu1Byte pDirection, // 1 = +(increase) 2 = -(decrease)
+ pu4Byte pOutWriteVal // Tx tracking CCK/OFDM BB swing index adjust
+ );
+
+
+VOID
+odm_TXPowerTrackingCallback_ThermalMeter_8188E(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ IN PDM_ODM_T pDM_Odm
+#else
+ IN PADAPTER Adapter
+#endif
+ );
+
+
+//1 7. IQK
+
+void
+PHY_IQCalibrate_8188E(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ IN PDM_ODM_T pDM_Odm,
+#else
+ IN PADAPTER Adapter,
+#endif
+ IN BOOLEAN bReCovery);
+
+
+//
+// LC calibrate
+//
+void
+PHY_LCCalibrate_8188E(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ IN PDM_ODM_T pDM_Odm
+#else
+ IN PADAPTER pAdapter
+#endif
+);
+
+//
+// AP calibrate
+//
+void
+PHY_APCalibrate_8188E(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ IN PDM_ODM_T pDM_Odm,
+#else
+ IN PADAPTER pAdapter,
+#endif
+ IN s1Byte delta);
+void
+PHY_DigitalPredistortion_8188E( IN PADAPTER pAdapter);
+
+
+VOID
+_PHY_SaveADDARegisters(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ IN PDM_ODM_T pDM_Odm,
+#else
+ IN PADAPTER pAdapter,
+#endif
+ IN pu4Byte ADDAReg,
+ IN pu4Byte ADDABackup,
+ IN u4Byte RegisterNum
+ );
+
+VOID
+_PHY_PathADDAOn(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ IN PDM_ODM_T pDM_Odm,
+#else
+ IN PADAPTER pAdapter,
+#endif
+ IN pu4Byte ADDAReg,
+ IN BOOLEAN isPathAOn,
+ IN BOOLEAN is2T
+ );
+
+VOID
+_PHY_MACSettingCalibration(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ IN PDM_ODM_T pDM_Odm,
+#else
+ IN PADAPTER pAdapter,
+#endif
+ IN pu4Byte MACReg,
+ IN pu4Byte MACBackup
+ );
+
+
+VOID
+_PHY_PathAStandBy(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ IN PDM_ODM_T pDM_Odm
+#else
+ IN PADAPTER pAdapter
+#endif
+ );
+
+
+#endif // #ifndef __HAL_PHY_RF_8188E_H__
+
diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/odm_RTL8188E.c b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/odm_RTL8188E.c new file mode 100755 index 00000000..fb99d0ee --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/odm_RTL8188E.c @@ -0,0 +1,1290 @@ +/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+//============================================================
+// include files
+//============================================================
+
+#include "../odm_precomp.h"
+
+#if (RTL8188E_SUPPORT == 1)
+
+VOID
+ODM_DIG_LowerBound_88E(
+ IN PDM_ODM_T pDM_Odm
+)
+{
+ pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;
+
+ if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
+ {
+ pDM_DigTable->rx_gain_range_min = (u1Byte) pDM_DigTable->AntDiv_RSSI_max;
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_DIG_LowerBound_88E(): pDM_DigTable->AntDiv_RSSI_max=%d \n",pDM_DigTable->AntDiv_RSSI_max));
+ }
+ //If only one Entry connected
+
+
+
+}
+
+#if(defined(CONFIG_HW_ANTENNA_DIVERSITY))
+VOID
+odm_RX_HWAntDivInit(
+ IN PDM_ODM_T pDM_Odm
+)
+{
+ u4Byte value32;
+ PADAPTER Adapter = pDM_Odm->Adapter;
+ #if (MP_DRIVER == 1)
+ if (*(pDM_Odm->mp_mode) == 1)
+ {
+ pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;
+ ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); // disable HW AntDiv
+ ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); // 1:CG, 0:CS
+ return;
+ }
+ #endif
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_RX_HWAntDivInit() \n"));
+
+ //MAC Setting
+ value32 = ODM_GetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);
+ ODM_SetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output
+ //Pin Settings
+ ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW
+ ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW
+ ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT22, 1); //Regb2c[22]=1'b0 //disable CS/CG switch
+ ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); //Regb2c[31]=1'b1 //output at CG only
+ //OFDM Settings
+ ODM_SetBBReg(pDM_Odm, ODM_REG_ANTDIV_PARA1_11N , bMaskDWord, 0x000000a0);
+ //CCK Settings
+ ODM_SetBBReg(pDM_Odm, ODM_REG_BB_PWR_SAV4_11N , BIT7, 1); //Fix CCK PHY status report issue
+ ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA2_11N , BIT4, 1); //CCK complete HW AntDiv within 64 samples
+ ODM_UpdateRxIdleAnt_88E(pDM_Odm, MAIN_ANT);
+ ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , 0xFFFF, 0x0201); //antenna mapping table
+
+ //ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); //Enable HW AntDiv
+ //ODM_SetBBReg(pDM_Odm, 0xa00 , BIT15, 1); //Enable CCK AntDiv
+}
+
+VOID
+odm_TRX_HWAntDivInit(
+ IN PDM_ODM_T pDM_Odm
+)
+{
+ u4Byte value32;
+ PADAPTER Adapter = pDM_Odm->Adapter;
+
+ #if (MP_DRIVER == 1)
+ if (*(pDM_Odm->mp_mode) == 1)
+ {
+ pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;
+ ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); // disable HW AntDiv
+ ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, 0); //Default RX (0/1)
+ return;
+ }
+
+ #endif
+
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_TRX_HWAntDivInit() \n"));
+
+ //MAC Setting
+ value32 = ODM_GetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);
+ ODM_SetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output
+ //Pin Settings
+ ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW
+ ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW
+ ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT22, 0); //Regb2c[22]=1'b0 //disable CS/CG switch
+ ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); //Regb2c[31]=1'b1 //output at CG only
+ //OFDM Settings
+ ODM_SetBBReg(pDM_Odm, ODM_REG_ANTDIV_PARA1_11N , bMaskDWord, 0x000000a0);
+ //CCK Settings
+ ODM_SetBBReg(pDM_Odm, ODM_REG_BB_PWR_SAV4_11N , BIT7, 1); //Fix CCK PHY status report issue
+ ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA2_11N , BIT4, 1); //CCK complete HW AntDiv within 64 samples
+ //Tx Settings
+ ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 0); //Reg80c[21]=1'b0 //from TX Reg
+ ODM_UpdateRxIdleAnt_88E(pDM_Odm, MAIN_ANT);
+
+ //antenna mapping table
+ if(!pDM_Odm->bIsMPChip) //testchip
+ {
+ ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT10|BIT9|BIT8, 1); //Reg858[10:8]=3'b001
+ ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT13|BIT12|BIT11, 2); //Reg858[13:11]=3'b010
+ }
+ else //MPchip
+ ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , bMaskDWord, 0x0201); //Reg914=3'b010, Reg915=3'b001
+
+ //ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); //Enable HW AntDiv
+ //ODM_SetBBReg(pDM_Odm, 0xa00 , BIT15, 1); //Enable CCK AntDiv
+}
+
+VOID
+odm_FastAntTrainingInit(
+ IN PDM_ODM_T pDM_Odm
+)
+{
+ u4Byte value32, i;
+ pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
+ u4Byte AntCombination = 2;
+ PADAPTER Adapter = pDM_Odm->Adapter;
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_FastAntTrainingInit() \n"));
+
+#if (MP_DRIVER == 1)
+ if (*(pDM_Odm->mp_mode) == 1)
+ {
+ ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("pDM_Odm->AntDivType: %d\n", pDM_Odm->AntDivType));
+ return;
+ }
+#endif
+
+ for(i=0; i<6; i++)
+ {
+ pDM_FatTable->Bssid[i] = 0;
+ pDM_FatTable->antSumRSSI[i] = 0;
+ pDM_FatTable->antRSSIcnt[i] = 0;
+ pDM_FatTable->antAveRSSI[i] = 0;
+ }
+ pDM_FatTable->TrainIdx = 0;
+ pDM_FatTable->FAT_State = FAT_NORMAL_STATE;
+
+ //MAC Setting
+ value32 = ODM_GetMACReg(pDM_Odm, 0x4c, bMaskDWord);
+ ODM_SetMACReg(pDM_Odm, 0x4c, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output
+ value32 = ODM_GetMACReg(pDM_Odm, 0x7B4, bMaskDWord);
+ ODM_SetMACReg(pDM_Odm, 0x7b4, bMaskDWord, value32|(BIT16|BIT17)); //Reg7B4[16]=1 enable antenna training, Reg7B4[17]=1 enable A2 match
+ //value32 = PlatformEFIORead4Byte(Adapter, 0x7B4);
+ //PlatformEFIOWrite4Byte(Adapter, 0x7b4, value32|BIT18); //append MACID in reponse packet
+
+ //Match MAC ADDR
+ ODM_SetMACReg(pDM_Odm, 0x7b4, 0xFFFF, 0);
+ ODM_SetMACReg(pDM_Odm, 0x7b0, bMaskDWord, 0);
+
+ ODM_SetBBReg(pDM_Odm, 0x870 , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW
+ ODM_SetBBReg(pDM_Odm, 0x864 , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW
+ ODM_SetBBReg(pDM_Odm, 0xb2c , BIT22, 0); //Regb2c[22]=1'b0 //disable CS/CG switch
+ ODM_SetBBReg(pDM_Odm, 0xb2c , BIT31, 1); //Regb2c[31]=1'b1 //output at CG only
+ ODM_SetBBReg(pDM_Odm, 0xca4 , bMaskDWord, 0x000000a0);
+
+ //antenna mapping table
+ if(AntCombination == 2)
+ {
+ if(!pDM_Odm->bIsMPChip) //testchip
+ {
+ ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 1); //Reg858[10:8]=3'b001
+ ODM_SetBBReg(pDM_Odm, 0x858 , BIT13|BIT12|BIT11, 2); //Reg858[13:11]=3'b010
+ }
+ else //MPchip
+ {
+ ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 1);
+ ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 2);
+ }
+ }
+ else if(AntCombination == 7)
+ {
+ if(!pDM_Odm->bIsMPChip) //testchip
+ {
+ ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 0); //Reg858[10:8]=3'b000
+ ODM_SetBBReg(pDM_Odm, 0x858 , BIT13|BIT12|BIT11, 1); //Reg858[13:11]=3'b001
+ ODM_SetBBReg(pDM_Odm, 0x878 , BIT16, 0);
+ ODM_SetBBReg(pDM_Odm, 0x858 , BIT15|BIT14, 2); //(Reg878[0],Reg858[14:15])=3'b010
+ ODM_SetBBReg(pDM_Odm, 0x878 , BIT19|BIT18|BIT17, 3);//Reg878[3:1]=3b'011
+ ODM_SetBBReg(pDM_Odm, 0x878 , BIT22|BIT21|BIT20, 4);//Reg878[6:4]=3b'100
+ ODM_SetBBReg(pDM_Odm, 0x878 , BIT25|BIT24|BIT23, 5);//Reg878[9:7]=3b'101
+ ODM_SetBBReg(pDM_Odm, 0x878 , BIT28|BIT27|BIT26, 6);//Reg878[12:10]=3b'110
+ ODM_SetBBReg(pDM_Odm, 0x878 , BIT31|BIT30|BIT29, 7);//Reg878[15:13]=3b'111
+ }
+ else //MPchip
+ {
+ ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 0);
+ ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 1);
+ ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte2, 2);
+ ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte3, 3);
+ ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte0, 4);
+ ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte1, 5);
+ ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte2, 6);
+ ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte3, 7);
+ }
+ }
+
+ //Default Ant Setting when no fast training
+ ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 1); //Reg80c[21]=1'b1 //from TX Info
+ ODM_SetBBReg(pDM_Odm, 0x864 , BIT5|BIT4|BIT3, 0); //Default RX
+ ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, 1); //Optional RX
+ //ODM_SetBBReg(pDM_Odm, 0x860 , BIT14|BIT13|BIT12, 1); //Default TX
+
+ //Enter Traing state
+ ODM_SetBBReg(pDM_Odm, 0x864 , BIT2|BIT1|BIT0, (AntCombination-1)); //Reg864[2:0]=3'd6 //ant combination=reg864[2:0]+1
+ //ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 0); //RegC50[7]=1'b0 //disable HW AntDiv
+ //ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 0); //RegE08[16]=1'b0 //disable fast training
+ //ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 1); //RegE08[16]=1'b1 //enable fast training
+ ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); //RegC50[7]=1'b1 //enable HW AntDiv
+
+
+ //SW Control
+ //PHY_SetBBReg(Adapter, 0x864 , BIT10, 1);
+ //PHY_SetBBReg(Adapter, 0x870 , BIT9, 1);
+ //PHY_SetBBReg(Adapter, 0x870 , BIT8, 1);
+ //PHY_SetBBReg(Adapter, 0x864 , BIT11, 1);
+ //PHY_SetBBReg(Adapter, 0x860 , BIT9, 0);
+ //PHY_SetBBReg(Adapter, 0x860 , BIT8, 0);
+}
+
+VOID
+ODM_AntennaDiversityInit_88E(
+ IN PDM_ODM_T pDM_Odm
+)
+{
+/*
+ //2012.03.27 LukeLee: For temp use, should be removed later
+ //pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV;
+ //{
+ PADAPTER Adapter = pDM_Odm->Adapter;
+ HAL_DATA_TYPE* pHalData = GET_HAL_DATA(Adapter);
+ //pHalData->AntDivCfg = 1;
+ //}
+*/
+ if(pDM_Odm->SupportICType != ODM_RTL8188E)
+ return;
+
+ //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_Odm->AntDivType=%d, pHalData->AntDivCfg=%d\n",
+ // pDM_Odm->AntDivType, pHalData->AntDivCfg));
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_Odm->AntDivType=%d\n",pDM_Odm->AntDivType));
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_Odm->bIsMPChip=%s\n",(pDM_Odm->bIsMPChip?"TRUE":"FALSE")));
+
+ if(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV)
+ odm_RX_HWAntDivInit(pDM_Odm);
+ else if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
+ odm_TRX_HWAntDivInit(pDM_Odm);
+ else if(pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)
+ odm_FastAntTrainingInit(pDM_Odm);
+}
+
+
+VOID
+ODM_UpdateRxIdleAnt_88E(IN PDM_ODM_T pDM_Odm, IN u1Byte Ant)
+{
+ pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
+ u4Byte DefaultAnt, OptionalAnt;
+
+ if(pDM_FatTable->RxIdleAnt != Ant)
+ {
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Need to Update Rx Idle Ant\n"));
+ if(Ant == MAIN_ANT)
+ {
+ DefaultAnt = (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)?MAIN_ANT_CG_TRX:MAIN_ANT_CGCS_RX;
+ OptionalAnt = (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)?AUX_ANT_CG_TRX:AUX_ANT_CGCS_RX;
+ }
+ else
+ {
+ DefaultAnt = (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)?AUX_ANT_CG_TRX:AUX_ANT_CGCS_RX;
+ OptionalAnt = (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)?MAIN_ANT_CG_TRX:MAIN_ANT_CGCS_RX;
+ }
+
+ if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
+ {
+ ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, DefaultAnt); //Default RX
+ ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT8|BIT7|BIT6, OptionalAnt); //Optional RX
+ ODM_SetBBReg(pDM_Odm, ODM_REG_ANTSEL_CTRL_11N , BIT14|BIT13|BIT12, DefaultAnt); //Default TX
+ ODM_SetMACReg(pDM_Odm, ODM_REG_RESP_TX_11N , BIT6|BIT7, DefaultAnt); //Resp Tx
+
+ }
+ else if(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV)
+ {
+ ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, DefaultAnt); //Default RX
+ ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT8|BIT7|BIT6, OptionalAnt); //Optional RX
+ }
+ }
+ pDM_FatTable->RxIdleAnt = Ant;
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("RxIdleAnt=%s\n",(Ant==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
+ printk("RxIdleAnt=%s\n",(Ant==MAIN_ANT)?"MAIN_ANT":"AUX_ANT");
+}
+
+
+VOID
+odm_UpdateTxAnt_88E(IN PDM_ODM_T pDM_Odm, IN u1Byte Ant, IN u4Byte MacId)
+{
+ pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
+ u1Byte TargetAnt;
+
+ if(Ant == MAIN_ANT)
+ TargetAnt = MAIN_ANT_CG_TRX;
+ else
+ TargetAnt = AUX_ANT_CG_TRX;
+
+ pDM_FatTable->antsel_a[MacId] = TargetAnt&BIT0;
+ pDM_FatTable->antsel_b[MacId] = (TargetAnt&BIT1)>>1;
+ pDM_FatTable->antsel_c[MacId] = (TargetAnt&BIT2)>>2;
+
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Tx from TxInfo, TargetAnt=%s\n",
+ (Ant==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("antsel_tr_mux=3'b%d%d%d\n",
+ pDM_FatTable->antsel_c[MacId] , pDM_FatTable->antsel_b[MacId] , pDM_FatTable->antsel_a[MacId] ));
+}
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE))
+VOID
+ODM_SetTxAntByTxInfo_88E(
+ IN PDM_ODM_T pDM_Odm,
+ IN pu1Byte pDesc,
+ IN u1Byte macId
+ )
+{
+ pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
+
+ if((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)||(pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV))
+ {
+ SET_TX_DESC_ANTSEL_A_88E(pDesc, pDM_FatTable->antsel_a[macId]);
+ SET_TX_DESC_ANTSEL_B_88E(pDesc, pDM_FatTable->antsel_b[macId]);
+ SET_TX_DESC_ANTSEL_C_88E(pDesc, pDM_FatTable->antsel_c[macId]);
+ //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SetTxAntByTxInfo_88E_WIN(): MacID=%d, antsel_tr_mux=3'b%d%d%d\n",
+ // macId, pDM_FatTable->antsel_c[macId], pDM_FatTable->antsel_b[macId], pDM_FatTable->antsel_a[macId]));
+ }
+}
+#else// (DM_ODM_SUPPORT_TYPE == ODM_AP)
+VOID
+ODM_SetTxAntByTxInfo_88E(
+ IN PDM_ODM_T pDM_Odm
+ )
+{
+}
+#endif
+
+VOID
+ODM_AntselStatistics_88E(
+ IN PDM_ODM_T pDM_Odm,
+ IN u1Byte antsel_tr_mux,
+ IN u4Byte MacId,
+ IN u1Byte RxPWDBAll
+)
+{
+ pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
+ if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
+ {
+ if(antsel_tr_mux == MAIN_ANT_CG_TRX)
+ {
+
+ pDM_FatTable->MainAnt_Sum[MacId]+=RxPWDBAll;
+ pDM_FatTable->MainAnt_Cnt[MacId]++;
+ }
+ else
+ {
+ pDM_FatTable->AuxAnt_Sum[MacId]+=RxPWDBAll;
+ pDM_FatTable->AuxAnt_Cnt[MacId]++;
+
+ }
+ }
+ else if(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV)
+ {
+ if(antsel_tr_mux == MAIN_ANT_CGCS_RX)
+ {
+
+ pDM_FatTable->MainAnt_Sum[MacId]+=RxPWDBAll;
+ pDM_FatTable->MainAnt_Cnt[MacId]++;
+ }
+ else
+ {
+ pDM_FatTable->AuxAnt_Sum[MacId]+=RxPWDBAll;
+ pDM_FatTable->AuxAnt_Cnt[MacId]++;
+
+ }
+ }
+}
+
+#define TX_BY_REG 0
+VOID
+odm_HWAntDiv(
+ IN PDM_ODM_T pDM_Odm
+)
+{
+ u4Byte i, MinRSSI=0xFF, AntDivMaxRSSI=0, MaxRSSI=0, LocalMinRSSI, LocalMaxRSSI;
+ u4Byte Main_RSSI, Aux_RSSI;
+ u1Byte RxIdleAnt=0, TargetAnt=7;
+ pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
+ pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;
+ BOOLEAN bMatchBSSID;
+ BOOLEAN bPktFilterMacth = FALSE;
+ PSTA_INFO_T pEntry;
+
+ for (i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++)
+ {
+ pEntry = pDM_Odm->pODM_StaInfo[i];
+ if(IS_STA_VALID(pEntry))
+ {
+ //2 Caculate RSSI per Antenna
+ Main_RSSI = (pDM_FatTable->MainAnt_Cnt[i]!=0)?(pDM_FatTable->MainAnt_Sum[i]/pDM_FatTable->MainAnt_Cnt[i]):0;
+ Aux_RSSI = (pDM_FatTable->AuxAnt_Cnt[i]!=0)?(pDM_FatTable->AuxAnt_Sum[i]/pDM_FatTable->AuxAnt_Cnt[i]):0;
+ TargetAnt = (Main_RSSI>=Aux_RSSI)?MAIN_ANT:AUX_ANT;
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MacID=%d, MainAnt_Sum=%d, MainAnt_Cnt=%d\n", i, pDM_FatTable->MainAnt_Sum[i], pDM_FatTable->MainAnt_Cnt[i]));
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MacID=%d, AuxAnt_Sum=%d, AuxAnt_Cnt=%d\n",i, pDM_FatTable->AuxAnt_Sum[i], pDM_FatTable->AuxAnt_Cnt[i]));
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MacID=%d, Main_RSSI= %d, Aux_RSSI= %d\n", i, Main_RSSI, Aux_RSSI));
+
+ //2 Select MaxRSSI for DIG
+ LocalMaxRSSI = (Main_RSSI>Aux_RSSI)?Main_RSSI:Aux_RSSI;
+ if((LocalMaxRSSI > AntDivMaxRSSI) && (LocalMaxRSSI < 40))
+ AntDivMaxRSSI = LocalMaxRSSI;
+ if(LocalMaxRSSI > MaxRSSI)
+ MaxRSSI = LocalMaxRSSI;
+
+ //2 Select RX Idle Antenna
+ if((pDM_FatTable->RxIdleAnt == MAIN_ANT) && (Main_RSSI == 0))
+ Main_RSSI = Aux_RSSI;
+ else if((pDM_FatTable->RxIdleAnt == AUX_ANT) && (Aux_RSSI == 0))
+ Aux_RSSI = Main_RSSI;
+
+ LocalMinRSSI = (Main_RSSI>Aux_RSSI)?Aux_RSSI:Main_RSSI;
+ if(LocalMinRSSI < MinRSSI)
+ {
+ MinRSSI = LocalMinRSSI;
+ RxIdleAnt = TargetAnt;
+ }
+#if TX_BY_REG
+
+#else
+ //2 Select TRX Antenna
+ if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
+ odm_UpdateTxAnt_88E(pDM_Odm, TargetAnt, i);
+#endif
+ }
+ pDM_FatTable->MainAnt_Sum[i] = 0;
+ pDM_FatTable->AuxAnt_Sum[i] = 0;
+ pDM_FatTable->MainAnt_Cnt[i] = 0;
+ pDM_FatTable->AuxAnt_Cnt[i] = 0;
+ }
+
+ //2 Set RX Idle Antenna
+ ODM_UpdateRxIdleAnt_88E(pDM_Odm, RxIdleAnt);
+
+ pDM_DigTable->AntDiv_RSSI_max = AntDivMaxRSSI;
+ pDM_DigTable->RSSI_max = MaxRSSI;
+}
+
+
+#if (!(DM_ODM_SUPPORT_TYPE == ODM_CE))
+VOID
+odm_SetNextMACAddrTarget(
+ IN PDM_ODM_T pDM_Odm
+)
+{
+ pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
+ PSTA_INFO_T pEntry;
+ //u1Byte Bssid[6];
+ u4Byte value32, i;
+
+ //
+ //2012.03.26 LukeLee: The MAC address is changed according to MACID in turn
+ //
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_SetNextMACAddrTarget() ==>\n"));
+ if(pDM_Odm->bLinked)
+ {
+ for (i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++)
+ {
+ if((pDM_FatTable->TrainIdx+1) == ODM_ASSOCIATE_ENTRY_NUM)
+ pDM_FatTable->TrainIdx = 0;
+ else
+ pDM_FatTable->TrainIdx++;
+
+ pEntry = pDM_Odm->pODM_StaInfo[pDM_FatTable->TrainIdx];
+ if(IS_STA_VALID(pEntry))
+ {
+ //Match MAC ADDR
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
+ value32 = (pEntry->hwaddr[5]<<8)|pEntry->hwaddr[4];
+#else
+ value32 = (pEntry->MacAddr[5]<<8)|pEntry->MacAddr[4];
+#endif
+ ODM_SetMACReg(pDM_Odm, 0x7b4, 0xFFFF, value32);
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
+ value32 = (pEntry->hwaddr[3]<<24)|(pEntry->hwaddr[2]<<16) |(pEntry->hwaddr[1]<<8) |pEntry->hwaddr[0];
+#else
+ value32 = (pEntry->MacAddr[3]<<24)|(pEntry->MacAddr[2]<<16) |(pEntry->MacAddr[1]<<8) |pEntry->MacAddr[0];
+#endif
+ ODM_SetMACReg(pDM_Odm, 0x7b0, bMaskDWord, value32);
+
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_FatTable->TrainIdx=%d\n",pDM_FatTable->TrainIdx));
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Training MAC Addr = %x:%x:%x:%x:%x:%x\n",
+ pEntry->hwaddr[5],pEntry->hwaddr[4],pEntry->hwaddr[3],pEntry->hwaddr[2],pEntry->hwaddr[1],pEntry->hwaddr[0]));
+#else
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Training MAC Addr = %x:%x:%x:%x:%x:%x\n",
+ pEntry->MacAddr[5],pEntry->MacAddr[4],pEntry->MacAddr[3],pEntry->MacAddr[2],pEntry->MacAddr[1],pEntry->MacAddr[0]));
+#endif
+
+ break;
+ }
+ }
+
+ }
+
+#if 0
+ //
+ //2012.03.26 LukeLee: This should be removed later, the MAC address is changed according to MACID in turn
+ //
+ #if( DM_ODM_SUPPORT_TYPE & ODM_MP)
+ {
+ PADAPTER Adapter = pDM_Odm->Adapter;
+ PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
+
+ for (i=0; i<6; i++)
+ {
+ Bssid[i] = pMgntInfo->Bssid[i];
+ //DbgPrint("Bssid[%d]=%x\n", i, Bssid[i]);
+ }
+ }
+ #endif
+
+ //odm_SetNextMACAddrTarget(pDM_Odm);
+
+ //1 Select MAC Address Filter
+ for (i=0; i<6; i++)
+ {
+ if(Bssid[i] != pDM_FatTable->Bssid[i])
+ {
+ bMatchBSSID = FALSE;
+ break;
+ }
+ }
+ if(bMatchBSSID == FALSE)
+ {
+ //Match MAC ADDR
+ value32 = (Bssid[5]<<8)|Bssid[4];
+ ODM_SetMACReg(pDM_Odm, 0x7b4, 0xFFFF, value32);
+ value32 = (Bssid[3]<<24)|(Bssid[2]<<16) |(Bssid[1]<<8) |Bssid[0];
+ ODM_SetMACReg(pDM_Odm, 0x7b0, bMaskDWord, value32);
+ }
+
+ return bMatchBSSID;
+#endif
+
+}
+
+VOID
+odm_FastAntTraining(
+ IN PDM_ODM_T pDM_Odm
+)
+{
+ u4Byte i, MaxRSSI=0;
+ u1Byte TargetAnt=2;
+ pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
+ BOOLEAN bPktFilterMacth = FALSE;
+ PSTA_INFO_T pEntry;
+
+
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("==>odm_FastAntTraining()\n"));
+
+ //1 TRAINING STATE
+ if(pDM_FatTable->FAT_State == FAT_TRAINING_STATE)
+ {
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Enter FAT_TRAINING_STATE\n"));
+ //2 Caculate RSSI per Antenna
+ for (i=0; i<7; i++)
+ {
+ if(pDM_FatTable->antRSSIcnt[i] == 0)
+ pDM_FatTable->antAveRSSI[i] = 0;
+ else
+ {
+ pDM_FatTable->antAveRSSI[i] = pDM_FatTable->antSumRSSI[i] /pDM_FatTable->antRSSIcnt[i];
+ bPktFilterMacth = TRUE;
+ }
+ if(pDM_FatTable->antAveRSSI[i] > MaxRSSI)
+ {
+ MaxRSSI = pDM_FatTable->antAveRSSI[i];
+ TargetAnt = (u1Byte) i;
+ }
+
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_FatTable->antAveRSSI[%d] = %d, pDM_FatTable->antRSSIcnt[%d] = %d\n",
+ i, pDM_FatTable->antAveRSSI[i], i, pDM_FatTable->antRSSIcnt[i]));
+ }
+
+ //2 Select TRX Antenna
+ if(bPktFilterMacth == FALSE)
+ {
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("None Packet is matched\n"));
+
+ ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 0); //RegE08[16]=1'b0 //disable fast training
+ ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 0); //RegC50[7]=1'b0 //disable HW AntDiv
+ }
+ else
+ {
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("TargetAnt=%d, MaxRSSI=%d\n",TargetAnt,MaxRSSI));
+
+ ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 0); //RegE08[16]=1'b0 //disable fast training
+ //ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 0); //RegC50[7]=1'b0 //disable HW AntDiv
+ ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, TargetAnt); //Default RX is Omni, Optional RX is the best decision by FAT
+ //ODM_SetBBReg(pDM_Odm, 0x860 , BIT14|BIT13|BIT12, TargetAnt); //Default TX
+ ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 1); //Reg80c[21]=1'b1 //from TX Info
+
+#if 0
+ pEntry = pDM_Odm->pODM_StaInfo[pDM_FatTable->TrainIdx];
+
+ if(IS_STA_VALID(pEntry))
+ {
+ pEntry->antsel_a = TargetAnt&BIT0;
+ pEntry->antsel_b = (TargetAnt&BIT1)>>1;
+ pEntry->antsel_c = (TargetAnt&BIT2)>>2;
+ }
+#else
+ pDM_FatTable->antsel_a[pDM_FatTable->TrainIdx] = TargetAnt&BIT0;
+ pDM_FatTable->antsel_b[pDM_FatTable->TrainIdx] = (TargetAnt&BIT1)>>1;
+ pDM_FatTable->antsel_c[pDM_FatTable->TrainIdx] = (TargetAnt&BIT2)>>2;
+#endif
+
+
+ if(TargetAnt == 0)
+ ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 0); //RegC50[7]=1'b0 //disable HW AntDiv
+
+ }
+
+ //2 Reset Counter
+ for(i=0; i<7; i++)
+ {
+ pDM_FatTable->antSumRSSI[i] = 0;
+ pDM_FatTable->antRSSIcnt[i] = 0;
+ }
+
+ pDM_FatTable->FAT_State = FAT_NORMAL_STATE;
+ return;
+ }
+
+ //1 NORMAL STATE
+ if(pDM_FatTable->FAT_State == FAT_NORMAL_STATE)
+ {
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Enter FAT_NORMAL_STATE\n"));
+
+ odm_SetNextMACAddrTarget(pDM_Odm);
+
+#if 0
+ pEntry = pDM_Odm->pODM_StaInfo[pDM_FatTable->TrainIdx];
+ if(IS_STA_VALID(pEntry))
+ {
+ pEntry->antsel_a = TargetAnt&BIT0;
+ pEntry->antsel_b = (TargetAnt&BIT1)>>1;
+ pEntry->antsel_c = (TargetAnt&BIT2)>>2;
+ }
+#endif
+
+ //2 Prepare Training
+ pDM_FatTable->FAT_State = FAT_TRAINING_STATE;
+ ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 1); //RegE08[16]=1'b1 //enable fast training
+ ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); //RegC50[7]=1'b1 //enable HW AntDiv
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Start FAT_TRAINING_STATE\n"));
+ ODM_SetTimer(pDM_Odm,&pDM_Odm->FastAntTrainingTimer, 500 ); //ms
+
+ }
+
+}
+
+VOID
+odm_FastAntTrainingCallback(
+ IN PDM_ODM_T pDM_Odm
+)
+{
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ PADAPTER padapter = pDM_Odm->Adapter;
+ if(padapter->net_closed == _TRUE)
+ return;
+ //if(*pDM_Odm->pbNet_closed == TRUE)
+ // return;
+#endif
+
+#if USE_WORKITEM
+ ODM_ScheduleWorkItem(&pDM_Odm->FastAntTrainingWorkitem);
+#else
+ odm_FastAntTraining(pDM_Odm);
+#endif
+}
+
+VOID
+odm_FastAntTrainingWorkItemCallback(
+ IN PDM_ODM_T pDM_Odm
+)
+{
+ odm_FastAntTraining(pDM_Odm);
+}
+#endif
+
+VOID
+ODM_AntennaDiversity_88E(
+ IN PDM_ODM_T pDM_Odm
+)
+{
+ pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
+ if((pDM_Odm->SupportICType != ODM_RTL8188E) || (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)))
+ {
+ //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_AntennaDiversity_88E: Not Support 88E AntDiv\n"));
+ return;
+ }
+#ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV
+ if(pDM_Odm->bLinked){
+ if(pDM_Odm->Adapter->registrypriv.force_ant != 0)
+ {
+ u4Byte Main_RSSI, Aux_RSSI;
+ u8 i=0;
+ Main_RSSI = (pDM_FatTable->MainAnt_Cnt[i]!=0)?(pDM_FatTable->MainAnt_Sum[i]/pDM_FatTable->MainAnt_Cnt[i]):0;
+ Aux_RSSI = (pDM_FatTable->AuxAnt_Cnt[i]!=0)?(pDM_FatTable->AuxAnt_Sum[i]/pDM_FatTable->AuxAnt_Cnt[i]):0;
+
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MacID=%d, MainAnt_Sum=%d, MainAnt_Cnt=%d\n", i, pDM_FatTable->MainAnt_Sum[i], pDM_FatTable->MainAnt_Cnt[i]));
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MacID=%d, AuxAnt_Sum=%d, AuxAnt_Cnt=%d\n",i, pDM_FatTable->AuxAnt_Sum[i], pDM_FatTable->AuxAnt_Cnt[i]));
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MacID=%d, Main_RSSI= %d, Aux_RSSI= %d\n", i, Main_RSSI, Aux_RSSI));
+ pDM_FatTable->MainAnt_Sum[i] = 0;
+ pDM_FatTable->AuxAnt_Sum[i] = 0;
+ pDM_FatTable->MainAnt_Cnt[i] = 0;
+ pDM_FatTable->AuxAnt_Cnt[i] = 0;
+ }
+ if(pDM_Odm->Adapter->registrypriv.force_ant==1){
+ ODM_UpdateRxIdleAnt_88E(pDM_Odm, MAIN_ANT);
+ printk("%s fixed antenna in Main ant\n",__FUNCTION__);
+ return;
+ }
+ else if(pDM_Odm->Adapter->registrypriv.force_ant==2){
+ ODM_UpdateRxIdleAnt_88E(pDM_Odm, AUX_ANT);
+ printk("%s fixed antenna in AUX ant\n",__FUNCTION__);
+ return;
+ }
+ }
+#endif
+
+
+
+ if(!pDM_Odm->bLinked)
+ {
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_AntennaDiversity_88E(): No Link.\n"));
+ if(pDM_FatTable->bBecomeLinked == TRUE)
+ {
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Need to Turn off HW AntDiv\n"));
+ ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); //RegC50[7]=1'b1 //enable HW AntDiv
+ ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA1_11N , BIT15, 0); //Enable CCK AntDiv
+ if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
+ ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 0); //Reg80c[21]=1'b0 //from TX Reg
+ pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked;
+ }
+ return;
+ }
+ else
+ {
+ if(pDM_FatTable->bBecomeLinked ==FALSE)
+ {
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Need to Turn on HW AntDiv\n"));
+ //Because HW AntDiv is disabled before Link, we enable HW AntDiv after link
+ ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 1); //RegC50[7]=1'b1 //enable HW AntDiv
+ ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA1_11N , BIT15, 1); //Enable CCK AntDiv
+ //ODM_SetMACReg(pDM_Odm, 0x7B4 , BIT18, 1); //Response Tx by current HW antdiv
+ if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
+ {
+#if TX_BY_REG
+ ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 0); //Reg80c[21]=1'b0 //from Reg
+#else
+ ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N , BIT21, 1); //Reg80c[21]=1'b1 //from TX Info
+#endif
+ }
+ pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked;
+ }
+ }
+
+
+
+ if((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)||(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV))
+ odm_HWAntDiv(pDM_Odm);
+ #if (!(DM_ODM_SUPPORT_TYPE == ODM_CE))
+ else if(pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)
+ odm_FastAntTraining(pDM_Odm);
+ #endif
+}
+
+
+/*
+#if (DM_ODM_SUPPORT_TYPE == ODM_MP)
+VOID
+odm_FastAntTrainingCallback(
+ PRT_TIMER pTimer
+)
+{
+ PADAPTER Adapter = (PADAPTER)pTimer->Adapter;
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+
+ //#if DEV_BUS_TYPE==RT_PCI_INTERFACE
+ //#if USE_WORKITEM
+ //PlatformScheduleWorkItem(&pHalData->SwAntennaSwitchWorkitem);
+ //#else
+ odm_FastAntTraining(&pHalData->DM_OutSrc);
+ //#endif
+ //#else
+ //PlatformScheduleWorkItem(&pHalData->SwAntennaSwitchWorkitem);
+ //#endif
+
+}
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+VOID odm_FastAntTrainingCallback(void *FunctionContext)
+{
+ PDM_ODM_T pDM_Odm= (PDM_ODM_T)FunctionContext;
+ PADAPTER padapter = pDM_Odm->Adapter;
+ if(padapter->net_closed == _TRUE)
+ return;
+ odm_FastAntTraining(pDM_Odm);
+}
+#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
+VOID odm_FastAntTrainingCallback(void *FunctionContext)
+{
+ PDM_ODM_T pDM_Odm= (PDM_ODM_T)FunctionContext;
+ odm_FastAntTraining(pDM_Odm);
+}
+
+#endif
+*/
+
+#else //#if(defined(CONFIG_HW_ANTENNA_DIVERSITY))
+#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE))
+VOID
+ODM_SetTxAntByTxInfo_88E(
+ IN PDM_ODM_T pDM_Odm,
+ IN pu1Byte pDesc,
+ IN u1Byte macId
+ )
+{
+}
+#else// (DM_ODM_SUPPORT_TYPE == ODM_AP)
+VOID
+ODM_SetTxAntByTxInfo_88E(
+ IN PDM_ODM_T pDM_Odm
+ )
+{
+}
+#endif
+#endif //#if(defined(CONFIG_HW_ANTENNA_DIVERSITY))
+//3============================================================
+//3 Dynamic Primary CCA
+//3============================================================
+
+VOID
+odm_PrimaryCCA_Init(
+ IN PDM_ODM_T pDM_Odm)
+{
+ pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA);
+ PrimaryCCA->DupRTS_flag = 0;
+ PrimaryCCA->intf_flag = 0;
+ PrimaryCCA->intf_type = 0;
+ PrimaryCCA->Monitor_flag = 0;
+ PrimaryCCA->PriCCA_flag = 0;
+}
+
+BOOLEAN
+ODM_DynamicPrimaryCCA_DupRTS(
+ IN PDM_ODM_T pDM_Odm
+ )
+{
+ pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA);
+
+ return PrimaryCCA->DupRTS_flag;
+}
+
+VOID
+odm_DynamicPrimaryCCA(
+ IN PDM_ODM_T pDM_Odm
+ )
+{
+ PADAPTER Adapter = pDM_Odm->Adapter; // for NIC
+ prtl8192cd_priv priv = pDM_Odm->priv; // for AP
+
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+#if (DM_ODM_SUPPORT_TYPE & (ODM_MP))
+ PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
+ PRT_WLAN_STA pEntry;
+#endif
+
+ PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pDM_Odm->FalseAlmCnt);
+ pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA);
+
+ BOOLEAN Is40MHz;
+ BOOLEAN Client_40MHz = FALSE, Client_tmp = FALSE; // connected client BW
+ BOOLEAN bConnected = FALSE; // connected or not
+ static u1Byte Client_40MHz_pre = 0;
+ static u8Byte lastTxOkCnt = 0;
+ static u8Byte lastRxOkCnt = 0;
+ static u4Byte Counter = 0;
+ static u1Byte Delay = 1;
+ u8Byte curTxOkCnt;
+ u8Byte curRxOkCnt;
+ u1Byte SecCHOffset;
+ u1Byte i;
+
+#if((DM_ODM_SUPPORT_TYPE==ODM_ADSL) ||( DM_ODM_SUPPORT_TYPE==ODM_CE))
+ return;
+#endif
+
+ if(pDM_Odm->SupportICType != ODM_RTL8188E)
+ return;
+
+ Is40MHz = *(pDM_Odm->pBandWidth);
+ SecCHOffset = *(pDM_Odm->pSecChOffset);
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Second CH Offset = %d\n", SecCHOffset));
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_MP)
+ if(Is40MHz==1)
+ SecCHOffset = SecCHOffset%2+1; // NIC's definition is reverse to AP 1:secondary below, 2: secondary above
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Second CH Offset = %d\n", SecCHOffset));
+ //3 Check Current WLAN Traffic
+ curTxOkCnt = Adapter->TxStats.NumTxBytesUnicast - lastTxOkCnt;
+ curRxOkCnt = Adapter->RxStats.NumRxBytesUnicast - lastRxOkCnt;
+ lastTxOkCnt = Adapter->TxStats.NumTxBytesUnicast;
+ lastRxOkCnt = Adapter->RxStats.NumRxBytesUnicast;
+#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
+ //3 Check Current WLAN Traffic
+ curTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast)-lastTxOkCnt;
+ curRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast)-lastRxOkCnt;
+ lastTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast);
+ lastRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast);
+#endif
+
+ //==================Debug Message====================
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("TP = %llu\n", curTxOkCnt+curRxOkCnt));
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Is40MHz = %d\n", Is40MHz));
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("BW_LSC = %d\n", FalseAlmCnt->Cnt_BW_LSC));
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("BW_USC = %d\n", FalseAlmCnt->Cnt_BW_USC));
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("CCA OFDM = %d\n", FalseAlmCnt->Cnt_OFDM_CCA));
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("CCA CCK = %d\n", FalseAlmCnt->Cnt_CCK_CCA));
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("OFDM FA = %d\n", FalseAlmCnt->Cnt_Ofdm_fail));
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("CCK FA = %d\n", FalseAlmCnt->Cnt_Cck_fail));
+ //================================================
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_MP)
+ if (ACTING_AS_AP(Adapter)) // primary cca process only do at AP mode
+#endif
+ {
+
+ #if (DM_ODM_SUPPORT_TYPE == ODM_MP)
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("ACTING as AP mode=%d\n", ACTING_AS_AP(Adapter)));
+ //3 To get entry's connection and BW infomation status.
+ for(i=0;i<ASSOCIATE_ENTRY_NUM;i++)
+ {
+ if(IsAPModeExist(Adapter)&&GetFirstExtAdapter(Adapter)!=NULL)
+ pEntry=AsocEntry_EnumStation(GetFirstExtAdapter(Adapter), i);
+ else
+ pEntry=AsocEntry_EnumStation(GetDefaultAdapter(Adapter), i);
+ if(pEntry!=NULL)
+ {
+ Client_tmp = pEntry->HTInfo.bBw40MHz; // client BW
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Client_BW=%d\n", Client_tmp));
+ if(Client_tmp>Client_40MHz)
+ Client_40MHz = Client_tmp; // 40M/20M coexist => 40M priority is High
+
+ if(pEntry->bAssociated)
+ {
+ bConnected=TRUE; // client is connected or not
+ break;
+ }
+ }
+ else
+ {
+ break;
+ }
+ }
+#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
+ //3 To get entry's connection and BW infomation status.
+
+ PSTA_INFO_T pstat;
+
+ for(i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++)
+ {
+ pstat = pDM_Odm->pODM_StaInfo[i];
+ if(IS_STA_VALID(pstat) )
+ {
+ Client_tmp = pstat->tx_bw;
+ if(Client_tmp>Client_40MHz)
+ Client_40MHz = Client_tmp; // 40M/20M coexist => 40M priority is High
+
+ bConnected = TRUE;
+ }
+ }
+#endif
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("bConnected=%d\n", bConnected));
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Is Client 40MHz=%d\n", Client_40MHz));
+ //1 Monitor whether the interference exists or not
+ if(PrimaryCCA->Monitor_flag == 1)
+ {
+ if(SecCHOffset == 1) // secondary channel is below the primary channel
+ {
+ if((FalseAlmCnt->Cnt_OFDM_CCA > 500)&&(FalseAlmCnt->Cnt_BW_LSC > FalseAlmCnt->Cnt_BW_USC+500))
+ {
+ if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1)
+ {
+ PrimaryCCA->intf_type = 1;
+ PrimaryCCA->PriCCA_flag = 1;
+ ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 2); // USC MF
+ if(PrimaryCCA->DupRTS_flag == 1)
+ PrimaryCCA->DupRTS_flag = 0;
+ }
+ else
+ {
+ PrimaryCCA->intf_type = 2;
+ if(PrimaryCCA->DupRTS_flag == 0)
+ PrimaryCCA->DupRTS_flag = 1;
+ }
+
+ }
+ else // interferecne disappear
+ {
+ PrimaryCCA->DupRTS_flag = 0;
+ PrimaryCCA->intf_flag = 0;
+ PrimaryCCA->intf_type = 0;
+ }
+ }
+ else if(SecCHOffset == 2) // secondary channel is above the primary channel
+ {
+ if((FalseAlmCnt->Cnt_OFDM_CCA > 500)&&(FalseAlmCnt->Cnt_BW_USC > FalseAlmCnt->Cnt_BW_LSC+500))
+ {
+ if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1)
+ {
+ PrimaryCCA->intf_type = 1;
+ PrimaryCCA->PriCCA_flag = 1;
+ ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 1); // LSC MF
+ if(PrimaryCCA->DupRTS_flag == 1)
+ PrimaryCCA->DupRTS_flag = 0;
+ }
+ else
+ {
+ PrimaryCCA->intf_type = 2;
+ if(PrimaryCCA->DupRTS_flag == 0)
+ PrimaryCCA->DupRTS_flag = 1;
+ }
+
+ }
+ else // interferecne disappear
+ {
+ PrimaryCCA->DupRTS_flag = 0;
+ PrimaryCCA->intf_flag = 0;
+ PrimaryCCA->intf_type = 0;
+ }
+
+
+ }
+ PrimaryCCA->Monitor_flag = 0;
+ }
+
+ //1 Dynamic Primary CCA Main Function
+ if(PrimaryCCA->Monitor_flag == 0)
+ {
+ if(Is40MHz) // if RFBW==40M mode which require to process primary cca
+ {
+ //2 STA is NOT Connected
+ if(!bConnected)
+ {
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("STA NOT Connected!!!!\n"));
+
+ if(PrimaryCCA->PriCCA_flag == 1) // reset primary cca when STA is disconnected
+ {
+ PrimaryCCA->PriCCA_flag = 0;
+ ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 0);
+ }
+ if(PrimaryCCA->DupRTS_flag == 1) // reset Duplicate RTS when STA is disconnected
+ PrimaryCCA->DupRTS_flag = 0;
+
+ if(SecCHOffset == 1) // secondary channel is below the primary channel
+ {
+ if((FalseAlmCnt->Cnt_OFDM_CCA > 800)&&(FalseAlmCnt->Cnt_BW_LSC*5 > FalseAlmCnt->Cnt_BW_USC*9))
+ {
+ PrimaryCCA->intf_flag = 1; // secondary channel interference is detected!!!
+ if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1)
+ PrimaryCCA->intf_type = 1; // interference is shift
+ else
+ PrimaryCCA->intf_type = 2; // interference is in-band
+ }
+ else
+ {
+ PrimaryCCA->intf_flag = 0;
+ PrimaryCCA->intf_type = 0;
+ }
+ }
+ else if(SecCHOffset == 2) // secondary channel is above the primary channel
+ {
+ if((FalseAlmCnt->Cnt_OFDM_CCA > 800)&&(FalseAlmCnt->Cnt_BW_USC*5 > FalseAlmCnt->Cnt_BW_LSC*9))
+ {
+ PrimaryCCA->intf_flag = 1; // secondary channel interference is detected!!!
+ if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1)
+ PrimaryCCA->intf_type = 1; // interference is shift
+ else
+ PrimaryCCA->intf_type = 2; // interference is in-band
+ }
+ else
+ {
+ PrimaryCCA->intf_flag = 0;
+ PrimaryCCA->intf_type = 0;
+ }
+ }
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("PrimaryCCA=%d\n",PrimaryCCA->PriCCA_flag));
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Intf_Type=%d\n", PrimaryCCA->intf_type));
+ }
+ //2 STA is Connected
+ else
+ {
+ if(Client_40MHz == 0) //3 // client BW = 20MHz
+ {
+ if(PrimaryCCA->PriCCA_flag == 0)
+ {
+ PrimaryCCA->PriCCA_flag = 1;
+ if(SecCHOffset==1)
+ ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 2);
+ else if(SecCHOffset==2)
+ ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 1);
+ }
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("STA Connected 20M!!! PrimaryCCA=%d\n", PrimaryCCA->PriCCA_flag));
+ }
+ else //3 // client BW = 40MHz
+ {
+ if(PrimaryCCA->intf_flag == 1) // interference is detected!!
+ {
+ if(PrimaryCCA->intf_type == 1)
+ {
+ if(PrimaryCCA->PriCCA_flag!=1)
+ {
+ PrimaryCCA->PriCCA_flag = 1;
+ if(SecCHOffset==1)
+ ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 2);
+ else if(SecCHOffset==2)
+ ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 1);
+ }
+ }
+ else if(PrimaryCCA->intf_type == 2)
+ {
+ if(PrimaryCCA->DupRTS_flag!=1)
+ PrimaryCCA->DupRTS_flag = 1;
+ }
+ }
+ else // if intf_flag==0
+ {
+ if((curTxOkCnt+curRxOkCnt)<10000) //idle mode or TP traffic is very low
+ {
+ if(SecCHOffset == 1)
+ {
+ if((FalseAlmCnt->Cnt_OFDM_CCA > 800)&&(FalseAlmCnt->Cnt_BW_LSC*5 > FalseAlmCnt->Cnt_BW_USC*9))
+ {
+ PrimaryCCA->intf_flag = 1;
+ if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1)
+ PrimaryCCA->intf_type = 1; // interference is shift
+ else
+ PrimaryCCA->intf_type = 2; // interference is in-band
+ }
+ }
+ else if(SecCHOffset == 2)
+ {
+ if((FalseAlmCnt->Cnt_OFDM_CCA > 800)&&(FalseAlmCnt->Cnt_BW_USC*5 > FalseAlmCnt->Cnt_BW_LSC*9))
+ {
+ PrimaryCCA->intf_flag = 1;
+ if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1)
+ PrimaryCCA->intf_type = 1; // interference is shift
+ else
+ PrimaryCCA->intf_type = 2; // interference is in-band
+ }
+
+ }
+ }
+ else // TP Traffic is High
+ {
+ if(SecCHOffset == 1)
+ {
+ if(FalseAlmCnt->Cnt_BW_LSC > (FalseAlmCnt->Cnt_BW_USC+500))
+ {
+ if(Delay == 0) // add delay to avoid interference occurring abruptly, jump one time
+ {
+ PrimaryCCA->intf_flag = 1;
+ if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1)
+ PrimaryCCA->intf_type = 1; // interference is shift
+ else
+ PrimaryCCA->intf_type = 2; // interference is in-band
+ Delay = 1;
+ }
+ else
+ Delay = 0;
+ }
+ }
+ else if(SecCHOffset == 2)
+ {
+ if(FalseAlmCnt->Cnt_BW_USC > (FalseAlmCnt->Cnt_BW_LSC+500))
+ {
+ if(Delay == 0) // add delay to avoid interference occurring abruptly
+ {
+ PrimaryCCA->intf_flag = 1;
+ if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1)
+ PrimaryCCA->intf_type = 1; // interference is shift
+ else
+ PrimaryCCA->intf_type = 2; // interference is in-band
+ Delay = 1;
+ }
+ else
+ Delay = 0;
+ }
+ }
+ }
+ }
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Primary CCA=%d\n", PrimaryCCA->PriCCA_flag));
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Duplicate RTS=%d\n", PrimaryCCA->DupRTS_flag));
+ }
+
+ }// end of connected
+ }
+ }
+ //1 Dynamic Primary CCA Monitor Counter
+ if((PrimaryCCA->PriCCA_flag == 1)||(PrimaryCCA->DupRTS_flag == 1))
+ {
+ if(Client_40MHz == 0) // client=20M no need to monitor primary cca flag
+ {
+ Client_40MHz_pre = Client_40MHz;
+ return;
+ }
+ Counter++;
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Counter=%d\n", Counter));
+ if((Counter == 30)||((Client_40MHz -Client_40MHz_pre)==1)) // Every 60 sec to monitor one time
+ {
+ PrimaryCCA->Monitor_flag = 1; // monitor flag is triggered!!!!!
+ if(PrimaryCCA->PriCCA_flag == 1)
+ {
+ PrimaryCCA->PriCCA_flag = 0;
+ ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 0);
+ }
+ Counter = 0;
+ }
+ }
+ }
+
+ Client_40MHz_pre = Client_40MHz;
+}
+#else //#if (RTL8188E_SUPPORT == 1)
+VOID
+ODM_UpdateRxIdleAnt_88E(IN PDM_ODM_T pDM_Odm, IN u1Byte Ant)
+{
+}
+VOID
+odm_PrimaryCCA_Init(
+ IN PDM_ODM_T pDM_Odm)
+{
+}
+VOID
+odm_DynamicPrimaryCCA(
+ IN PDM_ODM_T pDM_Odm
+ )
+{
+}
+BOOLEAN
+ODM_DynamicPrimaryCCA_DupRTS(
+ IN PDM_ODM_T pDM_Odm
+ )
+{
+ return FALSE;
+}
+#endif //#if (RTL8188E_SUPPORT == 1)
+
diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/odm_RTL8188E.h b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/odm_RTL8188E.h new file mode 100755 index 00000000..ac0e0067 --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/odm_RTL8188E.h @@ -0,0 +1,109 @@ +/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef __ODM_RTL8188E_H__
+#define __ODM_RTL8188E_H__
+
+#define MAIN_ANT 0
+#define AUX_ANT 1
+#define MAIN_ANT_CG_TRX 1
+#define AUX_ANT_CG_TRX 0
+#define MAIN_ANT_CGCS_RX 0
+#define AUX_ANT_CGCS_RX 1
+
+VOID
+ODM_DIG_LowerBound_88E(
+ IN PDM_ODM_T pDM_Odm
+);
+#if ( !(DM_ODM_SUPPORT_TYPE == ODM_CE))
+VOID
+odm_FastAntTrainingInit(
+ IN PDM_ODM_T pDM_Odm
+);
+#endif
+
+VOID
+ODM_AntennaDiversityInit_88E(
+ IN PDM_ODM_T pDM_Odm
+);
+
+VOID
+ODM_AntennaDiversity_88E
+(
+ IN PDM_ODM_T pDM_Odm
+);
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_MP|ODM_CE))
+VOID
+ODM_SetTxAntByTxInfo_88E(
+ IN PDM_ODM_T pDM_Odm,
+ IN pu1Byte pDesc,
+ IN u1Byte macId
+);
+#else// (DM_ODM_SUPPORT_TYPE == ODM_AP)
+VOID
+ODM_SetTxAntByTxInfo_88E(
+ IN PDM_ODM_T pDM_Odm
+);
+#endif
+
+VOID
+ODM_UpdateRxIdleAnt_88E(
+ IN PDM_ODM_T pDM_Odm,
+ IN u1Byte Ant
+);
+
+VOID
+ODM_AntselStatistics_88E(
+ IN PDM_ODM_T pDM_Odm,
+ IN u1Byte antsel_tr_mux,
+ IN u4Byte MacId,
+ IN u1Byte RxPWDBAll
+);
+
+#if ( !(DM_ODM_SUPPORT_TYPE == ODM_CE))
+VOID
+odm_FastAntTraining(
+ IN PDM_ODM_T pDM_Odm
+);
+
+VOID
+odm_FastAntTrainingCallback(
+ IN PDM_ODM_T pDM_Odm
+);
+
+VOID
+odm_FastAntTrainingWorkItemCallback(
+ IN PDM_ODM_T pDM_Odm
+);
+#endif
+VOID
+odm_PrimaryCCA_Init(
+ IN PDM_ODM_T pDM_Odm);
+
+BOOLEAN
+ODM_DynamicPrimaryCCA_DupRTS(
+ IN PDM_ODM_T pDM_Odm);
+
+VOID
+odm_DynamicPrimaryCCA(
+ IN PDM_ODM_T pDM_Odm);
+
+#endif
+
diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/odm_RegConfig8188E.c b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/odm_RegConfig8188E.c new file mode 100755 index 00000000..e0e7c8b8 --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/odm_RegConfig8188E.c @@ -0,0 +1,209 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "../odm_precomp.h" + +#if (RTL8188E_SUPPORT == 1) + +void +odm_ConfigRFReg_8188E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data, + IN ODM_RF_RADIO_PATH_E RF_PATH, + IN u4Byte RegAddr + ) +{ + if(Addr == 0xffe) + { + #ifdef CONFIG_LONG_DELAY_ISSUE + ODM_sleep_ms(50); + #else + ODM_delay_ms(50); + #endif + } + else if (Addr == 0xfd) + { + ODM_delay_ms(5); + } + else if (Addr == 0xfc) + { + ODM_delay_ms(1); + } + else if (Addr == 0xfb) + { + ODM_delay_us(50); + } + else if (Addr == 0xfa) + { + ODM_delay_us(5); + } + else if (Addr == 0xf9) + { + ODM_delay_us(1); + } + else + { + ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data); + // Add 1us delay between BB/RF register setting. + ODM_delay_us(1); + } +} + + +void +odm_ConfigRF_RadioA_8188E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ) +{ + u4Byte content = 0x1000; // RF_Content: radioa_txt + u4Byte maskforPhySet= (u4Byte)(content&0xE000); + + odm_ConfigRFReg_8188E(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data)); +} + +void +odm_ConfigRF_RadioB_8188E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ) +{ + u4Byte content = 0x1001; // RF_Content: radiob_txt + u4Byte maskforPhySet= (u4Byte)(content&0xE000); + + odm_ConfigRFReg_8188E(pDM_Odm, Addr, Data, ODM_RF_PATH_B, Addr|maskforPhySet); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioB] %08X %08X\n", Addr, Data)); + +} + +void +odm_ConfigMAC_8188E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u1Byte Data + ) +{ + ODM_Write1Byte(pDM_Odm, Addr, Data); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data)); +} + +void +odm_ConfigBB_AGC_8188E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ) +{ + ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); + // Add 1us delay between BB/RF register setting. + ODM_delay_us(1); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data)); +} + +void +odm_ConfigBB_PHY_REG_PG_8188E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ) +{ + if (Addr == 0xfe){ + #ifdef CONFIG_LONG_DELAY_ISSUE + ODM_sleep_ms(50); + #else + ODM_delay_ms(50); + #endif + } + else if (Addr == 0xfd){ + ODM_delay_ms(5); + } + else if (Addr == 0xfc){ + ODM_delay_ms(1); + } + else if (Addr == 0xfb){ + ODM_delay_us(50); + } + else if (Addr == 0xfa){ + ODM_delay_us(5); + } + else if (Addr == 0xf9){ + ODM_delay_us(1); + } + else{ + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("===> @@@@@@@ ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", Addr, Bitmask, Data)); + + #if !(DM_ODM_SUPPORT_TYPE&ODM_AP) + storePwrIndexDiffRateOffset(pDM_Odm->Adapter, Addr, Bitmask, Data); + #endif + } + +} + +void +odm_ConfigBB_PHY_8188E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ) +{ + if (Addr == 0xfe){ + #ifdef CONFIG_LONG_DELAY_ISSUE + ODM_sleep_ms(50); + #else + ODM_delay_ms(50); + #endif + } + else if (Addr == 0xfd){ + ODM_delay_ms(5); + } + else if (Addr == 0xfc){ + ODM_delay_ms(1); + } + else if (Addr == 0xfb){ + ODM_delay_us(50); + } + else if (Addr == 0xfa){ + ODM_delay_us(5); + } + else if (Addr == 0xf9){ + ODM_delay_us(1); + } + else{ + if (Addr == 0xa24) + pDM_Odm->RFCalibrateInfo.RegA24 = Data; + ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); + + // Add 1us delay between BB/RF register setting. + ODM_delay_us(1); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data)); + } +} +#endif + diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/odm_RegConfig8188E.h b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/odm_RegConfig8188E.h new file mode 100755 index 00000000..211b96de --- /dev/null +++ b/drivers/net/wireless/rtl8188E_8192E/hal/OUTSRC/rtl8188e/odm_RegConfig8188E.h @@ -0,0 +1,80 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __INC_ODM_REGCONFIG_H_8188E +#define __INC_ODM_REGCONFIG_H_8188E + +#if (RTL8188E_SUPPORT == 1) + +void +odm_ConfigRFReg_8188E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data, + IN ODM_RF_RADIO_PATH_E RF_PATH, + IN u4Byte RegAddr + ); + +void +odm_ConfigRF_RadioA_8188E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ); + +void +odm_ConfigRF_RadioB_8188E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ); + +void +odm_ConfigMAC_8188E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u1Byte Data + ); + +void +odm_ConfigBB_AGC_8188E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ); + +void +odm_ConfigBB_PHY_REG_PG_8188E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ); + +void +odm_ConfigBB_PHY_8188E( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ); +#endif +#endif // end of SUPPORT + |