diff options
Diffstat (limited to 'ANDROID_3.4.5/arch/arm/mach-mv78xx0')
23 files changed, 0 insertions, 2100 deletions
diff --git a/ANDROID_3.4.5/arch/arm/mach-mv78xx0/Kconfig b/ANDROID_3.4.5/arch/arm/mach-mv78xx0/Kconfig deleted file mode 100644 index f2d309d0..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-mv78xx0/Kconfig +++ /dev/null @@ -1,25 +0,0 @@ -if ARCH_MV78XX0 - -menu "Marvell MV78xx0 Implementations" - -config MACH_DB78X00_BP - bool "Marvell DB-78x00-BP Development Board" - help - Say 'Y' here if you want your kernel to support the - Marvell DB-78x00-BP Development Board. - -config MACH_RD78X00_MASA - bool "Marvell RD-78x00-mASA Reference Design" - help - Say 'Y' here if you want your kernel to support the - Marvell RD-78x00-mASA Reference Design. - -config MACH_TERASTATION_WXL - bool "Buffalo WLX (Terastation Duo) NAS" - help - Say 'Y' here if you want your kernel to support the - Buffalo WXL Nas. - -endmenu - -endif diff --git a/ANDROID_3.4.5/arch/arm/mach-mv78xx0/Makefile b/ANDROID_3.4.5/arch/arm/mach-mv78xx0/Makefile deleted file mode 100644 index 67a13f9b..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-mv78xx0/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -obj-y += common.o addr-map.o mpp.o irq.o pcie.o -obj-$(CONFIG_MACH_DB78X00_BP) += db78x00-bp-setup.o -obj-$(CONFIG_MACH_RD78X00_MASA) += rd78x00-masa-setup.o -obj-$(CONFIG_MACH_TERASTATION_WXL) += buffalo-wxl-setup.o diff --git a/ANDROID_3.4.5/arch/arm/mach-mv78xx0/Makefile.boot b/ANDROID_3.4.5/arch/arm/mach-mv78xx0/Makefile.boot deleted file mode 100644 index 760a0efe..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-mv78xx0/Makefile.boot +++ /dev/null @@ -1,3 +0,0 @@ - zreladdr-y += 0x00008000 -params_phys-y := 0x00000100 -initrd_phys-y := 0x00800000 diff --git a/ANDROID_3.4.5/arch/arm/mach-mv78xx0/addr-map.c b/ANDROID_3.4.5/arch/arm/mach-mv78xx0/addr-map.c deleted file mode 100644 index 62b53d71..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-mv78xx0/addr-map.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - * arch/arm/mach-mv78xx0/addr-map.c - * - * Address map functions for Marvell MV78xx0 SoCs - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/mbus.h> -#include <linux/io.h> -#include <plat/addr-map.h> -#include "common.h" - -/* - * Generic Address Decode Windows bit settings - */ -#define TARGET_DEV_BUS 1 -#define TARGET_PCIE0 4 -#define TARGET_PCIE1 8 -#define TARGET_PCIE(i) ((i) ? TARGET_PCIE1 : TARGET_PCIE0) -#define ATTR_DEV_SPI_ROM 0x1f -#define ATTR_DEV_BOOT 0x2f -#define ATTR_DEV_CS3 0x37 -#define ATTR_DEV_CS2 0x3b -#define ATTR_DEV_CS1 0x3d -#define ATTR_DEV_CS0 0x3e -#define ATTR_PCIE_IO(l) (0xf0 & ~(0x10 << (l))) -#define ATTR_PCIE_MEM(l) (0xf8 & ~(0x10 << (l))) - -/* - * CPU Address Decode Windows registers - */ -#define WIN0_OFF(n) (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4)) -#define WIN8_OFF(n) (BRIDGE_VIRT_BASE + 0x0900 + (((n) - 8) << 4)) - -static void __init __iomem *win_cfg_base(int win) -{ - /* - * Find the control register base address for this window. - * - * BRIDGE_VIRT_BASE points to the right (CPU0's or CPU1's) - * MBUS bridge depending on which CPU core we're running on, - * so we don't need to take that into account here. - */ - - return (void __iomem *)((win < 8) ? WIN0_OFF(win) : WIN8_OFF(win)); -} - -/* - * Description of the windows needed by the platform code - */ -static struct __initdata orion_addr_map_cfg addr_map_cfg = { - .num_wins = 14, - .remappable_wins = 8, - .win_cfg_base = win_cfg_base, -}; - -void __init mv78xx0_setup_cpu_mbus(void) -{ - /* - * Disable, clear and configure windows. - */ - orion_config_wins(&addr_map_cfg, NULL); - - /* - * Setup MBUS dram target info. - */ - if (mv78xx0_core_index() == 0) - orion_setup_cpu_mbus_target(&addr_map_cfg, - DDR_WINDOW_CPU0_BASE); - else - orion_setup_cpu_mbus_target(&addr_map_cfg, - DDR_WINDOW_CPU1_BASE); -} - -void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size, - int maj, int min) -{ - orion_setup_cpu_win(&addr_map_cfg, window, base, size, - TARGET_PCIE(maj), ATTR_PCIE_IO(min), -1); -} - -void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size, - int maj, int min) -{ - orion_setup_cpu_win(&addr_map_cfg, window, base, size, - TARGET_PCIE(maj), ATTR_PCIE_MEM(min), -1); -} diff --git a/ANDROID_3.4.5/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c b/ANDROID_3.4.5/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c deleted file mode 100644 index ee74ec97..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - * arch/arm/mach-mv78xx0/buffalo-wxl-setup.c - * - * Buffalo WXL (Terastation Duo) Setup routines - * - * sebastien requiem <sebastien@requiem.fr> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/ata_platform.h> -#include <linux/mv643xx_eth.h> -#include <linux/ethtool.h> -#include <linux/i2c.h> -#include <mach/mv78xx0.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include "common.h" -#include "mpp.h" - - -/* This arch has 2 Giga Ethernet */ - -static struct mv643xx_eth_platform_data db78x00_ge00_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(0), -}; - -static struct mv643xx_eth_platform_data db78x00_ge01_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(8), -}; - - -/* 2 SATA controller supporting HotPlug */ - -static struct mv_sata_platform_data db78x00_sata_data = { - .n_ports = 2, -}; - -static struct i2c_board_info __initdata db78x00_i2c_rtc = { - I2C_BOARD_INFO("ds1338", 0x68), -}; - - -static unsigned int wxl_mpp_config[] __initdata = { - MPP0_GE1_TXCLK, - MPP1_GE1_TXCTL, - MPP2_GE1_RXCTL, - MPP3_GE1_RXCLK, - MPP4_GE1_TXD0, - MPP5_GE1_TXD1, - MPP6_GE1_TXD2, - MPP7_GE1_TXD3, - MPP8_GE1_RXD0, - MPP9_GE1_RXD1, - MPP10_GE1_RXD2, - MPP11_GE1_RXD3, - MPP12_GPIO, - MPP13_SYSRST_OUTn, - MPP14_SATA1_ACTn, - MPP15_SATA0_ACTn, - MPP16_GPIO, - MPP17_GPIO, - MPP18_GPIO, - MPP19_GPIO, - MPP20_GPIO, - MPP21_GPIO, - MPP22_GPIO, - MPP23_GPIO, - MPP24_UA2_TXD, - MPP25_UA2_RXD, - MPP26_UA2_CTSn, - MPP27_UA2_RTSn, - MPP28_GPIO, - MPP29_SYSRST_OUTn, - MPP30_GPIO, - MPP31_GPIO, - MPP32_GPIO, - MPP33_GPIO, - MPP34_GPIO, - MPP35_GPIO, - MPP36_GPIO, - MPP37_GPIO, - MPP38_GPIO, - MPP39_GPIO, - MPP40_UNUSED, - MPP41_UNUSED, - MPP42_UNUSED, - MPP43_UNUSED, - MPP44_UNUSED, - MPP45_UNUSED, - MPP46_UNUSED, - MPP47_UNUSED, - MPP48_SATA1_ACTn, - MPP49_SATA0_ACTn, - 0 -}; - - -static void __init wxl_init(void) -{ - /* - * Basic MV78xx0 setup. Needs to be called early. - */ - mv78xx0_init(); - mv78xx0_mpp_conf(wxl_mpp_config); - - /* - * Partition on-chip peripherals between the two CPU cores. - */ - mv78xx0_ehci0_init(); - mv78xx0_ehci1_init(); - mv78xx0_ehci2_init(); - mv78xx0_ge00_init(&db78x00_ge00_data); - mv78xx0_ge01_init(&db78x00_ge01_data); - mv78xx0_sata_init(&db78x00_sata_data); - mv78xx0_uart0_init(); - mv78xx0_uart1_init(); - mv78xx0_uart2_init(); - mv78xx0_uart3_init(); - mv78xx0_i2c_init(); - i2c_register_board_info(0, &db78x00_i2c_rtc, 1); -} - -static int __init wxl_pci_init(void) -{ - if (machine_is_terastation_wxl()) { - /* - * Assign the x16 PCIe slot on the board to CPU core - * #0, and let CPU core #1 have the four x1 slots. - */ - if (mv78xx0_core_index() == 0) - mv78xx0_pcie_init(0, 1); - else - mv78xx0_pcie_init(1, 0); - } - - return 0; -} -subsys_initcall(wxl_pci_init); - -MACHINE_START(TERASTATION_WXL, "Buffalo Nas WXL") - /* Maintainer: Sebastien Requiem <sebastien@requiem.fr> */ - .atag_offset = 0x100, - .init_machine = wxl_init, - .map_io = mv78xx0_map_io, - .init_early = mv78xx0_init_early, - .init_irq = mv78xx0_init_irq, - .timer = &mv78xx0_timer, - .restart = mv78xx0_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-mv78xx0/common.c b/ANDROID_3.4.5/arch/arm/mach-mv78xx0/common.c deleted file mode 100644 index a5dcf766..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-mv78xx0/common.c +++ /dev/null @@ -1,416 +0,0 @@ -/* - * arch/arm/mach-mv78xx0/common.c - * - * Core functions for Marvell MV78xx0 SoCs - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/serial_8250.h> -#include <linux/ata_platform.h> -#include <linux/ethtool.h> -#include <asm/mach/map.h> -#include <asm/mach/time.h> -#include <mach/mv78xx0.h> -#include <mach/bridge-regs.h> -#include <plat/cache-feroceon-l2.h> -#include <plat/ehci-orion.h> -#include <plat/orion_nand.h> -#include <plat/time.h> -#include <plat/common.h> -#include <plat/addr-map.h> -#include "common.h" - -static int get_tclk(void); - -/***************************************************************************** - * Common bits - ****************************************************************************/ -int mv78xx0_core_index(void) -{ - u32 extra; - - /* - * Read Extra Features register. - */ - __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (extra)); - - return !!(extra & 0x00004000); -} - -static int get_hclk(void) -{ - int hclk; - - /* - * HCLK tick rate is configured by DEV_D[7:5] pins. - */ - switch ((readl(SAMPLE_AT_RESET_LOW) >> 5) & 7) { - case 0: - hclk = 166666667; - break; - case 1: - hclk = 200000000; - break; - case 2: - hclk = 266666667; - break; - case 3: - hclk = 333333333; - break; - case 4: - hclk = 400000000; - break; - default: - panic("unknown HCLK PLL setting: %.8x\n", - readl(SAMPLE_AT_RESET_LOW)); - } - - return hclk; -} - -static void get_pclk_l2clk(int hclk, int core_index, int *pclk, int *l2clk) -{ - u32 cfg; - - /* - * Core #0 PCLK/L2CLK is configured by bits [13:8], core #1 - * PCLK/L2CLK by bits [19:14]. - */ - if (core_index == 0) { - cfg = (readl(SAMPLE_AT_RESET_LOW) >> 8) & 0x3f; - } else { - cfg = (readl(SAMPLE_AT_RESET_LOW) >> 14) & 0x3f; - } - - /* - * Bits [11:8] ([17:14] for core #1) configure the PCLK:HCLK - * ratio (1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6). - */ - *pclk = ((u64)hclk * (2 + (cfg & 0xf))) >> 1; - - /* - * Bits [13:12] ([19:18] for core #1) configure the PCLK:L2CLK - * ratio (1, 2, 3). - */ - *l2clk = *pclk / (((cfg >> 4) & 3) + 1); -} - -static int get_tclk(void) -{ - int tclk; - - /* - * TCLK tick rate is configured by DEV_A[2:0] strap pins. - */ - switch ((readl(SAMPLE_AT_RESET_HIGH) >> 6) & 7) { - case 1: - tclk = 166666667; - break; - case 3: - tclk = 200000000; - break; - default: - panic("unknown TCLK PLL setting: %.8x\n", - readl(SAMPLE_AT_RESET_HIGH)); - } - - return tclk; -} - - -/***************************************************************************** - * I/O Address Mapping - ****************************************************************************/ -static struct map_desc mv78xx0_io_desc[] __initdata = { - { - .virtual = MV78XX0_CORE_REGS_VIRT_BASE, - .pfn = 0, - .length = MV78XX0_CORE_REGS_SIZE, - .type = MT_DEVICE, - }, { - .virtual = MV78XX0_PCIE_IO_VIRT_BASE(0), - .pfn = __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)), - .length = MV78XX0_PCIE_IO_SIZE * 8, - .type = MT_DEVICE, - }, { - .virtual = MV78XX0_REGS_VIRT_BASE, - .pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE), - .length = MV78XX0_REGS_SIZE, - .type = MT_DEVICE, - }, -}; - -void __init mv78xx0_map_io(void) -{ - unsigned long phys; - - /* - * Map the right set of per-core registers depending on - * which core we are running on. - */ - if (mv78xx0_core_index() == 0) { - phys = MV78XX0_CORE0_REGS_PHYS_BASE; - } else { - phys = MV78XX0_CORE1_REGS_PHYS_BASE; - } - mv78xx0_io_desc[0].pfn = __phys_to_pfn(phys); - - iotable_init(mv78xx0_io_desc, ARRAY_SIZE(mv78xx0_io_desc)); -} - - -/***************************************************************************** - * EHCI - ****************************************************************************/ -void __init mv78xx0_ehci0_init(void) -{ - orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0, EHCI_PHY_NA); -} - - -/***************************************************************************** - * EHCI1 - ****************************************************************************/ -void __init mv78xx0_ehci1_init(void) -{ - orion_ehci_1_init(USB1_PHYS_BASE, IRQ_MV78XX0_USB_1); -} - - -/***************************************************************************** - * EHCI2 - ****************************************************************************/ -void __init mv78xx0_ehci2_init(void) -{ - orion_ehci_2_init(USB2_PHYS_BASE, IRQ_MV78XX0_USB_2); -} - - -/***************************************************************************** - * GE00 - ****************************************************************************/ -void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data) -{ - orion_ge00_init(eth_data, - GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM, - IRQ_MV78XX0_GE_ERR, get_tclk()); -} - - -/***************************************************************************** - * GE01 - ****************************************************************************/ -void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data) -{ - orion_ge01_init(eth_data, - GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM, - NO_IRQ, get_tclk()); -} - - -/***************************************************************************** - * GE10 - ****************************************************************************/ -void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data) -{ - u32 dev, rev; - - /* - * On the Z0, ge10 and ge11 are internally connected back - * to back, and not brought out. - */ - mv78xx0_pcie_id(&dev, &rev); - if (dev == MV78X00_Z0_DEV_ID) { - eth_data->phy_addr = MV643XX_ETH_PHY_NONE; - eth_data->speed = SPEED_1000; - eth_data->duplex = DUPLEX_FULL; - } - - orion_ge10_init(eth_data, - GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM, - NO_IRQ, get_tclk()); -} - - -/***************************************************************************** - * GE11 - ****************************************************************************/ -void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data) -{ - u32 dev, rev; - - /* - * On the Z0, ge10 and ge11 are internally connected back - * to back, and not brought out. - */ - mv78xx0_pcie_id(&dev, &rev); - if (dev == MV78X00_Z0_DEV_ID) { - eth_data->phy_addr = MV643XX_ETH_PHY_NONE; - eth_data->speed = SPEED_1000; - eth_data->duplex = DUPLEX_FULL; - } - - orion_ge11_init(eth_data, - GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM, - NO_IRQ, get_tclk()); -} - -/***************************************************************************** - * I2C - ****************************************************************************/ -void __init mv78xx0_i2c_init(void) -{ - orion_i2c_init(I2C_0_PHYS_BASE, IRQ_MV78XX0_I2C_0, 8); - orion_i2c_1_init(I2C_1_PHYS_BASE, IRQ_MV78XX0_I2C_1, 8); -} - -/***************************************************************************** - * SATA - ****************************************************************************/ -void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data) -{ - orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_MV78XX0_SATA); -} - - -/***************************************************************************** - * UART0 - ****************************************************************************/ -void __init mv78xx0_uart0_init(void) -{ - orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, - IRQ_MV78XX0_UART_0, get_tclk()); -} - - -/***************************************************************************** - * UART1 - ****************************************************************************/ -void __init mv78xx0_uart1_init(void) -{ - orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, - IRQ_MV78XX0_UART_1, get_tclk()); -} - - -/***************************************************************************** - * UART2 - ****************************************************************************/ -void __init mv78xx0_uart2_init(void) -{ - orion_uart2_init(UART2_VIRT_BASE, UART2_PHYS_BASE, - IRQ_MV78XX0_UART_2, get_tclk()); -} - -/***************************************************************************** - * UART3 - ****************************************************************************/ -void __init mv78xx0_uart3_init(void) -{ - orion_uart3_init(UART3_VIRT_BASE, UART3_PHYS_BASE, - IRQ_MV78XX0_UART_3, get_tclk()); -} - -/***************************************************************************** - * Time handling - ****************************************************************************/ -void __init mv78xx0_init_early(void) -{ - orion_time_set_base(TIMER_VIRT_BASE); -} - -static void mv78xx0_timer_init(void) -{ - orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, - IRQ_MV78XX0_TIMER_1, get_tclk()); -} - -struct sys_timer mv78xx0_timer = { - .init = mv78xx0_timer_init, -}; - - -/***************************************************************************** - * General - ****************************************************************************/ -static char * __init mv78xx0_id(void) -{ - u32 dev, rev; - - mv78xx0_pcie_id(&dev, &rev); - - if (dev == MV78X00_Z0_DEV_ID) { - if (rev == MV78X00_REV_Z0) - return "MV78X00-Z0"; - else - return "MV78X00-Rev-Unsupported"; - } else if (dev == MV78100_DEV_ID) { - if (rev == MV78100_REV_A0) - return "MV78100-A0"; - else if (rev == MV78100_REV_A1) - return "MV78100-A1"; - else - return "MV78100-Rev-Unsupported"; - } else if (dev == MV78200_DEV_ID) { - if (rev == MV78100_REV_A0) - return "MV78200-A0"; - else - return "MV78200-Rev-Unsupported"; - } else { - return "Device-Unknown"; - } -} - -static int __init is_l2_writethrough(void) -{ - return !!(readl(CPU_CONTROL) & L2_WRITETHROUGH); -} - -void __init mv78xx0_init(void) -{ - int core_index; - int hclk; - int pclk; - int l2clk; - int tclk; - - core_index = mv78xx0_core_index(); - hclk = get_hclk(); - get_pclk_l2clk(hclk, core_index, &pclk, &l2clk); - tclk = get_tclk(); - - printk(KERN_INFO "%s ", mv78xx0_id()); - printk("core #%d, ", core_index); - printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000); - printk("L2 = %dMHz, ", (l2clk + 499999) / 1000000); - printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000); - printk("TCLK = %dMHz\n", (tclk + 499999) / 1000000); - - mv78xx0_setup_cpu_mbus(); - -#ifdef CONFIG_CACHE_FEROCEON_L2 - feroceon_l2_init(is_l2_writethrough()); -#endif -} - -void mv78xx0_restart(char mode, const char *cmd) -{ - /* - * Enable soft reset to assert RSTOUTn. - */ - writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK); - - /* - * Assert soft reset. - */ - writel(SOFT_RESET, SYSTEM_SOFT_RESET); - - while (1) - ; -} diff --git a/ANDROID_3.4.5/arch/arm/mach-mv78xx0/common.h b/ANDROID_3.4.5/arch/arm/mach-mv78xx0/common.h deleted file mode 100644 index 507c767d..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-mv78xx0/common.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * arch/arm/mach-mv78xx0/common.h - * - * Core functions for Marvell MV78xx0 SoCs - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ARCH_MV78XX0_COMMON_H -#define __ARCH_MV78XX0_COMMON_H - -struct mv643xx_eth_platform_data; -struct mv_sata_platform_data; - -/* - * Basic MV78xx0 init functions used early by machine-setup. - */ -int mv78xx0_core_index(void); -void mv78xx0_map_io(void); -void mv78xx0_init(void); -void mv78xx0_init_early(void); -void mv78xx0_init_irq(void); - -void mv78xx0_setup_cpu_mbus(void); -void mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size, - int maj, int min); -void mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size, - int maj, int min); - -void mv78xx0_pcie_id(u32 *dev, u32 *rev); - -void mv78xx0_ehci0_init(void); -void mv78xx0_ehci1_init(void); -void mv78xx0_ehci2_init(void); -void mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data); -void mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data); -void mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data); -void mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data); -void mv78xx0_pcie_init(int init_port0, int init_port1); -void mv78xx0_sata_init(struct mv_sata_platform_data *sata_data); -void mv78xx0_uart0_init(void); -void mv78xx0_uart1_init(void); -void mv78xx0_uart2_init(void); -void mv78xx0_uart3_init(void); -void mv78xx0_i2c_init(void); -void mv78xx0_restart(char, const char *); - -extern struct sys_timer mv78xx0_timer; - - -#endif diff --git a/ANDROID_3.4.5/arch/arm/mach-mv78xx0/db78x00-bp-setup.c b/ANDROID_3.4.5/arch/arm/mach-mv78xx0/db78x00-bp-setup.c deleted file mode 100644 index 4d6d48bf..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-mv78xx0/db78x00-bp-setup.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * arch/arm/mach-mv78xx0/db78x00-bp-setup.c - * - * Marvell DB-78x00-BP Development Board Setup - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/ata_platform.h> -#include <linux/mv643xx_eth.h> -#include <linux/ethtool.h> -#include <linux/i2c.h> -#include <mach/mv78xx0.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include "common.h" - -static struct mv643xx_eth_platform_data db78x00_ge00_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(8), -}; - -static struct mv643xx_eth_platform_data db78x00_ge01_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(9), -}; - -static struct mv643xx_eth_platform_data db78x00_ge10_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(10), -}; - -static struct mv643xx_eth_platform_data db78x00_ge11_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(11), -}; - -static struct mv_sata_platform_data db78x00_sata_data = { - .n_ports = 2, -}; - -static struct i2c_board_info __initdata db78x00_i2c_rtc = { - I2C_BOARD_INFO("ds1338", 0x68), -}; - - -static void __init db78x00_init(void) -{ - /* - * Basic MV78xx0 setup. Needs to be called early. - */ - mv78xx0_init(); - - /* - * Partition on-chip peripherals between the two CPU cores. - */ - if (mv78xx0_core_index() == 0) { - mv78xx0_ehci0_init(); - mv78xx0_ehci1_init(); - mv78xx0_ehci2_init(); - mv78xx0_ge00_init(&db78x00_ge00_data); - mv78xx0_ge01_init(&db78x00_ge01_data); - mv78xx0_ge10_init(&db78x00_ge10_data); - mv78xx0_ge11_init(&db78x00_ge11_data); - mv78xx0_sata_init(&db78x00_sata_data); - mv78xx0_uart0_init(); - mv78xx0_uart2_init(); - mv78xx0_i2c_init(); - i2c_register_board_info(0, &db78x00_i2c_rtc, 1); - } else { - mv78xx0_uart1_init(); - mv78xx0_uart3_init(); - } -} - -static int __init db78x00_pci_init(void) -{ - if (machine_is_db78x00_bp()) { - /* - * Assign the x16 PCIe slot on the board to CPU core - * #0, and let CPU core #1 have the four x1 slots. - */ - if (mv78xx0_core_index() == 0) - mv78xx0_pcie_init(0, 1); - else - mv78xx0_pcie_init(1, 0); - } - - return 0; -} -subsys_initcall(db78x00_pci_init); - -MACHINE_START(DB78X00_BP, "Marvell DB-78x00-BP Development Board") - /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */ - .atag_offset = 0x100, - .init_machine = db78x00_init, - .map_io = mv78xx0_map_io, - .init_early = mv78xx0_init_early, - .init_irq = mv78xx0_init_irq, - .timer = &mv78xx0_timer, - .restart = mv78xx0_restart, -MACHINE_END diff --git a/ANDROID_3.4.5/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h b/ANDROID_3.4.5/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h deleted file mode 100644 index eb187e0e..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * arch/arm/mach-mv78xx0/include/mach/bridge-regs.h - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_BRIDGE_REGS_H -#define __ASM_ARCH_BRIDGE_REGS_H - -#include <mach/mv78xx0.h> - -#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104) -#define L2_WRITETHROUGH 0x00020000 - -#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) -#define SOFT_RESET_OUT_EN 0x00000004 - -#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) -#define SOFT_RESET 0x00000001 - -#define BRIDGE_INT_TIMER1_CLR (~0x0004) - -#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) -#define IRQ_CAUSE_ERR_OFF 0x0000 -#define IRQ_CAUSE_LOW_OFF 0x0004 -#define IRQ_CAUSE_HIGH_OFF 0x0008 -#define IRQ_MASK_ERR_OFF 0x000c -#define IRQ_MASK_LOW_OFF 0x0010 -#define IRQ_MASK_HIGH_OFF 0x0014 - -#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) -#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE | 0x0300) - -#endif diff --git a/ANDROID_3.4.5/arch/arm/mach-mv78xx0/include/mach/debug-macro.S b/ANDROID_3.4.5/arch/arm/mach-mv78xx0/include/mach/debug-macro.S deleted file mode 100644 index a7df02b0..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-mv78xx0/include/mach/debug-macro.S +++ /dev/null @@ -1,19 +0,0 @@ -/* - * arch/arm/mach-mv78xx0/include/mach/debug-macro.S - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <mach/mv78xx0.h> - - .macro addruart, rp, rv, tmp - ldr \rp, =MV78XX0_REGS_PHYS_BASE - ldr \rv, =MV78XX0_REGS_VIRT_BASE - orr \rp, \rp, #0x00012000 - orr \rv, \rv, #0x00012000 - .endm - -#define UART_SHIFT 2 -#include <asm/hardware/debug-8250.S> diff --git a/ANDROID_3.4.5/arch/arm/mach-mv78xx0/include/mach/entry-macro.S b/ANDROID_3.4.5/arch/arm/mach-mv78xx0/include/mach/entry-macro.S deleted file mode 100644 index 6b1f088e..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-mv78xx0/include/mach/entry-macro.S +++ /dev/null @@ -1,41 +0,0 @@ -/* - * arch/arm/mach-mv78xx0/include/mach/entry-macro.S - * - * Low-level IRQ helper macros for Marvell MV78xx0 platforms - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <mach/bridge-regs.h> - - .macro get_irqnr_preamble, base, tmp - ldr \base, =IRQ_VIRT_BASE - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - @ check low interrupts - ldr \irqstat, [\base, #IRQ_CAUSE_LOW_OFF] - ldr \tmp, [\base, #IRQ_MASK_LOW_OFF] - mov \irqnr, #31 - ands \irqstat, \irqstat, \tmp - bne 1001f - - @ if no low interrupts set, check high interrupts - ldr \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF] - ldr \tmp, [\base, #IRQ_MASK_HIGH_OFF] - mov \irqnr, #63 - ands \irqstat, \irqstat, \tmp - bne 1001f - - @ if no high interrupts set, check error interrupts - ldr \irqstat, [\base, #IRQ_CAUSE_ERR_OFF] - ldr \tmp, [\base, #IRQ_MASK_ERR_OFF] - mov \irqnr, #95 - ands \irqstat, \irqstat, \tmp - - @ find first active interrupt source -1001: clzne \irqstat, \irqstat - subne \irqnr, \irqnr, \irqstat - .endm diff --git a/ANDROID_3.4.5/arch/arm/mach-mv78xx0/include/mach/gpio.h b/ANDROID_3.4.5/arch/arm/mach-mv78xx0/include/mach/gpio.h deleted file mode 100644 index 77e1b843..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-mv78xx0/include/mach/gpio.h +++ /dev/null @@ -1,9 +0,0 @@ -/* - * arch/asm-arm/mach-mv78xx0/include/mach/gpio.h - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <plat/gpio.h> diff --git a/ANDROID_3.4.5/arch/arm/mach-mv78xx0/include/mach/hardware.h b/ANDROID_3.4.5/arch/arm/mach-mv78xx0/include/mach/hardware.h deleted file mode 100644 index 67cab0a0..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-mv78xx0/include/mach/hardware.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * arch/arm/mach-mv78xx0/include/mach/hardware.h - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include "mv78xx0.h" - -#endif diff --git a/ANDROID_3.4.5/arch/arm/mach-mv78xx0/include/mach/io.h b/ANDROID_3.4.5/arch/arm/mach-mv78xx0/include/mach/io.h deleted file mode 100644 index c7d9d00d..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-mv78xx0/include/mach/io.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * arch/arm/mach-mv78xx0/include/mach/io.h - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_IO_H -#define __ASM_ARCH_IO_H - -#include "mv78xx0.h" - -#define IO_SPACE_LIMIT 0xffffffff - -static inline void __iomem *__io(unsigned long addr) -{ - return (void __iomem *)((addr - MV78XX0_PCIE_IO_PHYS_BASE(0)) - + MV78XX0_PCIE_IO_VIRT_BASE(0)); -} - -#define __io(a) __io(a) - -#endif diff --git a/ANDROID_3.4.5/arch/arm/mach-mv78xx0/include/mach/irqs.h b/ANDROID_3.4.5/arch/arm/mach-mv78xx0/include/mach/irqs.h deleted file mode 100644 index fa1d4221..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-mv78xx0/include/mach/irqs.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * arch/arm/mach-mv78xx0/include/mach/irqs.h - * - * IRQ definitions for Marvell MV78xx0 SoCs - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_IRQS_H -#define __ASM_ARCH_IRQS_H - -/* - * MV78xx0 Low Interrupt Controller - */ -#define IRQ_MV78XX0_ERR 0 -#define IRQ_MV78XX0_SPI 1 -#define IRQ_MV78XX0_I2C_0 2 -#define IRQ_MV78XX0_I2C_1 3 -#define IRQ_MV78XX0_IDMA_0 4 -#define IRQ_MV78XX0_IDMA_1 5 -#define IRQ_MV78XX0_IDMA_2 6 -#define IRQ_MV78XX0_IDMA_3 7 -#define IRQ_MV78XX0_TIMER_0 8 -#define IRQ_MV78XX0_TIMER_1 9 -#define IRQ_MV78XX0_TIMER_2 10 -#define IRQ_MV78XX0_TIMER_3 11 -#define IRQ_MV78XX0_UART_0 12 -#define IRQ_MV78XX0_UART_1 13 -#define IRQ_MV78XX0_UART_2 14 -#define IRQ_MV78XX0_UART_3 15 -#define IRQ_MV78XX0_USB_0 16 -#define IRQ_MV78XX0_USB_1 17 -#define IRQ_MV78XX0_USB_2 18 -#define IRQ_MV78XX0_CRYPTO 19 -#define IRQ_MV78XX0_SDIO_0 20 -#define IRQ_MV78XX0_SDIO_1 21 -#define IRQ_MV78XX0_XOR_0 22 -#define IRQ_MV78XX0_XOR_1 23 -#define IRQ_MV78XX0_I2S_0 24 -#define IRQ_MV78XX0_I2S_1 25 -#define IRQ_MV78XX0_SATA 26 -#define IRQ_MV78XX0_TDMI 27 - -/* - * MV78xx0 High Interrupt Controller - */ -#define IRQ_MV78XX0_PCIE_00 32 -#define IRQ_MV78XX0_PCIE_01 33 -#define IRQ_MV78XX0_PCIE_02 34 -#define IRQ_MV78XX0_PCIE_03 35 -#define IRQ_MV78XX0_PCIE_10 36 -#define IRQ_MV78XX0_PCIE_11 37 -#define IRQ_MV78XX0_PCIE_12 38 -#define IRQ_MV78XX0_PCIE_13 39 -#define IRQ_MV78XX0_GE00_SUM 40 -#define IRQ_MV78XX0_GE00_RX 41 -#define IRQ_MV78XX0_GE00_TX 42 -#define IRQ_MV78XX0_GE00_MISC 43 -#define IRQ_MV78XX0_GE01_SUM 44 -#define IRQ_MV78XX0_GE01_RX 45 -#define IRQ_MV78XX0_GE01_TX 46 -#define IRQ_MV78XX0_GE01_MISC 47 -#define IRQ_MV78XX0_GE10_SUM 48 -#define IRQ_MV78XX0_GE10_RX 49 -#define IRQ_MV78XX0_GE10_TX 50 -#define IRQ_MV78XX0_GE10_MISC 51 -#define IRQ_MV78XX0_GE11_SUM 52 -#define IRQ_MV78XX0_GE11_RX 53 -#define IRQ_MV78XX0_GE11_TX 54 -#define IRQ_MV78XX0_GE11_MISC 55 -#define IRQ_MV78XX0_GPIO_0_7 56 -#define IRQ_MV78XX0_GPIO_8_15 57 -#define IRQ_MV78XX0_GPIO_16_23 58 -#define IRQ_MV78XX0_GPIO_24_31 59 -#define IRQ_MV78XX0_DB_IN 60 -#define IRQ_MV78XX0_DB_OUT 61 - -/* - * MV78xx0 Error Interrupt Controller - */ -#define IRQ_MV78XX0_GE_ERR 70 - -/* - * MV78XX0 General Purpose Pins - */ -#define IRQ_MV78XX0_GPIO_START 96 -#define NR_GPIO_IRQS 32 - -#define NR_IRQS (IRQ_MV78XX0_GPIO_START + NR_GPIO_IRQS) - - -#endif diff --git a/ANDROID_3.4.5/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/ANDROID_3.4.5/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h deleted file mode 100644 index e807c4c5..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h +++ /dev/null @@ -1,123 +0,0 @@ -/* - * arch/arm/mach-mv78xx0/include/mach/mv78xx0.h - * - * Generic definitions for Marvell MV78xx0 SoC flavors: - * MV781x0 and MV782x0. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_MV78XX0_H -#define __ASM_ARCH_MV78XX0_H - -/* - * Marvell MV78xx0 address maps. - * - * phys - * c0000000 PCIe Memory space - * f0800000 PCIe #0 I/O space - * f0900000 PCIe #1 I/O space - * f0a00000 PCIe #2 I/O space - * f0b00000 PCIe #3 I/O space - * f0c00000 PCIe #4 I/O space - * f0d00000 PCIe #5 I/O space - * f0e00000 PCIe #6 I/O space - * f0f00000 PCIe #7 I/O space - * f1000000 on-chip peripheral registers - * - * virt phys size - * fe400000 f102x000 16K core-specific peripheral registers - * fe700000 f0800000 1M PCIe #0 I/O space - * fe800000 f0900000 1M PCIe #1 I/O space - * fe900000 f0a00000 1M PCIe #2 I/O space - * fea00000 f0b00000 1M PCIe #3 I/O space - * feb00000 f0c00000 1M PCIe #4 I/O space - * fec00000 f0d00000 1M PCIe #5 I/O space - * fed00000 f0e00000 1M PCIe #6 I/O space - * fee00000 f0f00000 1M PCIe #7 I/O space - * fef00000 f1000000 1M on-chip peripheral registers - */ -#define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000 -#define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000 -#define MV78XX0_CORE_REGS_VIRT_BASE 0xfe400000 -#define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000 -#define MV78XX0_CORE_REGS_SIZE SZ_16K - -#define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20)) -#define MV78XX0_PCIE_IO_VIRT_BASE(i) (0xfe700000 + ((i) << 20)) -#define MV78XX0_PCIE_IO_SIZE SZ_1M - -#define MV78XX0_REGS_PHYS_BASE 0xf1000000 -#define MV78XX0_REGS_VIRT_BASE 0xfef00000 -#define MV78XX0_REGS_SIZE SZ_1M - -#define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000 -#define MV78XX0_PCIE_MEM_SIZE 0x30000000 - -/* - * Core-specific peripheral registers. - */ -#define BRIDGE_VIRT_BASE (MV78XX0_CORE_REGS_VIRT_BASE) -#define BRIDGE_PHYS_BASE (MV78XX0_CORE_REGS_PHYS_BASE) - -/* - * Register Map - */ -#define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x00000) -#define DDR_WINDOW_CPU0_BASE (DDR_VIRT_BASE | 0x1500) -#define DDR_WINDOW_CPU1_BASE (DDR_VIRT_BASE | 0x1570) - -#define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x10000) -#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x10000) -#define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE | 0x0030) -#define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE | 0x0034) -#define GPIO_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x0100) -#define I2C_0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1000) -#define I2C_1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1100) -#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000) -#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000) -#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100) -#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100) -#define UART2_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2200) -#define UART2_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2200) -#define UART3_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2300) -#define UART3_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2300) - -#define GE10_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x30000) -#define GE11_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x34000) - -#define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x40000) -#define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x44000) -#define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x48000) -#define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x4c000) - -#define USB0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x50000) -#define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x51000) -#define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x52000) - -#define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x70000) -#define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x74000) - -#define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x80000) -#define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x84000) -#define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x88000) -#define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x8c000) - -#define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0xa0000) - -/* - * Supported devices and revisions. - */ -#define MV78X00_Z0_DEV_ID 0x6381 -#define MV78X00_REV_Z0 1 - -#define MV78100_DEV_ID 0x7810 -#define MV78100_REV_A0 1 -#define MV78100_REV_A1 2 - -#define MV78200_DEV_ID 0x7820 -#define MV78200_REV_A0 1 - -#endif diff --git a/ANDROID_3.4.5/arch/arm/mach-mv78xx0/include/mach/timex.h b/ANDROID_3.4.5/arch/arm/mach-mv78xx0/include/mach/timex.h deleted file mode 100644 index 0e8c443c..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-mv78xx0/include/mach/timex.h +++ /dev/null @@ -1,9 +0,0 @@ -/* - * arch/arm/mach-mv78xx0/include/mach/timex.h - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#define CLOCK_TICK_RATE (100 * HZ) diff --git a/ANDROID_3.4.5/arch/arm/mach-mv78xx0/include/mach/uncompress.h b/ANDROID_3.4.5/arch/arm/mach-mv78xx0/include/mach/uncompress.h deleted file mode 100644 index 36526429..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-mv78xx0/include/mach/uncompress.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * arch/arm/mach-mv78xx0/include/mach/uncompress.h - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/serial_reg.h> -#include <mach/mv78xx0.h> - -#define SERIAL_BASE ((unsigned char *)UART0_PHYS_BASE) - -static void putc(const char c) -{ - unsigned char *base = SERIAL_BASE; - int i; - - for (i = 0; i < 0x1000; i++) { - if (base[UART_LSR << 2] & UART_LSR_THRE) - break; - barrier(); - } - - base[UART_TX << 2] = c; -} - -static void flush(void) -{ - unsigned char *base = SERIAL_BASE; - unsigned char mask; - int i; - - mask = UART_LSR_TEMT | UART_LSR_THRE; - - for (i = 0; i < 0x1000; i++) { - if ((base[UART_LSR << 2] & mask) == mask) - break; - barrier(); - } -} - -/* - * nothing to do - */ -#define arch_decomp_setup() -#define arch_decomp_wdog() diff --git a/ANDROID_3.4.5/arch/arm/mach-mv78xx0/irq.c b/ANDROID_3.4.5/arch/arm/mach-mv78xx0/irq.c deleted file mode 100644 index e421b701..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-mv78xx0/irq.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * arch/arm/mach-mv78xx0/irq.c - * - * MV78xx0 IRQ handling. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ -#include <linux/gpio.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/pci.h> -#include <linux/irq.h> -#include <mach/bridge-regs.h> -#include <plat/irq.h> -#include "common.h" - -static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) -{ - BUG_ON(irq < IRQ_MV78XX0_GPIO_0_7 || irq > IRQ_MV78XX0_GPIO_24_31); - - orion_gpio_irq_handler((irq - IRQ_MV78XX0_GPIO_0_7) << 3); -} - -void __init mv78xx0_init_irq(void) -{ - orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)); - orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)); - orion_irq_init(64, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF)); - - /* - * Initialize gpiolib for GPIOs 0-31. (The GPIO interrupt mask - * registers for core #1 are at an offset of 0x18 from those of - * core #0.) - */ - orion_gpio_init(0, 32, GPIO_VIRT_BASE, - mv78xx0_core_index() ? 0x18 : 0, - IRQ_MV78XX0_GPIO_START); - irq_set_chained_handler(IRQ_MV78XX0_GPIO_0_7, gpio_irq_handler); - irq_set_chained_handler(IRQ_MV78XX0_GPIO_8_15, gpio_irq_handler); - irq_set_chained_handler(IRQ_MV78XX0_GPIO_16_23, gpio_irq_handler); - irq_set_chained_handler(IRQ_MV78XX0_GPIO_24_31, gpio_irq_handler); -} diff --git a/ANDROID_3.4.5/arch/arm/mach-mv78xx0/mpp.c b/ANDROID_3.4.5/arch/arm/mach-mv78xx0/mpp.c deleted file mode 100644 index df503421..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-mv78xx0/mpp.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * arch/arm/mach-mv78x00/mpp.c - * - * MPP functions for Marvell MV78x00 SoCs - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ -#include <linux/gpio.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/io.h> -#include <plat/mpp.h> -#include <mach/hardware.h> -#include "common.h" -#include "mpp.h" - -static unsigned int __init mv78xx0_variant(void) -{ - u32 dev, rev; - - mv78xx0_pcie_id(&dev, &rev); - - if (dev == MV78100_DEV_ID && rev >= MV78100_REV_A0) - return MPP_78100_A0_MASK; - - printk(KERN_ERR "MPP setup: unknown mv78x00 variant " - "(dev %#x rev %#x)\n", dev, rev); - return 0; -} - -void __init mv78xx0_mpp_conf(unsigned int *mpp_list) -{ - orion_mpp_conf(mpp_list, mv78xx0_variant(), - MPP_MAX, DEV_BUS_VIRT_BASE); -} diff --git a/ANDROID_3.4.5/arch/arm/mach-mv78xx0/mpp.h b/ANDROID_3.4.5/arch/arm/mach-mv78xx0/mpp.h deleted file mode 100644 index 3752302a..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-mv78xx0/mpp.h +++ /dev/null @@ -1,341 +0,0 @@ -/* - * linux/arch/arm/mach-mv78xx0/mpp.h -- Multi Purpose Pins - * - * - * sebastien requiem <sebastien@requiem.fr> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __MV78X00_MPP_H -#define __MV78X00_MPP_H - -#define MPP(_num, _sel, _in, _out, _78100_A0) (\ - /* MPP number */ ((_num) & 0xff) | \ - /* MPP select value */ (((_sel) & 0xf) << 8) | \ - /* may be input signal */ ((!!(_in)) << 12) | \ - /* may be output signal */ ((!!(_out)) << 13) | \ - /* available on A0 */ ((!!(_78100_A0)) << 14)) - - /* num sel i o 78100_A0 */ - -#define MPP_78100_A0_MASK MPP(0, 0x0, 0, 0, 1) - -#define MPP0_GPIO MPP(0, 0x0, 1, 1, 1) -#define MPP0_GE0_COL MPP(0, 0x1, 0, 0, 1) -#define MPP0_GE1_TXCLK MPP(0, 0x2, 0, 0, 1) -#define MPP0_UNUSED MPP(0, 0x3, 0, 0, 1) - -#define MPP1_GPIO MPP(1, 0x0, 1, 1, 1) -#define MPP1_GE0_RXERR MPP(1, 0x1, 0, 0, 1) -#define MPP1_GE1_TXCTL MPP(1, 0x2, 0, 0, 1) -#define MPP1_UNUSED MPP(1, 0x3, 0, 0, 1) - -#define MPP2_GPIO MPP(2, 0x0, 1, 1, 1) -#define MPP2_GE0_CRS MPP(2, 0x1, 0, 0, 1) -#define MPP2_GE1_RXCTL MPP(2, 0x2, 0, 0, 1) -#define MPP2_UNUSED MPP(2, 0x3, 0, 0, 1) - -#define MPP3_GPIO MPP(3, 0x0, 1, 1, 1) -#define MPP3_GE0_TXERR MPP(3, 0x1, 0, 0, 1) -#define MPP3_GE1_RXCLK MPP(3, 0x2, 0, 0, 1) -#define MPP3_UNUSED MPP(3, 0x3, 0, 0, 1) - -#define MPP4_GPIO MPP(4, 0x0, 1, 1, 1) -#define MPP4_GE0_TXD4 MPP(4, 0x1, 0, 0, 1) -#define MPP4_GE1_TXD0 MPP(4, 0x2, 0, 0, 1) -#define MPP4_UNUSED MPP(4, 0x3, 0, 0, 1) - -#define MPP5_GPIO MPP(5, 0x0, 1, 1, 1) -#define MPP5_GE0_TXD5 MPP(5, 0x1, 0, 0, 1) -#define MPP5_GE1_TXD1 MPP(5, 0x2, 0, 0, 1) -#define MPP5_UNUSED MPP(5, 0x3, 0, 0, 1) - -#define MPP6_GPIO MPP(6, 0x0, 1, 1, 1) -#define MPP6_GE0_TXD6 MPP(6, 0x1, 0, 0, 1) -#define MPP6_GE1_TXD2 MPP(6, 0x2, 0, 0, 1) -#define MPP6_UNUSED MPP(6, 0x3, 0, 0, 1) - -#define MPP7_GPIO MPP(7, 0x0, 1, 1, 1) -#define MPP7_GE0_TXD7 MPP(7, 0x1, 0, 0, 1) -#define MPP7_GE1_TXD3 MPP(7, 0x2, 0, 0, 1) -#define MPP7_UNUSED MPP(7, 0x3, 0, 0, 1) - -#define MPP8_GPIO MPP(8, 0x0, 1, 1, 1) -#define MPP8_GE0_RXD4 MPP(8, 0x1, 0, 0, 1) -#define MPP8_GE1_RXD0 MPP(8, 0x2, 0, 0, 1) -#define MPP8_UNUSED MPP(8, 0x3, 0, 0, 1) - -#define MPP9_GPIO MPP(9, 0x0, 1, 1, 1) -#define MPP9_GE0_RXD5 MPP(9, 0x1, 0, 0, 1) -#define MPP9_GE1_RXD1 MPP(9, 0x2, 0, 0, 1) -#define MPP9_UNUSED MPP(9, 0x3, 0, 0, 1) - -#define MPP10_GPIO MPP(10, 0x0, 1, 1, 1) -#define MPP10_GE0_RXD6 MPP(10, 0x1, 0, 0, 1) -#define MPP10_GE1_RXD2 MPP(10, 0x2, 0, 0, 1) -#define MPP10_UNUSED MPP(10, 0x3, 0, 0, 1) - -#define MPP11_GPIO MPP(11, 0x0, 1, 1, 1) -#define MPP11_GE0_RXD7 MPP(11, 0x1, 0, 0, 1) -#define MPP11_GE1_RXD3 MPP(11, 0x2, 0, 0, 1) -#define MPP11_UNUSED MPP(11, 0x3, 0, 0, 1) - -#define MPP12_GPIO MPP(12, 0x0, 1, 1, 1) -#define MPP12_M_BB MPP(12, 0x3, 0, 0, 1) -#define MPP12_UA0_CTSn MPP(12, 0x4, 0, 0, 1) -#define MPP12_NAND_FLASH_REn0 MPP(12, 0x5, 0, 0, 1) -#define MPP12_TDM0_SCSn MPP(12, 0X6, 0, 0, 1) -#define MPP12_UNUSED MPP(12, 0x1, 0, 0, 1) - -#define MPP13_GPIO MPP(13, 0x0, 1, 1, 1) -#define MPP13_SYSRST_OUTn MPP(13, 0x3, 0, 0, 1) -#define MPP13_UA0_RTSn MPP(13, 0x4, 0, 0, 1) -#define MPP13_NAN_FLASH_WEn0 MPP(13, 0x5, 0, 0, 1) -#define MPP13_TDM_SCLK MPP(13, 0x6, 0, 0, 1) -#define MPP13_UNUSED MPP(13, 0x1, 0, 0, 1) - -#define MPP14_GPIO MPP(14, 0x0, 1, 1, 1) -#define MPP14_SATA1_ACTn MPP(14, 0x3, 0, 0, 1) -#define MPP14_UA1_CTSn MPP(14, 0x4, 0, 0, 1) -#define MPP14_NAND_FLASH_REn1 MPP(14, 0x5, 0, 0, 1) -#define MPP14_TDM_SMOSI MPP(14, 0x6, 0, 0, 1) -#define MPP14_UNUSED MPP(14, 0x1, 0, 0, 1) - -#define MPP15_GPIO MPP(15, 0x0, 1, 1, 1) -#define MPP15_SATA0_ACTn MPP(15, 0x3, 0, 0, 1) -#define MPP15_UA1_RTSn MPP(15, 0x4, 0, 0, 1) -#define MPP15_NAND_FLASH_WEn1 MPP(15, 0x5, 0, 0, 1) -#define MPP15_TDM_SMISO MPP(15, 0x6, 0, 0, 1) -#define MPP15_UNUSED MPP(15, 0x1, 0, 0, 1) - -#define MPP16_GPIO MPP(16, 0x0, 1, 1, 1) -#define MPP16_SATA1_PRESENTn MPP(16, 0x3, 0, 0, 1) -#define MPP16_UA2_TXD MPP(16, 0x4, 0, 0, 1) -#define MPP16_NAND_FLASH_REn3 MPP(16, 0x5, 0, 0, 1) -#define MPP16_TDM_INTn MPP(16, 0x6, 0, 0, 1) -#define MPP16_UNUSED MPP(16, 0x1, 0, 0, 1) - - -#define MPP17_GPIO MPP(17, 0x0, 1, 1, 1) -#define MPP17_SATA0_PRESENTn MPP(17, 0x3, 0, 0, 1) -#define MPP17_UA2_RXD MPP(17, 0x4, 0, 0, 1) -#define MPP17_NAND_FLASH_WEn3 MPP(17, 0x5, 0, 0, 1) -#define MPP17_TDM_RSTn MPP(17, 0x6, 0, 0, 1) -#define MPP17_UNUSED MPP(17, 0x1, 0, 0, 1) - - -#define MPP18_GPIO MPP(18, 0x0, 1, 1, 1) -#define MPP18_UA0_CTSn MPP(18, 0x4, 0, 0, 1) -#define MPP18_BOOT_FLASH_REn MPP(18, 0x5, 0, 0, 1) -#define MPP18_UNUSED MPP(18, 0x1, 0, 0, 1) - - - -#define MPP19_GPIO MPP(19, 0x0, 1, 1, 1) -#define MPP19_UA0_CTSn MPP(19, 0x4, 0, 0, 1) -#define MPP19_BOOT_FLASH_WEn MPP(19, 0x5, 0, 0, 1) -#define MPP19_UNUSED MPP(19, 0x1, 0, 0, 1) - - -#define MPP20_GPIO MPP(20, 0x0, 1, 1, 1) -#define MPP20_UA1_CTSs MPP(20, 0x4, 0, 0, 1) -#define MPP20_TDM_PCLK MPP(20, 0x6, 0, 0, 0) -#define MPP20_UNUSED MPP(20, 0x1, 0, 0, 1) - - - -#define MPP21_GPIO MPP(21, 0x0, 1, 1, 1) -#define MPP21_UA1_CTSs MPP(21, 0x4, 0, 0, 1) -#define MPP21_TDM_FSYNC MPP(21, 0x6, 0, 0, 0) -#define MPP21_UNUSED MPP(21, 0x1, 0, 0, 1) - - - -#define MPP22_GPIO MPP(22, 0x0, 1, 1, 1) -#define MPP22_UA3_TDX MPP(22, 0x4, 0, 0, 1) -#define MPP22_NAND_FLASH_REn2 MPP(22, 0x5, 0, 0, 1) -#define MPP22_TDM_DRX MPP(22, 0x6, 0, 0, 1) -#define MPP22_UNUSED MPP(22, 0x1, 0, 0, 1) - - - -#define MPP23_GPIO MPP(23, 0x0, 1, 1, 1) -#define MPP23_UA3_RDX MPP(23, 0x4, 0, 0, 1) -#define MPP23_NAND_FLASH_WEn2 MPP(23, 0x5, 0, 0, 1) -#define MPP23_TDM_DTX MPP(23, 0x6, 0, 0, 1) -#define MPP23_UNUSED MPP(23, 0x1, 0, 0, 1) - - -#define MPP24_GPIO MPP(24, 0x0, 1, 1, 1) -#define MPP24_UA2_TXD MPP(24, 0x4, 0, 0, 1) -#define MPP24_TDM_INTn MPP(24, 0x6, 0, 0, 1) -#define MPP24_UNUSED MPP(24, 0x1, 0, 0, 1) - - -#define MPP25_GPIO MPP(25, 0x0, 1, 1, 1) -#define MPP25_UA2_RXD MPP(25, 0x4, 0, 0, 1) -#define MPP25_TDM_RSTn MPP(25, 0x6, 0, 0, 1) -#define MPP25_UNUSED MPP(25, 0x1, 0, 0, 1) - - -#define MPP26_GPIO MPP(26, 0x0, 1, 1, 1) -#define MPP26_UA2_CTSn MPP(26, 0x4, 0, 0, 1) -#define MPP26_TDM_PCLK MPP(26, 0x6, 0, 0, 1) -#define MPP26_UNUSED MPP(26, 0x1, 0, 0, 1) - - -#define MPP27_GPIO MPP(27, 0x0, 1, 1, 1) -#define MPP27_UA2_RTSn MPP(27, 0x4, 0, 0, 1) -#define MPP27_TDM_FSYNC MPP(27, 0x6, 0, 0, 1) -#define MPP27_UNUSED MPP(27, 0x1, 0, 0, 1) - - -#define MPP28_GPIO MPP(28, 0x0, 1, 1, 1) -#define MPP28_UA3_TXD MPP(28, 0x4, 0, 0, 1) -#define MPP28_TDM_DRX MPP(28, 0x6, 0, 0, 1) -#define MPP28_UNUSED MPP(28, 0x1, 0, 0, 1) - -#define MPP29_GPIO MPP(29, 0x0, 1, 1, 1) -#define MPP29_UA3_RXD MPP(29, 0x4, 0, 0, 1) -#define MPP29_SYSRST_OUTn MPP(29, 0x5, 0, 0, 1) -#define MPP29_TDM_DTX MPP(29, 0x6, 0, 0, 1) -#define MPP29_UNUSED MPP(29, 0x1, 0, 0, 1) - -#define MPP30_GPIO MPP(30, 0x0, 1, 1, 1) -#define MPP30_UA3_CTSn MPP(30, 0x4, 0, 0, 1) -#define MPP30_UNUSED MPP(30, 0x1, 0, 0, 1) - -#define MPP31_GPIO MPP(31, 0x0, 1, 1, 1) -#define MPP31_UA3_RTSn MPP(31, 0x4, 0, 0, 1) -#define MPP31_TDM1_SCSn MPP(31, 0x6, 0, 0, 1) -#define MPP31_UNUSED MPP(31, 0x1, 0, 0, 1) - - -#define MPP32_GPIO MPP(32, 0x1, 1, 1, 1) -#define MPP32_UA3_TDX MPP(32, 0x4, 0, 0, 1) -#define MPP32_SYSRST_OUTn MPP(32, 0x5, 0, 0, 1) -#define MPP32_TDM0_RXQ MPP(32, 0x6, 0, 0, 1) -#define MPP32_UNUSED MPP(32, 0x3, 0, 0, 1) - - -#define MPP33_GPIO MPP(33, 0x1, 1, 1, 1) -#define MPP33_UA3_RDX MPP(33, 0x4, 0, 0, 1) -#define MPP33_TDM0_TXQ MPP(33, 0x6, 0, 0, 1) -#define MPP33_UNUSED MPP(33, 0x3, 0, 0, 1) - - - -#define MPP34_GPIO MPP(34, 0x1, 1, 1, 1) -#define MPP34_UA2_TDX MPP(34, 0x4, 0, 0, 1) -#define MPP34_TDM1_RXQ MPP(34, 0x6, 0, 0, 1) -#define MPP34_UNUSED MPP(34, 0x3, 0, 0, 1) - - - -#define MPP35_GPIO MPP(35, 0x1, 1, 1, 1) -#define MPP35_UA2_RDX MPP(35, 0x4, 0, 0, 1) -#define MPP35_TDM1_TXQ MPP(35, 0x6, 0, 0, 1) -#define MPP35_UNUSED MPP(35, 0x3, 0, 0, 1) - -#define MPP36_GPIO MPP(36, 0x1, 1, 1, 1) -#define MPP36_UA0_CTSn MPP(36, 0x2, 0, 0, 1) -#define MPP36_UA2_TDX MPP(36, 0x4, 0, 0, 1) -#define MPP36_TDM0_SCSn MPP(36, 0x6, 0, 0, 1) -#define MPP36_UNUSED MPP(36, 0x3, 0, 0, 1) - - -#define MPP37_GPIO MPP(37, 0x1, 1, 1, 1) -#define MPP37_UA0_RTSn MPP(37, 0x2, 0, 0, 1) -#define MPP37_UA2_RXD MPP(37, 0x4, 0, 0, 1) -#define MPP37_SYSRST_OUTn MPP(37, 0x5, 0, 0, 1) -#define MPP37_TDM_SCLK MPP(37, 0x6, 0, 0, 1) -#define MPP37_UNUSED MPP(37, 0x3, 0, 0, 1) - - - - -#define MPP38_GPIO MPP(38, 0x1, 1, 1, 1) -#define MPP38_UA1_CTSn MPP(38, 0x2, 0, 0, 1) -#define MPP38_UA3_TXD MPP(38, 0x4, 0, 0, 1) -#define MPP38_SYSRST_OUTn MPP(38, 0x5, 0, 0, 1) -#define MPP38_TDM_SMOSI MPP(38, 0x6, 0, 0, 1) -#define MPP38_UNUSED MPP(38, 0x3, 0, 0, 1) - - - - -#define MPP39_GPIO MPP(39, 0x1, 1, 1, 1) -#define MPP39_UA1_RTSn MPP(39, 0x2, 0, 0, 1) -#define MPP39_UA3_RXD MPP(39, 0x4, 0, 0, 1) -#define MPP39_SYSRST_OUTn MPP(39, 0x5, 0, 0, 1) -#define MPP39_TDM_SMISO MPP(39, 0x6, 0, 0, 1) -#define MPP39_UNUSED MPP(39, 0x3, 0, 0, 1) - - - -#define MPP40_GPIO MPP(40, 0x1, 1, 1, 1) -#define MPP40_TDM_INTn MPP(40, 0x6, 0, 0, 1) -#define MPP40_UNUSED MPP(40, 0x0, 0, 0, 1) - - - -#define MPP41_GPIO MPP(41, 0x1, 1, 1, 1) -#define MPP41_TDM_RSTn MPP(41, 0x6, 0, 0, 1) -#define MPP41_UNUSED MPP(41, 0x0, 0, 0, 1) - - - -#define MPP42_GPIO MPP(42, 0x1, 1, 1, 1) -#define MPP42_TDM_PCLK MPP(42, 0x6, 0, 0, 1) -#define MPP42_UNUSED MPP(42, 0x0, 0, 0, 1) - - - -#define MPP43_GPIO MPP(43, 0x1, 1, 1, 1) -#define MPP43_TDM_FSYNC MPP(43, 0x6, 0, 0, 1) -#define MPP43_UNUSED MPP(43, 0x0, 0, 0, 1) - - - -#define MPP44_GPIO MPP(44, 0x1, 1, 1, 1) -#define MPP44_TDM_DRX MPP(44, 0x6, 0, 0, 1) -#define MPP44_UNUSED MPP(44, 0x0, 0, 0, 1) - - - -#define MPP45_GPIO MPP(45, 0x1, 1, 1, 1) -#define MPP45_SATA0_ACTn MPP(45, 0x3, 0, 0, 1) -#define MPP45_TDM_DRX MPP(45, 0x6, 0, 0, 1) -#define MPP45_UNUSED MPP(45, 0x0, 0, 0, 1) - - -#define MPP46_GPIO MPP(46, 0x1, 1, 1, 1) -#define MPP46_TDM_SCSn MPP(46, 0x6, 0, 0, 1) -#define MPP46_UNUSED MPP(46, 0x0, 0, 0, 1) - - -#define MPP47_GPIO MPP(47, 0x1, 1, 1, 1) -#define MPP47_UNUSED MPP(47, 0x0, 0, 0, 1) - - - -#define MPP48_GPIO MPP(48, 0x1, 1, 1, 1) -#define MPP48_SATA1_ACTn MPP(48, 0x3, 0, 0, 1) -#define MPP48_UNUSED MPP(48, 0x2, 0, 0, 1) - - - -#define MPP49_GPIO MPP(49, 0x1, 1, 1, 1) -#define MPP49_SATA0_ACTn MPP(49, 0x3, 0, 0, 1) -#define MPP49_M_BB MPP(49, 0x4, 0, 0, 1) -#define MPP49_UNUSED MPP(49, 0x2, 0, 0, 1) - - -#define MPP_MAX 49 - -void mv78xx0_mpp_conf(unsigned int *mpp_list); - -#endif diff --git a/ANDROID_3.4.5/arch/arm/mach-mv78xx0/pcie.c b/ANDROID_3.4.5/arch/arm/mach-mv78xx0/pcie.c deleted file mode 100644 index df3e3805..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-mv78xx0/pcie.c +++ /dev/null @@ -1,323 +0,0 @@ -/* - * arch/arm/mach-mv78xx0/pcie.c - * - * PCIe functions for Marvell MV78xx0 SoCs - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/pci.h> -#include <video/vga.h> -#include <asm/irq.h> -#include <asm/mach/pci.h> -#include <plat/pcie.h> -#include <plat/addr-map.h> -#include "common.h" - -struct pcie_port { - u8 maj; - u8 min; - u8 root_bus_nr; - void __iomem *base; - spinlock_t conf_lock; - char io_space_name[16]; - char mem_space_name[16]; - struct resource res[2]; -}; - -static struct pcie_port pcie_port[8]; -static int num_pcie_ports; -static struct resource pcie_io_space; -static struct resource pcie_mem_space; - - -void __init mv78xx0_pcie_id(u32 *dev, u32 *rev) -{ - *dev = orion_pcie_dev_id((void __iomem *)PCIE00_VIRT_BASE); - *rev = orion_pcie_rev((void __iomem *)PCIE00_VIRT_BASE); -} - -static void __init mv78xx0_pcie_preinit(void) -{ - int i; - u32 size_each; - u32 start; - int win; - - pcie_io_space.name = "PCIe I/O Space"; - pcie_io_space.start = MV78XX0_PCIE_IO_PHYS_BASE(0); - pcie_io_space.end = - MV78XX0_PCIE_IO_PHYS_BASE(0) + MV78XX0_PCIE_IO_SIZE * 8 - 1; - pcie_io_space.flags = IORESOURCE_IO; - if (request_resource(&iomem_resource, &pcie_io_space)) - panic("can't allocate PCIe I/O space"); - - pcie_mem_space.name = "PCIe MEM Space"; - pcie_mem_space.start = MV78XX0_PCIE_MEM_PHYS_BASE; - pcie_mem_space.end = - MV78XX0_PCIE_MEM_PHYS_BASE + MV78XX0_PCIE_MEM_SIZE - 1; - pcie_mem_space.flags = IORESOURCE_MEM; - if (request_resource(&iomem_resource, &pcie_mem_space)) - panic("can't allocate PCIe MEM space"); - - for (i = 0; i < num_pcie_ports; i++) { - struct pcie_port *pp = pcie_port + i; - - snprintf(pp->io_space_name, sizeof(pp->io_space_name), - "PCIe %d.%d I/O", pp->maj, pp->min); - pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0; - pp->res[0].name = pp->io_space_name; - pp->res[0].start = MV78XX0_PCIE_IO_PHYS_BASE(i); - pp->res[0].end = pp->res[0].start + MV78XX0_PCIE_IO_SIZE - 1; - pp->res[0].flags = IORESOURCE_IO; - - snprintf(pp->mem_space_name, sizeof(pp->mem_space_name), - "PCIe %d.%d MEM", pp->maj, pp->min); - pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0; - pp->res[1].name = pp->mem_space_name; - pp->res[1].flags = IORESOURCE_MEM; - } - - switch (num_pcie_ports) { - case 0: - size_each = 0; - break; - - case 1: - size_each = 0x30000000; - break; - - case 2 ... 3: - size_each = 0x10000000; - break; - - case 4 ... 6: - size_each = 0x08000000; - break; - - case 7: - size_each = 0x04000000; - break; - - default: - panic("invalid number of PCIe ports"); - } - - start = MV78XX0_PCIE_MEM_PHYS_BASE; - for (i = 0; i < num_pcie_ports; i++) { - struct pcie_port *pp = pcie_port + i; - - pp->res[1].start = start; - pp->res[1].end = start + size_each - 1; - start += size_each; - } - - for (i = 0; i < num_pcie_ports; i++) { - struct pcie_port *pp = pcie_port + i; - - if (request_resource(&pcie_io_space, &pp->res[0])) - panic("can't allocate PCIe I/O sub-space"); - - if (request_resource(&pcie_mem_space, &pp->res[1])) - panic("can't allocate PCIe MEM sub-space"); - } - - win = 0; - for (i = 0; i < num_pcie_ports; i++) { - struct pcie_port *pp = pcie_port + i; - - mv78xx0_setup_pcie_io_win(win++, pp->res[0].start, - resource_size(&pp->res[0]), - pp->maj, pp->min); - - mv78xx0_setup_pcie_mem_win(win++, pp->res[1].start, - resource_size(&pp->res[1]), - pp->maj, pp->min); - } -} - -static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys) -{ - struct pcie_port *pp; - - if (nr >= num_pcie_ports) - return 0; - - pp = &pcie_port[nr]; - pp->root_bus_nr = sys->busnr; - - /* - * Generic PCIe unit setup. - */ - orion_pcie_set_local_bus_nr(pp->base, sys->busnr); - orion_pcie_setup(pp->base); - - pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset); - pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset); - - return 1; -} - -static struct pcie_port *bus_to_port(int bus) -{ - int i; - - for (i = num_pcie_ports - 1; i >= 0; i--) { - int rbus = pcie_port[i].root_bus_nr; - if (rbus != -1 && rbus <= bus) - break; - } - - return i >= 0 ? pcie_port + i : NULL; -} - -static int pcie_valid_config(struct pcie_port *pp, int bus, int dev) -{ - /* - * Don't go out when trying to access nonexisting devices - * on the local bus. - */ - if (bus == pp->root_bus_nr && dev > 1) - return 0; - - return 1; -} - -static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, - int size, u32 *val) -{ - struct pcie_port *pp = bus_to_port(bus->number); - unsigned long flags; - int ret; - - if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) { - *val = 0xffffffff; - return PCIBIOS_DEVICE_NOT_FOUND; - } - - spin_lock_irqsave(&pp->conf_lock, flags); - ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val); - spin_unlock_irqrestore(&pp->conf_lock, flags); - - return ret; -} - -static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, - int where, int size, u32 val) -{ - struct pcie_port *pp = bus_to_port(bus->number); - unsigned long flags; - int ret; - - if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) - return PCIBIOS_DEVICE_NOT_FOUND; - - spin_lock_irqsave(&pp->conf_lock, flags); - ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val); - spin_unlock_irqrestore(&pp->conf_lock, flags); - - return ret; -} - -static struct pci_ops pcie_ops = { - .read = pcie_rd_conf, - .write = pcie_wr_conf, -}; - -static void __devinit rc_pci_fixup(struct pci_dev *dev) -{ - /* - * Prevent enumeration of root complex. - */ - if (dev->bus->parent == NULL && dev->devfn == 0) { - int i; - - for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { - dev->resource[i].start = 0; - dev->resource[i].end = 0; - dev->resource[i].flags = 0; - } - } -} -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup); - -static struct pci_bus __init * -mv78xx0_pcie_scan_bus(int nr, struct pci_sys_data *sys) -{ - struct pci_bus *bus; - - if (nr < num_pcie_ports) { - bus = pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys, - &sys->resources); - } else { - bus = NULL; - BUG(); - } - - return bus; -} - -static int __init mv78xx0_pcie_map_irq(const struct pci_dev *dev, u8 slot, - u8 pin) -{ - struct pcie_port *pp = bus_to_port(dev->bus->number); - - return IRQ_MV78XX0_PCIE_00 + (pp->maj << 2) + pp->min; -} - -static struct hw_pci mv78xx0_pci __initdata = { - .nr_controllers = 8, - .preinit = mv78xx0_pcie_preinit, - .swizzle = pci_std_swizzle, - .setup = mv78xx0_pcie_setup, - .scan = mv78xx0_pcie_scan_bus, - .map_irq = mv78xx0_pcie_map_irq, -}; - -static void __init add_pcie_port(int maj, int min, unsigned long base) -{ - printk(KERN_INFO "MV78xx0 PCIe port %d.%d: ", maj, min); - - if (orion_pcie_link_up((void __iomem *)base)) { - struct pcie_port *pp = &pcie_port[num_pcie_ports++]; - - printk("link up\n"); - - pp->maj = maj; - pp->min = min; - pp->root_bus_nr = -1; - pp->base = (void __iomem *)base; - spin_lock_init(&pp->conf_lock); - memset(pp->res, 0, sizeof(pp->res)); - } else { - printk("link down, ignoring\n"); - } -} - -void __init mv78xx0_pcie_init(int init_port0, int init_port1) -{ - vga_base = MV78XX0_PCIE_MEM_PHYS_BASE; - - if (init_port0) { - add_pcie_port(0, 0, PCIE00_VIRT_BASE); - if (!orion_pcie_x4_mode((void __iomem *)PCIE00_VIRT_BASE)) { - add_pcie_port(0, 1, PCIE01_VIRT_BASE); - add_pcie_port(0, 2, PCIE02_VIRT_BASE); - add_pcie_port(0, 3, PCIE03_VIRT_BASE); - } - } - - if (init_port1) { - add_pcie_port(1, 0, PCIE10_VIRT_BASE); - if (!orion_pcie_x4_mode((void __iomem *)PCIE10_VIRT_BASE)) { - add_pcie_port(1, 1, PCIE11_VIRT_BASE); - add_pcie_port(1, 2, PCIE12_VIRT_BASE); - add_pcie_port(1, 3, PCIE13_VIRT_BASE); - } - } - - pci_common_init(&mv78xx0_pci); -} diff --git a/ANDROID_3.4.5/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c b/ANDROID_3.4.5/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c deleted file mode 100644 index 9a882706..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * arch/arm/mach-mv78x00/rd78x00-masa-setup.c - * - * Marvell RD-78x00-mASA Development Board Setup - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/ata_platform.h> -#include <linux/mv643xx_eth.h> -#include <linux/ethtool.h> -#include <mach/mv78xx0.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include "common.h" - -static struct mv643xx_eth_platform_data rd78x00_masa_ge00_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(8), -}; - -static struct mv643xx_eth_platform_data rd78x00_masa_ge01_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(9), -}; - -static struct mv643xx_eth_platform_data rd78x00_masa_ge10_data = { -}; - -static struct mv643xx_eth_platform_data rd78x00_masa_ge11_data = { -}; - -static struct mv_sata_platform_data rd78x00_masa_sata_data = { - .n_ports = 2, -}; - -static void __init rd78x00_masa_init(void) -{ - /* - * Basic MV78x00 setup. Needs to be called early. - */ - mv78xx0_init(); - - /* - * Partition on-chip peripherals between the two CPU cores. - */ - if (mv78xx0_core_index() == 0) { - mv78xx0_ehci0_init(); - mv78xx0_ehci1_init(); - mv78xx0_ge00_init(&rd78x00_masa_ge00_data); - mv78xx0_ge10_init(&rd78x00_masa_ge10_data); - mv78xx0_sata_init(&rd78x00_masa_sata_data); - mv78xx0_uart0_init(); - mv78xx0_uart2_init(); - } else { - mv78xx0_ehci2_init(); - mv78xx0_ge01_init(&rd78x00_masa_ge01_data); - mv78xx0_ge11_init(&rd78x00_masa_ge11_data); - mv78xx0_uart1_init(); - mv78xx0_uart3_init(); - } -} - -static int __init rd78x00_pci_init(void) -{ - /* - * Assign all PCIe devices to CPU core #0. - */ - if (machine_is_rd78x00_masa() && mv78xx0_core_index() == 0) - mv78xx0_pcie_init(1, 1); - - return 0; -} -subsys_initcall(rd78x00_pci_init); - -MACHINE_START(RD78X00_MASA, "Marvell RD-78x00-MASA Development Board") - /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */ - .atag_offset = 0x100, - .init_machine = rd78x00_masa_init, - .map_io = mv78xx0_map_io, - .init_early = mv78xx0_init_early, - .init_irq = mv78xx0_init_irq, - .timer = &mv78xx0_timer, - .restart = mv78xx0_restart, -MACHINE_END |