Moved, renamed, and deleted files

The original directory structure was scattered and unorganized.
Changes are basically to make it look like kernel structure.

7 files changed, 1906 insertions, 0 deletions

diff --git a/drivers/video/wmt/hw/wmt-cec-reg.h b/drivers/video/wmt/hw/wmt-cec-reg.h
new file mode 100755
index 00000000..17e7275c
--- /dev/null
+++ b/drivers/video/wmt/hw/wmt-cec-reg.h
@@ -0,0 +1,220 @@
+/*++
+ * linux/drivers/video/wmt/hw/wmt-cec-reg.h
+ * WonderMedia video post processor (VPP) driver
+ *
+ * Copyright c 2013  WonderMedia  Technologies, Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * WonderMedia Technologies, Inc.
+ * 4F, 533, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C
+--*/
+
+#ifndef WMT_CEC_REG_H
+#define WMT_CEC_REG_H
+
+#define WMT_FTBLK_CEC
+
+#define CEC_BASE_ADDR			(LVDS_BASE_ADDR + 0x100)
+#define CEC_BASE2_ADDR			(LVDS_BASE_ADDR + 0x200)
+struct cec_base_regs {
+	union {
+		unsigned int val;
+		struct {
+			unsigned int wr_start:1;
+		} b;
+	} enable; /* 0x0 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int wr_num:8;
+		} b;
+	} encode_number; /* 0x04 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int wr_data_ack:1;
+			unsigned int wr_data_eom:1;
+			unsigned int _02_03:2;
+			unsigned int wr_data:8;
+		} b;
+	} encode_data[16]; /* 0x08 header,0x0c - 0x44 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int finish_reset:1;
+		} b;
+	} decode_reset; /* 0x48 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int rd_start:1;
+			unsigned int rd_all_ack:1;
+			unsigned int rd_finish:1;
+		} b;
+	} decode_start; /* 0x4c */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int rd_data_ack:1;
+			unsigned int rd_data_eom:1;
+			unsigned int _02_03:2;
+			unsigned int rd_data:8;
+		} b;
+	} decode_data[16]; /* 0x50 header, 0x54 - 0x8c */
+
+	unsigned int wr_start_set0; /* 0x90 */
+	unsigned int wr_start_set1; /* 0x94 */
+	unsigned int wr_logic0_set0; /* 0x98 */
+	unsigned int wr_logic0_set1; /* 0x9c */
+	unsigned int wr_logic1_set0; /* 0xa0 */
+	unsigned int wr_logic1_set1; /* 0xa4 */
+	unsigned int rd_start_l_set0; /* 0xa8 */
+	unsigned int rd_start_r_set0; /* 0xac */
+	unsigned int rd_start_l_set1; /* 0xb0 */
+	unsigned int rd_start_r_set1; /* 0xb4 */
+	unsigned int rd_logic0_l_set0; /* 0xb8 */
+	unsigned int rd_logic0_r_set0; /* 0xbc */
+	unsigned int rd_logic0_l_set1; /* 0xc0 */
+	unsigned int rd_logic0_r_set1; /* 0xc4 */
+	unsigned int rd_logic1_l_set0; /* 0xc8 */
+	unsigned int rd_logic1_r_set0; /* 0xcc */
+	unsigned int rd_logic1_l_set1; /* 0xd0 */
+	unsigned int rd_logic1_r_set1; /* 0xd4 */
+	unsigned int physical_addr; /* 0xd8 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int addr1:4;
+			unsigned int addr2:4;
+			unsigned int addr3:4;
+			unsigned int addr4:4;
+			unsigned int addr5:4;
+			unsigned int _20_23:4;
+			unsigned int valid1:1;
+			unsigned int valid2:1;
+			unsigned int valid3:1;
+			unsigned int valid4:1;
+			unsigned int valid5:1;
+		} b;
+	} logical_addr; /* 0xdc */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int retry:4;
+		} b;
+	} wr_retry; /* 0xe0 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int free_3x:4;
+			unsigned int _04_07:4;
+			unsigned int free_5x:4;
+			unsigned int _12_15:4;
+			unsigned int free_7x:4;
+		} b;
+	} free_3x; /* 0xe4 */
+
+	unsigned int wr_set0_error; /* 0xe8 */
+	unsigned int wr_set1_error; /* 0xec */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int next_decode:1; /*read enable*/
+		} b;
+	} reject; /* 0xf0 */
+
+	unsigned int rd_l_set0_error; /* 0xf4 */
+	unsigned int rd_r_set1_error; /* 0xf8 */
+	unsigned int rd_l_error; /* 0xfc */
+
+	unsigned int rx_trig_range; /* 0x100 */
+	unsigned int rx_sample_l_range; /* 0x104 */
+	unsigned int rx_sample_r_range; /* 0x108 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int disable:1;
+		} b;
+	} comp; /* 0x10c */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int err:1;
+			unsigned int no_ack:1;
+		} b;
+	} handle_disable; /* 0x110 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int r1_encode_ok:1; /* write finish */
+			unsigned int r1_decode_ok:1; /* read finish */
+			unsigned int r1_error:1; /* read error */
+			unsigned int r1_arb_fail:1; /* wr arb fail */
+			unsigned int r1_no_ack:1; /* wr no ack */
+		} b;
+	} status; /* 0x114 */
+
+	unsigned int int_enable; /* 0x118 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int disable:1;
+		} b;
+	} decode_full; /* 0x11c */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int start:1;
+			unsigned int logic0:1;
+			unsigned int logic1:1;
+		} b;
+	} status4_disable; /* 0x120 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int enable:1; /*1:rd self wr & all dest data */
+		} b;
+	} rd_encode; /* 0x124 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int disable:1; /* 1 : disable arb check */
+		} b;
+	} arb_check; /* 0x128 */
+};
+
+#define REG_CEC_BEGIN	(CEC_BASE_ADDR + 0x0)
+#define REG_CEC_END	(CEC_BASE2_ADDR + 0x28)
+#ifndef CEC_C
+extern struct cec_base_regs *cec_regs;
+#endif
+#endif /* WMT_CEC_REG_H */
+
diff --git a/drivers/video/wmt/hw/wmt-govrh-reg.h b/drivers/video/wmt/hw/wmt-govrh-reg.h
new file mode 100755
index 00000000..ecdeb4f2
--- /dev/null
+++ b/drivers/video/wmt/hw/wmt-govrh-reg.h
@@ -0,0 +1,366 @@
+/*++
+ * linux/drivers/video/wmt/hw/wmt-govrh-reg.h
+ * WonderMedia video post processor (VPP) driver
+ *
+ * Copyright c 2014  WonderMedia  Technologies, Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * WonderMedia Technologies, Inc.
+ * 4F, 533, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C
+--*/
+
+#ifndef WMT_GOVRH_REG_H
+#define WMT_GOVRH_REG_H
+
+/* feature */
+#define WMT_FTBLK_GOVRH
+#ifndef CONFIG_UBOOT
+#define WMT_FTBLK_GOVRH_CURSOR
+#endif
+#define WMT_FTBLK_GOVRH2
+
+#define GOVRH_FRAMEBUF_ALIGN	128
+
+struct govrh_regs {
+	/* base1 */
+	unsigned int cur_addr; /* 0x00 */
+	unsigned int cur_width;
+	unsigned int cur_fb_width;
+	unsigned int cur_vcrop;
+	unsigned int cur_hcrop; /* 0x10 */
+	union {
+		unsigned int val;
+		struct {
+			unsigned int start:11;
+			unsigned int reserved:5;
+			unsigned int end:11;
+		} b;
+	} cur_hcoord; /* 0x14 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int start:11;
+			unsigned int reserved:5;
+			unsigned int end:11;
+		} b;
+	} cur_vcoord; /* 0x18 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int enable:1;
+			unsigned int reserved:7;
+			unsigned int out_field:1;	/* 0:frame,1-field */
+		} b;
+	} cur_status; /* 0x1C */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int colkey:24;
+			unsigned int enable:1;
+			unsigned int invert:1;
+			unsigned int reserved:2;
+			unsigned int alpha:1;
+		} b;
+	} cur_color_key; /* 0x20 */
+
+	unsigned int reserved[3];
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int rgb:1;
+			unsigned int yuv422:1;
+		} b;
+	} dvo_pix; /* 0x30 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int delay:14;
+			unsigned int inv:1;
+		} b;
+	} dvo_dly_sel; /* 0x34 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int cur_enable:1;
+			unsigned int mem_enable:1;
+			unsigned int reserved:7;
+			unsigned int err_sts:1;
+			unsigned int reserved2:6;
+			unsigned int cur_sts:1;
+			unsigned int mem_sts:1;
+		} b;
+	} interrupt; /* 0x38 */
+
+	unsigned int dvo_blank_data;
+	unsigned int dirpath; /* 0x40 */
+	union {
+		unsigned int val;
+		struct {
+			unsigned int v:8;
+			unsigned int u:8;
+			unsigned int y:8;
+		} b;
+	} saturation; /* 0x44 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int enable:1;
+			unsigned int format:1; /* 0:YCbCr, 1:RGB */
+		} b;
+	} saturation_enable; /* 0x48 */
+
+	unsigned int reserved2[13];
+	union {
+		unsigned int val;
+		struct {
+			unsigned int enable:1;
+			unsigned int reserved:7;
+			unsigned int h264:1;
+		} b;
+	} mif; /* 0x80 */
+
+	unsigned int colfmt; /* 0x84, 0:422,1:420 */
+	unsigned int srcfmt; /* 0x88, 0:frame,1:field */
+	unsigned int dstfmt; /* 0x8C, 0:frame,1:field */
+	unsigned int ysa;	/* 0x90 */
+	unsigned int csa;
+	unsigned int pixwid;
+	unsigned int bufwid;
+	unsigned int vcrop;	/* 0xA0 */
+	unsigned int hcrop;
+	unsigned int fhi;
+	unsigned int colfmt2;	/* 0xAC, 1-444,other refer 0x84 */
+	unsigned int ysa2;	/* 0xB0 */
+	unsigned int csa2;
+	union {
+		unsigned int val;
+		struct {
+			unsigned int req_num:8;	/* Y & RGB */
+			unsigned int req_num_c:8;	/* C */
+			unsigned int frame_enable:1;
+		} b;
+	} mif_frame_mode; /* 0xB8 */
+
+	unsigned int reserved3[10];
+	union {
+		unsigned int val;
+		struct {
+			unsigned int update:1;
+			unsigned int reserved:7;
+			unsigned int level:1;	/* 0:level 1, 1:level2 */
+		} b;
+	} sts; /* 0xE4 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int fixed:1;	/* 0-top, 1-bottom */
+			unsigned int enable:1;
+		} b;
+	} swfld; /* 0xE8 */
+
+	unsigned int reserved4[5];
+	/* base2 */
+	union {
+		unsigned int val;
+		struct {
+			unsigned int enable:1;
+			unsigned int reserved:7;
+			unsigned int mode:1; /* 0-frame,1-field */
+		} b;
+	} tg_enable; /* 0x100 */
+
+	unsigned int read_cyc;
+	unsigned int h_allpxl;
+	unsigned int v_allln;
+	unsigned int actln_bg; /* 0x110 */
+	unsigned int actln_end;
+	unsigned int actpx_bg;
+	unsigned int actpx_end;
+	unsigned int vbie_line; /* 0x120 */
+	unsigned int pvbi_line;
+	unsigned int hdmi_vbisw;
+	unsigned int hdmi_hsynw;
+	union {
+		unsigned int val;
+		struct {
+			unsigned int offset:12;
+			unsigned int reserved:4;
+			unsigned int field_invert:1;
+		} b;
+	} vsync_offset; /* 0x130 */
+
+	unsigned int field_status; /* 0x134, 1-BOTTOM,0-TOP */
+	unsigned int reserved5[1]; /* 0x138 */
+	union {
+		unsigned int val;
+		struct {
+			unsigned int mode:3; /* 011-frame packing progressive
+				format,111-frame packing interlace format */
+			unsigned int inv_filed_polar:1;
+			unsigned int blank_value:16;
+			unsigned int reserved:11;
+			unsigned int addr_sel:1; /* in frame packing
+							interlace mode */
+		} b;
+	} hdmi_3d; /* 0x13C */
+
+	unsigned int reserved5_2[2];
+	union {
+		unsigned int val;
+		struct {
+			unsigned int outwidth:1; /* 0-24bit,1-12bit */
+			unsigned int hsync_polar:1; /* 0-act high,1-act low */
+			unsigned int enable:1;
+			unsigned int vsync_polar:1; /* 0-act high,1-act low */
+			unsigned int reserved:4;
+			unsigned int rgb_swap:2; /* 0-RGB[7:0],1-RGB[0:7],
+							2-BGR[7:0],3-BGR[0:7] */
+			unsigned int reserved2:6;
+			unsigned int blk_dis:1;	/* 0-Blank Data,
+						1-Embeded sync CCIR656 */
+		} b;
+	} dvo_set; /* 0x148 */
+
+	unsigned int reserved6;
+	union {
+		unsigned int val;
+		struct {
+			unsigned int enable:1;
+			unsigned int reserved1:7;
+			unsigned int mode:1;
+			unsigned int reserved2:7;
+			unsigned int inversion:1;
+		} b;
+	} cb_enable; /* 0x150 */
+
+	unsigned int reserved7;
+	unsigned int h_allpxl2;
+	unsigned int v_allln2;
+	unsigned int actln_bg2;	/* 0x160 */
+	unsigned int actln_end2;
+	unsigned int actpx_bg2;
+	unsigned int actpx_end2;
+	unsigned int vbie_line2; /* 0x170 */
+	unsigned int pvbi_line2;
+	unsigned int hdmi_vbisw2;
+	unsigned int hdmi_hsynw2;
+	union {
+		unsigned int val;
+		struct {
+			unsigned int outwidth:1; /* 0-24bit,1-12bit */
+			unsigned int hsync_polar:1; /* 0-act high,1-act low */
+			unsigned int enable:1;
+			unsigned int vsync_polar:1; /* 0-act high,1-act low */
+		} b;
+	} lvds_ctrl; /* 0x180 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int pix:2; /* 0-YUV444,1-RGB,2-YUV422,3-RGB */
+		} b;
+	} lvds_ctrl2; /* 0x184 */
+
+	unsigned int reserved_dac[12];
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int praf:8;
+			unsigned int pbaf:8;
+			unsigned int yaf:8;
+		} b;
+	} contrast; /* 0x1B8 */
+
+	unsigned int brightness;
+	unsigned int dmacsc_coef0; /* 0x1C0 */
+	unsigned int dmacsc_coef1;
+	unsigned int dmacsc_coef2;
+	unsigned int dmacsc_coef3;
+	unsigned int dmacsc_coef4; /* 0x1D0 */
+	unsigned int reserved8;
+	unsigned int dmacsc_coef5;
+	unsigned int dmacsc_coef6;
+	union {
+		unsigned int val;
+		struct {
+			unsigned int mode:1;	/* 1: YUV2RGB, 0: RGB2YUV */
+			unsigned int clamp:1;	/* 0:Y,1:Y-16 */
+		} b;
+	} csc_mode; /* 0x1E0 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int dvo:1;
+			unsigned int vga:1;
+			unsigned int reserved1:1;
+			unsigned int dac_clkinv:1;
+			unsigned int blank_zero:1;
+			unsigned int disp:1;
+			unsigned int lvds:1;
+			unsigned int hdmi:1;
+			unsigned int rgb_mode:2; /*0-YUV,1-RGB24,2-1555,3-565*/
+		} b;
+	} yuv2rgb; /* 0x1E4 */
+
+	unsigned int h264_input_en;	/* 0x1E8 */
+	unsigned int reserved9;
+	unsigned int lvds_clkinv;	/* 0x1F0 */
+	unsigned int hscale_up;		/* 0x1F4 */
+	union {
+		unsigned int val;
+		struct {
+			unsigned int mode:3; /* 0:888,1:555,2:666,3:565,4:ori */
+			unsigned int reserved:5;
+			unsigned int ldi:1; /* 0:shift right,1:shift left */
+		} b;
+	} igs_mode; /* 0x1F8 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int mode:3; /* 0:888,1:555,2:666,3:565,4:ori */
+			unsigned int reserved:5;
+			unsigned int ldi:1; /* 0:shift right,1:shift left */
+		} b;
+	} igs_mode2; /* 0x1FC */
+};
+
+/* GOVRH */
+#define REG_GOVRH_BASE1_BEGIN		(GOVRH_BASE1_ADDR+0x00)
+#define REG_GOVRH_YSA			(GOVRH_BASE1_ADDR+0x90)
+#define REG_GOVRH_CSA			(GOVRH_BASE1_ADDR+0x94)
+#define REG_GOVRH_BASE1_END		(GOVRH_BASE1_ADDR+0xe8)
+#define REG_GOVRH_BASE2_BEGIN		(GOVRH_BASE2_ADDR+0x00)
+#define REG_GOVRH_BASE2_END		(GOVRH_BASE2_ADDR+0xFC)
+
+/* GOVRH2 */
+#define REG_GOVRH2_BASE1_BEGIN		(GOVRH2_BASE1_ADDR+0x00)
+#define REG_GOVRH2_YSA			(GOVRH2_BASE1_ADDR+0x90)
+#define REG_GOVRH2_CSA			(GOVRH2_BASE1_ADDR+0x94)
+#define REG_GOVRH2_BASE1_END		(GOVRH2_BASE1_ADDR+0xe8)
+#define REG_GOVRH2_BASE2_BEGIN		(GOVRH2_BASE2_ADDR+0x00)
+#define REG_GOVRH2_BASE2_END		(GOVRH2_BASE2_ADDR+0xFC)
+
+#endif /* WMT_GOVRH_REG_H */
diff --git a/drivers/video/wmt/hw/wmt-hdmi-reg.h b/drivers/video/wmt/hw/wmt-hdmi-reg.h
new file mode 100755
index 00000000..c0650555
--- /dev/null
+++ b/drivers/video/wmt/hw/wmt-hdmi-reg.h
@@ -0,0 +1,379 @@
+/*++
+ * linux/drivers/video/wmt/hw/wmt-hdmi-reg.h
+ * WonderMedia video post processor (VPP) driver
+ *
+ * Copyright c 2014  WonderMedia  Technologies, Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * WonderMedia Technologies, Inc.
+ * 4F, 533, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C
+--*/
+
+#ifndef WMT_HDMI_REG_H
+#define WMT_HDMI_REG_H
+
+#define WMT_FTBLK_HDMI
+
+#define HDMI_BASE_ADDR	(HDMI_TRANSMITTE_BASE_ADDR + 0xC000)
+
+struct hdmi_base1_regs {
+	unsigned int _100_11c[8];
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int eeprom_reset:1;
+			unsigned int encode_enable:1;
+			unsigned int hden:1;
+			unsigned int eess_enable:1;
+			unsigned int verify_pj_enable:1;
+			unsigned int i2c_enable:1;
+			unsigned int auth_test_key:1;
+			unsigned int _7:1;
+			unsigned int cipher_1_1:1;
+			unsigned int _9_11:3;
+			unsigned int preamble:4;
+			unsigned int _16_19:4;
+			unsigned int encode_window:3;
+		} b;
+	} ctrl; /* 0x120 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int _0_6:7;
+			unsigned int force_exit_fsm:1;
+			unsigned int key_read_word:7;
+			unsigned int i2c_sw_reset:1;
+			unsigned int i2c_clk_divider:16;
+		} b;
+	} i2c_ctrl; /* 0x124 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int wr_data:8;
+			unsigned int rd_data:8;
+			unsigned int sw_start_req:1;
+			unsigned int sw_stop_req:1;
+			unsigned int wr_data_avail:1;
+			unsigned int i2c_status:1; /* 0-not using,1-in using */
+			unsigned int cp_key_req:1;
+			unsigned int cp_key_read:1;
+			unsigned int cp_key_last:1;
+			unsigned int _23:1;
+			unsigned int cp_src_sel:1;
+			unsigned int sw_read:1;
+			unsigned int sw_i2c_req:1;
+			unsigned int ksv_list_avail:1;
+			unsigned int ksv_verify_done:1;
+		} b;
+	} i2c_ctrl2; /* 0x128 */
+
+	unsigned int _12c_27c[85];
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int reset:1;
+			unsigned int enable:1;
+			unsigned int _2_5:4;
+			unsigned int dvi_mode_enable:1;
+			unsigned int output_format:2; /* 0-RGB,
+							1-YUV444,2-YUV422 */
+			unsigned int convert_yuv422:1;
+			unsigned int hsync_low_active:1; /* 0-active hi,1-lo */
+			unsigned int dbg_bus_select:1; /* 0-before,1-after */
+			unsigned int _12:1;
+			unsigned int vsync_low_active:1; /* 0-active hi,1-lo */
+			unsigned int _14_15:2;
+			unsigned int cp_delay:7;
+			unsigned int _23:1;
+			unsigned int vsync_enable:3; /* write only */
+			unsigned int state_machine_status:5;
+		} b;
+	} general_ctrl; /* 0x280 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int select:1; /* 0-fifo1,1-fifo2 */
+			unsigned int fifo1_rdy:1; /* Info frame FIFO 1 ready */
+			unsigned int fifo2_rdy:1; /* Info frame FIFO 2 ready */
+			unsigned int _3:1;
+			unsigned int fifo1_addr:4; /* FIFO 1 start address */
+			unsigned int fifo1_len:5; /* FIFO 1 length */
+			unsigned int _13_15:3;
+			unsigned int fifo2_addr:4; /* FIFO 2 start address */
+			unsigned int fifo2_len:5; /* FIFO 2 length */
+			unsigned int _25_27:3;
+			unsigned int horiz_blank_max_pck:3; /* Max packets
+						that insert during HSYNC */
+		} b;
+	} infoframe_ctrl; /* 0x284 */
+	unsigned int _288_290[3];
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int pck_insert_reset:1;
+			unsigned int pck_insert_enable:1;
+			unsigned int avmute_set_enable:1;
+			unsigned int avmute_clr_enable:1;
+			unsigned int insert_delay:12;
+			unsigned int _16_29:14;
+			unsigned int pixel_repetition:2; /* 0-none,1-2x,2-4x */
+		} b;
+	} aud_insert_ctrl; /* 0x294 */
+
+	unsigned int _298;
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int _0_7:8;
+			unsigned int acr_ratio:20;
+			unsigned int acr_enable:1;
+			unsigned int mute:1;
+		} b;
+	} aud_ratio; /* 0x29c */
+
+	unsigned int aud_enable; /* 0x2a0 */
+	unsigned int _2a4_2a8[2];
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int sub_packet:4;
+			unsigned int spflat:4;
+			unsigned int _2ch_eco:1;
+			unsigned int _9:1;
+			unsigned int layout:1; /* 0-2 channel,1-8 channel */
+			unsigned int pwr_saving:1; /* 0-normal,1-power saving */
+		} b;
+	} aud_mode; /* 0x2ac */
+
+	unsigned int _2b0_38c[56];
+	unsigned int aud_chan_status0; /* 0x390 */
+	unsigned int aud_chan_status1; /* 0x394 */
+	unsigned int aud_chan_status2; /* 0x398 */
+	unsigned int aud_chan_status3; /* 0x39c */
+	unsigned int aud_chan_status4; /* 0x3a0 */
+	unsigned int aud_chan_status5; /* 0x3a4 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int n_20bits:20;
+			unsigned int cts_low_12bits:12;
+		} b;
+	} aud_sample_rate1; /* 0x3a8 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int cts_hi_8bits:8;
+			unsigned int _8_27:20;
+			unsigned int aipclk_rate:2; /* 0-N/2,1-N,2-N/4,3-N*2 */
+			unsigned int cts_select:1; /* 0-auto,1-fixed from reg */
+		} b;
+	} aud_sample_rate2; /* 0x3ac */
+
+	unsigned int _3b0_3bc[4];
+	unsigned int wr_fifo_addr[9]; /* 0x3c0 - 0x3e0 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int wr_strobe:1;
+			unsigned int rd_strobe:1;
+			unsigned int _2_7:6;
+			unsigned int addr:8;
+		} b;
+	} fifo_ctrl; /* 0x3e4 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int ch0_data:10;
+			unsigned int ch0_enable:1;
+			unsigned int _11_15:5;
+			unsigned int ch1_data:10;
+			unsigned int ch1_enable:1;
+		} b;
+	} channel_test; /* 0x3e8 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int ch2_data:10;
+			unsigned int ch2_enable:1;
+			unsigned int _11_15:5;
+			unsigned int in_enable:1;
+			unsigned int out_enable:1;
+			unsigned int _18_23:6;
+			unsigned int in_sts:1;
+			unsigned int out_sts:1;
+			unsigned int _26_30:5;
+			unsigned int sts:1; /* 0-plug out,1-plug in */
+		} b;
+	} hotplug_detect; /* 0x3ec */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int sample:8;
+			unsigned int _8_15:8;
+			unsigned int detect:9;
+		} b;
+	} hotplug_debounce; /* 0x3f0 */
+
+	unsigned int _3f4;
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int test_enable:1;
+			unsigned int test_format:1;
+			unsigned int _2_9:8;
+			unsigned int infoframe_sram_enable:1;
+			unsigned int _11_15:5;
+			unsigned int clock_select:1; /* 0-clk 1x, 1-clk 2x */
+		} b;
+	} tmds_ctrl; /* 0x3f8 */
+
+	unsigned int _3fc;
+	unsigned int rd_fifo_addr[9]; /* 0x400 - 0x420 */
+};
+
+struct hdmi_base2_regs {
+	union {
+		unsigned int val;
+		struct {
+			unsigned int inv_clk:1;
+			unsigned int _1_3:3;
+			unsigned int dual_channel:1;
+			unsigned int _5_7:3;
+			unsigned int test:4;
+			unsigned int _12_18:7;
+			unsigned int internal_ldo:1;
+		} b;
+	} status; /* 0x00 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int drv_pdmode:1;
+			unsigned int _1:1;
+			unsigned int vbg_sel:2;
+			unsigned int _4_7:4;
+			unsigned int pd:1;
+			unsigned int tre_en:2;
+			unsigned int _11:1;
+			unsigned int pllck_dly:3;
+			unsigned int _15:1;
+			unsigned int pll_cpset:2;
+			unsigned int pll_r_f:1;
+		} b;
+	} test; /* 0x04 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int update:1;
+			unsigned int _1_7:7;
+			unsigned int level:1;
+		} b;
+	} level; /* 0x08 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int bpp_type:3; /* 0-888,1-555,2-666,3-565 */
+			unsigned int _3_7:5;
+			unsigned int ldi_shift_left:1; /* 0-right,1-left */
+		} b;
+	} igs; /* 0x0c */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int out_data_12:1; /* 0-24bit,1-12bit */
+			unsigned int hsync_polar_lo:1; /* 0-act hi,1-act low */
+			unsigned int dvo_enable:1;
+			unsigned int vsync_polar_lo:1; /* 0-act hi,1-act low */
+		} b;
+	} set; /* 0x10 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int colfmt_rgb:1;/* 0-RGB or YUV444,1-YUV422 */
+			unsigned int colfmt_yuv422:1;
+		} b;
+	} set2; /* 0x14 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int pll_ready:1;
+			unsigned int _1_7:7;
+			unsigned int rsen:1;
+		} b;
+	} detect; /* 0x18 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int pll_tsync:1;
+			unsigned int tp2s_type:1;
+			unsigned int div_sel:2;
+			unsigned int pd_v2i:1;
+			unsigned int vco_sx:1;
+			unsigned int vco_mode:1;
+			unsigned int _7:1;
+			unsigned int vsref_sel:2;
+			unsigned int mode:1;
+			unsigned int pd_l2ha:1;
+			unsigned int pd_l2hb:1;
+			unsigned int l2ha_hsen:1;
+			unsigned int resa_en:1;
+			unsigned int resa_s:1;
+			unsigned int pll_lpfs:2;
+		} b;
+	} test2; /* 0x1c */
+
+	unsigned int test3; /* 0x20 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int _0_15:16;
+			unsigned int reset_pll:1;
+		} b;
+	} dftset2; /* 0x24 */
+};
+
+#define REG_HDMI_BEGIN	(HDMI_BASE_ADDR + 0x100)
+#define REG_HDMI_END	(HDMI_BASE_ADDR + 0x420)
+#define REG_HDMI2_BEGIN	(HDMI_BASE2_ADDR + 0x00)
+#define REG_HDMI2_END	(HDMI_BASE2_ADDR + 0x28)
+
+#ifndef HDMI_C
+extern HW_REG struct hdmi_base1_regs *hdmi_regs1;
+extern HW_REG struct hdmi_base2_regs *hdmi_regs2;
+#endif
+#endif /* WMT_HDMI_REG_H */
+
diff --git a/drivers/video/wmt/hw/wmt-lvds-reg.h b/drivers/video/wmt/hw/wmt-lvds-reg.h
new file mode 100755
index 00000000..0a6e616c
--- /dev/null
+++ b/drivers/video/wmt/hw/wmt-lvds-reg.h
@@ -0,0 +1,129 @@
+/*++
+ * linux/drivers/video/wmt/hw/wmt-lvds-reg.h
+ * WonderMedia video post processor (VPP) driver
+ *
+ * Copyright c 2014  WonderMedia  Technologies, Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * WonderMedia Technologies, Inc.
+ * 4F, 533, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C
+--*/
+
+#ifndef WMT_LVDS_REG_H
+#define WMT_LVDS_REG_H
+
+#define WMT_FTBLK_LVDS
+
+struct lvds_base_regs {
+	union {
+		unsigned int val;
+		struct {
+			unsigned int inv_clk:1;
+			unsigned int _01_03:3;
+			unsigned int dual_channel:1;
+			unsigned int _05_07:3;
+			unsigned int test:4;
+		} b;
+	} status; /* 0x00 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int drv_pdmode:1;
+			unsigned int _01:1;
+			unsigned int vbg_sel:2;
+			unsigned int _04_07:4;
+			unsigned int pd:1;
+			unsigned int tre_en:2;
+			unsigned int _11:1;
+			unsigned int pllck_dly:3;
+			unsigned int _15:1;
+			unsigned int pll_cpset:2;
+			unsigned int pll_r_f:1;
+		} b;
+	} test; /* 0x04 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int update:1;
+			unsigned int _01_07:7;
+			unsigned int level:1;
+		} b;
+	} level; /* 0x08 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int bpp_type:3; /* 0-888,1-555,2-666,3-565 */
+			unsigned int _03_07:5;
+			unsigned int ldi_shift_left:1; /* 0-shift right,1-left*/
+		} b;
+	} igs; /* 0x0c */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int out_data_12:1; /* 0-24bit,1-12bit */
+			unsigned int hsync_polar_lo:1; /* 0-active hi,1-low */
+			unsigned int dvo_enable:1;
+			unsigned int vsync_polar_lo:1; /* 0-active hi,1-low */
+		} b;
+	} set; /* 0x10 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int colfmt:2; /* 0-YUV444,1/3-RGB,2-YUV422 */
+		} b;
+	} set2; /* 0x14 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int pll_ready:1;
+			unsigned int _01_07:7;
+			unsigned int rsen:1;
+		} b;
+	} detect; /* 0x18 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int pll_tsync:1;
+			unsigned int tp2s_type:1;
+			unsigned int div_sel:2;
+			unsigned int pd_v2i:1;
+			unsigned int vco_sx:1;
+			unsigned int vco_mode:1;
+			unsigned int _07:1;
+			unsigned int vsref_sel:2;
+			unsigned int mode:1;
+			unsigned int pd_l2ha:1;
+			unsigned int pd_l2hb:1;
+			unsigned int l2ha_hsen:1;
+			unsigned int resa_en:1;
+			unsigned int resa_s:1;
+			unsigned int pll_lpfs:2;
+		} b;
+	} test2; /* 0x1c */
+};
+
+#define REG_LVDS_BEGIN	(LVDS_BASE_ADDR + 0x00)
+#define REG_LVDS_END	(LVDS_BASE_ADDR + 0x1C)
+#ifndef LVDS_C
+extern struct lvds_base_regs *lvds_regs;
+#endif
+#endif /* WMT_LVDS_REG_H */
diff --git a/drivers/video/wmt/hw/wmt-scl-reg.h b/drivers/video/wmt/hw/wmt-scl-reg.h
new file mode 100755
index 00000000..773fad96
--- /dev/null
+++ b/drivers/video/wmt/hw/wmt-scl-reg.h
@@ -0,0 +1,543 @@
+/*++
+ * linux/drivers/video/wmt/hw/wmt-scl-reg.h
+ * WonderMedia video post processor (VPP) driver
+ *
+ * Copyright c 2014  WonderMedia  Technologies, Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * WonderMedia Technologies, Inc.
+ * 4F, 533, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C
+--*/
+
+#ifndef WMT_SCL_REG_H
+#define WMT_SCL_REG_H
+
+/* feature */
+#define WMT_FTBLK_SCL
+
+/* constant */
+#define WMT_SCL_RCYC_MIN	0	/* 1T */
+#define WMT_SCL_H_DIV_MAX	8192
+#define WMT_SCL_V_DIV_MAX	8192
+#define WMT_SCL_FB_WIDTH_MAX	8192
+
+#define WMT_SCL_SCALE_DST_H_MAX	1920	/* bypass no limit */
+
+struct scl_base1_regs {
+	union {
+		unsigned int val;
+		struct {
+			unsigned int alu_enable:1;
+		} b;
+	} en; /* 0x0 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int reg_update:1;
+		} b;
+	} upd; /* 0x04 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int reg_level:1;
+		} b;
+	} sel; /* 0x08 */
+
+	unsigned int _0c_38[12];
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int hxwidth:13;
+		} b;
+	} hxwidth; /* 0x3c */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int mif_en:1;
+			unsigned int _01_03:3;
+			unsigned int rgb_mode:2; /* 0-YUV,1-RGB565,3-RGB32 */
+			unsigned int _06_07:2;
+			unsigned int _420c_fmt:1; /* 0-frame,1-field */
+			unsigned int vfmt:3; /* 0-YUV422,1-YUV420,
+							2-YUV444,4-RGB32 */
+			unsigned int h264_fmt:1; /* 0-MPEG,1-H264 */
+			unsigned int _13_15:3;
+			unsigned int iofmt:1; /* 0-frame,1-field */
+			unsigned int _17_23:7;
+			unsigned int color_en:1; /* 0-disable,1-enable */
+			unsigned int color_wide:1; /* 0-Normal,1-Wider */
+			unsigned int color_inv:1; /* 0-Normal,1-Opposite color*/
+		} b;
+	} r2_ctl; /* 0x40 */
+
+	unsigned int r2_ysa; /* 0x44 */
+	unsigned int r2_csa; /* 0x48 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int fbw:13; /* frame buffer width pixel */
+			unsigned int _13_15:3;
+			unsigned int lnsize:13; /* line width pixel */
+		} b;
+	} r2_h_size; /* 0x4c */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int hcrop:13;
+			unsigned int _13_15:3;
+			unsigned int vcrop:13;
+		} b;
+	} r2_crop; /* 0x50 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int src:2; /* 0-RMIF1,1-RMIF2,2-Fixed ALPHA */
+			unsigned int _02_07:6;
+			unsigned int dst:2; /* 0-RMIF1,1-RMIF2,2-Fixed ALPHA */
+			unsigned int _09_15:6;
+			unsigned int swap:1; /* 0-(alpha,1-a),1:(1-a,alpha) */
+		} b;
+	} alpha_md; /* 0x54 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int src_fixed:8;
+			unsigned int dst_fixed:8;
+		} b;
+	} alpha_fxd; /* 0x58 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int enable:1;
+			unsigned int _01_07:7;
+			unsigned int from:1; /* 0-RMIF1,1-RMIF2 */
+			unsigned int _09_15:7;
+			unsigned int comp:2; /* 0-888,1-777,2-666,3-555 */
+			unsigned int _17_23:7;
+			unsigned int mode:3; /* (Non-Hit,Hit):0/1-(alpha,alpha),
+				2-(alpha,pix1),3-(pix1,alpha),4-(alpha,pix2),
+				5-(pix2,alpha),6-(pix1,pix2),7-(pix2,pix1) */
+		} b;
+	} alpha_colorkey; /* 0x5c */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int r:8;
+			unsigned int g:8;
+			unsigned int b:8;
+		} b;
+	} alpha_colorkey_rgb; /* 0x60 */
+
+	unsigned int _64_6c[3];
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int vxwidth:13;
+			unsigned int _13_15:3;
+			unsigned int dst_vxwidth:13;
+		} b;
+	} vxwidth; /* 0x70 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int h:1;
+			unsigned int _01_15:15;
+			unsigned int v:1;
+		} b;
+	} sclup_en; /* 0x74 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int thr:13;
+			unsigned int _13_15:3;
+			unsigned int substep:13;
+		} b;
+	} vscale1; /* 0x78 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int substepcnt:13;
+			unsigned int _13_15:3;
+			unsigned int step:13;
+		} b;
+	} vscale2; /* 0x7c */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int stepcnt:17;
+		} b;
+	} vscale3; /* 0x80 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int thr:13;
+			unsigned int _13_15:3;
+			unsigned int substep:13;
+		} b;
+	} hscale1; /* 0x84 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int substepcnt:13;
+			unsigned int _13_15:3;
+			unsigned int step:13;
+		} b;
+	} hscale2; /* 0x88 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int stepcnt:17;
+		} b;
+	} hscale3; /* 0x8c */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int y_req_num:8;
+			unsigned int c_req_num:8;
+		} b;
+	} r_req_num; /* 0x90 */
+
+	unsigned int scldw; /* 0x94 */ /* (VPU path, scale dn)
+					0 - bilinear mode, quality better */
+	unsigned int sw_426; /* 0x98 */ /* 1-follow 426, 0-437 */
+	unsigned int vbypass; /* 0x9c */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int enable:1;
+			unsigned int _1_3:3;
+			unsigned int err_off:1; /*disable TG_EN in tg timeout*/
+			unsigned int _5_7:3;
+			unsigned int watchdog_enable:1;
+			unsigned int _9_15:7;
+			unsigned int rdcyc:8;
+			unsigned int oneshot:1; /* sacling complete will set
+							SCL tg enable to 0 */
+		} b;
+	} tg_ctl; /* 0xa0 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int h_allpixel:13;
+			unsigned int _13_15:3;
+			unsigned int v_allline:13;
+		} b;
+	} tg_total; /* 0xa4 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int v_actbg:8;
+			unsigned int _8_15:8;
+			unsigned int v_actend:13;
+		} b;
+	} tg_v_active; /* 0xa8 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int h_actbg:10;
+			unsigned int _10_15:6;
+			unsigned int h_actend:13;
+		} b;
+	} tg_h_active; /* 0xac */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int vbie:7;
+			unsigned int _7:1;
+			unsigned int pvbi:5;
+		} b;
+	} tg_vbi; /* 0xb0 */
+
+	unsigned int tg_watchdog; /* 0xb4 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int tgerr:1;
+		} b;
+	} tg_sts; /* 0xb8 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int enable:1;
+		} b;
+	} tg_govw; /* 0xbc */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int mif_enable:1; /*0:Disable, 1:Enable */
+			unsigned int _1_3:3;
+			unsigned int rgb_mode:2; /*0:YC,1:RGB565,3:RGB32 */
+			unsigned int _6_7:2;
+			unsigned int src_disp_fmt:1; /*420C 0:Frame, 1:Field */
+			unsigned int yuv:2; /*0:422,1:420,2:444*/
+			unsigned int rgb:1; /*0:YCbCr, 1:RGB32 */
+			unsigned int h264:1; /*0:MPEG, 1:H264 */
+			unsigned int _13_15:3;
+			unsigned int field:1; /*0:Frame, 1:Field */
+			unsigned int _17_23:7;
+			unsigned int colorbar_enable:1;
+			unsigned int colorbar_mode:1;
+			unsigned int colorbar_inv:1;
+		} b;
+	} r_ctl; /* 0xc0 */
+
+	unsigned int r_ysa; /* 0xc4 */
+	unsigned int r_csa; /* 0xc8 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int fb_w:13;
+			unsigned int _13_15:3;
+			unsigned int pix_w:13;
+		} b;
+	} r_h_size; /* 0xcc */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int hcrop:13;
+			unsigned int _13_15:3;
+			unsigned int vcrop:13;
+		} b;
+	} r_crop; /* 0xd0 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int thr:4;
+			unsigned int _4_7:4;
+			unsigned int r1_mif_err:1;
+			unsigned int r2_mif_err:1;
+		} b;
+	} r_fifo_ctl; /* 0xd4 */
+
+	unsigned int _d8_dc[2];
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int mif_enable:1;
+			unsigned int _1_7:7;
+			unsigned int yuv:1; /* 0-444,1-422 */
+			unsigned int rgb:1; /* 0-YC,1-RGB32 */
+		} b;
+	} w_ctl; /* 0xe0 */
+
+	unsigned int w_ysa; /* 0xe4 */
+	unsigned int w_csa; /* 0xe8 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int fb_w:13;
+			unsigned int _13_15:3;
+			unsigned int pxl_w:13;
+		} b;
+	} w_y_time; /* 0xec */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int fb_w:13;
+			unsigned int _13_15:3;
+			unsigned int pxl_w:12;
+		} b;
+	} w_c_time; /* 0xf0 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int mif_c_err:1;
+			unsigned int _1_7:7;
+			unsigned int mif_y_err:1;
+			unsigned int _9_15:7;
+			unsigned int mif_rgb_err:1;
+		} b;
+	} w_ff_ctl; /* 0xf4 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int mif_c_err:1;
+			unsigned int mif_y_err:1;
+			unsigned int mif_rgb_err:1;
+			unsigned int _3_7:5;
+			unsigned int r2_mif_enable:1;
+			unsigned int r1_mif_enable:1;
+			unsigned int _10_15:6;
+			unsigned int tg_err:1;
+		} b;
+	} w_int_en; /* 0xf8 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int h:1;
+			unsigned int _1_7:7;
+			unsigned int v:1;
+		} b;
+	} true_bilinear; /* 0xfc */
+};
+
+struct scl_base2_regs {
+	union {
+		unsigned int val;
+		struct {
+			unsigned int mode:1; /* 0-RGB2YC,1-YC2RGB */
+			unsigned int _01_07:7;
+			unsigned int clamp_enable:1; /* clamp to 16-235 */
+			unsigned int _09_15:7;
+			unsigned int enable:1;
+		} b;
+	} csc_ctl; /* 0x0 */
+
+	unsigned int csc1; /* 0x4 */
+	unsigned int csc2; /* 0x8 */
+	unsigned int csc3; /* 0xc */
+	unsigned int csc4; /* 0x10 */
+	unsigned int csc5; /* 0x14 */
+	unsigned int csc6; /* 0x18 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int enable:1;
+			unsigned int _01_07:7;
+			unsigned int data:8;
+		} b;
+	} argb_alpha; /* 0x1c */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int mode:2; /* 0-888,1-555,2-666,3-565 */
+		} b;
+	} igs; /* 0x20 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int mode:1; /* 0-CCIR/ITU-601 */
+			unsigned int _01_07:7;
+			unsigned int clamp:1; /* 0-direct,1-16-235 */
+			unsigned int _09_15:7;
+			unsigned int enable:1;
+		} b;
+	} r2_csc; /* 0x24 */
+
+	unsigned int r2_csc1; /* 0x28 */
+	unsigned int r2_csc2; /* 0x2c */
+	unsigned int r2_csc3; /* 0x30 */
+	unsigned int r2_csc4; /* 0x34 */
+	unsigned int r2_csc5; /* 0x38 */
+	unsigned int r2_csc6; /* 0x3c */
+	unsigned int _40_9c[24];
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int h:1;
+			unsigned int _01_07:7;
+			unsigned int v:1;
+		} b;
+	} recursive_mode; /* 0xa0 */
+
+	unsigned int _a4_bc[7];
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int deblock:1;
+			unsigned int field_deflicker:1;
+			unsigned int frame_deflicker:1;
+		} b;
+	} field_mode; /* 0xc0 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int layer1_boundary:8;
+			unsigned int layer2_boundary:8;
+		} b;
+	} dblk_threshold; /* 0xc4 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int condition:1; /* 0-up or down,1-up & down */
+			unsigned int _01_07:7;
+			unsigned int y_thd:8;
+			unsigned int c_thd:8;
+		} b;
+	} field_flicker; /* 0xc8 */
+	union {
+		unsigned int val;
+		struct {
+			unsigned int rgb:1; /* 0-Y,1-RGB */
+			unsigned int _01_07:7;
+			unsigned int sampler:5; /* 2^x */
+			unsigned int _13_15:3;
+			unsigned int scene_chg_thd:8;
+		} b;
+	} frame_flicker; /* 0xcc */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int rdcyc_1t:1;
+		} b;
+	} readcyc_1t; /* 0xd0 */
+
+	unsigned int _d4_e0[4];
+};
+
+#define REG_SCL_BASE1_BEGIN	(SCL_BASE_ADDR + 0x00)
+#define REG_SCL_BASE1_END	(SCL_BASE_ADDR + 0xFC)
+#define REG_SCL_BASE2_BEGIN	(SCL_BASE2_ADDR + 0x00)
+#define REG_SCL_BASE2_END	(SCL_BASE2_ADDR + 0xE0)
+
+#ifndef SCL_C
+extern HW_REG struct scl_base1_regs *scl_regs1;
+extern HW_REG struct scl_base2_regs *scl_regs2;
+#endif
+#endif /* WMT_SCL_REG_H */
diff --git a/drivers/video/wmt/hw/wmt-vpp-hw.h b/drivers/video/wmt/hw/wmt-vpp-hw.h
new file mode 100755
index 00000000..599ebe03
--- /dev/null
+++ b/drivers/video/wmt/hw/wmt-vpp-hw.h
@@ -0,0 +1,137 @@
+/*++
+ * linux/drivers/video/wmt/hw/wmt-vpp-hw.h
+ * WonderMedia video post processor (VPP) driver
+ *
+ * Copyright c 2014  WonderMedia  Technologies, Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * WonderMedia Technologies, Inc.
+ * 4F, 533, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C
+--*/
+
+#ifndef WMT_VPP_HW_H
+#define WMT_VPP_HW_H
+
+/*-------------------- EXPORTED PRIVATE CONSTANTS ----------------------------*/
+/*
+* Product ID / Project ID
+* 84xx series: 8420/3300, 8430/3357, 8435/3437
+* 85xx series: 8500/3400, 8510/3426, 8520/3429
+*/
+/* 84xx series, (1-100) with VDU & DSP */
+#define VIA_PID_8420	10	/* 3300 */
+#define VIA_PID_8430	12	/* 3357 */
+#define WMT_PID_8435	14	/* 3437 */
+#define WMT_PID_8440	16	/* 3451 */
+#define WMT_PID_8425	18	/* 3429 */
+#define WMT_PID_8710	20	/* 3445 */
+#define WMT_PID_8950	22	/* 3481 */
+#define WMT_PID_8980	24	/* 3498 */
+
+/* 85xx series, (101-200) */
+#define VIA_PID_8500	110	/* 3400 */
+#define WMT_PID_8505	111
+#define WMT_PID_8510	112	/* 3426* */
+
+#define WMT_PID_8950_A	1
+
+/* current pid */
+#define WMT_CUR_PID	WMT_PID_8980
+#define WMT_SUB_PID	0
+
+/* #define WMT_SUB_PID	WMT_PID_8505 */
+#ifndef WMT_SUB_PID
+	#define WMT_SUB_PID	0
+#endif
+
+/* VPP interrupt map to irq */
+#define VPP_IRQ_SCL_FINISH	IRQ_VPP_IRQ0
+#define VPP_IRQ_SCL		IRQ_VPP_IRQ1
+#define VPP_IRQ_SCL444_TG	IRQ_VPP_IRQ2
+#define VPP_IRQ_VPPM		IRQ_VPP_IRQ3
+#define VPP_IRQ_GOVW_TG		IRQ_VPP_IRQ4
+#define VPP_IRQ_GOVW		IRQ_VPP_IRQ5
+#define VPP_IRQ_GOVM		IRQ_VPP_IRQ6
+#define VPP_IRQ_GE		IRQ_VPP_IRQ7
+#define VPP_IRQ_GOVRH_TG	IRQ_VPP_IRQ8	/* PVBI or VBIS or VBIE */
+#define VPP_IRQ_DVO		IRQ_VPP_IRQ9
+#define VPP_IRQ_VID		IRQ_VPP_IRQ10
+#define VPP_IRQ_GOVR		IRQ_VPP_IRQ11	/* underrun & mif */
+#define VPP_IRQ_GOVRSD_TG	IRQ_VPP_IRQ12
+#define VPP_IRQ_VPU		IRQ_VPP_IRQ13
+#define VPP_IRQ_VPU_TG		IRQ_VPP_IRQ14
+#define VPP_IRQ_HDMI_CP		IRQ_VPP_IRQ15
+#define VPP_IRQ_HDMI_HPDH	IRQ_VPP_IRQ16
+#define VPP_IRQ_HDMI_HPDL	IRQ_VPP_IRQ17
+#define VPP_IRQ_GOVR_0		IRQ_VPP_IRQ18
+#define VPP_IRQ_GOVR_2		IRQ_VPP_IRQ19
+#define VPP_IRQ_CEC		IRQ_VPP_IRQ20
+#define VPP_IRQ_GOVR2_0		IRQ_VPP_IRQ21
+#define VPP_IRQ_GOVR2		IRQ_VPP_IRQ22
+#define VPP_IRQ_GOVR2_2		IRQ_VPP_IRQ23
+#define VPP_IRQ_DVO2		IRQ_VPP_IRQ24
+#define VPP_IRQ_GOVR2_TG	IRQ_VPP_IRQ25
+
+/* DVI I2C */
+#define VPP_DVI_I2C_DEFAULT	1 /* default i2c bus */
+#define VPP_DVI_I2C_SW_BIT	0x10 /* hw or sw i2c */
+#define VPP_DVI_I2C_ID_MASK	0x1F
+#define VPP_DVI_I2C_ID		g_vpp.dvi_i2c_no
+#define VPP_DVI_EDID_ID		(VPP_DVI_I2C_SW_BIT + 0x1) /* DVO EDID use
+								sw i2c bus 1 */
+
+/* vout */
+#define VPP_VOUT_INFO_NUM	5 /* linux fb or govr number */
+
+#define VPP_VOUT_NUM		2
+#define VPP_VOUT_ALL		0xFFFFFFFF
+#define VPP_VOUT_NUM_HDMI	0
+#define VPP_VOUT_NUM_LVDS	1
+#define VPP_VOUT_NUM_DVI	1
+
+#define WMT_FTBLK_VOUT_DVI
+#define WMT_FTBLK_VOUT_HDMI
+#define WMT_FTBLK_VOUT_LVDS
+
+/* hw parameter */
+#define VPP_DVI_INT_DEFAULT	0 /* default interrupt gpio */
+#define VPP_VOINT_NO		g_vpp.dvi_int_no
+#define VPP_UBOOT_COLFMT	VDO_COL_FMT_RGB_565
+#define VPP_FB_ADDR_ALIGN	64
+#define VPP_FB_WIDTH_ALIGN	64 /* hw should 4 byte align,android
+	framework 8 byte align modify by aksenxu VPU need 64bytes alignment
+	you need modify FramebufferNativeWindow::FramebufferNativeWindow
+	in android framework together */
+#define VPP_GOVR_DVO_DELAY_24	0x4036
+#define VPP_GOVR_DVO_DELAY_12	0x120
+
+/*-------------------- DEPENDENCY -------------------------------------*/
+#ifdef __KERNEL__
+#ifndef CONFIG_WMT_HDMI
+#undef WMT_FTBLK_VOUT_HDMI
+#endif
+#endif
+
+#include "wmt-vpp-reg.h"
+#include "wmt-govrh-reg.h"
+#include "wmt-lvds-reg.h"
+#ifdef WMT_FTBLK_VOUT_HDMI
+#include "wmt-hdmi-reg.h"
+#endif
+#include "wmt-scl-reg.h"
+#ifndef CONFIG_UBOOT
+#include "wmt-cec-reg.h"
+#endif
+#endif /* WMT_VPP_HW_H */
diff --git a/drivers/video/wmt/hw/wmt-vpp-reg.h b/drivers/video/wmt/hw/wmt-vpp-reg.h
new file mode 100755
index 00000000..b96e64db
--- /dev/null
+++ b/drivers/video/wmt/hw/wmt-vpp-reg.h
@@ -0,0 +1,132 @@
+/*++
+ * linux/drivers/video/wmt/hw/wmt-vpp-reg.h
+ * WonderMedia video post processor (VPP) driver
+ *
+ * Copyright c 2014  WonderMedia  Technologies, Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * WonderMedia Technologies, Inc.
+ * 4F, 533, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C
+--*/
+
+#ifndef WMT_VPP_REG_H
+#define WMT_VPP_REG_H
+
+#define VPP_DAC_SEL_TV		1
+#define VPP_DAC_SEL_VGA		0
+
+struct vppm_base_regs {
+	unsigned int _00; /* 0x00 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int _0_7:8;
+			unsigned int govrh_pvbi:1;
+			unsigned int govrh_vbis:1;
+			unsigned int govrh_vbie:1;
+			unsigned int _11:1;
+			unsigned int govrh2_pvbi:1;
+			unsigned int govrh2_vbis:1;
+			unsigned int govrh2_vbie:1;
+			unsigned int _15:1;
+			unsigned int scl_pvbi:1;
+			unsigned int scl_vbis:1;
+			unsigned int scl_vbie:1;
+			unsigned int _19:1;
+			unsigned int ge_tg:1;
+		} b;
+	} int_sts; /* 0x4 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int _0_7:8;
+			unsigned int govrh_pvbi:1;
+			unsigned int govrh_vbis:1;
+			unsigned int govrh_vbie:1;
+			unsigned int _11:1;
+			unsigned int govrh2_pvbi:1;
+			unsigned int govrh2_vbis:1;
+			unsigned int govrh2_vbie:1;
+			unsigned int _15:1;
+			unsigned int scl_pvbi:1;
+			unsigned int scl_vbis:1;
+			unsigned int scl_vbie:1;
+			unsigned int _19:1;
+			unsigned int ge_tg:1;
+		} b;
+	} int_en; /* 0x8 */
+
+	unsigned int watch_sel; /* 0x0C */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int scl:1;
+			unsigned int _1_7:7;
+			unsigned int vid:1;
+			unsigned int _9_15:7;
+			unsigned int ge:1;
+		} b;
+	} sw_reset1; /* 0x10 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int govrh:1;
+			unsigned int _1_3:3;
+			unsigned int lvds:1;
+			unsigned int _5_7:3;
+			unsigned int dvo:1;
+			unsigned int dvo2:1;
+			unsigned int _10_11:2;
+			unsigned int cec:1;
+		} b;
+	} sw_reset2; /* 0x14 */
+
+	unsigned int dac_sel; /* 0x18 */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int hdmi:1;
+			unsigned int _1_7:7;
+			unsigned int ddc:1;
+			unsigned int _9_15:7;
+			unsigned int hdmi2:1;
+		} b;
+	} sw_reset3; /* 0x1C */
+
+	union {
+		unsigned int val;
+		struct {
+			unsigned int disable:1;
+			unsigned int _1_7:7;
+			unsigned int csi_act_lane_sel:1; /*0-lane 0/1,1-2/3*/
+		} b;
+	} sscg; /* 0x20 */
+};
+
+#define REG_VPP_BEGIN		(VPP_BASE_ADDR + 0x00)
+#define REG_VPP_END		(VPP_BASE_ADDR + 0x28)
+
+#ifndef VPPM_C
+extern HW_REG struct vppm_base_regs *vppm_regs;
+#endif
+
+
+#endif /* WMT_VPP_REG_H */
+