Moved, renamed, and deleted files

The original directory structure was scattered and unorganized.
Changes are basically to make it look like kernel structure.

20 files changed, 30129 insertions, 0 deletions

diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/Hal8188EPwrSeq.c b/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/Hal8188EPwrSeq.c
new file mode 100755
index 00000000..c38c25a0
--- /dev/null
+++ b/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/Hal8188EPwrSeq.c
@@ -0,0 +1,97 @@
+/******************************************************************************

+ *

+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.

+ *                                        

+ * This program is free software; you can redistribute it and/or modify it

+ * under the terms of version 2 of the GNU General Public License as

+ * published by the Free Software Foundation.

+ *

+ * This program is distributed in the hope that it will be useful, but WITHOUT

+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for

+ * more details.

+ *

+ * You should have received a copy of the GNU General Public License along with

+ * this program; if not, write to the Free Software Foundation, Inc.,

+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA

+ *

+ *

+ ******************************************************************************/

+

+#include "Hal8188EPwrSeq.h"

+#include <rtl8188e_hal.h>

+

+/* 

+    drivers should parse below arrays and do the corresponding actions

+*/

+//3 Power on  Array

+WLAN_PWR_CFG rtl8188E_power_on_flow[RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS]=

+{

+	RTL8188E_TRANS_CARDEMU_TO_ACT

+	RTL8188E_TRANS_END

+};

+

+//3Radio off Array

+WLAN_PWR_CFG rtl8188E_radio_off_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_END_STEPS]=

+{

+	RTL8188E_TRANS_ACT_TO_CARDEMU

+	RTL8188E_TRANS_END

+};

+

+//3Card Disable Array

+WLAN_PWR_CFG rtl8188E_card_disable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS]=

+{

+	RTL8188E_TRANS_ACT_TO_CARDEMU

+	RTL8188E_TRANS_CARDEMU_TO_CARDDIS

+	RTL8188E_TRANS_END

+};

+

+//3 Card Enable Array

+WLAN_PWR_CFG rtl8188E_card_enable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS]=

+{

+	RTL8188E_TRANS_CARDDIS_TO_CARDEMU

+	RTL8188E_TRANS_CARDEMU_TO_ACT

+	RTL8188E_TRANS_END

+};

+

+//3Suspend Array

+WLAN_PWR_CFG rtl8188E_suspend_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS]=

+{

+	RTL8188E_TRANS_ACT_TO_CARDEMU

+	RTL8188E_TRANS_CARDEMU_TO_SUS

+	RTL8188E_TRANS_END

+};

+

+//3 Resume Array

+WLAN_PWR_CFG rtl8188E_resume_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS]=

+{

+	RTL8188E_TRANS_SUS_TO_CARDEMU

+	RTL8188E_TRANS_CARDEMU_TO_ACT

+	RTL8188E_TRANS_END

+};

+

+

+//3HWPDN Array

+WLAN_PWR_CFG rtl8188E_hwpdn_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS]=

+{

+	RTL8188E_TRANS_ACT_TO_CARDEMU

+	RTL8188E_TRANS_CARDEMU_TO_PDN	

+	RTL8188E_TRANS_END

+};

+

+//3 Enter LPS 

+WLAN_PWR_CFG rtl8188E_enter_lps_flow[RTL8188E_TRANS_ACT_TO_LPS_STEPS+RTL8188E_TRANS_END_STEPS]=

+{

+	//FW behavior

+	RTL8188E_TRANS_ACT_TO_LPS	

+	RTL8188E_TRANS_END

+};

+

+//3 Leave LPS 

+WLAN_PWR_CFG rtl8188E_leave_lps_flow[RTL8188E_TRANS_LPS_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS]=

+{

+	//FW behavior

+	RTL8188E_TRANS_LPS_TO_ACT

+	RTL8188E_TRANS_END

+};

+

diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/rtl8188e_cmd.c b/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/rtl8188e_cmd.c
new file mode 100755
index 00000000..f75703cd
--- /dev/null
+++ b/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/rtl8188e_cmd.c
@@ -0,0 +1,1194 @@
+/******************************************************************************

+ *

+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.

+ *

+ * This program is free software; you can redistribute it and/or modify it

+ * under the terms of version 2 of the GNU General Public License as

+ * published by the Free Software Foundation.

+ *

+ * This program is distributed in the hope that it will be useful, but WITHOUT

+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for

+ * more details.

+ *

+ * You should have received a copy of the GNU General Public License along with

+ * this program; if not, write to the Free Software Foundation, Inc.,

+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA

+ *

+ *

+ ******************************************************************************/

+#define _RTL8188E_CMD_C_

+

+#include <drv_conf.h>

+#include <osdep_service.h>

+#include <drv_types.h>

+#include <recv_osdep.h>

+#include <cmd_osdep.h>

+#include <mlme_osdep.h>

+#include <rtw_byteorder.h>

+#include <circ_buf.h>

+#include <rtw_ioctl_set.h>

+

+#include <rtl8188e_hal.h>

+

+#define CONFIG_H2C_EF

+

+#define RTL88E_MAX_H2C_BOX_NUMS	4

+#define RTL88E_MAX_CMD_LEN	7

+#define RTL88E_MESSAGE_BOX_SIZE		4

+#define RTL88E_EX_MESSAGE_BOX_SIZE	4

+

+

+static u8 _is_fw_read_cmd_down(_adapter* padapter, u8 msgbox_num)

+{

+	u8	read_down = _FALSE;

+	int 	retry_cnts = 100;

+

+	u8 valid;

+

+	//DBG_8192C(" _is_fw_read_cmd_down ,reg_1cc(%x),msg_box(%d)...\n",rtw_read8(padapter,REG_HMETFR),msgbox_num);

+

+	do{

+		valid = rtw_read8(padapter,REG_HMETFR) & BIT(msgbox_num);

+		if(0 == valid ){

+			read_down = _TRUE;

+		}

+#ifdef CONFIG_WOWLAN

+		rtw_msleep_os(2);

+#endif

+	}while( (!read_down) && (retry_cnts--));

+

+	return read_down;

+

+}

+

+

+/*****************************************

+* H2C Msg format :

+* 0x1DF - 0x1D0

+*| 31 - 8	| 7-5 	 4 - 0	|

+*| h2c_msg 	|Class_ID CMD_ID	|

+*

+* Extend 0x1FF - 0x1F0

+*|31 - 0	  |

+*|ext_msg|

+******************************************/

+static s32 FillH2CCmd_88E(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer)

+{

+	u8 bcmd_down = _FALSE;

+	s32 retry_cnts = 100;

+	u8 h2c_box_num;

+	u32	msgbox_addr;

+	u32 msgbox_ex_addr;

+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);

+	u8 cmd_idx,ext_cmd_len;

+	u32	h2c_cmd = 0;

+	u32	h2c_cmd_ex = 0;

+	s32 ret = _FAIL;

+

+_func_enter_;

+

+	padapter = GET_PRIMARY_ADAPTER(padapter);		

+	pHalData = GET_HAL_DATA(padapter);

+

+	if(padapter->bFWReady == _FALSE)

+	{

+		DBG_8192C("FillH2CCmd_88E(): return H2C cmd because fw is not ready\n");

+		return ret;

+	}

+

+	_enter_critical_mutex(&(adapter_to_dvobj(padapter)->h2c_fwcmd_mutex), NULL);

+

+	if (!pCmdBuffer) {

+		goto exit;

+	}

+	if (CmdLen > RTL88E_MAX_CMD_LEN) {

+		goto exit;

+	}

+	if (padapter->bSurpriseRemoved == _TRUE)

+		goto exit;

+

+	//pay attention to if  race condition happened in  H2C cmd setting.

+	do{

+		h2c_box_num = pHalData->LastHMEBoxNum;

+

+		if(!_is_fw_read_cmd_down(padapter, h2c_box_num)){

+			DBG_8192C(" fw read cmd failed...\n");

+			goto exit;

+		}

+

+		*(u8*)(&h2c_cmd) = ElementID;

+

+		if(CmdLen<=3)

+		{

+			_rtw_memcpy((u8*)(&h2c_cmd)+1, pCmdBuffer, CmdLen );

+		}

+		else{			

+			_rtw_memcpy((u8*)(&h2c_cmd)+1, pCmdBuffer,3);

+			ext_cmd_len = CmdLen-3;	

+			_rtw_memcpy((u8*)(&h2c_cmd_ex), pCmdBuffer+3,ext_cmd_len );

+

+			//Write Ext command

+			msgbox_ex_addr = REG_HMEBOX_EXT_0 + (h2c_box_num *RTL88E_EX_MESSAGE_BOX_SIZE);

+			#ifdef CONFIG_H2C_EF

+			for(cmd_idx=0;cmd_idx<ext_cmd_len;cmd_idx++ ){

+				rtw_write8(padapter,msgbox_ex_addr+cmd_idx,*((u8*)(&h2c_cmd_ex)+cmd_idx));

+			}

+			#else

+			h2c_cmd_ex = le32_to_cpu( h2c_cmd_ex );

+			rtw_write32(padapter, msgbox_ex_addr, h2c_cmd_ex);

+			#endif

+		}

+		// Write command

+		msgbox_addr =REG_HMEBOX_0 + (h2c_box_num *RTL88E_MESSAGE_BOX_SIZE);

+		#ifdef CONFIG_H2C_EF

+		for(cmd_idx=0;cmd_idx<RTL88E_MESSAGE_BOX_SIZE;cmd_idx++ ){

+			rtw_write8(padapter,msgbox_addr+cmd_idx,*((u8*)(&h2c_cmd)+cmd_idx));

+		}

+		#else

+		h2c_cmd = le32_to_cpu( h2c_cmd );

+		rtw_write32(padapter,msgbox_addr, h2c_cmd);

+		#endif

+

+		bcmd_down = _TRUE;

+

+	//	DBG_8192C("MSG_BOX:%d,CmdLen(%d), reg:0x%x =>h2c_cmd:0x%x, reg:0x%x =>h2c_cmd_ex:0x%x ..\n"

+	//	 	,pHalData->LastHMEBoxNum ,CmdLen,msgbox_addr,h2c_cmd,msgbox_ex_addr,h2c_cmd_ex);

+

+		pHalData->LastHMEBoxNum = (h2c_box_num+1) % RTL88E_MAX_H2C_BOX_NUMS;

+

+	}while((!bcmd_down) && (retry_cnts--));

+

+	ret = _SUCCESS;

+

+exit:

+

+	_exit_critical_mutex(&(adapter_to_dvobj(padapter)->h2c_fwcmd_mutex), NULL);	

+

+_func_exit_;

+

+	return ret;

+}

+

+u8 rtl8192c_h2c_msg_hdl(_adapter *padapter, unsigned char *pbuf)

+{

+	u8 ElementID, CmdLen;

+	u8 *pCmdBuffer;

+	struct cmd_msg_parm  *pcmdmsg;

+

+	if(!pbuf)

+		return H2C_PARAMETERS_ERROR;

+

+	pcmdmsg = (struct cmd_msg_parm*)pbuf;

+	ElementID = pcmdmsg->eid;

+	CmdLen = pcmdmsg->sz;

+	pCmdBuffer = pcmdmsg->buf;

+

+	FillH2CCmd_88E(padapter, ElementID, CmdLen, pCmdBuffer);

+

+	return H2C_SUCCESS;

+}

+/*

+#if defined(CONFIG_AUTOSUSPEND) && defined(SUPPORT_HW_RFOFF_DETECTED)

+u8 rtl8192c_set_FwSelectSuspend_cmd(_adapter *padapter ,u8 bfwpoll, u16 period)

+{

+	u8	res=_SUCCESS;

+	struct H2C_SS_RFOFF_PARAM param;

+	DBG_8192C("==>%s bfwpoll(%x)\n",__FUNCTION__,bfwpoll);

+	param.gpio_period = period;//Polling GPIO_11 period time

+	param.ROFOn = (_TRUE == bfwpoll)?1:0;

+	FillH2CCmd_88E(padapter, SELECTIVE_SUSPEND_ROF_CMD, sizeof(param), (u8*)(&param));		

+	return res;

+}

+#endif //CONFIG_AUTOSUSPEND && SUPPORT_HW_RFOFF_DETECTED

+*/

+u8 rtl8188e_set_rssi_cmd(_adapter*padapter, u8 *param)

+{

+	u8	res=_SUCCESS;

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);

+_func_enter_;

+

+	if(pHalData->fw_ractrl == _TRUE){

+		#if 0

+	*((u32*) param ) = cpu_to_le32( *((u32*) param ) );

+

+		FillH2CCmd_88E(padapter, RSSI_SETTING_EID, 3, param);

+		#endif

+	}else{

+		DBG_8192C("==>%s fw dont support RA \n",__FUNCTION__);

+		res=_FAIL;

+	}

+

+_func_exit_;

+

+	return res;

+}

+

+u8 rtl8188e_set_raid_cmd(_adapter*padapter, u32 mask)

+{

+	u8	buf[3];

+	u8	res=_SUCCESS;

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);

+_func_enter_;

+	if(pHalData->fw_ractrl == _TRUE){

+		_rtw_memset(buf, 0, 3);

+		mask = cpu_to_le32( mask );

+		_rtw_memcpy(buf, &mask, 3);		

+

+		FillH2CCmd_88E(padapter, H2C_DM_MACID_CFG, 3, buf);

+	}else{

+		DBG_8192C("==>%s fw dont support RA \n",__FUNCTION__);

+		res=_FAIL;

+	}	

+

+_func_exit_;

+

+	return res;

+

+}

+

+//bitmap[0:27] = tx_rate_bitmap

+//bitmap[28:31]= Rate Adaptive id

+//arg[0:4] = macid

+//arg[5] = Short GI

+void rtl8188e_Add_RateATid(PADAPTER pAdapter, u32 bitmap, u8 arg, u8 rssi_level)

+{

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);

+	//struct dm_priv	*pdmpriv = &pHalData->dmpriv;

+

+	u8 macid, init_rate, raid, shortGIrate=_FALSE;

+

+#ifdef CONFIG_CONCURRENT_MODE

+	if(rtw_buddy_adapter_up(pAdapter) && pAdapter->adapter_type > PRIMARY_ADAPTER)	

+		pHalData = GET_HAL_DATA(pAdapter->pbuddy_adapter);				

+#endif //CONFIG_CONCURRENT_MODE

+

+	macid = arg&0x1f;

+

+#ifdef CONFIG_ODM_REFRESH_RAMASK

+	raid = (bitmap>>28) & 0x0f;

+	bitmap &=0x0fffffff;	

+	

+	if(rssi_level != DM_RATR_STA_INIT)

+		bitmap = ODM_Get_Rate_Bitmap(&pHalData->odmpriv, macid, bitmap, rssi_level);		

+	

+	bitmap |= ((raid<<28)&0xf0000000);

+#endif //CONFIG_ODM_REFRESH_RAMASK

+		

+

+	init_rate = get_highest_rate_idx(bitmap&0x0fffffff)&0x3f;

+

+	shortGIrate = (arg&BIT(5)) ? _TRUE:_FALSE;

+

+	if (shortGIrate==_TRUE)

+		init_rate |= BIT(6);

+	

+

+	//rtw_write8(pAdapter, (REG_INIDATA_RATE_SEL+macid), (u8)init_rate);

+	

+	raid = (bitmap>>28) & 0x0f;

+

+	bitmap &= 0x0fffffff;

+	

+	DBG_871X("%s=> mac_id:%d , raid:%d , ra_bitmap=0x%x, shortGIrate=0x%02x\n", 

+			__FUNCTION__,macid ,raid ,bitmap, shortGIrate);

+

+

+#if(RATE_ADAPTIVE_SUPPORT == 1)

+	ODM_RA_UpdateRateInfo_8188E(

+			&(pHalData->odmpriv),

+			macid,

+			raid, 

+			bitmap,

+			shortGIrate

+			);

+#endif	

+

+}

+

+void rtl8188e_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode)

+{

+	SETPWRMODE_PARM H2CSetPwrMode;

+	struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;

+	u8	RLBM = 0; // 0:Min, 1:Max , 2:User define

+_func_enter_;

+

+	DBG_871X("%s: Mode=%d SmartPS=%d UAPSD=%d\n", __FUNCTION__,

+			Mode, pwrpriv->smart_ps, padapter->registrypriv.uapsd_enable);

+

+	switch(Mode)

+	{

+		case PS_MODE_ACTIVE:

+			H2CSetPwrMode.Mode = 0;

+			break;

+		case PS_MODE_MIN:

+			H2CSetPwrMode.Mode = 1;

+			break;

+		case PS_MODE_MAX:

+			RLBM = 1;

+			H2CSetPwrMode.Mode = 1;

+			break;

+		case PS_MODE_DTIM:

+			RLBM = 2;

+			H2CSetPwrMode.Mode = 1;

+			break;

+		case PS_MODE_UAPSD_WMM:

+			H2CSetPwrMode.Mode = 2;

+			break;

+		default:

+			H2CSetPwrMode.Mode = 0;

+			break;

+	}

+

+	//H2CSetPwrMode.Mode = Mode;

+

+	H2CSetPwrMode.SmartPS_RLBM = (((pwrpriv->smart_ps<<4)&0xf0) | (RLBM & 0x0f));

+

+	H2CSetPwrMode.AwakeInterval = 1;

+

+	H2CSetPwrMode.bAllQueueUAPSD = padapter->registrypriv.uapsd_enable;

+

+	if(Mode > 0)

+	{

+		H2CSetPwrMode.PwrState = 0x00;// AllON(0x0C), RFON(0x04), RFOFF(0x00)

+#ifdef CONFIG_EXT_CLK

+		H2CSetPwrMode.Mode |= BIT(7);//supporting 26M XTAL CLK_Request feature.

+#endif //CONFIG_EXT_CLK

+	}

+	else

+		H2CSetPwrMode.PwrState = 0x0C;// AllON(0x0C), RFON(0x04), RFOFF(0x00)

+

+	FillH2CCmd_88E(padapter, H2C_PS_PWR_MODE, sizeof(H2CSetPwrMode), (u8 *)&H2CSetPwrMode);

+	

+

+_func_exit_;

+}

+

+void rtl8188e_set_FwMediaStatus_cmd(PADAPTER padapter, u16 mstatus_rpt )

+{

+	u8 opmode,macid;

+	u16 mst_rpt = cpu_to_le16 (mstatus_rpt);

+	opmode = (u8) mst_rpt;

+	macid = (u8)(mst_rpt >> 8)  ;

+	

+	DBG_871X("### %s: MStatus=%x MACID=%d \n", __FUNCTION__,opmode,macid);

+	FillH2CCmd_88E(padapter, H2C_COM_MEDIA_STATUS_RPT, sizeof(mst_rpt), (u8 *)&mst_rpt);

+}

+

+void ConstructBeacon(_adapter *padapter, u8 *pframe, u32 *pLength)

+{

+	struct rtw_ieee80211_hdr	*pwlanhdr;

+	u16					*fctrl;

+	u32					rate_len, pktlen;

+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);

+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);

+	WLAN_BSSID_EX 		*cur_network = &(pmlmeinfo->network);

+	u8	bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};

+

+

+	//DBG_871X("%s\n", __FUNCTION__);

+

+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;

+

+	fctrl = &(pwlanhdr->frame_ctl);

+	*(fctrl) = 0;

+

+	_rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);

+	_rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN);

+	_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN);

+

+	SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/);

+	//pmlmeext->mgnt_seq++;

+	SetFrameSubType(pframe, WIFI_BEACON);

+

+	pframe += sizeof(struct rtw_ieee80211_hdr_3addr);

+	pktlen = sizeof (struct rtw_ieee80211_hdr_3addr);

+

+	//timestamp will be inserted by hardware

+	pframe += 8;

+	pktlen += 8;

+

+	// beacon interval: 2 bytes

+	_rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2);

+

+	pframe += 2;

+	pktlen += 2;

+

+	// capability info: 2 bytes

+	_rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2);

+

+	pframe += 2;

+	pktlen += 2;

+

+	if( (pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)

+	{

+		//DBG_871X("ie len=%d\n", cur_network->IELength);

+		pktlen += cur_network->IELength - sizeof(NDIS_802_11_FIXED_IEs);

+		_rtw_memcpy(pframe, cur_network->IEs+sizeof(NDIS_802_11_FIXED_IEs), pktlen);

+

+		goto _ConstructBeacon;

+	}

+

+	//below for ad-hoc mode

+

+	// SSID

+	pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pktlen);

+

+	// supported rates...

+	rate_len = rtw_get_rateset_len(cur_network->SupportedRates);

+	pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8)? 8: rate_len), cur_network->SupportedRates, &pktlen);

+

+	// DS parameter set

+	pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pktlen);

+

+	if( (pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE)

+	{

+		u32 ATIMWindow;

+		// IBSS Parameter Set...

+		//ATIMWindow = cur->Configuration.ATIMWindow;

+		ATIMWindow = 0;

+		pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pktlen);

+	}

+

+

+	//todo: ERP IE

+

+

+	// EXTERNDED SUPPORTED RATE

+	if (rate_len > 8)

+	{

+		pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pktlen);

+	}

+

+

+	//todo:HT for adhoc

+

+_ConstructBeacon:

+

+	if ((pktlen + TXDESC_SIZE) > 512)

+	{

+		DBG_871X("beacon frame too large\n");

+		return;

+	}

+

+	*pLength = pktlen;

+

+	//DBG_871X("%s bcn_sz=%d\n", __FUNCTION__, pktlen);

+

+}

+

+void ConstructPSPoll(_adapter *padapter, u8 *pframe, u32 *pLength)

+{

+	struct rtw_ieee80211_hdr	*pwlanhdr;

+	u16					*fctrl;

+	u32					pktlen;

+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);

+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);

+

+	//DBG_871X("%s\n", __FUNCTION__);

+

+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;

+

+	// Frame control.

+	fctrl = &(pwlanhdr->frame_ctl);

+	*(fctrl) = 0;

+	SetPwrMgt(fctrl);

+	SetFrameSubType(pframe, WIFI_PSPOLL);

+

+	// AID.

+	SetDuration(pframe, (pmlmeinfo->aid | 0xc000));

+

+	// BSSID.

+	_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);

+

+	// TA.

+	_rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN);

+

+	*pLength = 16;

+}

+

+void ConstructNullFunctionData(

+	PADAPTER padapter,

+	u8		*pframe,

+	u32		*pLength,

+	u8		*StaAddr,

+	u8		bQoS,

+	u8		AC,

+	u8		bEosp,

+	u8		bForcePowerSave)

+{

+	struct rtw_ieee80211_hdr	*pwlanhdr;

+	u16						*fctrl;

+	u32						pktlen;

+	struct mlme_priv		*pmlmepriv = &padapter->mlmepriv;

+	struct wlan_network		*cur_network = &pmlmepriv->cur_network;

+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);

+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);

+

+

+	//DBG_871X("%s:%d\n", __FUNCTION__, bForcePowerSave);

+

+	pwlanhdr = (struct rtw_ieee80211_hdr*)pframe;

+

+	fctrl = &pwlanhdr->frame_ctl;

+	*(fctrl) = 0;

+	if (bForcePowerSave)

+	{

+		SetPwrMgt(fctrl);

+	}

+

+	switch(cur_network->network.InfrastructureMode)

+	{

+		case Ndis802_11Infrastructure:

+			SetToDs(fctrl);

+			_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);

+			_rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN);

+			_rtw_memcpy(pwlanhdr->addr3, StaAddr, ETH_ALEN);

+			break;

+		case Ndis802_11APMode:

+			SetFrDs(fctrl);

+			_rtw_memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN);

+			_rtw_memcpy(pwlanhdr->addr2, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);

+			_rtw_memcpy(pwlanhdr->addr3, myid(&(padapter->eeprompriv)), ETH_ALEN);

+			break;

+		case Ndis802_11IBSS:

+		default:

+			_rtw_memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN);

+			_rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN);

+			_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);

+			break;

+	}

+

+	SetSeqNum(pwlanhdr, 0);

+

+	if (bQoS == _TRUE) {

+		struct rtw_ieee80211_hdr_3addr_qos *pwlanqoshdr;

+

+		SetFrameSubType(pframe, WIFI_QOS_DATA_NULL);

+

+		pwlanqoshdr = (struct rtw_ieee80211_hdr_3addr_qos*)pframe;

+		SetPriority(&pwlanqoshdr->qc, AC);

+		SetEOSP(&pwlanqoshdr->qc, bEosp);

+

+		pktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos);

+	} else {

+		SetFrameSubType(pframe, WIFI_DATA_NULL);

+

+		pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);

+	}

+

+	*pLength = pktlen;

+}

+

+void ConstructProbeRsp(_adapter *padapter, u8 *pframe, u32 *pLength, u8 *StaAddr, BOOLEAN bHideSSID)

+{

+	struct rtw_ieee80211_hdr	*pwlanhdr;

+	u16					*fctrl;

+	u8					*mac, *bssid;

+	u32					pktlen;

+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);

+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);

+	WLAN_BSSID_EX 		*cur_network = &(pmlmeinfo->network);

+

+

+	//DBG_871X("%s\n", __FUNCTION__);

+

+	pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;

+

+	mac = myid(&(padapter->eeprompriv));

+	bssid = cur_network->MacAddress;

+

+	fctrl = &(pwlanhdr->frame_ctl);

+	*(fctrl) = 0;

+	_rtw_memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN);

+	_rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN);

+	_rtw_memcpy(pwlanhdr->addr3, bssid, ETH_ALEN);

+

+	SetSeqNum(pwlanhdr, 0);

+	SetFrameSubType(fctrl, WIFI_PROBERSP);

+

+	pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);

+	pframe += pktlen;

+

+	if(cur_network->IELength>MAX_IE_SZ)

+		return;

+

+	_rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength);

+	pframe += cur_network->IELength;

+	pktlen += cur_network->IELength;

+

+	*pLength = pktlen;

+}

+

+// To check if reserved page content is destroyed by beacon beacuse beacon is too large.

+// 2010.06.23. Added by tynli.

+VOID

+CheckFwRsvdPageContent(

+	IN	PADAPTER		Adapter

+)

+{

+	HAL_DATA_TYPE*	pHalData = GET_HAL_DATA(Adapter);

+	u32	MaxBcnPageNum;

+

+ 	if(pHalData->FwRsvdPageStartOffset != 0)

+ 	{

+ 		/*MaxBcnPageNum = PageNum_128(pMgntInfo->MaxBeaconSize);

+		RT_ASSERT((MaxBcnPageNum <= pHalData->FwRsvdPageStartOffset),

+			("CheckFwRsvdPageContent(): The reserved page content has been"\

+			"destroyed by beacon!!! MaxBcnPageNum(%d) FwRsvdPageStartOffset(%d)\n!",

+			MaxBcnPageNum, pHalData->FwRsvdPageStartOffset));*/

+ 	}

+}

+

+//

+// Description: Fill the reserved packets that FW will use to RSVD page.

+//			Now we just send 4 types packet to rsvd page.

+//			(1)Beacon, (2)Ps-poll, (3)Null data, (4)ProbeRsp.

+//	Input:

+//	    bDLFinished - FALSE: At the first time we will send all the packets as a large packet to Hw,

+//				 		so we need to set the packet length to total lengh.

+//			      TRUE: At the second time, we should send the first packet (default:beacon)

+//						to Hw again and set the lengh in descriptor to the real beacon lengh.

+// 2009.10.15 by tynli.

+static void SetFwRsvdPagePkt(PADAPTER padapter, BOOLEAN bDLFinished)

+{

+	PHAL_DATA_TYPE pHalData;

+	struct xmit_frame	*pmgntframe;

+	struct pkt_attrib	*pattrib;

+	struct xmit_priv	*pxmitpriv;

+	struct mlme_ext_priv	*pmlmeext;

+	struct mlme_ext_info	*pmlmeinfo;

+	u32	BeaconLength, ProbeRspLength, PSPollLength;

+	u32	NullDataLength, QosNullLength, BTQosNullLength;

+	u8	*ReservedPagePacket;

+	u8	PageNum, PageNeed, TxDescLen;

+	u16	BufIndex;

+	u32	TotalPacketLen;

+	RSVDPAGE_LOC	RsvdPageLoc;

+

+

+	DBG_871X("%s\n", __FUNCTION__);

+

+	ReservedPagePacket = (u8*)rtw_zmalloc(1000);

+	if (ReservedPagePacket == NULL) {

+		DBG_871X("%s: alloc ReservedPagePacket fail!\n", __FUNCTION__);

+		return;

+	}

+

+	pHalData = GET_HAL_DATA(padapter);

+	pxmitpriv = &padapter->xmitpriv;

+	pmlmeext = &padapter->mlmeextpriv;

+	pmlmeinfo = &pmlmeext->mlmext_info;

+

+	TxDescLen = TXDESC_SIZE;

+	PageNum = 0;

+

+	//3 (1) beacon * 2 pages

+	BufIndex = TXDESC_OFFSET;

+	ConstructBeacon(padapter, &ReservedPagePacket[BufIndex], &BeaconLength);

+

+	// When we count the first page size, we need to reserve description size for the RSVD

+	// packet, it will be filled in front of the packet in TXPKTBUF.

+	PageNeed = (u8)PageNum_128(TxDescLen + BeaconLength);

+	// To reserved 2 pages for beacon buffer. 2010.06.24.

+	if (PageNeed == 1)

+		PageNeed += 1;

+	PageNum += PageNeed;

+	pHalData->FwRsvdPageStartOffset = PageNum;

+

+	BufIndex += PageNeed*128;

+

+	//3 (2) ps-poll *1 page

+	RsvdPageLoc.LocPsPoll = PageNum;

+	ConstructPSPoll(padapter, &ReservedPagePacket[BufIndex], &PSPollLength);

+	rtl8188e_fill_fake_txdesc(padapter, &ReservedPagePacket[BufIndex-TxDescLen], PSPollLength, _TRUE, _FALSE);

+

+	PageNeed = (u8)PageNum_128(TxDescLen + PSPollLength);

+	PageNum += PageNeed;

+

+	BufIndex += PageNeed*128;

+

+	//3 (3) null data * 1 page

+	RsvdPageLoc.LocNullData = PageNum;

+	ConstructNullFunctionData(

+		padapter,

+		&ReservedPagePacket[BufIndex],

+		&NullDataLength,

+		get_my_bssid(&pmlmeinfo->network),

+		_FALSE, 0, 0, _FALSE);

+	rtl8188e_fill_fake_txdesc(padapter, &ReservedPagePacket[BufIndex-TxDescLen], NullDataLength, _FALSE, _FALSE);

+

+	PageNeed = (u8)PageNum_128(TxDescLen + NullDataLength);

+	PageNum += PageNeed;

+

+	BufIndex += PageNeed*128;

+

+	//3 (4) probe response * 1page

+	RsvdPageLoc.LocProbeRsp = PageNum;

+	ConstructProbeRsp(

+		padapter,

+		&ReservedPagePacket[BufIndex],

+		&ProbeRspLength,

+		get_my_bssid(&pmlmeinfo->network),

+		_FALSE);

+	rtl8188e_fill_fake_txdesc(padapter, &ReservedPagePacket[BufIndex-TxDescLen], ProbeRspLength, _FALSE, _FALSE);

+

+	PageNeed = (u8)PageNum_128(TxDescLen + ProbeRspLength);

+	PageNum += PageNeed;

+

+	BufIndex += PageNeed*128;

+

+	//3 (5) Qos null data

+	RsvdPageLoc.LocQosNull = PageNum;

+	ConstructNullFunctionData(

+		padapter, 

+		&ReservedPagePacket[BufIndex],

+		&QosNullLength,

+		get_my_bssid(&pmlmeinfo->network),

+		_TRUE, 0, 0, _FALSE);

+	rtl8188e_fill_fake_txdesc(padapter, &ReservedPagePacket[BufIndex-TxDescLen], QosNullLength, _FALSE, _FALSE);

+

+	PageNeed = (u8)PageNum_128(TxDescLen + QosNullLength);

+	PageNum += PageNeed;

+

+	TotalPacketLen = BufIndex + QosNullLength;

+/*

+	BufIndex += PageNeed*128;

+

+	//3 (6) BT Qos null data

+	RsvdPageLoc.LocBTQosNull = PageNum;

+	ConstructNullFunctionData(

+		padapter, 

+		&ReservedPagePacket[BufIndex],

+		&BTQosNullLength,

+		get_my_bssid(&pmlmeinfo->network),

+		_TRUE, 0, 0, _FALSE);

+	rtl8188e_fill_fake_txdesc(padapter, &ReservedPagePacket[BufIndex-TxDescLen], BTQosNullLength, _FALSE, _TRUE);

+

+	TotalPacketLen = BufIndex + BTQosNullLength;

+*/

+

+	pmgntframe = alloc_mgtxmitframe(pxmitpriv);

+	if (pmgntframe == NULL)

+		goto exit;

+

+	// update attribute

+	pattrib = &pmgntframe->attrib;

+	update_mgntframe_attrib(padapter, pattrib);

+	pattrib->qsel = 0x10;

+	pattrib->pktlen = pattrib->last_txcmdsz = TotalPacketLen - TXDESC_OFFSET;

+	_rtw_memcpy(pmgntframe->buf_addr, ReservedPagePacket, TotalPacketLen);

+

+	rtw_hal_mgnt_xmit(padapter, pmgntframe);

+

+	DBG_871X("%s: Set RSVD page location to Fw\n", __FUNCTION__);

+	FillH2CCmd_88E(padapter, H2C_COM_RSVD_PAGE, sizeof(RsvdPageLoc), (u8*)&RsvdPageLoc);

+

+exit:

+	rtw_mfree(ReservedPagePacket, 1000);

+}

+

+void rtl8188e_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus)

+{

+	JOINBSSRPT_PARM	JoinBssRptParm;

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);

+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);

+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);

+	BOOLEAN		bSendBeacon=_FALSE;

+	BOOLEAN		bcn_valid = _FALSE;

+	u8	DLBcnCount=0;

+	u32 poll = 0;

+

+_func_enter_;

+

+	DBG_871X("%s mstatus(%x)\n", __FUNCTION__,mstatus);

+

+	if(mstatus == 1)

+	{

+		// We should set AID, correct TSF, HW seq enable before set JoinBssReport to Fw in 88/92C.

+		// Suggested by filen. Added by tynli.

+		rtw_write16(padapter, REG_BCN_PSR_RPT, (0xC000|pmlmeinfo->aid));

+		// Do not set TSF again here or vWiFi beacon DMA INT will not work.

+		//correct_TSF(padapter, pmlmeext);

+		// Hw sequende enable by dedault. 2010.06.23. by tynli.

+		//rtw_write16(padapter, REG_NQOS_SEQ, ((pmlmeext->mgnt_seq+100)&0xFFF));

+		//rtw_write8(padapter, REG_HWSEQ_CTRL, 0xFF);

+

+		//Set REG_CR bit 8. DMA beacon by SW.

+		pHalData->RegCR_1 |= BIT0;

+		rtw_write8(padapter,  REG_CR+1, pHalData->RegCR_1);

+		

+		// Disable Hw protection for a time which revserd for Hw sending beacon.

+		// Fix download reserved page packet fail that access collision with the protection time.

+		// 2010.05.11. Added by tynli.

+		//SetBcnCtrlReg(padapter, 0, BIT3);

+		//SetBcnCtrlReg(padapter, BIT4, 0);

+		rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL)&(~BIT(3)));

+		rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL)|BIT(4));

+			

+		if(pHalData->RegFwHwTxQCtrl&BIT6)

+		{

+			DBG_871X("HalDownloadRSVDPage(): There is an Adapter is sending beacon.\n");

+			bSendBeacon = _TRUE;

+		}

+

+		// Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.

+		rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, (pHalData->RegFwHwTxQCtrl&(~BIT6)));

+		pHalData->RegFwHwTxQCtrl &= (~BIT6);

+

+		// Clear beacon valid check bit.

+		rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL);

+		DLBcnCount = 0;

+		poll = 0;

+		do

+		{

+			// download rsvd page.

+			SetFwRsvdPagePkt(padapter, _FALSE);

+			DLBcnCount++;

+			do

+			{

+				rtw_yield_os();

+				//rtw_mdelay_os(10);

+				// check rsvd page download OK.

+				rtw_hal_get_hwreg(padapter, HW_VAR_BCN_VALID, (u8*)(&bcn_valid));

+				poll++;

+			} while(!bcn_valid && (poll%10)!=0 && !padapter->bSurpriseRemoved && !padapter->bDriverStopped);

+			

+		}while(!bcn_valid && DLBcnCount<=100 && !padapter->bSurpriseRemoved && !padapter->bDriverStopped);

+		

+		//RT_ASSERT(bcn_valid, ("HalDownloadRSVDPage88ES(): 1 Download RSVD page failed!\n"));

+		if(padapter->bSurpriseRemoved || padapter->bDriverStopped)

+		{

+		}

+		else if(!bcn_valid)

+			DBG_871X("%s: 1 Download RSVD page failed! DLBcnCount:%u, poll:%u\n", __FUNCTION__ ,DLBcnCount, poll);

+		else

+			DBG_871X("%s: 1 Download RSVD success! DLBcnCount:%u, poll:%u\n", __FUNCTION__, DLBcnCount, poll);

+		//

+		// We just can send the reserved page twice during the time that Tx thread is stopped (e.g. pnpsetpower)

+		// becuase we need to free the Tx BCN Desc which is used by the first reserved page packet.

+		// At run time, we cannot get the Tx Desc until it is released in TxHandleInterrupt() so we will return

+		// the beacon TCB in the following code. 2011.11.23. by tynli.

+		//

+		//if(bcn_valid && padapter->bEnterPnpSleep)

+		if(0)

+		{

+			if(bSendBeacon)

+			{

+				rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL);

+				DLBcnCount = 0;

+				poll = 0;

+				do

+				{

+					SetFwRsvdPagePkt(padapter, _TRUE);

+					DLBcnCount++;

+					

+					do

+					{

+						rtw_yield_os();

+						//rtw_mdelay_os(10);

+						// check rsvd page download OK.

+						rtw_hal_get_hwreg(padapter, HW_VAR_BCN_VALID, (u8*)(&bcn_valid));

+						poll++;

+					} while(!bcn_valid && (poll%10)!=0 && !padapter->bSurpriseRemoved && !padapter->bDriverStopped);

+				}while(!bcn_valid && DLBcnCount<=100 && !padapter->bSurpriseRemoved && !padapter->bDriverStopped);

+				

+				//RT_ASSERT(bcn_valid, ("HalDownloadRSVDPage(): 2 Download RSVD page failed!\n"));

+				if(padapter->bSurpriseRemoved || padapter->bDriverStopped)

+				{

+				}

+				else if(!bcn_valid)

+					DBG_871X("%s: 2 Download RSVD page failed! DLBcnCount:%u, poll:%u\n", __FUNCTION__ ,DLBcnCount, poll);

+				else

+					DBG_871X("%s: 2 Download RSVD success! DLBcnCount:%u, poll:%u\n", __FUNCTION__, DLBcnCount, poll);

+			}

+		}

+

+		// Enable Bcn

+		//SetBcnCtrlReg(padapter, BIT3, 0);

+		//SetBcnCtrlReg(padapter, 0, BIT4);

+		rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL)|BIT(3));

+		rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL)&(~BIT(4)));

+

+		// To make sure that if there exists an adapter which would like to send beacon.

+		// If exists, the origianl value of 0x422[6] will be 1, we should check this to

+		// prevent from setting 0x422[6] to 0 after download reserved page, or it will cause 

+		// the beacon cannot be sent by HW.

+		// 2010.06.23. Added by tynli.

+		if(bSendBeacon)

+		{

+			rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, (pHalData->RegFwHwTxQCtrl|BIT6));

+			pHalData->RegFwHwTxQCtrl |= BIT6;

+		}

+

+		//

+		// Update RSVD page location H2C to Fw.

+		//

+		if(bcn_valid)

+		{

+			rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL);

+			DBG_871X("Set RSVD page location to Fw.\n");

+			//FillH2CCmd88E(Adapter, H2C_88E_RSVDPAGE, H2C_RSVDPAGE_LOC_LENGTH, pMgntInfo->u1RsvdPageLoc);

+		}

+		

+		// Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.

+		//if(!padapter->bEnterPnpSleep)

+		{

+			// Clear CR[8] or beacon packet will not be send to TxBuf anymore.

+			pHalData->RegCR_1 &= (~BIT0);

+			rtw_write8(padapter,  REG_CR+1, pHalData->RegCR_1);

+		}

+	}

+#ifdef CONFIG_WOWLAN

+	if (padapter->pwrctrlpriv.wowlan_mode){

+		JoinBssRptParm.OpMode = mstatus;

+		JoinBssRptParm.MacID = 0;

+		FillH2CCmd_88E(padapter, H2C_COM_MEDIA_STATUS_RPT, sizeof(JoinBssRptParm), (u8 *)&JoinBssRptParm);

+		DBG_871X_LEVEL(_drv_info_, "%s opmode:%d MacId:%d\n", __func__, JoinBssRptParm.OpMode, JoinBssRptParm.MacID);

+	} else {

+		DBG_871X_LEVEL(_drv_info_, "%s wowlan_mode is off\n", __func__);

+	}

+#endif //CONFIG_WOWLAN

+_func_exit_;

+}

+

+#ifdef CONFIG_P2P_PS

+void rtl8188e_set_p2p_ps_offload_cmd(_adapter* padapter, u8 p2p_ps_state)

+{

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);

+	struct pwrctrl_priv		*pwrpriv = &padapter->pwrctrlpriv;

+	struct wifidirect_info	*pwdinfo = &( padapter->wdinfo );

+	struct P2P_PS_Offload_t	*p2p_ps_offload = &pHalData->p2p_ps_offload;

+	u8	i;

+

+_func_enter_;

+

+#if 1

+	switch(p2p_ps_state)

+	{

+		case P2P_PS_DISABLE:

+			DBG_8192C("P2P_PS_DISABLE \n");

+			_rtw_memset(p2p_ps_offload, 0 ,1);

+			break;

+		case P2P_PS_ENABLE:

+			DBG_8192C("P2P_PS_ENABLE \n");

+			// update CTWindow value.

+			if( pwdinfo->ctwindow > 0 )

+			{

+				p2p_ps_offload->CTWindow_En = 1;

+				rtw_write8(padapter, REG_P2P_CTWIN, pwdinfo->ctwindow);

+			}

+

+			// hw only support 2 set of NoA

+			for( i=0 ; i<pwdinfo->noa_num ; i++)

+			{

+				// To control the register setting for which NOA

+				rtw_write8(padapter, REG_NOA_DESC_SEL, (i << 4));

+				if(i == 0)

+					p2p_ps_offload->NoA0_En = 1;

+				else

+					p2p_ps_offload->NoA1_En = 1;

+

+				// config P2P NoA Descriptor Register

+				//DBG_8192C("%s(): noa_duration = %x\n",__FUNCTION__,pwdinfo->noa_duration[i]);

+				rtw_write32(padapter, REG_NOA_DESC_DURATION, pwdinfo->noa_duration[i]);

+

+				//DBG_8192C("%s(): noa_interval = %x\n",__FUNCTION__,pwdinfo->noa_interval[i]);

+				rtw_write32(padapter, REG_NOA_DESC_INTERVAL, pwdinfo->noa_interval[i]);

+

+				//DBG_8192C("%s(): start_time = %x\n",__FUNCTION__,pwdinfo->noa_start_time[i]);

+				rtw_write32(padapter, REG_NOA_DESC_START, pwdinfo->noa_start_time[i]);

+

+				//DBG_8192C("%s(): noa_count = %x\n",__FUNCTION__,pwdinfo->noa_count[i]);

+				rtw_write8(padapter, REG_NOA_DESC_COUNT, pwdinfo->noa_count[i]);

+			}

+

+			if( (pwdinfo->opp_ps == 1) || (pwdinfo->noa_num > 0) )

+			{

+				// rst p2p circuit

+				rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(4));

+

+				p2p_ps_offload->Offload_En = 1;

+

+				if(pwdinfo->role == P2P_ROLE_GO)

+				{

+					p2p_ps_offload->role= 1;

+					p2p_ps_offload->AllStaSleep = 0;

+				}

+				else

+				{

+					p2p_ps_offload->role= 0;

+				}

+

+				p2p_ps_offload->discovery = 0;

+			}

+			break;

+		case P2P_PS_SCAN:

+			DBG_8192C("P2P_PS_SCAN \n");

+			p2p_ps_offload->discovery = 1;

+			break;

+		case P2P_PS_SCAN_DONE:

+			DBG_8192C("P2P_PS_SCAN_DONE \n");

+			p2p_ps_offload->discovery = 0;

+			pwdinfo->p2p_ps_state = P2P_PS_ENABLE;

+			break;

+		default:

+			break;

+	}

+

+	FillH2CCmd_88E(padapter, H2C_PS_P2P_OFFLOAD, 1, (u8 *)p2p_ps_offload);

+#endif

+

+_func_exit_;

+

+}

+#endif //CONFIG_P2P_PS

+

+#ifdef CONFIG_TSF_RESET_OFFLOAD

+/*

+	ask FW to Reset sync register at Beacon early interrupt

+*/

+u8 rtl8188e_reset_tsf(_adapter *padapter, u8 reset_port )

+{	

+	u8	buf[2];

+	u8	res=_SUCCESS;

+

+	s32 ret;

+_func_enter_;

+	if (IFACE_PORT0==reset_port) {

+		buf[0] = 0x1; buf[1] = 0;

+	} else{

+		buf[0] = 0x0; buf[1] = 0x1;

+	}

+

+	ret = FillH2CCmd_88E(padapter, H2C_RESET_TSF, 2, buf);

+

+_func_exit_;

+

+	return res;

+}

+

+int reset_tsf(PADAPTER Adapter, u8 reset_port )

+{

+	u8 reset_cnt_before = 0, reset_cnt_after = 0, loop_cnt = 0;

+	u32 reg_reset_tsf_cnt = (IFACE_PORT0==reset_port) ?

+				REG_FW_RESET_TSF_CNT_0:REG_FW_RESET_TSF_CNT_1;

+	u32 reg_bcncrtl = (IFACE_PORT0==reset_port) ?

+				REG_BCN_CTRL_1:REG_BCN_CTRL;

+

+	rtw_scan_abort(Adapter->pbuddy_adapter);	/*	site survey will cause reset_tsf fail	*/

+	reset_cnt_after = reset_cnt_before = rtw_read8(Adapter,reg_reset_tsf_cnt);

+	rtl8188e_reset_tsf(Adapter, reset_port);

+

+	while ((reset_cnt_after == reset_cnt_before ) && (loop_cnt < 10)) {

+		rtw_msleep_os(100);

+		loop_cnt++;

+		reset_cnt_after = rtw_read8(Adapter, reg_reset_tsf_cnt);

+	}

+

+	return(loop_cnt >= 10) ? _FAIL : _TRUE;

+}

+

+

+#endif	// CONFIG_TSF_RESET_OFFLOAD

+

+#ifdef CONFIG_WOWLAN

+void rtl8188es_set_wowlan_cmd(_adapter* padapter, u8 enable)

+{

+	u8		res=_SUCCESS;

+	u32		test=0;

+	struct recv_priv	*precvpriv = &padapter->recvpriv;

+	SETWOWLAN_PARM		pwowlan_parm;

+	SETAOAC_GLOBAL_INFO	paoac_global_info_parm;

+	struct pwrctrl_priv	*pwrpriv=&padapter->pwrctrlpriv;

+

+_func_enter_;

+		DBG_871X_LEVEL(_drv_always_, "+%s+\n", __func__);

+

+		pwowlan_parm.mode =0;

+		pwowlan_parm.gpio_index=0;

+		pwowlan_parm.gpio_duration=0;

+		pwowlan_parm.second_mode =0;

+		pwowlan_parm.reserve=0;

+

+		if(enable){

+

+			pwowlan_parm.mode |=FW_WOWLAN_FUN_EN;

+			pwrpriv->wowlan_magic =_TRUE;

+			pwrpriv->wowlan_unicast =_TRUE;

+

+			if(pwrpriv->wowlan_pattern ==_TRUE){

+				pwowlan_parm.mode |= FW_WOWLAN_PATTERN_MATCH;

+				DBG_871X_LEVEL(_drv_info_, "%s 2.pwowlan_parm.mode=0x%x \n",__FUNCTION__,pwowlan_parm.mode );

+			}

+			if(pwrpriv->wowlan_magic ==_TRUE){

+				pwowlan_parm.mode |=FW_WOWLAN_MAGIC_PKT;

+				DBG_871X_LEVEL(_drv_info_, "%s 3.pwowlan_parm.mode=0x%x \n",__FUNCTION__,pwowlan_parm.mode );

+			}

+			if(pwrpriv->wowlan_unicast ==_TRUE){

+				pwowlan_parm.mode |=FW_WOWLAN_UNICAST;

+				DBG_871X_LEVEL(_drv_info_, "%s 4.pwowlan_parm.mode=0x%x \n",__FUNCTION__,pwowlan_parm.mode );

+			}

+

+			if(!(padapter->pwrctrlpriv.wowlan_wake_reason & FWDecisionDisconnect))

+				rtl8188e_set_FwJoinBssReport_cmd(padapter, 1);

+			else

+				DBG_871X_LEVEL(_drv_always_, "%s, disconnected, no FwJoinBssReport\n",__FUNCTION__);	

+			rtw_msleep_os(2);

+

+			//WOWLAN_GPIO_ACTIVE means GPIO high active

+			//pwowlan_parm.mode |=FW_WOWLAN_GPIO_ACTIVE;

+			pwowlan_parm.mode |=FW_WOWLAN_REKEY_WAKEUP;

+			pwowlan_parm.mode |=FW_WOWLAN_DEAUTH_WAKEUP;

+

+			//DataPinWakeUp

+#ifdef CONFIG_USB_HCI

+			pwowlan_parm.gpio_index=0x0;

+#endif //CONFIG_USB_HCI

+

+#ifdef CONFIG_SDIO_HCI

+			pwowlan_parm.gpio_index=0x80;

+#endif //CONFIG_SDIO_HCI

+

+			DBG_871X_LEVEL(_drv_info_, "%s 5.pwowlan_parm.mode=0x%x \n",__FUNCTION__,pwowlan_parm.mode);

+			DBG_871X_LEVEL(_drv_info_, "%s 6.pwowlan_parm.index=0x%x \n",__FUNCTION__,pwowlan_parm.gpio_index);

+			res = FillH2CCmd_88E(padapter, H2C_COM_WWLAN, 2, (u8 *)&pwowlan_parm);

+

+			rtw_msleep_os(2);

+

+			//disconnect decision

+			pwowlan_parm.mode =1;

+			pwowlan_parm.gpio_index=0;

+			pwowlan_parm.gpio_duration=0;

+			FillH2CCmd_88E(padapter, H2C_COM_DISCNT_DECISION, 3, (u8 *)&pwowlan_parm);

+

+			//keep alive period = 10 * 10 BCN interval

+			pwowlan_parm.mode =1;

+			pwowlan_parm.gpio_index=10;

+			res = FillH2CCmd_88E(padapter, H2C_COM_KEEP_ALIVE, 2, (u8 *)&pwowlan_parm);

+

+			rtw_msleep_os(2);

+			//Configure STA security information for GTK rekey wakeup event.

+			paoac_global_info_parm.pairwiseEncAlg=

+						padapter->securitypriv.dot11PrivacyAlgrthm;

+			paoac_global_info_parm.groupEncAlg=

+						padapter->securitypriv.dot118021XGrpPrivacy;

+			res = FillH2CCmd_88E(padapter, H2C_COM_AOAC_GLOBAL_INFO, 2, (u8 *)&paoac_global_info_parm);

+

+			rtw_msleep_os(2);

+			//enable Remote wake ctrl

+			pwowlan_parm.mode = 1;

+			pwowlan_parm.gpio_index=0;

+			pwowlan_parm.gpio_duration=0;

+			res = FillH2CCmd_88E(padapter, H2C_COM_REMOTE_WAKE_CTRL, 3, (u8 *)&pwowlan_parm);

+		} else {

+			pwrpriv->wowlan_magic =_FALSE;

+			res = FillH2CCmd_88E(padapter, H2C_COM_WWLAN, 2, (u8 *)&pwowlan_parm);

+			rtw_msleep_os(2);

+			res = FillH2CCmd_88E(padapter, H2C_COM_REMOTE_WAKE_CTRL, 3, (u8 *)&pwowlan_parm);

+		}

+_func_exit_;

+		DBG_871X_LEVEL(_drv_always_, "-%s res:%d-\n", __func__, res);

+		return ;

+}

+#endif  //CONFIG_WOWLAN
\ No newline at end of file
diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/rtl8188e_dm.c b/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/rtl8188e_dm.c
new file mode 100755
index 00000000..4494acb4
--- /dev/null
+++ b/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/rtl8188e_dm.c
@@ -0,0 +1,637 @@
+/******************************************************************************

+ *

+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.

+ *

+ * This program is free software; you can redistribute it and/or modify it

+ * under the terms of version 2 of the GNU General Public License as

+ * published by the Free Software Foundation.

+ *

+ * This program is distributed in the hope that it will be useful, but WITHOUT

+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for

+ * more details.

+ *

+ * You should have received a copy of the GNU General Public License along with

+ * this program; if not, write to the Free Software Foundation, Inc.,

+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA

+ *

+ *

+ ******************************************************************************/

+//============================================================

+// Description:

+//

+// This file is for 92CE/92CU dynamic mechanism only

+//

+//

+//============================================================

+#define _RTL8188E_DM_C_

+

+//============================================================

+// include files

+//============================================================

+#include <drv_conf.h>

+#include <osdep_service.h>

+#include <drv_types.h>

+#include <rtw_byteorder.h>

+

+#include <rtl8188e_hal.h>

+

+//============================================================

+// Global var

+//============================================================

+

+

+static VOID

+dm_CheckProtection(

+	IN	PADAPTER	Adapter

+	)

+{

+#if 0

+	PMGNT_INFO		pMgntInfo = &(Adapter->MgntInfo);

+	u1Byte			CurRate, RateThreshold;

+

+	if(pMgntInfo->pHTInfo->bCurBW40MHz)

+		RateThreshold = MGN_MCS1;

+	else

+		RateThreshold = MGN_MCS3;

+

+	if(Adapter->TxStats.CurrentInitTxRate <= RateThreshold)

+	{

+		pMgntInfo->bDmDisableProtect = TRUE;

+		DbgPrint("Forced disable protect: %x\n", Adapter->TxStats.CurrentInitTxRate);

+	}

+	else

+	{

+		pMgntInfo->bDmDisableProtect = FALSE;

+		DbgPrint("Enable protect: %x\n", Adapter->TxStats.CurrentInitTxRate);

+	}

+#endif

+}

+

+static VOID

+dm_CheckStatistics(

+	IN	PADAPTER	Adapter

+	)

+{

+#if 0

+	if(!Adapter->MgntInfo.bMediaConnect)

+		return;

+

+	//2008.12.10 tynli Add for getting Current_Tx_Rate_Reg flexibly.

+	rtw_hal_get_hwreg( Adapter, HW_VAR_INIT_TX_RATE, (pu1Byte)(&Adapter->TxStats.CurrentInitTxRate) );

+

+	// Calculate current Tx Rate(Successful transmited!!)

+

+	// Calculate current Rx Rate(Successful received!!)

+

+	//for tx tx retry count

+	rtw_hal_get_hwreg( Adapter, HW_VAR_RETRY_COUNT, (pu1Byte)(&Adapter->TxStats.NumTxRetryCount) );

+#endif

+}

+

+static void dm_CheckPbcGPIO(_adapter *padapter)

+{

+	u8	tmp1byte;

+	u8	bPbcPressed = _FALSE;

+

+	if(!padapter->registrypriv.hw_wps_pbc)

+		return;

+

+#ifdef CONFIG_USB_HCI

+	tmp1byte = rtw_read8(padapter, GPIO_IO_SEL);

+	tmp1byte |= (HAL_8192C_HW_GPIO_WPS_BIT);

+	rtw_write8(padapter, GPIO_IO_SEL, tmp1byte);	//enable GPIO[2] as output mode

+

+	tmp1byte &= ~(HAL_8192C_HW_GPIO_WPS_BIT);

+	rtw_write8(padapter,  GPIO_IN, tmp1byte);		//reset the floating voltage level

+

+	tmp1byte = rtw_read8(padapter, GPIO_IO_SEL);

+	tmp1byte &= ~(HAL_8192C_HW_GPIO_WPS_BIT);

+	rtw_write8(padapter, GPIO_IO_SEL, tmp1byte);	//enable GPIO[2] as input mode

+

+	tmp1byte =rtw_read8(padapter, GPIO_IN);

+

+	if (tmp1byte == 0xff)

+		return ;

+

+	if (tmp1byte&HAL_8192C_HW_GPIO_WPS_BIT)

+	{

+		bPbcPressed = _TRUE;

+	}

+#else

+	tmp1byte = rtw_read8(padapter, GPIO_IN);

+	//RT_TRACE(COMP_IO, DBG_TRACE, ("dm_CheckPbcGPIO - %x\n", tmp1byte));

+

+	if (tmp1byte == 0xff || padapter->init_adpt_in_progress)

+		return ;

+

+	if((tmp1byte&HAL_8192C_HW_GPIO_WPS_BIT)==0)

+	{

+		bPbcPressed = _TRUE;

+	}

+#endif

+

+	if( _TRUE == bPbcPressed)

+	{

+		// Here we only set bPbcPressed to true

+		// After trigger PBC, the variable will be set to false

+		DBG_8192C("CheckPbcGPIO - PBC is pressed\n");

+

+#ifdef RTK_DMP_PLATFORM

+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,12))

+		kobject_uevent(&padapter->pnetdev->dev.kobj, KOBJ_NET_PBC);

+#else

+		kobject_hotplug(&padapter->pnetdev->class_dev.kobj, KOBJ_NET_PBC);

+#endif

+#else

+

+		if ( padapter->pid[0] == 0 )

+		{	//	0 is the default value and it means the application monitors the HW PBC doesn't privde its pid to driver.

+			return;

+		}

+

+#ifdef PLATFORM_LINUX

+		rtw_signal_process(padapter->pid[0], SIGUSR1);

+#endif

+#endif

+	}

+}

+

+#ifdef CONFIG_PCI_HCI

+//

+//	Description:

+//		Perform interrupt migration dynamically to reduce CPU utilization.

+//

+//	Assumption:

+//		1. Do not enable migration under WIFI test.

+//

+//	Created by Roger, 2010.03.05.

+//

+VOID

+dm_InterruptMigration(

+	IN	PADAPTER	Adapter

+	)

+{

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);

+	struct mlme_priv	*pmlmepriv = &(Adapter->mlmepriv);

+	BOOLEAN			bCurrentIntMt, bCurrentACIntDisable;

+	BOOLEAN			IntMtToSet = _FALSE;

+	BOOLEAN			ACIntToSet = _FALSE;

+

+

+	// Retrieve current interrupt migration and Tx four ACs IMR settings first.

+	bCurrentIntMt = pHalData->bInterruptMigration;

+	bCurrentACIntDisable = pHalData->bDisableTxInt;

+

+	//

+	// <Roger_Notes> Currently we use busy traffic for reference instead of RxIntOK counts to prevent non-linear Rx statistics

+	// when interrupt migration is set before. 2010.03.05.

+	//

+	if(!Adapter->registrypriv.wifi_spec &&

+		(check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) &&

+		pmlmepriv->LinkDetectInfo.bHigherBusyTraffic)

+	{

+		IntMtToSet = _TRUE;

+

+		// To check whether we should disable Tx interrupt or not.

+		if(pmlmepriv->LinkDetectInfo.bHigherBusyRxTraffic )

+			ACIntToSet = _TRUE;

+	}

+

+	//Update current settings.

+	if( bCurrentIntMt != IntMtToSet ){

+		DBG_8192C("%s(): Update interrrupt migration(%d)\n",__FUNCTION__,IntMtToSet);

+		if(IntMtToSet)

+		{

+			//

+			// <Roger_Notes> Set interrrupt migration timer and corresponging Tx/Rx counter.

+			// timer 25ns*0xfa0=100us for 0xf packets.

+			// 2010.03.05.

+			//

+			rtw_write32(Adapter, REG_INT_MIG, 0xff000fa0);// 0x306:Rx, 0x307:Tx

+			pHalData->bInterruptMigration = IntMtToSet;

+		}

+		else

+		{

+			// Reset all interrupt migration settings.

+			rtw_write32(Adapter, REG_INT_MIG, 0);

+			pHalData->bInterruptMigration = IntMtToSet;

+		}

+	}

+

+	/*if( bCurrentACIntDisable != ACIntToSet ){

+		DBG_8192C("%s(): Update AC interrrupt(%d)\n",__FUNCTION__,ACIntToSet);

+		if(ACIntToSet) // Disable four ACs interrupts.

+		{

+			//

+			// <Roger_Notes> Disable VO, VI, BE and BK four AC interrupts to gain more efficient CPU utilization.

+			// When extremely highly Rx OK occurs, we will disable Tx interrupts.

+			// 2010.03.05.

+			//

+			UpdateInterruptMask8192CE( Adapter, 0, RT_AC_INT_MASKS );

+			pHalData->bDisableTxInt = ACIntToSet;

+		}

+		else// Enable four ACs interrupts.

+		{

+			UpdateInterruptMask8192CE( Adapter, RT_AC_INT_MASKS, 0 );

+			pHalData->bDisableTxInt = ACIntToSet;

+		}

+	}*/

+

+}

+

+#endif

+

+//

+// Initialize GPIO setting registers

+//

+static void

+dm_InitGPIOSetting(

+	IN	PADAPTER	Adapter

+	)

+{

+	PHAL_DATA_TYPE		pHalData = GET_HAL_DATA(Adapter);

+

+	u8	tmp1byte;

+

+	tmp1byte = rtw_read8(Adapter, REG_GPIO_MUXCFG);

+	tmp1byte &= (GPIOSEL_GPIO | ~GPIOSEL_ENBT);

+

+#ifdef CONFIG_BT_COEXIST

+	// UMB-B cut bug. We need to support the modification.

+	if (IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID) &&

+		pHalData->bt_coexist.BT_Coexist)

+	{

+		tmp1byte |= (BIT5);

+	}

+#endif

+	rtw_write8(Adapter, REG_GPIO_MUXCFG, tmp1byte);

+

+}

+

+//============================================================

+// functions

+//============================================================

+static void Init_ODM_ComInfo_88E(PADAPTER	Adapter)

+{

+

+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);

+	struct dm_priv	*pdmpriv = &pHalData->dmpriv;

+	PDM_ODM_T		pDM_Odm = &(pHalData->odmpriv);

+	u8	cut_ver,fab_ver;

+	

+	//

+	// Init Value

+	//

+	_rtw_memset(pDM_Odm,0,sizeof(pDM_Odm));

+	

+	pDM_Odm->Adapter = Adapter;	

+	

+	ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_PLATFORM,ODM_CE);

+

+	if(Adapter->interface_type == RTW_GSPI )

+		ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_INTERFACE,ODM_ITRF_SDIO);

+	else

+		ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_INTERFACE,Adapter->interface_type);//RTL871X_HCI_TYPE

+	

+	ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_IC_TYPE,ODM_RTL8188E);

+

+	fab_ver = ODM_TSMC;

+	cut_ver = ODM_CUT_A;	

+

+	ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_FAB_VER,fab_ver);		

+	ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_CUT_VER,cut_ver);

+

+	ODM_CmnInfoInit(pDM_Odm,	ODM_CMNINFO_MP_TEST_CHIP,IS_NORMAL_CHIP(pHalData->VersionID));

+	

+#if 0	

+//#ifdef CONFIG_USB_HCI	

+	ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_BOARD_TYPE,pHalData->BoardType);

+

+	if(pHalData->BoardType == BOARD_USB_High_PA){

+		ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_EXT_LNA,_TRUE);

+		ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_EXT_PA,_TRUE);

+	}

+#endif	

+	ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_PATCH_ID,pHalData->CustomerID);

+	//	ODM_CMNINFO_BINHCT_TEST only for MP Team

+	ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_BWIFI_TEST,Adapter->registrypriv.wifi_spec);

+		

+	

+	if(pHalData->rf_type == RF_1T1R){

+		ODM_CmnInfoUpdate(pDM_Odm,ODM_CMNINFO_RF_TYPE,ODM_1T1R);		

+	}

+	else if(pHalData->rf_type == RF_2T2R){

+		ODM_CmnInfoUpdate(pDM_Odm,ODM_CMNINFO_RF_TYPE,ODM_2T2R);		

+	}

+	else if(pHalData->rf_type == RF_1T2R){		

+		ODM_CmnInfoUpdate(pDM_Odm,ODM_CMNINFO_RF_TYPE,ODM_1T2R);		

+	}	

+

+ 	ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RF_ANTENNA_TYPE, pHalData->TRxAntDivType);

+	

+	#ifdef CONFIG_DISABLE_ODM

+	pdmpriv->InitODMFlag = 0;

+	#else

+	pdmpriv->InitODMFlag =	ODM_RF_CALIBRATION		|

+							ODM_RF_TX_PWR_TRACK	//|

+							;	

+	//if(pHalData->AntDivCfg)

+	//	pdmpriv->InitODMFlag |= ODM_BB_ANT_DIV;

+	#endif	

+

+	ODM_CmnInfoUpdate(pDM_Odm,ODM_CMNINFO_ABILITY,pdmpriv->InitODMFlag);

+	

+}

+static void Update_ODM_ComInfo_88E(PADAPTER	Adapter)

+{

+	struct mlme_ext_priv	*pmlmeext = &Adapter->mlmeextpriv;

+	struct mlme_priv	*pmlmepriv = &Adapter->mlmepriv;

+	struct pwrctrl_priv *pwrctrlpriv = &Adapter->pwrctrlpriv;

+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);

+	PDM_ODM_T		pDM_Odm = &(pHalData->odmpriv);

+	struct dm_priv	*pdmpriv = &pHalData->dmpriv;	

+	int i;	

+	#ifdef CONFIG_DISABLE_ODM

+	pdmpriv->InitODMFlag = 0;

+	#else //CONFIG_DISABLE_ODM

+	

+	pdmpriv->InitODMFlag =	ODM_BB_DIG				|

+#ifdef	CONFIG_ODM_REFRESH_RAMASK

+							ODM_BB_RA_MASK		|

+#endif							

+							ODM_BB_DYNAMIC_TXPWR	|

+							ODM_BB_FA_CNT			|

+							ODM_BB_RSSI_MONITOR	|

+							ODM_BB_CCK_PD			|							

+							ODM_BB_PWR_SAVE		|							

+							ODM_MAC_EDCA_TURBO	|

+							ODM_RF_CALIBRATION		|

+							ODM_RF_TX_PWR_TRACK	

+							;	

+	if(pHalData->AntDivCfg)

+		pdmpriv->InitODMFlag |= ODM_BB_ANT_DIV;

+

+	#if (MP_DRIVER==1)

+		if (Adapter->registrypriv.mp_mode == 1)

+		{

+		pdmpriv->InitODMFlag = 	ODM_RF_CALIBRATION	|

+								ODM_RF_TX_PWR_TRACK;	

+		}

+	#endif//(MP_DRIVER==1)

+	

+	#endif//CONFIG_DISABLE_ODM	

+	ODM_CmnInfoUpdate(pDM_Odm,ODM_CMNINFO_ABILITY,pdmpriv->InitODMFlag);

+	

+	ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_TX_UNI,&(Adapter->xmitpriv.tx_bytes));

+	ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_RX_UNI,&(Adapter->recvpriv.rx_bytes));

+	ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_WM_MODE,&(pmlmeext->cur_wireless_mode));

+	ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_SEC_CHNL_OFFSET,&(pHalData->nCur40MhzPrimeSC));

+	ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_SEC_MODE,&(Adapter->securitypriv.dot11PrivacyAlgrthm));

+	ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BW,&(pHalData->CurrentChannelBW ));

+	ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_CHNL,&( pHalData->CurrentChannel));	

+	ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_NET_CLOSED,&( Adapter->net_closed));

+	ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_MP_MODE,&(Adapter->registrypriv.mp_mode));

+	//================= only for 8192D   =================

+	/*

+	//pHalData->CurrentBandType92D

+	ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BAND,&(pDM_Odm->u1Byte_temp));

+	ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_DMSP_GET_VALUE,&(pDM_Odm->u1Byte_temp));

+	ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BUDDY_ADAPTOR,&(pDM_Odm->PADAPTER_temp));

+	ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_DMSP_IS_MASTER,&(pDM_Odm->u1Byte_temp));

+	//================= only for 8192D   =================

+	// driver havn't those variable now

+	ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BT_OPERATION,&(pDM_Odm->u1Byte_temp));

+	ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BT_DISABLE_EDCA,&(pDM_Odm->u1Byte_temp));

+	*/

+	

+	ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_SCAN,&(pmlmepriv->bScanInProcess));

+	ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_POWER_SAVING,&(pwrctrlpriv->bpower_saving));

+	ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RF_ANTENNA_TYPE, pHalData->TRxAntDivType);

+

+	for(i=0; i< NUM_STA; i++)

+	{

+		//pDM_Odm->pODM_StaInfo[i] = NULL;

+		ODM_CmnInfoPtrArrayHook(pDM_Odm, ODM_CMNINFO_STA_STATUS,i,NULL);

+	}	

+}

+

+void

+rtl8188e_InitHalDm(

+	IN	PADAPTER	Adapter

+	)

+{

+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);

+	struct dm_priv	*pdmpriv = &pHalData->dmpriv;

+	PDM_ODM_T		pDM_Odm = &(pHalData->odmpriv);

+	u8	i;

+

+#ifdef CONFIG_USB_HCI

+	dm_InitGPIOSetting(Adapter);

+#endif

+

+	pdmpriv->DM_Type = DM_Type_ByDriver;

+	pdmpriv->DMFlag = DYNAMIC_FUNC_DISABLE;

+	

+	Update_ODM_ComInfo_88E(Adapter);

+	ODM_DMInit(pDM_Odm);

+

+	Adapter->fix_rate = 0xFF;

+

+}

+

+

+VOID

+rtl8188e_HalDmWatchDog(

+	IN	PADAPTER	Adapter

+	)

+{

+	BOOLEAN		bFwCurrentInPSMode = _FALSE;

+	BOOLEAN		bFwPSAwake = _TRUE;

+	u8 hw_init_completed = _FALSE;

+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);

+	struct dm_priv	*pdmpriv = &pHalData->dmpriv;

+	PDM_ODM_T		pDM_Odm = &(pHalData->odmpriv);

+#ifdef CONFIG_CONCURRENT_MODE

+	PADAPTER pbuddy_adapter = Adapter->pbuddy_adapter;

+#endif //CONFIG_CONCURRENT_MODE

+

+	_func_enter_;

+

+	hw_init_completed = Adapter->hw_init_completed;

+

+	if (hw_init_completed == _FALSE)

+		goto skip_dm;

+

+#ifdef CONFIG_LPS

+	#ifdef CONFIG_CONCURRENT_MODE

+	if (Adapter->iface_type != IFACE_PORT0 && pbuddy_adapter) {

+		bFwCurrentInPSMode = pbuddy_adapter->pwrctrlpriv.bFwCurrentInPSMode;

+		rtw_hal_get_hwreg(pbuddy_adapter, HW_VAR_FWLPS_RF_ON, (u8 *)(&bFwPSAwake));

+	} else

+	#endif //CONFIG_CONCURRENT_MODE

+	{

+		bFwCurrentInPSMode = Adapter->pwrctrlpriv.bFwCurrentInPSMode;

+		rtw_hal_get_hwreg(Adapter, HW_VAR_FWLPS_RF_ON, (u8 *)(&bFwPSAwake));

+	}

+#endif

+

+#ifdef CONFIG_P2P_PS

+	// Fw is under p2p powersaving mode, driver should stop dynamic mechanism.

+	// modifed by thomas. 2011.06.11.

+	if(Adapter->wdinfo.p2p_ps_mode)

+		bFwPSAwake = _FALSE;

+#endif //CONFIG_P2P_PS

+

+	if( (hw_init_completed == _TRUE)

+		&& ((!bFwCurrentInPSMode) && bFwPSAwake))

+	{

+		//

+		// Calculate Tx/Rx statistics.

+		//

+		dm_CheckStatistics(Adapter);

+	

+		//

+		// Dynamically switch RTS/CTS protection.

+		//

+		//dm_CheckProtection(Adapter);

+

+#ifdef CONFIG_PCI_HCI

+		// 20100630 Joseph: Disable Interrupt Migration mechanism temporarily because it degrades Rx throughput.

+		// Tx Migration settings.

+		//dm_InterruptMigration(Adapter);

+

+		//if(Adapter->HalFunc.TxCheckStuckHandler(Adapter))

+		//	PlatformScheduleWorkItem(&(GET_HAL_DATA(Adapter)->HalResetWorkItem));

+#endif

+	

+	}

+

+

+	//ODM

+	if (hw_init_completed == _TRUE)

+	{

+		u8	bLinked=_FALSE;

+

+		#ifdef CONFIG_DISABLE_ODM

+		pHalData->odmpriv.SupportAbility = 0;

+		#endif

+			

+		if(rtw_linked_check(Adapter))

+			bLinked = _TRUE;

+		

+#ifdef CONFIG_CONCURRENT_MODE

+		if(pbuddy_adapter && rtw_linked_check(pbuddy_adapter))

+			bLinked = _TRUE;

+#endif //CONFIG_CONCURRENT_MODE

+

+		ODM_CmnInfoUpdate(&pHalData->odmpriv ,ODM_CMNINFO_LINK, bLinked);

+		ODM_DMWatchdog(&pHalData->odmpriv);

+			

+	}

+

+skip_dm:

+

+	// Check GPIO to determine current RF on/off and Pbc status.

+	// Check Hardware Radio ON/OFF or not

+#ifdef CONFIG_PCI_HCI

+	if(pHalData->bGpioHwWpsPbc)

+#endif

+	{

+		//temp removed

+		//dm_CheckPbcGPIO(Adapter);				

+	}

+	return;

+}

+

+void rtl8188e_init_dm_priv(IN PADAPTER Adapter)

+{

+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);

+	struct dm_priv	*pdmpriv = &pHalData->dmpriv;

+	PDM_ODM_T 		podmpriv = &pHalData->odmpriv;

+	_rtw_memset(pdmpriv, 0, sizeof(struct dm_priv));

+	//_rtw_spinlock_init(&(pHalData->odm_stainfo_lock));

+	Init_ODM_ComInfo_88E(Adapter);

+#ifdef CONFIG_SW_ANTENNA_DIVERSITY

+	//_init_timer(&(pdmpriv->SwAntennaSwitchTimer),  Adapter->pnetdev , odm_SW_AntennaSwitchCallback, Adapter);	

+	ODM_InitAllTimers(podmpriv );	

+#endif

+	ODM_InitDebugSetting(podmpriv);	

+}

+

+void rtl8188e_deinit_dm_priv(IN PADAPTER Adapter)

+{

+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);

+	struct dm_priv	*pdmpriv = &pHalData->dmpriv;

+	PDM_ODM_T 		podmpriv = &pHalData->odmpriv;

+	//_rtw_spinlock_free(&pHalData->odm_stainfo_lock);

+#ifdef CONFIG_SW_ANTENNA_DIVERSITY

+	//_cancel_timer_ex(&pdmpriv->SwAntennaSwitchTimer);	

+	ODM_CancelAllTimers(podmpriv);	

+#endif

+}

+

+

+#ifdef CONFIG_ANTENNA_DIVERSITY

+// Add new function to reset the state of antenna diversity before link.

+//

+// Compare RSSI for deciding antenna

+void	AntDivCompare8188E(PADAPTER Adapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src)

+{

+	//PADAPTER Adapter = pDM_Odm->Adapter ;

+	

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);

+	if(0 != pHalData->AntDivCfg )

+	{

+		//DBG_8192C("update_network=> orgRSSI(%d)(%d),newRSSI(%d)(%d)\n",dst->Rssi,query_rx_pwr_percentage(dst->Rssi),

+		//	src->Rssi,query_rx_pwr_percentage(src->Rssi));

+		//select optimum_antenna for before linked =>For antenna diversity

+		if(dst->Rssi >=  src->Rssi )//keep org parameter

+		{

+			src->Rssi = dst->Rssi;

+			src->PhyInfo.Optimum_antenna = dst->PhyInfo.Optimum_antenna;						

+		}

+	}

+}

+

+// Add new function to reset the state of antenna diversity before link.

+u8 AntDivBeforeLink8188E(PADAPTER Adapter )

+{

+	

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);	

+	PDM_ODM_T 	pDM_Odm =&pHalData->odmpriv;

+	SWAT_T		*pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;

+	struct mlme_priv	*pmlmepriv = &(Adapter->mlmepriv);

+	

+	// Condition that does not need to use antenna diversity.

+	if(pHalData->AntDivCfg==0)

+	{

+		//DBG_8192C("odm_AntDivBeforeLink8192C(): No AntDiv Mechanism.\n");

+		return _FALSE;

+	}

+

+	if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)	

+	{		

+		return _FALSE;

+	}

+

+

+	if(pDM_SWAT_Table->SWAS_NoLink_State == 0){

+		//switch channel

+		pDM_SWAT_Table->SWAS_NoLink_State = 1;

+		pDM_SWAT_Table->CurAntenna = (pDM_SWAT_Table->CurAntenna==Antenna_A)?Antenna_B:Antenna_A;

+

+		//PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, pDM_SWAT_Table->CurAntenna);

+		rtw_antenna_select_cmd(Adapter, pDM_SWAT_Table->CurAntenna, _FALSE);

+		//DBG_8192C("%s change antenna to ANT_( %s ).....\n",__FUNCTION__, (pDM_SWAT_Table->CurAntenna==Antenna_A)?"A":"B");

+		return _TRUE;

+	}

+	else

+	{

+		pDM_SWAT_Table->SWAS_NoLink_State = 0;

+		return _FALSE;

+	}	

+

+}

+#endif

+

diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/rtl8188e_hal_init.c b/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/rtl8188e_hal_init.c
new file mode 100755
index 00000000..d276cd1f
--- /dev/null
+++ b/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/rtl8188e_hal_init.c
@@ -0,0 +1,3833 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#define _HAL_INIT_C_
+
+#include <drv_types.h>
+#include <rtw_byteorder.h>
+#include <rtw_efuse.h>
+
+#include <rtl8188e_hal.h>
+
+#include <rtw_iol.h>
+
+#if defined(CONFIG_IOL)
+#ifdef CONFIG_USB_HCI
+#include <usb_ops.h>
+#endif
+static void iol_mode_enable(PADAPTER padapter, u8 enable)
+{
+	u8 reg_0xf0 = 0;
+	
+	if(enable)
+	{
+		//Enable initial offload
+		reg_0xf0 = rtw_read8(padapter, REG_SYS_CFG);
+		//DBG_871X("%s reg_0xf0:0x%02x, write 0x%02x\n", __FUNCTION__, reg_0xf0, reg_0xf0|SW_OFFLOAD_EN);
+		rtw_write8(padapter, REG_SYS_CFG, reg_0xf0|SW_OFFLOAD_EN);
+		
+		if(padapter->bFWReady == _FALSE)
+		{
+			printk("bFWReady == _FALSE call reset 8051...\n");
+			_8051Reset88E(padapter);
+		}		
+			
+	}
+	else
+	{
+		//disable initial offload
+		reg_0xf0 = rtw_read8(padapter, REG_SYS_CFG);
+		//DBG_871X("%s reg_0xf0:0x%02x, write 0x%02x\n", __FUNCTION__, reg_0xf0, reg_0xf0& ~SW_OFFLOAD_EN);
+		rtw_write8(padapter, REG_SYS_CFG, reg_0xf0 & ~SW_OFFLOAD_EN);
+	}
+}
+
+static s32 iol_execute(PADAPTER padapter, u8 control)
+{
+	s32 status = _FAIL;
+	u8 reg_0x88 = 0,reg_1c7=0;
+	u32 start = 0, passing_time = 0;
+	
+	u32 t1,t2;
+	control = control&0x0f;
+	reg_0x88 = rtw_read8(padapter, REG_HMEBOX_E0);
+	//DBG_871X("%s reg_0x88:0x%02x, write 0x%02x\n", __FUNCTION__, reg_0x88, reg_0x88|control);
+	rtw_write8(padapter, REG_HMEBOX_E0,  reg_0x88|control);
+
+	t1 = start = rtw_get_current_time();
+	while(
+		//(reg_1c7 = rtw_read8(padapter, 0x1c7) >1) &&
+		(reg_0x88=rtw_read8(padapter, REG_HMEBOX_E0)) & control
+		&& (passing_time=rtw_get_passing_time_ms(start))<1000
+	) {
+		//DBG_871X("%s polling reg_0x88:0x%02x,reg_0x1c7:0x%02x\n", __FUNCTION__, reg_0x88,rtw_read8(padapter, 0x1c7) );
+		//rtw_udelay_os(100);
+	}
+
+	reg_0x88 = rtw_read8(padapter, REG_HMEBOX_E0);
+	status = (reg_0x88 & control)?_FAIL:_SUCCESS;
+	if(reg_0x88 & control<<4)
+		status = _FAIL;
+	t2= rtw_get_current_time();
+	//printk("==> step iol_execute :  %5u reg-0x1c0= 0x%02x\n",rtw_get_time_interval_ms(t1,t2),rtw_read8(padapter, 0x1c0));
+	//DBG_871X("%s in %u ms, reg_0x88:0x%02x\n", __FUNCTION__, passing_time, reg_0x88);
+	
+	return status;
+}
+
+static s32 iol_InitLLTTable(
+	PADAPTER padapter,
+	u8 txpktbuf_bndy
+	)
+{
+	s32 rst = _SUCCESS; 
+	iol_mode_enable(padapter, 1);
+	//DBG_871X("%s txpktbuf_bndy:%u\n", __FUNCTION__, txpktbuf_bndy);
+	rtw_write8(padapter, REG_TDECTRL+1, txpktbuf_bndy);
+	rst = iol_execute(padapter, CMD_INIT_LLT);
+	iol_mode_enable(padapter, 0);
+	return rst;
+}
+
+static VOID
+efuse_phymap_to_logical(u8 * phymap, u16 _offset, u16 _size_byte, u8  *pbuf)
+{
+	u8	*efuseTbl = NULL;
+	u8	rtemp8;
+	u16	eFuse_Addr = 0;
+	u8	offset, wren;
+	u16	i, j;
+	u16	**eFuseWord = NULL;
+	u16	efuse_utilized = 0;
+	u8	efuse_usage = 0;
+	u8	u1temp = 0;
+
+
+	efuseTbl = (u8*)rtw_zmalloc(EFUSE_MAP_LEN_88E);
+	if(efuseTbl == NULL)
+	{
+		DBG_871X("%s: alloc efuseTbl fail!\n", __FUNCTION__);
+		goto exit;
+	}
+
+	eFuseWord= (u16 **)rtw_malloc2d(EFUSE_MAX_SECTION_88E, EFUSE_MAX_WORD_UNIT, sizeof(u16));
+	if(eFuseWord == NULL)
+	{
+		DBG_871X("%s: alloc eFuseWord fail!\n", __FUNCTION__);
+		goto exit;
+	}
+
+	// 0. Refresh efuse init map as all oxFF.
+	for (i = 0; i < EFUSE_MAX_SECTION_88E; i++)
+		for (j = 0; j < EFUSE_MAX_WORD_UNIT; j++)
+			eFuseWord[i][j] = 0xFFFF;
+
+	//
+	// 1. Read the first byte to check if efuse is empty!!!
+	// 
+	//
+	rtemp8 = *(phymap+eFuse_Addr);
+	if(rtemp8 != 0xFF)
+	{
+		efuse_utilized++;
+		//printk("efuse_Addr-%d efuse_data=%x\n", eFuse_Addr, *rtemp8);
+		eFuse_Addr++;
+	}
+	else
+	{
+		DBG_871X("EFUSE is empty efuse_Addr-%d efuse_data=%x\n", eFuse_Addr, rtemp8);
+		goto exit;
+	}
+
+
+	//
+	// 2. Read real efuse content. Filter PG header and every section data.
+	//
+	while((rtemp8 != 0xFF) && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN_88E))
+	{
+		//RTPRINT(FEEPROM, EFUSE_READ_ALL, ("efuse_Addr-%d efuse_data=%x\n", eFuse_Addr-1, *rtemp8));
+	
+		// Check PG header for section num.
+		if((rtemp8 & 0x1F ) == 0x0F)		//extended header
+		{			
+			u1temp =( (rtemp8 & 0xE0) >> 5);
+			//RTPRINT(FEEPROM, EFUSE_READ_ALL, ("extended header u1temp=%x *rtemp&0xE0 0x%x\n", u1temp, *rtemp8 & 0xE0));
+
+			//RTPRINT(FEEPROM, EFUSE_READ_ALL, ("extended header u1temp=%x \n", u1temp));
+
+			rtemp8 = *(phymap+eFuse_Addr);
+
+			//RTPRINT(FEEPROM, EFUSE_READ_ALL, ("extended header efuse_Addr-%d efuse_data=%x\n", eFuse_Addr, *rtemp8));	
+			
+			if((rtemp8 & 0x0F) == 0x0F)
+			{
+				eFuse_Addr++;			
+				rtemp8 = *(phymap+eFuse_Addr);
+				
+				if(rtemp8 != 0xFF && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN_88E))
+				{
+					eFuse_Addr++;				
+				}				
+				continue;
+			}
+			else
+			{
+				offset = ((rtemp8 & 0xF0) >> 1) | u1temp;
+				wren = (rtemp8 & 0x0F);
+				eFuse_Addr++;				
+			}
+		}
+		else
+		{
+			offset = ((rtemp8 >> 4) & 0x0f);
+			wren = (rtemp8 & 0x0f);			
+		}
+		
+		if(offset < EFUSE_MAX_SECTION_88E)
+		{
+			// Get word enable value from PG header
+			//RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Offset-%d Worden=%x\n", offset, wren));
+
+			for(i=0; i<EFUSE_MAX_WORD_UNIT; i++)
+			{
+				// Check word enable condition in the section				
+				if(!(wren & 0x01))
+				{
+					//RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Addr=%d \n", eFuse_Addr));
+					rtemp8 = *(phymap+eFuse_Addr);
+					eFuse_Addr++;
+					//RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Data=0x%x\n", *rtemp8)); 				
+					efuse_utilized++;
+					eFuseWord[offset][i] = (rtemp8 & 0xff);
+					
+
+					if(eFuse_Addr >= EFUSE_REAL_CONTENT_LEN_88E) 
+						break;
+
+					//RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Addr=%d", eFuse_Addr));
+					rtemp8 = *(phymap+eFuse_Addr);
+					eFuse_Addr++;
+					//RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Data=0x%x\n", *rtemp8)); 				
+					
+					efuse_utilized++;
+					eFuseWord[offset][i] |= (((u2Byte)rtemp8 << 8) & 0xff00);
+
+					if(eFuse_Addr >= EFUSE_REAL_CONTENT_LEN_88E) 
+						break;
+				}
+				
+				wren >>= 1;
+				
+			}
+		}
+
+		// Read next PG header
+		rtemp8 = *(phymap+eFuse_Addr);
+		//RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Addr=%d rtemp 0x%x\n", eFuse_Addr, *rtemp8));
+		
+		if(rtemp8 != 0xFF && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN_88E))
+		{
+			efuse_utilized++;
+			eFuse_Addr++;
+		}
+	}
+
+	//
+	// 3. Collect 16 sections and 4 word unit into Efuse map.
+	//
+	for(i=0; i<EFUSE_MAX_SECTION_88E; i++)
+	{
+		for(j=0; j<EFUSE_MAX_WORD_UNIT; j++)
+		{
+			efuseTbl[(i*8)+(j*2)]=(eFuseWord[i][j] & 0xff);
+			efuseTbl[(i*8)+((j*2)+1)]=((eFuseWord[i][j] >> 8) & 0xff);
+		}
+	}
+
+
+	//
+	// 4. Copy from Efuse map to output pointer memory!!!
+	//
+	for(i=0; i<_size_byte; i++)
+	{		
+		pbuf[i] = efuseTbl[_offset+i];
+	}
+
+	//
+	// 5. Calculate Efuse utilization.
+	//
+	efuse_usage = (u1Byte)((efuse_utilized*100)/EFUSE_REAL_CONTENT_LEN_88E);
+	//Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_utilized);
+
+exit:
+	if(efuseTbl)
+		rtw_mfree(efuseTbl, EFUSE_MAP_LEN_88E);
+
+	if(eFuseWord)
+		rtw_mfree2d((void *)eFuseWord, EFUSE_MAX_SECTION_88E, EFUSE_MAX_WORD_UNIT, sizeof(u16));
+}
+
+void efuse_read_phymap_from_txpktbuf(
+	ADAPTER *adapter,
+	int bcnhead,	//beacon head, where FW store len(2-byte) and efuse physical map.
+	u8 *content,	//buffer to store efuse physical map
+	u16 *size	//for efuse content: the max byte to read. will update to byte read
+	)
+{
+	u16 dbg_addr = 0;
+	u32 start  = 0, passing_time = 0;
+	u8 reg_0x143 = 0;
+	u8 reg_0x106 = 0;
+	u32 lo32 = 0, hi32 = 0;
+	u16 len = 0, count = 0;
+	int i = 0;
+	u16 limit = *size;
+
+	u8 *pos = content;
+	
+	if(bcnhead<0) //if not valid
+		bcnhead = rtw_read8(adapter, REG_TDECTRL+1);
+
+	DBG_871X("%s bcnhead:%d\n", __FUNCTION__, bcnhead);
+
+	//reg_0x106 = rtw_read8(adapter, REG_PKT_BUFF_ACCESS_CTRL);
+	//DBG_871X("%s reg_0x106:0x%02x, write 0x%02x\n", __FUNCTION__, reg_0x106, 0x69);
+	rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, TXPKT_BUF_SELECT);
+	//DBG_871X("%s reg_0x106:0x%02x\n", __FUNCTION__, rtw_read8(adapter, 0x106));
+
+	dbg_addr = bcnhead*128/8; //8-bytes addressing
+
+	while(1)
+	{
+		//DBG_871X("%s dbg_addr:0x%x\n", __FUNCTION__, dbg_addr+i);
+		rtw_write16(adapter, REG_PKTBUF_DBG_ADDR, dbg_addr+i);
+
+		//DBG_871X("%s write reg_0x143:0x00\n", __FUNCTION__);
+		rtw_write8(adapter, REG_TXPKTBUF_DBG, 0);
+		start = rtw_get_current_time();
+		while(!(reg_0x143=rtw_read8(adapter, REG_TXPKTBUF_DBG))//dbg
+		//while(rtw_read8(adapter, REG_TXPKTBUF_DBG) & BIT0
+			&& (passing_time=rtw_get_passing_time_ms(start))<1000
+		) {
+			DBG_871X("%s polling reg_0x143:0x%02x, reg_0x106:0x%02x\n", __FUNCTION__, reg_0x143, rtw_read8(adapter, 0x106));
+			rtw_usleep_os(100);
+		}
+
+
+		lo32 = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_L);
+		hi32 = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_H);
+
+		#if 0
+		DBG_871X("%s lo32:0x%08x, %02x %02x %02x %02x\n", __FUNCTION__, lo32
+			, rtw_read8(adapter, REG_PKTBUF_DBG_DATA_L)
+			, rtw_read8(adapter, REG_PKTBUF_DBG_DATA_L+1)
+			, rtw_read8(adapter, REG_PKTBUF_DBG_DATA_L+2)
+			, rtw_read8(adapter, REG_PKTBUF_DBG_DATA_L+3)
+		);
+		DBG_871X("%s hi32:0x%08x, %02x %02x %02x %02x\n", __FUNCTION__, hi32
+			, rtw_read8(adapter, REG_PKTBUF_DBG_DATA_H)
+			, rtw_read8(adapter, REG_PKTBUF_DBG_DATA_H+1)
+			, rtw_read8(adapter, REG_PKTBUF_DBG_DATA_H+2)
+			, rtw_read8(adapter, REG_PKTBUF_DBG_DATA_H+3)
+		);
+		#endif
+
+		if(i==0)
+		{
+			#if 1 //for debug
+			u8 lenc[2];
+			u16 lenbak, aaabak;
+			u16 aaa;
+			lenc[0] = rtw_read8(adapter, REG_PKTBUF_DBG_DATA_L);
+			lenc[1] = rtw_read8(adapter, REG_PKTBUF_DBG_DATA_L+1);
+
+			aaabak = le16_to_cpup((u16*)lenc);
+			lenbak = le16_to_cpu(*((u16*)lenc));
+			aaa = le16_to_cpup((u16*)&lo32);
+			#endif
+			len = le16_to_cpu(*((u16*)&lo32));
+
+			limit = (len-2<limit)?len-2:limit;
+
+			DBG_871X("%s len:%u, lenbak:%u, aaa:%u, aaabak:%u\n", __FUNCTION__, len, lenbak, aaa, aaabak);
+
+			_rtw_memcpy(pos, ((u8*)&lo32)+2, (limit>=count+2)?2:limit-count);
+			count+= (limit>=count+2)?2:limit-count;
+			pos=content+count;
+			
+		}
+		else
+		{
+			_rtw_memcpy(pos, ((u8*)&lo32), (limit>=count+4)?4:limit-count);
+			count+=(limit>=count+4)?4:limit-count;
+			pos=content+count;
+			
+
+		}
+
+		if(limit>count && len-2>count) {
+			_rtw_memcpy(pos, (u8*)&hi32, (limit>=count+4)?4:limit-count);
+			count+=(limit>=count+4)?4:limit-count;
+			pos=content+count;
+		}
+
+		if(limit<=count || len-2<=count)
+			break;
+
+		i++;
+	}
+
+	rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, DISABLE_TRXPKT_BUF_ACCESS);
+	
+	DBG_871X("%s read count:%u\n", __FUNCTION__, count);
+	*size = count;
+
+}
+
+
+static s32 iol_read_efuse(
+	PADAPTER padapter,
+	u8 txpktbuf_bndy,
+	u16 offset,
+	u16 size_byte,
+	u8 *logical_map
+	)
+{
+	s32 status = _FAIL;
+	u8 reg_0x106 = 0;
+	u8 physical_map[512];
+	u16 size = 512;
+	int i;
+
+
+	rtw_write8(padapter, REG_TDECTRL+1, txpktbuf_bndy);
+	_rtw_memset(physical_map, 0xFF, 512);
+	
+	///reg_0x106 = rtw_read8(padapter, REG_PKT_BUFF_ACCESS_CTRL);
+	//DBG_871X("%s reg_0x106:0x%02x, write 0x%02x\n", __FUNCTION__, reg_0x106, 0x69);
+	rtw_write8(padapter, REG_PKT_BUFF_ACCESS_CTRL, TXPKT_BUF_SELECT);
+	//DBG_871X("%s reg_0x106:0x%02x\n", __FUNCTION__, rtw_read8(padapter, 0x106));
+
+	status = iol_execute(padapter, CMD_READ_EFUSE_MAP);
+
+	if(status == _SUCCESS)
+		efuse_read_phymap_from_txpktbuf(padapter, txpktbuf_bndy, physical_map, &size);
+
+	#if 0
+	DBG_871X("%s physical map\n", __FUNCTION__);
+	for(i=0;i<size;i++)
+	{
+		DBG_871X("%02x ", physical_map[i]);
+		if(i%16==15)
+			DBG_871X("\n");
+	}
+	DBG_871X("\n");
+	#endif
+
+	efuse_phymap_to_logical(physical_map, offset, size_byte, logical_map);
+
+	return status;
+}
+
+s32 rtl8188e_iol_efuse_patch(PADAPTER padapter)
+{
+	s32	result = _SUCCESS;
+	printk("==> %s \n",__FUNCTION__);
+	
+	if(rtw_IOL_applied(padapter)){
+		iol_mode_enable(padapter, 1);
+		result = iol_execute(padapter, CMD_READ_EFUSE_MAP);
+		if(result == _SUCCESS)			
+			result = iol_execute(padapter, CMD_EFUSE_PATCH);
+		
+		iol_mode_enable(padapter, 0);
+	}
+	return result;
+}
+
+static s32 iol_ioconfig(
+	PADAPTER padapter,
+	u8 iocfg_bndy
+	)
+{
+	s32 rst = _SUCCESS; 
+	
+	//DBG_871X("%s iocfg_bndy:%u\n", __FUNCTION__, iocfg_bndy);
+	rtw_write8(padapter, REG_TDECTRL+1, iocfg_bndy);
+	rst = iol_execute(padapter, CMD_IOCONFIG);
+	
+	return rst;
+}
+
+int rtl8188e_IOL_exec_cmds_sync(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms,u32 bndy_cnt)
+{
+	
+	u32 start_time = rtw_get_current_time();
+	u32 passing_time_ms;
+	u8 polling_ret,i;
+	int ret = _FAIL;
+	u32 t1,t2;
+	
+	//printk("===> %s ,bndy_cnt = %d \n",__FUNCTION__,bndy_cnt);
+	if (rtw_IOL_append_END_cmd(xmit_frame) != _SUCCESS)
+		goto exit;
+#ifdef CONFIG_USB_HCI
+	{
+		struct pkt_attrib	*pattrib = &xmit_frame->attrib;		
+		if(rtw_usb_bulk_size_boundary(adapter,TXDESC_SIZE+pattrib->last_txcmdsz))
+		{
+			if (rtw_IOL_append_END_cmd(xmit_frame) != _SUCCESS)
+				goto exit;
+		}			
+	}
+#endif //CONFIG_USB_HCI
+	
+	//rtw_IOL_cmd_buf_dump(adapter,xmit_frame->attrib.pktlen+TXDESC_OFFSET,xmit_frame->buf_addr);
+	//rtw_hal_mgnt_xmit(adapter, xmit_frame);
+	//rtw_dump_xframe_sync(adapter, xmit_frame);
+	
+	dump_mgntframe_and_wait(adapter, xmit_frame, max_wating_ms);
+	
+	t1=	rtw_get_current_time();
+	iol_mode_enable(adapter, 1);
+	for(i=0;i<bndy_cnt;i++){
+		u8 page_no = 0;
+		page_no = i*2 ;
+		//printk(" i = %d, page_no = %d \n",i,page_no);	
+		if( (ret = iol_ioconfig(adapter, page_no)) != _SUCCESS)
+		{
+			break;
+		}
+	}
+	iol_mode_enable(adapter, 0);
+	t2 = rtw_get_current_time();
+	//printk("==> %s :  %5u\n",__FUNCTION__,rtw_get_time_interval_ms(t1,t2));
+exit:
+	//restore BCN_HEAD
+	rtw_write8(adapter, REG_TDECTRL+1, 0);	
+	return ret;
+}
+
+void rtw_IOL_cmd_tx_pkt_buf_dump(ADAPTER *Adapter,int data_len)
+{
+	u32 fifo_data,reg_140;
+	u32 addr,rstatus,loop=0;
+
+	u16 data_cnts = (data_len/8)+1;				
+	u8 *pbuf =rtw_zvmalloc(data_len+10);
+	printk("###### %s ######\n",__FUNCTION__);
+	
+	rtw_write8(Adapter, REG_PKT_BUFF_ACCESS_CTRL, TXPKT_BUF_SELECT);
+	if(pbuf){
+		for(addr=0;addr< data_cnts;addr++){
+			//printk("==> addr:0x%02x\n",addr);
+			rtw_write32(Adapter,0x140,addr);
+			rtw_usleep_os(2);
+			loop=0;
+			do{
+				rstatus=(reg_140=rtw_read32(Adapter,REG_PKTBUF_DBG_CTRL)&BIT24);	
+				//printk("rstatus = %02x, reg_140:0x%08x\n",rstatus,reg_140);
+				if(rstatus){
+					fifo_data = rtw_read32(Adapter,REG_PKTBUF_DBG_DATA_L);
+					//printk("fifo_data_144:0x%08x\n",fifo_data);					
+					_rtw_memcpy(pbuf+(addr*8),&fifo_data , 4);  
+					
+					fifo_data = rtw_read32(Adapter,REG_PKTBUF_DBG_DATA_H);
+					//printk("fifo_data_148:0x%08x\n",fifo_data);					
+					_rtw_memcpy(pbuf+(addr*8+4), &fifo_data, 4); 
+					
+				}
+				rtw_usleep_os(2);
+			}while( !rstatus && (loop++ <10));
+		}
+		rtw_IOL_cmd_buf_dump(Adapter,data_len,pbuf);
+		rtw_vmfree(pbuf, data_len+10);	
+		
+	}					
+	printk("###### %s ######\n",__FUNCTION__);
+}
+
+#endif /* defined(CONFIG_IOL) */
+
+
+static VOID
+_FWDownloadEnable(
+	IN	PADAPTER		padapter,
+	IN	BOOLEAN			enable
+	)
+{
+	u8	tmp;
+
+	if(enable)
+	{
+		// MCU firmware download enable.
+		tmp = rtw_read8(padapter, REG_MCUFWDL);
+		rtw_write8(padapter, REG_MCUFWDL, tmp|0x01);
+
+		// 8051 reset
+		tmp = rtw_read8(padapter, REG_MCUFWDL+2);
+		rtw_write8(padapter, REG_MCUFWDL+2, tmp&0xf7);
+	}
+	else
+	{		
+		
+		// MCU firmware download disable.
+		tmp = rtw_read8(padapter, REG_MCUFWDL);
+		rtw_write8(padapter, REG_MCUFWDL, tmp&0xfe);
+
+		// Reserved for fw extension.
+		rtw_write8(padapter, REG_MCUFWDL+1, 0x00);
+	}
+}
+#define MAX_REG_BOLCK_SIZE	196 
+static int
+_BlockWrite(
+	IN		PADAPTER		padapter,
+	IN		PVOID		buffer,
+	IN		u32			buffSize
+	)
+{
+	int ret = _SUCCESS;
+
+	u32			blockSize_p1 = 4;	// (Default) Phase #1 : PCI muse use 4-byte write to download FW
+	u32			blockSize_p2 = 8;	// Phase #2 : Use 8-byte, if Phase#1 use big size to write FW.
+	u32			blockSize_p3 = 1;	// Phase #3 : Use 1-byte, the remnant of FW image.
+	u32			blockCount_p1 = 0, blockCount_p2 = 0, blockCount_p3 = 0;
+	u32			remainSize_p1 = 0, remainSize_p2 = 0;
+	u8			*bufferPtr	= (u8*)buffer;
+	u32			i=0, offset=0;
+#ifdef CONFIG_PCI_HCI
+	u8			remainFW[4] = {0, 0, 0, 0};
+	u8			*p = NULL;
+#endif
+
+#ifdef CONFIG_USB_HCI
+	blockSize_p1 = MAX_REG_BOLCK_SIZE;
+#endif
+
+	//3 Phase #1
+	blockCount_p1 = buffSize / blockSize_p1;
+	remainSize_p1 = buffSize % blockSize_p1;
+
+	if (blockCount_p1) {
+		RT_TRACE(_module_hal_init_c_, _drv_notice_,
+				("_BlockWrite: [P1] buffSize(%d) blockSize_p1(%d) blockCount_p1(%d) remainSize_p1(%d)\n",
+				buffSize, blockSize_p1, blockCount_p1, remainSize_p1));
+	}
+
+	for (i = 0; i < blockCount_p1; i++)
+	{
+#ifdef CONFIG_USB_HCI
+		ret = rtw_writeN(padapter, (FW_8188E_START_ADDRESS + i * blockSize_p1), blockSize_p1, (bufferPtr + i * blockSize_p1));
+#else
+		ret = rtw_write32(padapter, (FW_8188E_START_ADDRESS + i * blockSize_p1), le32_to_cpu(*((u32*)(bufferPtr + i * blockSize_p1))));
+#endif
+
+		if(ret == _FAIL)
+			goto exit;
+	}
+
+#ifdef CONFIG_PCI_HCI
+	p = (u8*)((u32*)(bufferPtr + blockCount_p1 * blockSize_p1));
+	if (remainSize_p1) {
+		switch (remainSize_p1) {
+		case 0:
+			break;
+		case 3:
+			remainFW[2]=*(p+2);
+		case 2: 	
+			remainFW[1]=*(p+1);
+		case 1: 	
+			remainFW[0]=*(p);
+			ret = rtw_write32(padapter, (FW_8188E_START_ADDRESS + blockCount_p1 * blockSize_p1), 
+				 le32_to_cpu(*(u32*)remainFW));	
+		}
+		return ret;
+	}
+#endif
+
+	//3 Phase #2
+	if (remainSize_p1)
+	{
+		offset = blockCount_p1 * blockSize_p1;
+
+		blockCount_p2 = remainSize_p1/blockSize_p2;
+		remainSize_p2 = remainSize_p1%blockSize_p2;
+
+		if (blockCount_p2) {
+				RT_TRACE(_module_hal_init_c_, _drv_notice_,
+						("_BlockWrite: [P2] buffSize_p2(%d) blockSize_p2(%d) blockCount_p2(%d) remainSize_p2(%d)\n",
+						(buffSize-offset), blockSize_p2 ,blockCount_p2, remainSize_p2));
+		}
+
+#ifdef CONFIG_USB_HCI
+		for (i = 0; i < blockCount_p2; i++) {
+			ret = rtw_writeN(padapter, (FW_8188E_START_ADDRESS + offset + i*blockSize_p2), blockSize_p2, (bufferPtr + offset + i*blockSize_p2));
+			
+			if(ret == _FAIL)
+				goto exit;
+		}
+#endif
+	}
+
+	//3 Phase #3
+	if (remainSize_p2)
+	{
+		offset = (blockCount_p1 * blockSize_p1) + (blockCount_p2 * blockSize_p2);
+
+		blockCount_p3 = remainSize_p2 / blockSize_p3;
+
+		RT_TRACE(_module_hal_init_c_, _drv_notice_,
+				("_BlockWrite: [P3] buffSize_p3(%d) blockSize_p3(%d) blockCount_p3(%d)\n",
+				(buffSize-offset), blockSize_p3, blockCount_p3));
+
+		for(i = 0 ; i < blockCount_p3 ; i++){
+			ret =rtw_write8(padapter, (FW_8188E_START_ADDRESS + offset + i), *(bufferPtr + offset + i));
+			
+			if(ret == _FAIL)
+				goto exit;
+		}
+	}
+
+exit:
+	return ret;
+}
+
+static int
+_PageWrite(
+	IN		PADAPTER	padapter,
+	IN		u32			page,
+	IN		PVOID		buffer,
+	IN		u32			size
+	)
+{
+	u8 value8;
+	u8 u8Page = (u8) (page & 0x07) ;
+
+	value8 = (rtw_read8(padapter, REG_MCUFWDL+2) & 0xF8) | u8Page ;
+	rtw_write8(padapter, REG_MCUFWDL+2,value8);
+
+	return _BlockWrite(padapter,buffer,size);
+}
+
+static VOID
+_FillDummy(
+	u8*		pFwBuf,
+	u32*	pFwLen
+	)
+{
+	u32	FwLen = *pFwLen;
+	u8	remain = (u8)(FwLen%4);
+	remain = (remain==0)?0:(4-remain);
+
+	while(remain>0)
+	{
+		pFwBuf[FwLen] = 0;
+		FwLen++;
+		remain--;
+	}
+
+	*pFwLen = FwLen;
+}
+
+static int
+_WriteFW(
+	IN		PADAPTER		padapter,
+	IN		PVOID			buffer,
+	IN		u32			size
+	)
+{
+	// Since we need dynamic decide method of dwonload fw, so we call this function to get chip version.
+	// We can remove _ReadChipVersion from ReadpadapterInfo8192C later.
+	int ret = _SUCCESS;
+	u32 	pageNums,remainSize ;
+	u32 	page, offset;
+	u8		*bufferPtr = (u8*)buffer;
+
+#ifdef CONFIG_PCI_HCI
+	// 20100120 Joseph: Add for 88CE normal chip.
+	// Fill in zero to make firmware image to dword alignment.
+//		_FillDummy(bufferPtr, &size);
+#endif
+
+	pageNums = size / MAX_PAGE_SIZE ;
+	//RT_ASSERT((pageNums <= 4), ("Page numbers should not greater then 4 \n"));
+	remainSize = size % MAX_PAGE_SIZE;
+
+	for (page = 0; page < pageNums; page++) {
+		offset = page * MAX_PAGE_SIZE;
+		ret = _PageWrite(padapter, page, bufferPtr+offset, MAX_PAGE_SIZE);
+		
+		if(ret == _FAIL)
+			goto exit;
+	}
+	if (remainSize) {
+		offset = pageNums * MAX_PAGE_SIZE;
+		page = pageNums;
+		ret = _PageWrite(padapter, page, bufferPtr+offset, remainSize);
+		
+		if(ret == _FAIL)
+			goto exit;
+
+	}
+	RT_TRACE(_module_hal_init_c_, _drv_info_, ("_WriteFW Done- for Normal chip.\n"));
+
+exit:
+	return ret;
+}
+
+void _MCUIO_Reset88E(PADAPTER padapter,u8 bReset)
+{
+	u8 u1bTmp;
+
+	if(bReset==_TRUE){
+		// Reset MCU IO Wrapper- sugggest by SD1-Gimmy
+		u1bTmp = rtw_read8(padapter, REG_RSV_CTRL+1);
+		rtw_write8(padapter,REG_RSV_CTRL+1, (u1bTmp&(~BIT3)));
+	}else{
+		// Enable MCU IO Wrapper
+		u1bTmp = rtw_read8(padapter, REG_RSV_CTRL+1);
+		rtw_write8(padapter, REG_RSV_CTRL+1, u1bTmp|BIT3);
+	}
+
+}
+void _8051Reset88E(PADAPTER padapter)
+{
+	u8 u1bTmp;
+	
+	_MCUIO_Reset88E(padapter,_TRUE);
+	u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
+	rtw_write8(padapter, REG_SYS_FUNC_EN+1, u1bTmp&(~BIT2));
+	_MCUIO_Reset88E(padapter,_FALSE);
+	rtw_write8(padapter, REG_SYS_FUNC_EN+1, u1bTmp|(BIT2));
+	
+	DBG_871X("=====> _8051Reset88E(): 8051 reset success .\n");
+}
+
+static s32 _FWFreeToGo(PADAPTER padapter)
+{
+	u32	counter = 0;
+	u32	value32;
+	u8 	value8;
+
+	// polling CheckSum report
+	do {
+		value32 = rtw_read32(padapter, REG_MCUFWDL);
+		if (value32 & FWDL_ChkSum_rpt) break;
+	} while (counter++ < POLLING_READY_TIMEOUT_COUNT);
+
+	if (counter >= POLLING_READY_TIMEOUT_COUNT) {
+		DBG_871X("%s: chksum report fail! REG_MCUFWDL:0x%08x\n", __FUNCTION__, value32);
+		return _FAIL;
+	}
+	DBG_871X("%s: Checksum report OK! REG_MCUFWDL:0x%08x\n", __FUNCTION__, value32);
+
+
+	value32 = rtw_read32(padapter, REG_MCUFWDL);
+	value32 |= MCUFWDL_RDY;
+	value32 &= ~WINTINI_RDY;
+	rtw_write32(padapter, REG_MCUFWDL, value32);
+
+	_8051Reset88E(padapter);
+
+	// polling for FW ready
+	counter = 0;
+	do {
+		value32 = rtw_read32(padapter, REG_MCUFWDL);
+		if (value32 & WINTINI_RDY) {
+			DBG_871X("%s: Polling FW ready success!! REG_MCUFWDL:0x%08x\n", __FUNCTION__, value32);
+			return _SUCCESS;
+		}
+		rtw_udelay_os(5);
+	} while (counter++ < POLLING_READY_TIMEOUT_COUNT);
+
+	DBG_871X ("%s: Polling FW ready fail!! REG_MCUFWDL:0x%08x\n", __FUNCTION__, value32);
+	return _FAIL;
+}
+
+#define IS_FW_81xxC(padapter)	(((GET_HAL_DATA(padapter))->FirmwareSignature & 0xFFF0) == 0x88C0)
+
+
+#ifdef CONFIG_FILE_FWIMG
+extern char *rtw_fw_file_path;
+u8	FwBuffer8188E[FW_8188E_SIZE];
+#endif //CONFIG_FILE_FWIMG
+#ifdef CONFIG_WOWLAN
+//
+//	Description:
+//		Download 8192C firmware code.
+//
+//
+s32 rtl8188e_FirmwareDownload(PADAPTER padapter, BOOLEAN  bUsedWoWLANFw)
+#else
+s32 rtl8188e_FirmwareDownload(PADAPTER padapter)
+#endif
+{
+	s32	rtStatus = _SUCCESS;
+	u8 writeFW_retry = 0;
+	u32 fwdl_start_time;
+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(padapter);	
+	
+	u8			*FwImage;
+	u32			FwImageLen;
+	u8			*pFwImageFileName;
+#ifdef CONFIG_WOWLAN
+	u8			*FwImageWoWLAN;
+	u32			FwImageWoWLANLen;
+#endif
+	u8			*pucMappedFile = NULL;
+	PRT_FIRMWARE_8188E	pFirmware = NULL;
+	PRT_8188E_FIRMWARE_HDR		pFwHdr = NULL;
+	u8			*pFirmwareBuf;
+	u32			FirmwareLen;
+
+
+	RT_TRACE(_module_hal_init_c_, _drv_info_, ("+%s\n", __FUNCTION__));
+	pFirmware = (PRT_FIRMWARE_8188E)rtw_zmalloc(sizeof(RT_FIRMWARE_8188E));
+	if(!pFirmware)
+	{
+	
+		rtStatus = _FAIL;
+		goto Exit;
+	}
+	
+	FwImage = (u8*)Rtl8188E_FwImageArray;
+	FwImageLen = Rtl8188E_FWImgArrayLength;
+
+#ifdef CONFIG_WOWLAN
+	FwImageWoWLAN = (u8*)Rtl8188E_FwWoWImageArray;
+	FwImageWoWLANLen = Rtl8188E_FwWoWImgArrayLength;
+#endif //CONFIG_WOWLAN
+	
+//	RT_TRACE(_module_hal_init_c_, _drv_err_, ("rtl8723a_FirmwareDownload: %s\n", pFwImageFileName));
+
+	#ifdef CONFIG_FILE_FWIMG
+	if(rtw_is_file_readable(rtw_fw_file_path) == _TRUE)
+	{
+		DBG_871X("%s accquire FW from file:%s\n", __FUNCTION__, rtw_fw_file_path);
+		pFirmware->eFWSource = FW_SOURCE_IMG_FILE;
+	}
+	else
+	#endif //CONFIG_FILE_FWIMG
+	{
+		pFirmware->eFWSource = FW_SOURCE_HEADER_FILE;
+	}
+
+	switch(pFirmware->eFWSource)
+	{
+		case FW_SOURCE_IMG_FILE:
+			#ifdef CONFIG_FILE_FWIMG
+			rtStatus = rtw_retrive_from_file(rtw_fw_file_path, FwBuffer8188E, FW_8188E_SIZE);
+			pFirmware->ulFwLength = rtStatus>=0?rtStatus:0;
+			pFirmware->szFwBuffer = FwBuffer8188E;
+			#endif //CONFIG_FILE_FWIMG
+			break;
+		case FW_SOURCE_HEADER_FILE:
+			if (FwImageLen > FW_8188E_SIZE) {
+				rtStatus = _FAIL;
+				RT_TRACE(_module_hal_init_c_, _drv_err_, ("Firmware size exceed 0x%X. Check it.\n", FW_8188E_SIZE) );
+				goto Exit;
+			}
+
+			pFirmware->szFwBuffer = FwImage;
+			pFirmware->ulFwLength = FwImageLen;
+#ifdef CONFIG_WOWLAN
+			if(bUsedWoWLANFw){
+				pFirmware->szWoWLANFwBuffer = FwImageWoWLAN;
+				pFirmware->ulWoWLANFwLength = FwImageWoWLANLen;
+			}
+#endif //CONFIG_WOWLAN
+			break;
+	}
+#ifdef CONFIG_WOWLAN
+	if(bUsedWoWLANFw) {
+		pFirmwareBuf = pFirmware->szWoWLANFwBuffer;
+		FirmwareLen = pFirmware->ulWoWLANFwLength;
+		pFwHdr = (PRT_8188E_FIRMWARE_HDR)pFirmware->szWoWLANFwBuffer;
+	} else
+#endif
+	{
+	pFirmwareBuf = pFirmware->szFwBuffer;
+	FirmwareLen = pFirmware->ulFwLength;
+	DBG_871X_LEVEL(_drv_info_, "+%s: !bUsedWoWLANFw, FmrmwareLen:%d+\n", __func__, FirmwareLen);
+
+	// To Check Fw header. Added by tynli. 2009.12.04.
+	pFwHdr = (PRT_8188E_FIRMWARE_HDR)pFirmware->szFwBuffer;
+	}
+
+	pHalData->FirmwareVersion =  le16_to_cpu(pFwHdr->Version);
+	pHalData->FirmwareSubVersion = pFwHdr->Subversion;
+	pHalData->FirmwareSignature = le16_to_cpu(pFwHdr->Signature);
+
+	DBG_871X ("%s: fw_ver=%d fw_subver=%d sig=0x%x\n",
+		  __FUNCTION__, pHalData->FirmwareVersion, pHalData->FirmwareSubVersion, pHalData->FirmwareSignature);
+
+	if (IS_FW_HEADER_EXIST(pFwHdr))
+	{
+		// Shift 32 bytes for FW header
+		pFirmwareBuf = pFirmwareBuf + 32;
+		FirmwareLen = FirmwareLen - 32;
+	}
+
+	// Suggested by Filen. If 8051 is running in RAM code, driver should inform Fw to reset by itself,
+	// or it will cause download Fw fail. 2010.02.01. by tynli.
+	if (rtw_read8(padapter, REG_MCUFWDL) & RAM_DL_SEL) //8051 RAM code
+	{
+		rtw_write8(padapter, REG_MCUFWDL, 0x00);
+		_8051Reset88E(padapter);		
+	}
+
+	_FWDownloadEnable(padapter, _TRUE);
+	fwdl_start_time = rtw_get_current_time();
+	while(1) {
+		//reset the FWDL chksum
+		rtw_write8(padapter, REG_MCUFWDL, rtw_read8(padapter, REG_MCUFWDL)|FWDL_ChkSum_rpt);
+		
+		rtStatus = _WriteFW(padapter, pFirmwareBuf, FirmwareLen);
+
+		if(rtStatus == _SUCCESS
+			||(rtw_get_passing_time_ms(fwdl_start_time) > 500 && writeFW_retry++ >= 3)
+		)
+			break;
+
+		DBG_871X("%s writeFW_retry:%u, time after fwdl_start_time:%ums\n", __FUNCTION__
+			, writeFW_retry
+			, rtw_get_passing_time_ms(fwdl_start_time)
+		);
+	}
+	_FWDownloadEnable(padapter, _FALSE);
+	if(_SUCCESS != rtStatus){
+		DBG_871X("DL Firmware failed!\n");
+		goto Exit;
+	}
+
+	rtStatus = _FWFreeToGo(padapter);
+	if (_SUCCESS != rtStatus) {
+		DBG_871X("DL Firmware failed!\n");
+		goto Exit;
+	}
+	RT_TRACE(_module_hal_init_c_, _drv_info_, ("Firmware is ready to run!\n"));
+
+Exit:
+
+	if (pFirmware)
+		rtw_mfree((u8*)pFirmware, sizeof(RT_FIRMWARE_8188E));
+
+	//RT_TRACE(COMP_INIT, DBG_LOUD, (" <=== FirmwareDownload91C()\n"));
+#ifdef CONFIG_WOWLAN
+	if (padapter->pwrctrlpriv.wowlan_mode)
+		rtl8188e_InitializeFirmwareVars(padapter);	
+	else
+		DBG_871X_LEVEL(_drv_always_, "%s: wowland_mode:%d wowlan_wake_reason:%d\n", 
+			__func__, padapter->pwrctrlpriv.wowlan_mode, 
+			padapter->pwrctrlpriv.wowlan_wake_reason);
+#endif
+
+	return rtStatus;
+}
+
+#ifdef CONFIG_WOWLAN
+void rtl8188e_InitializeFirmwareVars(PADAPTER padapter)
+{
+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
+	struct pwrctrl_priv *pwrpriv;
+	pwrpriv = &padapter->pwrctrlpriv;
+
+	// Init Fw LPS related.
+	padapter->pwrctrlpriv.bFwCurrentInPSMode = _FALSE;
+	// Init H2C counter. by tynli. 2009.12.09.
+	pHalData->LastHMEBoxNum = 0;
+}
+
+//===========================================
+
+//
+// Description: Prepare some information to Fw for WoWLAN.
+//					(1) Download wowlan Fw.
+//					(2) Download RSVD page packets.
+//					(3) Enable AP offload if needed.
+//
+// 2011.04.12 by tynli.
+//
+VOID
+SetFwRelatedForWoWLAN8188ES(
+		IN		PADAPTER			padapter,
+		IN		u8					bHostIsGoingtoSleep
+)
+{
+		int				status=_FAIL;
+		HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+		u8				bRecover = _FALSE;
+	//
+	// 1. Before WoWLAN we need to re-download WoWLAN Fw.
+	//
+	status = rtl8188e_FirmwareDownload(padapter, bHostIsGoingtoSleep);
+	if(status != _SUCCESS) {
+		DBG_871X("ConfigFwRelatedForWoWLAN8188ES(): Re-Download Firmware failed!!\n");
+		return;
+	} else {
+		DBG_871X("ConfigFwRelatedForWoWLAN8188ES(): Re-Download Firmware Success !!\n");
+	}
+	//
+	// 2. Re-Init the variables about Fw related setting.
+	//
+	rtl8188e_InitializeFirmwareVars(padapter);
+}
+#else
+void rtl8188e_InitializeFirmwareVars(PADAPTER padapter)
+{
+	PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
+
+	// Init Fw LPS related.
+	padapter->pwrctrlpriv.bFwCurrentInPSMode = _FALSE;
+
+	// Init H2C counter. by tynli. 2009.12.09.
+	pHalData->LastHMEBoxNum = 0;
+//	pHalData->H2CQueueHead = 0;
+//	pHalData->H2CQueueTail = 0;
+//	pHalData->H2CStopInsertQueue = FALSE;
+}
+#endif //CONFIG_WOWLAN
+
+static void rtl8188e_free_hal_data(PADAPTER padapter)
+{
+_func_enter_;
+	if (padapter->HalData) {
+		rtw_mfree(padapter->HalData, sizeof(HAL_DATA_TYPE));
+		padapter->HalData = NULL;
+	}
+_func_exit_;
+}
+
+//===========================================================
+//				Efuse related code
+//===========================================================
+enum{
+		VOLTAGE_V25						= 0x03,
+		LDOE25_SHIFT						= 28 ,
+	};
+
+static BOOLEAN
+hal_EfusePgPacketWrite2ByteHeader(
+	IN	PADAPTER		pAdapter,
+	IN	u8				efuseType,
+	IN	u16				*pAddr,
+	IN	PPGPKT_STRUCT	pTargetPkt,
+	IN	BOOLEAN			bPseudoTest);
+static BOOLEAN
+hal_EfusePgPacketWrite1ByteHeader(
+	IN	PADAPTER		pAdapter,
+	IN	u8				efuseType,
+	IN	u16				*pAddr,
+	IN	PPGPKT_STRUCT	pTargetPkt,
+	IN	BOOLEAN			bPseudoTest);
+static BOOLEAN
+hal_EfusePgPacketWriteData(
+	IN	PADAPTER		pAdapter,
+	IN	u8				efuseType,
+	IN	u16				*pAddr,
+	IN	PPGPKT_STRUCT	pTargetPkt,
+	IN	BOOLEAN			bPseudoTest);
+
+static VOID
+hal_EfusePowerSwitch_RTL8188E(
+	IN	PADAPTER	pAdapter,
+	IN	u8		bWrite,
+	IN	u8		PwrState)
+{
+	u8	tempval;
+	u16	tmpV16;
+
+	if (PwrState == _TRUE)
+	{
+		rtw_write8(pAdapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_ON);
+
+		// 1.2V Power: From VDDON with Power Cut(0x0000h[15]), defualt valid
+		tmpV16 = rtw_read16(pAdapter,REG_SYS_ISO_CTRL);
+		if( ! (tmpV16 & PWC_EV12V ) ){
+			tmpV16 |= PWC_EV12V ;
+			 rtw_write16(pAdapter,REG_SYS_ISO_CTRL,tmpV16);
+		}
+		// Reset: 0x0000h[28], default valid
+		tmpV16 =  rtw_read16(pAdapter,REG_SYS_FUNC_EN);
+		if( !(tmpV16 & FEN_ELDR) ){
+			tmpV16 |= FEN_ELDR ;
+			rtw_write16(pAdapter,REG_SYS_FUNC_EN,tmpV16);
+		}
+
+		// Clock: Gated(0x0008h[5]) 8M(0x0008h[1]) clock from ANA, default valid
+		tmpV16 = rtw_read16(pAdapter,REG_SYS_CLKR);
+		if( (!(tmpV16 & LOADER_CLK_EN) )  ||(!(tmpV16 & ANA8M) ) ){
+			tmpV16 |= (LOADER_CLK_EN |ANA8M ) ;
+			rtw_write16(pAdapter,REG_SYS_CLKR,tmpV16);
+		}
+
+		if(bWrite == _TRUE)
+		{
+			// Enable LDO 2.5V before read/write action
+			tempval = rtw_read8(pAdapter, EFUSE_TEST+3);
+			tempval &= 0x0F;
+			tempval |= (VOLTAGE_V25 << 4);
+			rtw_write8(pAdapter, EFUSE_TEST+3, (tempval | 0x80));
+		}
+	}
+	else
+	{
+		rtw_write8(pAdapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_OFF);
+
+		if(bWrite == _TRUE){
+			// Disable LDO 2.5V after read/write action
+			tempval = rtw_read8(pAdapter, EFUSE_TEST+3);
+			rtw_write8(pAdapter, EFUSE_TEST+3, (tempval & 0x7F));
+		}
+	}
+}
+
+static VOID
+rtl8188e_EfusePowerSwitch(
+	IN	PADAPTER	pAdapter,
+	IN	u8		bWrite,
+	IN	u8		PwrState)
+{
+	hal_EfusePowerSwitch_RTL8188E(pAdapter, bWrite, PwrState);	
+}
+
+
+
+static bool efuse_read_phymap(
+	PADAPTER	Adapter,
+	u8			*pbuf,	//buffer to store efuse physical map
+	u16			*size	//the max byte to read. will update to byte read
+	)
+{
+	u8 *pos = pbuf;
+	u16 limit = *size;
+	u16 addr = 0;
+	bool reach_end = _FALSE;
+
+	//
+	// Refresh efuse init map as all 0xFF.
+	//
+	_rtw_memset(pbuf, 0xFF, limit);
+		
+	
+	//
+	// Read physical efuse content.
+	//
+	while(addr < limit)
+	{
+		ReadEFuseByte(Adapter, addr, pos, _FALSE);
+		if(*pos != 0xFF)
+		{
+			pos++;
+			addr++;
+		}
+		else
+		{
+			reach_end = _TRUE;
+			break;
+		}
+	}
+
+	*size = addr;
+
+	return reach_end;
+
+}
+
+static VOID
+Hal_EfuseReadEFuse88E(
+	PADAPTER		Adapter,
+	u16			_offset,
+	u16 			_size_byte,
+	u8      		*pbuf,
+	IN	BOOLEAN	bPseudoTest
+	)
+{
+	//u8	efuseTbl[EFUSE_MAP_LEN_88E];
+	u8	*efuseTbl = NULL;
+	u8	rtemp8[1];
+	u16	eFuse_Addr = 0;
+	u8	offset, wren;
+	u16	i, j;
+	//u16	eFuseWord[EFUSE_MAX_SECTION_88E][EFUSE_MAX_WORD_UNIT];
+	u16	**eFuseWord = NULL;
+	u16	efuse_utilized = 0;
+	u8	efuse_usage = 0;
+	u8	u1temp = 0;
+
+	//
+	// Do NOT excess total size of EFuse table. Added by Roger, 2008.11.10.
+	//
+	if((_offset + _size_byte)>EFUSE_MAP_LEN_88E)
+	{// total E-Fuse table is 512bytes
+		DBG_8192C("Hal_EfuseReadEFuse88E(): Invalid offset(%#x) with read bytes(%#x)!!\n",_offset, _size_byte);
+		goto exit;
+	}
+
+	efuseTbl = (u8*)rtw_zmalloc(EFUSE_MAP_LEN_88E);
+	if(efuseTbl == NULL)
+	{
+		DBG_871X("%s: alloc efuseTbl fail!\n", __FUNCTION__);
+		goto exit;
+	}
+
+	eFuseWord= (u16 **)rtw_malloc2d(EFUSE_MAX_SECTION_88E, EFUSE_MAX_WORD_UNIT, sizeof(u16));
+	if(eFuseWord == NULL)
+	{
+		DBG_871X("%s: alloc eFuseWord fail!\n", __FUNCTION__);
+		goto exit;
+	}
+
+	// 0. Refresh efuse init map as all oxFF.
+	for (i = 0; i < EFUSE_MAX_SECTION_88E; i++)
+		for (j = 0; j < EFUSE_MAX_WORD_UNIT; j++)
+			eFuseWord[i][j] = 0xFFFF;
+
+	//
+	// 1. Read the first byte to check if efuse is empty!!!
+	// 
+	//
+	ReadEFuseByte(Adapter, eFuse_Addr, rtemp8, bPseudoTest);	
+	if(*rtemp8 != 0xFF)
+	{
+		efuse_utilized++;
+		//DBG_8192C("efuse_Addr-%d efuse_data=%x\n", eFuse_Addr, *rtemp8);
+		eFuse_Addr++;
+	}
+	else
+	{
+		DBG_871X("EFUSE is empty efuse_Addr-%d efuse_data=%x\n", eFuse_Addr, *rtemp8);
+		goto exit;
+	}
+
+
+	//
+	// 2. Read real efuse content. Filter PG header and every section data.
+	//
+	while((*rtemp8 != 0xFF) && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN_88E))
+	{
+		//RTPRINT(FEEPROM, EFUSE_READ_ALL, ("efuse_Addr-%d efuse_data=%x\n", eFuse_Addr-1, *rtemp8));
+	
+		// Check PG header for section num.
+		if((*rtemp8 & 0x1F ) == 0x0F)		//extended header
+		{			
+			u1temp =( (*rtemp8 & 0xE0) >> 5);
+			//RTPRINT(FEEPROM, EFUSE_READ_ALL, ("extended header u1temp=%x *rtemp&0xE0 0x%x\n", u1temp, *rtemp8 & 0xE0));
+
+			//RTPRINT(FEEPROM, EFUSE_READ_ALL, ("extended header u1temp=%x \n", u1temp));
+			
+			ReadEFuseByte(Adapter, eFuse_Addr, rtemp8, bPseudoTest);	
+
+			//RTPRINT(FEEPROM, EFUSE_READ_ALL, ("extended header efuse_Addr-%d efuse_data=%x\n", eFuse_Addr, *rtemp8));	
+			
+			if((*rtemp8 & 0x0F) == 0x0F)
+			{
+				eFuse_Addr++;			
+				ReadEFuseByte(Adapter, eFuse_Addr, rtemp8, bPseudoTest); 
+				
+				if(*rtemp8 != 0xFF && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN_88E))
+				{
+					eFuse_Addr++;				
+				}				
+				continue;
+			}
+			else
+			{
+				offset = ((*rtemp8 & 0xF0) >> 1) | u1temp;
+				wren = (*rtemp8 & 0x0F);
+				eFuse_Addr++;				
+			}
+		}
+		else
+		{
+			offset = ((*rtemp8 >> 4) & 0x0f);
+			wren = (*rtemp8 & 0x0f);			
+		}
+		
+		if(offset < EFUSE_MAX_SECTION_88E)
+		{
+			// Get word enable value from PG header
+			//RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Offset-%d Worden=%x\n", offset, wren));
+
+			for(i=0; i<EFUSE_MAX_WORD_UNIT; i++)
+			{
+				// Check word enable condition in the section				
+				if(!(wren & 0x01))
+				{
+					//RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Addr=%d \n", eFuse_Addr));
+					ReadEFuseByte(Adapter, eFuse_Addr, rtemp8, bPseudoTest);	
+					eFuse_Addr++;
+					//RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Data=0x%x\n", *rtemp8)); 				
+					efuse_utilized++;
+					eFuseWord[offset][i] = (*rtemp8 & 0xff);
+					
+
+					if(eFuse_Addr >= EFUSE_REAL_CONTENT_LEN_88E) 
+						break;
+
+					//RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Addr=%d", eFuse_Addr));
+					ReadEFuseByte(Adapter, eFuse_Addr, rtemp8, bPseudoTest);	
+					eFuse_Addr++;
+					//RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Data=0x%x\n", *rtemp8)); 				
+					
+					efuse_utilized++;
+					eFuseWord[offset][i] |= (((u2Byte)*rtemp8 << 8) & 0xff00);
+
+					if(eFuse_Addr >= EFUSE_REAL_CONTENT_LEN_88E) 
+						break;
+				}
+				
+				wren >>= 1;
+				
+			}
+		}
+
+		// Read next PG header
+		ReadEFuseByte(Adapter, eFuse_Addr, rtemp8, bPseudoTest);	
+		//RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Addr=%d rtemp 0x%x\n", eFuse_Addr, *rtemp8));
+		
+		if(*rtemp8 != 0xFF && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN_88E))
+		{
+			efuse_utilized++;
+			eFuse_Addr++;
+		}
+	}
+
+	//
+	// 3. Collect 16 sections and 4 word unit into Efuse map.
+	//
+	for(i=0; i<EFUSE_MAX_SECTION_88E; i++)
+	{
+		for(j=0; j<EFUSE_MAX_WORD_UNIT; j++)
+		{
+			efuseTbl[(i*8)+(j*2)]=(eFuseWord[i][j] & 0xff);
+			efuseTbl[(i*8)+((j*2)+1)]=((eFuseWord[i][j] >> 8) & 0xff);
+		}
+	}
+
+
+	//
+	// 4. Copy from Efuse map to output pointer memory!!!
+	//
+	for(i=0; i<_size_byte; i++)
+	{		
+		pbuf[i] = efuseTbl[_offset+i];
+	}
+
+	//
+	// 5. Calculate Efuse utilization.
+	//
+	efuse_usage = (u1Byte)((eFuse_Addr*100)/EFUSE_REAL_CONTENT_LEN_88E);
+	rtw_hal_set_hwreg(Adapter, HW_VAR_EFUSE_BYTES, (u8 *)&eFuse_Addr);
+
+exit:
+	if(efuseTbl)
+		rtw_mfree(efuseTbl, EFUSE_MAP_LEN_88E);
+
+	if(eFuseWord)
+		rtw_mfree2d((void *)eFuseWord, EFUSE_MAX_SECTION_88E, EFUSE_MAX_WORD_UNIT, sizeof(u16));
+}
+
+
+static BOOLEAN
+Hal_EfuseSwitchToBank(
+	IN		PADAPTER	pAdapter,
+	IN		u8			bank,
+	IN		BOOLEAN		bPseudoTest
+	)
+{
+	BOOLEAN		bRet = _FALSE;
+	u32		value32=0;
+
+	//RTPRINT(FEEPROM, EFUSE_PG, ("Efuse switch bank to %d\n", bank));
+	if(bPseudoTest)
+	{
+		fakeEfuseBank = bank;
+		bRet = _TRUE;
+	}
+	else
+	{
+		if(IS_HARDWARE_TYPE_8723A(pAdapter) &&
+			INCLUDE_MULTI_FUNC_BT(pAdapter))
+		{
+			value32 = rtw_read32(pAdapter, EFUSE_TEST);
+			bRet = _TRUE;
+			switch(bank)
+			{
+			case 0:
+				value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
+				break;
+			case 1:
+				value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_0);
+				break;
+			case 2:
+				value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_1);
+				break;
+			case 3:
+				value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_2);
+				break;
+			default:
+				value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
+				bRet = _FALSE;
+				break;
+			}
+			rtw_write32(pAdapter, EFUSE_TEST, value32);
+		}
+		else
+			bRet = _TRUE;
+	}
+	return bRet;
+}
+
+
+
+static VOID
+ReadEFuseByIC(
+	PADAPTER	Adapter,
+	u8		efuseType,
+	u16		 _offset,
+	u16 		_size_byte,
+	u8      	*pbuf,
+	IN BOOLEAN	bPseudoTest
+	)
+{
+#ifdef DBG_IOL_READ_EFUSE_MAP
+	u8 logical_map[512];
+#endif
+
+#ifdef CONFIG_IOL_READ_EFUSE_MAP
+	if(!bPseudoTest )//&& rtw_IOL_applied(Adapter))
+	{
+		int ret = _FAIL;
+		if(rtw_IOL_applied(Adapter))
+		{
+			rtw_hal_power_on(Adapter);
+			
+			iol_mode_enable(Adapter, 1);
+			#ifdef DBG_IOL_READ_EFUSE_MAP
+			iol_read_efuse(Adapter, 0, _offset, _size_byte, logical_map);
+			#else
+			ret = iol_read_efuse(Adapter, 0, _offset, _size_byte, pbuf);
+			#endif
+			iol_mode_enable(Adapter, 0);	
+			
+			if(_SUCCESS == ret) 
+				goto exit;
+		}
+	}
+#endif
+	Hal_EfuseReadEFuse88E(Adapter, _offset, _size_byte, pbuf, bPseudoTest);
+
+exit:
+	
+#ifdef DBG_IOL_READ_EFUSE_MAP
+	if(_rtw_memcmp(logical_map, Adapter->eeprompriv.efuse_eeprom_data, 0x130) == _FALSE)
+	{
+		int i;
+		DBG_871X("%s compare first 0x130 byte fail\n", __FUNCTION__);
+		for(i=0;i<512;i++)
+		{
+			if(i%16==0)
+				DBG_871X("0x%03x: ", i);
+			DBG_871X("%02x ", logical_map[i]);
+			if(i%16==15)
+				DBG_871X("\n");
+		}
+		DBG_871X("\n");
+	}
+#endif
+
+	return;	
+}
+
+static VOID
+ReadEFuse_Pseudo(
+	PADAPTER	Adapter,
+	u8		efuseType,
+	u16		 _offset,
+	u16 		_size_byte,
+	u8      	*pbuf,
+	IN BOOLEAN	bPseudoTest
+	)
+{
+	Hal_EfuseReadEFuse88E(Adapter, _offset, _size_byte, pbuf, bPseudoTest);
+}
+
+static VOID
+rtl8188e_ReadEFuse(
+	PADAPTER	Adapter,
+	u8		efuseType,
+	u16		_offset,
+	u16 		_size_byte,
+	u8      	*pbuf,
+	IN	BOOLEAN	bPseudoTest
+	)
+{
+	if(bPseudoTest)
+	{
+		ReadEFuse_Pseudo(Adapter, efuseType, _offset, _size_byte, pbuf, bPseudoTest);
+	}
+	else
+	{
+		ReadEFuseByIC(Adapter, efuseType, _offset, _size_byte, pbuf, bPseudoTest);
+	}
+}
+
+//Do not support BT
+VOID
+Hal_EFUSEGetEfuseDefinition88E(
+	IN		PADAPTER	pAdapter,
+	IN		u1Byte		efuseType,
+	IN		u1Byte		type,
+	OUT		PVOID		pOut
+	)
+{
+	switch(type)
+	{
+		case TYPE_EFUSE_MAX_SECTION:
+			{
+				u8*	pMax_section;
+				pMax_section = (u8*)pOut;
+				*pMax_section = EFUSE_MAX_SECTION_88E;
+			}
+			break;
+		case TYPE_EFUSE_REAL_CONTENT_LEN:
+			{
+				u16* pu2Tmp;
+				pu2Tmp = (u16*)pOut;
+				*pu2Tmp = EFUSE_REAL_CONTENT_LEN_88E;
+			}
+			break;
+		case TYPE_EFUSE_CONTENT_LEN_BANK:
+			{
+				u16* pu2Tmp;
+				pu2Tmp = (u16*)pOut;
+				*pu2Tmp = EFUSE_REAL_CONTENT_LEN_88E;
+			}
+			break;
+		case TYPE_AVAILABLE_EFUSE_BYTES_BANK:
+			{
+				u16* pu2Tmp;
+				pu2Tmp = (u16*)pOut;
+				*pu2Tmp = (u16)(EFUSE_REAL_CONTENT_LEN_88E-EFUSE_OOB_PROTECT_BYTES_88E);
+			}
+			break;
+		case TYPE_AVAILABLE_EFUSE_BYTES_TOTAL:
+			{
+				u16* pu2Tmp;
+				pu2Tmp = (u16*)pOut;
+				*pu2Tmp = (u16)(EFUSE_REAL_CONTENT_LEN_88E-EFUSE_OOB_PROTECT_BYTES_88E);
+			}
+			break;
+		case TYPE_EFUSE_MAP_LEN:
+			{
+				u16* pu2Tmp;
+				pu2Tmp = (u16*)pOut;
+				*pu2Tmp = (u16)EFUSE_MAP_LEN_88E;
+			}
+			break;
+		case TYPE_EFUSE_PROTECT_BYTES_BANK:
+			{
+				u8* pu1Tmp;
+				pu1Tmp = (u8*)pOut;
+				*pu1Tmp = (u8)(EFUSE_OOB_PROTECT_BYTES_88E);
+			}
+			break;
+		default:
+			{
+				u8* pu1Tmp;
+				pu1Tmp = (u8*)pOut;
+				*pu1Tmp = 0;
+			}
+			break;
+	}
+}
+VOID
+Hal_EFUSEGetEfuseDefinition_Pseudo88E(
+	IN		PADAPTER	pAdapter,
+	IN		u8			efuseType,
+	IN		u8			type,
+	OUT		PVOID		pOut
+	)
+{
+	switch(type)
+	{
+		case TYPE_EFUSE_MAX_SECTION:
+			{
+				u8*		pMax_section;
+				pMax_section = (pu1Byte)pOut;
+				*pMax_section = EFUSE_MAX_SECTION_88E;
+			}
+			break;
+		case TYPE_EFUSE_REAL_CONTENT_LEN:
+			{
+				u16* pu2Tmp;
+				pu2Tmp = (pu2Byte)pOut;
+				*pu2Tmp = EFUSE_REAL_CONTENT_LEN_88E;
+			}
+			break;
+		case TYPE_EFUSE_CONTENT_LEN_BANK:
+			{
+				u16* pu2Tmp;
+				pu2Tmp = (pu2Byte)pOut;
+				*pu2Tmp = EFUSE_REAL_CONTENT_LEN_88E;
+			}
+			break;
+		case TYPE_AVAILABLE_EFUSE_BYTES_BANK:
+			{
+				u16* pu2Tmp;
+				pu2Tmp = (pu2Byte)pOut;
+				*pu2Tmp = (u2Byte)(EFUSE_REAL_CONTENT_LEN_88E-EFUSE_OOB_PROTECT_BYTES_88E);
+			}
+			break;
+		case TYPE_AVAILABLE_EFUSE_BYTES_TOTAL:
+			{
+				u16* pu2Tmp;
+				pu2Tmp = (pu2Byte)pOut;
+				*pu2Tmp = (u2Byte)(EFUSE_REAL_CONTENT_LEN_88E-EFUSE_OOB_PROTECT_BYTES_88E);
+			}
+			break;
+		case TYPE_EFUSE_MAP_LEN:
+			{
+				u16* pu2Tmp;
+				pu2Tmp = (pu2Byte)pOut;
+				*pu2Tmp = (u2Byte)EFUSE_MAP_LEN_88E;
+			}
+			break;
+		case TYPE_EFUSE_PROTECT_BYTES_BANK:
+			{
+				u8* pu1Tmp;
+				pu1Tmp = (u8*)pOut;
+				*pu1Tmp = (u8)(EFUSE_OOB_PROTECT_BYTES_88E);
+			}
+			break;
+		default:
+			{
+				u8* pu1Tmp;
+				pu1Tmp = (u8*)pOut;
+				*pu1Tmp = 0;
+			}
+			break;
+	}
+}
+
+
+static VOID
+rtl8188e_EFUSE_GetEfuseDefinition(
+	IN		PADAPTER	pAdapter,
+	IN		u8		efuseType,
+	IN		u8		type,
+	OUT		void		*pOut,
+	IN		BOOLEAN		bPseudoTest
+	)
+{
+	if(bPseudoTest)
+	{
+		Hal_EFUSEGetEfuseDefinition_Pseudo88E(pAdapter, efuseType, type, pOut);
+	}
+	else
+	{
+		Hal_EFUSEGetEfuseDefinition88E(pAdapter, efuseType, type, pOut);
+	}
+}
+
+static u8
+Hal_EfuseWordEnableDataWrite(	IN	PADAPTER	pAdapter,
+							IN	u16		efuse_addr,
+							IN	u8		word_en,
+							IN	u8		*data,
+							IN	BOOLEAN		bPseudoTest)
+{
+	u16	tmpaddr = 0;
+	u16	start_addr = efuse_addr;
+	u8	badworden = 0x0F;
+	u8	tmpdata[8];
+
+	_rtw_memset((PVOID)tmpdata, 0xff, PGPKT_DATA_SIZE);
+	//RT_TRACE(COMP_EFUSE, DBG_LOUD, ("word_en = %x efuse_addr=%x\n", word_en, efuse_addr));
+
+	if(!(word_en&BIT0))
+	{
+		tmpaddr = start_addr;
+		efuse_OneByteWrite(pAdapter,start_addr++, data[0], bPseudoTest);
+		efuse_OneByteWrite(pAdapter,start_addr++, data[1], bPseudoTest);
+
+		efuse_OneByteRead(pAdapter,tmpaddr, &tmpdata[0], bPseudoTest);
+		efuse_OneByteRead(pAdapter,tmpaddr+1, &tmpdata[1], bPseudoTest);
+		if((data[0]!=tmpdata[0])||(data[1]!=tmpdata[1])){
+			badworden &= (~BIT0);
+		}
+	}
+	if(!(word_en&BIT1))
+	{
+		tmpaddr = start_addr;
+		efuse_OneByteWrite(pAdapter,start_addr++, data[2], bPseudoTest);
+		efuse_OneByteWrite(pAdapter,start_addr++, data[3], bPseudoTest);
+
+		efuse_OneByteRead(pAdapter,tmpaddr    , &tmpdata[2], bPseudoTest);
+		efuse_OneByteRead(pAdapter,tmpaddr+1, &tmpdata[3], bPseudoTest);
+		if((data[2]!=tmpdata[2])||(data[3]!=tmpdata[3])){
+			badworden &=( ~BIT1);
+		}
+	}
+	if(!(word_en&BIT2))
+	{
+		tmpaddr = start_addr;
+		efuse_OneByteWrite(pAdapter,start_addr++, data[4], bPseudoTest);
+		efuse_OneByteWrite(pAdapter,start_addr++, data[5], bPseudoTest);
+
+		efuse_OneByteRead(pAdapter,tmpaddr, &tmpdata[4], bPseudoTest);
+		efuse_OneByteRead(pAdapter,tmpaddr+1, &tmpdata[5], bPseudoTest);
+		if((data[4]!=tmpdata[4])||(data[5]!=tmpdata[5])){
+			badworden &=( ~BIT2);
+		}
+	}
+	if(!(word_en&BIT3))
+	{
+		tmpaddr = start_addr;
+		efuse_OneByteWrite(pAdapter,start_addr++, data[6], bPseudoTest);
+		efuse_OneByteWrite(pAdapter,start_addr++, data[7], bPseudoTest);
+
+		efuse_OneByteRead(pAdapter,tmpaddr, &tmpdata[6], bPseudoTest);
+		efuse_OneByteRead(pAdapter,tmpaddr+1, &tmpdata[7], bPseudoTest);
+		if((data[6]!=tmpdata[6])||(data[7]!=tmpdata[7])){
+			badworden &=( ~BIT3);
+		}
+	}
+	return badworden;
+}
+
+static u8
+Hal_EfuseWordEnableDataWrite_Pseudo(	IN	PADAPTER	pAdapter,
+							IN	u16		efuse_addr,
+							IN	u8		word_en,
+							IN	u8		*data,
+							IN	BOOLEAN		bPseudoTest)
+{
+	u8	ret=0;
+
+	ret = Hal_EfuseWordEnableDataWrite(pAdapter, efuse_addr, word_en, data, bPseudoTest);
+
+	return ret;
+}
+
+static u8
+rtl8188e_Efuse_WordEnableDataWrite(	IN	PADAPTER	pAdapter,
+							IN	u16		efuse_addr,
+							IN	u8		word_en,
+							IN	u8		*data,
+							IN	BOOLEAN		bPseudoTest)
+{
+	u8	ret=0;
+
+	if(bPseudoTest)
+	{
+		ret = Hal_EfuseWordEnableDataWrite_Pseudo(pAdapter, efuse_addr, word_en, data, bPseudoTest);
+	}
+	else
+	{
+		ret = Hal_EfuseWordEnableDataWrite(pAdapter, efuse_addr, word_en, data, bPseudoTest);
+	}
+
+	return ret;
+}
+
+
+static u16
+hal_EfuseGetCurrentSize_8188e(IN	PADAPTER	pAdapter,
+		IN		BOOLEAN			bPseudoTest)
+{
+	int	bContinual = _TRUE;
+
+	u16	efuse_addr = 0;
+	u8	hoffset=0,hworden=0;
+	u8	efuse_data,word_cnts=0;
+
+	if(bPseudoTest)
+	{
+		efuse_addr = (u16)(fakeEfuseUsedBytes);
+	}
+	else
+	{
+		rtw_hal_get_hwreg(pAdapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_addr);
+	}
+	//RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfuseGetCurrentSize_8723A(), start_efuse_addr = %d\n", efuse_addr));
+
+	while (	bContinual &&
+			efuse_OneByteRead(pAdapter, efuse_addr ,&efuse_data, bPseudoTest) &&
+			AVAILABLE_EFUSE_ADDR(efuse_addr))
+	{
+		if(efuse_data!=0xFF)
+		{
+			if((efuse_data&0x1F) == 0x0F)		//extended header
+			{
+				hoffset = efuse_data;
+				efuse_addr++;
+				efuse_OneByteRead(pAdapter, efuse_addr ,&efuse_data, bPseudoTest);
+				if((efuse_data & 0x0F) == 0x0F)
+				{
+					efuse_addr++;
+					continue;
+				}
+				else
+				{
+					hoffset = ((hoffset & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1);
+					hworden = efuse_data & 0x0F;
+				}
+			}
+			else
+			{
+				hoffset = (efuse_data>>4) & 0x0F;
+				hworden =  efuse_data & 0x0F;
+			}
+			word_cnts = Efuse_CalculateWordCnts(hworden);
+			//read next header
+			efuse_addr = efuse_addr + (word_cnts*2)+1;
+		}
+		else
+		{
+			bContinual = _FALSE ;
+		}
+	}
+
+	if(bPseudoTest)
+	{
+		fakeEfuseUsedBytes = efuse_addr;
+		//RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfuseGetCurrentSize_8723A(), return %d\n", fakeEfuseUsedBytes));
+	}
+	else
+	{
+		rtw_hal_set_hwreg(pAdapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_addr);
+		//RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfuseGetCurrentSize_8723A(), return %d\n", efuse_addr));
+	}
+
+	return efuse_addr;
+}
+
+static u16
+Hal_EfuseGetCurrentSize_Pseudo(IN	PADAPTER	pAdapter,
+		IN		BOOLEAN			bPseudoTest)
+{
+	u16	ret=0;
+
+	ret = hal_EfuseGetCurrentSize_8188e(pAdapter, bPseudoTest);
+
+	return ret;
+}
+
+
+static u16
+rtl8188e_EfuseGetCurrentSize(
+	IN	PADAPTER	pAdapter,
+	IN	u8			efuseType,
+	IN	BOOLEAN		bPseudoTest)
+{
+	u16	ret=0;
+
+	if(bPseudoTest)
+	{
+		ret = Hal_EfuseGetCurrentSize_Pseudo(pAdapter, bPseudoTest);
+	}
+	else
+	{
+		ret = hal_EfuseGetCurrentSize_8188e(pAdapter, bPseudoTest);
+		
+	}
+
+	return ret;
+}
+
+
+static int
+hal_EfusePgPacketRead_8188e(
+	IN	PADAPTER	pAdapter,
+	IN	u8			offset,
+	IN	u8			*data,
+	IN	BOOLEAN		bPseudoTest)
+{
+	u8	ReadState = PG_STATE_HEADER;
+
+	int	bContinual = _TRUE;
+	int	bDataEmpty = _TRUE ;
+
+	u8	efuse_data,word_cnts = 0;
+	u16	efuse_addr = 0;
+	u8	hoffset = 0,hworden = 0;
+	u8	tmpidx = 0;
+	u8	tmpdata[8];
+	u8	max_section = 0;
+	u8	tmp_header = 0;
+
+	EFUSE_GetEfuseDefinition(pAdapter, EFUSE_WIFI, TYPE_EFUSE_MAX_SECTION, (PVOID)&max_section, bPseudoTest);
+
+	if(data==NULL)
+		return _FALSE;
+	if(offset>max_section)
+		return _FALSE;
+
+	_rtw_memset((PVOID)data, 0xff, sizeof(u8)*PGPKT_DATA_SIZE);
+	_rtw_memset((PVOID)tmpdata, 0xff, sizeof(u8)*PGPKT_DATA_SIZE);
+
+
+	//
+	// <Roger_TODO> Efuse has been pre-programmed dummy 5Bytes at the end of Efuse by CP.
+	// Skip dummy parts to prevent unexpected data read from Efuse.
+	// By pass right now. 2009.02.19.
+	//
+	while(bContinual && AVAILABLE_EFUSE_ADDR(efuse_addr) )
+	{
+		//-------  Header Read -------------
+		if(ReadState & PG_STATE_HEADER)
+		{
+			if(efuse_OneByteRead(pAdapter, efuse_addr ,&efuse_data, bPseudoTest)&&(efuse_data!=0xFF))
+			{
+				if(EXT_HEADER(efuse_data))
+				{
+					tmp_header = efuse_data;
+					efuse_addr++;
+					efuse_OneByteRead(pAdapter, efuse_addr ,&efuse_data, bPseudoTest);
+					if(!ALL_WORDS_DISABLED(efuse_data))
+					{
+						hoffset = ((tmp_header & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1);
+						hworden = efuse_data & 0x0F;
+					}
+					else
+					{
+						DBG_8192C("Error, All words disabled\n");
+						efuse_addr++;
+						continue;
+					}
+				}
+				else
+				{
+					hoffset = (efuse_data>>4) & 0x0F;
+					hworden =  efuse_data & 0x0F;
+				}
+				word_cnts = Efuse_CalculateWordCnts(hworden);
+				bDataEmpty = _TRUE ;
+
+				if(hoffset==offset)
+				{
+					for(tmpidx = 0;tmpidx< word_cnts*2 ;tmpidx++)
+					{
+						if(efuse_OneByteRead(pAdapter, efuse_addr+1+tmpidx ,&efuse_data, bPseudoTest) )
+						{
+							tmpdata[tmpidx] = efuse_data;
+							if(efuse_data!=0xff)
+							{
+								bDataEmpty = _FALSE;
+							}
+						}
+					}
+					if(bDataEmpty==_FALSE){
+						ReadState = PG_STATE_DATA;
+					}else{//read next header
+						efuse_addr = efuse_addr + (word_cnts*2)+1;
+						ReadState = PG_STATE_HEADER;
+					}
+				}
+				else{//read next header
+					efuse_addr = efuse_addr + (word_cnts*2)+1;
+					ReadState = PG_STATE_HEADER;
+				}
+
+			}
+			else{
+				bContinual = _FALSE ;
+			}
+		}
+		//-------  Data section Read -------------
+		else if(ReadState & PG_STATE_DATA)
+		{
+			efuse_WordEnableDataRead(hworden,tmpdata,data);
+			efuse_addr = efuse_addr + (word_cnts*2)+1;
+			ReadState = PG_STATE_HEADER;
+		}
+
+	}
+
+	if(	(data[0]==0xff) &&(data[1]==0xff) && (data[2]==0xff)  && (data[3]==0xff) &&
+		(data[4]==0xff) &&(data[5]==0xff) && (data[6]==0xff)  && (data[7]==0xff))
+		return _FALSE;
+	else
+		return _TRUE;
+
+}
+
+static int
+Hal_EfusePgPacketRead(	IN	PADAPTER	pAdapter,
+					IN	u8			offset,
+					IN	u8			*data,
+					IN	BOOLEAN			bPseudoTest)
+{
+	int	ret=0;
+
+	ret = hal_EfusePgPacketRead_8188e(pAdapter, offset, data, bPseudoTest);
+	
+
+	return ret;
+}
+
+static int
+Hal_EfusePgPacketRead_Pseudo(	IN	PADAPTER	pAdapter,
+					IN	u8			offset,
+					IN	u8			*data,
+					IN	BOOLEAN		bPseudoTest)
+{
+	int	ret=0;
+
+	ret = hal_EfusePgPacketRead_8188e(pAdapter, offset, data, bPseudoTest);
+
+	return ret;
+}
+
+static int
+rtl8188e_Efuse_PgPacketRead(	IN	PADAPTER	pAdapter,
+					IN	u8			offset,
+					IN	u8			*data,
+					IN	BOOLEAN		bPseudoTest)
+{
+	int	ret=0;
+
+	if(bPseudoTest)
+	{
+		ret = Hal_EfusePgPacketRead_Pseudo(pAdapter, offset, data, bPseudoTest);
+	}
+	else
+	{
+		ret = Hal_EfusePgPacketRead(pAdapter, offset, data, bPseudoTest);
+	}
+
+	return ret;
+}
+
+static BOOLEAN
+hal_EfuseFixHeaderProcess(
+	IN		PADAPTER			pAdapter,
+	IN		u8					efuseType,
+	IN		PPGPKT_STRUCT		pFixPkt,
+	IN		u16					*pAddr,
+	IN		BOOLEAN				bPseudoTest
+)
+{
+	u8	originaldata[8], badworden=0;
+	u16	efuse_addr=*pAddr;
+	u32	PgWriteSuccess=0;
+
+	_rtw_memset((PVOID)originaldata, 0xff, 8);
+
+	if(Efuse_PgPacketRead(pAdapter, pFixPkt->offset, originaldata, bPseudoTest))
+	{	//check if data exist
+		badworden = Efuse_WordEnableDataWrite(pAdapter, efuse_addr+1, pFixPkt->word_en, originaldata, bPseudoTest);
+
+		if(badworden != 0xf)	// write fail
+		{			
+			PgWriteSuccess = Efuse_PgPacketWrite(pAdapter, pFixPkt->offset, badworden, originaldata, bPseudoTest);
+
+			if(!PgWriteSuccess)
+				return _FALSE;
+			else
+				efuse_addr = Efuse_GetCurrentSize(pAdapter, efuseType, bPseudoTest);
+		}
+		else
+		{
+			efuse_addr = efuse_addr + (pFixPkt->word_cnts*2) +1;
+		}
+	}
+	else
+	{
+		efuse_addr = efuse_addr + (pFixPkt->word_cnts*2) +1;
+	}
+	*pAddr = efuse_addr;
+	return _TRUE;
+}
+
+static BOOLEAN
+hal_EfusePgPacketWrite2ByteHeader(
+	IN			PADAPTER		pAdapter,
+	IN			u8				efuseType,
+	IN			u16				*pAddr,
+	IN			PPGPKT_STRUCT	pTargetPkt,
+	IN			BOOLEAN			bPseudoTest)
+{
+	BOOLEAN		bRet=_FALSE, bContinual=_TRUE;
+	u16	efuse_addr=*pAddr, efuse_max_available_len=0;
+	u8	pg_header=0, tmp_header=0, pg_header_temp=0;
+	u8	repeatcnt=0;
+
+	//RTPRINT(FEEPROM, EFUSE_PG, ("Wirte 2byte header\n"));
+	EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_BANK, (PVOID)&efuse_max_available_len, bPseudoTest);
+
+	while(efuse_addr < efuse_max_available_len)
+	{
+		pg_header = ((pTargetPkt->offset & 0x07) << 5) | 0x0F;
+		//RTPRINT(FEEPROM, EFUSE_PG, ("pg_header = 0x%x\n", pg_header));
+		efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest);
+		efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest);
+
+		while(tmp_header == 0xFF)
+		{
+			if(repeatcnt++ > EFUSE_REPEAT_THRESHOLD_)
+			{
+				//RTPRINT(FEEPROM, EFUSE_PG, ("Repeat over limit for pg_header!!\n"));
+				return _FALSE;
+			}
+
+			efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest);
+			efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest);
+		}
+
+		//to write ext_header
+		if(tmp_header == pg_header)
+		{
+			efuse_addr++;
+			pg_header_temp = pg_header;
+			pg_header = ((pTargetPkt->offset & 0x78) << 1) | pTargetPkt->word_en;
+
+			efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest);
+			efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest);
+
+			while(tmp_header == 0xFF)
+			{
+				if(repeatcnt++ > EFUSE_REPEAT_THRESHOLD_)
+				{
+					//RTPRINT(FEEPROM, EFUSE_PG, ("Repeat over limit for ext_header!!\n"));
+					return _FALSE;
+				}
+
+				efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest);
+				efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest);
+			}
+
+			if((tmp_header & 0x0F) == 0x0F)	//word_en PG fail
+			{
+				if(repeatcnt++ > EFUSE_REPEAT_THRESHOLD_)
+				{
+					//RTPRINT(FEEPROM, EFUSE_PG, ("Repeat over limit for word_en!!\n"));
+					return _FALSE;
+				}
+				else
+				{
+					efuse_addr++;
+					continue;
+				}
+			}
+			else if(pg_header != tmp_header)	//offset PG fail
+			{
+				PGPKT_STRUCT	fixPkt;
+				//RTPRINT(FEEPROM, EFUSE_PG, ("Error condition for offset PG fail, need to cover the existed data\n"));
+				fixPkt.offset = ((pg_header_temp & 0xE0) >> 5) | ((tmp_header & 0xF0) >> 1);
+				fixPkt.word_en = tmp_header & 0x0F;
+				fixPkt.word_cnts = Efuse_CalculateWordCnts(fixPkt.word_en);
+				if(!hal_EfuseFixHeaderProcess(pAdapter, efuseType, &fixPkt, &efuse_addr, bPseudoTest))
+					return _FALSE;
+			}
+			else
+			{
+				bRet = _TRUE;
+				break;
+			}
+		}
+		else if ((tmp_header & 0x1F) == 0x0F)		//wrong extended header
+		{
+			efuse_addr+=2;
+			continue;
+		}
+	}
+
+	*pAddr = efuse_addr;
+	return bRet;
+}
+
+static BOOLEAN
+hal_EfusePgPacketWrite1ByteHeader(
+	IN			PADAPTER		pAdapter,
+	IN			u8				efuseType,
+	IN			u16				*pAddr,
+	IN			PPGPKT_STRUCT	pTargetPkt,
+	IN			BOOLEAN			bPseudoTest)
+{
+	BOOLEAN		bRet=_FALSE;
+	u8	pg_header=0, tmp_header=0;
+	u16	efuse_addr=*pAddr;
+	u8	repeatcnt=0;
+
+	//RTPRINT(FEEPROM, EFUSE_PG, ("Wirte 1byte header\n"));
+	pg_header = ((pTargetPkt->offset << 4) & 0xf0) |pTargetPkt->word_en;
+
+	efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest);
+	efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest);
+
+	while(tmp_header == 0xFF)
+	{
+		if(repeatcnt++ > EFUSE_REPEAT_THRESHOLD_)
+		{
+			return _FALSE;
+		}
+		efuse_OneByteWrite(pAdapter,efuse_addr, pg_header, bPseudoTest);
+		efuse_OneByteRead(pAdapter,efuse_addr, &tmp_header, bPseudoTest);
+	}
+
+	if(pg_header == tmp_header)
+	{
+		bRet = _TRUE;
+	}
+	else
+	{
+		PGPKT_STRUCT	fixPkt;
+		//RTPRINT(FEEPROM, EFUSE_PG, ("Error condition for fixed PG packet, need to cover the existed data\n"));
+		fixPkt.offset = (tmp_header>>4) & 0x0F;
+		fixPkt.word_en = tmp_header & 0x0F;
+		fixPkt.word_cnts = Efuse_CalculateWordCnts(fixPkt.word_en);
+		if(!hal_EfuseFixHeaderProcess(pAdapter, efuseType, &fixPkt, &efuse_addr, bPseudoTest))
+			return _FALSE;
+	}
+
+	*pAddr = efuse_addr;
+	return bRet;
+}
+
+static BOOLEAN
+hal_EfusePgPacketWriteData(
+	IN			PADAPTER		pAdapter,
+	IN			u8				efuseType,
+	IN			u16				*pAddr,
+	IN			PPGPKT_STRUCT	pTargetPkt,
+	IN			BOOLEAN			bPseudoTest)
+{
+	BOOLEAN	bRet=_FALSE;
+	u16	efuse_addr=*pAddr;
+	u8	badworden=0;
+	u32	PgWriteSuccess=0;
+
+	badworden = 0x0f;
+	badworden = Efuse_WordEnableDataWrite(pAdapter, efuse_addr+1, pTargetPkt->word_en, pTargetPkt->data, bPseudoTest);
+	if(badworden == 0x0F)
+	{
+		// write ok
+		//RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfusePgPacketWriteData ok!!\n"));
+		return _TRUE;
+	}
+	else
+	{
+		//RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfusePgPacketWriteData Fail!!\n"));
+		//reorganize other pg packet
+		
+		PgWriteSuccess = Efuse_PgPacketWrite(pAdapter, pTargetPkt->offset, badworden, pTargetPkt->data, bPseudoTest);
+		
+		if(!PgWriteSuccess)
+			return _FALSE;
+		else
+			return _TRUE;
+	}
+
+	return bRet;
+}
+
+static BOOLEAN
+hal_EfusePgPacketWriteHeader(
+	IN			PADAPTER		pAdapter,
+	IN			u8				efuseType,
+	IN			u16				*pAddr,
+	IN			PPGPKT_STRUCT	pTargetPkt,
+	IN			BOOLEAN			bPseudoTest)
+{
+	BOOLEAN		bRet=_FALSE;
+
+	if(pTargetPkt->offset >= EFUSE_MAX_SECTION_BASE)
+	{
+		bRet = hal_EfusePgPacketWrite2ByteHeader(pAdapter, efuseType, pAddr, pTargetPkt, bPseudoTest);
+	}
+	else
+	{
+		bRet = hal_EfusePgPacketWrite1ByteHeader(pAdapter, efuseType, pAddr, pTargetPkt, bPseudoTest);
+	}
+
+	return bRet;
+}
+
+static BOOLEAN
+wordEnMatched(
+	IN	PPGPKT_STRUCT	pTargetPkt,
+	IN	PPGPKT_STRUCT	pCurPkt,
+	IN	u8				*pWden
+)
+{
+	u8	match_word_en = 0x0F;	// default all words are disabled
+	u8	i;
+
+	// check if the same words are enabled both target and current PG packet
+	if( ((pTargetPkt->word_en & BIT0) == 0) &&
+		((pCurPkt->word_en & BIT0) == 0) )
+	{
+		match_word_en &= ~BIT0;				// enable word 0
+	}
+	if( ((pTargetPkt->word_en & BIT1) == 0) &&
+		((pCurPkt->word_en & BIT1) == 0) )
+	{
+		match_word_en &= ~BIT1;				// enable word 1
+	}
+	if( ((pTargetPkt->word_en & BIT2) == 0) &&
+		((pCurPkt->word_en & BIT2) == 0) )
+	{
+		match_word_en &= ~BIT2;				// enable word 2
+	}
+	if( ((pTargetPkt->word_en & BIT3) == 0) &&
+		((pCurPkt->word_en & BIT3) == 0) )
+	{
+		match_word_en &= ~BIT3;				// enable word 3
+	}
+
+	*pWden = match_word_en;
+
+	if(match_word_en != 0xf)
+		return _TRUE;
+	else
+		return _FALSE;
+}
+
+static BOOLEAN
+hal_EfuseCheckIfDatafollowed(
+	IN		PADAPTER		pAdapter,
+	IN		u8				word_cnts,
+	IN		u16				startAddr,
+	IN		BOOLEAN			bPseudoTest
+	)
+{
+	BOOLEAN		bRet=_FALSE;
+	u8	i, efuse_data;
+
+	for(i=0; i<(word_cnts*2) ; i++)
+	{
+		if(efuse_OneByteRead(pAdapter, (startAddr+i) ,&efuse_data, bPseudoTest)&&(efuse_data != 0xFF))
+			bRet = _TRUE;
+	}
+
+	return bRet;
+}
+
+static BOOLEAN
+hal_EfusePartialWriteCheck(
+					IN	PADAPTER		pAdapter,
+					IN	u8				efuseType,
+					IN	u16				*pAddr,
+					IN	PPGPKT_STRUCT	pTargetPkt,
+					IN	BOOLEAN			bPseudoTest
+					)
+{
+	BOOLEAN		bRet=_FALSE;
+	u8	i, efuse_data=0, cur_header=0;
+	u8	new_wden=0, matched_wden=0, badworden=0;
+	u16	startAddr=0, efuse_max_available_len=0, efuse_max=0;
+	PGPKT_STRUCT	curPkt;
+
+	EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_BANK, (PVOID)&efuse_max_available_len, bPseudoTest);
+	EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_EFUSE_REAL_CONTENT_LEN, (PVOID)&efuse_max, bPseudoTest);
+
+	if(efuseType == EFUSE_WIFI)
+	{
+		if(bPseudoTest)
+		{
+			startAddr = (u16)(fakeEfuseUsedBytes%EFUSE_REAL_CONTENT_LEN);
+		}
+		else
+		{
+			rtw_hal_get_hwreg(pAdapter, HW_VAR_EFUSE_BYTES, (u8 *)&startAddr);
+			startAddr%=EFUSE_REAL_CONTENT_LEN;
+		}
+	}
+	else
+	{
+		if(bPseudoTest)
+		{
+			startAddr = (u16)(fakeBTEfuseUsedBytes%EFUSE_REAL_CONTENT_LEN);
+		}
+		else
+		{
+			startAddr = (u16)(BTEfuseUsedBytes%EFUSE_REAL_CONTENT_LEN);
+		}
+	}
+	//RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfusePartialWriteCheck(), startAddr=%d\n", startAddr));
+
+	while(1)
+	{
+		if(startAddr >= efuse_max_available_len)
+		{
+			bRet = _FALSE;
+			break;
+		}
+
+		if(efuse_OneByteRead(pAdapter, startAddr, &efuse_data, bPseudoTest) && (efuse_data!=0xFF))
+		{
+			if(EXT_HEADER(efuse_data))
+			{
+				cur_header = efuse_data;
+				startAddr++;
+				efuse_OneByteRead(pAdapter, startAddr, &efuse_data, bPseudoTest);
+				if(ALL_WORDS_DISABLED(efuse_data))
+				{
+					//RTPRINT(FEEPROM, EFUSE_PG, ("Error condition, all words disabled"));
+					bRet = _FALSE;
+					break;
+				}
+				else
+				{
+					curPkt.offset = ((cur_header & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1);
+					curPkt.word_en = efuse_data & 0x0F;
+				}
+			}
+			else
+			{
+				cur_header  =  efuse_data;
+				curPkt.offset = (cur_header>>4) & 0x0F;
+				curPkt.word_en = cur_header & 0x0F;
+			}
+
+			curPkt.word_cnts = Efuse_CalculateWordCnts(curPkt.word_en);
+			// if same header is found but no data followed
+			// write some part of data followed by the header.
+			if( (curPkt.offset == pTargetPkt->offset) &&
+				(!hal_EfuseCheckIfDatafollowed(pAdapter, curPkt.word_cnts, startAddr+1, bPseudoTest)) &&
+				wordEnMatched(pTargetPkt, &curPkt, &matched_wden) )
+			{
+				//RTPRINT(FEEPROM, EFUSE_PG, ("Need to partial write data by the previous wrote header\n"));
+				// Here to write partial data
+				badworden = Efuse_WordEnableDataWrite(pAdapter, startAddr+1, matched_wden, pTargetPkt->data, bPseudoTest);
+				if(badworden != 0x0F)
+				{
+					u32	PgWriteSuccess=0;
+					// if write fail on some words, write these bad words again
+					
+					PgWriteSuccess = Efuse_PgPacketWrite(pAdapter, pTargetPkt->offset, badworden, pTargetPkt->data, bPseudoTest);
+					
+					if(!PgWriteSuccess)
+					{
+						bRet = _FALSE;	// write fail, return
+						break;
+					}
+				}
+				// partial write ok, update the target packet for later use
+				for(i=0; i<4; i++)
+				{
+					if((matched_wden & (0x1<<i)) == 0)	// this word has been written
+					{
+						pTargetPkt->word_en |= (0x1<<i);	// disable the word
+					}
+				}
+				pTargetPkt->word_cnts = Efuse_CalculateWordCnts(pTargetPkt->word_en);
+			}
+			// read from next header
+			startAddr = startAddr + (curPkt.word_cnts*2) +1;
+		}
+		else
+		{
+			// not used header, 0xff
+			*pAddr = startAddr;
+			//RTPRINT(FEEPROM, EFUSE_PG, ("Started from unused header offset=%d\n", startAddr));
+			bRet = _TRUE;
+			break;
+		}
+	}
+	return bRet;
+}
+
+static BOOLEAN
+hal_EfusePgCheckAvailableAddr(
+	IN	PADAPTER	pAdapter,
+	IN	u8			efuseType,
+	IN	BOOLEAN		bPseudoTest
+	)
+{
+	u16	efuse_max_available_len=0;
+
+	//Change to check TYPE_EFUSE_MAP_LEN ,beacuse 8188E raw 256,logic map over 256.
+	EFUSE_GetEfuseDefinition(pAdapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (PVOID)&efuse_max_available_len, _FALSE);
+	
+	//EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&efuse_max_available_len, bPseudoTest);
+	//RTPRINT(FEEPROM, EFUSE_PG, ("efuse_max_available_len = %d\n", efuse_max_available_len));
+
+	if(Efuse_GetCurrentSize(pAdapter, efuseType, bPseudoTest) >= efuse_max_available_len)
+	{
+		//RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfusePgCheckAvailableAddr error!!\n"));
+		return _FALSE;
+	}
+	return _TRUE;
+}
+
+static VOID
+hal_EfuseConstructPGPkt(
+					IN	u8 				offset,
+					IN	u8				word_en,
+					IN	u8				*pData,
+					IN	PPGPKT_STRUCT	pTargetPkt
+
+)
+{
+	_rtw_memset((PVOID)pTargetPkt->data, 0xFF, sizeof(u8)*8);
+	pTargetPkt->offset = offset;
+	pTargetPkt->word_en= word_en;
+	efuse_WordEnableDataRead(word_en, pData, pTargetPkt->data);
+	pTargetPkt->word_cnts = Efuse_CalculateWordCnts(pTargetPkt->word_en);
+
+	//RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfuseConstructPGPkt(), targetPkt, offset=%d, word_en=0x%x, word_cnts=%d\n", pTargetPkt->offset, pTargetPkt->word_en, pTargetPkt->word_cnts));
+}
+
+static BOOLEAN
+hal_EfusePgPacketWrite_BT(
+					IN	PADAPTER	pAdapter,
+					IN	u8 			offset,
+					IN	u8			word_en,
+					IN	u8			*pData,
+					IN	BOOLEAN		bPseudoTest
+					)
+{
+	PGPKT_STRUCT 	targetPkt;
+	u16	startAddr=0;
+	u8	efuseType=EFUSE_BT;
+
+	if(!hal_EfusePgCheckAvailableAddr(pAdapter, efuseType, bPseudoTest))
+		return _FALSE;
+
+	hal_EfuseConstructPGPkt(offset, word_en, pData, &targetPkt);
+
+	if(!hal_EfusePartialWriteCheck(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
+		return _FALSE;
+
+	if(!hal_EfusePgPacketWriteHeader(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
+		return _FALSE;
+
+	if(!hal_EfusePgPacketWriteData(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
+		return _FALSE;
+
+	return _TRUE;
+}
+
+static BOOLEAN
+hal_EfusePgPacketWrite_8188e(
+					IN	PADAPTER		pAdapter,
+					IN	u8 			offset,
+					IN	u8			word_en,
+					IN	u8			*pData,
+					IN	BOOLEAN		bPseudoTest
+					)
+{
+	PGPKT_STRUCT 	targetPkt;
+	u16			startAddr=0;
+	u8			efuseType=EFUSE_WIFI;
+
+	if(!hal_EfusePgCheckAvailableAddr(pAdapter, efuseType, bPseudoTest))
+		return _FALSE;
+
+	hal_EfuseConstructPGPkt(offset, word_en, pData, &targetPkt);
+
+	if(!hal_EfusePartialWriteCheck(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
+		return _FALSE;
+
+	if(!hal_EfusePgPacketWriteHeader(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
+		return _FALSE;
+
+	if(!hal_EfusePgPacketWriteData(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
+		return _FALSE;
+
+	return _TRUE;
+}
+
+
+static int
+Hal_EfusePgPacketWrite_Pseudo(IN	PADAPTER	pAdapter,
+					IN	u8 			offset,
+					IN	u8			word_en,
+					IN	u8			*data,
+					IN	BOOLEAN		bPseudoTest)
+{
+	int ret;
+
+	ret = hal_EfusePgPacketWrite_8188e(pAdapter, offset, word_en, data, bPseudoTest);
+
+	return ret;
+}
+
+static int
+Hal_EfusePgPacketWrite(IN	PADAPTER	pAdapter,
+					IN	u8 			offset,
+					IN	u8			word_en,
+					IN	u8			*data,
+					IN	BOOLEAN		bPseudoTest)
+{
+	int	ret=0;
+	ret = hal_EfusePgPacketWrite_8188e(pAdapter, offset, word_en, data, bPseudoTest);
+	
+
+	return ret;
+}
+
+static int
+rtl8188e_Efuse_PgPacketWrite(IN	PADAPTER	pAdapter,
+					IN	u8 			offset,
+					IN	u8			word_en,
+					IN	u8			*data,
+					IN	BOOLEAN		bPseudoTest)
+{
+	int	ret;
+
+	if(bPseudoTest)
+	{
+		ret = Hal_EfusePgPacketWrite_Pseudo(pAdapter, offset, word_en, data, bPseudoTest);
+	}
+	else
+	{
+		ret = Hal_EfusePgPacketWrite(pAdapter, offset, word_en, data, bPseudoTest);
+	}
+	return ret;
+}
+
+static HAL_VERSION
+ReadChipVersion8188E(
+	IN	PADAPTER	padapter
+	)
+{
+	u32				value32;
+	HAL_VERSION				ChipVersion;
+	HAL_DATA_TYPE	*pHalData;
+
+
+	pHalData = GET_HAL_DATA(padapter);
+
+	value32 = rtw_read32(padapter, REG_SYS_CFG);
+	ChipVersion.ICType = CHIP_8188E ;
+	ChipVersion.ChipType = ((value32 & RTL_ID) ? TEST_CHIP : NORMAL_CHIP);
+
+	ChipVersion.RFType = RF_TYPE_1T1R;
+	ChipVersion.VendorType = ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : CHIP_VENDOR_TSMC);
+	ChipVersion.CUTVersion = (value32 & CHIP_VER_RTL_MASK)>>CHIP_VER_RTL_SHIFT; // IC version (CUT)
+
+	// For regulator mode. by tynli. 2011.01.14
+	pHalData->RegulatorMode = ((value32 & TRP_BT_EN) ? RT_LDO_REGULATOR : RT_SWITCHING_REGULATOR);
+
+	ChipVersion.ROMVer = 0;	// ROM code version.	
+	pHalData->MultiFunc = RT_MULTI_FUNC_NONE;
+	
+
+//#if DBG
+#if 1	
+	dump_chip_info(ChipVersion);
+#endif
+
+	pHalData->VersionID = ChipVersion;
+
+	if (IS_1T2R(ChipVersion)){
+		pHalData->rf_type = RF_1T2R;
+		pHalData->NumTotalRFPath = 2;
+	}
+	else if (IS_2T2R(ChipVersion)){
+		pHalData->rf_type = RF_2T2R;
+		pHalData->NumTotalRFPath = 2;
+	}
+	else{
+		pHalData->rf_type = RF_1T1R;
+		pHalData->NumTotalRFPath = 1;
+	}
+		
+	MSG_8192C("RF_Type is %x!!\n", pHalData->rf_type);
+
+	return ChipVersion;
+}
+
+static void rtl8188e_read_chip_version(PADAPTER padapter)
+{
+	ReadChipVersion8188E(padapter);	
+}
+void rtl8188e_GetHalODMVar(	
+	PADAPTER				Adapter,
+	HAL_ODM_VARIABLE		eVariable,
+	PVOID					pValue1,
+	BOOLEAN					bSet)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
+	PDM_ODM_T podmpriv = &pHalData->odmpriv;
+	switch(eVariable){
+		case HAL_ODM_STA_INFO:
+			break;
+		default:
+			break;
+	}
+}
+void rtl8188e_SetHalODMVar(
+	PADAPTER				Adapter,
+	HAL_ODM_VARIABLE		eVariable,
+	PVOID					pValue1,
+	BOOLEAN					bSet)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
+	PDM_ODM_T podmpriv = &pHalData->odmpriv;
+	//_irqL irqL;
+	switch(eVariable){
+		case HAL_ODM_STA_INFO:
+			{	
+				struct sta_info *psta = (struct sta_info *)pValue1;				
+				#ifdef CONFIG_CONCURRENT_MODE	
+				//get Primary adapter's odmpriv
+				if(Adapter->adapter_type > PRIMARY_ADAPTER){
+					pHalData = GET_HAL_DATA(Adapter->pbuddy_adapter);
+					podmpriv = &pHalData->odmpriv;	
+				}
+				#endif				
+				if(bSet){
+					DBG_8192C("### Set STA_(%d) info\n",psta->mac_id);
+					ODM_CmnInfoPtrArrayHook(podmpriv, ODM_CMNINFO_STA_STATUS,psta->mac_id,psta);
+					#if(RATE_ADAPTIVE_SUPPORT==1)
+					ODM_RAInfo_Init(podmpriv,psta->mac_id);
+					#endif
+				}
+				else{
+					DBG_8192C("### Clean STA_(%d) info\n",psta->mac_id);
+					//_enter_critical_bh(&pHalData->odm_stainfo_lock, &irqL);
+					ODM_CmnInfoPtrArrayHook(podmpriv, ODM_CMNINFO_STA_STATUS,psta->mac_id,NULL);
+					
+					//_exit_critical_bh(&pHalData->odm_stainfo_lock, &irqL);
+			            }
+			}
+			break;
+		case HAL_ODM_P2P_STATE:		
+				ODM_CmnInfoUpdate(podmpriv,ODM_CMNINFO_WIFI_DIRECT,bSet);
+			break;
+		case HAL_ODM_WIFI_DISPLAY_STATE:
+				ODM_CmnInfoUpdate(podmpriv,ODM_CMNINFO_WIFI_DISPLAY,bSet);
+			break;
+		default:
+			break;
+	}
+}	
+
+void rtl8188e_clone_haldata(_adapter* dst_adapter, _adapter* src_adapter)
+{
+#ifdef CONFIG_SDIO_HCI
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(dst_adapter);
+	//_thread_hdl_  SdioXmitThread;
+#ifndef CONFIG_SDIO_TX_TASKLET
+	_sema             temp_SdioXmitSema;
+	_sema             temp_SdioXmitTerminateSema;
+#endif
+	//u8                    SdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE];
+	_lock                temp_SdioTxFIFOFreePageLock;
+
+#ifndef CONFIG_SDIO_TX_TASKLET
+	_rtw_memcpy(&temp_SdioXmitSema, &(pHalData->SdioXmitSema), sizeof(_sema));
+	_rtw_memcpy(&temp_SdioXmitTerminateSema, &(pHalData->SdioXmitTerminateSema), sizeof(_sema));
+#endif
+	_rtw_memcpy(&temp_SdioTxFIFOFreePageLock, &(pHalData->SdioTxFIFOFreePageLock), sizeof(_lock));
+
+	_rtw_memcpy(dst_adapter->HalData, src_adapter->HalData, dst_adapter->hal_data_sz);
+
+#ifndef CONFIG_SDIO_TX_TASKLET	
+	_rtw_memcpy(&(pHalData->SdioXmitSema), &temp_SdioXmitSema, sizeof(_sema));
+	_rtw_memcpy(&(pHalData->SdioXmitTerminateSema), &temp_SdioXmitTerminateSema, sizeof(_sema));
+#endif
+	_rtw_memcpy(&(pHalData->SdioTxFIFOFreePageLock), &temp_SdioTxFIFOFreePageLock, sizeof(_lock));	
+
+#else
+	_rtw_memcpy(dst_adapter->HalData, src_adapter->HalData, dst_adapter->hal_data_sz);
+#endif
+
+}
+
+void rtl8188e_start_thread(_adapter *padapter)
+{
+#ifdef CONFIG_SDIO_HCI
+#ifndef CONFIG_SDIO_TX_TASKLET
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+
+	pHalData->SdioXmitThread = kthread_run(rtl8188es_xmit_thread, padapter, "RTWHALXT");
+	if (IS_ERR(pHalData->SdioXmitThread))
+	{
+		RT_TRACE(_module_hal_xmit_c_, _drv_err_, ("%s: start rtl8188es_xmit_thread FAIL!!\n", __FUNCTION__));
+	}
+#endif
+#endif
+}
+
+void rtl8188e_stop_thread(_adapter *padapter)
+{
+#ifdef CONFIG_SDIO_HCI
+#ifndef CONFIG_SDIO_TX_TASKLET
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+
+	// stop xmit_buf_thread
+	if (pHalData->SdioXmitThread ) {
+		_rtw_up_sema(&pHalData->SdioXmitSema);
+		_rtw_down_sema(&pHalData->SdioXmitTerminateSema);
+		pHalData->SdioXmitThread = 0;
+	}
+#endif
+#endif
+}
+void hal_notch_filter_8188e(_adapter *adapter, bool enable)
+{
+	if (enable) {
+		DBG_871X("Enable notch filter\n");
+		rtw_write8(adapter, rOFDM0_RxDSP+1, rtw_read8(adapter, rOFDM0_RxDSP+1) | BIT1);
+	} else {
+		DBG_871X("Disable notch filter\n");
+		rtw_write8(adapter, rOFDM0_RxDSP+1, rtw_read8(adapter, rOFDM0_RxDSP+1) & ~BIT1);
+	}
+}
+void rtl8188e_set_hal_ops(struct hal_ops *pHalFunc)
+{
+	pHalFunc->free_hal_data = &rtl8188e_free_hal_data;
+
+	pHalFunc->dm_init = &rtl8188e_init_dm_priv;
+	pHalFunc->dm_deinit = &rtl8188e_deinit_dm_priv;
+
+	pHalFunc->read_chip_version = &rtl8188e_read_chip_version;
+
+	pHalFunc->set_bwmode_handler = &PHY_SetBWMode8188E;
+	pHalFunc->set_channel_handler = &PHY_SwChnl8188E;
+
+	pHalFunc->hal_dm_watchdog = &rtl8188e_HalDmWatchDog;
+
+	pHalFunc->Add_RateATid = &rtl8188e_Add_RateATid;
+#ifdef CONFIG_CONCURRENT_MODE		
+	pHalFunc->clone_haldata = &rtl8188e_clone_haldata;
+#endif
+	pHalFunc->run_thread= &rtl8188e_start_thread;
+	pHalFunc->cancel_thread= &rtl8188e_stop_thread;
+
+#ifdef CONFIG_ANTENNA_DIVERSITY
+	pHalFunc->AntDivBeforeLinkHandler = &AntDivBeforeLink8188E;
+	pHalFunc->AntDivCompareHandler = &AntDivCompare8188E;
+#endif
+
+	pHalFunc->read_bbreg = &rtl8188e_PHY_QueryBBReg;
+	pHalFunc->write_bbreg = &rtl8188e_PHY_SetBBReg;
+	pHalFunc->read_rfreg = &rtl8188e_PHY_QueryRFReg;
+	pHalFunc->write_rfreg = &rtl8188e_PHY_SetRFReg;
+
+
+	// Efuse related function
+	pHalFunc->EfusePowerSwitch = &rtl8188e_EfusePowerSwitch;
+	pHalFunc->ReadEFuse = &rtl8188e_ReadEFuse;
+	pHalFunc->EFUSEGetEfuseDefinition = &rtl8188e_EFUSE_GetEfuseDefinition;
+	pHalFunc->EfuseGetCurrentSize = &rtl8188e_EfuseGetCurrentSize;
+	pHalFunc->Efuse_PgPacketRead = &rtl8188e_Efuse_PgPacketRead;
+	pHalFunc->Efuse_PgPacketWrite = &rtl8188e_Efuse_PgPacketWrite;
+	pHalFunc->Efuse_WordEnableDataWrite = &rtl8188e_Efuse_WordEnableDataWrite;
+
+#ifdef DBG_CONFIG_ERROR_DETECT
+	pHalFunc->sreset_init_value = &sreset_init_value;
+	pHalFunc->sreset_reset_value = &sreset_reset_value;
+	pHalFunc->silentreset = &sreset_reset;
+	pHalFunc->sreset_xmit_status_check = &rtl8188e_sreset_xmit_status_check;
+	pHalFunc->sreset_linked_status_check  = &rtl8188e_sreset_linked_status_check;
+	pHalFunc->sreset_get_wifi_status  = &sreset_get_wifi_status;
+	pHalFunc->sreset_inprogress= &sreset_inprogress;
+#endif //DBG_CONFIG_ERROR_DETECT
+
+	pHalFunc->GetHalODMVarHandler = &rtl8188e_GetHalODMVar;
+	pHalFunc->SetHalODMVarHandler = &rtl8188e_SetHalODMVar;
+
+#ifdef CONFIG_XMIT_THREAD_MODE
+	pHalFunc->xmit_thread_handler = &hal_xmit_handler;
+#endif
+
+#ifdef CONFIG_IOL
+	pHalFunc->IOL_exec_cmds_sync = &rtl8188e_IOL_exec_cmds_sync;
+#endif
+
+	pHalFunc->hal_notch_filter = &hal_notch_filter_8188e;
+
+}
+
+u8 GetEEPROMSize8188E(PADAPTER padapter)
+{
+	u8 size = 0;
+	u32	cr;
+
+	cr = rtw_read16(padapter, REG_9346CR);
+	// 6: EEPROM used is 93C46, 4: boot from E-Fuse.
+	size = (cr & BOOT_FROM_EEPROM) ? 6 : 4;
+
+	MSG_8192C("EEPROM type is %s\n", size==4 ? "E-FUSE" : "93C46");
+
+	return size;
+}
+
+#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_PCI_HCI)
+//-------------------------------------------------------------------------
+//
+// LLT R/W/Init function
+//
+//-------------------------------------------------------------------------
+s32 _LLTWrite(PADAPTER padapter, u32 address, u32 data)
+{
+	s32	status = _SUCCESS;
+	s32	count = 0;
+	u32	value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
+	u16	LLTReg = REG_LLT_INIT;
+
+
+	rtw_write32(padapter, LLTReg, value);
+
+	//polling
+	do {
+		value = rtw_read32(padapter, LLTReg);
+		if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)) {
+			break;
+		}
+
+		if (count > POLLING_LLT_THRESHOLD) {
+			RT_TRACE(_module_hal_init_c_, _drv_err_, ("Failed to polling write LLT done at address %d!\n", address));
+			status = _FAIL;
+			break;
+		}
+	} while (count++);
+
+	return status;
+}
+
+u8 _LLTRead(PADAPTER padapter, u32 address)
+{
+	s32	count = 0;
+	u32	value = _LLT_INIT_ADDR(address) | _LLT_OP(_LLT_READ_ACCESS);
+	u16	LLTReg = REG_LLT_INIT;
+
+
+	rtw_write32(padapter, LLTReg, value);
+
+	//polling and get value
+	do {
+		value = rtw_read32(padapter, LLTReg);
+		if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)) {
+			return (u8)value;
+		}
+
+		if (count > POLLING_LLT_THRESHOLD) {
+			RT_TRACE(_module_hal_init_c_, _drv_err_, ("Failed to polling read LLT done at address %d!\n", address));
+			break;
+		}
+	} while (count++);
+
+	return 0xFF;
+}
+void Read_LLT_Tab(PADAPTER padapter)
+{
+	u32 addr,next_addr;
+      printk("############### %s ###################\n",__FUNCTION__);
+      for(addr=0;addr<176;addr++)
+      {
+      		next_addr = _LLTRead(padapter,addr);
+             printk("%d->",next_addr);
+             if(((addr+1) %8) ==0)
+             	printk("\n");
+      }
+       printk("\n##################################\n");
+       
+}
+
+s32 InitLLTTable(PADAPTER padapter, u8 txpktbuf_bndy)
+{
+	s32	status = _FAIL;
+	u32	i;
+	u32	Last_Entry_Of_TxPktBuf = LAST_ENTRY_OF_TX_PKT_BUFFER;// 176, 22k
+	HAL_DATA_TYPE *pHalData	= GET_HAL_DATA(padapter);
+
+#if defined(CONFIG_IOL_LLT)
+	if(rtw_IOL_applied(padapter))
+	{		
+		status = iol_InitLLTTable(padapter, txpktbuf_bndy);			
+	}
+	else
+#endif
+	{
+		for (i = 0; i < (txpktbuf_bndy - 1); i++) {
+			status = _LLTWrite(padapter, i, i + 1);
+			if (_SUCCESS != status) {
+				return status;
+			}
+		}
+
+		// end of list
+		status = _LLTWrite(padapter, (txpktbuf_bndy - 1), 0xFF);
+		if (_SUCCESS != status) {
+			return status;
+		}
+
+		// Make the other pages as ring buffer
+		// This ring buffer is used as beacon buffer if we config this MAC as two MAC transfer.
+		// Otherwise used as local loopback buffer.
+		for (i = txpktbuf_bndy; i < Last_Entry_Of_TxPktBuf; i++) {
+			status = _LLTWrite(padapter, i, (i + 1));
+			if (_SUCCESS != status) {
+				return status;
+			}
+		}
+
+		// Let last entry point to the start entry of ring buffer
+		status = _LLTWrite(padapter, Last_Entry_Of_TxPktBuf, txpktbuf_bndy);
+		if (_SUCCESS != status) {
+			return status;
+		}
+	}
+
+	return status;
+}
+#endif
+
+
+void
+Hal_InitPGData88E(PADAPTER	padapter)
+{
+	EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
+//	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	u32			i;
+	u16			value16;
+
+	if(_FALSE == pEEPROM->bautoload_fail_flag)
+	{ // autoload OK.
+		if (is_boot_from_eeprom(padapter))
+		{
+			// Read all Content from EEPROM or EFUSE.
+			for(i = 0; i < HWSET_MAX_SIZE_88E; i += 2)
+			{
+//				value16 = EF2Byte(ReadEEprom(pAdapter, (u2Byte) (i>>1)));
+//				*((u16*)(&PROMContent[i])) = value16;
+			}
+		}
+		else
+		{
+			// Read EFUSE real map to shadow.
+			EFUSE_ShadowMapUpdate(padapter, EFUSE_WIFI, _FALSE);
+		}
+	}
+	else
+	{//autoload fail
+		RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("AutoLoad Fail reported from CR9346!!\n"));
+//		pHalData->AutoloadFailFlag = _TRUE;
+		//update to default value 0xFF
+		if (!is_boot_from_eeprom(padapter))
+			EFUSE_ShadowMapUpdate(padapter, EFUSE_WIFI, _FALSE);
+	}
+}
+
+void
+Hal_EfuseParseIDCode88E(
+	IN	PADAPTER	padapter,
+	IN	u8			*hwinfo
+	)
+{
+	EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
+//	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	u16			EEPROMId;
+
+
+	// Checl 0x8129 again for making sure autoload status!!
+	EEPROMId = le16_to_cpu(*((u16*)hwinfo));
+	if (EEPROMId != RTL_EEPROM_ID)
+	{
+		DBG_8192C("EEPROM ID(%#x) is invalid!!\n", EEPROMId);
+		pEEPROM->bautoload_fail_flag = _TRUE;
+	}
+	else
+	{
+		pEEPROM->bautoload_fail_flag = _FALSE;
+	}
+
+	DBG_871X("EEPROM ID=0x%04x\n", EEPROMId);
+}
+
+static void
+Hal_EEValueCheck(
+	IN		u8		EEType,
+	IN		PVOID		pInValue,
+	OUT		PVOID		pOutValue
+	)
+{
+	switch(EEType)
+	{
+		case EETYPE_TX_PWR:
+			{
+				u8	*pIn, *pOut;
+				pIn = (u8*)pInValue;
+				pOut = (u8*)pOutValue;
+				if(*pIn >= 0 && *pIn <= 63)
+				{
+					*pOut = *pIn;
+				}
+				else
+				{
+					RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("EETYPE_TX_PWR, value=%d is invalid, set to default=0x%x\n",
+						*pIn, EEPROM_Default_TxPowerLevel));
+					*pOut = EEPROM_Default_TxPowerLevel;
+				}
+			}
+			break;
+		default:
+			break;
+	}
+}
+
+static void
+Hal_ReadPowerValueFromPROM_8188E(
+	IN	PADAPTER 		padapter,
+	IN	PTxPowerInfo24G	pwrInfo24G,
+	IN	u8*				PROMContent,
+	IN	BOOLEAN			AutoLoadFail
+	)
+{		
+	u32 rfPath, eeAddr=EEPROM_TX_PWR_INX_88E, group,TxCount=0;
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	
+	_rtw_memset(pwrInfo24G, 0, sizeof(TxPowerInfo24G));
+
+	if(AutoLoadFail)
+	{	
+		for(rfPath = 0 ; rfPath < pHalData->NumTotalRFPath ; rfPath++)
+		{
+			//2.4G default value
+			for(group = 0 ; group < MAX_CHNL_GROUP_24G; group++)
+			{
+				pwrInfo24G->IndexCCK_Base[rfPath][group] =	EEPROM_DEFAULT_24G_INDEX;
+				pwrInfo24G->IndexBW40_Base[rfPath][group] =	EEPROM_DEFAULT_24G_INDEX;
+			}
+			for(TxCount=0;TxCount<MAX_TX_COUNT;TxCount++)
+			{
+				if(TxCount==0)
+				{
+					pwrInfo24G->BW20_Diff[rfPath][0] =	EEPROM_DEFAULT_24G_HT20_DIFF;
+					pwrInfo24G->OFDM_Diff[rfPath][0] =	EEPROM_DEFAULT_24G_OFDM_DIFF;
+				}
+				else
+				{
+					pwrInfo24G->BW20_Diff[rfPath][TxCount] =	EEPROM_DEFAULT_DIFF;
+					pwrInfo24G->BW40_Diff[rfPath][TxCount] =	EEPROM_DEFAULT_DIFF;
+					pwrInfo24G->CCK_Diff[rfPath][TxCount] =	EEPROM_DEFAULT_DIFF;
+					pwrInfo24G->OFDM_Diff[rfPath][TxCount] =	EEPROM_DEFAULT_DIFF;
+				}
+			}	
+			
+			
+		}
+		
+		//pHalData->bNOPG = TRUE;				
+		return;
+	}	
+
+	for(rfPath = 0 ; rfPath < pHalData->NumTotalRFPath ; rfPath++)
+	{
+		//2.4G default value
+		for(group = 0 ; group < MAX_CHNL_GROUP_24G; group++)
+		{
+			//printk(" IndexCCK_Base rfPath:%d group:%d,eeAddr:0x%02x ",rfPath,group,eeAddr);
+			pwrInfo24G->IndexCCK_Base[rfPath][group] =	PROMContent[eeAddr++];
+			//printk(" IndexCCK_Base:%02x \n",pwrInfo24G->IndexCCK_Base[rfPath][group] );
+			if(pwrInfo24G->IndexCCK_Base[rfPath][group] == 0xFF)
+			{
+				pwrInfo24G->IndexCCK_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
+//				pHalData->bNOPG = TRUE; 							
+			}
+		}
+		for(group = 0 ; group < MAX_CHNL_GROUP_24G-1; group++)
+		{
+			//printk(" IndexBW40_Base rfPath:%d group:%d,eeAddr:0x%02x ",rfPath,group,eeAddr);
+			pwrInfo24G->IndexBW40_Base[rfPath][group] =	PROMContent[eeAddr++];
+			//printk(" IndexBW40_Base: %02x \n",pwrInfo24G->IndexBW40_Base[rfPath][group]  );
+			if(pwrInfo24G->IndexBW40_Base[rfPath][group] == 0xFF)
+				pwrInfo24G->IndexBW40_Base[rfPath][group] =	EEPROM_DEFAULT_24G_INDEX;
+		}			
+		for(TxCount=0;TxCount<MAX_TX_COUNT;TxCount++)
+		{
+			if(TxCount==0)
+			{
+				pwrInfo24G->BW40_Diff[rfPath][TxCount] = 0;
+				if(PROMContent[eeAddr] == 0xFF)
+					pwrInfo24G->BW20_Diff[rfPath][TxCount] =	EEPROM_DEFAULT_24G_HT20_DIFF;
+				else
+				{
+					pwrInfo24G->BW20_Diff[rfPath][TxCount] =	(PROMContent[eeAddr]&0xf0)>>4;				
+				 	if(pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT3)		//4bit sign number to 8 bit sign number
+						pwrInfo24G->BW20_Diff[rfPath][TxCount] |= 0xF0;
+				}
+
+				if(PROMContent[eeAddr] == 0xFF)
+					pwrInfo24G->OFDM_Diff[rfPath][TxCount] =	EEPROM_DEFAULT_24G_OFDM_DIFF;				
+				else 
+				{
+					pwrInfo24G->OFDM_Diff[rfPath][TxCount] =	(PROMContent[eeAddr]&0x0f);					
+					if(pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT3)		//4bit sign number to 8 bit sign number
+						pwrInfo24G->OFDM_Diff[rfPath][TxCount] |= 0xF0;
+				}		
+				pwrInfo24G->CCK_Diff[rfPath][TxCount] = 0;
+				eeAddr++;
+			}
+			else
+			{				
+				if(PROMContent[eeAddr] == 0xFF)
+					pwrInfo24G->BW40_Diff[rfPath][TxCount] =	EEPROM_DEFAULT_DIFF;								
+				else 
+				{
+					pwrInfo24G->BW40_Diff[rfPath][TxCount] =	(PROMContent[eeAddr]&0xf0)>>4;				
+					if(pwrInfo24G->BW40_Diff[rfPath][TxCount] & BIT3)		//4bit sign number to 8 bit sign number
+						pwrInfo24G->BW40_Diff[rfPath][TxCount] |= 0xF0;
+				}
+				
+				if(PROMContent[eeAddr] == 0xFF)
+					pwrInfo24G->BW20_Diff[rfPath][TxCount] =	EEPROM_DEFAULT_DIFF;				
+				else 
+				{
+					pwrInfo24G->BW20_Diff[rfPath][TxCount] =	(PROMContent[eeAddr]&0x0f);				
+					if(pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT3)		//4bit sign number to 8 bit sign number
+						pwrInfo24G->BW20_Diff[rfPath][TxCount] |= 0xF0;
+				}
+				eeAddr++;
+				
+				if(PROMContent[eeAddr] == 0xFF)
+					pwrInfo24G->OFDM_Diff[rfPath][TxCount] =	EEPROM_DEFAULT_DIFF;								
+				else 
+				{
+					pwrInfo24G->OFDM_Diff[rfPath][TxCount] =	(PROMContent[eeAddr]&0xf0)>>4;				
+					if(pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT3)		//4bit sign number to 8 bit sign number
+						pwrInfo24G->OFDM_Diff[rfPath][TxCount] |= 0xF0;
+				}
+			
+				if(PROMContent[eeAddr] == 0xFF)
+					pwrInfo24G->CCK_Diff[rfPath][TxCount] =	EEPROM_DEFAULT_DIFF;												
+				else 
+				{
+					pwrInfo24G->CCK_Diff[rfPath][TxCount] =	(PROMContent[eeAddr]&0x0f);				
+					if(pwrInfo24G->CCK_Diff[rfPath][TxCount] & BIT3)		//4bit sign number to 8 bit sign number
+						pwrInfo24G->CCK_Diff[rfPath][TxCount] |= 0xF0;
+				}
+				eeAddr++;
+			}
+		}
+
+	}
+
+
+}
+
+static u8
+Hal_GetChnlGroup(
+	IN	u8 chnl
+	)
+{
+	u8	group=0;
+
+	if (chnl < 3)			// Cjanel 1-3
+		group = 0;
+	else if (chnl < 9)		// Channel 4-9
+		group = 1;
+	else					// Channel 10-14
+		group = 2;
+
+	return group;
+}
+static u8 
+Hal_GetChnlGroup88E(
+	IN	u8 	chnl,
+	OUT u8*	pGroup
+	)
+{
+	u8 bIn24G=_TRUE;
+
+	if(chnl<=14)
+	{
+		bIn24G=_TRUE;
+
+		if (chnl < 3)			// Chanel 1-2
+			*pGroup = 0;
+		else if (chnl < 6)		// Channel 3-5
+			*pGroup = 1;
+		else	 if(chnl <9)		// Channel 6-8
+			*pGroup = 2;
+		else if(chnl <12)		// Channel 9-11
+			*pGroup = 3;
+		else if(chnl <14)		// Channel 12-13
+			*pGroup = 4;
+		else if(chnl ==14)		// Channel 14
+			*pGroup = 5;	
+		else
+		{
+			//RT_TRACE(COMP_EFUSE,DBG_LOUD,("==>Hal_GetChnlGroup88E in 2.4 G, but Channel %d in Group not found \n",chnl));
+		}
+	}
+	else
+	{
+		bIn24G=_FALSE;
+		
+		if (chnl <=40)	
+			*pGroup = 0;
+		else if (chnl <=48)
+			*pGroup = 1;
+		else	 if(chnl <=56)	
+			*pGroup = 2;
+		else if(chnl <=64)	
+			*pGroup = 3;
+		else if(chnl <=104)
+			*pGroup = 4;
+		else if(chnl <=112)
+			*pGroup = 5;	
+		else if(chnl <=120)
+			*pGroup = 5;	
+		else if(chnl <=128)
+			*pGroup = 6;		
+		else if(chnl <=136)
+			*pGroup = 7;		
+		else if(chnl <=144)
+			*pGroup = 8;		
+		else if(chnl <=153)
+			*pGroup = 9;		
+		else if(chnl <=161)
+			*pGroup = 10;		
+		else if(chnl <=177)
+			*pGroup = 11;	
+		else
+		{
+			//RT_TRACE(COMP_EFUSE,DBG_LOUD,("==>Hal_GetChnlGroup88E in 5G, but Channel %d in Group not found \n",chnl));
+		}
+
+	}
+	//RT_TRACE(COMP_EFUSE,DBG_LOUD,("<==Hal_GetChnlGroup88E,  Channel = %d, bIn24G =%d,\n",chnl,bIn24G));
+	return bIn24G;
+}
+
+void Hal_ReadPowerSavingMode88E(
+	PADAPTER		padapter,
+	IN	u8*			hwinfo,
+	IN	BOOLEAN			AutoLoadFail
+	)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	struct pwrctrl_priv *pwrctrlpriv = &padapter->pwrctrlpriv;
+	u8 tmpvalue;
+
+	if(AutoLoadFail){
+		padapter->pwrctrlpriv.bHWPowerdown = _FALSE;
+		padapter->pwrctrlpriv.bSupportRemoteWakeup = _FALSE;
+	}
+	else	{		
+
+		//hw power down mode selection , 0:rf-off / 1:power down
+
+		if(padapter->registrypriv.hwpdn_mode==2)
+			padapter->pwrctrlpriv.bHWPowerdown = (hwinfo[EEPROM_RF_FEATURE_OPTION_88E] & BIT4);
+		else
+			padapter->pwrctrlpriv.bHWPowerdown = padapter->registrypriv.hwpdn_mode;
+				
+		// decide hw if support remote wakeup function
+		// if hw supported, 8051 (SIE) will generate WeakUP signal( D+/D- toggle) when autoresume
+#ifdef CONFIG_USB_HCI
+		padapter->pwrctrlpriv.bSupportRemoteWakeup = (hwinfo[EEPROM_USB_OPTIONAL_FUNCTION0] & BIT1)?_TRUE :_FALSE;
+#endif //CONFIG_USB_HCI
+
+		//if(SUPPORT_HW_RADIO_DETECT(Adapter))	
+			//Adapter->registrypriv.usbss_enable = Adapter->pwrctrlpriv.bSupportRemoteWakeup ;
+		
+		DBG_8192C("%s...bHWPwrPindetect(%x)-bHWPowerdown(%x) ,bSupportRemoteWakeup(%x)\n",__FUNCTION__,
+		padapter->pwrctrlpriv.bHWPwrPindetect,padapter->pwrctrlpriv.bHWPowerdown ,padapter->pwrctrlpriv.bSupportRemoteWakeup);
+
+		DBG_8192C("### PS params=>  power_mgnt(%x),usbss_enable(%x) ###\n",padapter->registrypriv.power_mgnt,padapter->registrypriv.usbss_enable);
+	
+	}
+
+}
+
+void
+Hal_ReadTxPowerInfo88E(
+	IN	PADAPTER 		padapter,
+	IN	u8*				PROMContent,
+	IN	BOOLEAN			AutoLoadFail
+	)
+{	
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	TxPowerInfo24G		pwrInfo24G;
+	u8			rfPath, ch, group, rfPathMax=1;
+	u8			pwr, diff,bIn24G,TxCount;
+
+	Hal_ReadPowerValueFromPROM_8188E(padapter,&pwrInfo24G, PROMContent, AutoLoadFail);
+
+	if(!AutoLoadFail)
+		pHalData->bTXPowerDataReadFromEEPORM = TRUE;		
+
+	//for(rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++)
+	for(rfPath = 0 ; rfPath < pHalData->NumTotalRFPath ; rfPath++)
+	{
+		for(ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++)
+		{
+			bIn24G = Hal_GetChnlGroup88E(ch+1,&group);
+			if(bIn24G)
+			{
+
+				pHalData->Index24G_CCK_Base[rfPath][ch]=pwrInfo24G.IndexCCK_Base[rfPath][group];
+
+				if(ch==(14-1))
+					pHalData->Index24G_BW40_Base[rfPath][ch]=pwrInfo24G.IndexBW40_Base[rfPath][4];
+				else
+					pHalData->Index24G_BW40_Base[rfPath][ch]=pwrInfo24G.IndexBW40_Base[rfPath][group];
+			}
+			
+			if(bIn24G)
+			{
+				DBG_871X("======= Path %d, Channel %d =======\n",rfPath,ch+1 );			
+				DBG_871X("Index24G_CCK_Base[%d][%d] = 0x%x\n",rfPath,ch+1 ,pHalData->Index24G_CCK_Base[rfPath][ch]);
+				DBG_871X("Index24G_BW40_Base[%d][%d] = 0x%x\n",rfPath,ch+1 ,pHalData->Index24G_BW40_Base[rfPath][ch]);			
+			}			
+		}	
+
+		for(TxCount=0;TxCount<MAX_TX_COUNT;TxCount++)
+		{
+			pHalData->CCK_24G_Diff[rfPath][TxCount]=pwrInfo24G.CCK_Diff[rfPath][TxCount];
+			pHalData->OFDM_24G_Diff[rfPath][TxCount]=pwrInfo24G.OFDM_Diff[rfPath][TxCount];
+			pHalData->BW20_24G_Diff[rfPath][TxCount]=pwrInfo24G.BW20_Diff[rfPath][TxCount];
+			pHalData->BW40_24G_Diff[rfPath][TxCount]=pwrInfo24G.BW40_Diff[rfPath][TxCount];
+#if DBG			
+			DBG_871X("======= TxCount %d =======\n",TxCount );	
+			DBG_871X("CCK_24G_Diff[%d][%d]= %d\n",rfPath,TxCount,pHalData->CCK_24G_Diff[rfPath][TxCount]);
+			DBG_871X("OFDM_24G_Diff[%d][%d]= %d\n",rfPath,TxCount,pHalData->OFDM_24G_Diff[rfPath][TxCount]);
+			DBG_871X("BW20_24G_Diff[%d][%d]= %d\n",rfPath,TxCount,pHalData->BW20_24G_Diff[rfPath][TxCount]);
+			DBG_871X("BW40_24G_Diff[%d][%d]= %d\n",rfPath,TxCount,pHalData->BW40_24G_Diff[rfPath][TxCount]);
+#endif							
+		}
+	}
+
+	
+	// 2010/10/19 MH Add Regulator recognize for CU.
+	if(!AutoLoadFail)
+	{
+		struct registry_priv  *registry_par = &padapter->registrypriv;
+		if( registry_par->regulatory_tid == 0xff){			
+			if(PROMContent[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)
+				pHalData->EEPROMRegulatory = (EEPROM_DEFAULT_BOARD_OPTION&0x7);	//bit0~2
+			else
+				pHalData->EEPROMRegulatory = (PROMContent[EEPROM_RF_BOARD_OPTION_88E]&0x7);	//bit0~2
+		}else{
+			pHalData->EEPROMRegulatory = registry_par->regulatory_tid;
+		}
+	}
+	else
+	{
+		pHalData->EEPROMRegulatory = 0;
+	}
+	DBG_871X("EEPROMRegulatory = 0x%x\n", pHalData->EEPROMRegulatory);
+
+}
+
+
+VOID
+Hal_EfuseParseXtal_8188E(
+	IN	PADAPTER		pAdapter,
+	IN	u8*			hwinfo,
+	IN	BOOLEAN		AutoLoadFail
+	)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
+
+	if(!AutoLoadFail)
+	{
+		pHalData->CrystalCap = hwinfo[EEPROM_XTAL_88E];
+		if(pHalData->CrystalCap == 0xFF)
+			pHalData->CrystalCap = EEPROM_Default_CrystalCap_88E;	
+	}
+	else
+	{
+		pHalData->CrystalCap = EEPROM_Default_CrystalCap_88E;
+	}
+	DBG_871X("CrystalCap: 0x%2x\n", pHalData->CrystalCap);
+}
+
+void
+Hal_EfuseParseBoardType88E(
+	IN	PADAPTER		pAdapter,
+	IN	u8*				hwinfo,
+	IN	BOOLEAN			AutoLoadFail
+	)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
+
+	if (!AutoLoadFail)
+		pHalData->BoardType = ((hwinfo[EEPROM_RF_BOARD_OPTION_88E]&0xE0)>>5);
+	else
+		pHalData->BoardType = 0;
+	DBG_871X("Board Type: 0x%2x\n", pHalData->BoardType);
+}
+
+void
+Hal_EfuseParseEEPROMVer88E(
+	IN	PADAPTER		padapter,
+	IN	u8*			hwinfo,
+	IN	BOOLEAN			AutoLoadFail
+	)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+
+	if(!AutoLoadFail){		
+		pHalData->EEPROMVersion = hwinfo[EEPROM_VERSION_88E];
+		if(pHalData->EEPROMVersion == 0xFF)
+			pHalData->EEPROMVersion = EEPROM_Default_Version;				
+	}
+	else{
+		pHalData->EEPROMVersion = 1;
+	}
+	RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Hal_EfuseParseEEPROMVer(), EEVer = %d\n",
+		pHalData->EEPROMVersion));
+}
+
+void
+rtl8188e_EfuseParseChnlPlan(
+	IN	PADAPTER		padapter,
+	IN	u8*			hwinfo,
+	IN	BOOLEAN			AutoLoadFail
+	)
+{
+	padapter->mlmepriv.ChannelPlan = hal_com_get_channel_plan(
+		padapter
+		, hwinfo?hwinfo[EEPROM_ChannelPlan_88E]:0xFF
+		, padapter->registrypriv.channel_plan
+		, RT_CHANNEL_DOMAIN_WORLD_WIDE_13
+		, AutoLoadFail
+	);
+
+	DBG_871X("mlmepriv.ChannelPlan = 0x%02x\n", padapter->mlmepriv.ChannelPlan);
+}
+
+void
+Hal_EfuseParseCustomerID88E(
+	IN	PADAPTER		padapter,
+	IN	u8*			hwinfo,
+	IN	BOOLEAN			AutoLoadFail
+	)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+
+	if (!AutoLoadFail)
+	{
+		pHalData->EEPROMCustomerID = hwinfo[EEPROM_CUSTOMERID_88E];
+		//pHalData->EEPROMSubCustomerID = hwinfo[EEPROM_CUSTOMERID_88E];
+	}
+	else
+	{
+		pHalData->EEPROMCustomerID = 0;
+		pHalData->EEPROMSubCustomerID = 0;
+	}
+	DBG_871X("EEPROM Customer ID: 0x%2x\n", pHalData->EEPROMCustomerID);
+	//DBG_871X("EEPROM SubCustomer ID: 0x%02x\n", pHalData->EEPROMSubCustomerID);
+}
+
+
+void
+Hal_ReadAntennaDiversity88E(
+	IN	PADAPTER		pAdapter,
+	IN	u8*				PROMContent,
+	IN	BOOLEAN			AutoLoadFail
+	)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
+	struct registry_priv	*registry_par = &pAdapter->registrypriv;	
+
+	if(!AutoLoadFail)
+	{	
+		// Antenna Diversity setting.
+		if(registry_par->antdiv_cfg == 2)// 2:By EFUSE
+		{
+			pHalData->AntDivCfg = (PROMContent[EEPROM_RF_BOARD_OPTION_88E]&0x18)>>3;
+			if(PROMContent[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)			
+				pHalData->AntDivCfg = (EEPROM_DEFAULT_BOARD_OPTION&0x18)>>3;;				
+		}
+		else
+		{
+			pHalData->AntDivCfg = registry_par->antdiv_cfg ;  // 0:OFF , 1:ON, 2:By EFUSE
+		}
+
+		if(registry_par->antdiv_type == 0)// If TRxAntDivType is AUTO in advanced setting, use EFUSE value instead.
+		{	
+        		pHalData->TRxAntDivType = PROMContent[EEPROM_RF_ANTENNA_OPT_88E];
+        		if (pHalData->TRxAntDivType == 0xFF)
+        	    		pHalData->TRxAntDivType = CG_TRX_HW_ANTDIV; // For 88EE, 1Tx and 1RxCG are fixed.(1Ant, Tx and RxCG are both on aux port)
+		}
+		else{
+			pHalData->TRxAntDivType = registry_par->antdiv_type ;
+		}
+			
+		if (pHalData->TRxAntDivType == CG_TRX_HW_ANTDIV || pHalData->TRxAntDivType == CGCS_RX_HW_ANTDIV)
+			pHalData->AntDivCfg = 1; // 0xC1[3] is ignored.
+	}
+	else
+	{
+		pHalData->AntDivCfg = 0;
+        	pHalData->TRxAntDivType = pHalData->TRxAntDivType; // The value in the driver setting of device manager.
+	}
+	
+	DBG_871X("EEPROM : AntDivCfg = %x, TRxAntDivType = %x\n",pHalData->AntDivCfg, pHalData->TRxAntDivType);
+
+
+}
+
+void
+Hal_ReadThermalMeter_88E(
+	IN	PADAPTER	Adapter,	
+	IN	u8* 			PROMContent,
+	IN	BOOLEAN 	AutoloadFail
+	)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
+	u1Byte			tempval;
+
+	//
+	// ThermalMeter from EEPROM
+	//
+	if(!AutoloadFail)	
+		pHalData->EEPROMThermalMeter = PROMContent[EEPROM_THERMAL_METER_88E];
+	else
+		pHalData->EEPROMThermalMeter = EEPROM_Default_ThermalMeter_88E;
+//	pHalData->EEPROMThermalMeter = (tempval&0x1f);	//[4:0]
+
+	if(pHalData->EEPROMThermalMeter == 0xff || AutoloadFail)
+	{
+		pHalData->bAPKThermalMeterIgnore = _TRUE;
+		pHalData->EEPROMThermalMeter = EEPROM_Default_ThermalMeter_88E;		
+	}
+
+	//pHalData->ThermalMeter[0] = pHalData->EEPROMThermalMeter;	
+	DBG_871X("ThermalMeter = 0x%x\n", pHalData->EEPROMThermalMeter);	
+
+}
+
+
+void
+Hal_InitChannelPlan(
+	IN		PADAPTER	padapter
+	)
+{
+#if 0
+	PMGNT_INFO		pMgntInfo = &(padapter->MgntInfo);
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+
+	if((pMgntInfo->RegChannelPlan >= RT_CHANNEL_DOMAIN_MAX) || (pHalData->EEPROMChannelPlan & EEPROM_CHANNEL_PLAN_BY_HW_MASK))
+	{
+		pMgntInfo->ChannelPlan = hal_MapChannelPlan8192C(padapter, (pHalData->EEPROMChannelPlan & (~(EEPROM_CHANNEL_PLAN_BY_HW_MASK))));
+		pMgntInfo->bChnlPlanFromHW = (pHalData->EEPROMChannelPlan & EEPROM_CHANNEL_PLAN_BY_HW_MASK) ? TRUE : FALSE; // User cannot change  channel plan.
+	}
+	else
+	{
+		pMgntInfo->ChannelPlan = (RT_CHANNEL_DOMAIN)pMgntInfo->RegChannelPlan;
+	}
+
+	switch(pMgntInfo->ChannelPlan)
+	{
+		case RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN:
+		{
+			PRT_DOT11D_INFO	pDot11dInfo = GET_DOT11D_INFO(pMgntInfo);
+
+			pDot11dInfo->bEnabled = TRUE;
+		}
+			RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("ReadAdapterInfo8187(): Enable dot11d when RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN!\n"));
+			break;
+
+		default: //for MacOSX compiler warning.
+			break;
+	}
+
+	RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("RegChannelPlan(%d) EEPROMChannelPlan(%d)", pMgntInfo->RegChannelPlan, pHalData->EEPROMChannelPlan));
+	RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Mgnt ChannelPlan = %d\n" , pMgntInfo->ChannelPlan));
+#endif
+}
+
+BOOLEAN HalDetectPwrDownMode88E(PADAPTER Adapter)
+{
+	u8 tmpvalue = 0;
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+	struct pwrctrl_priv *pwrctrlpriv = &Adapter->pwrctrlpriv;
+
+	EFUSE_ShadowRead(Adapter, 1, EEPROM_RF_FEATURE_OPTION_88E, (u32 *)&tmpvalue);
+
+	// 2010/08/25 MH INF priority > PDN Efuse value.
+	if(tmpvalue & BIT(4) && pwrctrlpriv->reg_pdnmode)
+	{
+		pHalData->pwrdown = _TRUE;
+	}
+	else
+	{
+		pHalData->pwrdown = _FALSE;
+	}
+
+	DBG_8192C("HalDetectPwrDownMode(): PDN=%d\n", pHalData->pwrdown);
+
+	return pHalData->pwrdown;
+}	// HalDetectPwrDownMode
+
+#ifdef CONFIG_WOWLAN
+void Hal_DetectWoWMode(PADAPTER pAdapter)
+{
+	pAdapter->pwrctrlpriv.bSupportRemoteWakeup = _TRUE;
+	DBG_871X("%s\n", __func__);
+}
+#endif
+
+#ifdef CONFIG_RF_GAIN_OFFSET
+void Hal_ReadRFGainOffset(
+	IN		PADAPTER		Adapter,
+	IN		u8*				PROMContent,
+	IN		BOOLEAN			AutoloadFail)
+{
+	u8 buff[EFUSE_MAX_SIZE];
+	u32 res;
+	//
+	// BB_RF Gain Offset from EEPROM
+	//
+	res = rtw_efuse_access(Adapter, _FALSE, 0, EFUSE_MAX_SIZE, buff);
+	if(!AutoloadFail && res != _FAIL)
+		Adapter->eeprompriv.EEPROMRFGainOffset = buff[EEPROM_RF_GAIN_OFFSET_88E];
+	else
+		Adapter->eeprompriv.EEPROMRFGainOffset = EEPROM_Default_RFGainOffset;
+	DBG_871X("EEPRORFGainOffset = 0x%02x\n", Adapter->eeprompriv.EEPROMRFGainOffset);
+}
+#endif //CONFIG_RF_GAIN_OFFSET
+
+//====================================================================================
+//
+// 20100209 Joseph:
+// This function is used only for 92C to set REG_BCN_CTRL(0x550) register.
+// We just reserve the value of the register in variable pHalData->RegBcnCtrlVal and then operate
+// the value of the register via atomic operation.
+// This prevents from race condition when setting this register.
+// The value of pHalData->RegBcnCtrlVal is initialized in HwConfigureRTL8192CE() function.
+//
+void SetBcnCtrlReg(
+	PADAPTER	padapter,
+	u8		SetBits,
+	u8		ClearBits)
+{
+	PHAL_DATA_TYPE pHalData;
+
+
+	pHalData = GET_HAL_DATA(padapter);
+
+	pHalData->RegBcnCtrlVal |= SetBits;
+	pHalData->RegBcnCtrlVal &= ~ClearBits;
+
+#if 0
+//#ifdef CONFIG_SDIO_HCI
+	if (pHalData->sdio_himr & (SDIO_HIMR_TXBCNOK_MSK | SDIO_HIMR_TXBCNERR_MSK))
+		pHalData->RegBcnCtrlVal |= EN_TXBCN_RPT;
+#endif
+
+	rtw_write8(padapter, REG_BCN_CTRL, (u8)pHalData->RegBcnCtrlVal);
+}
+
+
diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/rtl8188e_mp.c b/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/rtl8188e_mp.c
new file mode 100755
index 00000000..15125702
--- /dev/null
+++ b/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/rtl8188e_mp.c
@@ -0,0 +1,1140 @@
+/******************************************************************************

+ *

+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.

+ *

+ * This program is free software; you can redistribute it and/or modify it

+ * under the terms of version 2 of the GNU General Public License as

+ * published by the Free Software Foundation.

+ *

+ * This program is distributed in the hope that it will be useful, but WITHOUT

+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for

+ * more details.

+ *

+ * You should have received a copy of the GNU General Public License along with

+ * this program; if not, write to the Free Software Foundation, Inc.,

+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA

+ *

+ *

+ ******************************************************************************/

+#define _RTL8188E_MP_C_

+#ifdef CONFIG_MP_INCLUDED

+

+#include <drv_types.h>

+#include <rtw_mp.h>

+

+#include <rtl8188e_hal.h>

+#include <rtl8188e_dm.h>

+

+

+s32 Hal_SetPowerTracking(PADAPTER padapter, u8 enable)

+{

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);

+	

+	struct dm_priv	*pdmpriv = &pHalData->dmpriv;

+	PDM_ODM_T		pDM_Odm = &(pHalData->odmpriv);

+

+

+	if (!netif_running(padapter->pnetdev)) {

+		RT_TRACE(_module_mp_, _drv_warning_, ("SetPowerTracking! Fail: interface not opened!\n"));

+		return _FAIL;

+	}

+

+	if (check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {

+		RT_TRACE(_module_mp_, _drv_warning_, ("SetPowerTracking! Fail: not in MP mode!\n"));

+		return _FAIL;

+	}

+

+	if (enable)

+	{

+			pDM_Odm->RFCalibrateInfo.bTXPowerTracking = _TRUE;

+	}

+	else

+		pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit= _FALSE;

+

+	return _SUCCESS;

+}

+

+void Hal_GetPowerTracking(PADAPTER padapter, u8 *enable)

+{

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);

+	

+	struct dm_priv	*pdmpriv = &pHalData->dmpriv;

+	PDM_ODM_T		pDM_Odm = &(pHalData->odmpriv);

+

+

+	*enable = pDM_Odm->RFCalibrateInfo.TxPowerTrackControl;

+}

+

+static void Hal_disable_dm(PADAPTER padapter)

+{

+	u8 v8;

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);

+

+	struct dm_priv	*pdmpriv = &pHalData->dmpriv;

+	PDM_ODM_T		pDM_Odm = &(pHalData->odmpriv);

+

+

+	//3 1. disable firmware dynamic mechanism

+	// disable Power Training, Rate Adaptive

+	v8 = rtw_read8(padapter, REG_BCN_CTRL);

+	v8 &= ~EN_BCN_FUNCTION;

+	rtw_write8(padapter, REG_BCN_CTRL, v8);

+

+	//3 2. disable driver dynamic mechanism

+	// disable Dynamic Initial Gain

+	// disable High Power

+	// disable Power Tracking

+	Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, _FALSE);

+

+	// enable APK, LCK and IQK but disable power tracking

+	pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _FALSE;

+	Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, _TRUE);

+}

+

+/*-----------------------------------------------------------------------------

+ * Function:	mpt_SwitchRfSetting

+ *

+ * Overview:	Change RF Setting when we siwthc channel/rate/BW for MP.

+ *

+ * Input:       IN	PADAPTER				pAdapter

+ *

+ * Output:      NONE

+ *

+ * Return:      NONE

+ *

+ * Revised History:

+ * When			Who		Remark

+ * 01/08/2009	MHC		Suggestion from SD3 Willis for 92S series.

+ * 01/09/2009	MHC		Add CCK modification for 40MHZ. Suggestion from SD3.

+ *

+ *---------------------------------------------------------------------------*/

+void Hal_mpt_SwitchRfSetting(PADAPTER pAdapter)

+{	

+	//HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);

+	struct mp_priv	*pmp = &pAdapter->mppriv;

+	u1Byte				ChannelToSw = pmp->channel;

+	ULONG				ulRateIdx = pmp->rateidx;

+	ULONG				ulbandwidth = pmp->bandwidth;

+	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(pAdapter);

+	

+	// <20120525, Kordan> Dynamic mechanism for APK, asked by Dennis.

+		pmp->MptCtx.backup0x52_RF_A = (u1Byte)PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0);

+		pmp->MptCtx.backup0x52_RF_B = (u1Byte)PHY_QueryRFReg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0);

+		PHY_SetRFReg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xD);

+		PHY_SetRFReg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xD);

+

+	return ;

+}

+/*---------------------------hal\rtl8192c\MPT_Phy.c---------------------------*/

+

+/*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/

+void Hal_MPT_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)

+{

+	u32		TempVal = 0, TempVal2 = 0, TempVal3 = 0;

+	u32		CurrCCKSwingVal = 0, CCKSwingIndex = 12;

+	u8		i;

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);

+

+

+	// get current cck swing value and check 0xa22 & 0xa23 later to match the table.

+	CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);

+

+	if (!bInCH14)

+	{

+		// Readback the current bb cck swing value and compare with the table to

+		// get the current swing index

+		for (i = 0; i < CCK_TABLE_SIZE; i++)

+		{

+			if (((CurrCCKSwingVal&0xff) == (u32)CCKSwingTable_Ch1_Ch13[i][0]) &&

+				(((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch1_Ch13[i][1]))

+			{

+				CCKSwingIndex = i;

+//				RT_TRACE(COMP_INIT, DBG_LOUD,("Ch1~13, Current reg0x%x = 0x%lx, CCKSwingIndex=0x%x\n",

+//					(rCCK0_TxFilter1+2), CurrCCKSwingVal, CCKSwingIndex));

+				break;

+			}

+		}

+

+		//Write 0xa22 0xa23

+		TempVal = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][0] +

+				(CCKSwingTable_Ch1_Ch13[CCKSwingIndex][1]<<8) ;

+

+

+		//Write 0xa24 ~ 0xa27

+		TempVal2 = 0;

+		TempVal2 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][2] +

+				(CCKSwingTable_Ch1_Ch13[CCKSwingIndex][3]<<8) +

+				(CCKSwingTable_Ch1_Ch13[CCKSwingIndex][4]<<16 )+

+				(CCKSwingTable_Ch1_Ch13[CCKSwingIndex][5]<<24);

+

+		//Write 0xa28  0xa29

+		TempVal3 = 0;

+		TempVal3 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][6] +

+				(CCKSwingTable_Ch1_Ch13[CCKSwingIndex][7]<<8) ;

+	}

+	else

+	{

+		for (i = 0; i < CCK_TABLE_SIZE; i++)

+		{

+			if (((CurrCCKSwingVal&0xff) == (u32)CCKSwingTable_Ch14[i][0]) &&

+				(((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch14[i][1]))

+			{

+				CCKSwingIndex = i;

+//				RT_TRACE(COMP_INIT, DBG_LOUD,("Ch14, Current reg0x%x = 0x%lx, CCKSwingIndex=0x%x\n",

+//					(rCCK0_TxFilter1+2), CurrCCKSwingVal, CCKSwingIndex));

+				break;

+			}

+		}

+

+		//Write 0xa22 0xa23

+		TempVal = CCKSwingTable_Ch14[CCKSwingIndex][0] +

+				(CCKSwingTable_Ch14[CCKSwingIndex][1]<<8) ;

+

+		//Write 0xa24 ~ 0xa27

+		TempVal2 = 0;

+		TempVal2 = CCKSwingTable_Ch14[CCKSwingIndex][2] +

+				(CCKSwingTable_Ch14[CCKSwingIndex][3]<<8) +

+				(CCKSwingTable_Ch14[CCKSwingIndex][4]<<16 )+

+				(CCKSwingTable_Ch14[CCKSwingIndex][5]<<24);

+

+		//Write 0xa28  0xa29

+		TempVal3 = 0;

+		TempVal3 = CCKSwingTable_Ch14[CCKSwingIndex][6] +

+				(CCKSwingTable_Ch14[CCKSwingIndex][7]<<8) ;

+	}

+

+	write_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord, TempVal);

+	write_bbreg(Adapter, rCCK0_TxFilter2, bMaskDWord, TempVal2);

+	write_bbreg(Adapter, rCCK0_DebugPort, bMaskLWord, TempVal3);

+}

+

+void Hal_MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, BOOLEAN beven)

+{

+	s32		TempCCk;

+	u8		CCK_index, CCK_index_old;

+	u8		Action = 0;	//0: no action, 1: even->odd, 2:odd->even

+	u8		TimeOut = 100;

+	s32		i = 0;

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);

+	PMPT_CONTEXT	pMptCtx = &pAdapter->mppriv.MptCtx;

+

+	struct dm_priv	*pdmpriv = &pHalData->dmpriv;

+	PDM_ODM_T		pDM_Odm = &(pHalData->odmpriv);

+

+

+	if (!IS_92C_SERIAL(pHalData->VersionID))

+		return;

+#if 0

+	while(PlatformAtomicExchange(&Adapter->IntrCCKRefCount, TRUE) == TRUE)

+	{

+		PlatformSleepUs(100);

+		TimeOut--;

+		if(TimeOut <= 0)

+		{

+			RTPRINT(FINIT, INIT_TxPower,

+			 ("!!!MPT_CCKTxPowerAdjustbyIndex Wait for check CCK gain index too long!!!\n" ));

+			break;

+		}

+	}

+#endif

+	if (beven && !pMptCtx->bMptIndexEven)	//odd->even

+	{

+		Action = 2;

+		pMptCtx->bMptIndexEven = _TRUE;

+	}

+	else if (!beven && pMptCtx->bMptIndexEven)	//even->odd

+	{

+		Action = 1;

+		pMptCtx->bMptIndexEven = _FALSE;

+	}

+

+	if (Action != 0)

+	{

+		//Query CCK default setting From 0xa24

+		TempCCk = read_bbreg(pAdapter, rCCK0_TxFilter2, bMaskDWord) & bMaskCCK;

+		for (i = 0; i < CCK_TABLE_SIZE; i++)

+		{

+			if (pDM_Odm->RFCalibrateInfo.bCCKinCH14)

+			{

+				if (_rtw_memcmp((void*)&TempCCk, (void*)&CCKSwingTable_Ch14[i][2], 4) == _TRUE)

+				{

+					CCK_index_old = (u8) i;

+//					RTPRINT(FINIT, INIT_TxPower,("MPT_CCKTxPowerAdjustbyIndex: Initial reg0x%x = 0x%lx, CCK_index=0x%x, ch 14 %d\n",

+//						rCCK0_TxFilter2, TempCCk, CCK_index_old, pHalData->bCCKinCH14));

+					break;

+				}

+			}

+			else

+			{

+				if (_rtw_memcmp((void*)&TempCCk, (void*)&CCKSwingTable_Ch1_Ch13[i][2], 4) == _TRUE)

+				{

+					CCK_index_old = (u8) i;

+//					RTPRINT(FINIT, INIT_TxPower,("MPT_CCKTxPowerAdjustbyIndex: Initial reg0x%x = 0x%lx, CCK_index=0x%x, ch14 %d\n",

+//						rCCK0_TxFilter2, TempCCk, CCK_index_old, pHalData->bCCKinCH14));

+					break;

+				}

+			}

+		}

+

+		if (Action == 1)

+			CCK_index = CCK_index_old - 1;

+		else

+			CCK_index = CCK_index_old + 1;

+

+//		RTPRINT(FINIT, INIT_TxPower,("MPT_CCKTxPowerAdjustbyIndex: new CCK_index=0x%x\n",

+//			 CCK_index));

+

+		//Adjust CCK according to gain index

+		if (!pDM_Odm->RFCalibrateInfo.bCCKinCH14) {

+			rtw_write8(pAdapter, 0xa22, CCKSwingTable_Ch1_Ch13[CCK_index][0]);

+			rtw_write8(pAdapter, 0xa23, CCKSwingTable_Ch1_Ch13[CCK_index][1]);

+			rtw_write8(pAdapter, 0xa24, CCKSwingTable_Ch1_Ch13[CCK_index][2]);

+			rtw_write8(pAdapter, 0xa25, CCKSwingTable_Ch1_Ch13[CCK_index][3]);

+			rtw_write8(pAdapter, 0xa26, CCKSwingTable_Ch1_Ch13[CCK_index][4]);

+			rtw_write8(pAdapter, 0xa27, CCKSwingTable_Ch1_Ch13[CCK_index][5]);

+			rtw_write8(pAdapter, 0xa28, CCKSwingTable_Ch1_Ch13[CCK_index][6]);

+			rtw_write8(pAdapter, 0xa29, CCKSwingTable_Ch1_Ch13[CCK_index][7]);

+		} else {

+			rtw_write8(pAdapter, 0xa22, CCKSwingTable_Ch14[CCK_index][0]);

+			rtw_write8(pAdapter, 0xa23, CCKSwingTable_Ch14[CCK_index][1]);

+			rtw_write8(pAdapter, 0xa24, CCKSwingTable_Ch14[CCK_index][2]);

+			rtw_write8(pAdapter, 0xa25, CCKSwingTable_Ch14[CCK_index][3]);

+			rtw_write8(pAdapter, 0xa26, CCKSwingTable_Ch14[CCK_index][4]);

+			rtw_write8(pAdapter, 0xa27, CCKSwingTable_Ch14[CCK_index][5]);

+			rtw_write8(pAdapter, 0xa28, CCKSwingTable_Ch14[CCK_index][6]);

+			rtw_write8(pAdapter, 0xa29, CCKSwingTable_Ch14[CCK_index][7]);

+		}

+	}

+#if 0

+	RTPRINT(FINIT, INIT_TxPower,

+	("MPT_CCKTxPowerAdjustbyIndex 0xa20=%x\n", PlatformEFIORead4Byte(Adapter, 0xa20)));

+

+	PlatformAtomicExchange(&Adapter->IntrCCKRefCount, FALSE);

+#endif

+}

+/*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/

+

+/*

+ * SetChannel

+ * Description

+ *	Use H2C command to change channel,

+ *	not only modify rf register, but also other setting need to be done.

+ */

+void Hal_SetChannel(PADAPTER pAdapter)

+{

+#if 0

+	struct mp_priv *pmp = &pAdapter->mppriv;

+

+//	SelectChannel(pAdapter, pmp->channel);

+	set_channel_bwmode(pAdapter, pmp->channel, pmp->channel_offset, pmp->bandwidth);

+#else

+	u8 		eRFPath;

+

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);

+	struct mp_priv	*pmp = &pAdapter->mppriv;

+	struct dm_priv	*pdmpriv = &pHalData->dmpriv;

+	PDM_ODM_T		pDM_Odm = &(pHalData->odmpriv);

+	

+	u8		channel = pmp->channel;

+	u8		bandwidth = pmp->bandwidth;

+	u8		rate = pmp->rateidx;

+

+

+	// set RF channel register

+	for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++)

+	{

+      		if(IS_HARDWARE_TYPE_8192D(pAdapter))

+			_write_rfreg(pAdapter, (RF_RADIO_PATH_E)eRFPath, ODM_CHANNEL, 0xFF, channel);

+		else

+			_write_rfreg(pAdapter, eRFPath, ODM_CHANNEL, 0x3FF, channel);

+	}

+	Hal_mpt_SwitchRfSetting(pAdapter);

+

+	SelectChannel(pAdapter, channel);

+

+	if (pHalData->CurrentChannel == 14 && !pDM_Odm->RFCalibrateInfo.bCCKinCH14) {

+		pDM_Odm->RFCalibrateInfo.bCCKinCH14 = _TRUE;

+		Hal_MPT_CCKTxPowerAdjust(pAdapter, pDM_Odm->RFCalibrateInfo.bCCKinCH14);

+	}

+	else if (pHalData->CurrentChannel != 14 && pDM_Odm->RFCalibrateInfo.bCCKinCH14) {

+		pDM_Odm->RFCalibrateInfo.bCCKinCH14 = _FALSE;

+		Hal_MPT_CCKTxPowerAdjust(pAdapter, pDM_Odm->RFCalibrateInfo.bCCKinCH14);

+	}

+

+#endif

+}

+

+/*

+ * Notice

+ *	Switch bandwitdth may change center frequency(channel)

+ */

+void Hal_SetBandwidth(PADAPTER pAdapter)

+{

+	struct mp_priv *pmp = &pAdapter->mppriv;

+

+

+	SetBWMode(pAdapter, pmp->bandwidth, pmp->prime_channel_offset);

+	Hal_mpt_SwitchRfSetting(pAdapter);

+}

+

+void Hal_SetCCKTxPower(PADAPTER pAdapter, u8 *TxPower)

+{

+	u32 tmpval = 0;

+

+

+	// rf-A cck tx power

+	write_bbreg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, TxPower[RF_PATH_A]);

+	tmpval = (TxPower[RF_PATH_A]<<16) | (TxPower[RF_PATH_A]<<8) | TxPower[RF_PATH_A];

+	write_bbreg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);

+

+	// rf-B cck tx power

+	write_bbreg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, TxPower[RF_PATH_B]);

+	tmpval = (TxPower[RF_PATH_B]<<16) | (TxPower[RF_PATH_B]<<8) | TxPower[RF_PATH_B];

+	write_bbreg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval);

+

+	RT_TRACE(_module_mp_, _drv_notice_,

+		 ("-SetCCKTxPower: A[0x%02x] B[0x%02x]\n",

+		  TxPower[RF_PATH_A], TxPower[RF_PATH_B]));

+}

+

+void Hal_SetOFDMTxPower(PADAPTER pAdapter, u8 *TxPower)

+{

+	u32 TxAGC = 0;

+	u8 tmpval = 0;

+	PMPT_CONTEXT	pMptCtx = &pAdapter->mppriv.MptCtx;

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);

+

+

+	// HT Tx-rf(A)

+	tmpval = TxPower[RF_PATH_A];

+	TxAGC = (tmpval<<24) | (tmpval<<16) | (tmpval<<8) | tmpval;

+

+	write_bbreg(pAdapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC);

+	write_bbreg(pAdapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC);

+	write_bbreg(pAdapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC);

+	write_bbreg(pAdapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC);

+	write_bbreg(pAdapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC);

+	write_bbreg(pAdapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC);

+

+	// HT Tx-rf(B)

+	tmpval = TxPower[RF_PATH_B];

+	TxAGC = (tmpval<<24) | (tmpval<<16) | (tmpval<<8) | tmpval;

+

+	write_bbreg(pAdapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC);

+	write_bbreg(pAdapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC);

+	write_bbreg(pAdapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC);

+	write_bbreg(pAdapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC);

+	write_bbreg(pAdapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC);

+	write_bbreg(pAdapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC);

+

+}

+

+void Hal_SetAntennaPathPower(PADAPTER pAdapter)

+{

+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);

+	u8 TxPowerLevel[MAX_RF_PATH_NUMS];

+	u8 rfPath;

+

+	TxPowerLevel[RF_PATH_A] = pAdapter->mppriv.txpoweridx;

+	TxPowerLevel[RF_PATH_B] = pAdapter->mppriv.txpoweridx_b;

+

+	switch (pAdapter->mppriv.antenna_tx)

+	{

+		case ANTENNA_A:

+		default:

+			rfPath = RF_PATH_A;

+			break;

+		case ANTENNA_B:

+			rfPath = RF_PATH_B;

+			break;

+		case ANTENNA_C:

+			rfPath = RF_PATH_C;

+			break;

+	}

+

+	switch (pHalData->rf_chip)

+	{

+		case RF_8225:

+		case RF_8256:

+		case RF_6052:

+			Hal_SetCCKTxPower(pAdapter, TxPowerLevel);

+			if (pAdapter->mppriv.rateidx < MPT_RATE_6M)	// CCK rate

+				Hal_MPT_CCKTxPowerAdjustbyIndex(pAdapter, TxPowerLevel[rfPath]%2 == 0);

+			Hal_SetOFDMTxPower(pAdapter, TxPowerLevel);

+			break;

+

+		default:

+			break;

+	}

+}

+

+void Hal_SetTxPower(PADAPTER pAdapter)

+{

+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);

+	u8 TxPower = pAdapter->mppriv.txpoweridx;

+	u8 TxPowerLevel[MAX_RF_PATH_NUMS];

+	u8 rf, rfPath;

+

+	for (rf = 0; rf < MAX_RF_PATH_NUMS; rf++) {

+		TxPowerLevel[rf] = TxPower;

+	}

+

+	switch (pAdapter->mppriv.antenna_tx)

+	{

+		case ANTENNA_A:

+		default:

+			rfPath = RF_PATH_A;

+			break;

+		case ANTENNA_B:

+			rfPath = RF_PATH_B;

+			break;

+		case ANTENNA_C:

+			rfPath = RF_PATH_C;

+			break;

+	}

+

+	switch (pHalData->rf_chip)

+	{

+		// 2008/09/12 MH Test only !! We enable the TX power tracking for MP!!!!!

+		// We should call normal driver API later!!

+		case RF_8225:

+		case RF_8256:

+		case RF_6052:

+			Hal_SetCCKTxPower(pAdapter, TxPowerLevel);

+			if (pAdapter->mppriv.rateidx < MPT_RATE_6M)	// CCK rate

+				Hal_MPT_CCKTxPowerAdjustbyIndex(pAdapter, TxPowerLevel[rfPath]%2 == 0);

+			Hal_SetOFDMTxPower(pAdapter, TxPowerLevel);

+			break;

+

+		default:

+			break;

+	}

+

+//	SetCCKTxPower(pAdapter, TxPower);

+//	SetOFDMTxPower(pAdapter, TxPower);

+}

+

+void Hal_SetTxAGCOffset(PADAPTER pAdapter, u32 ulTxAGCOffset)

+{

+	u32 TxAGCOffset_B, TxAGCOffset_C, TxAGCOffset_D,tmpAGC;

+

+	TxAGCOffset_B = (ulTxAGCOffset&0x000000ff);

+	TxAGCOffset_C = ((ulTxAGCOffset&0x0000ff00)>>8);

+	TxAGCOffset_D = ((ulTxAGCOffset&0x00ff0000)>>16);

+

+	tmpAGC = (TxAGCOffset_D<<8 | TxAGCOffset_C<<4 | TxAGCOffset_B);

+	write_bbreg(pAdapter, rFPGA0_TxGainStage,

+			(bXBTxAGC|bXCTxAGC|bXDTxAGC), tmpAGC);

+}

+

+void Hal_SetDataRate(PADAPTER pAdapter)

+{

+	Hal_mpt_SwitchRfSetting(pAdapter);

+}

+

+void Hal_SetAntenna(PADAPTER pAdapter)

+{

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);

+

+	R_ANTENNA_SELECT_OFDM *p_ofdm_tx;	/* OFDM Tx register */

+	R_ANTENNA_SELECT_CCK *p_cck_txrx;

+

+	u8	r_rx_antenna_ofdm = 0, r_ant_select_cck_val = 0;

+	u8	chgTx = 0, chgRx = 0;

+	u32	r_ant_sel_cck_val = 0, r_ant_select_ofdm_val = 0, r_ofdm_tx_en_val = 0;

+

+

+	p_ofdm_tx = (R_ANTENNA_SELECT_OFDM *)&r_ant_select_ofdm_val;

+	p_cck_txrx = (R_ANTENNA_SELECT_CCK *)&r_ant_select_cck_val;

+

+	p_ofdm_tx->r_ant_ht1	= 0x1;

+	p_ofdm_tx->r_ant_ht2	= 0x2;	// Second TX RF path is A

+	p_ofdm_tx->r_ant_non_ht = 0x3;	// 0x1+0x2=0x3

+

+	switch (pAdapter->mppriv.antenna_tx)

+	{

+		case ANTENNA_A:

+			p_ofdm_tx->r_tx_antenna		= 0x1;

+			r_ofdm_tx_en_val		= 0x1;

+			p_ofdm_tx->r_ant_l 		= 0x1;

+			p_ofdm_tx->r_ant_ht_s1 		= 0x1;

+			p_ofdm_tx->r_ant_non_ht_s1 	= 0x1;

+			p_cck_txrx->r_ccktx_enable	= 0x8;

+			chgTx = 1;

+

+			// From SD3 Willis suggestion !!! Set RF A=TX and B as standby

+//			if (IS_HARDWARE_TYPE_8192S(pAdapter))

+			{

+			write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);

+			write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1);

+			r_ofdm_tx_en_val		= 0x3;

+

+			// Power save

+			//cosa r_ant_select_ofdm_val = 0x11111111;

+

+			// We need to close RFB by SW control

+			if (pHalData->rf_type == RF_2T2R)

+			{

+				PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);

+				PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 1);

+				PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);

+				PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);

+				PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 0);

+			}

+			}

+			break;

+

+		case ANTENNA_B:

+			p_ofdm_tx->r_tx_antenna		= 0x2;

+			r_ofdm_tx_en_val		= 0x2;

+			p_ofdm_tx->r_ant_l 		= 0x2;

+			p_ofdm_tx->r_ant_ht_s1 		= 0x2;

+			p_ofdm_tx->r_ant_non_ht_s1 	= 0x2;

+			p_cck_txrx->r_ccktx_enable	= 0x4;

+			chgTx = 1;

+

+			// From SD3 Willis suggestion !!! Set RF A as standby

+			//if (IS_HARDWARE_TYPE_8192S(pAdapter))

+			{

+			PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1);

+			PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);

+//			r_ofdm_tx_en_val		= 0x3;

+

+			// Power save

+			//cosa r_ant_select_ofdm_val = 0x22222222;

+

+			// 2008/10/31 MH From SD3 Willi's suggestion. We must read RF 1T table.

+			// 2009/01/08 MH From Sd3 Willis. We need to close RFA by SW control

+			if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_1T2R)

+			{

+				PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 1);

+				PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0);

+				PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);

+//				PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);

+				PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 0);

+				PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);

+			}

+			}

+		break;

+

+		case ANTENNA_AB:	// For 8192S

+			p_ofdm_tx->r_tx_antenna		= 0x3;

+			r_ofdm_tx_en_val		= 0x3;

+			p_ofdm_tx->r_ant_l 		= 0x3;

+			p_ofdm_tx->r_ant_ht_s1 		= 0x3;

+			p_ofdm_tx->r_ant_non_ht_s1 	= 0x3;

+			p_cck_txrx->r_ccktx_enable	= 0xC;

+			chgTx = 1;

+

+			// From SD3 Willis suggestion !!! Set RF B as standby

+			//if (IS_HARDWARE_TYPE_8192S(pAdapter))

+			{

+			PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);

+			PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);

+

+			// Disable Power save

+			//cosa r_ant_select_ofdm_val = 0x3321333;

+#if 0

+			// 2008/10/31 MH From SD3 Willi's suggestion. We must read RFA 2T table.

+			if ((pHalData->VersionID == VERSION_8192S_ACUT)) // For RTL8192SU A-Cut only, by Roger, 2008.11.07.

+			{

+				mpt_RFConfigFromPreParaArrary(pAdapter, 1, RF_PATH_A);

+			}

+#endif

+			// 2009/01/08 MH From Sd3 Willis. We need to enable RFA/B by SW control

+			if (pHalData->rf_type == RF_2T2R)

+			{

+				PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);

+				PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);

+//				PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);

+				PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);

+				PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);

+			}

+			}

+			break;

+

+		default:

+			break;

+	}

+

+	//

+	// r_rx_antenna_ofdm, bit0=A, bit1=B, bit2=C, bit3=D

+	// r_cckrx_enable : CCK default, 0=A, 1=B, 2=C, 3=D

+	// r_cckrx_enable_2 : CCK option, 0=A, 1=B, 2=C, 3=D

+	//

+	switch (pAdapter->mppriv.antenna_rx)

+	{

+		case ANTENNA_A:

+			r_rx_antenna_ofdm 		= 0x1;	// A

+			p_cck_txrx->r_cckrx_enable 	= 0x0;	// default: A

+			p_cck_txrx->r_cckrx_enable_2	= 0x0;	// option: A

+			chgRx = 1;

+			break;

+

+		case ANTENNA_B:

+			r_rx_antenna_ofdm 		= 0x2;	// B

+			p_cck_txrx->r_cckrx_enable 	= 0x1;	// default: B

+			p_cck_txrx->r_cckrx_enable_2	= 0x1;	// option: B

+			chgRx = 1;

+			break;

+

+		case ANTENNA_AB:

+			r_rx_antenna_ofdm 		= 0x3;	// AB

+			p_cck_txrx->r_cckrx_enable 	= 0x0;	// default:A

+			p_cck_txrx->r_cckrx_enable_2	= 0x1;	// option:B

+			chgRx = 1;

+			break;

+

+		default:

+			break;

+	}

+

+	if (chgTx && chgRx)

+	{

+		switch(pHalData->rf_chip)

+		{

+			case RF_8225:

+			case RF_8256:

+			case RF_6052:

+				//r_ant_sel_cck_val = r_ant_select_cck_val;

+				PHY_SetBBReg(pAdapter, rFPGA1_TxInfo, 0x7fffffff, r_ant_select_ofdm_val);	//OFDM Tx

+				PHY_SetBBReg(pAdapter, rFPGA0_TxInfo, 0x0000000f, r_ofdm_tx_en_val);		//OFDM Tx

+				PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm);	//OFDM Rx

+				PHY_SetBBReg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm);	//OFDM Rx

+				PHY_SetBBReg(pAdapter, rCCK0_AFESetting, bMaskByte3, r_ant_select_cck_val);//r_ant_sel_cck_val);		//CCK TxRx

+

+				break;

+

+			default:

+				break;

+		}

+	}

+

+	RT_TRACE(_module_mp_, _drv_notice_, ("-SwitchAntenna: finished\n"));

+}

+

+s32 Hal_SetThermalMeter(PADAPTER pAdapter, u8 target_ther)

+{

+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);

+

+

+	if (!netif_running(pAdapter->pnetdev)) {

+		RT_TRACE(_module_mp_, _drv_warning_, ("SetThermalMeter! Fail: interface not opened!\n"));

+		return _FAIL;

+	}

+

+	if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {

+		RT_TRACE(_module_mp_, _drv_warning_, ("SetThermalMeter: Fail! not in MP mode!\n"));

+		return _FAIL;

+	}

+

+	target_ther &= 0xff;

+	if (target_ther < 0x07)

+		target_ther = 0x07;

+	else if (target_ther > 0x1d)

+		target_ther = 0x1d;

+

+	pHalData->EEPROMThermalMeter = target_ther;

+

+	return _SUCCESS;

+}

+

+void Hal_TriggerRFThermalMeter(PADAPTER pAdapter)

+{

+  

+	_write_rfreg( pAdapter, RF_PATH_A , RF_T_METER_88E , BIT17 |BIT16 , 0x03 );

+

+//	RT_TRACE(_module_mp_,_drv_alert_, ("TriggerRFThermalMeter() finished.\n" ));

+}

+

+u8 Hal_ReadRFThermalMeter(PADAPTER pAdapter)

+{

+	u32 ThermalValue = 0;

+

+	//ThermalValue = _read_rfreg(pAdapter, RF_PATH_A, RF_T_METER, 0x1F);	// 0x24: RF Reg[4:0]

+

+	ThermalValue = _read_rfreg(pAdapter, RF_PATH_A, RF_T_METER_88E, 0xfc00);

+	

+//	RT_TRACE(_module_mp_, _drv_alert_, ("ThermalValue = 0x%x\n", ThermalValue));

+	return (u8)ThermalValue;

+}

+

+void Hal_GetThermalMeter(PADAPTER pAdapter, u8 *value)

+{

+#if 0

+	fw_cmd(pAdapter, IOCMD_GET_THERMAL_METER);

+	rtw_msleep_os(1000);

+	fw_cmd_data(pAdapter, value, 1);

+	*value &= 0xFF;

+#else

+

+	Hal_TriggerRFThermalMeter(pAdapter);

+	rtw_msleep_os(1000);

+	*value = Hal_ReadRFThermalMeter(pAdapter);

+#endif

+}

+

+void Hal_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)

+{

+    HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);

+	pAdapter->mppriv.MptCtx.bSingleCarrier = bStart;

+	if (bStart)// Start Single Carrier.

+	{

+		RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleCarrierTx: test start\n"));

+		// 1. if OFDM block on?

+		if(!read_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn))

+			write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);//set OFDM block on

+

+		{

+		// 2. set CCK test mode off, set to CCK normal mode

+		write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);

+		// 3. turn on scramble setting

+		write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable);

+         }

+		// 4. Turn On Single Carrier Tx and turn off the other test modes.

+		write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);

+		write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bEnable);

+		write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);

+#ifdef CONFIG_RTL8192C

+		// 5. Disable TX power saving at STF & LLTF

+		write_bbreg(pAdapter, rOFDM1_LSTF, BIT22, 1);

+#endif

+		//for dynamic set Power index.

+		write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);

+		write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);

+		

+	}

+	else// Stop Single Carrier.

+	{

+		RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleCarrierTx: test stop\n"));

+

+		// Turn off all test modes.

+		write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);

+		write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);

+		write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);

+#ifdef CONFIG_RTL8192C

+		// Cancel disable TX power saving at STF&LLTF

+		write_bbreg(pAdapter, rOFDM1_LSTF, BIT22, 0);

+#endif

+		//Delay 10 ms //delay_ms(10);

+		rtw_msleep_os(10);

+

+		//BB Reset

+		write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);

+		write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);

+

+		//Stop for dynamic set Power index.

+		write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);

+		write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);

+		

+	}

+}

+

+

+void Hal_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)

+{

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);

+	BOOLEAN		is92C = IS_92C_SERIAL(pHalData->VersionID);

+

+	u8 rfPath;

+	u32              reg58 = 0x0;

+	switch (pAdapter->mppriv.antenna_tx)

+	{

+		case ANTENNA_A:

+		default:

+			rfPath = RF_PATH_A;

+			break;

+		case ANTENNA_B:

+			rfPath = RF_PATH_B;

+			break;

+		case ANTENNA_C:

+			rfPath = RF_PATH_C;

+			break;

+	}

+

+	pAdapter->mppriv.MptCtx.bSingleTone = bStart;

+	if (bStart)// Start Single Tone.

+	{

+		RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleToneTx: test start\n"));

+		{   // <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu)

+            if (IS_HARDWARE_TYPE_8188E(pAdapter)) 

+            {

+                reg58 = PHY_QueryRFReg(pAdapter, RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask);

+                reg58 &= 0xFFFFFFF0;

+                reg58 += 2;

+                PHY_SetRFReg(pAdapter, RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask, reg58);

+            }

+		PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x0);

+		PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x0);

+        }

+

+		if (is92C)

+       		 {

+			_write_rfreg(pAdapter, RF_PATH_A, 0x21, BIT19, 0x01);

+			rtw_usleep_os(100);

+			if (rfPath == RF_PATH_A)

+				write_rfreg(pAdapter, RF_PATH_B, 0x00, 0x10000); // PAD all on.

+			else if (rfPath == RF_PATH_B)

+				write_rfreg(pAdapter, RF_PATH_A, 0x00, 0x10000); // PAD all on.

+			write_rfreg(pAdapter, rfPath, 0x00, 0x2001f); // PAD all on.

+			rtw_usleep_os(100);

+		} 

+		else

+		{

+			write_rfreg(pAdapter, rfPath, 0x21, 0xd4000);

+			rtw_usleep_os(100);

+			write_rfreg(pAdapter, rfPath, 0x00, 0x2001f); // PAD all on.

+			rtw_usleep_os(100);

+		}

+

+		//for dynamic set Power index.

+		write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);

+		write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);

+		

+	}

+	else// Stop Single Tone.

+	{

+			RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleToneTx: test stop\n"));

+			

+	 	{   // <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu)

+            // <20120326, Kordan> Only in single tone mode. (asked by Edlu)

+            if (IS_HARDWARE_TYPE_8188E(pAdapter)) 

+            {

+                reg58 = PHY_QueryRFReg(pAdapter, RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask);

+                reg58 &= 0xFFFFFFF0;

+                PHY_SetRFReg(pAdapter, RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask, reg58);

+            }

+	

+		write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x1);

+		write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x1);

+		}

+		if (is92C) {

+			_write_rfreg(pAdapter, RF_PATH_A, 0x21, BIT19, 0x00);

+			rtw_usleep_os(100);

+			write_rfreg(pAdapter, RF_PATH_A, 0x00, 0x32d75); // PAD all on.

+			write_rfreg(pAdapter, RF_PATH_B, 0x00, 0x32d75); // PAD all on.

+			rtw_usleep_os(100);

+		} else {

+			write_rfreg(pAdapter, rfPath, 0x21, 0x54000);

+			rtw_usleep_os(100);

+			write_rfreg(pAdapter, rfPath, 0x00, 0x30000); // PAD all on.

+			rtw_usleep_os(100);

+		}

+

+		//Stop for dynamic set Power index.

+		write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);

+		write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);

+		

+	}

+	

+}

+

+

+

+void Hal_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)

+{

+	pAdapter->mppriv.MptCtx.bCarrierSuppression = bStart;

+	if (bStart) // Start Carrier Suppression.

+	{

+		RT_TRACE(_module_mp_,_drv_alert_, ("SetCarrierSuppressionTx: test start\n"));

+		//if(pMgntInfo->dot11CurrentWirelessMode == WIRELESS_MODE_B)

+		if (pAdapter->mppriv.rateidx <= MPT_RATE_11M)

+		  {

+			// 1. if CCK block on?

+			if(!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))

+				write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);//set CCK block on

+

+			//Turn Off All Test Mode

+			write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);

+			write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);

+			write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);

+

+			write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2);    //transmit mode

+			write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x0);  //turn off scramble setting

+

+			//Set CCK Tx Test Rate

+			//PHY_SetBBReg(pAdapter, rCCK0_System, bCCKTxRate, pMgntInfo->ForcedDataRate);

+			write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, 0x0);    //Set FTxRate to 1Mbps

+		}

+

+		//for dynamic set Power index.

+		write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);

+		write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);

+		

+	}

+	else// Stop Carrier Suppression.

+	{

+		RT_TRACE(_module_mp_,_drv_alert_, ("SetCarrierSuppressionTx: test stop\n"));

+		//if(pMgntInfo->dot11CurrentWirelessMode == WIRELESS_MODE_B)

+		if (pAdapter->mppriv.rateidx <= MPT_RATE_11M ) {

+			write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0);    //normal mode

+			write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x1);  //turn on scramble setting

+

+			//BB Reset

+			write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);

+			write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);

+		}

+

+		//Stop for dynamic set Power index.

+		write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);

+		write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);

+		

+	}

+	//DbgPrint("\n MPT_ProSetCarrierSupp() is finished. \n");

+}

+

+void Hal_SetCCKContinuousTx(PADAPTER pAdapter, u8 bStart)

+{

+	u32 cckrate;

+

+	if (bStart)

+	{

+		RT_TRACE(_module_mp_, _drv_alert_,

+			 ("SetCCKContinuousTx: test start\n"));

+

+		// 1. if CCK block on?

+		if(!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))

+			write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);//set CCK block on

+

+		//Turn Off All Test Mode

+		write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);

+		write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);

+		write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);

+		//Set CCK Tx Test Rate

+		#if 0

+		switch(pAdapter->mppriv.rateidx)

+		{

+			case 2:

+				cckrate = 0;

+				break;

+			case 4:

+				cckrate = 1;

+				break;

+			case 11:

+				cckrate = 2;

+				break;

+			case 22:

+				cckrate = 3;

+				break;

+			default:

+				cckrate = 0;

+				break;

+		}

+		#else

+		cckrate  = pAdapter->mppriv.rateidx;

+		#endif

+		write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);

+		write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2);	//transmit mode

+		write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable);	//turn on scramble setting

+

+

+		// Patch for CCK 11M waveform

+		if (cckrate == MPT_RATE_1M)

+			write_bbreg(pAdapter, 0xA71, BIT(6), bDisable);

+		else

+			write_bbreg(pAdapter, 0xA71, BIT(6), bEnable);

+

+		//for dynamic set Power index.

+		write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);

+		write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);

+

+	}

+	else {

+		RT_TRACE(_module_mp_, _drv_info_,

+			 ("SetCCKContinuousTx: test stop\n"));

+

+		write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0);	//normal mode

+		write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable);	//turn on scramble setting

+

+		//BB Reset

+		write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);

+		write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);

+

+		//Stop for dynamic set Power index.

+		write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);

+		write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);

+	}

+

+	pAdapter->mppriv.MptCtx.bCckContTx = bStart;

+	pAdapter->mppriv.MptCtx.bOfdmContTx = _FALSE;

+}/* mpt_StartCckContTx */

+

+void Hal_SetOFDMContinuousTx(PADAPTER pAdapter, u8 bStart)

+{

+    HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);

+

+	if (bStart) {

+		RT_TRACE(_module_mp_, _drv_info_, ("SetOFDMContinuousTx: test start\n"));

+		// 1. if OFDM block on?

+		if(!read_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn))

+			write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);//set OFDM block on

+        {

+

+		// 2. set CCK test mode off, set to CCK normal mode

+		write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);

+

+		// 3. turn on scramble setting

+		write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable);

+        }

+		// 4. Turn On Continue Tx and turn off the other test modes.

+		write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bEnable);

+		write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);

+		write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);

+

+		//for dynamic set Power index.

+		write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);

+		write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);

+		

+	} else {

+		RT_TRACE(_module_mp_,_drv_info_, ("SetOFDMContinuousTx: test stop\n"));

+		write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);

+		write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);

+		write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);

+		//Delay 10 ms

+		rtw_msleep_os(10);

+		//BB Reset

+		write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);

+		write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);

+

+		//Stop for dynamic set Power index.

+		write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);

+		write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);

+	}

+

+	pAdapter->mppriv.MptCtx.bCckContTx = _FALSE;

+	pAdapter->mppriv.MptCtx.bOfdmContTx = bStart;

+}/* mpt_StartOfdmContTx */

+

+void Hal_SetContinuousTx(PADAPTER pAdapter, u8 bStart)

+{

+#if 0

+	// ADC turn off [bit24-21] adc port0 ~ port1

+	if (bStart) {

+		write_bbreg(pAdapter, rRx_Wait_CCCA, read_bbreg(pAdapter, rRx_Wait_CCCA) & 0xFE1FFFFF);

+		rtw_usleep_os(100);

+	}

+#endif

+	RT_TRACE(_module_mp_, _drv_info_,

+		 ("SetContinuousTx: rate:%d\n", pAdapter->mppriv.rateidx));

+

+	pAdapter->mppriv.MptCtx.bStartContTx = bStart;

+	if (pAdapter->mppriv.rateidx <= MPT_RATE_11M)

+	{

+		Hal_SetCCKContinuousTx(pAdapter, bStart);

+	}

+	else if ((pAdapter->mppriv.rateidx >= MPT_RATE_6M) &&

+		 (pAdapter->mppriv.rateidx <= MPT_RATE_MCS15))

+	{

+		Hal_SetOFDMContinuousTx(pAdapter, bStart);

+	}

+#if 0

+	// ADC turn on [bit24-21] adc port0 ~ port1

+	if (!bStart) {

+		write_bbreg(pAdapter, rRx_Wait_CCCA, read_bbreg(pAdapter, rRx_Wait_CCCA) | 0x01E00000);

+	}

+#endif

+}

+

+#endif // CONFIG_MP_INCLUDE

+

diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/rtl8188e_phycfg.c b/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/rtl8188e_phycfg.c
new file mode 100755
index 00000000..89d2f4f7
--- /dev/null
+++ b/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/rtl8188e_phycfg.c
@@ -0,0 +1,3533 @@
+/******************************************************************************

+ *

+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.

+ *

+ * This program is free software; you can redistribute it and/or modify it

+ * under the terms of version 2 of the GNU General Public License as

+ * published by the Free Software Foundation.

+ *

+ * This program is distributed in the hope that it will be useful, but WITHOUT

+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for

+ * more details.

+ *

+ * You should have received a copy of the GNU General Public License along with

+ * this program; if not, write to the Free Software Foundation, Inc.,

+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA

+ *

+ *

+ ******************************************************************************/

+#define _RTL8188E_PHYCFG_C_

+

+#include <drv_conf.h>

+#include <osdep_service.h>

+#include <drv_types.h>

+#include <rtw_byteorder.h>

+

+#ifdef CONFIG_IOL

+#include <rtw_iol.h>

+#endif

+

+#include <rtl8188e_hal.h>

+

+

+/*---------------------------Define Local Constant---------------------------*/

+/* Channel switch:The size of command tables for switch channel*/

+#define MAX_PRECMD_CNT 16

+#define MAX_RFDEPENDCMD_CNT 16

+#define MAX_POSTCMD_CNT 16

+

+#define MAX_DOZE_WAITING_TIMES_9x 64

+

+/*---------------------------Define Local Constant---------------------------*/

+

+

+/*------------------------Define global variable-----------------------------*/

+

+/*------------------------Define local variable------------------------------*/

+

+

+/*--------------------Define export function prototype-----------------------*/

+// Please refer to header file

+/*--------------------Define export function prototype-----------------------*/

+

+/*----------------------------Function Body----------------------------------*/

+//

+// 1. BB register R/W API

+//

+

+/**

+* Function:	phy_CalculateBitShift

+*

+* OverView:	Get shifted position of the BitMask

+*

+* Input:

+*			u4Byte		BitMask,

+*

+* Output:	none

+* Return:		u4Byte		Return the shift bit bit position of the mask

+*/

+static	u32

+phy_CalculateBitShift(

+	u32 BitMask

+	)

+{

+	u32 i;

+

+	for(i=0; i<=31; i++)

+	{

+		if ( ((BitMask>>i) &  0x1 ) == 1)

+			break;

+	}

+

+	return (i);

+}

+

+#if(SIC_ENABLE == 1)

+static BOOLEAN

+sic_IsSICReady(

+	IN	PADAPTER	Adapter

+	)

+{

+	BOOLEAN		bRet=_FALSE;

+	u32		retryCnt=0;

+	u8		sic_cmd=0xff;

+

+	while(1)

+	{		

+		if(retryCnt++ >= SIC_MAX_POLL_CNT)

+		{

+			//RTPRINT(FPHY, (PHY_SICR|PHY_SICW), ("[SIC], sic_IsSICReady() return FALSE\n"));

+			return _FALSE;

+		}

+

+		//if(RT_SDIO_CANNOT_IO(Adapter))

+		//	return _FALSE;

+

+		sic_cmd = rtw_read8(Adapter, SIC_CMD_REG);

+		//sic_cmd = PlatformEFIORead1Byte(Adapter, SIC_CMD_REG);

+#if(SIC_HW_SUPPORT == 1)

+		sic_cmd &= 0xf0;	// [7:4]

+#endif

+		//RTPRINT(FPHY, (PHY_SICR|PHY_SICW), ("[SIC], sic_IsSICReady(), readback 0x%x=0x%x\n", SIC_CMD_REG, sic_cmd));

+		if(sic_cmd == SIC_CMD_READY)

+			return _TRUE;

+		else

+		{

+			rtw_msleep_os(1);

+			//delay_ms(1);

+		}

+	}

+

+	return bRet;

+}

+

+/*

+u32

+sic_CalculateBitShift(

+	u32 BitMask

+	)

+{

+	u32 i;

+

+	for(i=0; i<=31; i++)

+	{

+		if ( ((BitMask>>i) &  0x1 ) == 1)

+			break;

+	}

+

+	return (i);

+}

+*/

+

+static u32

+sic_Read4Byte(

+	PVOID		Adapter,

+	u32		offset

+	)

+{

+	u32	u4ret=0xffffffff;

+#if RTL8188E_SUPPORT == 1

+	u8	retry = 0;

+#endif

+

+	//RTPRINT(FPHY, PHY_SICR, ("[SIC], sic_Read4Byte(): read offset(%#x)\n", offset));

+	

+	if(sic_IsSICReady(Adapter))

+	{

+#if(SIC_HW_SUPPORT == 1)

+		rtw_write8(Adapter, SIC_CMD_REG, SIC_CMD_PREREAD);

+		//PlatformEFIOWrite1Byte(Adapter, SIC_CMD_REG, SIC_CMD_PREREAD);

+		//RTPRINT(FPHY, PHY_SICR, ("write cmdreg 0x%x = 0x%x\n", SIC_CMD_REG, SIC_CMD_PREREAD));

+#endif

+		rtw_write8(Adapter, SIC_ADDR_REG, (u8)(offset&0xff));

+		//PlatformEFIOWrite1Byte(Adapter, SIC_ADDR_REG, (u1Byte)(offset&0xff));

+		//RTPRINT(FPHY, PHY_SICR, ("write 0x%x = 0x%x\n", SIC_ADDR_REG, (u1Byte)(offset&0xff)));

+		rtw_write8(Adapter, SIC_ADDR_REG+1, (u8)((offset&0xff00)>>8));

+		//PlatformEFIOWrite1Byte(Adapter, SIC_ADDR_REG+1, (u1Byte)((offset&0xff00)>>8));

+		//RTPRINT(FPHY, PHY_SICR, ("write 0x%x = 0x%x\n", SIC_ADDR_REG+1, (u1Byte)((offset&0xff00)>>8)));

+		rtw_write8(Adapter, SIC_CMD_REG, SIC_CMD_READ);

+		//PlatformEFIOWrite1Byte(Adapter, SIC_CMD_REG, SIC_CMD_READ);

+		//RTPRINT(FPHY, PHY_SICR, ("write cmdreg 0x%x = 0x%x\n", SIC_CMD_REG, SIC_CMD_READ));

+

+#if RTL8188E_SUPPORT == 1

+		retry = 4;

+		while(retry--){			

+			rtw_udelay_os(50);

+			//PlatformStallExecution(50);

+		}

+#else

+		rtw_udelay_os(200);

+		//PlatformStallExecution(200);

+#endif

+

+		if(sic_IsSICReady(Adapter))

+		{

+			u4ret = rtw_read32(Adapter, SIC_DATA_REG);

+			//u4ret = PlatformEFIORead4Byte(Adapter, SIC_DATA_REG);

+			//RTPRINT(FPHY, PHY_SICR, ("read 0x%x = 0x%x\n", SIC_DATA_REG, u4ret));

+			//DbgPrint("<===Read 0x%x = 0x%x\n", offset, u4ret);

+		}

+	}

+	

+	return u4ret;

+}

+

+static VOID

+sic_Write4Byte(

+	PVOID		Adapter,

+	u32		offset,

+	u32		data

+	)

+{

+#if RTL8188E_SUPPORT == 1

+	u8	retry = 6;

+#endif

+	//DbgPrint("=>Write 0x%x = 0x%x\n", offset, data);

+	//RTPRINT(FPHY, PHY_SICW, ("[SIC], sic_Write4Byte(): write offset(%#x)=0x%x\n", offset, data));

+	if(sic_IsSICReady(Adapter))

+	{

+#if(SIC_HW_SUPPORT == 1)

+		rtw_write8(Adapter, SIC_CMD_REG, SIC_CMD_PREWRITE);

+		//PlatformEFIOWrite1Byte(Adapter, SIC_CMD_REG, SIC_CMD_PREWRITE);

+		//RTPRINT(FPHY, PHY_SICW, ("write data 0x%x = 0x%x\n", SIC_CMD_REG, SIC_CMD_PREWRITE));

+#endif

+		rtw_write8(Adapter, SIC_ADDR_REG, (u8)(offset&0xff));

+		//PlatformEFIOWrite1Byte(Adapter, SIC_ADDR_REG, (u1Byte)(offset&0xff));

+		//RTPRINT(FPHY, PHY_SICW, ("write 0x%x=0x%x\n", SIC_ADDR_REG, (u1Byte)(offset&0xff)));

+		rtw_write8(Adapter, SIC_ADDR_REG+1, (u8)((offset&0xff00)>>8));

+		//PlatformEFIOWrite1Byte(Adapter, SIC_ADDR_REG+1, (u1Byte)((offset&0xff00)>>8));

+		//RTPRINT(FPHY, PHY_SICW, ("write 0x%x=0x%x\n", (SIC_ADDR_REG+1), (u1Byte)((offset&0xff00)>>8)));

+		rtw_write32(Adapter, SIC_DATA_REG, (u32)data);

+		//PlatformEFIOWrite4Byte(Adapter, SIC_DATA_REG, (u4Byte)data);

+		//RTPRINT(FPHY, PHY_SICW, ("write data 0x%x = 0x%x\n", SIC_DATA_REG, data));

+		rtw_write8(Adapter, SIC_CMD_REG, SIC_CMD_WRITE);

+		//PlatformEFIOWrite1Byte(Adapter, SIC_CMD_REG, SIC_CMD_WRITE);

+		//RTPRINT(FPHY, PHY_SICW, ("write data 0x%x = 0x%x\n", SIC_CMD_REG, SIC_CMD_WRITE));

+#if RTL8188E_SUPPORT == 1

+		while(retry--){

+			rtw_udelay_os(50);

+			//PlatformStallExecution(50);

+		}

+#else

+		rtw_udelay_os(150);

+		//PlatformStallExecution(150);

+#endif

+

+	}

+}

+//============================================================

+// extern function

+//============================================================

+static VOID

+SIC_SetBBReg(

+	IN	PADAPTER	Adapter,

+	IN	u32		RegAddr,

+	IN	u32		BitMask,

+	IN	u32		Data

+	)

+{

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);

+	u32			OriginalValue, BitShift;

+	u16			BBWaitCounter = 0;

+

+	//RTPRINT(FPHY, PHY_SICW, ("[SIC], SIC_SetBBReg() start\n"));

+/*

+	while(PlatformAtomicExchange(&pHalData->bChangeBBInProgress, _TRUE) == _TRUE)

+	{

+		BBWaitCounter ++;

+		delay_ms(10); // 1 ms

+

+		if((BBWaitCounter > 100) || RT_CANNOT_IO(Adapter))

+		{// Wait too long, return FALSE to avoid to be stuck here.

+			RTPRINT(FPHY, PHY_SICW, ("[SIC], SIC_SetBBReg(), Fail to set BB offset(%#x)!!, WaitCnt(%d)\n", RegAddr, BBWaitCounter));

+			return;

+		}		

+	}

+*/

+	//

+	// Critical section start

+	// 

+	

+	//RTPRINT(FPHY, PHY_SICW, ("[SIC], SIC_SetBBReg(), mask=0x%x, addr[0x%x]=0x%x\n", BitMask, RegAddr, Data));

+

+	if(BitMask!= bMaskDWord){//if not "double word" write

+		OriginalValue = sic_Read4Byte(Adapter, RegAddr);

+		//BitShift = sic_CalculateBitShift(BitMask);

+		BitShift = phy_CalculateBitShift(BitMask);		

+		Data = (((OriginalValue) & (~BitMask)) | (Data << BitShift));

+	}

+

+	sic_Write4Byte(Adapter, RegAddr, Data);

+

+	//PlatformAtomicExchange(&pHalData->bChangeBBInProgress, _FALSE);

+	//RTPRINT(FPHY, PHY_SICW, ("[SIC], SIC_SetBBReg() end\n"));

+}

+

+static u32

+SIC_QueryBBReg(

+	IN	PADAPTER	Adapter,

+	IN	u32		RegAddr,

+	IN	u32		BitMask

+	)

+{

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);

+	u32			ReturnValue = 0, OriginalValue, BitShift;

+	u16			BBWaitCounter = 0;

+

+	//RTPRINT(FPHY, PHY_SICR, ("[SIC], SIC_QueryBBReg() start\n"));

+

+/*

+	while(PlatformAtomicExchange(&pHalData->bChangeBBInProgress, _TRUE) == _TRUE)

+	{

+		BBWaitCounter ++;

+		delay_ms(10); // 10 ms

+

+		if((BBWaitCounter > 100) || RT_CANNOT_IO(Adapter))

+		{// Wait too long, return FALSE to avoid to be stuck here.

+			RTPRINT(FPHY, PHY_SICW, ("[SIC], SIC_QueryBBReg(), Fail to query BB offset(%#x)!!, WaitCnt(%d)\n", RegAddr, BBWaitCounter));

+			return ReturnValue;

+		}		

+	}

+*/

+	OriginalValue = sic_Read4Byte(Adapter, RegAddr);

+	//BitShift = sic_CalculateBitShift(BitMask);

+	BitShift = phy_CalculateBitShift(BitMask);

+	ReturnValue = (OriginalValue & BitMask) >> BitShift;

+

+	//RTPRINT(FPHY, PHY_SICR, ("[SIC], SIC_QueryBBReg(), 0x%x=0x%x\n", RegAddr, OriginalValue));

+	//RTPRINT(FPHY, PHY_SICR, ("[SIC], SIC_QueryBBReg() end\n"));

+

+	//PlatformAtomicExchange(&pHalData->bChangeBBInProgress, _FALSE);	

+	return (ReturnValue);

+}

+

+VOID

+SIC_Init(

+	IN	PADAPTER	Adapter

+	)

+{

+	// Here we need to write 0x1b8~0x1bf = 0 after fw is downloaded

+	// because for 8723E at beginning 0x1b8=0x1e, that will cause

+	// sic always not be ready

+#if(SIC_HW_SUPPORT == 1)

+	//RTPRINT(FPHY, PHY_SICR, ("[SIC], SIC_Init(), write 0x%x = 0x%x\n", 

+	//	SIC_INIT_REG, SIC_INIT_VAL));

+	rtw_write8(Adapter, SIC_INIT_REG, SIC_INIT_VAL);

+	//PlatformEFIOWrite1Byte(Adapter, SIC_INIT_REG, SIC_INIT_VAL);

+	//RTPRINT(FPHY, PHY_SICR, ("[SIC], SIC_Init(), write 0x%x = 0x%x\n", 

+	//	SIC_CMD_REG, SIC_CMD_INIT));

+	rtw_write8(Adapter, SIC_CMD_REG, SIC_CMD_INIT);

+	//PlatformEFIOWrite1Byte(Adapter, SIC_CMD_REG, SIC_CMD_INIT);

+#else

+	//RTPRINT(FPHY, PHY_SICR, ("[SIC], SIC_Init(), write 0x1b8~0x1bf = 0x0\n"));

+	rtw_write32(Adapter, SIC_CMD_REG, 0);

+	//PlatformEFIOWrite4Byte(Adapter, SIC_CMD_REG, 0);

+	rtw_write32(Adapter, SIC_CMD_REG+4, 0);

+	//PlatformEFIOWrite4Byte(Adapter, SIC_CMD_REG+4, 0);

+#endif

+}

+

+static BOOLEAN

+SIC_LedOff(

+	IN	PADAPTER	Adapter

+	)

+{

+	// When SIC is enabled, led pin will be used as debug pin,

+	// so don't execute led function when SIC is enabled.

+	return _TRUE;

+}

+#endif

+

+/**

+* Function:	PHY_QueryBBReg

+*

+* OverView:	Read "sepcific bits" from BB register

+*

+* Input:

+*			PADAPTER		Adapter,

+*			u4Byte			RegAddr,		//The target address to be readback

+*			u4Byte			BitMask		//The target bit position in the target address

+*										//to be readback

+* Output:	None

+* Return:		u4Byte			Data			//The readback register value

+* Note:		This function is equal to "GetRegSetting" in PHY programming guide

+*/

+u32

+rtl8188e_PHY_QueryBBReg(

+	IN	PADAPTER	Adapter,

+	IN	u32		RegAddr,

+	IN	u32		BitMask

+	)

+{

+  	u32	ReturnValue = 0, OriginalValue, BitShift;

+	u16	BBWaitCounter = 0;

+

+#if (DISABLE_BB_RF == 1)

+	return 0;

+#endif

+

+#if(SIC_ENABLE == 1)

+	return SIC_QueryBBReg(Adapter, RegAddr, BitMask);

+#endif

+

+	//RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_QueryBBReg(): RegAddr(%#lx), BitMask(%#lx)\n", RegAddr, BitMask));

+

+	OriginalValue = rtw_read32(Adapter, RegAddr);

+	BitShift = phy_CalculateBitShift(BitMask);

+	ReturnValue = (OriginalValue & BitMask) >> BitShift;

+

+	//RTPRINT(FPHY, PHY_BBR, ("BBR MASK=0x%lx Addr[0x%lx]=0x%lx\n", BitMask, RegAddr, OriginalValue));

+	//RT_TRACE(COMP_RF, DBG_TRACE, ("<---PHY_QueryBBReg(): RegAddr(%#lx), BitMask(%#lx), OriginalValue(%#lx)\n", RegAddr, BitMask, OriginalValue));

+

+	return (ReturnValue);

+

+}

+

+

+/**

+* Function:	PHY_SetBBReg

+*

+* OverView:	Write "Specific bits" to BB register (page 8~)

+*

+* Input:

+*			PADAPTER		Adapter,

+*			u4Byte			RegAddr,		//The target address to be modified

+*			u4Byte			BitMask		//The target bit position in the target address

+*										//to be modified

+*			u4Byte			Data			//The new register value in the target bit position

+*										//of the target address

+*

+* Output:	None

+* Return:		None

+* Note:		This function is equal to "PutRegSetting" in PHY programming guide

+*/

+

+VOID

+rtl8188e_PHY_SetBBReg(

+	IN	PADAPTER	Adapter,

+	IN	u32		RegAddr,

+	IN	u32		BitMask,

+	IN	u32		Data

+	)

+{

+	HAL_DATA_TYPE	*pHalData		= GET_HAL_DATA(Adapter);

+	//u16			BBWaitCounter	= 0;

+	u32			OriginalValue, BitShift;

+

+#if (DISABLE_BB_RF == 1)

+	return;

+#endif

+

+#if(SIC_ENABLE == 1)

+	SIC_SetBBReg(Adapter, RegAddr, BitMask, Data);

+	return; 

+#endif

+

+	//RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_SetBBReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx)\n", RegAddr, BitMask, Data));

+

+	if(BitMask!= bMaskDWord){//if not "double word" write

+		OriginalValue = rtw_read32(Adapter, RegAddr);

+		BitShift = phy_CalculateBitShift(BitMask);

+		Data = ((OriginalValue & (~BitMask)) | (Data << BitShift));

+	}

+

+	rtw_write32(Adapter, RegAddr, Data);

+

+	//RTPRINT(FPHY, PHY_BBW, ("BBW MASK=0x%lx Addr[0x%lx]=0x%lx\n", BitMask, RegAddr, Data));

+	//RT_TRACE(COMP_RF, DBG_TRACE, ("<---PHY_SetBBReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx)\n", RegAddr, BitMask, Data));

+

+}

+

+

+//

+// 2. RF register R/W API

+//

+/**

+* Function:	phy_RFSerialRead

+*

+* OverView:	Read regster from RF chips

+*

+* Input:

+*			PADAPTER		Adapter,

+*			RF_RADIO_PATH_E	eRFPath,	//Radio path of A/B/C/D

+*			u4Byte			Offset,		//The target address to be read

+*

+* Output:	None

+* Return:		u4Byte			reback value

+* Note:		Threre are three types of serial operations:

+*			1. Software serial write

+*			2. Hardware LSSI-Low Speed Serial Interface

+*			3. Hardware HSSI-High speed

+*			serial write. Driver need to implement (1) and (2).

+*			This function is equal to the combination of RF_ReadReg() and  RFLSSIRead()

+*/

+static	u32

+phy_RFSerialRead(

+	IN	PADAPTER			Adapter,

+	IN	RF_RADIO_PATH_E	eRFPath,

+	IN	u32				Offset

+	)

+{

+	u32						retValue = 0;

+	HAL_DATA_TYPE				*pHalData = GET_HAL_DATA(Adapter);

+	BB_REGISTER_DEFINITION_T	*pPhyReg = &pHalData->PHYRegDef[eRFPath];

+	u32						NewOffset;

+	u32 						tmplong,tmplong2;

+	u8					RfPiEnable=0;

+#if 0

+	if(pHalData->RFChipID == RF_8225 && Offset > 0x24) //36 valid regs

+		return	retValue;

+	if(pHalData->RFChipID == RF_8256 && Offset > 0x2D) //45 valid regs

+		return	retValue;

+#endif

+	//

+	// Make sure RF register offset is correct

+	//

+	Offset &= 0xff;

+

+	//

+	// Switch page for 8256 RF IC

+	//

+	NewOffset = Offset;

+

+	// 2009/06/17 MH We can not execute IO for power save or other accident mode.

+	//if(RT_CANNOT_IO(Adapter))

+	//{

+	//	RTPRINT(FPHY, PHY_RFR, ("phy_RFSerialRead return all one\n"));

+	//	return	0xFFFFFFFF;

+	//}

+

+	// For 92S LSSI Read RFLSSIRead

+	// For RF A/B write 0x824/82c(does not work in the future)

+	// We must use 0x824 for RF A and B to execute read trigger

+	tmplong = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord);

+	if(eRFPath == RF_PATH_A)

+		tmplong2 = tmplong;

+	else

+		tmplong2 = PHY_QueryBBReg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord);

+

+	tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge;	//T65 RF

+

+	PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong&(~bLSSIReadEdge));

+	rtw_udelay_os(10);// PlatformStallExecution(10);

+

+	PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord, tmplong2);

+	rtw_udelay_os(100);//PlatformStallExecution(100);

+

+	//PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong|bLSSIReadEdge);

+	rtw_udelay_os(10);//PlatformStallExecution(10);

+

+	if(eRFPath == RF_PATH_A)

+		RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1, BIT8);

+	else if(eRFPath == RF_PATH_B)

+		RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter1, BIT8);

+

+	if(RfPiEnable)

+	{	// Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF

+		retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBackPi, bLSSIReadBackData);

+		//DBG_8192C("Readback from RF-PI : 0x%x\n", retValue);

+	}

+	else

+	{	//Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF

+		retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);

+		//DBG_8192C("Readback from RF-SI : 0x%x\n", retValue);

+	}

+	//DBG_8192C("RFR-%d Addr[0x%x]=0x%x\n", eRFPath, pPhyReg->rfLSSIReadBack, retValue);

+

+	return retValue;

+

+}

+

+

+

+/**

+* Function:	phy_RFSerialWrite

+*

+* OverView:	Write data to RF register (page 8~)

+*

+* Input:

+*			PADAPTER		Adapter,

+*			RF_RADIO_PATH_E	eRFPath,	//Radio path of A/B/C/D

+*			u4Byte			Offset,		//The target address to be read

+*			u4Byte			Data			//The new register Data in the target bit position

+*										//of the target to be read

+*

+* Output:	None

+* Return:		None

+* Note:		Threre are three types of serial operations:

+*			1. Software serial write

+*			2. Hardware LSSI-Low Speed Serial Interface

+*			3. Hardware HSSI-High speed

+*			serial write. Driver need to implement (1) and (2).

+*			This function is equal to the combination of RF_ReadReg() and  RFLSSIRead()

+ *

+ * Note: 		  For RF8256 only

+ *			 The total count of RTL8256(Zebra4) register is around 36 bit it only employs

+ *			 4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10])

+ *			 to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration

+ *			 programming guide" for more details.

+ *			 Thus, we define a sub-finction for RTL8526 register address conversion

+ *		       ===========================================================

+ *			 Register Mode		RegCTL[1]		RegCTL[0]		Note

+ *								(Reg00[12])		(Reg00[10])

+ *		       ===========================================================

+ *			 Reg_Mode0				0				x			Reg 0 ~15(0x0 ~ 0xf)

+ *		       ------------------------------------------------------------------

+ *			 Reg_Mode1				1				0			Reg 16 ~30(0x1 ~ 0xf)

+ *		       ------------------------------------------------------------------

+ *			 Reg_Mode2				1				1			Reg 31 ~ 45(0x1 ~ 0xf)

+ *		       ------------------------------------------------------------------

+ *

+ *	2008/09/02	MH	Add 92S RF definition

+ *

+ *

+ *

+*/

+static	VOID

+phy_RFSerialWrite(

+	IN	PADAPTER			Adapter,

+	IN	RF_RADIO_PATH_E	eRFPath,

+	IN	u32				Offset,

+	IN	u32				Data

+	)

+{

+	u32						DataAndAddr = 0;

+	HAL_DATA_TYPE				*pHalData = GET_HAL_DATA(Adapter);

+	BB_REGISTER_DEFINITION_T	*pPhyReg = &pHalData->PHYRegDef[eRFPath];

+	u32						NewOffset;

+

+#if 0

+	//<Roger_TODO> We should check valid regs for RF_6052 case.

+	if(pHalData->RFChipID == RF_8225 && Offset > 0x24) //36 valid regs

+		return;

+	if(pHalData->RFChipID == RF_8256 && Offset > 0x2D) //45 valid regs

+		return;

+#endif

+

+	// 2009/06/17 MH We can not execute IO for power save or other accident mode.

+	//if(RT_CANNOT_IO(Adapter))

+	//{

+	//	RTPRINT(FPHY, PHY_RFW, ("phy_RFSerialWrite stop\n"));

+	//	return;

+	//}

+

+	Offset &= 0xff;

+

+	//

+	// Shadow Update

+	//

+	//PHY_RFShadowWrite(Adapter, eRFPath, Offset, Data);

+

+	//

+	// Switch page for 8256 RF IC

+	//

+	NewOffset = Offset;

+

+	//

+	// Put write addr in [5:0]  and write data in [31:16]

+	//

+	//DataAndAddr = (Data<<16) | (NewOffset&0x3f);

+	DataAndAddr = ((NewOffset<<20) | (Data&0x000fffff)) & 0x0fffffff;	// T65 RF

+

+	//

+	// Write Operation

+	//

+	PHY_SetBBReg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);

+	//RTPRINT(FPHY, PHY_RFW, ("RFW-%d Addr[0x%lx]=0x%lx\n", eRFPath, pPhyReg->rf3wireOffset, DataAndAddr));

+

+}

+

+

+/**

+* Function:	PHY_QueryRFReg

+*

+* OverView:	Query "Specific bits" to RF register (page 8~)

+*

+* Input:

+*			PADAPTER		Adapter,

+*			RF_RADIO_PATH_E	eRFPath,	//Radio path of A/B/C/D

+*			u4Byte			RegAddr,		//The target address to be read

+*			u4Byte			BitMask		//The target bit position in the target address

+*										//to be read

+*

+* Output:	None

+* Return:		u4Byte			Readback value

+* Note:		This function is equal to "GetRFRegSetting" in PHY programming guide

+*/

+u32

+rtl8188e_PHY_QueryRFReg(

+	IN	PADAPTER			Adapter,

+	IN	RF_RADIO_PATH_E	eRFPath,

+	IN	u32				RegAddr,

+	IN	u32				BitMask

+	)

+{

+	u32 Original_Value, Readback_Value, BitShift;

+	//HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(Adapter);

+	//u8	RFWaitCounter = 0;

+	//_irqL	irqL;

+

+#if (DISABLE_BB_RF == 1)

+	return 0;

+#endif

+

+	//RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_QueryRFReg(): RegAddr(%#lx), eRFPath(%#x), BitMask(%#lx)\n", RegAddr, eRFPath,BitMask));

+

+#ifdef CONFIG_USB_HCI

+	//PlatformAcquireMutex(&pHalData->mxRFOperate);

+#else

+	//_enter_critical(&pHalData->rf_lock, &irqL);

+#endif

+

+

+	Original_Value = phy_RFSerialRead(Adapter, eRFPath, RegAddr);

+

+	BitShift =  phy_CalculateBitShift(BitMask);

+	Readback_Value = (Original_Value & BitMask) >> BitShift;

+

+#ifdef CONFIG_USB_HCI

+	//PlatformReleaseMutex(&pHalData->mxRFOperate);

+#else

+	//_exit_critical(&pHalData->rf_lock, &irqL);

+#endif

+

+

+	//RTPRINT(FPHY, PHY_RFR, ("RFR-%d MASK=0x%lx Addr[0x%lx]=0x%lx\n", eRFPath, BitMask, RegAddr, Original_Value));//BitMask(%#lx),BitMask,

+	//RT_TRACE(COMP_RF, DBG_TRACE, ("<---PHY_QueryRFReg(): RegAddr(%#lx), eRFPath(%#x),  Original_Value(%#lx)\n",

+	//				RegAddr, eRFPath, Original_Value));

+

+	return (Readback_Value);

+}

+

+/**

+* Function:	PHY_SetRFReg

+*

+* OverView:	Write "Specific bits" to RF register (page 8~)

+*

+* Input:

+*			PADAPTER		Adapter,

+*			RF_RADIO_PATH_E	eRFPath,	//Radio path of A/B/C/D

+*			u4Byte			RegAddr,		//The target address to be modified

+*			u4Byte			BitMask		//The target bit position in the target address

+*										//to be modified

+*			u4Byte			Data			//The new register Data in the target bit position

+*										//of the target address

+*

+* Output:	None

+* Return:		None

+* Note:		This function is equal to "PutRFRegSetting" in PHY programming guide

+*/

+VOID

+rtl8188e_PHY_SetRFReg(

+	IN	PADAPTER			Adapter,

+	IN	RF_RADIO_PATH_E	eRFPath,

+	IN	u32				RegAddr,

+	IN	u32				BitMask,

+	IN	u32				Data

+	)

+{

+

+	//HAL_DATA_TYPE	*pHalData		= GET_HAL_DATA(Adapter);

+	//u1Byte			RFWaitCounter	= 0;

+	u32		Original_Value, BitShift;

+	//_irqL	irqL;

+

+#if (DISABLE_BB_RF == 1)

+	return;

+#endif

+

+	//RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_SetRFReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx), eRFPath(%#x)\n",

+	//	RegAddr, BitMask, Data, eRFPath));

+	//RTPRINT(FINIT, INIT_RF, ("PHY_SetRFReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx), eRFPath(%#x)\n",

+	//	RegAddr, BitMask, Data, eRFPath));

+

+

+#ifdef CONFIG_USB_HCI

+	//PlatformAcquireMutex(&pHalData->mxRFOperate);

+#else

+	//_enter_critical(&pHalData->rf_lock, &irqL);

+#endif

+

+

+	// RF data is 12 bits only

+	if (BitMask != bRFRegOffsetMask)

+	{

+		Original_Value = phy_RFSerialRead(Adapter, eRFPath, RegAddr);

+		BitShift =  phy_CalculateBitShift(BitMask);

+		Data = ((Original_Value & (~BitMask)) | (Data<< BitShift));

+	}

+

+	phy_RFSerialWrite(Adapter, eRFPath, RegAddr, Data);

+

+

+#ifdef CONFIG_USB_HCI

+	//PlatformReleaseMutex(&pHalData->mxRFOperate);

+#else

+	//_exit_critical(&pHalData->rf_lock, &irqL);

+#endif

+

+	//PHY_QueryRFReg(Adapter,eRFPath,RegAddr,BitMask);

+	//RT_TRACE(COMP_RF, DBG_TRACE, ("<---PHY_SetRFReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx), eRFPath(%#x)\n",

+	//		RegAddr, BitMask, Data, eRFPath));

+

+}

+

+

+//

+// 3. Initial MAC/BB/RF config by reading MAC/BB/RF txt.

+//

+

+/*-----------------------------------------------------------------------------

+ * Function:    phy_ConfigMACWithParaFile()

+ *

+ * Overview:    This function read BB parameters from general file format, and do register

+ *			  Read/Write

+ *

+ * Input:      	PADAPTER		Adapter

+ *			ps1Byte 			pFileName

+ *

+ * Output:      NONE

+ *

+ * Return:      RT_STATUS_SUCCESS: configuration file exist

+ *

+ * Note: 		The format of MACPHY_REG.txt is different from PHY and RF.

+ *			[Register][Mask][Value]

+ *---------------------------------------------------------------------------*/

+static	int

+phy_ConfigMACWithParaFile(

+	IN	PADAPTER		Adapter,

+	IN	u8* 			pFileName

+)

+{

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);

+

+	int		rtStatus = _FAIL;

+

+	return rtStatus;

+}

+

+/*-----------------------------------------------------------------------------

+ * Function:    phy_ConfigMACWithHeaderFile()

+ *

+ * Overview:    This function read BB parameters from Header file we gen, and do register

+ *			  Read/Write

+ *

+ * Input:      	PADAPTER		Adapter

+ *			ps1Byte 			pFileName

+ *

+ * Output:      NONE

+ *

+ * Return:      RT_STATUS_SUCCESS: configuration file exist

+ *

+ * Note: 		The format of MACPHY_REG.txt is different from PHY and RF.

+ *			[Register][Mask][Value]

+ *---------------------------------------------------------------------------*/

+#ifndef CONFIG_PHY_SETTING_WITH_ODM

+static	int

+phy_ConfigMACWithHeaderFile(

+	IN	PADAPTER		Adapter

+)

+{

+	u32					i = 0;

+	u32					ArrayLength = 0;

+	u32*				ptrArray;

+	//HAL_DATA_TYPE			*pHalData = GET_HAL_DATA(Adapter);

+

+	//2008.11.06 Modified by tynli.

+	//RT_TRACE(COMP_INIT, DBG_LOUD, ("Read Rtl819XMACPHY_Array\n"));

+	ArrayLength = Rtl8188E_MAC_ArrayLength;

+	ptrArray = (u32*)Rtl8188E_MAC_Array;

+

+#ifdef CONFIG_IOL_MAC

+	{

+		struct xmit_frame	*xmit_frame;

+		if((xmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL)

+			return _FAIL;

+

+		for(i = 0 ;i < ArrayLength;i=i+2){ // Add by tynli for 2 column

+			rtw_IOL_append_WB_cmd(xmit_frame, ptrArray[i], (u8)ptrArray[i+1]);

+		}

+

+		return rtw_IOL_exec_cmds_sync(Adapter, xmit_frame, 1000,0);

+	}

+#else

+	for(i = 0 ;i < ArrayLength;i=i+2){ // Add by tynli for 2 column

+		rtw_write8(Adapter, ptrArray[i], (u8)ptrArray[i+1]);

+	}

+#endif

+

+	return _SUCCESS;

+

+}

+#endif //#ifndef CONFIG_PHY_SETTING_WITH_ODM

+

+/*-----------------------------------------------------------------------------

+ * Function:    PHY_MACConfig8192C

+ *

+ * Overview:	Condig MAC by header file or parameter file.

+ *

+ * Input:       NONE

+ *

+ * Output:      NONE

+ *

+ * Return:      NONE

+ *

+ * Revised History:

+ *  When		Who		Remark

+ *  08/12/2008	MHC		Create Version 0.

+ *

+ *---------------------------------------------------------------------------*/

+s32 PHY_MACConfig8188E(PADAPTER Adapter)

+{

+	int		rtStatus = _SUCCESS;

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);

+	s8			*pszMACRegFile;

+	s8			sz8188EMACRegFile[] = RTL8188E_PHY_MACREG;

+

+	pszMACRegFile = sz8188EMACRegFile;

+

+	//

+	// Config MAC

+	//

+#ifdef CONFIG_EMBEDDED_FWIMG

+	#ifdef CONFIG_PHY_SETTING_WITH_ODM

+	if(HAL_STATUS_FAILURE == ODM_ConfigMACWithHeaderFile(&pHalData->odmpriv))

+		rtStatus = _FAIL;

+	#else

+	rtStatus = phy_ConfigMACWithHeaderFile(Adapter);

+	#endif//#ifdef CONFIG_PHY_SETTING_WITH_ODM

+#else

+

+	// Not make sure EEPROM, add later

+	//RT_TRACE(COMP_INIT, DBG_LOUD, ("Read MACREG.txt\n"));

+	rtStatus = phy_ConfigMACWithParaFile(Adapter, pszMACRegFile);	

+#endif//CONFIG_EMBEDDED_FWIMG

+

+

+	// 2010.07.13 AMPDU aggregation number B

+	rtw_write16(Adapter, REG_MAX_AGGR_NUM, MAX_AGGR_NUM);

+	//rtw_write8(Adapter, REG_MAX_AGGR_NUM, 0x0B); 

+

+	return rtStatus;

+

+}

+

+

+/**

+* Function:	phy_InitBBRFRegisterDefinition

+*

+* OverView:	Initialize Register definition offset for Radio Path A/B/C/D

+*

+* Input:

+*			PADAPTER		Adapter,

+*

+* Output:	None

+* Return:		None

+* Note:		The initialization value is constant and it should never be changes

+*/

+static	VOID

+phy_InitBBRFRegisterDefinition(

+	IN	PADAPTER		Adapter

+)

+{

+	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(Adapter);

+

+	// RF Interface Sowrtware Control

+	pHalData->PHYRegDef[RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870

+	pHalData->PHYRegDef[RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872)

+	pHalData->PHYRegDef[RF_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 LSBs if read 32-bit from 0x874

+	pHalData->PHYRegDef[RF_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876)

+

+	// RF Interface Readback Value

+	pHalData->PHYRegDef[RF_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0	

+	pHalData->PHYRegDef[RF_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2)

+	pHalData->PHYRegDef[RF_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 LSBs if read 32-bit from 0x8E4

+	pHalData->PHYRegDef[RF_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6)

+

+	// RF Interface Output (and Enable)

+	pHalData->PHYRegDef[RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860

+	pHalData->PHYRegDef[RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x864

+

+	// RF Interface (Output and)  Enable

+	pHalData->PHYRegDef[RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862)

+	pHalData->PHYRegDef[RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866)

+

+	//Addr of LSSI. Wirte RF register by driver

+	pHalData->PHYRegDef[RF_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter

+	pHalData->PHYRegDef[RF_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;

+

+	// RF parameter

+	pHalData->PHYRegDef[RF_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter;  //BB Band Select

+	pHalData->PHYRegDef[RF_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;

+	pHalData->PHYRegDef[RF_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;

+	pHalData->PHYRegDef[RF_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;

+

+	// Tx AGC Gain Stage (same for all path. Should we remove this?)

+	pHalData->PHYRegDef[RF_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage

+	pHalData->PHYRegDef[RF_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage

+	pHalData->PHYRegDef[RF_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage

+	pHalData->PHYRegDef[RF_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage

+

+	// Tranceiver A~D HSSI Parameter-1

+	pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;  //wire control parameter1

+	pHalData->PHYRegDef[RF_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;  //wire control parameter1

+

+	// Tranceiver A~D HSSI Parameter-2

+	pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;  //wire control parameter2

+	pHalData->PHYRegDef[RF_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;  //wire control parameter2

+

+	// RF switch Control

+	pHalData->PHYRegDef[RF_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; //TR/Ant switch control

+	pHalData->PHYRegDef[RF_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;

+	pHalData->PHYRegDef[RF_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;

+	pHalData->PHYRegDef[RF_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;

+

+	// AGC control 1

+	pHalData->PHYRegDef[RF_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;

+	pHalData->PHYRegDef[RF_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;

+	pHalData->PHYRegDef[RF_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;

+	pHalData->PHYRegDef[RF_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;

+

+	// AGC control 2

+	pHalData->PHYRegDef[RF_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;

+	pHalData->PHYRegDef[RF_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;

+	pHalData->PHYRegDef[RF_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;

+	pHalData->PHYRegDef[RF_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;

+

+	// RX AFE control 1

+	pHalData->PHYRegDef[RF_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;

+	pHalData->PHYRegDef[RF_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;

+	pHalData->PHYRegDef[RF_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;

+	pHalData->PHYRegDef[RF_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;	

+

+	// RX AFE control 1

+	pHalData->PHYRegDef[RF_PATH_A].rfRxAFE = rOFDM0_XARxAFE;

+	pHalData->PHYRegDef[RF_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;

+	pHalData->PHYRegDef[RF_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;

+	pHalData->PHYRegDef[RF_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;	

+

+	// Tx AFE control 1

+	pHalData->PHYRegDef[RF_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;

+	pHalData->PHYRegDef[RF_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;

+	pHalData->PHYRegDef[RF_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;

+	pHalData->PHYRegDef[RF_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;	

+

+	// Tx AFE control 2

+	pHalData->PHYRegDef[RF_PATH_A].rfTxAFE = rOFDM0_XATxAFE;

+	pHalData->PHYRegDef[RF_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;

+	pHalData->PHYRegDef[RF_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;

+	pHalData->PHYRegDef[RF_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;	

+

+	// Tranceiver LSSI Readback SI mode

+	pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;

+	pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;

+	pHalData->PHYRegDef[RF_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;

+	pHalData->PHYRegDef[RF_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;	

+

+	// Tranceiver LSSI Readback PI mode

+	pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback;

+	pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback;

+	//pHalData->PHYRegDef[RF_PATH_C].rfLSSIReadBackPi = rFPGA0_XC_LSSIReadBack;

+	//pHalData->PHYRegDef[RF_PATH_D].rfLSSIReadBackPi = rFPGA0_XD_LSSIReadBack;	

+

+}

+

+

+/*-----------------------------------------------------------------------------

+ * Function:    phy_ConfigBBWithParaFile()

+ *

+ * Overview:    This function read BB parameters from general file format, and do register

+ *			  Read/Write

+ *

+ * Input:      	PADAPTER		Adapter

+ *			ps1Byte 			pFileName

+ *

+ * Output:      NONE

+ *

+ * Return:      RT_STATUS_SUCCESS: configuration file exist

+ *	2008/11/06	MH	For 92S we do not support silent reset now. Disable

+ *					parameter file compare!!!!!!??

+ *

+ *---------------------------------------------------------------------------*/

+static	int

+phy_ConfigBBWithParaFile(

+	IN	PADAPTER		Adapter,

+	IN	u8* 			pFileName

+)

+{

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);

+

+	int		rtStatus = _SUCCESS;

+

+	return rtStatus;

+}

+

+

+

+//****************************************

+// The following is for High Power PA

+//****************************************

+VOID

+phy_ConfigBBExternalPA(

+	IN	PADAPTER			Adapter

+)

+{

+#ifdef CONFIG_USB_HCI

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);

+	u16 i=0;

+	u32 temp=0;

+

+	if(!pHalData->ExternalPA)

+	{

+		return;

+	}

+

+	// 2010/10/19 MH According to Jenyu/EEChou 's opinion, we need not to execute the

+	// same code as SU. It is already updated in PHY_REG_1T_HP.txt.

+#if 0

+	PHY_SetBBReg(Adapter, 0xee8, BIT28, 1);

+	temp = PHY_QueryBBReg(Adapter, 0x860, bMaskDWord);

+	temp |= (BIT26|BIT21|BIT10|BIT5);

+	PHY_SetBBReg(Adapter, 0x860, bMaskDWord, temp);

+	PHY_SetBBReg(Adapter, 0x870, BIT10, 0);

+	PHY_SetBBReg(Adapter, 0xc80, bMaskDWord, 0x20000080);

+	PHY_SetBBReg(Adapter, 0xc88, bMaskDWord, 0x40000100);

+#endif

+

+#endif

+}

+

+/*-----------------------------------------------------------------------------

+ * Function:    phy_ConfigBBWithHeaderFile()

+ *

+ * Overview:    This function read BB parameters from general file format, and do register

+ *			  Read/Write

+ *

+ * Input:      	PADAPTER		Adapter

+ *			u1Byte 			ConfigType     0 => PHY_CONFIG

+ *										 1 =>AGC_TAB

+ *

+ * Output:      NONE

+ *

+ * Return:      RT_STATUS_SUCCESS: configuration file exist

+ *

+ *---------------------------------------------------------------------------*/

+#ifndef CONFIG_PHY_SETTING_WITH_ODM

+static	int

+phy_ConfigBBWithHeaderFile(

+	IN	PADAPTER		Adapter,

+	IN	u8 			ConfigType

+)

+{

+	int i;

+	u32*	Rtl819XPHY_REGArray_Table;

+	u32*	Rtl819XAGCTAB_Array_Table;

+	u16	PHY_REGArrayLen, AGCTAB_ArrayLen;

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);

+	DM_ODM_T 		*podmpriv = &pHalData->odmpriv;

+	int ret = _SUCCESS;

+

+

+	AGCTAB_ArrayLen = Rtl8188E_AGCTAB_1TArrayLength;

+	Rtl819XAGCTAB_Array_Table = (u32*)Rtl8188E_AGCTAB_1TArray;

+	PHY_REGArrayLen = Rtl8188E_PHY_REG_1TArrayLength;

+	Rtl819XPHY_REGArray_Table = (u32*)Rtl8188E_PHY_REG_1TArray;

+//	RT_TRACE(COMP_INIT, DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() phy:Rtl8188EAGCTAB_1TArray\n"));

+//	RT_TRACE(COMP_INIT, DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() agc:Rtl8188EPHY_REG_1TArray\n"));

+

+	if(ConfigType == CONFIG_BB_PHY_REG)

+	{

+		#ifdef CONFIG_IOL_BB_PHY_REG

+		{

+			struct xmit_frame	*xmit_frame;

+			u32 tmp_value;

+

+			if((xmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL) {

+				ret = _FAIL;

+				goto exit;

+			}

+

+			for(i=0;i<PHY_REGArrayLen;i=i+2)

+			{

+				tmp_value=Rtl819XPHY_REGArray_Table[i+1];

+				

+				if (Rtl819XPHY_REGArray_Table[i] == 0xfe)

+					rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 50);

+				else if (Rtl819XPHY_REGArray_Table[i] == 0xfd)

+					rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 5);

+				else if (Rtl819XPHY_REGArray_Table[i] == 0xfc)

+					rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 1);

+				else if (Rtl819XPHY_REGArray_Table[i] == 0xfb)

+					rtw_IOL_append_DELAY_US_cmd(xmit_frame, 50);

+				else if (Rtl819XPHY_REGArray_Table[i] == 0xfa)

+					rtw_IOL_append_DELAY_US_cmd(xmit_frame, 5);

+				else if (Rtl819XPHY_REGArray_Table[i] == 0xf9)

+					rtw_IOL_append_DELAY_US_cmd(xmit_frame, 1);

+				else if (Rtl819XPHY_REGArray_Table[i] == 0xa24)

+					podmpriv->RFCalibrateInfo.RegA24 = Rtl819XPHY_REGArray_Table[i+1];	

+

+				rtw_IOL_append_WD_cmd(xmit_frame, Rtl819XPHY_REGArray_Table[i], tmp_value);	

+				//RT_TRACE(COMP_INIT, DBG_TRACE, ("The Rtl819XPHY_REGArray_Table[0] is %lx Rtl819XPHY_REGArray[1] is %lx \n",Rtl819XPHY_REGArray_Table[i], Rtl819XPHY_REGArray_Table[i+1]));

+			}

+		

+			ret = rtw_IOL_exec_cmds_sync(Adapter, xmit_frame, 1000,0);

+		}

+		#else

+		for(i=0;i<PHY_REGArrayLen;i=i+2)

+		{

+			if (Rtl819XPHY_REGArray_Table[i] == 0xfe){

+				#ifdef CONFIG_LONG_DELAY_ISSUE

+				rtw_msleep_os(50);

+				#else

+				rtw_mdelay_os(50);

+				#endif

+			}

+			else if (Rtl819XPHY_REGArray_Table[i] == 0xfd)

+				rtw_mdelay_os(5);

+			else if (Rtl819XPHY_REGArray_Table[i] == 0xfc)

+				rtw_mdelay_os(1);

+			else if (Rtl819XPHY_REGArray_Table[i] == 0xfb)

+				rtw_udelay_os(50);

+			else if (Rtl819XPHY_REGArray_Table[i] == 0xfa)

+				rtw_udelay_os(5);

+			else if (Rtl819XPHY_REGArray_Table[i] == 0xf9)

+				rtw_udelay_os(1);

+			else if (Rtl819XPHY_REGArray_Table[i] == 0xa24)

+				podmpriv->RFCalibrateInfo.RegA24 = Rtl819XPHY_REGArray_Table[i+1];	

+				

+			PHY_SetBBReg(Adapter, Rtl819XPHY_REGArray_Table[i], bMaskDWord, Rtl819XPHY_REGArray_Table[i+1]);

+

+			// Add 1us delay between BB/RF register setting.

+			rtw_udelay_os(1);

+

+			//RT_TRACE(COMP_INIT, DBG_TRACE, ("The Rtl819XPHY_REGArray_Table[0] is %lx Rtl819XPHY_REGArray[1] is %lx \n",Rtl819XPHY_REGArray_Table[i], Rtl819XPHY_REGArray_Table[i+1]));

+		}

+		#endif

+		// for External PA

+		phy_ConfigBBExternalPA(Adapter);

+	}

+	else if(ConfigType == CONFIG_BB_AGC_TAB)

+	{

+		#ifdef CONFIG_IOL_BB_AGC_TAB

+		{

+			struct xmit_frame	*xmit_frame;

+

+			if((xmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL) {

+				ret = _FAIL;

+				goto exit;

+			}

+

+			for(i=0;i<AGCTAB_ArrayLen;i=i+2)

+			{

+				rtw_IOL_append_WD_cmd(xmit_frame, Rtl819XAGCTAB_Array_Table[i], Rtl819XAGCTAB_Array_Table[i+1]);							

+				//RT_TRACE(COMP_INIT, DBG_TRACE, ("The Rtl819XAGCTAB_Array_Table[0] is %lx Rtl819XPHY_REGArray[1] is %lx \n",Rtl819XAGCTAB_Array_Table[i], Rtl819XAGCTAB_Array_Table[i+1]));

+			}

+		

+			ret = rtw_IOL_exec_cmds_sync(Adapter, xmit_frame, 1000,0);

+		}

+		#else

+		for(i=0;i<AGCTAB_ArrayLen;i=i+2)

+		{

+			PHY_SetBBReg(Adapter, Rtl819XAGCTAB_Array_Table[i], bMaskDWord, Rtl819XAGCTAB_Array_Table[i+1]);

+

+			// Add 1us delay between BB/RF register setting.

+			rtw_udelay_os(1);

+

+			//RT_TRACE(COMP_INIT, DBG_TRACE, ("The Rtl819XAGCTAB_Array_Table[0] is %lx Rtl819XPHY_REGArray[1] is %lx \n",Rtl819XAGCTAB_Array_Table[i], Rtl819XAGCTAB_Array_Table[i+1]));

+		}

+		#endif

+	}

+

+exit:

+	return ret;

+}

+#endif //#ifndef CONFIG_PHY_SETTING_WITH_ODM

+

+VOID

+storePwrIndexDiffRateOffset(

+	IN	PADAPTER	Adapter,

+	IN	u32		RegAddr,

+	IN	u32		BitMask,

+	IN	u32		Data

+	)

+{

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);

+	

+	if(RegAddr == rTxAGC_A_Rate18_06)

+	{

+		pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][0] = Data;

+		//printk("MCSTxPowerLevelOriginalOffset[%d][0]-TxAGC_A_Rate18_06 = 0x%x\n", pHalData->pwrGroupCnt,

+		//	pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][0]);

+	}

+	if(RegAddr == rTxAGC_A_Rate54_24)

+	{

+		pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][1] = Data;

+		//printk("MCSTxPowerLevelOriginalOffset[%d][1]-TxAGC_A_Rate54_24 = 0x%x\n", pHalData->pwrGroupCnt,

+		//	pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][1]);

+	}

+	if(RegAddr == rTxAGC_A_CCK1_Mcs32)

+	{

+		pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][6] = Data;

+		//printk("MCSTxPowerLevelOriginalOffset[%d][6]-TxAGC_A_CCK1_Mcs32 = 0x%x\n", pHalData->pwrGroupCnt,

+		//	pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][6]);

+	}

+	if(RegAddr == rTxAGC_B_CCK11_A_CCK2_11 && BitMask == 0xffffff00)

+	{

+		pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][7] = Data;

+		//printk("MCSTxPowerLevelOriginalOffset[%d][7]-TxAGC_B_CCK11_A_CCK2_11 = 0x%x\n", pHalData->pwrGroupCnt,

+		//	pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][7]);

+	}

+	if(RegAddr == rTxAGC_A_Mcs03_Mcs00)

+	{

+		pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][2] = Data;

+		//printk("MCSTxPowerLevelOriginalOffset[%d][2]-TxAGC_A_Mcs03_Mcs00 = 0x%x\n", pHalData->pwrGroupCnt,

+		//	pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][2]);

+	}

+	if(RegAddr == rTxAGC_A_Mcs07_Mcs04)

+	{

+		pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][3] = Data;

+		//printk("MCSTxPowerLevelOriginalOffset[%d][3]-TxAGC_A_Mcs07_Mcs04 = 0x%x\n", pHalData->pwrGroupCnt,

+		//	pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][3]);

+	}

+	if(RegAddr == rTxAGC_A_Mcs11_Mcs08)

+	{

+		pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][4] = Data;

+		//printk("MCSTxPowerLevelOriginalOffset[%d][4]-TxAGC_A_Mcs11_Mcs08 = 0x%x\n", pHalData->pwrGroupCnt,

+		//	pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][4]);

+	}

+	if(RegAddr == rTxAGC_A_Mcs15_Mcs12)

+	{

+		pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][5] = Data;

+		//printk("MCSTxPowerLevelOriginalOffset[%d][5]-TxAGC_A_Mcs15_Mcs12 = 0x%x\n", pHalData->pwrGroupCnt,pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][5]);

+		if(pHalData->rf_type== RF_1T1R)

+		{

+			//printk("pwrGroupCnt = %d\n", pHalData->pwrGroupCnt);

+			pHalData->pwrGroupCnt++;			

+		}

+	}

+	if(RegAddr == rTxAGC_B_Rate18_06)

+	{

+		pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][8] = Data;

+		//printk("MCSTxPowerLevelOriginalOffset[%d][8]-TxAGC_B_Rate18_06 = 0x%x\n", pHalData->pwrGroupCnt,

+		//	pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][8]);

+	}

+	if(RegAddr == rTxAGC_B_Rate54_24)

+	{

+		pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][9] = Data;

+		//printk("MCSTxPowerLevelOriginalOffset[%d][9]-TxAGC_B_Rate54_24 = 0x%x\n", pHalData->pwrGroupCnt,

+		//	pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][9]);

+	}

+	if(RegAddr == rTxAGC_B_CCK1_55_Mcs32)

+	{

+		pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][14] = Data;

+		//printk("MCSTxPowerLevelOriginalOffset[%d][14]-TxAGC_B_CCK1_55_Mcs32 = 0x%x\n", pHalData->pwrGroupCnt,

+		//	pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][14]);

+	}

+	if(RegAddr == rTxAGC_B_CCK11_A_CCK2_11 && BitMask == 0x000000ff)

+	{

+		pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][15] = Data;

+		//printk("MCSTxPowerLevelOriginalOffset[%d][15]-TxAGC_B_CCK11_A_CCK2_11 = 0x%x\n", pHalData->pwrGroupCnt,

+		//	pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][15]);

+	}

+	if(RegAddr == rTxAGC_B_Mcs03_Mcs00)

+	{

+		pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][10] = Data;

+		//printk("MCSTxPowerLevelOriginalOffset[%d][10]-TxAGC_B_Mcs03_Mcs00 = 0x%x\n", pHalData->pwrGroupCnt,

+		//	pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][10]);

+	}

+	if(RegAddr == rTxAGC_B_Mcs07_Mcs04)

+	{

+		pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][11] = Data;

+		//printk("MCSTxPowerLevelOriginalOffset[%d][11]-TxAGC_B_Mcs07_Mcs04 = 0x%x\n", pHalData->pwrGroupCnt,

+		//	pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][11]);

+	}

+	if(RegAddr == rTxAGC_B_Mcs11_Mcs08)

+	{

+		pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][12] = Data;

+		//printk("MCSTxPowerLevelOriginalOffset[%d][12]-TxAGC_B_Mcs11_Mcs08 = 0x%x\n", pHalData->pwrGroupCnt,

+		//	pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][12]);

+	}

+	if(RegAddr == rTxAGC_B_Mcs15_Mcs12)

+	{

+		pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][13] = Data;

+		//printk("MCSTxPowerLevelOriginalOffset[%d][13]-TxAGC_B_Mcs15_Mcs12 = 0x%x\n", pHalData->pwrGroupCnt,

+		//	pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][13]);

+		

+		if(pHalData->rf_type != RF_1T1R)

+		{

+			//printk("pwrGroupCnt = %d\n", pHalData->pwrGroupCnt);	

+			pHalData->pwrGroupCnt++;

+		}

+	}

+}

+/*-----------------------------------------------------------------------------

+ * Function:	phy_ConfigBBWithPgParaFile

+ *

+ * Overview:

+ *

+ * Input:       NONE

+ *

+ * Output:      NONE

+ *

+ * Return:      NONE

+ *

+ * Revised History:

+ * When			Who		Remark

+ * 11/06/2008 	MHC		Create Version 0.

+ * 2009/07/29	tynli		(porting from 92SE branch)2009/03/11 Add copy parameter file to buffer for silent reset

+ *---------------------------------------------------------------------------*/

+static	int

+phy_ConfigBBWithPgParaFile(

+	IN	PADAPTER		Adapter,

+	IN	u8* 			pFileName)

+{

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);

+

+	int		rtStatus = _SUCCESS;

+

+

+	return rtStatus;

+

+}	/* phy_ConfigBBWithPgParaFile */

+

+#ifndef CONFIG_PHY_SETTING_WITH_ODM

+/*-----------------------------------------------------------------------------

+ * Function:	phy_ConfigBBWithPgHeaderFile

+ *

+ * Overview:	Config PHY_REG_PG array

+ *

+ * Input:       NONE

+ *

+ * Output:      NONE

+ *

+ * Return:      NONE

+ *

+ * Revised History:

+ * When			Who		Remark

+ * 11/06/2008 	MHC		Add later!!!!!!.. Please modify for new files!!!!

+ * 11/10/2008	tynli		Modify to mew files.

+ *---------------------------------------------------------------------------*/

+static	int

+phy_ConfigBBWithPgHeaderFile(

+	IN	PADAPTER		Adapter,

+	IN	u8 			ConfigType)

+{

+	int i;

+	u32*	Rtl819XPHY_REGArray_Table_PG;

+	u16	PHY_REGArrayPGLen;

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);

+

+

+	PHY_REGArrayPGLen = Rtl8188E_PHY_REG_Array_PGLength;

+	Rtl819XPHY_REGArray_Table_PG = (u32*)Rtl8188E_PHY_REG_Array_PG;

+

+	if(ConfigType == CONFIG_BB_PHY_REG)

+	{

+		for(i=0;i<PHY_REGArrayPGLen;i=i+3)

+		{

+			#if 0 //without IO, no delay is neeeded...

+			if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfe){

+				#ifdef CONFIG_LONG_DELAY_ISSUE

+				rtw_msleep_os(50);

+				#else

+				rtw_mdelay_os(50);

+				#endif

+			}

+			else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfd)

+				rtw_mdelay_os(5);

+			else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfc)

+				rtw_mdelay_os(1);

+			else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfb)

+				rtw_udelay_os(50);

+			else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfa)

+				rtw_udelay_os(5);

+			else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xf9)

+				rtw_udelay_os(1);

+			//PHY_SetBBReg(Adapter, Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1], Rtl819XPHY_REGArray_Table_PG[i+2]);		

+			#endif

+			

+			storePwrIndexDiffRateOffset(Adapter, Rtl819XPHY_REGArray_Table_PG[i],

+				Rtl819XPHY_REGArray_Table_PG[i+1],

+				Rtl819XPHY_REGArray_Table_PG[i+2]);

+			//PHY_SetBBReg(Adapter, Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1], Rtl819XPHY_REGArray_Table_PG[i+2]);

+			//RT_TRACE(COMP_SEND, DBG_TRACE, ("The Rtl819XPHY_REGArray_Table_PG[0] is %lx Rtl819XPHY_REGArray_Table_PG[1] is %lx \n",Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1]));

+		}

+	}

+	else

+	{

+

+		//RT_TRACE(COMP_SEND, DBG_LOUD, ("phy_ConfigBBWithPgHeaderFile(): ConfigType != CONFIG_BB_PHY_REG\n"));

+	}

+

+	return _SUCCESS;

+

+}	/* phy_ConfigBBWithPgHeaderFile */

+#endif //CONFIG_PHY_SETTING_WITH_ODM

+

+

+

+static VOID

+phy_BB8192C_Config_1T(

+	IN PADAPTER Adapter

+	)

+{

+#if 0

+	//for path - A

+	PHY_SetBBReg(Adapter, rFPGA0_TxInfo, 0x3, 0x1);

+	PHY_SetBBReg(Adapter, rFPGA1_TxInfo, 0x0303, 0x0101);

+	PHY_SetBBReg(Adapter, 0xe74, 0x0c000000, 0x1);

+	PHY_SetBBReg(Adapter, 0xe78, 0x0c000000, 0x1);

+	PHY_SetBBReg(Adapter, 0xe7c, 0x0c000000, 0x1);

+	PHY_SetBBReg(Adapter, 0xe80, 0x0c000000, 0x1);

+	PHY_SetBBReg(Adapter, 0xe88, 0x0c000000, 0x1);

+#endif

+	//for path - B

+	PHY_SetBBReg(Adapter, rFPGA0_TxInfo, 0x3, 0x2);

+	PHY_SetBBReg(Adapter, rFPGA1_TxInfo, 0x300033, 0x200022);

+

+	// 20100519 Joseph: Add for 1T2R config. Suggested by Kevin, Jenyu and Yunan.

+	PHY_SetBBReg(Adapter, rCCK0_AFESetting, bMaskByte3, 0x45);

+	PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, bMaskByte0, 0x23);

+	PHY_SetBBReg(Adapter, rOFDM0_AGCParameter1, 0x30, 0x1);	// B path first AGC

+

+	PHY_SetBBReg(Adapter, 0xe74, 0x0c000000, 0x2);

+	PHY_SetBBReg(Adapter, 0xe78, 0x0c000000, 0x2);

+	PHY_SetBBReg(Adapter, 0xe7c, 0x0c000000, 0x2);

+	PHY_SetBBReg(Adapter, 0xe80, 0x0c000000, 0x2);

+	PHY_SetBBReg(Adapter, 0xe88, 0x0c000000, 0x2);

+

+

+}

+

+// Joseph test: new initialize order!!

+// Test only!! This part need to be re-organized.

+// Now it is just for 8256.

+static	int

+phy_BB8190_Config_HardCode(

+	IN	PADAPTER	Adapter

+	)

+{

+	//RT_ASSERT(FALSE, ("This function is not implement yet!! \n"));

+	return _SUCCESS;

+}

+

+static	int

+phy_BB8188E_Config_ParaFile(

+	IN	PADAPTER	Adapter

+	)

+{

+	EEPROM_EFUSE_PRIV	*pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter);

+	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(Adapter);

+	int			rtStatus = _SUCCESS;

+

+	u8	sz8188EBBRegFile[] = RTL8188E_PHY_REG;

+	u8	sz8188EAGCTableFile[] = RTL8188E_AGC_TAB;

+	u8	sz8188EBBRegPgFile[] = RTL8188E_PHY_REG_PG;

+	u8	sz8188EBBRegMpFile[] = RTL8188E_PHY_REG_MP;

+

+	u8	*pszBBRegFile = NULL, *pszAGCTableFile = NULL, *pszBBRegPgFile = NULL, *pszBBRegMpFile=NULL;

+

+

+	//RT_TRACE(COMP_INIT, DBG_TRACE, ("==>phy_BB8192S_Config_ParaFile\n"));

+

+	pszBBRegFile = sz8188EBBRegFile ;

+	pszAGCTableFile = sz8188EAGCTableFile;

+	pszBBRegPgFile = sz8188EBBRegPgFile;

+	pszBBRegMpFile = sz8188EBBRegMpFile;

+

+	//

+	// 1. Read PHY_REG.TXT BB INIT!!

+	// We will seperate as 88C / 92C according to chip version

+	//

+#ifdef CONFIG_EMBEDDED_FWIMG

+	#ifdef CONFIG_PHY_SETTING_WITH_ODM

+	if(HAL_STATUS_FAILURE ==ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG))

+		rtStatus = _FAIL;

+	#else

+	rtStatus = phy_ConfigBBWithHeaderFile(Adapter, CONFIG_BB_PHY_REG);

+	#endif//#ifdef CONFIG_PHY_SETTING_WITH_ODM

+#else

+	// No matter what kind of CHIP we always read PHY_REG.txt. We must copy different

+	// type of parameter files to phy_reg.txt at first.

+	rtStatus = phy_ConfigBBWithParaFile(Adapter,pszBBRegFile);

+#endif//#ifdef CONFIG_EMBEDDED_FWIMG

+

+	if(rtStatus != _SUCCESS){

+		//RT_TRACE(COMP_INIT, DBG_SERIOUS, ("phy_BB8192S_Config_ParaFile():Write BB Reg Fail!!"));

+		goto phy_BB8190_Config_ParaFile_Fail;

+	}

+

+	//

+	// 20100318 Joseph: Config 2T2R to 1T2R if necessary.

+	//

+	//if(pHalData->rf_type == RF_1T2R)

+	//{

+		//phy_BB8192C_Config_1T(Adapter);

+		//DBG_8192C("phy_BB8188E_Config_ParaFile():Config to 1T!!\n");

+	//}

+

+	//

+	// 2. If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt

+	//

+	if (pEEPROM->bautoload_fail_flag == _FALSE)

+	{

+		pHalData->pwrGroupCnt = 0;

+

+#ifdef CONFIG_EMBEDDED_FWIMG

+		#ifdef CONFIG_PHY_SETTING_WITH_ODM	

+		if(HAL_STATUS_FAILURE ==ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG_PG))

+			rtStatus = _FAIL;

+		#else

+		rtStatus = phy_ConfigBBWithPgHeaderFile(Adapter, CONFIG_BB_PHY_REG_PG);

+		#endif

+#else

+		rtStatus = phy_ConfigBBWithPgParaFile(Adapter, pszBBRegPgFile);

+#endif

+	}

+

+	if(rtStatus != _SUCCESS){

+		//RT_TRACE(COMP_INIT, DBG_SERIOUS, ("phy_BB8192S_Config_ParaFile():BB_PG Reg Fail!!"));

+		goto phy_BB8190_Config_ParaFile_Fail;

+	}

+

+	//

+	// 3. BB AGC table Initialization

+	//

+#ifdef CONFIG_EMBEDDED_FWIMG

+	#ifdef CONFIG_PHY_SETTING_WITH_ODM	

+	if(HAL_STATUS_FAILURE ==ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv,  CONFIG_BB_AGC_TAB))

+		rtStatus = _FAIL;

+	#else

+	rtStatus = phy_ConfigBBWithHeaderFile(Adapter, CONFIG_BB_AGC_TAB);

+	#endif//#ifdef CONFIG_PHY_SETTING_WITH_ODM	

+#else

+	//RT_TRACE(COMP_INIT, DBG_LOUD, ("phy_BB8192S_Config_ParaFile AGC_TAB.txt\n"));

+	rtStatus = phy_ConfigBBWithParaFile(Adapter, pszAGCTableFile);

+#endif//#ifdef CONFIG_EMBEDDED_FWIMG

+

+	if(rtStatus != _SUCCESS){

+		//RT_TRACE(COMP_FPGA, DBG_SERIOUS, ("phy_BB8192S_Config_ParaFile():AGC Table Fail\n"));

+		goto phy_BB8190_Config_ParaFile_Fail;

+	}

+

+

+phy_BB8190_Config_ParaFile_Fail:

+

+	return rtStatus;

+}

+

+

+int

+PHY_BBConfig8188E(

+	IN	PADAPTER	Adapter

+	)

+{

+	int	rtStatus = _SUCCESS;

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);

+	u32	RegVal;

+	u8	TmpU1B=0;

+	u8	value8,CrystalCap;

+

+	phy_InitBBRFRegisterDefinition(Adapter);

+

+

+	// Enable BB and RF

+	RegVal = rtw_read16(Adapter, REG_SYS_FUNC_EN);

+	rtw_write16(Adapter, REG_SYS_FUNC_EN, (u16)(RegVal|BIT13|BIT0|BIT1));

+

+	// 20090923 Joseph: Advised by Steven and Jenyu. Power sequence before init RF.

+	//rtw_write8(Adapter, REG_AFE_PLL_CTRL, 0x83);

+	//rtw_write8(Adapter, REG_AFE_PLL_CTRL+1, 0xdb);

+

+	rtw_write8(Adapter, REG_RF_CTRL, RF_EN|RF_RSTB|RF_SDMRSTB);

+

+#ifdef CONFIG_USB_HCI

+	rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_USBA | FEN_USBD | FEN_BB_GLB_RSTn | FEN_BBRSTB);

+#else

+	rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_PPLL|FEN_PCIEA|FEN_DIO_PCIE|FEN_BB_GLB_RSTn|FEN_BBRSTB);

+#endif

+

+#if 0

+#ifdef CONFIG_USB_HCI

+	//To Fix MAC loopback mode fail. Suggested by SD4 Johnny. 2010.03.23.

+	rtw_write8(Adapter, REG_LDOHCI12_CTRL, 0x0f);

+	rtw_write8(Adapter, 0x15, 0xe9);

+#endif

+

+	rtw_write8(Adapter, REG_AFE_XTAL_CTRL+1, 0x80);

+#endif

+

+#ifdef CONFIG_USB_HCI

+		//rtw_write8(Adapter, 0x15, 0xe9);

+#endif

+

+

+#ifdef CONFIG_PCI_HCI

+	// Force use left antenna by default for 88C.

+	//	if(!IS_92C_SERIAL(pHalData->VersionID) || IS_92C_1T2R(pHalData->VersionID))

+	if(Adapter->ledpriv.LedStrategy != SW_LED_MODE10)

+	{

+		RegVal = rtw_read32(Adapter, REG_LEDCFG0);

+		rtw_write32(Adapter, REG_LEDCFG0, RegVal|BIT23);

+	}

+#endif

+

+	//

+	// Config BB and AGC

+	//

+	rtStatus = phy_BB8188E_Config_ParaFile(Adapter);

+	

+	// write 0x24[16:11] = 0x24[22:17] = CrystalCap

+	CrystalCap = pHalData->CrystalCap & 0x3F;

+	PHY_SetBBReg(Adapter, REG_AFE_XTAL_CTRL, 0x7ff800, (CrystalCap | (CrystalCap << 6)));

+

+	return rtStatus;

+	

+}

+

+

+int

+PHY_RFConfig8188E(

+	IN	PADAPTER	Adapter

+	)

+{

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);

+	int		rtStatus = _SUCCESS;

+

+	//

+	// RF config

+	//

+	rtStatus = PHY_RF6052_Config8188E(Adapter);

+#if 0

+	switch(pHalData->rf_chip)

+	{

+		case RF_6052:

+			rtStatus = PHY_RF6052_Config(Adapter);

+			break;

+		case RF_8225:

+			rtStatus = PHY_RF8225_Config(Adapter);

+			break;

+		case RF_8256:

+			rtStatus = PHY_RF8256_Config(Adapter);

+			break;

+		case RF_8258:

+			break;

+		case RF_PSEUDO_11N:

+			rtStatus = PHY_RF8225_Config(Adapter);

+			break;

+		default: //for MacOs Warning: "RF_TYPE_MIN" not handled in switch

+			break;

+	}

+#endif

+	return rtStatus;

+}

+

+

+/*-----------------------------------------------------------------------------

+ * Function:    PHY_ConfigRFWithParaFile()

+ *

+ * Overview:    This function read RF parameters from general file format, and do RF 3-wire

+ *

+ * Input:      	PADAPTER			Adapter

+ *			ps1Byte 				pFileName

+ *			RF_RADIO_PATH_E	eRFPath

+ *

+ * Output:      NONE

+ *

+ * Return:      RT_STATUS_SUCCESS: configuration file exist

+ *

+ * Note:		Delay may be required for RF configuration

+ *---------------------------------------------------------------------------*/

+int

+rtl8188e_PHY_ConfigRFWithParaFile(

+	IN	PADAPTER			Adapter,

+	IN	u8* 				pFileName,

+	RF_RADIO_PATH_E		eRFPath

+)

+{

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);

+

+	int	rtStatus = _SUCCESS;

+

+

+	return rtStatus;

+

+}

+

+//****************************************

+// The following is for High Power PA

+//****************************************

+#define HighPowerRadioAArrayLen 22

+//This is for High power PA

+u32 Rtl8192S_HighPower_RadioA_Array[HighPowerRadioAArrayLen] = {

+0x013,0x00029ea4,

+0x013,0x00025e74,

+0x013,0x00020ea4,

+0x013,0x0001ced0,

+0x013,0x00019f40,

+0x013,0x00014e70,

+0x013,0x000106a0,

+0x013,0x0000c670,

+0x013,0x000082a0,

+0x013,0x00004270,

+0x013,0x00000240,

+};

+

+int

+PHY_ConfigRFExternalPA(

+	IN	PADAPTER			Adapter,

+	RF_RADIO_PATH_E		eRFPath

+)

+{

+	int	rtStatus = _SUCCESS;

+#ifdef CONFIG_USB_HCI

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);

+	u16 i=0;

+

+	if(!pHalData->ExternalPA)

+	{

+		return rtStatus;

+	}

+

+	// 2010/10/19 MH According to Jenyu/EEChou 's opinion, we need not to execute the

+	// same code as SU. It is already updated in radio_a_1T_HP.txt.

+#if 0

+	//add for SU High Power PA

+	for(i = 0;i<HighPowerRadioAArrayLen; i=i+2)

+	{

+		RT_TRACE(COMP_INIT, DBG_LOUD, ("External PA, write RF 0x%lx=0x%lx\n", Rtl8192S_HighPower_RadioA_Array[i], Rtl8192S_HighPower_RadioA_Array[i+1]));

+		PHY_SetRFReg(Adapter, eRFPath, Rtl8192S_HighPower_RadioA_Array[i], bRFRegOffsetMask, Rtl8192S_HighPower_RadioA_Array[i+1]);

+	}

+#endif

+

+#endif

+	return rtStatus;

+}

+//****************************************

+/*-----------------------------------------------------------------------------

+ * Function:    PHY_ConfigRFWithHeaderFile()

+ *

+ * Overview:    This function read RF parameters from general file format, and do RF 3-wire

+ *

+ * Input:      	PADAPTER			Adapter

+ *			ps1Byte 				pFileName

+ *			RF_RADIO_PATH_E	eRFPath

+ *

+ * Output:      NONE

+ *

+ * Return:      RT_STATUS_SUCCESS: configuration file exist

+ *

+ * Note:		Delay may be required for RF configuration

+ *---------------------------------------------------------------------------*/

+#ifndef CONFIG_PHY_SETTING_WITH_ODM

+int

+rtl8188e_PHY_ConfigRFWithHeaderFile(

+	IN	PADAPTER			Adapter,

+	RF_RADIO_PATH_E			eRFPath

+)

+{

+

+	int			i;

+	int			rtStatus = _SUCCESS;

+	u32*		Rtl819XRadioA_Array_Table;

+	u32*		Rtl819XRadioB_Array_Table;

+	u16		RadioA_ArrayLen,RadioB_ArrayLen;

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);

+

+

+	RadioA_ArrayLen = Rtl8188E_RadioA_1TArrayLength;

+	Rtl819XRadioA_Array_Table = (u32*)Rtl8188E_RadioA_1TArray;

+	RadioB_ArrayLen = Rtl8188E_RadioB_1TArrayLength;

+	Rtl819XRadioB_Array_Table = (u32*)Rtl8188E_RadioB_1TArray;

+//	RT_TRACE(COMP_INIT, DBG_LOUD, (" ===> PHY_ConfigRFWithHeaderFile() Radio_A:Rtl8188ERadioA_1TArray\n"));

+//	RT_TRACE(COMP_INIT, DBG_LOUD, (" ===> PHY_ConfigRFWithHeaderFile() Radio_B:Rtl8188ERadioB_1TArray\n"));

+

+	switch (eRFPath)

+	{

+		case RF_PATH_A:

+                    #ifdef CONFIG_IOL_RF_RF_PATH_A

+			{

+				struct xmit_frame	*xmit_frame;

+				if((xmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL) {

+					rtStatus = _FAIL;

+					goto exit;

+				}

+

+				for(i = 0;i<RadioA_ArrayLen; i=i+2)

+				{

+					if(Rtl819XRadioA_Array_Table[i] == 0xfe)

+						rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 50);

+					else if (Rtl819XRadioA_Array_Table[i] == 0xfd)

+						rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 5);

+					else if (Rtl819XRadioA_Array_Table[i] == 0xfc)

+						rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 1);

+					else if (Rtl819XRadioA_Array_Table[i] == 0xfb)

+						rtw_IOL_append_DELAY_US_cmd(xmit_frame, 50);

+					else if (Rtl819XRadioA_Array_Table[i] == 0xfa)

+						rtw_IOL_append_DELAY_US_cmd(xmit_frame, 5);

+					else if (Rtl819XRadioA_Array_Table[i] == 0xf9)

+						rtw_IOL_append_DELAY_US_cmd(xmit_frame, 1);

+					else

+					{

+						BB_REGISTER_DEFINITION_T	*pPhyReg = &pHalData->PHYRegDef[eRFPath];

+						u32	NewOffset = 0;

+						u32	DataAndAddr = 0;

+

+						NewOffset = Rtl819XRadioA_Array_Table[i] & 0x3f;

+						DataAndAddr = ((NewOffset<<20) | (Rtl819XRadioA_Array_Table[i+1]&0x000fffff)) & 0x0fffffff;	// T65 RF

+						rtw_IOL_append_WD_cmd(xmit_frame, pPhyReg->rf3wireOffset, DataAndAddr);

+					}

+				}

+				rtStatus = rtw_IOL_exec_cmds_sync(Adapter, xmit_frame, 1000,0);

+			}

+			#else

+			for(i = 0;i<RadioA_ArrayLen; i=i+2)

+			{

+				if(Rtl819XRadioA_Array_Table[i] == 0xfe) {

+					#ifdef CONFIG_LONG_DELAY_ISSUE

+					rtw_msleep_os(50);

+					#else

+					rtw_mdelay_os(50);

+					#endif

+				}

+				else if (Rtl819XRadioA_Array_Table[i] == 0xfd)

+					rtw_mdelay_os(5);

+				else if (Rtl819XRadioA_Array_Table[i] == 0xfc)

+					rtw_mdelay_os(1);

+				else if (Rtl819XRadioA_Array_Table[i] == 0xfb)

+					rtw_udelay_os(50);

+				else if (Rtl819XRadioA_Array_Table[i] == 0xfa)

+					rtw_udelay_os(5);

+				else if (Rtl819XRadioA_Array_Table[i] == 0xf9)

+					rtw_udelay_os(1);

+				else

+				{

+					PHY_SetRFReg(Adapter, eRFPath, Rtl819XRadioA_Array_Table[i], bRFRegOffsetMask, Rtl819XRadioA_Array_Table[i+1]);

+					// Add 1us delay between BB/RF register setting.

+					rtw_udelay_os(1);

+				}

+			}

+			#endif

+			//Add for High Power PA

+			PHY_ConfigRFExternalPA(Adapter, eRFPath);

+			break;

+		case RF_PATH_B:

+                    #ifdef CONFIG_IOL_RF_RF_PATH_B

+			{

+				struct xmit_frame	*xmit_frame;

+				if((xmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL) {

+					rtStatus = _FAIL;

+					goto exit;

+				}

+

+				for(i = 0;i<RadioB_ArrayLen; i=i+2)

+				{

+					if(Rtl819XRadioB_Array_Table[i] == 0xfe)

+						rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 50);

+					else if (Rtl819XRadioB_Array_Table[i] == 0xfd)

+						rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 5);

+					else if (Rtl819XRadioB_Array_Table[i] == 0xfc)

+						rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 1);

+					else if (Rtl819XRadioB_Array_Table[i] == 0xfb)

+						rtw_IOL_append_DELAY_US_cmd(xmit_frame, 50);

+					else if (Rtl819XRadioB_Array_Table[i] == 0xfa)

+						rtw_IOL_append_DELAY_US_cmd(xmit_frame, 5);

+					else if (Rtl819XRadioB_Array_Table[i] == 0xf9)

+						rtw_IOL_append_DELAY_US_cmd(xmit_frame, 1);

+					else

+					{

+						BB_REGISTER_DEFINITION_T	*pPhyReg = &pHalData->PHYRegDef[eRFPath];

+						u32	NewOffset = 0;

+						u32	DataAndAddr = 0;

+

+						NewOffset = Rtl819XRadioB_Array_Table[i] & 0x3f;

+						DataAndAddr = ((NewOffset<<20) | (Rtl819XRadioB_Array_Table[i+1]&0x000fffff)) & 0x0fffffff;	// T65 RF

+						rtw_IOL_append_WD_cmd(xmit_frame, pPhyReg->rf3wireOffset, DataAndAddr);

+					}

+				}

+				rtStatus = rtw_IOL_exec_cmds_sync(Adapter, xmit_frame, 1000,0);

+			}

+			#else

+			for(i = 0;i<RadioB_ArrayLen; i=i+2)

+			{

+				if(Rtl819XRadioB_Array_Table[i] == 0xfe)

+				{ // Deay specific ms. Only RF configuration require delay.

+#if 0//#ifdef CONFIG_USB_HCI

+					#ifdef CONFIG_LONG_DELAY_ISSUE

+					rtw_msleep_os(1000);

+					#else

+					rtw_mdelay_os(1000);

+					#endif

+#else

+					#ifdef CONFIG_LONG_DELAY_ISSUE

+					rtw_msleep_os(50);

+					#else

+					rtw_mdelay_os(50);

+					#endif

+#endif

+				}

+				else if (Rtl819XRadioB_Array_Table[i] == 0xfd)

+					rtw_mdelay_os(5);

+				else if (Rtl819XRadioB_Array_Table[i] == 0xfc)

+					rtw_mdelay_os(1);

+				else if (Rtl819XRadioB_Array_Table[i] == 0xfb)

+					rtw_udelay_os(50);

+				else if (Rtl819XRadioB_Array_Table[i] == 0xfa)

+					rtw_udelay_os(5);

+				else if (Rtl819XRadioB_Array_Table[i] == 0xf9)

+					rtw_udelay_os(1);

+				else

+				{

+					PHY_SetRFReg(Adapter, eRFPath, Rtl819XRadioB_Array_Table[i], bRFRegOffsetMask, Rtl819XRadioB_Array_Table[i+1]);

+					// Add 1us delay between BB/RF register setting.

+					rtw_udelay_os(1);

+				}

+			}

+			#endif

+			break;

+		case RF_PATH_C:

+			break;

+		case RF_PATH_D:

+			break;

+	}

+

+exit:

+	return rtStatus;

+

+}

+#endif//#ifndef CONFIG_PHY_SETTING_WITH_ODM

+

+/*-----------------------------------------------------------------------------

+ * Function:    PHY_CheckBBAndRFOK()

+ *

+ * Overview:    This function is write register and then readback to make sure whether

+ *			  BB[PHY0, PHY1], RF[Patha, path b, path c, path d] is Ok

+ *

+ * Input:      	PADAPTER			Adapter

+ *			HW90_BLOCK_E		CheckBlock

+ *			RF_RADIO_PATH_E	eRFPath		// it is used only when CheckBlock is HW90_BLOCK_RF

+ *

+ * Output:      NONE

+ *

+ * Return:      RT_STATUS_SUCCESS: PHY is OK

+ *

+ * Note:		This function may be removed in the ASIC

+ *---------------------------------------------------------------------------*/

+int

+PHY_CheckBBAndRFOK(

+	IN	PADAPTER			Adapter,

+	IN	HW90_BLOCK_E		CheckBlock,

+	IN	RF_RADIO_PATH_E	eRFPath

+	)

+{

+	int			rtStatus = _SUCCESS;

+

+	u32				i, CheckTimes = 4,ulRegRead = 0;

+

+	u32				WriteAddr[4];

+	u32				WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};

+

+	// Initialize register address offset to be checked

+	WriteAddr[HW90_BLOCK_MAC] = 0x100;

+	WriteAddr[HW90_BLOCK_PHY0] = 0x900;

+	WriteAddr[HW90_BLOCK_PHY1] = 0x800;

+	WriteAddr[HW90_BLOCK_RF] = 0x3;

+

+	for(i=0 ; i < CheckTimes ; i++)

+	{

+

+		//

+		// Write Data to register and readback

+		//

+		switch(CheckBlock)

+		{

+		case HW90_BLOCK_MAC:

+			//RT_ASSERT(FALSE, ("PHY_CheckBBRFOK(): Never Write 0x100 here!"));

+			//RT_TRACE(COMP_INIT, DBG_LOUD, ("PHY_CheckBBRFOK(): Never Write 0x100 here!\n"));

+			break;

+

+		case HW90_BLOCK_PHY0:

+		case HW90_BLOCK_PHY1:

+			rtw_write32(Adapter, WriteAddr[CheckBlock], WriteData[i]);

+			ulRegRead = rtw_read32(Adapter, WriteAddr[CheckBlock]);

+			break;

+

+		case HW90_BLOCK_RF:

+			// When initialization, we want the delay function(delay_ms(), delay_us()

+			// ==> actually we call PlatformStallExecution()) to do NdisStallExecution()

+			// [busy wait] instead of NdisMSleep(). So we acquire RT_INITIAL_SPINLOCK

+			// to run at Dispatch level to achive it.

+			//cosa PlatformAcquireSpinLock(Adapter, RT_INITIAL_SPINLOCK);

+			WriteData[i] &= 0xfff;

+			PHY_SetRFReg(Adapter, eRFPath, WriteAddr[HW90_BLOCK_RF], bRFRegOffsetMask, WriteData[i]);

+			// TODO: we should not delay for such a long time. Ask SD3

+			rtw_mdelay_os(10);

+			ulRegRead = PHY_QueryRFReg(Adapter, eRFPath, WriteAddr[HW90_BLOCK_RF], bMaskDWord);

+			rtw_mdelay_os(10);

+			//cosa PlatformReleaseSpinLock(Adapter, RT_INITIAL_SPINLOCK);

+			break;

+

+		default:

+			rtStatus = _FAIL;

+			break;

+		}

+

+

+		//

+		// Check whether readback data is correct

+		//

+		if(ulRegRead != WriteData[i])

+		{

+			//RT_TRACE(COMP_FPGA, DBG_LOUD, ("ulRegRead: %lx, WriteData: %lx \n", ulRegRead, WriteData[i]));

+			rtStatus = _FAIL;

+			break;

+		}

+	}

+

+	return rtStatus;

+}

+

+

+VOID

+rtl8192c_PHY_GetHWRegOriginalValue(

+	IN	PADAPTER		Adapter

+	)

+{

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);

+

+	// read rx initial gain

+	pHalData->DefaultInitialGain[0] = (u8)PHY_QueryBBReg(Adapter, rOFDM0_XAAGCCore1, bMaskByte0);

+	pHalData->DefaultInitialGain[1] = (u8)PHY_QueryBBReg(Adapter, rOFDM0_XBAGCCore1, bMaskByte0);

+	pHalData->DefaultInitialGain[2] = (u8)PHY_QueryBBReg(Adapter, rOFDM0_XCAGCCore1, bMaskByte0);

+	pHalData->DefaultInitialGain[3] = (u8)PHY_QueryBBReg(Adapter, rOFDM0_XDAGCCore1, bMaskByte0);

+	//RT_TRACE(COMP_INIT, DBG_LOUD,

+	//("Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n",

+	//pHalData->DefaultInitialGain[0], pHalData->DefaultInitialGain[1],

+	//pHalData->DefaultInitialGain[2], pHalData->DefaultInitialGain[3]));

+

+	// read framesync

+	pHalData->framesync = (u8)PHY_QueryBBReg(Adapter, rOFDM0_RxDetector3, bMaskByte0);

+	pHalData->framesyncC34 = PHY_QueryBBReg(Adapter, rOFDM0_RxDetector2, bMaskDWord);

+	//RT_TRACE(COMP_INIT, DBG_LOUD, ("Default framesync (0x%x) = 0x%x \n",

+	//	rOFDM0_RxDetector3, pHalData->framesync));

+}

+

+

+//

+//	Description:

+//		Map dBm into Tx power index according to

+//		current HW model, for example, RF and PA, and

+//		current wireless mode.

+//	By Bruce, 2008-01-29.

+//

+static	u8

+phy_DbmToTxPwrIdx(

+	IN	PADAPTER		Adapter,

+	IN	WIRELESS_MODE	WirelessMode,

+	IN	int			PowerInDbm

+	)

+{

+	u8				TxPwrIdx = 0;

+	int				Offset = 0;

+

+

+	//

+	// Tested by MP, we found that CCK Index 0 equals to 8dbm, OFDM legacy equals to

+	// 3dbm, and OFDM HT equals to 0dbm repectively.

+	// Note:

+	//	The mapping may be different by different NICs. Do not use this formula for what needs accurate result.

+	// By Bruce, 2008-01-29.

+	//

+	switch(WirelessMode)

+	{

+	case WIRELESS_MODE_B:

+		Offset = -7;

+		break;

+

+	case WIRELESS_MODE_G:

+	case WIRELESS_MODE_N_24G:

+		Offset = -8;

+		break;

+	default:

+		Offset = -8;

+		break;

+	}

+

+	if((PowerInDbm - Offset) > 0)

+	{

+		TxPwrIdx = (u8)((PowerInDbm - Offset) * 2);

+	}

+	else

+	{

+		TxPwrIdx = 0;

+	}

+

+	// Tx Power Index is too large.

+	if(TxPwrIdx > MAX_TXPWR_IDX_NMODE_92S)

+		TxPwrIdx = MAX_TXPWR_IDX_NMODE_92S;

+

+	return TxPwrIdx;

+}

+

+//

+//	Description:

+//		Map Tx power index into dBm according to

+//		current HW model, for example, RF and PA, and

+//		current wireless mode.

+//	By Bruce, 2008-01-29.

+//

+int

+phy_TxPwrIdxToDbm(

+	IN	PADAPTER		Adapter,

+	IN	WIRELESS_MODE	WirelessMode,

+	IN	u8			TxPwrIdx

+	)

+{

+	int				Offset = 0;

+	int				PwrOutDbm = 0;

+

+	//

+	// Tested by MP, we found that CCK Index 0 equals to -7dbm, OFDM legacy equals to -8dbm.

+	// Note:

+	//	The mapping may be different by different NICs. Do not use this formula for what needs accurate result.

+	// By Bruce, 2008-01-29.

+	//

+	switch(WirelessMode)

+	{

+	case WIRELESS_MODE_B:

+		Offset = -7;

+		break;

+

+	case WIRELESS_MODE_G:

+	case WIRELESS_MODE_N_24G:

+		Offset = -8;

+	default:

+		Offset = -8;

+		break;

+	}

+

+	PwrOutDbm = TxPwrIdx / 2 + Offset; // Discard the decimal part.

+

+	return PwrOutDbm;

+}

+

+

+/*-----------------------------------------------------------------------------

+ * Function:    GetTxPowerLevel8190()

+ *

+ * Overview:    This function is export to "common" moudule

+ *

+ * Input:       PADAPTER		Adapter

+ *			psByte			Power Level

+ *

+ * Output:      NONE

+ *

+ * Return:      NONE

+ *

+ *---------------------------------------------------------------------------*/

+VOID

+PHY_GetTxPowerLevel8188E(

+	IN	PADAPTER		Adapter,

+	OUT u32*    		powerlevel

+	)

+{

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);

+	u8			TxPwrLevel = 0;

+	int			TxPwrDbm;

+

+	//

+	// Because the Tx power indexes are different, we report the maximum of them to

+	// meet the CCX TPC request. By Bruce, 2008-01-31.

+	//

+

+	// CCK

+	TxPwrLevel = pHalData->CurrentCckTxPwrIdx;

+	TxPwrDbm = phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_B, TxPwrLevel);

+

+	// Legacy OFDM

+	TxPwrLevel = pHalData->CurrentOfdm24GTxPwrIdx + pHalData->LegacyHTTxPowerDiff;

+

+	// Compare with Legacy OFDM Tx power.

+	if(phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_G, TxPwrLevel) > TxPwrDbm)

+		TxPwrDbm = phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_G, TxPwrLevel);

+

+	// HT OFDM

+	TxPwrLevel = pHalData->CurrentOfdm24GTxPwrIdx;

+

+	// Compare with HT OFDM Tx power.

+	if(phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_N_24G, TxPwrLevel) > TxPwrDbm)

+		TxPwrDbm = phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_N_24G, TxPwrLevel);

+

+	*powerlevel = TxPwrDbm;

+}

+

+#if 0

+static void getTxPowerIndex(

+	IN	PADAPTER		Adapter,

+	IN	u8			channel,

+	IN OUT u8*		cckPowerLevel,

+	IN OUT u8*		ofdmPowerLevel

+	)

+{

+	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(Adapter);

+	u8				index = (channel -1);

+	// 1. CCK

+	cckPowerLevel[RF_PATH_A] = pHalData->TxPwrLevelCck[RF_PATH_A][index];	//RF-A

+	cckPowerLevel[RF_PATH_B] = pHalData->TxPwrLevelCck[RF_PATH_B][index];	//RF-B

+

+	// 2. OFDM for 1S or 2S

+	if (GET_RF_TYPE(Adapter) == RF_1T2R || GET_RF_TYPE(Adapter) == RF_1T1R)

+	{

+		// Read HT 40 OFDM TX power

+		ofdmPowerLevel[RF_PATH_A] = pHalData->TxPwrLevelHT40_1S[RF_PATH_A][index];

+		ofdmPowerLevel[RF_PATH_B] = pHalData->TxPwrLevelHT40_1S[RF_PATH_B][index];

+	}

+	else if (GET_RF_TYPE(Adapter) == RF_2T2R)

+	{

+		// Read HT 40 OFDM TX power

+		ofdmPowerLevel[RF_PATH_A] = pHalData->TxPwrLevelHT40_2S[RF_PATH_A][index];

+		ofdmPowerLevel[RF_PATH_B] = pHalData->TxPwrLevelHT40_2S[RF_PATH_B][index];

+	}

+	//RTPRINT(FPHY, PHY_TXPWR, ("Channel-%d, set tx power index !!\n", channel));

+}

+#endif

+

+void getTxPowerIndex88E(

+	IN	PADAPTER		Adapter,

+	IN	u8				channel,

+	IN OUT u8*			cckPowerLevel,

+	IN OUT u8*			ofdmPowerLevel,

+	IN OUT u8*			BW20PowerLevel,

+	IN OUT u8*			BW40PowerLevel

+	)

+{

+

+	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(Adapter);

+	u8				index = (channel -1);

+	u8				TxCount=0,path_nums;

+		

+	

+	if((RF_1T2R == pHalData->rf_type) ||(RF_1T1R ==pHalData->rf_type ))	

+		path_nums = 1;

+	else	

+		path_nums = 2;

+	

+	for(TxCount=0;TxCount< path_nums ;TxCount++)

+	{

+		if(TxCount==RF_PATH_A)

+		{

+			// 1. CCK

+			cckPowerLevel[TxCount]		= pHalData->Index24G_CCK_Base[TxCount][index];

+			//2. OFDM

+			ofdmPowerLevel[TxCount]		= pHalData->Index24G_BW40_Base[RF_PATH_A][index]+

+				pHalData->OFDM_24G_Diff[TxCount][RF_PATH_A];	

+			// 1. BW20

+			BW20PowerLevel[TxCount]	= pHalData->Index24G_BW40_Base[RF_PATH_A][index]+

+				pHalData->BW20_24G_Diff[TxCount][RF_PATH_A];

+			//2. BW40

+			BW40PowerLevel[TxCount]	= pHalData->Index24G_BW40_Base[TxCount][index];

+			//RTPRINT(FPHY, PHY_TXPWR, ("getTxPowerIndex88E(): 40MBase=0x%x  20Mdiff=%d  20MBase=0x%x!!\n", 

+			//	pHalData->Index24G_BW40_Base[RF_PATH_A][index],

+			//	pHalData->BW20_24G_Diff[TxCount][RF_PATH_A],

+			//	BW20PowerLevel[TxCount]));

+		}

+		else if(TxCount==RF_PATH_B)

+		{

+			// 1. CCK

+			cckPowerLevel[TxCount]		= pHalData->Index24G_CCK_Base[TxCount][index];

+			//2. OFDM

+			ofdmPowerLevel[TxCount]		= pHalData->Index24G_BW40_Base[RF_PATH_A][index]+

+			pHalData->BW20_24G_Diff[RF_PATH_A][index]+

+			pHalData->BW20_24G_Diff[TxCount][index];	

+			// 1. BW20

+			BW20PowerLevel[TxCount]	= pHalData->Index24G_BW40_Base[RF_PATH_A][index]+

+			pHalData->BW20_24G_Diff[TxCount][RF_PATH_A]+

+			pHalData->BW20_24G_Diff[TxCount][index];

+			//2. BW40

+			BW40PowerLevel[TxCount]	= pHalData->Index24G_BW40_Base[TxCount][index];		

+		}

+		else if(TxCount==RF_PATH_C)

+		{

+	// 1. CCK

+			cckPowerLevel[TxCount]		= pHalData->Index24G_CCK_Base[TxCount][index];

+			//2. OFDM

+			ofdmPowerLevel[TxCount]		= pHalData->Index24G_BW40_Base[RF_PATH_A][index]+

+			pHalData->BW20_24G_Diff[RF_PATH_A][index]+

+			pHalData->BW20_24G_Diff[RF_PATH_B][index]+

+			pHalData->BW20_24G_Diff[TxCount][index];

+			// 1. BW20

+			BW20PowerLevel[TxCount]	= pHalData->Index24G_BW40_Base[RF_PATH_A][index]+

+			pHalData->BW20_24G_Diff[RF_PATH_A][index]+

+			pHalData->BW20_24G_Diff[RF_PATH_B][index]+

+			pHalData->BW20_24G_Diff[TxCount][index];

+			//2. BW40

+			BW40PowerLevel[TxCount]	= pHalData->Index24G_BW40_Base[TxCount][index];		

+		}

+		else if(TxCount==RF_PATH_D)

+		{

+			// 1. CCK

+			cckPowerLevel[TxCount]		= pHalData->Index24G_CCK_Base[TxCount][index];

+			//2. OFDM

+			ofdmPowerLevel[TxCount]		= pHalData->Index24G_BW40_Base[RF_PATH_A][index]+

+				pHalData->BW20_24G_Diff[RF_PATH_A][index]+

+				pHalData->BW20_24G_Diff[RF_PATH_B][index]+

+				pHalData->BW20_24G_Diff[RF_PATH_C][index]+

+				pHalData->BW20_24G_Diff[TxCount][index];

+

+			// 1. BW20

+			BW20PowerLevel[TxCount]	= pHalData->Index24G_BW40_Base[RF_PATH_A][index]+

+				pHalData->BW20_24G_Diff[RF_PATH_A][index]+

+				pHalData->BW20_24G_Diff[RF_PATH_B][index]+

+				pHalData->BW20_24G_Diff[RF_PATH_C][index]+

+				pHalData->BW20_24G_Diff[TxCount][index];

+

+			//2. BW40

+			BW40PowerLevel[TxCount]	= pHalData->Index24G_BW40_Base[TxCount][index];		

+		}	

+		else

+		{

+		}

+	}

+

+#if 0 // (INTEL_PROXIMITY_SUPPORT == 1)

+	switch(pMgntInfo->IntelProximityModeInfo.PowerOutput){

+		case 1: // 100%

+			break;

+		case 2: // 70%

+			cckPowerLevel[0] -= 3;

+			cckPowerLevel[1] -= 3;

+			ofdmPowerLevel[0] -=3;

+			ofdmPowerLevel[1] -= 3; 

+			break;

+		case 3: // 50%

+			cckPowerLevel[0] -= 6;

+			cckPowerLevel[1] -= 6;

+			ofdmPowerLevel[0] -=6;

+			ofdmPowerLevel[1] -= 6; 

+			break;

+		case 4: // 35%

+			cckPowerLevel[0] -= 9;

+			cckPowerLevel[1] -= 9;

+			ofdmPowerLevel[0] -=9;

+			ofdmPowerLevel[1] -= 9; 

+			break;

+		case 5: // 15%

+			cckPowerLevel[0] -= 17;

+			cckPowerLevel[1] -= 17;

+			ofdmPowerLevel[0] -=17;

+			ofdmPowerLevel[1] -= 17; 

+			break;

+	

+		default:

+			break;

+	}	

+#endif

+	//RTPRINT(FPHY, PHY_TXPWR, ("Channel-%d, set tx power index !!\n", channel));

+}

+

+void phy_PowerIndexCheck88E(

+	IN	PADAPTER	Adapter,

+	IN	u8			channel,

+	IN OUT u8 *		cckPowerLevel,

+	IN OUT u8 *		ofdmPowerLevel,

+	IN OUT u8 *		BW20PowerLevel,

+	IN OUT u8 *		BW40PowerLevel	

+	)

+{

+

+	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(Adapter);

+#if 0 // (CCX_SUPPORT == 1)

+	PMGNT_INFO			pMgntInfo = &(Adapter->MgntInfo);

+	PRT_CCX_INFO		pCcxInfo = GET_CCX_INFO(pMgntInfo);

+

+	//

+	// CCX 2 S31, AP control of client transmit power:

+	// 1. We shall not exceed Cell Power Limit as possible as we can.

+	// 2. Tolerance is +/- 5dB.

+	// 3. 802.11h Power Contraint takes higher precedence over CCX Cell Power Limit.

+	// 

+	// TODO: 

+	// 1. 802.11h power contraint 

+	//

+	// 071011, by rcnjko.

+	//

+	if(	pMgntInfo->OpMode == RT_OP_MODE_INFRASTRUCTURE && 

+		pMgntInfo->mAssoc &&

+		pCcxInfo->bUpdateCcxPwr &&

+		pCcxInfo->bWithCcxCellPwr &&

+		channel == pMgntInfo->dot11CurrentChannelNumber)

+	{

+		u1Byte	CckCellPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_B, pCcxInfo->CcxCellPwr);

+		u1Byte	LegacyOfdmCellPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_G, pCcxInfo->CcxCellPwr);

+		u1Byte	OfdmCellPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_N_24G, pCcxInfo->CcxCellPwr);

+

+		RT_TRACE(COMP_TXAGC, DBG_LOUD, 

+		("CCX Cell Limit: %d dbm => CCK Tx power index : %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n", 

+		pCcxInfo->CcxCellPwr, CckCellPwrIdx, LegacyOfdmCellPwrIdx, OfdmCellPwrIdx));

+		RT_TRACE(COMP_TXAGC, DBG_LOUD, 

+		("EEPROM channel(%d) => CCK Tx power index: %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",

+		channel, cckPowerLevel[0], ofdmPowerLevel[0] + pHalData->LegacyHTTxPowerDiff, ofdmPowerLevel[0])); 

+

+		// CCK

+		if(cckPowerLevel[0] > CckCellPwrIdx)

+			cckPowerLevel[0] = CckCellPwrIdx;

+		// Legacy OFDM, HT OFDM

+		if(ofdmPowerLevel[0] + pHalData->LegacyHTTxPowerDiff > LegacyOfdmCellPwrIdx)

+		{

+			if((OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff) > 0)

+			{

+				ofdmPowerLevel[0] = OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff;

+			}

+			else

+			{

+				ofdmPowerLevel[0] = 0;

+			}

+		}

+

+		RT_TRACE(COMP_TXAGC, DBG_LOUD, 

+		("Altered CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n", 

+		cckPowerLevel[0], ofdmPowerLevel[0] + pHalData->LegacyHTTxPowerDiff, ofdmPowerLevel[0]));

+	}

+#else

+	// Add or not ???

+#endif

+

+	pHalData->CurrentCckTxPwrIdx = cckPowerLevel[0];

+	pHalData->CurrentOfdm24GTxPwrIdx = ofdmPowerLevel[0];

+	pHalData->CurrentBW2024GTxPwrIdx = BW20PowerLevel[0];

+	pHalData->CurrentBW4024GTxPwrIdx = BW40PowerLevel[0];

+

+	//DBG_871X("PHY_SetTxPowerLevel8188E(): CurrentCckTxPwrIdx : 0x%x,CurrentOfdm24GTxPwrIdx: 0x%x, CurrentBW2024GTxPwrIdx: 0x%dx, CurrentBW4024GTxPwrIdx: 0x%x \n", 

+	//	pHalData->CurrentCckTxPwrIdx, pHalData->CurrentOfdm24GTxPwrIdx, pHalData->CurrentBW2024GTxPwrIdx, pHalData->CurrentBW4024GTxPwrIdx);

+}

+/*-----------------------------------------------------------------------------

+ * Function:    SetTxPowerLevel8190()

+ *

+ * Overview:    This function is export to "HalCommon" moudule

+ *			We must consider RF path later!!!!!!!

+ *

+ * Input:       PADAPTER		Adapter

+ *			u1Byte		channel

+ *

+ * Output:      NONE

+ *

+ * Return:      NONE

+ *	2008/11/04	MHC		We remove EEPROM_93C56.

+ *						We need to move CCX relative code to independet file.

+ *	2009/01/21	MHC		Support new EEPROM format from SD3 requirement.

+ *

+ *---------------------------------------------------------------------------*/

+VOID

+PHY_SetTxPowerLevel8188E(

+	IN	PADAPTER		Adapter,

+	IN	u8				channel

+	)

+{

+	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(Adapter);

+	

+	u8	cckPowerLevel[MAX_TX_COUNT], ofdmPowerLevel[MAX_TX_COUNT];// [0]:RF-A, [1]:RF-B

+	u8	BW20PowerLevel[MAX_TX_COUNT], BW40PowerLevel[MAX_TX_COUNT];

+	u8	i=0;

+/*

+#if(MP_DRIVER == 1)

+	if (Adapter->registrypriv.mp_mode == 1)

+	return;

+#endif

+*/

+	//getTxPowerIndex(Adapter, channel, &cckPowerLevel[0], &ofdmPowerLevel[0]);

+	getTxPowerIndex88E(Adapter, channel, &cckPowerLevel[0], &ofdmPowerLevel[0],&BW20PowerLevel[0],&BW40PowerLevel[0]);

+

+	//printk("Channel-%d, cckPowerLevel =  0x%x,   ofdmPowerLeve = 0x%x, BW20PowerLevel  =  0x%x,   BW40PowerLevel = 0x%x,\n", 

+	//		channel, cckPowerLevel[0],  ofdmPowerLevel[0], BW20PowerLevel[0] ,BW40PowerLevel[0]);

+	

+	//RTPRINT(FPHY, PHY_TXPWR, ("Channel-%d, cckPowerLevel (A / B) = 0x%x / 0x%x,   ofdmPowerLevel (A / B) = 0x%x / 0x%x\n",

+	//	channel, cckPowerLevel[0], cckPowerLevel[1], ofdmPowerLevel[0], ofdmPowerLevel[1]));

+

+	//ccxPowerIndexCheck(Adapter, channel, &cckPowerLevel[0], &ofdmPowerLevel[0]);

+	phy_PowerIndexCheck88E(Adapter, channel, &cckPowerLevel[0], &ofdmPowerLevel[0],&BW20PowerLevel[0],&BW40PowerLevel[0]);

+

+	rtl8188e_PHY_RF6052SetCckTxPower(Adapter, &cckPowerLevel[0]);

+	rtl8188e_PHY_RF6052SetOFDMTxPower(Adapter, &ofdmPowerLevel[0],&BW20PowerLevel[0],&BW40PowerLevel[0], channel);

+

+#if 0

+	switch(pHalData->rf_chip)

+	{

+		case RF_8225:

+			PHY_SetRF8225CckTxPower(Adapter, cckPowerLevel[0]);

+			PHY_SetRF8225OfdmTxPower(Adapter, ofdmPowerLevel[0]);

+		break;

+

+		case RF_8256:

+			PHY_SetRF8256CCKTxPower(Adapter, cckPowerLevel[0]);

+			PHY_SetRF8256OFDMTxPower(Adapter, ofdmPowerLevel[0]);

+			break;

+

+		case RF_6052:

+			PHY_RF6052SetCckTxPower(Adapter, &cckPowerLevel[0]);

+			PHY_RF6052SetOFDMTxPower(Adapter, &ofdmPowerLevel[0], channel);

+			break;

+

+		case RF_8258:

+			break;

+	}

+#endif

+

+}

+

+

+//

+//	Description:

+//		Update transmit power level of all channel supported.

+//

+//	TODO:

+//		A mode.

+//	By Bruce, 2008-02-04.

+//

+BOOLEAN

+PHY_UpdateTxPowerDbm8188E(

+	IN	PADAPTER	Adapter,

+	IN	int		powerInDbm

+	)

+{

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);

+	u8				idx;

+	u8			rf_path;

+

+	// TODO: A mode Tx power.

+	u8	CckTxPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_B, powerInDbm);

+	u8	OfdmTxPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_N_24G, powerInDbm);

+

+	if(OfdmTxPwrIdx - pHalData->LegacyHTTxPowerDiff > 0)

+		OfdmTxPwrIdx -= pHalData->LegacyHTTxPowerDiff;

+	else

+		OfdmTxPwrIdx = 0;

+

+	//RT_TRACE(COMP_TXAGC, DBG_LOUD, ("PHY_UpdateTxPowerDbm8192S(): %ld dBm , CckTxPwrIdx = %d, OfdmTxPwrIdx = %d\n", powerInDbm, CckTxPwrIdx, OfdmTxPwrIdx));

+

+	for(idx = 0; idx < 14; idx++)

+	{

+		for (rf_path = 0; rf_path < 2; rf_path++)

+		{

+			pHalData->TxPwrLevelCck[rf_path][idx] = CckTxPwrIdx;

+			pHalData->TxPwrLevelHT40_1S[rf_path][idx] =

+			pHalData->TxPwrLevelHT40_2S[rf_path][idx] = OfdmTxPwrIdx;

+		}

+	}

+

+	//Adapter->HalFunc.SetTxPowerLevelHandler(Adapter, pHalData->CurrentChannel);//gtest:todo

+

+	return _TRUE;

+}

+

+

+/*

+	Description:

+		When beacon interval is changed, the values of the

+		hw registers should be modified.

+	By tynli, 2008.10.24.

+

+*/

+

+

+void

+rtl8192c_PHY_SetBeaconHwReg(

+	IN	PADAPTER		Adapter,

+	IN	u16			BeaconInterval

+	)

+{

+

+}

+

+

+VOID

+PHY_ScanOperationBackup8188E(

+	IN	PADAPTER	Adapter,

+	IN	u8		Operation

+	)

+{

+#if 0

+	IO_TYPE	IoType;

+

+	if(!Adapter->bDriverStopped)

+	{

+		switch(Operation)

+		{

+			case SCAN_OPT_BACKUP:

+				IoType = IO_CMD_PAUSE_DM_BY_SCAN;

+				rtw_hal_set_hwreg(Adapter,HW_VAR_IO_CMD,  (pu1Byte)&IoType);

+

+				break;

+

+			case SCAN_OPT_RESTORE:

+				IoType = IO_CMD_RESUME_DM_BY_SCAN;

+				rtw_hal_set_hwreg(Adapter,HW_VAR_IO_CMD,  (pu1Byte)&IoType);

+				break;

+

+			default:

+				RT_TRACE(COMP_SCAN, DBG_LOUD, ("Unknown Scan Backup Operation. \n"));

+				break;

+		}

+	}

+#endif

+}

+

+/*-----------------------------------------------------------------------------

+ * Function:    PHY_SetBWModeCallback8192C()

+ *

+ * Overview:    Timer callback function for SetSetBWMode

+ *

+ * Input:       	PRT_TIMER		pTimer

+ *

+ * Output:      NONE

+ *

+ * Return:      NONE

+ *

+ * Note:		(1) We do not take j mode into consideration now

+ *			(2) Will two workitem of "switch channel" and "switch channel bandwidth" run

+ *			     concurrently?

+ *---------------------------------------------------------------------------*/

+static VOID

+_PHY_SetBWMode92C(

+	IN	PADAPTER	Adapter

+)

+{

+//	PADAPTER			Adapter = (PADAPTER)pTimer->Adapter;

+	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(Adapter);

+	u8				regBwOpMode;

+	u8				regRRSR_RSC;

+

+	//return;

+

+	// Added it for 20/40 mhz switch time evaluation by guangan 070531

+	//u4Byte				NowL, NowH;

+	//u8Byte				BeginTime, EndTime;

+

+	/*RT_TRACE(COMP_SCAN, DBG_LOUD, ("==>PHY_SetBWModeCallback8192C()  Switch to %s bandwidth\n", \

+					pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"))*/

+

+	if(pHalData->rf_chip == RF_PSEUDO_11N)

+	{

+		//pHalData->SetBWModeInProgress= _FALSE;

+		return;

+	}

+

+	// There is no 40MHz mode in RF_8225.

+	if(pHalData->rf_chip==RF_8225)

+		return;

+

+	if(Adapter->bDriverStopped)

+		return;

+

+	// Added it for 20/40 mhz switch time evaluation by guangan 070531

+	//NowL = PlatformEFIORead4Byte(Adapter, TSFR);

+	//NowH = PlatformEFIORead4Byte(Adapter, TSFR+4);

+	//BeginTime = ((u8Byte)NowH << 32) + NowL;

+

+	//3//

+	//3//<1>Set MAC register

+	//3//

+	//Adapter->HalFunc.SetBWModeHandler();

+

+	regBwOpMode = rtw_read8(Adapter, REG_BWOPMODE);

+	regRRSR_RSC = rtw_read8(Adapter, REG_RRSR+2);

+	//regBwOpMode = rtw_hal_get_hwreg(Adapter,HW_VAR_BWMODE,(pu1Byte)&regBwOpMode);

+

+	switch(pHalData->CurrentChannelBW)

+	{

+		case HT_CHANNEL_WIDTH_20:

+			regBwOpMode |= BW_OPMODE_20MHZ;

+			   // 2007/02/07 Mark by Emily becasue we have not verify whether this register works

+			rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode);

+			break;

+

+		case HT_CHANNEL_WIDTH_40:

+			regBwOpMode &= ~BW_OPMODE_20MHZ;

+				// 2007/02/07 Mark by Emily becasue we have not verify whether this register works

+			rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode);

+

+			regRRSR_RSC = (regRRSR_RSC&0x90) |(pHalData->nCur40MhzPrimeSC<<5);

+			rtw_write8(Adapter, REG_RRSR+2, regRRSR_RSC);

+			break;

+

+		default:

+			/*RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetBWModeCallback8192C():

+						unknown Bandwidth: %#X\n",pHalData->CurrentChannelBW));*/

+			break;

+	}

+

+	//3//

+	//3//<2>Set PHY related register

+	//3//

+	switch(pHalData->CurrentChannelBW)

+	{

+		/* 20 MHz channel*/

+		case HT_CHANNEL_WIDTH_20:

+			PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x0);

+			PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x0);

+			//PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, BIT10, 1);

+

+			break;

+

+

+		/* 40 MHz channel*/

+		case HT_CHANNEL_WIDTH_40:

+			PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x1);

+			PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x1);

+

+			// Set Control channel to upper or lower. These settings are required only for 40MHz

+			PHY_SetBBReg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC>>1));

+			PHY_SetBBReg(Adapter, rOFDM1_LSTF, 0xC00, pHalData->nCur40MhzPrimeSC);

+			//PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, BIT10, 0);

+

+			PHY_SetBBReg(Adapter, 0x818, (BIT26|BIT27), (pHalData->nCur40MhzPrimeSC==HAL_PRIME_CHNL_OFFSET_LOWER)?2:1);

+

+			break;

+

+

+

+		default:

+			/*RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetBWModeCallback8192C(): unknown Bandwidth: %#X\n"\

+						,pHalData->CurrentChannelBW));*/

+			break;

+

+	}

+	//Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315

+

+	// Added it for 20/40 mhz switch time evaluation by guangan 070531

+	//NowL = PlatformEFIORead4Byte(Adapter, TSFR);

+	//NowH = PlatformEFIORead4Byte(Adapter, TSFR+4);

+	//EndTime = ((u8Byte)NowH << 32) + NowL;

+	//RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWModeCallback8190Pci: time of SetBWMode = %I64d us!\n", (EndTime - BeginTime)));

+

+	//3<3>Set RF related register

+	switch(pHalData->rf_chip)

+	{

+		case RF_8225:

+			//PHY_SetRF8225Bandwidth(Adapter, pHalData->CurrentChannelBW);

+			break;

+

+		case RF_8256:

+			// Please implement this function in Hal8190PciPhy8256.c

+			//PHY_SetRF8256Bandwidth(Adapter, pHalData->CurrentChannelBW);

+			break;

+

+		case RF_8258:

+			// Please implement this function in Hal8190PciPhy8258.c

+			// PHY_SetRF8258Bandwidth();

+			break;

+

+		case RF_PSEUDO_11N:

+			// Do Nothing

+			break;

+

+		case RF_6052:

+			rtl8188e_PHY_RF6052SetBandwidth(Adapter, pHalData->CurrentChannelBW);

+			break;

+

+		default:

+			//RT_ASSERT(FALSE, ("Unknown RFChipID: %d\n", pHalData->RFChipID));

+			break;

+	}

+

+	//pHalData->SetBWModeInProgress= FALSE;

+

+	//RT_TRACE(COMP_SCAN, DBG_LOUD, ("<==PHY_SetBWModeCallback8192C() \n" ));

+}

+

+

+ /*-----------------------------------------------------------------------------

+ * Function:   SetBWMode8190Pci()

+ *

+ * Overview:  This function is export to "HalCommon" moudule

+ *

+ * Input:       	PADAPTER			Adapter

+ *			HT_CHANNEL_WIDTH	Bandwidth	//20M or 40M

+ *

+ * Output:      NONE

+ *

+ * Return:      NONE

+ *

+ * Note:		We do not take j mode into consideration now

+ *---------------------------------------------------------------------------*/

+VOID

+PHY_SetBWMode8188E(

+	IN	PADAPTER					Adapter,

+	IN	HT_CHANNEL_WIDTH	Bandwidth,	// 20M or 40M

+	IN	unsigned char	Offset		// Upper, Lower, or Don't care

+)

+{

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);

+	HT_CHANNEL_WIDTH 	tmpBW= pHalData->CurrentChannelBW;

+	// Modified it for 20/40 mhz switch by guangan 070531

+	//PMGNT_INFO	pMgntInfo=&Adapter->MgntInfo;

+

+	//return;

+

+	//if(pHalData->SwChnlInProgress)

+//	if(pMgntInfo->bScanInProgress)

+//	{

+//		RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SetBWMode8192C() %s Exit because bScanInProgress!\n",

+//					Bandwidth == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"));

+//		return;

+//	}

+

+//	if(pHalData->SetBWModeInProgress)

+//	{

+//		// Modified it for 20/40 mhz switch by guangan 070531

+//		RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SetBWMode8192C() %s cancel last timer because SetBWModeInProgress!\n",

+//					Bandwidth == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"));

+//		PlatformCancelTimer(Adapter, &pHalData->SetBWModeTimer);

+//		//return;

+//	}

+

+	//if(pHalData->SetBWModeInProgress)

+	//	return;

+

+	//pHalData->SetBWModeInProgress= TRUE;

+

+	pHalData->CurrentChannelBW = Bandwidth;

+

+#if 0

+	if(Offset==HT_EXTCHNL_OFFSET_LOWER)

+		pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;

+	else if(Offset==HT_EXTCHNL_OFFSET_UPPER)

+		pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;

+	else

+		pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;

+#else

+	pHalData->nCur40MhzPrimeSC = Offset;

+#endif

+

+	if((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved))

+	{

+	#if 0

+		//PlatformSetTimer(Adapter, &(pHalData->SetBWModeTimer), 0);

+	#else

+		_PHY_SetBWMode92C(Adapter);

+	#endif

+	}

+	else

+	{

+		//RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SetBWMode8192C() SetBWModeInProgress FALSE driver sleep or unload\n"));

+		//pHalData->SetBWModeInProgress= FALSE;

+		pHalData->CurrentChannelBW = tmpBW;

+	}

+	

+}

+

+

+static void _PHY_SwChnl8192C(PADAPTER Adapter, u8 channel)

+{

+	u8 eRFPath;

+	u32 param1, param2;

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);

+

+	if ( Adapter->bNotifyChannelChange )

+	{

+		DBG_871X( "[%s] ch = %d\n", __FUNCTION__, channel );

+	}

+

+	//s1. pre common command - CmdID_SetTxPowerLevel

+	PHY_SetTxPowerLevel8188E(Adapter, channel);

+

+	//s2. RF dependent command - CmdID_RF_WriteReg, param1=RF_CHNLBW, param2=channel

+	param1 = RF_CHNLBW;

+	param2 = channel;

+	for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)

+	{

+		pHalData->RfRegChnlVal[eRFPath] = ((pHalData->RfRegChnlVal[eRFPath] & 0xfffffc00) | param2);

+		PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, param1, bRFRegOffsetMask, pHalData->RfRegChnlVal[eRFPath]);

+	}

+

+

+	//s3. post common command - CmdID_End, None

+

+}

+

+VOID

+PHY_SwChnl8188E(	// Call after initialization

+	IN	PADAPTER	Adapter,

+	IN	u8		channel

+	)

+{

+	//PADAPTER Adapter =  ADJUST_TO_ADAPTIVE_ADAPTER(pAdapter, _TRUE);

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);

+	u8	tmpchannel = pHalData->CurrentChannel;

+	BOOLEAN  bResult = _TRUE;

+

+	if(pHalData->rf_chip == RF_PSEUDO_11N)

+	{

+		//pHalData->SwChnlInProgress=FALSE;

+		return; 								//return immediately if it is peudo-phy

+	}

+

+	//if(pHalData->SwChnlInProgress)

+	//	return;

+

+	//if(pHalData->SetBWModeInProgress)

+	//	return;

+

+	//--------------------------------------------

+	switch(pHalData->CurrentWirelessMode)

+	{

+		case WIRELESS_MODE_A:

+		case WIRELESS_MODE_N_5G:

+			//RT_ASSERT((channel>14), ("WIRELESS_MODE_A but channel<=14"));

+			break;

+

+		case WIRELESS_MODE_B:

+			//RT_ASSERT((channel<=14), ("WIRELESS_MODE_B but channel>14"));

+			break;

+

+		case WIRELESS_MODE_G:

+		case WIRELESS_MODE_N_24G:

+			//RT_ASSERT((channel<=14), ("WIRELESS_MODE_G but channel>14"));

+			break;

+

+		default:

+			//RT_ASSERT(FALSE, ("Invalid WirelessMode(%#x)!!\n", pHalData->CurrentWirelessMode));

+			break;

+	}

+	//--------------------------------------------

+

+	//pHalData->SwChnlInProgress = TRUE;

+	if(channel == 0)

+		channel = 1;

+

+	pHalData->CurrentChannel=channel;

+

+	//pHalData->SwChnlStage=0;

+	//pHalData->SwChnlStep=0;

+

+	if((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved))

+	{

+		#if 0

+		//PlatformSetTimer(Adapter, &(pHalData->SwChnlTimer), 0);

+		#else

+		_PHY_SwChnl8192C(Adapter, channel);

+		#endif

+

+		if(bResult)

+		{

+			//RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SwChnl8192C SwChnlInProgress TRUE schdule workitem done\n"));

+		}

+		else

+		{

+			//RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SwChnl8192C SwChnlInProgress FALSE schdule workitem error\n"));

+			//if(IS_HARDWARE_TYPE_8192SU(Adapter))

+			//{

+			//	pHalData->SwChnlInProgress = FALSE;

+				pHalData->CurrentChannel = tmpchannel;

+			//}

+		}

+

+	}

+	else

+	{

+		//RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SwChnl8192C SwChnlInProgress FALSE driver sleep or unload\n"));

+		//if(IS_HARDWARE_TYPE_8192SU(Adapter))

+		//{

+		//	pHalData->SwChnlInProgress = FALSE;

+			pHalData->CurrentChannel = tmpchannel;

+		//}

+	}

+}

+

+

+static	BOOLEAN

+phy_SwChnlStepByStep(

+	IN	PADAPTER	Adapter,

+	IN	u8		channel,

+	IN	u8		*stage,

+	IN	u8		*step,

+	OUT u32		*delay

+	)

+{

+#if 0

+	HAL_DATA_TYPE			*pHalData = GET_HAL_DATA(Adapter);

+	PCHANNEL_ACCESS_SETTING	pChnlAccessSetting;

+	SwChnlCmd				PreCommonCmd[MAX_PRECMD_CNT];

+	u4Byte					PreCommonCmdCnt;

+	SwChnlCmd				PostCommonCmd[MAX_POSTCMD_CNT];

+	u4Byte					PostCommonCmdCnt;

+	SwChnlCmd				RfDependCmd[MAX_RFDEPENDCMD_CNT];

+	u4Byte					RfDependCmdCnt;

+	SwChnlCmd				*CurrentCmd;

+	u1Byte					eRFPath;

+	u4Byte					RfTXPowerCtrl;

+	BOOLEAN					bAdjRfTXPowerCtrl = _FALSE;

+

+

+	RT_ASSERT((Adapter != NULL), ("Adapter should not be NULL\n"));

+#if(MP_DRIVER != 1)

+	RT_ASSERT(IsLegalChannel(Adapter, channel), ("illegal channel: %d\n", channel));

+#endif

+	RT_ASSERT((pHalData != NULL), ("pHalData should not be NULL\n"));

+

+	pChnlAccessSetting = &Adapter->MgntInfo.Info8185.ChannelAccessSetting;

+	RT_ASSERT((pChnlAccessSetting != NULL), ("pChnlAccessSetting should not be NULL\n"));

+

+	//for(eRFPath = RF_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)

+	//for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)

+	//{

+		// <1> Fill up pre common command.

+	PreCommonCmdCnt = 0;

+	phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,

+				CmdID_SetTxPowerLevel, 0, 0, 0);

+	phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,

+				CmdID_End, 0, 0, 0);

+

+		// <2> Fill up post common command.

+	PostCommonCmdCnt = 0;

+

+	phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT,

+				CmdID_End, 0, 0, 0);

+

+		// <3> Fill up RF dependent command.

+	RfDependCmdCnt = 0;

+	switch( pHalData->RFChipID )

+	{

+		case RF_8225:

+		RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel));

+		// 2008/09/04 MH Change channel.

+		if(channel==14) channel++;

+		phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,

+			CmdID_RF_WriteReg, rZebra1_Channel, (0x10+channel-1), 10);

+		phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,

+		CmdID_End, 0, 0, 0);

+		break;

+

+	case RF_8256:

+		// TEST!! This is not the table for 8256!!

+		RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel));

+		phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,

+			CmdID_RF_WriteReg, rRfChannel, channel, 10);

+		phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,

+		CmdID_End, 0, 0, 0);

+		break;

+

+	case RF_6052:

+		RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel));

+		phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,

+			CmdID_RF_WriteReg, RF_CHNLBW, channel, 10);

+		phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,

+		CmdID_End, 0, 0, 0);

+

+		break;

+

+	case RF_8258:

+		break;

+

+	// For FPGA two MAC verification

+	case RF_PSEUDO_11N:

+		return TRUE;

+	default:

+		RT_ASSERT(FALSE, ("Unknown RFChipID: %d\n", pHalData->RFChipID));

+		return FALSE;

+		break;

+	}

+

+

+	do{

+		switch(*stage)

+		{

+		case 0:

+			CurrentCmd=&PreCommonCmd[*step];

+			break;

+		case 1:

+			CurrentCmd=&RfDependCmd[*step];

+			break;

+		case 2:

+			CurrentCmd=&PostCommonCmd[*step];

+			break;

+		}

+

+		if(CurrentCmd->CmdID==CmdID_End)

+		{

+			if((*stage)==2)

+			{

+				return TRUE;

+			}

+			else

+			{

+				(*stage)++;

+				(*step)=0;

+				continue;

+			}

+		}

+

+		switch(CurrentCmd->CmdID)

+		{

+		case CmdID_SetTxPowerLevel:

+			PHY_SetTxPowerLevel8192C(Adapter,channel);

+			break;

+		case CmdID_WritePortUlong:

+			PlatformEFIOWrite4Byte(Adapter, CurrentCmd->Para1, CurrentCmd->Para2);

+			break;

+		case CmdID_WritePortUshort:

+			PlatformEFIOWrite2Byte(Adapter, CurrentCmd->Para1, (u2Byte)CurrentCmd->Para2);

+			break;

+		case CmdID_WritePortUchar:

+			PlatformEFIOWrite1Byte(Adapter, CurrentCmd->Para1, (u1Byte)CurrentCmd->Para2);

+			break;

+		case CmdID_RF_WriteReg:	// Only modify channel for the register now !!!!!

+			for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)

+			{

+#if 1

+				pHalData->RfRegChnlVal[eRFPath] = ((pHalData->RfRegChnlVal[eRFPath] & 0xfffffc00) | CurrentCmd->Para2);

+				PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bRFRegOffsetMask, pHalData->RfRegChnlVal[eRFPath]);

+#else

+				PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bRFRegOffsetMask, (CurrentCmd->Para2));

+#endif

+			}

+			break;

+		}

+

+		break;

+	}while(TRUE);

+	//cosa }/*for(Number of RF paths)*/

+

+	(*delay)=CurrentCmd->msDelay;

+	(*step)++;

+	return FALSE;

+#endif

+	return _TRUE;

+}

+

+

+static	BOOLEAN

+phy_SetSwChnlCmdArray(

+	SwChnlCmd*		CmdTable,

+	u32			CmdTableIdx,

+	u32			CmdTableSz,

+	SwChnlCmdID		CmdID,

+	u32			Para1,

+	u32			Para2,

+	u32			msDelay

+	)

+{

+	SwChnlCmd* pCmd;

+

+	if(CmdTable == NULL)

+	{

+		//RT_ASSERT(FALSE, ("phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n"));

+		return _FALSE;

+	}

+	if(CmdTableIdx >= CmdTableSz)

+	{

+		//RT_ASSERT(FALSE,

+		//		("phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%ld, CmdTableSz:%ld\n",

+		//		CmdTableIdx, CmdTableSz));

+		return _FALSE;

+	}

+

+	pCmd = CmdTable + CmdTableIdx;

+	pCmd->CmdID = CmdID;

+	pCmd->Para1 = Para1;

+	pCmd->Para2 = Para2;

+	pCmd->msDelay = msDelay;

+

+	return _TRUE;

+}

+

+

+static	void

+phy_FinishSwChnlNow(	// We should not call this function directly

+		IN	PADAPTER	Adapter,

+		IN	u8		channel

+		)

+{

+#if 0

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);

+	u32			delay;

+

+	while(!phy_SwChnlStepByStep(Adapter,channel,&pHalData->SwChnlStage,&pHalData->SwChnlStep,&delay))

+	{

+		if(delay>0)

+			rtw_mdelay_os(delay);

+	}

+#endif

+}

+

+

+

+//

+// Description:

+//	Switch channel synchronously. Called by SwChnlByDelayHandler.

+//

+// Implemented by Bruce, 2008-02-14.

+// The following procedure is operted according to SwChanlCallback8190Pci().

+// However, this procedure is performed synchronously  which should be running under

+// passive level.

+//

+VOID

+PHY_SwChnlPhy8192C(	// Only called during initialize

+	IN	PADAPTER	Adapter,

+	IN	u8		channel

+	)

+{

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);

+

+	//RT_TRACE(COMP_SCAN | COMP_RM, DBG_LOUD, ("==>PHY_SwChnlPhy8192S(), switch from channel %d to channel %d.\n", pHalData->CurrentChannel, channel));

+

+	// Cannot IO.

+	//if(RT_CANNOT_IO(Adapter))

+	//	return;

+

+	// Channel Switching is in progress.

+	//if(pHalData->SwChnlInProgress)

+	//	return;

+

+	//return immediately if it is peudo-phy

+	if(pHalData->rf_chip == RF_PSEUDO_11N)

+	{

+		//pHalData->SwChnlInProgress=FALSE;

+		return;

+	}

+

+	//pHalData->SwChnlInProgress = TRUE;

+	if( channel == 0)

+		channel = 1;

+

+	pHalData->CurrentChannel=channel;

+

+	//pHalData->SwChnlStage = 0;

+	//pHalData->SwChnlStep = 0;

+

+	phy_FinishSwChnlNow(Adapter,channel);

+

+	//pHalData->SwChnlInProgress = FALSE;

+}

+

+

+//

+//	Description:

+//		Configure H/W functionality to enable/disable Monitor mode.

+//		Note, because we possibly need to configure BB and RF in this function,

+//		so caller should in PASSIVE_LEVEL. 080118, by rcnjko.

+//

+VOID

+PHY_SetMonitorMode8192C(

+	IN	PADAPTER			pAdapter,

+	IN	BOOLEAN				bEnableMonitorMode

+	)

+{

+#if 0

+	HAL_DATA_TYPE		*pHalData	= GET_HAL_DATA(pAdapter);

+	BOOLEAN				bFilterOutNonAssociatedBSSID = FALSE;

+

+	//2 Note: we may need to stop antenna diversity.

+	if(bEnableMonitorMode)

+	{

+		bFilterOutNonAssociatedBSSID = FALSE;

+		RT_TRACE(COMP_RM, DBG_LOUD, ("PHY_SetMonitorMode8192S(): enable monitor mode\n"));

+

+		pHalData->bInMonitorMode = TRUE;

+		pAdapter->HalFunc.AllowAllDestAddrHandler(pAdapter, TRUE, TRUE);

+		rtw_hal_set_hwreg(pAdapter, HW_VAR_CHECK_BSSID, (pu1Byte)&bFilterOutNonAssociatedBSSID);

+	}

+	else

+	{

+		bFilterOutNonAssociatedBSSID = TRUE;

+		RT_TRACE(COMP_RM, DBG_LOUD, ("PHY_SetMonitorMode8192S(): disable monitor mode\n"));

+

+		pAdapter->HalFunc.AllowAllDestAddrHandler(pAdapter, FALSE, TRUE);

+		pHalData->bInMonitorMode = FALSE;

+		rtw_hal_set_hwreg(pAdapter, HW_VAR_CHECK_BSSID, (pu1Byte)&bFilterOutNonAssociatedBSSID);

+	}

+#endif

+}

+

+

+/*-----------------------------------------------------------------------------

+ * Function:	PHYCheckIsLegalRfPath8190Pci()

+ *

+ * Overview:	Check different RF type to execute legal judgement. If RF Path is illegal

+ *			We will return false.

+ *

+ * Input:		NONE

+ *

+ * Output:		NONE

+ *

+ * Return:		NONE

+ *

+ * Revised History:

+ *	When		Who		Remark

+ *	11/15/2007	MHC		Create Version 0.

+ *

+ *---------------------------------------------------------------------------*/

+BOOLEAN

+PHY_CheckIsLegalRfPath8192C(

+	IN	PADAPTER	pAdapter,

+	IN	u32	eRFPath)

+{

+//	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);

+	BOOLEAN				rtValue = _TRUE;

+

+	// NOt check RF Path now.!

+#if 0

+	if (pHalData->RF_Type == RF_1T2R && eRFPath != RF_PATH_A)

+	{

+		rtValue = FALSE;

+	}

+	if (pHalData->RF_Type == RF_1T2R && eRFPath != RF_PATH_A)

+	{

+

+	}

+#endif

+	return	rtValue;

+

+}	/* PHY_CheckIsLegalRfPath8192C */

+

+static VOID _PHY_SetRFPathSwitch(

+	IN	PADAPTER	pAdapter,

+	IN	BOOLEAN		bMain,

+	IN	BOOLEAN		is2T

+	)

+{

+	u8	u1bTmp;

+

+	if(!pAdapter->hw_init_completed)

+	{

+		u1bTmp = rtw_read8(pAdapter, REG_LEDCFG2) | BIT7;

+		rtw_write8(pAdapter, REG_LEDCFG2, u1bTmp);

+		//PHY_SetBBReg(pAdapter, REG_LEDCFG0, BIT23, 0x01);

+		PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT13, 0x01);

+	}

+

+	if(is2T)

+	{

+		if(bMain)

+			PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x1);	//92C_Path_A

+		else

+			PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x2);	//BT

+	}

+	else

+	{

+

+		if(bMain)

+			PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, 0x300, 0x2);	//Main

+		else

+			PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, 0x300, 0x1);	//Aux

+	}

+

+}

+

+//return value TRUE => Main; FALSE => Aux

+

+static BOOLEAN _PHY_QueryRFPathSwitch(

+	IN	PADAPTER	pAdapter,

+	IN	BOOLEAN		is2T

+	)

+{

+//	if(is2T)

+//		return _TRUE;

+

+	if(!pAdapter->hw_init_completed)

+	{

+		PHY_SetBBReg(pAdapter, REG_LEDCFG0, BIT23, 0x01);

+		PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT13, 0x01);

+	}

+

+	if(is2T)

+	{

+		if(PHY_QueryBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6) == 0x01)

+			return _TRUE;

+		else

+			return _FALSE;

+	}

+	else

+	{

+		if(PHY_QueryBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, 0x300) == 0x02)

+			return _TRUE;

+		else

+			return _FALSE;

+	}

+}

+

+

+static VOID

+_PHY_DumpRFReg(IN	PADAPTER	pAdapter)

+{

+	u32 rfRegValue,rfRegOffset;

+

+	//RTPRINT(FINIT, INIT_RF, ("PHY_DumpRFReg()====>\n"));

+

+	for(rfRegOffset = 0x00;rfRegOffset<=0x30;rfRegOffset++){

+		rfRegValue = PHY_QueryRFReg(pAdapter,RF_PATH_A, rfRegOffset, bMaskDWord);

+		//RTPRINT(FINIT, INIT_RF, (" 0x%02x = 0x%08x\n",rfRegOffset,rfRegValue));

+	}

+	//RTPRINT(FINIT, INIT_RF, ("<===== PHY_DumpRFReg()\n"));

+}

+

+

+//

+// Move from phycfg.c to gen.c to be code independent later

+//

+//-------------------------Move to other DIR later----------------------------*/

+#ifdef CONFIG_USB_HCI

+

+//

+//	Description:

+// 		To dump all Tx FIFO LLT related link-list table.

+//		Added by Roger, 2009.03.10.

+//

+VOID

+DumpBBDbgPort_92CU(

+	IN	PADAPTER			Adapter

+	)

+{

+

+	//RT_TRACE(COMP_SEND, DBG_WARNING, ("\n>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"));

+	//RT_TRACE(COMP_SEND, DBG_WARNING, ("BaseBand Debug Ports:\n"));

+

+	PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0000);

+	//RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord)));

+

+	PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0803);

+	//RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord)));

+

+	PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0a06);

+	//RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord)));

+

+	PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0007);

+	//RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord)));

+

+	PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0100);

+	PHY_SetBBReg(Adapter, 0x0a28, 0x00ff0000, 0x000f0000);

+	//RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord)));

+

+	PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0100);

+	PHY_SetBBReg(Adapter, 0x0a28, 0x00ff0000, 0x00150000);

+	//RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord)));

+

+	//RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0x800, PHY_QueryBBReg(Adapter, 0x0800, bMaskDWord)));

+	//RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0x900, PHY_QueryBBReg(Adapter, 0x0900, bMaskDWord)));

+	//RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xa00, PHY_QueryBBReg(Adapter, 0x0a00, bMaskDWord)));

+	//RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xa54, PHY_QueryBBReg(Adapter, 0x0a54, bMaskDWord)));

+	//RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xa58, PHY_QueryBBReg(Adapter, 0x0a58, bMaskDWord)));

+

+}

+#endif

+

diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/rtl8188e_rf6052.c b/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/rtl8188e_rf6052.c
new file mode 100755
index 00000000..de50d94a
--- /dev/null
+++ b/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/rtl8188e_rf6052.c
@@ -0,0 +1,1265 @@
+/******************************************************************************

+ *

+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.

+ *

+ * This program is free software; you can redistribute it and/or modify it

+ * under the terms of version 2 of the GNU General Public License as

+ * published by the Free Software Foundation.

+ *

+ * This program is distributed in the hope that it will be useful, but WITHOUT

+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for

+ * more details.

+ *

+ * You should have received a copy of the GNU General Public License along with

+ * this program; if not, write to the Free Software Foundation, Inc.,

+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA

+ *

+ *

+ ******************************************************************************/

+/******************************************************************************

+ *

+ *

+ * Module:	rtl8192c_rf6052.c	( Source C File)

+ *

+ * Note:	Provide RF 6052 series relative API.

+ *

+ * Function:

+ *

+ * Export:

+ *

+ * Abbrev:

+ *

+ * History:

+ * Data			Who		Remark

+ *

+ * 09/25/2008	MHC		Create initial version.

+ * 11/05/2008 	MHC		Add API for tw power setting.

+ *

+ *

+******************************************************************************/

+

+#define _RTL8188E_RF6052_C_

+

+#include <drv_conf.h>

+#include <osdep_service.h>

+#include <drv_types.h>

+#include <rtw_byteorder.h>

+

+#include <rtl8188e_hal.h>

+

+/*---------------------------Define Local Constant---------------------------*/

+// Define local structure for debug!!!!!

+typedef struct RF_Shadow_Compare_Map {

+	// Shadow register value

+	u32		Value;

+	// Compare or not flag

+	u8		Compare;

+	// Record If it had ever modified unpredicted

+	u8		ErrorOrNot;

+	// Recorver Flag

+	u8		Recorver;

+	//

+	u8		Driver_Write;

+}RF_SHADOW_T;

+/*---------------------------Define Local Constant---------------------------*/

+

+

+/*------------------------Define global variable-----------------------------*/

+/*------------------------Define global variable-----------------------------*/

+

+

+/*------------------------Define local variable------------------------------*/

+// 2008/11/20 MH For Debug only, RF

+//static	RF_SHADOW_T	RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG] = {0};

+static	RF_SHADOW_T	RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG];

+/*------------------------Define local variable------------------------------*/

+

+

+/*-----------------------------------------------------------------------------

+ * Function:	RF_ChangeTxPath

+ *

+ * Overview:	For RL6052, we must change some RF settign for 1T or 2T.

+ *

+ * Input:		u2Byte DataRate		// 0x80-8f, 0x90-9f

+ *

+ * Output:      NONE

+ *

+ * Return:      NONE

+ *

+ * Revised History:

+ * When			Who		Remark

+ * 09/25/2008 	MHC		Create Version 0.

+ *						Firmwaer support the utility later.

+ *

+ *---------------------------------------------------------------------------*/

+void rtl8188e_RF_ChangeTxPath(	IN	PADAPTER	Adapter,

+										IN	u16		DataRate)

+{

+// We do not support gain table change inACUT now !!!! Delete later !!!

+#if 0//(RTL92SE_FPGA_VERIFY == 0)

+	static	u1Byte	RF_Path_Type = 2;	// 1 = 1T 2= 2T

+	static	u4Byte	tx_gain_tbl1[6]

+			= {0x17f50, 0x11f40, 0x0cf30, 0x08720, 0x04310, 0x00100};

+	static	u4Byte	tx_gain_tbl2[6]

+			= {0x15ea0, 0x10e90, 0x0c680, 0x08250, 0x04040, 0x00030};

+	u1Byte	i;

+

+	if (RF_Path_Type == 2 && (DataRate&0xF) <= 0x7)

+	{

+		// Set TX SYNC power G2G3 loop filter

+		PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,

+					RF_TXPA_G2, bRFRegOffsetMask, 0x0f000);

+		PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,

+					RF_TXPA_G3, bRFRegOffsetMask, 0xeacf1);

+

+		// Change TX AGC gain table

+		for (i = 0; i < 6; i++)

+			PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,

+						RF_TX_AGC, bRFRegOffsetMask, tx_gain_tbl1[i]);

+

+		// Set PA to high value

+		PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,

+					RF_TXPA_G2, bRFRegOffsetMask, 0x01e39);

+	}

+	else if (RF_Path_Type == 1 && (DataRate&0xF) >= 0x8)

+	{

+		// Set TX SYNC power G2G3 loop filter

+		PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,

+					RF_TXPA_G2, bRFRegOffsetMask, 0x04440);

+		PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,

+					RF_TXPA_G3, bRFRegOffsetMask, 0xea4f1);

+

+		// Change TX AGC gain table

+		for (i = 0; i < 6; i++)

+			PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,

+						RF_TX_AGC, bRFRegOffsetMask, tx_gain_tbl2[i]);

+

+		// Set PA low gain

+		PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,

+					RF_TXPA_G2, bRFRegOffsetMask, 0x01e19);

+	}

+#endif

+

+}	/* RF_ChangeTxPath */

+

+

+/*-----------------------------------------------------------------------------

+ * Function:    PHY_RF6052SetBandwidth()

+ *

+ * Overview:    This function is called by SetBWModeCallback8190Pci() only

+ *

+ * Input:       PADAPTER				Adapter

+ *			WIRELESS_BANDWIDTH_E	Bandwidth	//20M or 40M

+ *

+ * Output:      NONE

+ *

+ * Return:      NONE

+ *

+ * Note:		For RF type 0222D

+ *---------------------------------------------------------------------------*/

+VOID

+rtl8188e_PHY_RF6052SetBandwidth(

+	IN	PADAPTER				Adapter,

+	IN	HT_CHANNEL_WIDTH		Bandwidth)	//20M or 40M

+{

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);

+

+	switch(Bandwidth)

+	{

+		case HT_CHANNEL_WIDTH_20:

+			pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT(10) | BIT(11));

+			PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);

+			break;

+

+		case HT_CHANNEL_WIDTH_40:

+			pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff)| BIT(10));

+			PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);

+			break;

+

+		default:

+			//RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth ));

+			break;

+	}

+

+}

+

+

+/*-----------------------------------------------------------------------------

+ * Function:	PHY_RF6052SetCckTxPower

+ *

+ * Overview:

+ *

+ * Input:       NONE

+ *

+ * Output:      NONE

+ *

+ * Return:      NONE

+ *

+ * Revised History:

+ * When			Who		Remark

+ * 11/05/2008 	MHC		Simulate 8192series..

+ *

+ *---------------------------------------------------------------------------*/

+

+VOID

+rtl8188e_PHY_RF6052SetCckTxPower(

+	IN	PADAPTER		Adapter,

+	IN	u8*			pPowerlevel)

+{

+	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(Adapter);

+	struct mlme_priv	*pmlmepriv = &Adapter->mlmepriv;

+	struct dm_priv		*pdmpriv = &pHalData->dmpriv;

+	struct mlme_ext_priv 		*pmlmeext = &Adapter->mlmeextpriv;

+	//PMGNT_INFO		pMgntInfo=&Adapter->MgntInfo;

+	u32			TxAGC[2]={0, 0}, tmpval=0,pwrtrac_value;

+	BOOLEAN		TurboScanOff = _FALSE;

+	u8			idx1, idx2;

+	u8*			ptr;

+	u8			direction;

+	//FOR CE ,must disable turbo scan

+	TurboScanOff = _TRUE;

+	

+

+	if(pmlmeext->sitesurvey_res.state == SCAN_PROCESS)

+	{

+		TxAGC[RF_PATH_A] = 0x3f3f3f3f;

+		TxAGC[RF_PATH_B] = 0x3f3f3f3f;

+

+		TurboScanOff = _TRUE;//disable turbo scan

+

+		if(TurboScanOff)

+		{

+			for(idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++)

+			{

+				TxAGC[idx1] =

+					pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) |

+					(pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24);

+#ifdef CONFIG_USB_HCI

+				// 2010/10/18 MH For external PA module. We need to limit power index to be less than 0x20.

+				if (TxAGC[idx1] > 0x20 && pHalData->ExternalPA)

+					TxAGC[idx1] = 0x20;

+#endif

+			}

+		}

+	}

+	else

+	{

+// 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism.

+// Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism.

+// In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder.

+		if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)

+		{

+			TxAGC[RF_PATH_A] = 0x10101010;

+			TxAGC[RF_PATH_B] = 0x10101010;

+		}

+		else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)

+		{

+			TxAGC[RF_PATH_A] = 0x00000000;

+			TxAGC[RF_PATH_B] = 0x00000000;

+		}

+		else

+		{

+			for(idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++)

+			{

+				TxAGC[idx1] =

+					pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) |

+					(pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24);

+			}

+

+			if(pHalData->EEPROMRegulatory==0)

+			{

+				tmpval = (pHalData->MCSTxPowerLevelOriginalOffset[0][6]) +

+						(pHalData->MCSTxPowerLevelOriginalOffset[0][7]<<8);

+				TxAGC[RF_PATH_A] += tmpval;

+

+				tmpval = (pHalData->MCSTxPowerLevelOriginalOffset[0][14]) +

+						(pHalData->MCSTxPowerLevelOriginalOffset[0][15]<<24);

+				TxAGC[RF_PATH_B] += tmpval;

+			}

+		}

+	}

+

+	for(idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++)

+	{

+		ptr = (u8*)(&(TxAGC[idx1]));

+		for(idx2=0; idx2<4; idx2++)

+		{

+			if(*ptr > RF6052_MAX_TX_PWR)

+				*ptr = RF6052_MAX_TX_PWR;

+			ptr++;

+		}

+	}

+	ODM_TxPwrTrackAdjust88E(&pHalData->odmpriv, 1, &direction, &pwrtrac_value);

+

+	if (direction == 1)			// Increase TX pwoer

+	{

+		TxAGC[0] += pwrtrac_value;

+		TxAGC[1] += pwrtrac_value;

+	}

+	else if (direction == 2)	// Decrease TX pwoer

+	{

+		TxAGC[0] -=  pwrtrac_value;

+		TxAGC[1] -=  pwrtrac_value;

+	}

+

+

+	// rf-A cck tx power

+	tmpval = TxAGC[RF_PATH_A]&0xff;

+	PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval);

+	//RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_A_CCK1_Mcs32));

+	tmpval = TxAGC[RF_PATH_A]>>8;

+	PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);

+	//RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_B_CCK11_A_CCK2_11));

+

+	// rf-B cck tx power

+	tmpval = TxAGC[RF_PATH_B]>>24;

+	PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, tmpval);

+	//RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_B_CCK11_A_CCK2_11));

+	tmpval = TxAGC[RF_PATH_B]&0x00ffffff;

+	PHY_SetBBReg(Adapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval);

+	//RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n",

+	//	tmpval, rTxAGC_B_CCK1_55_Mcs32));

+

+}	/* PHY_RF6052SetCckTxPower */

+

+#if 0

+//

+// powerbase0 for OFDM rates

+// powerbase1 for HT MCS rates

+//

+static void getPowerBase(

+	IN	PADAPTER	Adapter,

+	IN	u8*		pPowerLevel,

+	IN	u8		Channel,

+	IN OUT u32*	OfdmBase,

+	IN OUT u32*	MCSBase

+	)

+{

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);

+	u32			powerBase0, powerBase1;

+	u8			Legacy_pwrdiff=0, HT20_pwrdiff=0;

+	u8			i, powerlevel[2];

+

+	for(i=0; i<2; i++)

+	{

+		powerlevel[i] = pPowerLevel[i];

+		Legacy_pwrdiff = pHalData->TxPwrLegacyHtDiff[i][Channel-1];

+		powerBase0 = powerlevel[i] + Legacy_pwrdiff;

+

+		powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0;

+		*(OfdmBase+i) = powerBase0;

+		//RTPRINT(FPHY, PHY_TXPWR, (" [OFDM power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(OfdmBase+i)));

+	}

+

+	for(i=0; i<2; i++)

+	{

+		//Check HT20 to HT40 diff

+		if(pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)

+		{

+			HT20_pwrdiff = pHalData->TxPwrHt20Diff[i][Channel-1];

+			powerlevel[i] += HT20_pwrdiff;

+		}

+		powerBase1 = powerlevel[i];

+		powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1;

+		*(MCSBase+i) = powerBase1;

+		//RTPRINT(FPHY, PHY_TXPWR, (" [MCS power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(MCSBase+i)));

+	}

+}

+#endif

+//

+// powerbase0 for OFDM rates

+// powerbase1 for HT MCS rates

+//

+void getPowerBase88E(

+	IN	PADAPTER	Adapter,

+	IN	u8*			pPowerLevelOFDM,

+	IN	u8*			pPowerLevelBW20,

+	IN	u8*			pPowerLevelBW40,

+	IN	u8			Channel,

+	IN OUT u32*		OfdmBase,

+	IN OUT u32*		MCSBase

+	)

+{

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);

+	u32			powerBase0, powerBase1;

+	u8			Legacy_pwrdiff=0;

+	s8			HT20_pwrdiff=0;

+	u8			i, powerlevel[2];

+

+	for(i=0; i<2; i++)

+	{

+		powerBase0 = pPowerLevelOFDM[i];

+

+		powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0;

+		*(OfdmBase+i) = powerBase0;

+		//DBG_871X(" [OFDM power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(OfdmBase+i));

+	}

+

+	for(i=0; i<pHalData->NumTotalRFPath; i++)

+	{

+		//Check HT20 to HT40 diff

+		if(pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)

+		{

+			powerlevel[i] = pPowerLevelBW20[i];

+		}

+		else

+		{

+			powerlevel[i] = pPowerLevelBW40[i];

+		}	

+		powerBase1 = powerlevel[i];

+		powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1;

+		*(MCSBase+i) = powerBase1;

+		//DBG_871X(" [MCS power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(MCSBase+i));

+	}

+}

+#if 0

+static void getTxPowerWriteValByRegulatory(

+	IN		PADAPTER	Adapter,

+	IN		u8			Channel,

+	IN		u8			index,

+	IN		u32*		powerBase0,

+	IN		u32*		powerBase1,

+	OUT		u32*		pOutWriteVal

+	)

+{

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);

+	struct dm_priv	*pdmpriv = &pHalData->dmpriv;

+	u8	i, chnlGroup, pwr_diff_limit[4];

+	u32 	writeVal, customer_limit, rf;

+

+	//

+	// Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate

+	//

+	for(rf=0; rf<2; rf++)

+	{

+		switch(pHalData->EEPROMRegulatory)

+		{

+			case 0:	// Realtek better performance

+					// increase power diff defined by Realtek for large power

+				chnlGroup = 0;

+				//RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",

+				//	chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]));

+				writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +

+					((index<2)?powerBase0[rf]:powerBase1[rf]);

+				//RTPRINT(FPHY, PHY_TXPWR, ("RTK better performance, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));

+				break;

+			case 1:	// Realtek regulatory

+					// increase power diff defined by Realtek for regulatory

+				{

+					if(pHalData->pwrGroupCnt == 1)

+						chnlGroup = 0;

+					if(pHalData->pwrGroupCnt >= 3)

+					{

+						if(Channel <= 3)

+							chnlGroup = 0;

+						else if(Channel >= 4 && Channel <= 9)

+							chnlGroup = 1;

+						else if(Channel > 9)

+							chnlGroup = 2;

+

+						if(pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)

+							chnlGroup++;

+						else

+							chnlGroup+=4;

+					}

+					//RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",

+					//chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]));

+					writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +

+							((index<2)?powerBase0[rf]:powerBase1[rf]);

+					//RTPRINT(FPHY, PHY_TXPWR, ("Realtek regulatory, 20MHz, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));

+				}

+				break;

+			case 2:	// Better regulatory

+					// don't increase any power diff

+				writeVal = ((index<2)?powerBase0[rf]:powerBase1[rf]);

+				//RTPRINT(FPHY, PHY_TXPWR, ("Better regulatory, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));

+				break;

+			case 3:	// Customer defined power diff.

+					// increase power diff defined by customer.

+				chnlGroup = 0;

+				//RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",

+				//	chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]));

+

+				if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40)

+				{

+					//RTPRINT(FPHY, PHY_TXPWR, ("customer's limit, 40MHz rf(%c) = 0x%x\n",

+					//	((rf==0)?'A':'B'), pHalData->PwrGroupHT40[rf][Channel-1]));

+				}

+				else

+				{

+					//RTPRINT(FPHY, PHY_TXPWR, ("customer's limit, 20MHz rf(%c) = 0x%x\n",

+					//	((rf==0)?'A':'B'), pHalData->PwrGroupHT20[rf][Channel-1]));

+				}

+				for (i=0; i<4; i++)

+				{

+					pwr_diff_limit[i] = (u8)((pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]&(0x7f<<(i*8)))>>(i*8));

+					if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40)

+					{

+						if(pwr_diff_limit[i] > pHalData->PwrGroupHT40[rf][Channel-1])

+							pwr_diff_limit[i] = pHalData->PwrGroupHT40[rf][Channel-1];

+					}

+					else

+					{

+						if(pwr_diff_limit[i] > pHalData->PwrGroupHT20[rf][Channel-1])

+							pwr_diff_limit[i] = pHalData->PwrGroupHT20[rf][Channel-1];

+					}

+				}

+				customer_limit = (pwr_diff_limit[3]<<24) | (pwr_diff_limit[2]<<16) |

+								(pwr_diff_limit[1]<<8) | (pwr_diff_limit[0]);

+				//RTPRINT(FPHY, PHY_TXPWR, ("Customer's limit rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), customer_limit));

+

+				writeVal = customer_limit + ((index<2)?powerBase0[rf]:powerBase1[rf]);

+				//RTPRINT(FPHY, PHY_TXPWR, ("Customer, writeVal rf(%c)= 0x%x\n", ((rf==0)?'A':'B'), writeVal));

+				break;

+			default:

+				chnlGroup = 0;

+				writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +

+						((index<2)?powerBase0[rf]:powerBase1[rf]);

+				//RTPRINT(FPHY, PHY_TXPWR, ("RTK better performance, writeVal rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));

+				break;

+		}

+

+// 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism.

+// Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism.

+// In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder.

+

+		if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)

+			writeVal = 0x14141414;

+		else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)

+			writeVal = 0x00000000;

+

+

+		// 20100628 Joseph: High power mode for BT-Coexist mechanism.

+		// This mechanism is only applied when Driver-Highpower-Mechanism is OFF.

+		if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT1)

+		{

+			//RTPRINT(FBT, BT_TRACE, ("Tx Power (-6)\n"));

+			writeVal = writeVal - 0x06060606;

+		}

+		else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT2)

+		{

+			//RTPRINT(FBT, BT_TRACE, ("Tx Power (-0)\n"));

+			writeVal = writeVal;

+		}

+		*(pOutWriteVal+rf) = writeVal;

+	}

+}

+#endif

+void getTxPowerWriteValByRegulatory88E(

+	IN		PADAPTER	Adapter,

+	IN		u8			Channel,

+	IN		u8			index,

+	IN		u32*		powerBase0,

+	IN		u32*		powerBase1,

+	OUT		u32*		pOutWriteVal

+	)

+{

+	

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);

+	struct dm_priv	*pdmpriv = &pHalData->dmpriv;

+	u1Byte			i, chnlGroup=0, pwr_diff_limit[4], customer_pwr_limit;

+	s1Byte			pwr_diff=0;

+	u4Byte 			writeVal, customer_limit, rf;

+	u1Byte			Regulatory = pHalData->EEPROMRegulatory;

+

+	//

+	// Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate

+	//

+#if 0 // (INTEL_PROXIMITY_SUPPORT == 1)

+	if(pMgntInfo->IntelProximityModeInfo.PowerOutput > 0)

+		Regulatory = 2;

+#endif

+

+	for(rf=0; rf<2; rf++)

+	{

+		switch(Regulatory)

+		{

+			case 0:	// Realtek better performance

+					// increase power diff defined by Realtek for large power

+				chnlGroup = 0;

+				//RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n", 

+				//	chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]));

+				writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] + 

+					((index<2)?powerBase0[rf]:powerBase1[rf]);

+				//RTPRINT(FPHY, PHY_TXPWR, ("RTK better performance, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));

+				break;

+			case 1:	// Realtek regulatory

+					// increase power diff defined by Realtek for regulatory

+				{

+					if(pHalData->pwrGroupCnt == 1)

+						chnlGroup = 0;

+					//if(pHalData->pwrGroupCnt >= pHalData->PGMaxGroup)

+					{

+						if (Channel < 3)			// Chanel 1-2

+							chnlGroup = 0;

+						else if (Channel < 6)		// Channel 3-5

+							chnlGroup = 1;

+						else	 if(Channel <9)		// Channel 6-8

+							chnlGroup = 2;

+						else if(Channel <12)		// Channel 9-11

+							chnlGroup = 3;

+						else if(Channel <14)		// Channel 12-13

+							chnlGroup = 4;

+						else if(Channel ==14)		// Channel 14

+							chnlGroup = 4;	

+						

+						if(pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)

+							chnlGroup++;

+						else

+							chnlGroup+=6;

+				

+/*

+						if(Channel <= 3)

+							chnlGroup = 0;

+						else if(Channel >= 4 && Channel <= 9)

+							chnlGroup = 1;

+						else if(Channel > 9)

+							chnlGroup = 2;

+						

+						

+						if(pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)

+							chnlGroup++;

+						else

+							chnlGroup+=4;

+*/							

+					}

+					//RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n", 

+					//chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]));

+					writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] + 

+							((index<2)?powerBase0[rf]:powerBase1[rf]);

+					//RTPRINT(FPHY, PHY_TXPWR, ("Realtek regulatory, 20MHz, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));

+				}

+				break;

+			case 2:	// Better regulatory

+					// don't increase any power diff

+				writeVal = ((index<2)?powerBase0[rf]:powerBase1[rf]);

+				//RTPRINT(FPHY, PHY_TXPWR, ("Better regulatory, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));

+				break;

+			case 3:	// Customer defined power diff.

+					// increase power diff defined by customer.

+				chnlGroup = 0;

+				//RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n", 

+				//	chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]));

+

+				/*

+				if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40)

+				{

+					RTPRINT(FPHY, PHY_TXPWR, ("customer's limit, 40MHz rf(%c) = 0x%x\n", 

+						((rf==0)?'A':'B'), pHalData->PwrGroupHT40[rf][Channel-1]));

+				}

+				else

+				{

+					RTPRINT(FPHY, PHY_TXPWR, ("customer's limit, 20MHz rf(%c) = 0x%x\n", 

+						((rf==0)?'A':'B'), pHalData->PwrGroupHT20[rf][Channel-1]));

+				}*/

+

+				if(index < 2)

+					pwr_diff = pHalData->TxPwrLegacyHtDiff[rf][Channel-1];

+				else if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)

+					pwr_diff = pHalData->TxPwrHt20Diff[rf][Channel-1];

+

+				//RTPRINT(FPHY, PHY_TXPWR, ("power diff rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), pwr_diff));

+

+				if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40)

+					customer_pwr_limit = pHalData->PwrGroupHT40[rf][Channel-1];

+				else

+					customer_pwr_limit = pHalData->PwrGroupHT20[rf][Channel-1];

+

+				//RTPRINT(FPHY, PHY_TXPWR, ("customer pwr limit  rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), customer_pwr_limit));

+

+				if(pwr_diff >= customer_pwr_limit)

+					pwr_diff = 0;

+				else

+					pwr_diff = customer_pwr_limit - pwr_diff;

+				

+				for (i=0; i<4; i++)

+					{

+					pwr_diff_limit[i] = (u1Byte)((pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]&(0x7f<<(i*8)))>>(i*8));

+					

+					if(pwr_diff_limit[i] > pwr_diff)

+						pwr_diff_limit[i] = pwr_diff;

+				}

+				customer_limit = (pwr_diff_limit[3]<<24) | (pwr_diff_limit[2]<<16) |

+								(pwr_diff_limit[1]<<8) | (pwr_diff_limit[0]);

+				//RTPRINT(FPHY, PHY_TXPWR, ("Customer's limit rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), customer_limit));

+				writeVal = customer_limit + ((index<2)?powerBase0[rf]:powerBase1[rf]);

+				//RTPRINT(FPHY, PHY_TXPWR, ("Customer, writeVal rf(%c)= 0x%x\n", ((rf==0)?'A':'B'), writeVal));

+				break;

+			default:

+				chnlGroup = 0;

+				writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] + 

+						((index<2)?powerBase0[rf]:powerBase1[rf]);

+				//RTPRINT(FPHY, PHY_TXPWR, ("RTK better performance, writeVal rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));

+				break;

+		}

+

+// 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism.

+// Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism.

+// In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder.

+		//92d do not need this

+		if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)

+			writeVal = 0x14141414;

+		else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)

+			writeVal = 0x00000000;

+

+		// 20100628 Joseph: High power mode for BT-Coexist mechanism.

+		// This mechanism is only applied when Driver-Highpower-Mechanism is OFF.

+		if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT1)

+		{

+			//RTPRINT(FBT, BT_TRACE, ("Tx Power (-6)\n"));

+			writeVal = writeVal - 0x06060606;

+		}

+		else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT2)

+		{

+			//RTPRINT(FBT, BT_TRACE, ("Tx Power (-0)\n"));

+			writeVal = writeVal ;		

+		}

+		/*

+		if(pMgntInfo->bDisableTXPowerByRate)

+		{

+		// add for  OID_RT_11N_TX_POWER_BY_RATE ,disable tx powre change by rate                                  

+			writeVal = 0x2c2c2c2c;

+		}

+		*/

+		*(pOutWriteVal+rf) = writeVal;

+	}

+}

+

+static void writeOFDMPowerReg88E(

+	IN		PADAPTER	Adapter,

+	IN		u8		index,

+	IN 		u32*		pValue

+	)

+{

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);

+	u16 RegOffset_A[6] = {	rTxAGC_A_Rate18_06, rTxAGC_A_Rate54_24,

+							rTxAGC_A_Mcs03_Mcs00, rTxAGC_A_Mcs07_Mcs04,

+							rTxAGC_A_Mcs11_Mcs08, rTxAGC_A_Mcs15_Mcs12};

+	u16 RegOffset_B[6] = {	rTxAGC_B_Rate18_06, rTxAGC_B_Rate54_24,

+							rTxAGC_B_Mcs03_Mcs00, rTxAGC_B_Mcs07_Mcs04,

+							rTxAGC_B_Mcs11_Mcs08, rTxAGC_B_Mcs15_Mcs12};

+	u8 i, rf, pwr_val[4];

+	u32 writeVal;

+	u16 RegOffset;

+

+	for(rf=0; rf<2; rf++)

+	{

+		writeVal = pValue[rf];

+		for(i=0; i<4; i++)

+		{

+			pwr_val[i] = (u8)((writeVal & (0x7f<<(i*8)))>>(i*8));

+			if (pwr_val[i]  > RF6052_MAX_TX_PWR)

+				pwr_val[i]  = RF6052_MAX_TX_PWR;

+		}

+		writeVal = (pwr_val[3]<<24) | (pwr_val[2]<<16) |(pwr_val[1]<<8) |pwr_val[0];

+

+		if(rf == 0)

+			RegOffset = RegOffset_A[index];

+		else

+			RegOffset = RegOffset_B[index];

+

+		PHY_SetBBReg(Adapter, RegOffset, bMaskDWord, writeVal);

+		//RTPRINT(FPHY, PHY_TXPWR, ("Set 0x%x = %08x\n", RegOffset, writeVal));

+

+		// 201005115 Joseph: Set Tx Power diff for Tx power training mechanism.

+		if(((pHalData->rf_type == RF_2T2R) &&

+				(RegOffset == rTxAGC_A_Mcs15_Mcs12 || RegOffset == rTxAGC_B_Mcs15_Mcs12))||

+		     ((pHalData->rf_type != RF_2T2R) &&

+				(RegOffset == rTxAGC_A_Mcs07_Mcs04 || RegOffset == rTxAGC_B_Mcs07_Mcs04))	)

+		{

+			writeVal = pwr_val[3];

+			if(RegOffset == rTxAGC_A_Mcs15_Mcs12 || RegOffset == rTxAGC_A_Mcs07_Mcs04)

+				RegOffset = 0xc90;

+			if(RegOffset == rTxAGC_B_Mcs15_Mcs12 || RegOffset == rTxAGC_B_Mcs07_Mcs04)

+				RegOffset = 0xc98;

+			for(i=0; i<3; i++)

+			{

+				if(i!=2)

+					writeVal = (writeVal>8)?(writeVal-8):0;

+				else

+					writeVal = (writeVal>6)?(writeVal-6):0;

+				rtw_write8(Adapter, (u32)(RegOffset+i), (u8)writeVal);

+			}

+		}

+	}

+}

+

+

+/*-----------------------------------------------------------------------------

+ * Function:	PHY_RF6052SetOFDMTxPower

+ *

+ * Overview:	For legacy and HY OFDM, we must read EEPROM TX power index for

+ *			different channel and read original value in TX power register area from

+ *			0xe00. We increase offset and original value to be correct tx pwr.

+ *

+ * Input:       NONE

+ *

+ * Output:      NONE

+ *

+ * Return:      NONE

+ *

+ * Revised History:

+ * When			Who		Remark

+ * 11/05/2008 	MHC		Simulate 8192 series method.

+ * 01/06/2009	MHC		1. Prevent Path B tx power overflow or underflow dure to

+ *						A/B pwr difference or legacy/HT pwr diff.

+ *						2. We concern with path B legacy/HT OFDM difference.

+ * 01/22/2009	MHC		Support new EPRO format from SD3.

+ *

+ *---------------------------------------------------------------------------*/

+

+VOID 

+rtl8188e_PHY_RF6052SetOFDMTxPower(

+	IN	PADAPTER	Adapter,

+	IN	u8*		pPowerLevelOFDM,

+	IN	u8*		pPowerLevelBW20,

+	IN	u8*		pPowerLevelBW40,	

+	IN	u8		Channel)

+{

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);

+	u32 writeVal[2], powerBase0[2], powerBase1[2], pwrtrac_value;

+	u8 direction;

+	u8 index = 0;	

+	

+

+	//DBG_871X("PHY_RF6052SetOFDMTxPower, channel(%d) \n", Channel);

+

+	getPowerBase88E(Adapter, pPowerLevelOFDM,pPowerLevelBW20,pPowerLevelBW40, Channel, &powerBase0[0], &powerBase1[0]);

+

+	//

+	// 2012/04/23 MH According to power tracking value, we need to revise OFDM tx power.

+	// This is ued to fix unstable power tracking mode.

+	//

+	ODM_TxPwrTrackAdjust88E(&pHalData->odmpriv, 0, &direction, &pwrtrac_value);

+	

+	for(index=0; index<6; index++)

+	{

+		getTxPowerWriteValByRegulatory88E(Adapter, Channel, index, 

+			&powerBase0[0], &powerBase1[0], &writeVal[0]);

+

+		if (direction == 1)

+		{

+			writeVal[0] += pwrtrac_value;

+			writeVal[1] += pwrtrac_value;

+		}

+		else if (direction == 2)

+		{

+			writeVal[0] -= pwrtrac_value;

+			writeVal[1] -= pwrtrac_value;

+		}

+		

+		writeOFDMPowerReg88E(Adapter, index, &writeVal[0]);

+	}

+}

+

+

+static VOID

+phy_RF6052_Config_HardCode(

+	IN	PADAPTER		Adapter

+	)

+{

+

+	// Set Default Bandwidth to 20M

+	//Adapter->HalFunc	.SetBWModeHandler(Adapter, HT_CHANNEL_WIDTH_20);

+

+	// TODO: Set Default Channel to channel one for RTL8225

+

+}

+

+static int

+phy_RF6052_Config_ParaFile(

+	IN	PADAPTER		Adapter

+	)

+{

+	u32					u4RegValue;

+	u8					eRFPath;

+	BB_REGISTER_DEFINITION_T	*pPhyReg;

+

+	int					rtStatus = _SUCCESS;

+	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(Adapter);

+

+	static char			sz88eRadioAFile[] = RTL8188E_PHY_RADIO_A;

+	static char			sz88eRadioBFile[] = RTL8188E_PHY_RADIO_B;

+	char					*pszRadioAFile, *pszRadioBFile;

+

+

+

+	pszRadioAFile = sz88eRadioAFile;

+	pszRadioBFile = sz88eRadioBFile;

+

+

+	//3//-----------------------------------------------------------------

+	//3// <2> Initialize RF

+	//3//-----------------------------------------------------------------

+	//for(eRFPath = RF_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)

+	for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)

+	{

+

+		pPhyReg = &pHalData->PHYRegDef[eRFPath];

+

+		/*----Store original RFENV control type----*/

+		switch(eRFPath)

+		{

+		case RF_PATH_A:

+		case RF_PATH_C:

+			u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV);

+			break;

+		case RF_PATH_B :

+		case RF_PATH_D:

+			u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16);

+			break;

+		}

+

+		/*----Set RF_ENV enable----*/

+		PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);

+		rtw_udelay_os(1);//PlatformStallExecution(1);

+

+		/*----Set RF_ENV output high----*/

+		PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);

+		rtw_udelay_os(1);//PlatformStallExecution(1);

+

+		/* Set bit number of Address and Data for RF register */

+		PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); 	// Set 1 to 4 bits for 8255

+		rtw_udelay_os(1);//PlatformStallExecution(1);

+

+		PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0);	// Set 0 to 12  bits for 8255

+		rtw_udelay_os(1);//PlatformStallExecution(1);

+

+		/*----Initialize RF fom connfiguration file----*/

+		switch(eRFPath)

+		{

+		case RF_PATH_A:

+#ifdef CONFIG_EMBEDDED_FWIMG

+			#ifdef CONFIG_PHY_SETTING_WITH_ODM

+			if(HAL_STATUS_FAILURE ==ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv,(ODM_RF_RADIO_PATH_E)eRFPath, (ODM_RF_RADIO_PATH_E)eRFPath))

+				rtStatus= _FAIL;

+			#else

+				rtStatus= rtl8188e_PHY_ConfigRFWithHeaderFile(Adapter,(RF_RADIO_PATH_E)eRFPath);

+			#endif//#ifdef CONFIG_PHY_SETTING_WITH_ODM

+#else

+			rtStatus = rtl8188e_PHY_ConfigRFWithParaFile(Adapter, pszRadioAFile, (RF_RADIO_PATH_E)eRFPath);

+#endif//#ifdef CONFIG_EMBEDDED_FWIMG

+			break;

+		case RF_PATH_B:

+#ifdef CONFIG_EMBEDDED_FWIMG

+			#ifdef CONFIG_PHY_SETTING_WITH_ODM

+			if(HAL_STATUS_FAILURE ==ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv,(ODM_RF_RADIO_PATH_E)eRFPath, (ODM_RF_RADIO_PATH_E)eRFPath))

+				rtStatus= _FAIL;	

+			#else

+				rtStatus = rtl8188e_PHY_ConfigRFWithHeaderFile(Adapter,(RF_RADIO_PATH_E)eRFPath);

+			#endif //#ifdef CONFIG_PHY_SETTING_WITH_ODM

+#else

+			rtStatus =rtl8188e_PHY_ConfigRFWithParaFile(Adapter, pszRadioBFile, (RF_RADIO_PATH_E)eRFPath);

+#endif

+			break;

+		case RF_PATH_C:

+			break;

+		case RF_PATH_D:

+			break;

+		}

+

+		/*----Restore RFENV control type----*/;

+		switch(eRFPath)

+		{

+		case RF_PATH_A:

+		case RF_PATH_C:

+			PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);

+			break;

+		case RF_PATH_B :

+		case RF_PATH_D:

+			PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);

+			break;

+		}

+

+		if(rtStatus != _SUCCESS){

+			//RT_TRACE(COMP_FPGA, DBG_LOUD, ("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath));

+			goto phy_RF6052_Config_ParaFile_Fail;

+		}

+

+	}

+

+	//RT_TRACE(COMP_INIT, DBG_LOUD, ("<---phy_RF6052_Config_ParaFile()\n"));

+	return rtStatus;

+

+phy_RF6052_Config_ParaFile_Fail:

+	return rtStatus;

+}

+

+

+int

+PHY_RF6052_Config8188E(

+	IN	PADAPTER		Adapter)

+{

+	HAL_DATA_TYPE				*pHalData = GET_HAL_DATA(Adapter);

+	int					rtStatus = _SUCCESS;

+

+	//

+	// Initialize general global value

+	//

+	// TODO: Extend RF_PATH_C and RF_PATH_D in the future

+	if(pHalData->rf_type == RF_1T1R)

+		pHalData->NumTotalRFPath = 1;

+	else

+		pHalData->NumTotalRFPath = 2;

+

+	//

+	// Config BB and RF

+	//

+	rtStatus = phy_RF6052_Config_ParaFile(Adapter);

+#if 0

+	switch( Adapter->MgntInfo.bRegHwParaFile )

+	{

+		case 0:

+			phy_RF6052_Config_HardCode(Adapter);

+			break;

+

+		case 1:

+			rtStatus = phy_RF6052_Config_ParaFile(Adapter);

+			break;

+

+		case 2:

+			// Partial Modify.

+			phy_RF6052_Config_HardCode(Adapter);

+			phy_RF6052_Config_ParaFile(Adapter);

+			break;

+

+		default:

+			phy_RF6052_Config_HardCode(Adapter);

+			break;

+	}

+#endif

+	return rtStatus;

+

+}

+

+

+//

+// ==> RF shadow Operation API Code Section!!!

+//

+/*-----------------------------------------------------------------------------

+ * Function:	PHY_RFShadowRead

+ *				PHY_RFShadowWrite

+ *				PHY_RFShadowCompare

+ *				PHY_RFShadowRecorver

+ *				PHY_RFShadowCompareAll

+ *				PHY_RFShadowRecorverAll

+ *				PHY_RFShadowCompareFlagSet

+ *				PHY_RFShadowRecorverFlagSet

+ *

+ * Overview:	When we set RF register, we must write shadow at first.

+ *			When we are running, we must compare shadow abd locate error addr.

+ *			Decide to recorver or not.

+ *

+ * Input:       NONE

+ *

+ * Output:      NONE

+ *

+ * Return:      NONE

+ *

+ * Revised History:

+ * When			Who		Remark

+ * 11/20/2008 	MHC		Create Version 0.

+ *

+ *---------------------------------------------------------------------------*/

+u32

+PHY_RFShadowRead(

+	IN	PADAPTER			Adapter,

+	IN	RF_RADIO_PATH_E	eRFPath,

+	IN	u32				Offset)

+{

+	return	RF_Shadow[eRFPath][Offset].Value;

+

+}	/* PHY_RFShadowRead */

+

+

+VOID

+PHY_RFShadowWrite(

+	IN	PADAPTER			Adapter,

+	IN	RF_RADIO_PATH_E	eRFPath,

+	IN	u32				Offset,

+	IN	u32				Data)

+{

+	RF_Shadow[eRFPath][Offset].Value = (Data & bRFRegOffsetMask);

+	RF_Shadow[eRFPath][Offset].Driver_Write = _TRUE;

+

+}	/* PHY_RFShadowWrite */

+

+

+BOOLEAN

+PHY_RFShadowCompare(

+	IN	PADAPTER			Adapter,

+	IN	RF_RADIO_PATH_E	eRFPath,

+	IN	u32				Offset)

+{

+	u32	reg;

+	// Check if we need to check the register

+	if (RF_Shadow[eRFPath][Offset].Compare == _TRUE)

+	{

+		reg = PHY_QueryRFReg(Adapter, eRFPath, Offset, bRFRegOffsetMask);

+		// Compare shadow and real rf register for 20bits!!

+		if (RF_Shadow[eRFPath][Offset].Value != reg)

+		{

+			// Locate error position.

+			RF_Shadow[eRFPath][Offset].ErrorOrNot = _TRUE;

+			//RT_TRACE(COMP_INIT, DBG_LOUD,

+			//("PHY_RFShadowCompare RF-%d Addr%02lx Err = %05lx\n",

+			//eRFPath, Offset, reg));

+		}

+		return RF_Shadow[eRFPath][Offset].ErrorOrNot ;

+	}

+	return _FALSE;

+}	/* PHY_RFShadowCompare */

+

+

+VOID

+PHY_RFShadowRecorver(

+	IN	PADAPTER			Adapter,

+	IN	RF_RADIO_PATH_E	eRFPath,

+	IN	u32				Offset)

+{

+	// Check if the address is error

+	if (RF_Shadow[eRFPath][Offset].ErrorOrNot == _TRUE)

+	{

+		// Check if we need to recorver the register.

+		if (RF_Shadow[eRFPath][Offset].Recorver == _TRUE)

+		{

+			PHY_SetRFReg(Adapter, eRFPath, Offset, bRFRegOffsetMask,

+							RF_Shadow[eRFPath][Offset].Value);

+			//RT_TRACE(COMP_INIT, DBG_LOUD,

+			//("PHY_RFShadowRecorver RF-%d Addr%02lx=%05lx",

+			//eRFPath, Offset, RF_Shadow[eRFPath][Offset].Value));

+		}

+	}

+

+}	/* PHY_RFShadowRecorver */

+

+

+VOID

+PHY_RFShadowCompareAll(

+	IN	PADAPTER			Adapter)

+{

+	u32		eRFPath;

+	u32		Offset;

+

+	for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)

+	{

+		for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)

+		{

+			PHY_RFShadowCompare(Adapter, (RF_RADIO_PATH_E)eRFPath, Offset);

+		}

+	}

+

+}	/* PHY_RFShadowCompareAll */

+

+

+VOID

+PHY_RFShadowRecorverAll(

+	IN	PADAPTER			Adapter)

+{

+	u32		eRFPath;

+	u32		Offset;

+

+	for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)

+	{

+		for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)

+		{

+			PHY_RFShadowRecorver(Adapter, (RF_RADIO_PATH_E)eRFPath, Offset);

+		}

+	}

+

+}	/* PHY_RFShadowRecorverAll */

+

+

+VOID

+PHY_RFShadowCompareFlagSet(

+	IN	PADAPTER			Adapter,

+	IN	RF_RADIO_PATH_E	eRFPath,

+	IN	u32				Offset,

+	IN	u8				Type)

+{

+	// Set True or False!!!

+	RF_Shadow[eRFPath][Offset].Compare = Type;

+

+}	/* PHY_RFShadowCompareFlagSet */

+

+

+VOID

+PHY_RFShadowRecorverFlagSet(

+	IN	PADAPTER			Adapter,

+	IN	RF_RADIO_PATH_E	eRFPath,

+	IN	u32				Offset,

+	IN	u8				Type)

+{

+	// Set True or False!!!

+	RF_Shadow[eRFPath][Offset].Recorver= Type;

+

+}	/* PHY_RFShadowRecorverFlagSet */

+

+

+VOID

+PHY_RFShadowCompareFlagSetAll(

+	IN	PADAPTER			Adapter)

+{

+	u32		eRFPath;

+	u32		Offset;

+

+	for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)

+	{

+		for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)

+		{

+			// 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!!

+			if (Offset != 0x26 && Offset != 0x27)

+				PHY_RFShadowCompareFlagSet(Adapter, (RF_RADIO_PATH_E)eRFPath, Offset, _FALSE);

+			else

+				PHY_RFShadowCompareFlagSet(Adapter, (RF_RADIO_PATH_E)eRFPath, Offset, _TRUE);

+		}

+	}

+

+}	/* PHY_RFShadowCompareFlagSetAll */

+

+

+VOID

+PHY_RFShadowRecorverFlagSetAll(

+	IN	PADAPTER			Adapter)

+{

+	u32		eRFPath;

+	u32		Offset;

+

+	for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)

+	{

+		for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)

+		{

+			// 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!!

+			if (Offset != 0x26 && Offset != 0x27)

+				PHY_RFShadowRecorverFlagSet(Adapter, (RF_RADIO_PATH_E)eRFPath, Offset, _FALSE);

+			else

+				PHY_RFShadowRecorverFlagSet(Adapter, (RF_RADIO_PATH_E)eRFPath, Offset, _TRUE);

+		}

+	}

+

+}	/* PHY_RFShadowCompareFlagSetAll */

+

+VOID

+PHY_RFShadowRefresh(

+	IN	PADAPTER			Adapter)

+{

+	u32		eRFPath;

+	u32		Offset;

+

+	for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)

+	{

+		for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)

+		{

+			RF_Shadow[eRFPath][Offset].Value = 0;

+			RF_Shadow[eRFPath][Offset].Compare = _FALSE;

+			RF_Shadow[eRFPath][Offset].Recorver  = _FALSE;

+			RF_Shadow[eRFPath][Offset].ErrorOrNot = _FALSE;

+			RF_Shadow[eRFPath][Offset].Driver_Write = _FALSE;

+		}

+	}

+

+}	/* PHY_RFShadowRead */

+

+/* End of HalRf6052.c */

+

diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/rtl8188e_rxdesc.c b/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/rtl8188e_rxdesc.c
new file mode 100755
index 00000000..21df6d30
--- /dev/null
+++ b/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/rtl8188e_rxdesc.c
@@ -0,0 +1,355 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#define _RTL8188E_REDESC_C_
+
+#include <drv_conf.h>
+#include <osdep_service.h>
+#include <drv_types.h>
+#include <rtl8188e_hal.h>
+
+static s32  translate2dbm(u8 signal_strength_idx)
+{
+	s32	signal_power; // in dBm.
+
+
+	// Translate to dBm (x=0.5y-95).
+	signal_power = (s32)((signal_strength_idx + 1) >> 1);
+	signal_power -= 95;
+
+	return signal_power;
+}
+
+
+static void process_rssi(_adapter *padapter,union recv_frame *prframe)
+{
+	u32	last_rssi, tmp_val;
+	struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;
+#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
+	struct signal_stat * signal_stat = &padapter->recvpriv.signal_strength_data;
+#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS
+
+	//DBG_8192C("process_rssi=> pattrib->rssil(%d) signal_strength(%d)\n ",pattrib->RecvSignalPower,pattrib->signal_strength);
+	//if(pRfd->Status.bPacketToSelf || pRfd->Status.bPacketBeacon)
+	{
+	
+	#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
+		if(signal_stat->update_req) {
+			signal_stat->total_num = 0;
+			signal_stat->total_val = 0;
+			signal_stat->update_req = 0;
+		}
+
+		signal_stat->total_num++;
+		signal_stat->total_val  += pattrib->phy_info.SignalStrength;
+		signal_stat->avg_val = signal_stat->total_val / signal_stat->total_num;		
+	#else //CONFIG_NEW_SIGNAL_STAT_PROCESS
+	
+		//Adapter->RxStats.RssiCalculateCnt++;	//For antenna Test
+		if(padapter->recvpriv.signal_strength_data.total_num++ >= PHY_RSSI_SLID_WIN_MAX)
+		{
+			padapter->recvpriv.signal_strength_data.total_num = PHY_RSSI_SLID_WIN_MAX;
+			last_rssi = padapter->recvpriv.signal_strength_data.elements[padapter->recvpriv.signal_strength_data.index];
+			padapter->recvpriv.signal_strength_data.total_val -= last_rssi;
+		}
+		padapter->recvpriv.signal_strength_data.total_val  +=pattrib->phy_info.SignalStrength;
+
+		padapter->recvpriv.signal_strength_data.elements[padapter->recvpriv.signal_strength_data.index++] = pattrib->phy_info.SignalStrength;
+		if(padapter->recvpriv.signal_strength_data.index >= PHY_RSSI_SLID_WIN_MAX)
+			padapter->recvpriv.signal_strength_data.index = 0;
+
+
+		tmp_val = padapter->recvpriv.signal_strength_data.total_val/padapter->recvpriv.signal_strength_data.total_num;
+		
+		if(padapter->recvpriv.is_signal_dbg) {
+			padapter->recvpriv.signal_strength= padapter->recvpriv.signal_strength_dbg;
+			padapter->recvpriv.rssi=(s8)translate2dbm((u8)padapter->recvpriv.signal_strength_dbg);
+		} else {
+			padapter->recvpriv.signal_strength= tmp_val;
+			padapter->recvpriv.rssi=(s8)translate2dbm((u8)tmp_val);
+		}
+
+		RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("UI RSSI = %d, ui_rssi.TotalVal = %d, ui_rssi.TotalNum = %d\n", tmp_val, padapter->recvpriv.signal_strength_data.total_val,padapter->recvpriv.signal_strength_data.total_num));
+	#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS
+	}
+
+}// Process_UI_RSSI_8192C
+
+
+
+static void process_link_qual(_adapter *padapter,union recv_frame *prframe)
+{
+	u32	last_evm=0, tmpVal;
+ 	struct rx_pkt_attrib *pattrib;
+#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
+	struct signal_stat * signal_stat;
+#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS
+
+	if(prframe == NULL || padapter==NULL){
+		return;
+	}
+
+	pattrib = &prframe->u.hdr.attrib;
+#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
+	signal_stat = &padapter->recvpriv.signal_qual_data;
+#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS
+
+	//DBG_8192C("process_link_qual=> pattrib->signal_qual(%d)\n ",pattrib->signal_qual);
+
+#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
+	if(signal_stat->update_req) {
+		signal_stat->total_num = 0;
+		signal_stat->total_val = 0;
+		signal_stat->update_req = 0;
+	}
+
+	signal_stat->total_num++;
+	signal_stat->total_val  += pattrib->phy_info.SignalQuality;
+	signal_stat->avg_val = signal_stat->total_val / signal_stat->total_num;
+	
+#else //CONFIG_NEW_SIGNAL_STAT_PROCESS
+	if(pattrib->phy_info.SignalQuality != 0)
+	{
+			//
+			// 1. Record the general EVM to the sliding window.
+			//
+			if(padapter->recvpriv.signal_qual_data.total_num++ >= PHY_LINKQUALITY_SLID_WIN_MAX)
+			{
+				padapter->recvpriv.signal_qual_data.total_num = PHY_LINKQUALITY_SLID_WIN_MAX;
+				last_evm = padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index];
+				padapter->recvpriv.signal_qual_data.total_val -= last_evm;
+			}
+			padapter->recvpriv.signal_qual_data.total_val += pattrib->phy_info.SignalQuality;
+
+			padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index++] = pattrib->phy_info.SignalQuality;
+			if(padapter->recvpriv.signal_qual_data.index >= PHY_LINKQUALITY_SLID_WIN_MAX)
+				padapter->recvpriv.signal_qual_data.index = 0;
+
+			RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("Total SQ=%d  pattrib->signal_qual= %d\n", padapter->recvpriv.signal_qual_data.total_val, pattrib->phy_info.SignalQuality));
+
+			// <1> Showed on UI for user, in percentage.
+			tmpVal = padapter->recvpriv.signal_qual_data.total_val/padapter->recvpriv.signal_qual_data.total_num;
+			padapter->recvpriv.signal_qual=(u8)tmpVal;
+
+	}
+	else
+	{
+		RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,(" pattrib->signal_qual =%d\n", pattrib->phy_info.SignalQuality));
+	}
+#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS
+
+}
+
+//void rtl8188e_process_phy_info(_adapter *padapter, union recv_frame *prframe)
+void rtl8188e_process_phy_info(_adapter *padapter, void *prframe)
+{
+	union recv_frame *precvframe = (union recv_frame *)prframe;
+
+	//
+	// Check RSSI
+	//
+	process_rssi(padapter, precvframe);
+	//
+	// Check PWDB.
+	//
+	//process_PWDB(padapter, precvframe); 
+
+	//UpdateRxSignalStatistics8192C(Adapter, pRfd);
+	//
+	// Check EVM
+	//
+	process_link_qual(padapter,  precvframe);
+
+}
+
+
+void update_recvframe_attrib_88e(
+	union recv_frame *precvframe,
+	struct recv_stat *prxstat)
+{
+	struct rx_pkt_attrib	*pattrib;
+	struct recv_stat	report;
+	PRXREPORT		prxreport;
+	//struct recv_frame_hdr	*phdr;
+
+	//phdr = &precvframe->u.hdr;
+
+	report.rxdw0 = le32_to_cpu(prxstat->rxdw0);
+	report.rxdw1 = le32_to_cpu(prxstat->rxdw1);
+	report.rxdw2 = le32_to_cpu(prxstat->rxdw2);
+	report.rxdw3 = le32_to_cpu(prxstat->rxdw3);
+	report.rxdw4 = le32_to_cpu(prxstat->rxdw4);
+	report.rxdw5 = le32_to_cpu(prxstat->rxdw5);
+
+	prxreport = (PRXREPORT)&report;
+
+	pattrib = &precvframe->u.hdr.attrib;
+	_rtw_memset(pattrib, 0, sizeof(struct rx_pkt_attrib));
+
+	pattrib->crc_err = (u8)((report.rxdw0 >> 14) & 0x1);;//(u8)prxreport->crc32;	
+	
+	// update rx report to recv_frame attribute
+	pattrib->pkt_rpt_type = (u8)((report.rxdw3 >> 14) & 0x3);//prxreport->rpt_sel;
+	
+	if(pattrib->pkt_rpt_type == NORMAL_RX)//Normal rx packet	
+	{
+		pattrib->pkt_len = (u16)(report.rxdw0 &0x00003fff);//(u16)prxreport->pktlen;
+		pattrib->drvinfo_sz = (u8)((report.rxdw0 >> 16) & 0xf) * 8;//(u8)(prxreport->drvinfosize << 3);
+			
+		pattrib->physt =  (u8)((report.rxdw0 >> 26) & 0x1);//(u8)prxreport->physt;	
+
+		pattrib->bdecrypted = (report.rxdw0 & BIT(27))? 0:1;//(u8)(prxreport->swdec ? 0 : 1);
+		pattrib->encrypt = (u8)((report.rxdw0 >> 20) & 0x7);//(u8)prxreport->security;
+
+		pattrib->qos = (u8)((report.rxdw0 >> 23) & 0x1);//(u8)prxreport->qos;
+		pattrib->priority = (u8)((report.rxdw1 >> 8) & 0xf);//(u8)prxreport->tid;
+
+		pattrib->amsdu = (u8)((report.rxdw1 >> 13) & 0x1);//(u8)prxreport->amsdu;
+
+		pattrib->seq_num = (u16)(report.rxdw2 & 0x00000fff);//(u16)prxreport->seq;
+		pattrib->frag_num = (u8)((report.rxdw2 >> 12) & 0xf);//(u8)prxreport->frag;
+		pattrib->mfrag = (u8)((report.rxdw1 >> 27) & 0x1);//(u8)prxreport->mf;
+		pattrib->mdata = (u8)((report.rxdw1 >> 26) & 0x1);//(u8)prxreport->md;
+
+		pattrib->mcs_rate = (u8)(report.rxdw3 & 0x3f);//(u8)prxreport->rxmcs;
+		pattrib->rxht = (u8)((report.rxdw3 >> 6) & 0x1);//(u8)prxreport->rxht;
+		
+		pattrib->icv_err = (u8)((report.rxdw0 >> 15) & 0x1);//(u8)prxreport->icverr;
+		pattrib->shift_sz = (u8)((report.rxdw0 >> 24) & 0x3);
+	
+	}
+	else if(pattrib->pkt_rpt_type == TX_REPORT1)//CCX
+	{
+		pattrib->pkt_len = TX_RPT1_PKT_LEN;
+		pattrib->drvinfo_sz = 0;
+	}
+	else if(pattrib->pkt_rpt_type == TX_REPORT2)// TX RPT
+	{
+		pattrib->pkt_len =(u16)(report.rxdw0 & 0x3FF);//Rx length[9:0]
+		pattrib->drvinfo_sz = 0;
+
+		//
+		// Get TX report MAC ID valid.
+		//
+		pattrib->MacIDValidEntry[0] = report.rxdw4;
+		pattrib->MacIDValidEntry[1] = report.rxdw5;
+		
+	}
+	else if(pattrib->pkt_rpt_type == HIS_REPORT)// USB HISR RPT
+	{
+		pattrib->pkt_len = (u16)(report.rxdw0 &0x00003fff);//(u16)prxreport->pktlen;
+	}	
+	
+}
+
+/*
+ * Notice:
+ *	Before calling this function,
+ *	precvframe->u.hdr.rx_data should be ready!
+ */
+void update_recvframe_phyinfo_88e(
+	union recv_frame	*precvframe,
+	struct phy_stat *pphy_status)
+{
+	PADAPTER 			padapter = precvframe->u.hdr.adapter;
+	struct rx_pkt_attrib	*pattrib = &precvframe->u.hdr.attrib;
+	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(padapter);	
+	PODM_PHY_INFO_T 	pPHYInfo  = (PODM_PHY_INFO_T)(&pattrib->phy_info);
+	u8					*wlanhdr;
+	ODM_PACKET_INFO_T	pkt_info;
+	u8 *sa;
+	struct sta_priv *pstapriv;
+	struct sta_info *psta;
+	//_irqL		irqL;
+	
+	pkt_info.bPacketMatchBSSID =_FALSE;
+	pkt_info.bPacketToSelf = _FALSE;
+	pkt_info.bPacketBeacon = _FALSE;
+	
+	wlanhdr = get_recvframe_data(precvframe);
+
+	pkt_info.bPacketMatchBSSID = ((!IsFrameTypeCtrl(wlanhdr)) &&
+		!pattrib->icv_err && !pattrib->crc_err &&
+		_rtw_memcmp(get_hdr_bssid(wlanhdr), get_bssid(&padapter->mlmepriv), ETH_ALEN));
+
+	pkt_info.bPacketToSelf = pkt_info.bPacketMatchBSSID && (_rtw_memcmp(get_da(wlanhdr), myid(&padapter->eeprompriv), ETH_ALEN));
+
+	pkt_info.bPacketBeacon = pkt_info.bPacketMatchBSSID && (GetFrameSubType(wlanhdr) == WIFI_BEACON);
+
+	if(pkt_info.bPacketBeacon){
+		if(check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == _TRUE){				
+			sa = padapter->mlmepriv.cur_network.network.MacAddress;
+			#if 0
+			{					
+				DBG_8192C("==> rx beacon from AP[%02x:%02x:%02x:%02x:%02x:%02x]\n",
+					sa[0],sa[1],sa[2],sa[3],sa[4],sa[5]);					
+			}
+			#endif
+		}
+		//to do Ad-hoc
+	}
+	else{
+		sa = get_sa(wlanhdr);
+	}	
+	
+	pstapriv = &padapter->stapriv;
+	pkt_info.StationID = 0xFF;
+	psta = rtw_get_stainfo(pstapriv, sa);
+	if (psta)
+	{
+		pkt_info.StationID = psta->mac_id;		
+		//DBG_8192C("%s ==> StationID(%d)\n",__FUNCTION__,pkt_info.StationID);
+	}			
+	pkt_info.Rate = pattrib->mcs_rate;	
+	//rtl8188e_query_rx_phy_status(precvframe, pphy_status);
+
+	#ifdef CONFIG_CONCURRENT_MODE	
+	//get Primary adapter's odmpriv
+	if(padapter->adapter_type > PRIMARY_ADAPTER){
+		pHalData = GET_HAL_DATA(padapter->pbuddy_adapter);		
+	}
+	#endif
+	//_enter_critical_bh(&pHalData->odm_stainfo_lock, &irqL);	
+	ODM_PhyStatusQuery(&pHalData->odmpriv,pPHYInfo,(u8 *)pphy_status,&(pkt_info));
+	//_exit_critical_bh(&pHalData->odm_stainfo_lock, &irqL);
+
+	precvframe->u.hdr.psta = NULL;
+	if (pkt_info.bPacketMatchBSSID &&
+		(check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE))
+	{		
+		if (psta)
+		{			
+			precvframe->u.hdr.psta = psta;
+			rtl8188e_process_phy_info(padapter, precvframe);
+			
+		}		
+	}
+	else if (pkt_info.bPacketToSelf || pkt_info.bPacketBeacon)
+	{
+		if (check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE) == _TRUE)
+		{		
+			if (psta)
+			{				
+				precvframe->u.hdr.psta = psta;
+			}
+		}
+		rtl8188e_process_phy_info(padapter, precvframe);		
+	}
+}
+
diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/rtl8188e_sreset.c b/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/rtl8188e_sreset.c
new file mode 100755
index 00000000..38a10fea
--- /dev/null
+++ b/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/rtl8188e_sreset.c
@@ -0,0 +1,118 @@
+/******************************************************************************

+ *

+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.

+ *

+ * This program is free software; you can redistribute it and/or modify it

+ * under the terms of version 2 of the GNU General Public License as

+ * published by the Free Software Foundation.

+ *

+ * This program is distributed in the hope that it will be useful, but WITHOUT

+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for

+ * more details.

+ *

+ * You should have received a copy of the GNU General Public License along with

+ * this program; if not, write to the Free Software Foundation, Inc.,

+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA

+ *

+ *

+ ******************************************************************************/

+#define _RTL8188E_SRESET_C_

+

+#include <rtl8188e_sreset.h>

+#include <rtl8188e_hal.h>

+

+#ifdef DBG_CONFIG_ERROR_DETECT

+

+void rtl8188e_sreset_xmit_status_check(_adapter *padapter)

+{

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);

+	struct sreset_priv *psrtpriv = &pHalData->srestpriv;

+

+	unsigned long current_time;

+	struct xmit_priv	*pxmitpriv = &padapter->xmitpriv;

+	unsigned int diff_time;

+	u32 txdma_status;

+	

+	if( (txdma_status=rtw_read32(padapter, REG_TXDMA_STATUS)) !=0x00){

+		DBG_871X("%s REG_TXDMA_STATUS:0x%08x\n", __FUNCTION__, txdma_status);	

+		rtw_hal_sreset_reset(padapter);

+	}

+#ifdef CONFIG_USB_HCI

+	//total xmit irp = 4

+	//DBG_8192C("==>%s free_xmitbuf_cnt(%d),txirp_cnt(%d)\n",__FUNCTION__,pxmitpriv->free_xmitbuf_cnt,pxmitpriv->txirp_cnt);

+	//if(pxmitpriv->txirp_cnt == NR_XMITBUFF+1)

+	current_time = rtw_get_current_time();

+

+	if(0 == pxmitpriv->free_xmitbuf_cnt || 0 == pxmitpriv->free_xmit_extbuf_cnt) {

+

+		diff_time = rtw_get_passing_time_ms(psrtpriv->last_tx_time);

+

+		if (diff_time > 2000) {

+			if (psrtpriv->last_tx_complete_time == 0) {

+				psrtpriv->last_tx_complete_time = current_time;

+			}

+			else{

+				diff_time = rtw_get_passing_time_ms(psrtpriv->last_tx_complete_time);

+				if (diff_time > 4000) {

+					//padapter->Wifi_Error_Status = WIFI_TX_HANG;

+					DBG_871X("%s tx hang\n", __FUNCTION__);

+					rtw_hal_sreset_reset(padapter);

+				}

+			}

+		}

+	}

+#endif //CONFIG_USB_HCI

+

+	if (psrtpriv->dbg_trigger_point == SRESET_TGP_XMIT_STATUS) {

+		psrtpriv->dbg_trigger_point = SRESET_TGP_NULL;

+		rtw_hal_sreset_reset(padapter);

+		return;

+	}

+}

+

+void rtl8188e_sreset_linked_status_check(_adapter *padapter)

+{

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);

+	struct sreset_priv *psrtpriv = &pHalData->srestpriv;

+

+	u32 rx_dma_status = 0;

+	u8 fw_status=0;

+	rx_dma_status = rtw_read32(padapter,REG_RXDMA_STATUS);

+	if(rx_dma_status!= 0x00){

+		DBG_8192C("%s REG_RXDMA_STATUS:0x%08x \n",__FUNCTION__,rx_dma_status);

+		rtw_write32(padapter,REG_RXDMA_STATUS,rx_dma_status);

+	}	

+	fw_status = rtw_read8(padapter,REG_FMETHR);

+	if(fw_status != 0x00)

+	{		

+		if(fw_status == 1)

+			DBG_8192C("%s REG_FW_STATUS (0x%02x), Read_Efuse_Fail !!   \n",__FUNCTION__,fw_status);

+		else if(fw_status == 2)

+			DBG_8192C("%s REG_FW_STATUS (0x%02x), Condition_No_Match !!   \n",__FUNCTION__,fw_status);

+	}

+#if 0

+	u32 regc50,regc58,reg824,reg800;

+	regc50 = rtw_read32(padapter,0xc50);

+	regc58 = rtw_read32(padapter,0xc58);

+	reg824 = rtw_read32(padapter,0x824);

+	reg800 = rtw_read32(padapter,0x800);

+	if(	((regc50&0xFFFFFF00)!= 0x69543400)||

+		((regc58&0xFFFFFF00)!= 0x69543400)||

+		(((reg824&0xFFFFFF00)!= 0x00390000)&&(((reg824&0xFFFFFF00)!= 0x80390000)))||

+		( ((reg800&0xFFFFFF00)!= 0x03040000)&&((reg800&0xFFFFFF00)!= 0x83040000)))

+	{

+		DBG_8192C("%s regc50:0x%08x, regc58:0x%08x, reg824:0x%08x, reg800:0x%08x,\n", __FUNCTION__,

+			regc50, regc58, reg824, reg800);

+		rtw_hal_sreset_reset(padapter);

+	}

+#endif

+

+	if (psrtpriv->dbg_trigger_point == SRESET_TGP_LINK_STATUS) {

+		psrtpriv->dbg_trigger_point = SRESET_TGP_NULL;

+		rtw_hal_sreset_reset(padapter);

+		return;

+	}

+}

+#endif

+

diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/rtl8188e_xmit.c b/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/rtl8188e_xmit.c
new file mode 100755
index 00000000..55c1ca55
--- /dev/null
+++ b/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/rtl8188e_xmit.c
@@ -0,0 +1,293 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#define _RTL8188E_XMIT_C_
+
+#include <drv_conf.h>
+#include <osdep_service.h>
+#include <drv_types.h>
+#include <sdio_ops.h>
+#include <rtl8188e_hal.h>
+
+#ifdef CONFIG_XMIT_ACK
+void dump_txrpt_ccx_88e(void *buf)
+{
+	struct txrpt_ccx_88e *txrpt_ccx = (struct txrpt_ccx_88e *)buf;
+
+	DBG_871X("%s:\n"
+		"tag1:%u, pkt_num:%u, txdma_underflow:%u, int_bt:%u, int_tri:%u, int_ccx:%u\n"
+		"mac_id:%u, pkt_ok:%u, bmc:%u\n"
+		"retry_cnt:%u, lifetime_over:%u, retry_over:%u\n"
+		"ccx_qtime:%u\n"
+		"final_data_rate:0x%02x\n"
+		"qsel:%u, sw:0x%03x\n"
+		, __func__
+		, txrpt_ccx->tag1, txrpt_ccx->pkt_num, txrpt_ccx->txdma_underflow, txrpt_ccx->int_bt, txrpt_ccx->int_tri, txrpt_ccx->int_ccx
+		, txrpt_ccx->mac_id, txrpt_ccx->pkt_ok, txrpt_ccx->bmc
+		, txrpt_ccx->retry_cnt, txrpt_ccx->lifetime_over, txrpt_ccx->retry_over 
+		, txrpt_ccx_qtime_88e(txrpt_ccx)
+		, txrpt_ccx->final_data_rate
+		, txrpt_ccx->qsel, txrpt_ccx_sw_88e(txrpt_ccx)
+	);
+}
+
+void handle_txrpt_ccx_88e(_adapter *adapter, u8 *buf)
+{
+	struct txrpt_ccx_88e *txrpt_ccx = (struct txrpt_ccx_88e *)buf;
+
+	#ifdef DBG_CCX
+	dump_txrpt_ccx_88e(buf);
+	#endif
+
+	if (txrpt_ccx->int_ccx) {
+		if (txrpt_ccx->pkt_ok)
+			rtw_ack_tx_done(&adapter->xmitpriv, RTW_SCTX_DONE_SUCCESS);
+		else
+			rtw_ack_tx_done(&adapter->xmitpriv, RTW_SCTX_DONE_CCX_PKT_FAIL);
+	}
+}
+#endif //CONFIG_XMIT_ACK
+
+void _dbg_dump_tx_info(_adapter	*padapter,int frame_tag,struct tx_desc *ptxdesc)
+{
+	u8 bDumpTxPkt;
+	u8 bDumpTxDesc = _FALSE;
+	rtw_hal_get_def_var(padapter, HAL_DEF_DBG_DUMP_TXPKT, &(bDumpTxPkt));
+
+	if(bDumpTxPkt ==1){//dump txdesc for data frame
+		DBG_871X("dump tx_desc for data frame\n");
+		if((frame_tag&0x0f) == DATA_FRAMETAG){	
+			bDumpTxDesc = _TRUE;		
+		}
+	}	
+	else if(bDumpTxPkt ==2){//dump txdesc for mgnt frame
+		DBG_871X("dump tx_desc for mgnt frame\n");
+		if((frame_tag&0x0f) == MGNT_FRAMETAG){	
+			bDumpTxDesc = _TRUE;		
+		}
+	}	
+	else if(bDumpTxPkt ==3){//dump early info
+	}
+
+	if(bDumpTxDesc){
+		//	ptxdesc->txdw4 = cpu_to_le32(0x00001006);//RTS Rate=24M
+		//	ptxdesc->txdw6 = 0x6666f800;
+		DBG_8192C("=====================================\n");
+		DBG_8192C("txdw0(0x%08x)\n",ptxdesc->txdw0);
+		DBG_8192C("txdw1(0x%08x)\n",ptxdesc->txdw1);
+		DBG_8192C("txdw2(0x%08x)\n",ptxdesc->txdw2);
+		DBG_8192C("txdw3(0x%08x)\n",ptxdesc->txdw3);
+		DBG_8192C("txdw4(0x%08x)\n",ptxdesc->txdw4);
+		DBG_8192C("txdw5(0x%08x)\n",ptxdesc->txdw5);
+		DBG_8192C("txdw6(0x%08x)\n",ptxdesc->txdw6);
+		DBG_8192C("txdw7(0x%08x)\n",ptxdesc->txdw7);
+		DBG_8192C("=====================================\n");
+	}
+
+}
+
+/*
+ * Description:
+ *	Aggregation packets and send to hardware
+ *
+ * Return:
+ *	0	Success
+ *	-1	Hardware resource(TX FIFO) not ready
+ *	-2	Software resource(xmitbuf) not ready
+ */
+#ifdef CONFIG_TX_EARLY_MODE
+
+//#define DBG_EMINFO
+
+#if RTL8188E_EARLY_MODE_PKT_NUM_10 == 1	
+	#define EARLY_MODE_MAX_PKT_NUM	10
+#else
+	#define EARLY_MODE_MAX_PKT_NUM	5
+#endif
+
+
+struct EMInfo{
+	u8 	EMPktNum;
+	u16  EMPktLen[EARLY_MODE_MAX_PKT_NUM];
+};
+
+
+void
+InsertEMContent_8188E(
+	struct EMInfo *pEMInfo,
+	IN pu1Byte	VirtualAddress)
+{
+
+#if RTL8188E_EARLY_MODE_PKT_NUM_10 == 1
+	u1Byte index=0;
+	u4Byte	dwtmp=0;
+#endif
+
+	_rtw_memset(VirtualAddress, 0, EARLY_MODE_INFO_SIZE);
+	if(pEMInfo->EMPktNum==0)
+		return;
+
+	#ifdef DBG_EMINFO
+	{
+		int i;
+		DBG_8192C("\n%s ==> pEMInfo->EMPktNum =%d\n",__FUNCTION__,pEMInfo->EMPktNum);
+		for(i=0;i< EARLY_MODE_MAX_PKT_NUM;i++){
+			DBG_8192C("%s ==> pEMInfo->EMPktLen[%d] =%d\n",__FUNCTION__,i,pEMInfo->EMPktLen[i]);
+		}
+
+	}
+	#endif
+	
+#if RTL8188E_EARLY_MODE_PKT_NUM_10 == 1
+	SET_EARLYMODE_PKTNUM(VirtualAddress, pEMInfo->EMPktNum);
+
+	if(pEMInfo->EMPktNum == 1){
+		dwtmp = pEMInfo->EMPktLen[0];
+	}else{
+		dwtmp = pEMInfo->EMPktLen[0];
+		dwtmp += ((dwtmp%4)?(4-dwtmp%4):0)+4;
+		dwtmp += pEMInfo->EMPktLen[1];
+	}
+	SET_EARLYMODE_LEN0(VirtualAddress, dwtmp);
+	if(pEMInfo->EMPktNum <= 3){
+		dwtmp = pEMInfo->EMPktLen[2];
+	}else{
+		dwtmp = pEMInfo->EMPktLen[2];
+		dwtmp += ((dwtmp%4)?(4-dwtmp%4):0)+4;
+		dwtmp += pEMInfo->EMPktLen[3];
+	}
+	SET_EARLYMODE_LEN1(VirtualAddress, dwtmp);
+	if(pEMInfo->EMPktNum <= 5){
+		dwtmp = pEMInfo->EMPktLen[4];
+	}else{
+		dwtmp = pEMInfo->EMPktLen[4];
+		dwtmp += ((dwtmp%4)?(4-dwtmp%4):0)+4;
+		dwtmp += pEMInfo->EMPktLen[5];
+	}
+	SET_EARLYMODE_LEN2_1(VirtualAddress, dwtmp&0xF);
+	SET_EARLYMODE_LEN2_2(VirtualAddress, dwtmp>>4);
+	if(pEMInfo->EMPktNum <= 7){
+		dwtmp = pEMInfo->EMPktLen[6];
+	}else{
+		dwtmp = pEMInfo->EMPktLen[6];
+		dwtmp += ((dwtmp%4)?(4-dwtmp%4):0)+4;
+		dwtmp += pEMInfo->EMPktLen[7];
+	}
+	SET_EARLYMODE_LEN3(VirtualAddress, dwtmp);
+	if(pEMInfo->EMPktNum <= 9){
+		dwtmp = pEMInfo->EMPktLen[8];
+	}else{
+		dwtmp = pEMInfo->EMPktLen[8];
+		dwtmp += ((dwtmp%4)?(4-dwtmp%4):0)+4;
+		dwtmp += pEMInfo->EMPktLen[9];
+	}
+	SET_EARLYMODE_LEN4(VirtualAddress, dwtmp);
+#else	
+	SET_EARLYMODE_PKTNUM(VirtualAddress, pEMInfo->EMPktNum);
+	SET_EARLYMODE_LEN0(VirtualAddress, pEMInfo->EMPktLen[0]);
+	SET_EARLYMODE_LEN1(VirtualAddress, pEMInfo->EMPktLen[1]);
+	SET_EARLYMODE_LEN2_1(VirtualAddress, pEMInfo->EMPktLen[2]&0xF);
+	SET_EARLYMODE_LEN2_2(VirtualAddress, pEMInfo->EMPktLen[2]>>4);
+	SET_EARLYMODE_LEN3(VirtualAddress, pEMInfo->EMPktLen[3]);
+	SET_EARLYMODE_LEN4(VirtualAddress, pEMInfo->EMPktLen[4]);
+#endif	
+	//RT_PRINT_DATA(COMP_SEND, DBG_LOUD, "EMHdr:", VirtualAddress, 8);
+
+}
+
+
+
+void UpdateEarlyModeInfo8188E(struct xmit_priv *pxmitpriv,struct xmit_buf *pxmitbuf )
+{
+	//_adapter *padapter, struct xmit_frame *pxmitframe,struct tx_servq	*ptxservq
+	int index,j;
+	u16 offset,pktlen;
+	PTXDESC ptxdesc;
+	
+	u8 *pmem,*pEMInfo_mem;
+	s8 node_num_0=0,node_num_1=0;
+	struct EMInfo eminfo;
+	struct agg_pkt_info *paggpkt;
+	struct xmit_frame *pframe = (struct xmit_frame*)pxmitbuf->priv_data;	
+	pmem= pframe->buf_addr;	
+	
+	#ifdef DBG_EMINFO			
+	DBG_8192C("\n%s ==> agg_num:%d\n",__FUNCTION__, pframe->agg_num);
+	for(index=0;index<pframe->agg_num;index++){
+		offset = 	pxmitpriv->agg_pkt[index].offset;
+		pktlen = pxmitpriv->agg_pkt[index].pkt_len;
+		DBG_8192C("%s ==> agg_pkt[%d].offset=%d\n",__FUNCTION__,index,offset);
+		DBG_8192C("%s ==> agg_pkt[%d].pkt_len=%d\n",__FUNCTION__,index,pktlen);
+	}
+	#endif
+	
+	if( pframe->agg_num > EARLY_MODE_MAX_PKT_NUM)
+	{	
+		node_num_0 = pframe->agg_num;
+		node_num_1= EARLY_MODE_MAX_PKT_NUM-1;
+	}
+	
+	for(index=0;index<pframe->agg_num;index++){
+
+		offset = pxmitpriv->agg_pkt[index].offset;
+		pktlen = pxmitpriv->agg_pkt[index].pkt_len;		
+
+		_rtw_memset(&eminfo,0,sizeof(struct EMInfo));
+		if( pframe->agg_num > EARLY_MODE_MAX_PKT_NUM){
+			if(node_num_0 > EARLY_MODE_MAX_PKT_NUM){
+				eminfo.EMPktNum = EARLY_MODE_MAX_PKT_NUM;
+				node_num_0--;
+			}
+			else{
+				eminfo.EMPktNum = node_num_1;
+				node_num_1--;				
+			}			
+		}
+		else{
+			eminfo.EMPktNum = pframe->agg_num-(index+1);	
+		}				
+		for(j=0;j< eminfo.EMPktNum ;j++){
+			eminfo.EMPktLen[j] = pxmitpriv->agg_pkt[index+1+j].pkt_len+4;// 4 bytes CRC
+		}
+			
+		if(pmem){
+			if(index==0){
+				ptxdesc = (PTXDESC)(pmem);
+				pEMInfo_mem = ((u8 *)ptxdesc)+TXDESC_SIZE;				
+			}
+			else{
+				pmem = pmem + pxmitpriv->agg_pkt[index-1].offset;
+				ptxdesc = (PTXDESC)(pmem);
+				pEMInfo_mem = ((u8 *)ptxdesc)+TXDESC_SIZE;					
+			}
+			
+			#ifdef DBG_EMINFO
+			DBG_8192C("%s ==> desc.pkt_len=%d\n",__FUNCTION__,ptxdesc->pktlen);
+			#endif
+			InsertEMContent_8188E(&eminfo,pEMInfo_mem);
+		}	
+		
+		
+	} 
+	_rtw_memset(pxmitpriv->agg_pkt,0,sizeof(struct agg_pkt_info)*MAX_AGG_PKT_NUM);
+
+}
+#endif
+
+
diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/sdio/rtl8189es_led.c b/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/sdio/rtl8189es_led.c
new file mode 100755
index 00000000..06c90c55
--- /dev/null
+++ b/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/sdio/rtl8189es_led.c
@@ -0,0 +1,124 @@
+/******************************************************************************

+ *

+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.

+ *

+ * This program is free software; you can redistribute it and/or modify it

+ * under the terms of version 2 of the GNU General Public License as

+ * published by the Free Software Foundation.

+ *

+ * This program is distributed in the hope that it will be useful, but WITHOUT

+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for

+ * more details.

+ *

+ * You should have received a copy of the GNU General Public License along with

+ * this program; if not, write to the Free Software Foundation, Inc.,

+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA

+ *

+ *

+ ******************************************************************************/

+#define _RTL8189ES_LED_C_

+

+#include "drv_types.h"

+#include "rtl8188e_hal.h"

+

+//================================================================================

+// LED object.

+//================================================================================

+

+

+//================================================================================

+//	Prototype of protected function.

+//================================================================================

+

+//================================================================================

+// LED_819xUsb routines.

+//================================================================================

+

+//

+//	Description:

+//		Turn on LED according to LedPin specified.

+//

+void

+SwLedOn(

+	_adapter			*padapter,

+	PLED_871x		pLed

+)

+{

+	u8	LedCfg;

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);

+

+	if( (padapter->bSurpriseRemoved == _TRUE) || ( padapter->bDriverStopped == _TRUE))

+	{

+		return;

+	}

+

+	pLed->bLedOn = _TRUE;

+}

+

+

+//

+//	Description:

+//		Turn off LED according to LedPin specified.

+//

+void

+SwLedOff(

+	_adapter			*padapter,

+	PLED_871x		pLed

+)

+{

+	u8	LedCfg;

+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);

+

+	if((padapter->bSurpriseRemoved == _TRUE) || ( padapter->bDriverStopped == _TRUE))

+	{

+		goto exit;

+	}

+

+exit:

+	pLed->bLedOn = _FALSE;

+

+}

+

+//================================================================================

+// Default LED behavior.

+//================================================================================

+

+//

+//	Description:

+//		Initialize all LED_871x objects.

+//

+void

+rtl8188es_InitSwLeds(

+	_adapter	*padapter

+	)

+{

+	struct led_priv *pledpriv = &(padapter->ledpriv);

+

+#if 0

+	pledpriv->LedControlHandler = LedControl871x;

+

+	InitLed871x(padapter, &(pledpriv->SwLed0), LED_PIN_LED0);

+

+	InitLed871x(padapter,&(pledpriv->SwLed1), LED_PIN_LED1);

+#endif

+}

+

+

+//

+//	Description:

+//		DeInitialize all LED_819xUsb objects.

+//

+void

+rtl8188es_DeInitSwLeds(

+	_adapter	*padapter

+	)

+{

+#if 0

+	struct led_priv	*ledpriv = &(padapter->ledpriv);

+

+	DeInitLed871x( &(ledpriv->SwLed0) );

+	DeInitLed871x( &(ledpriv->SwLed1) );

+#endif

+}

+

diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/sdio/rtl8189es_recv.c b/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/sdio/rtl8189es_recv.c
new file mode 100755
index 00000000..06807f97
--- /dev/null
+++ b/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/sdio/rtl8189es_recv.c
@@ -0,0 +1,852 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#define _RTL8189ES_RECV_C_
+
+#include <drv_conf.h>
+
+#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS)
+#error "Shall be Linux or Windows, but not both!\n"
+#endif
+
+#include <drv_types.h>
+#include <recv_osdep.h>
+#include <rtl8188e_hal.h>
+
+static void rtl8188es_recv_tasklet(void *priv);
+
+static s32 initrecvbuf(struct recv_buf *precvbuf, PADAPTER padapter)
+{
+	_rtw_init_listhead(&precvbuf->list);
+	_rtw_spinlock_init(&precvbuf->recvbuf_lock);
+
+	precvbuf->adapter = padapter;
+
+	return _SUCCESS;
+}
+
+static void freerecvbuf(struct recv_buf *precvbuf)
+{
+	_rtw_spinlock_free(&precvbuf->recvbuf_lock);
+}
+
+/*
+ * Initialize recv private variable for hardware dependent
+ * 1. recv buf
+ * 2. recv tasklet
+ *
+ */
+s32 rtl8188es_init_recv_priv(PADAPTER padapter)
+{
+	s32			res;
+	u32			i, n;
+	struct recv_priv	*precvpriv;
+	struct recv_buf		*precvbuf;
+
+
+	res = _SUCCESS;
+	precvpriv = &padapter->recvpriv;
+
+	//3 1. init recv buffer
+	_rtw_init_queue(&precvpriv->free_recv_buf_queue);
+	_rtw_init_queue(&precvpriv->recv_buf_pending_queue);
+
+	n = NR_RECVBUFF * sizeof(struct recv_buf) + 4;
+	precvpriv->pallocated_recv_buf = rtw_zmalloc(n);
+	if (precvpriv->pallocated_recv_buf == NULL) {
+		res = _FAIL;
+		RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("alloc recv_buf fail!\n"));
+		goto exit;
+	}
+
+	precvpriv->precv_buf = (u8*)N_BYTE_ALIGMENT((SIZE_PTR)(precvpriv->pallocated_recv_buf), 4);
+
+	// init each recv buffer
+	precvbuf = (struct recv_buf*)precvpriv->precv_buf;
+	for (i = 0; i < NR_RECVBUFF; i++)
+	{
+		res = initrecvbuf(precvbuf, padapter);
+		if (res == _FAIL)
+			break;
+
+		res = rtw_os_recvbuf_resource_alloc(padapter, precvbuf);
+		if (res == _FAIL) {
+			freerecvbuf(precvbuf);
+			break;
+		}
+
+#ifdef CONFIG_SDIO_RX_COPY
+		if (precvbuf->pskb == NULL) {
+			SIZE_PTR tmpaddr=0;
+			SIZE_PTR alignment=0;
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) // http://www.mail-archive.com/netdev@vger.kernel.org/msg17214.html
+			precvbuf->pskb = __dev_alloc_skb(MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ, GFP_KERNEL);
+#else
+			precvbuf->pskb = __netdev_alloc_skb(padapter->pnetdev, MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ, GFP_KERNEL);
+#endif
+
+			if(precvbuf->pskb)
+			{
+				precvbuf->pskb->dev = padapter->pnetdev;
+
+				tmpaddr = (SIZE_PTR)precvbuf->pskb->data;
+				alignment = tmpaddr & (RECVBUFF_ALIGN_SZ-1);
+				skb_reserve(precvbuf->pskb, (RECVBUFF_ALIGN_SZ - alignment));
+
+				precvbuf->phead = precvbuf->pskb->head;
+				precvbuf->pdata = precvbuf->pskb->data;
+				precvbuf->ptail = skb_tail_pointer(precvbuf->pskb);
+				precvbuf->pend = skb_end_pointer(precvbuf->pskb);
+				precvbuf->len = 0;
+			}
+
+			if (precvbuf->pskb == NULL) {
+				DBG_871X("%s: alloc_skb fail!\n", __FUNCTION__);
+			}
+		}
+#endif
+
+		rtw_list_insert_tail(&precvbuf->list, &precvpriv->free_recv_buf_queue.queue);
+
+		precvbuf++;
+	}
+	precvpriv->free_recv_buf_queue_cnt = i;
+
+	if (res == _FAIL)
+		goto initbuferror;
+
+	//3 2. init tasklet
+#ifdef PLATFORM_LINUX
+	tasklet_init(&precvpriv->recv_tasklet,
+	     (void(*)(unsigned long))rtl8188es_recv_tasklet,
+	     (unsigned long)padapter);
+#endif
+
+	goto exit;
+
+initbuferror:
+	precvbuf = (struct recv_buf*)precvpriv->precv_buf;
+	if (precvbuf) {
+		n = precvpriv->free_recv_buf_queue_cnt;
+		precvpriv->free_recv_buf_queue_cnt = 0;
+		for (i = 0; i < n ; i++)
+		{
+			rtw_list_delete(&precvbuf->list);
+			rtw_os_recvbuf_resource_free(padapter, precvbuf);
+			freerecvbuf(precvbuf);
+			precvbuf++;
+		}
+		precvpriv->precv_buf = NULL;
+	}
+
+	if (precvpriv->pallocated_recv_buf) {
+		n = NR_RECVBUFF * sizeof(struct recv_buf) + 4;
+		rtw_mfree(precvpriv->pallocated_recv_buf, n);
+		precvpriv->pallocated_recv_buf = NULL;
+	}
+
+exit:
+	return res;
+}
+
+/*
+ * Free recv private variable of hardware dependent
+ * 1. recv buf
+ * 2. recv tasklet
+ *
+ */
+void rtl8188es_free_recv_priv(PADAPTER padapter)
+{
+	u32			i, n;
+	struct recv_priv	*precvpriv;
+	struct recv_buf		*precvbuf;
+
+
+	precvpriv = &padapter->recvpriv;
+
+	//3 1. kill tasklet
+#ifdef PLATFORM_LINUX
+	tasklet_kill(&precvpriv->recv_tasklet);
+#endif
+
+	//3 2. free all recv buffers
+	precvbuf = (struct recv_buf*)precvpriv->precv_buf;
+	if (precvbuf) {
+		n = NR_RECVBUFF;
+		precvpriv->free_recv_buf_queue_cnt = 0;
+		for (i = 0; i < n ; i++)
+		{
+			rtw_list_delete(&precvbuf->list);
+			rtw_os_recvbuf_resource_free(padapter, precvbuf);
+			freerecvbuf(precvbuf);
+			precvbuf++;
+		}
+		precvpriv->precv_buf = NULL;
+	}
+
+	if (precvpriv->pallocated_recv_buf) {
+		n = NR_RECVBUFF * sizeof(struct recv_buf) + 4;
+		rtw_mfree(precvpriv->pallocated_recv_buf, n);
+		precvpriv->pallocated_recv_buf = NULL;
+	}
+}
+
+#ifdef CONFIG_SDIO_RX_COPY
+static s32 pre_recv_entry(union recv_frame *precvframe, struct recv_buf	*precvbuf, struct phy_stat *pphy_status)
+{	
+	s32 ret=_SUCCESS;
+#ifdef CONFIG_CONCURRENT_MODE	
+	u8 *primary_myid, *secondary_myid, *paddr1;
+	union recv_frame	*precvframe_if2 = NULL;
+	_adapter *primary_padapter = precvframe->u.hdr.adapter;
+	_adapter *secondary_padapter = primary_padapter->pbuddy_adapter;
+	struct recv_priv *precvpriv = &primary_padapter->recvpriv;
+	_queue *pfree_recv_queue = &precvpriv->free_recv_queue;
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(primary_padapter);
+
+	if(!secondary_padapter)
+		return ret;
+
+	paddr1 = GetAddr1Ptr(precvframe->u.hdr.rx_data);
+
+	if(IS_MCAST(paddr1) == _FALSE)//unicast packets
+	{
+		//primary_myid = myid(&primary_padapter->eeprompriv);
+		secondary_myid = myid(&secondary_padapter->eeprompriv);
+
+		if(_rtw_memcmp(paddr1, secondary_myid, ETH_ALEN))
+		{			
+			//change to secondary interface
+			precvframe->u.hdr.adapter = secondary_padapter;
+		}	
+
+		//ret = recv_entry(precvframe);
+
+	}
+	else // Handle BC/MC Packets	
+	{
+		//clone/copy to if2
+		_pkt	 *pkt_copy = NULL;
+		struct rx_pkt_attrib *pattrib = NULL;
+		
+		precvframe_if2 = rtw_alloc_recvframe(pfree_recv_queue);
+
+		if(!precvframe_if2)
+			return _FAIL;
+		
+		precvframe_if2->u.hdr.adapter = secondary_padapter;
+		_rtw_memcpy(&precvframe_if2->u.hdr.attrib, &precvframe->u.hdr.attrib, sizeof(struct rx_pkt_attrib));
+		pattrib = &precvframe_if2->u.hdr.attrib;
+
+		//driver need to set skb len for skb_copy().
+		//If skb->len is zero, skb_copy() will not copy data from original skb.
+		skb_put(precvframe->u.hdr.pkt, pattrib->pkt_len);
+
+		pkt_copy = skb_copy( precvframe->u.hdr.pkt, GFP_ATOMIC);
+		if (pkt_copy == NULL)
+		{
+			if((pattrib->mfrag == 1)&&(pattrib->frag_num == 0))
+			{				
+				DBG_8192C("pre_recv_entry(): skb_copy fail , drop frag frame \n");
+				rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
+				return ret;
+			}
+
+			pkt_copy = skb_clone( precvframe->u.hdr.pkt, GFP_ATOMIC);
+			if(pkt_copy == NULL)
+			{
+				DBG_8192C("pre_recv_entry(): skb_clone fail , drop frame\n");
+				rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
+				return ret;
+			}
+		}
+		
+		pkt_copy->dev = secondary_padapter->pnetdev;
+
+		precvframe_if2->u.hdr.pkt = pkt_copy;
+		precvframe_if2->u.hdr.rx_head = pkt_copy->head;
+		precvframe_if2->u.hdr.rx_data = pkt_copy->data;
+		precvframe_if2->u.hdr.rx_tail = skb_tail_pointer(pkt_copy);
+		precvframe_if2->u.hdr.rx_end = skb_end_pointer(pkt_copy);
+		precvframe_if2->u.hdr.len = pkt_copy->len;
+
+		//recvframe_put(precvframe_if2, pattrib->pkt_len);
+
+		if ( pHalData->ReceiveConfig & RCR_APPFCS)
+			recvframe_pull_tail(precvframe_if2, IEEE80211_FCS_LEN);
+
+		if (pattrib->physt) 
+			update_recvframe_phyinfo_88e(precvframe_if2, pphy_status);
+
+		if(rtw_recv_entry(precvframe_if2) != _SUCCESS)
+		{
+			RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,
+				("recvbuf2recvframe: rtw_recv_entry(precvframe) != _SUCCESS\n"));
+		}
+	}
+	
+	if (precvframe->u.hdr.attrib.physt)
+		update_recvframe_phyinfo_88e(precvframe, pphy_status);
+	ret = rtw_recv_entry(precvframe);
+
+#endif
+
+	return ret;
+
+}
+
+static void rtl8188es_recv_tasklet(void *priv)
+{
+	PADAPTER			padapter;
+	PHAL_DATA_TYPE		pHalData;
+	struct recv_priv		*precvpriv;
+	struct recv_buf		*precvbuf;
+	union recv_frame		*precvframe;
+	struct recv_frame_hdr	*phdr;
+	struct rx_pkt_attrib	*pattrib;
+	_irqL	irql;
+	u8		*ptr;
+	u32		pkt_offset, skb_len, alloc_sz;
+	s32		transfer_len;
+	_pkt		*pkt_copy = NULL;
+	struct phy_stat	*pphy_status = NULL;
+	u8		shift_sz = 0, rx_report_sz = 0;
+
+
+	padapter = (PADAPTER)priv;
+	pHalData = GET_HAL_DATA(padapter);
+	precvpriv = &padapter->recvpriv;
+	
+	do {
+		if ((padapter->bDriverStopped == _TRUE)||(padapter->bSurpriseRemoved== _TRUE))
+		{
+			DBG_8192C("recv_tasklet => bDriverStopped or bSurpriseRemoved \n");
+			break;
+		}
+		
+		precvbuf = rtw_dequeue_recvbuf(&precvpriv->recv_buf_pending_queue);
+		if (NULL == precvbuf) break;
+
+		transfer_len = (s32)precvbuf->len;
+		ptr = precvbuf->pdata;
+
+		do {
+			precvframe = rtw_alloc_recvframe(&precvpriv->free_recv_queue);
+			if (precvframe == NULL) {
+				RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("%s: no enough recv frame!\n",__FUNCTION__));
+				rtw_enqueue_recvbuf_to_head(precvbuf, &precvpriv->recv_buf_pending_queue);
+
+				// The case of can't allocte recvframe should be temporary,
+				// schedule again and hope recvframe is available next time.
+#ifdef PLATFORM_LINUX
+				tasklet_schedule(&precvpriv->recv_tasklet);
+#endif
+				return;
+			}
+
+			//rx desc parsing
+			update_recvframe_attrib_88e(precvframe, (struct recv_stat*)ptr);
+
+			pattrib = &precvframe->u.hdr.attrib;
+
+			// fix Hardware RX data error, drop whole recv_buffer
+			if ((!(pHalData->ReceiveConfig & RCR_ACRC32)) && pattrib->crc_err)
+			{
+				#if !(MP_DRIVER==1)
+				DBG_8192C("%s()-%d: RX Warning! rx CRC ERROR !!\n", __FUNCTION__, __LINE__);
+				#endif
+				rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
+				break;
+			}
+
+			if (pHalData->ReceiveConfig & RCR_APP_BA_SSN)
+				rx_report_sz = RXDESC_SIZE + 4 + pattrib->drvinfo_sz;
+			else
+				rx_report_sz = RXDESC_SIZE + pattrib->drvinfo_sz;
+
+			pkt_offset = rx_report_sz + pattrib->shift_sz + pattrib->pkt_len;
+
+			if ((pattrib->pkt_len==0) || (pkt_offset>transfer_len)) {
+				DBG_8192C("%s()-%d: RX Warning!,pkt_len==0 or pkt_offset(%d)> transfoer_len(%d) \n", __FUNCTION__, __LINE__, pkt_offset, transfer_len);
+				rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
+				break;
+			}
+
+			if ((pattrib->crc_err) || (pattrib->icv_err))
+			{
+				DBG_8192C("%s: crc_err=%d icv_err=%d, skip!\n", __FUNCTION__, pattrib->crc_err, pattrib->icv_err);
+				rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
+			}
+			else
+			{
+				//	Modified by Albert 20101213
+				//	For 8 bytes IP header alignment.
+				if (pattrib->qos)	//	Qos data, wireless lan header length is 26
+				{
+					shift_sz = 6;
+				}
+				else
+				{
+					shift_sz = 0;
+				}
+
+				skb_len = pattrib->pkt_len;
+
+				// for first fragment packet, driver need allocate 1536+drvinfo_sz+RXDESC_SIZE to defrag packet.
+				// modify alloc_sz for recvive crc error packet by thomas 2011-06-02
+				if((pattrib->mfrag == 1)&&(pattrib->frag_num == 0)){
+					//alloc_sz = 1664;	//1664 is 128 alignment.
+					if(skb_len <= 1650)
+						alloc_sz = 1664;
+					else
+						alloc_sz = skb_len + 14;
+				}
+				else {
+					alloc_sz = skb_len;
+					//	6 is for IP header 8 bytes alignment in QoS packet case.
+					//	8 is for skb->data 4 bytes alignment.
+					alloc_sz += 14;
+				}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) // http://www.mail-archive.com/netdev@vger.kernel.org/msg17214.html
+				pkt_copy = dev_alloc_skb(alloc_sz);
+#else			
+				pkt_copy = netdev_alloc_skb(padapter->pnetdev, alloc_sz);
+#endif		
+				if(pkt_copy)
+				{
+					pkt_copy->dev = padapter->pnetdev;
+					precvframe->u.hdr.pkt = pkt_copy;
+					skb_reserve( pkt_copy, 8 - ((SIZE_PTR)( pkt_copy->data ) & 7 ));//force pkt_copy->data at 8-byte alignment address
+					skb_reserve( pkt_copy, shift_sz );//force ip_hdr at 8-byte alignment address according to shift_sz.
+					_rtw_memcpy(pkt_copy->data, (ptr + rx_report_sz + pattrib->shift_sz), skb_len);
+					precvframe->u.hdr.rx_head = pkt_copy->head;
+					precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail = pkt_copy->data;
+					precvframe->u.hdr.rx_end = skb_end_pointer(pkt_copy);
+				}
+				else
+				{
+					if((pattrib->mfrag == 1)&&(pattrib->frag_num == 0))
+					{				
+						DBG_8192C("rtl8188es_recv_tasklet: alloc_skb fail , drop frag frame \n");
+						rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
+						break;
+					}
+					
+					precvframe->u.hdr.pkt = skb_clone(precvbuf->pskb, GFP_ATOMIC);
+					if(precvframe->u.hdr.pkt)
+					{
+						_pkt	*pkt_clone = precvframe->u.hdr.pkt;
+
+						pkt_clone->data = ptr + rx_report_sz + pattrib->shift_sz;
+						skb_reset_tail_pointer(pkt_clone);
+						precvframe->u.hdr.rx_head = precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail 
+							= pkt_clone->data;
+						precvframe->u.hdr.rx_end =  pkt_clone->data + skb_len;
+					}
+					else
+					{
+						DBG_8192C("rtl8188es_recv_tasklet: skb_clone fail\n");
+						rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
+						break;
+					}
+				}
+
+				recvframe_put(precvframe, skb_len);
+				//recvframe_pull(precvframe, drvinfo_sz + RXDESC_SIZE);
+
+				if (pHalData->ReceiveConfig & RCR_APPFCS)
+					recvframe_pull_tail(precvframe, IEEE80211_FCS_LEN);
+
+				// update drv info
+				if (pHalData->ReceiveConfig & RCR_APP_BA_SSN) {
+					//rtl8723s_update_bassn(padapter, (ptr + RXDESC_SIZE));
+				}
+
+				if(pattrib->pkt_rpt_type == NORMAL_RX)//Normal rx packet
+				{
+					pphy_status = (struct phy_stat *)(ptr + (rx_report_sz - pattrib->drvinfo_sz));
+				
+#ifdef CONFIG_CONCURRENT_MODE
+					if(rtw_buddy_adapter_up(padapter))
+					{
+						if(pre_recv_entry(precvframe, precvbuf, (struct phy_stat*)pphy_status) != _SUCCESS)
+						{
+							RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,
+								("recvbuf2recvframe: recv_entry(precvframe) != _SUCCESS\n"));
+						}
+					}
+					else
+#endif
+					{
+						if (pattrib->physt)
+							update_recvframe_phyinfo_88e(precvframe, (struct phy_stat*)pphy_status);
+
+						if (rtw_recv_entry(precvframe) != _SUCCESS)
+						{
+							RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("%s: rtw_recv_entry(precvframe) != _SUCCESS\n",__FUNCTION__));
+						}
+					}
+				}
+				else{ // pkt_rpt_type == TX_REPORT1-CCX, TX_REPORT2-TX RTP,HIS_REPORT-USB HISR RTP
+
+					//enqueue recvframe to txrtp queue
+					if(pattrib->pkt_rpt_type == TX_REPORT1){
+						//DBG_8192C("rx CCX \n");
+						//CCX-TXRPT ack for xmit mgmt frames.
+						handle_txrpt_ccx_88e(padapter, precvframe->u.hdr.rx_data);
+					}
+					else if(pattrib->pkt_rpt_type == TX_REPORT2){
+						//printk("rx TX RPT \n");
+						ODM_RA_TxRPT2Handle_8188E(
+									&pHalData->odmpriv,
+									precvframe->u.hdr.rx_data,
+									pattrib->pkt_len,
+									pattrib->MacIDValidEntry[0],
+									pattrib->MacIDValidEntry[1]
+									);
+
+					}
+					/*
+					else if(pattrib->pkt_rpt_type == HIS_REPORT){
+						printk("rx USB HISR \n");						
+					}*/
+
+					rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);					
+
+				}
+			}
+
+			// Page size of receive package is 128 bytes alignment =>DMA AGG
+			// refer to _InitTransferPageSize()
+			pkt_offset = _RND128(pkt_offset);
+			transfer_len -= pkt_offset;
+			ptr += pkt_offset;	
+			precvframe = NULL;
+			pkt_copy = NULL;
+		}while(transfer_len>0);
+
+		precvbuf->len = 0;
+
+		rtw_enqueue_recvbuf(precvbuf, &precvpriv->free_recv_buf_queue);
+	} while (1);
+
+}
+#else
+static s32 pre_recv_entry(union recv_frame *precvframe, struct recv_buf	*precvbuf, struct phy_stat *pphy_status)
+{	
+	s32 ret=_SUCCESS;
+#ifdef CONFIG_CONCURRENT_MODE	
+	u8 *primary_myid, *secondary_myid, *paddr1;
+	union recv_frame	*precvframe_if2 = NULL;
+	_adapter *primary_padapter = precvframe->u.hdr.adapter;
+	_adapter *secondary_padapter = primary_padapter->pbuddy_adapter;
+	struct recv_priv *precvpriv = &primary_padapter->recvpriv;
+	_queue *pfree_recv_queue = &precvpriv->free_recv_queue;
+	u8	*pbuf = precvframe->u.hdr.rx_head;
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(primary_padapter);
+
+	if(!secondary_padapter)
+		return ret;
+
+	paddr1 = GetAddr1Ptr(precvframe->u.hdr.rx_data);
+
+	if(IS_MCAST(paddr1) == _FALSE)//unicast packets
+	{
+		//primary_myid = myid(&primary_padapter->eeprompriv);
+		secondary_myid = myid(&secondary_padapter->eeprompriv);
+
+		if(_rtw_memcmp(paddr1, secondary_myid, ETH_ALEN))
+		{			
+			//change to secondary interface
+			precvframe->u.hdr.adapter = secondary_padapter;
+		}	
+
+		//ret = recv_entry(precvframe);
+
+	}
+	else // Handle BC/MC Packets	
+	{
+		//clone/copy to if2
+		u8 shift_sz = 0;
+		u32 alloc_sz, skb_len;		
+		_pkt	 *pkt_copy = NULL;
+		struct rx_pkt_attrib *pattrib = NULL;
+		
+		precvframe_if2 = rtw_alloc_recvframe(pfree_recv_queue);
+
+		if(!precvframe_if2)
+			return _FAIL;
+		
+		precvframe_if2->u.hdr.adapter = secondary_padapter;
+		_rtw_init_listhead(&precvframe_if2->u.hdr.list);	
+		precvframe_if2->u.hdr.precvbuf = NULL;	//can't access the precvbuf for new arch.
+		precvframe_if2->u.hdr.len=0;
+		_rtw_memcpy(&precvframe_if2->u.hdr.attrib, &precvframe->u.hdr.attrib, sizeof(struct rx_pkt_attrib));
+		pattrib = &precvframe_if2->u.hdr.attrib;
+
+		pkt_copy = skb_copy( precvframe->u.hdr.pkt, GFP_ATOMIC);
+		if (pkt_copy == NULL)
+		{
+			RT_TRACE(_module_rtl871x_recv_c_, _drv_crit_, ("%s: no enough memory to allocate SKB!\n",__FUNCTION__));
+			rtw_free_recvframe(precvframe_if2, &precvpriv->free_recv_queue);
+			rtw_enqueue_recvbuf_to_head(precvbuf, &precvpriv->recv_buf_pending_queue);
+
+			// The case of can't allocte skb is serious and may never be recovered,
+			// once bDriverStopped is enable, this task should be stopped.
+			if (secondary_padapter->bDriverStopped == _FALSE)
+#ifdef PLATFORM_LINUX
+				tasklet_schedule(&precvpriv->recv_tasklet);
+#endif
+			return ret;
+		}
+		pkt_copy->dev = secondary_padapter->pnetdev;
+
+
+
+		if((pattrib->mfrag == 1)&&(pattrib->frag_num == 0)){
+			//alloc_sz = 1664;	//1664 is 128 alignment.
+			if(skb_len <= 1650)
+				alloc_sz = 1664;
+			else
+				alloc_sz = skb_len + 14;
+		}
+		else {
+			alloc_sz = skb_len;
+			//	6 is for IP header 8 bytes alignment in QoS packet case.
+			//	8 is for skb->data 4 bytes alignment.
+			alloc_sz += 14;
+		}
+
+#if 1
+		precvframe_if2->u.hdr.pkt = pkt_copy;
+		precvframe_if2->u.hdr.rx_head = pkt_copy->head;
+		precvframe_if2->u.hdr.rx_data = precvframe_if2->u.hdr.rx_tail = pkt_copy->data; 
+		precvframe_if2->u.hdr.rx_end = pkt_copy->data + alloc_sz;
+#endif
+		recvframe_put(precvframe_if2, pkt_offset);
+		recvframe_pull(precvframe_if2, RXDESC_SIZE + pattrib->drvinfo_sz);
+
+		if ( pHalData->ReceiveConfig & RCR_APPFCS)
+			recvframe_pull_tail(precvframe_if2, IEEE80211_FCS_LEN);
+
+		if (pattrib->physt) 
+			update_recvframe_phyinfo_88e(precvframe_if2, pphy_status);
+
+		if(rtw_recv_entry(precvframe_if2) != _SUCCESS)
+		{
+			RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,
+				("recvbuf2recvframe: rtw_recv_entry(precvframe) != _SUCCESS\n"));
+		}
+	}
+	
+	if (precvframe->u.hdr.attrib.physt)
+		update_recvframe_phyinfo_88e(precvframe, (struct phy_stat*)pphy_status);	
+	ret = rtw_recv_entry(precvframe);
+
+#endif
+
+	return ret;
+
+}
+
+static void rtl8188es_recv_tasklet(void *priv)
+{
+	PADAPTER				padapter;
+	PHAL_DATA_TYPE			pHalData;
+	struct recv_priv		*precvpriv;
+	struct recv_buf			*precvbuf;
+	union recv_frame		*precvframe;
+	struct recv_frame_hdr	*phdr;
+	struct rx_pkt_attrib	*pattrib;
+	u8			*ptr;
+	_pkt		*ppkt;
+	u32			pkt_offset;
+	_irqL		irql;
+#ifdef CONFIG_CONCURRENT_MODE	
+	struct recv_stat	*prxstat;
+#endif
+
+	padapter = (PADAPTER)priv;
+	pHalData = GET_HAL_DATA(padapter);
+	precvpriv = &padapter->recvpriv;
+	
+	do {
+		precvbuf = rtw_dequeue_recvbuf(&precvpriv->recv_buf_pending_queue);
+		if (NULL == precvbuf) break;
+
+		ptr = precvbuf->pdata;
+
+		while (ptr < precvbuf->ptail)
+		{
+			precvframe = rtw_alloc_recvframe(&precvpriv->free_recv_queue);
+			if (precvframe == NULL) {
+				RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("%s: no enough recv frame!\n",__FUNCTION__));
+				rtw_enqueue_recvbuf_to_head(precvbuf, &precvpriv->recv_buf_pending_queue);
+
+				// The case of can't allocte recvframe should be temporary,
+				// schedule again and hope recvframe is available next time.
+#ifdef PLATFORM_LINUX
+				tasklet_schedule(&precvpriv->recv_tasklet);
+#endif
+				return;
+			}
+
+			phdr = &precvframe->u.hdr;
+			pattrib = &phdr->attrib;
+
+			//rx desc parsing
+			update_recvframe_attrib_88e(precvframe, (struct recv_stat*)ptr);
+#ifdef CONFIG_CONCURRENT_MODE
+			prxstat = (struct recv_stat*)ptr;
+#endif
+			// fix Hardware RX data error, drop whole recv_buffer
+			if ((!(pHalData->ReceiveConfig & RCR_ACRC32)) && pattrib->crc_err)
+			{
+				//#if !(MP_DRIVER==1)
+				if (padapter->registrypriv.mp_mode == 0)
+				DBG_8192C("%s()-%d: RX Warning! rx CRC ERROR !!\n", __FUNCTION__, __LINE__);
+				//#endif
+				rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
+				break;
+			}
+
+			pkt_offset = RXDESC_SIZE + pattrib->drvinfo_sz + pattrib->pkt_len;
+
+			if ((ptr + pkt_offset) > precvbuf->ptail) {
+				DBG_8192C("%s()-%d: : next pkt len(%p,%d) exceed ptail(%p)!\n", __FUNCTION__, __LINE__, ptr, pkt_offset, precvbuf->ptail);
+				rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
+				break;
+			}
+
+			if ((pattrib->crc_err) || (pattrib->icv_err))
+			{
+				DBG_8192C("%s: crc_err=%d icv_err=%d, skip!\n", __FUNCTION__, pattrib->crc_err, pattrib->icv_err);
+				rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
+			}
+			else
+			{
+				ppkt = skb_clone(precvbuf->pskb, GFP_ATOMIC);
+				if (ppkt == NULL)
+				{
+					RT_TRACE(_module_rtl871x_recv_c_, _drv_crit_, ("%s: no enough memory to allocate SKB!\n",__FUNCTION__));
+					rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
+					rtw_enqueue_recvbuf_to_head(precvbuf, &precvpriv->recv_buf_pending_queue);
+
+					// The case of can't allocte skb is serious and may never be recovered,
+					// once bDriverStopped is enable, this task should be stopped.
+					if (padapter->bDriverStopped == _FALSE) {
+#ifdef PLATFORM_LINUX
+						tasklet_schedule(&precvpriv->recv_tasklet);
+#endif
+					}
+
+					return;
+				}
+
+				phdr->pkt = ppkt;
+				phdr->len = 0;
+				phdr->rx_head = precvbuf->phead;
+				phdr->rx_data = phdr->rx_tail = precvbuf->pdata;
+				phdr->rx_end = precvbuf->pend;
+
+				recvframe_put(precvframe, pkt_offset);
+				recvframe_pull(precvframe, RXDESC_SIZE + pattrib->drvinfo_sz);
+
+				if (pHalData->ReceiveConfig & RCR_APPFCS)
+					recvframe_pull_tail(precvframe, IEEE80211_FCS_LEN);
+
+				// move to drv info position
+				ptr += RXDESC_SIZE;
+
+				// update drv info
+				if (pHalData->ReceiveConfig & RCR_APP_BA_SSN) {
+//					rtl8723s_update_bassn(padapter, pdrvinfo);
+					ptr += 4;
+				}
+
+				if(pattrib->pkt_rpt_type == NORMAL_RX)//Normal rx packet
+				{
+#ifdef CONFIG_CONCURRENT_MODE
+					if(rtw_buddy_adapter_up(padapter))
+					{
+						if(pre_recv_entry(precvframe, precvbuf, (struct phy_stat*)ptr) != _SUCCESS)
+						{
+							RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,
+								("recvbuf2recvframe: recv_entry(precvframe) != _SUCCESS\n"));
+						}
+					}
+					else
+#endif
+					{
+						if (pattrib->physt) 
+					update_recvframe_phyinfo_88e(precvframe, (struct phy_stat*)ptr);
+
+					if (rtw_recv_entry(precvframe) != _SUCCESS)
+					{
+							RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,
+								("recvbuf2recvframe: rtw_recv_entry(precvframe) != _SUCCESS\n"));
+						}
+					}
+				}
+				else{ // pkt_rpt_type == TX_REPORT1-CCX, TX_REPORT2-TX RTP,HIS_REPORT-USB HISR RTP
+
+					//enqueue recvframe to txrtp queue
+					if(pattrib->pkt_rpt_type == TX_REPORT1){
+						DBG_8192C("rx CCX \n");
+					}
+					else if(pattrib->pkt_rpt_type == TX_REPORT2){
+						//DBG_8192C("rx TX RPT \n");
+						ODM_RA_TxRPT2Handle_8188E(
+									&pHalData->odmpriv,
+									precvframe->u.hdr.rx_data,
+									pattrib->pkt_len,
+									pattrib->MacIDValidEntry[0],
+									pattrib->MacIDValidEntry[1]
+									);
+
+					}
+					/*
+					else if(pattrib->pkt_rpt_type == HIS_REPORT){
+						DBG_8192C("rx USB HISR \n");
+					}*/
+
+					rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);					
+
+				}
+			}
+
+			// Page size of receive package is 128 bytes alignment =>DMA AGG
+			// refer to _InitTransferPageSize()
+			pkt_offset = _RND128(pkt_offset);
+			precvbuf->pdata += pkt_offset;
+			ptr = precvbuf->pdata;
+
+		}
+
+		dev_kfree_skb_any(precvbuf->pskb);
+		precvbuf->pskb = NULL;
+		rtw_enqueue_recvbuf(precvbuf, &precvpriv->free_recv_buf_queue);
+
+	} while (1);
+
+}
+#endif
+
diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/sdio/rtl8189es_xmit.c b/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/sdio/rtl8189es_xmit.c
new file mode 100755
index 00000000..8fe70f10
--- /dev/null
+++ b/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/sdio/rtl8189es_xmit.c
@@ -0,0 +1,1691 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#define _RTL8189ES_XMIT_C_
+
+#include <drv_conf.h>
+#include <osdep_service.h>
+#include <drv_types.h>
+#include <sdio_ops.h>
+#include <rtl8188e_hal.h>
+
+static void fill_txdesc_sectype(struct pkt_attrib *pattrib, PTXDESC ptxdesc)
+{
+	if ((pattrib->encrypt > 0) && !pattrib->bswenc)
+	{
+		switch (pattrib->encrypt)
+		{
+			// SEC_TYPE
+			case _WEP40_:
+			case _WEP104_:
+			case _TKIP_:
+			case _TKIP_WTMIC_:
+				ptxdesc->sectype = 1;
+				break;
+#ifdef CONFIG_WAPI_SUPPORT
+			case _SMS4_:
+				ptxdesc->sectype = 2;
+				break;
+#endif
+			case _AES_:
+				ptxdesc->sectype = 3;
+				break;
+
+			case _NO_PRIVACY_:
+			default:
+					break;
+		}
+	}
+}
+
+ 
+ static void fill_txdesc_vcs(struct pkt_attrib *pattrib, PTXDESC ptxdesc)
+{
+	//DBG_8192C("cvs_mode=%d\n", pattrib->vcs_mode);
+
+	switch (pattrib->vcs_mode)
+	{
+		case RTS_CTS:
+			ptxdesc->rtsen = 1;
+			break;
+
+		case CTS_TO_SELF:
+			ptxdesc->cts2self = 1;
+			break;
+
+		case NONE_VCS:
+		default:
+			break;
+	}
+
+	if(pattrib->vcs_mode) {
+		ptxdesc->hw_rts_en = 1; // ENABLE HW RTS
+
+		// Set RTS BW
+		if(pattrib->ht_en)
+		{
+			if (pattrib->bwmode & HT_CHANNEL_WIDTH_40)
+				ptxdesc->rts_bw = 1;
+
+			switch (pattrib->ch_offset)
+			{
+				case HAL_PRIME_CHNL_OFFSET_DONT_CARE:
+					ptxdesc->rts_sc = 0;
+					break;
+
+				case HAL_PRIME_CHNL_OFFSET_LOWER:
+					ptxdesc->rts_sc = 1;
+					break;
+
+				case HAL_PRIME_CHNL_OFFSET_UPPER:
+					ptxdesc->rts_sc = 2;
+					break;
+
+				default:
+					ptxdesc->rts_sc = 3; // Duplicate
+					break;
+			}
+		}
+	}
+}
+
+static void fill_txdesc_phy(struct pkt_attrib *pattrib, PTXDESC ptxdesc)
+{
+	//DBG_8192C("bwmode=%d, ch_off=%d\n", pattrib->bwmode, pattrib->ch_offset);
+
+	if (pattrib->ht_en)
+	{
+		if (pattrib->bwmode & HT_CHANNEL_WIDTH_40)
+			ptxdesc->data_bw = 1;
+
+		switch (pattrib->ch_offset)
+		{
+			case HAL_PRIME_CHNL_OFFSET_DONT_CARE:
+				ptxdesc->data_sc = 0;
+				break;
+
+			case HAL_PRIME_CHNL_OFFSET_LOWER:
+				ptxdesc->data_sc = 1;
+				break;
+
+			case HAL_PRIME_CHNL_OFFSET_UPPER:
+				ptxdesc->data_sc = 2;
+				break;
+
+			default:
+				ptxdesc->data_sc = 3; // Duplicate
+				break;
+		}
+	}
+}
+
+static void rtl8188e_cal_txdesc_chksum(struct tx_desc *ptxdesc)
+{
+	u16	*usPtr = (u16*)ptxdesc;
+	u32 count = 16;		// (32 bytes / 2 bytes per XOR) => 16 times
+	u32 index;
+	u16 checksum = 0;
+
+
+	// Clear first
+	ptxdesc->txdw7 &= cpu_to_le32(0xffff0000);
+
+	for (index = 0; index < count; index++) {
+		checksum ^= le16_to_cpu(*(usPtr + index));
+	}
+
+	ptxdesc->txdw7 |= cpu_to_le32(checksum & 0x0000ffff);
+}
+//
+// Description: In normal chip, we should send some packet to Hw which will be used by Fw
+//			in FW LPS mode. The function is to fill the Tx descriptor of this packets, then
+//			Fw can tell Hw to send these packet derectly.
+//
+void rtl8188e_fill_fake_txdesc(
+	PADAPTER	padapter,
+	u8*			pDesc,
+	u32			BufferLen,
+	u8			IsPsPoll,
+	u8			IsBTQosNull)
+{
+	struct tx_desc *ptxdesc;
+
+
+	// Clear all status
+	ptxdesc = (struct tx_desc*)pDesc;
+	_rtw_memset(pDesc, 0, TXDESC_SIZE);
+
+	//offset 0
+	ptxdesc->txdw0 |= cpu_to_le32( OWN | FSG | LSG); //own, bFirstSeg, bLastSeg;
+
+	ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE+OFFSET_SZ)<<OFFSET_SHT)&0x00ff0000); //32 bytes for TX Desc
+
+	ptxdesc->txdw0 |= cpu_to_le32(BufferLen&0x0000ffff); // Buffer size + command header
+
+	//offset 4
+	ptxdesc->txdw1 |= cpu_to_le32((QSLT_MGNT<<QSEL_SHT)&0x00001f00); // Fixed queue of Mgnt queue
+
+	//Set NAVUSEHDR to prevent Ps-poll AId filed to be changed to error vlaue by Hw.
+	if (IsPsPoll)
+	{
+		ptxdesc->txdw1 |= cpu_to_le32(NAVUSEHDR);
+	}
+	else
+	{
+		ptxdesc->txdw4 |= cpu_to_le32(BIT(7)); // Hw set sequence number
+		ptxdesc->txdw3 |= cpu_to_le32((8 <<28)); //set bit3 to 1. Suugested by TimChen. 2009.12.29.
+	}
+
+	if (_TRUE == IsBTQosNull)
+	{
+		ptxdesc->txdw2 |= cpu_to_le32(BIT(23)); // BT NULL
+	}
+
+	//offset 16
+	ptxdesc->txdw4 |= cpu_to_le32(BIT(8));//driver uses rate
+
+#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
+	// USB interface drop packet if the checksum of descriptor isn't correct.
+	// Using this checksum can let hardware recovery from packet bulk out error (e.g. Cancel URC, Bulk out error.).
+	rtl8188e_cal_txdesc_chksum(ptxdesc);
+#endif
+}
+
+
+#define SDIO_TX_AGG_MAX	(5)
+//#define CONFIG_FIX_CORE_DUMP ==> have bug
+//#define DBG_EMINFO
+
+#if 0
+void rtl8188e_cal_txdesc_chksum(struct tx_desc *ptxdesc)
+{
+	u16	*usPtr = (u16*)ptxdesc;
+	u32 count = 16;		// (32 bytes / 2 bytes per XOR) => 16 times
+	u32 index;
+	u16 checksum = 0;
+
+
+	// Clear first
+	ptxdesc->txdw7 &= cpu_to_le32(0xffff0000);
+
+	for (index = 0; index < count; index++) {
+		checksum ^= le16_to_cpu(*(usPtr + index));
+	}
+
+	ptxdesc->txdw7 |= cpu_to_le32(checksum & 0x0000ffff);
+}
+
+static void fill_txdesc_sectype(struct pkt_attrib *pattrib, PTXDESC ptxdesc)
+{
+	if ((pattrib->encrypt > 0) && !pattrib->bswenc)
+	{
+		switch (pattrib->encrypt)
+		{
+			// SEC_TYPE
+			case _WEP40_:
+			case _WEP104_:
+			case _TKIP_:
+			case _TKIP_WTMIC_:
+				ptxdesc->sectype = 1;
+				break;
+
+			case _AES_:
+				ptxdesc->sectype = 3;
+				break;
+
+			case _NO_PRIVACY_:
+			default:
+					break;
+		}
+	}
+}
+
+static void fill_txdesc_vcs(struct pkt_attrib *pattrib, PTXDESC ptxdesc)
+{
+	//DBG_8192C("cvs_mode=%d\n", pattrib->vcs_mode);
+
+	switch (pattrib->vcs_mode)
+	{
+		case RTS_CTS:
+			ptxdesc->rtsen = 1;
+			break;
+
+		case CTS_TO_SELF:
+			ptxdesc->cts2self = 1;
+			break;
+
+		case NONE_VCS:
+		default:
+			break;
+	}
+
+	if (pattrib->vcs_mode)
+		ptxdesc->hw_rts_en = 1; // ENABLE HW RTS
+}
+
+static void fill_txdesc_phy(struct pkt_attrib *pattrib, PTXDESC ptxdesc)
+{
+	//DBG_8192C("bwmode=%d, ch_off=%d\n", pattrib->bwmode, pattrib->ch_offset);
+
+	if (pattrib->ht_en)
+	{
+		if (pattrib->bwmode & HT_CHANNEL_WIDTH_40)
+			ptxdesc->data_bw = 1;
+
+		switch (pattrib->ch_offset)
+		{
+			case HAL_PRIME_CHNL_OFFSET_DONT_CARE:
+				ptxdesc->data_sc = 0;
+				break;
+
+			case HAL_PRIME_CHNL_OFFSET_LOWER:
+				ptxdesc->data_sc = 1;
+				break;
+
+			case HAL_PRIME_CHNL_OFFSET_UPPER:
+				ptxdesc->data_sc = 2;
+				break;
+
+			default:
+				ptxdesc->data_sc = 3; // Duplicate
+				break;
+		}
+	}
+}
+#endif
+
+void rtl8188es_fill_default_txdesc(
+	struct xmit_frame *pxmitframe,
+	u8 *pbuf)
+{
+	PADAPTER padapter;
+	HAL_DATA_TYPE *pHalData;
+	struct mlme_ext_priv *pmlmeext;
+	struct mlme_ext_info *pmlmeinfo;
+	struct dm_priv *pdmpriv;
+	struct pkt_attrib *pattrib;
+	PTXDESC ptxdesc;
+	s32 bmcst;
+
+
+	padapter = pxmitframe->padapter;
+	pHalData = GET_HAL_DATA(padapter);
+	//pdmpriv = &pHalData->dmpriv;
+	pmlmeext = &padapter->mlmeextpriv;
+	pmlmeinfo = &(pmlmeext->mlmext_info);
+
+	pattrib = &pxmitframe->attrib;
+	bmcst = IS_MCAST(pattrib->ra);
+
+	ptxdesc = (PTXDESC)pbuf;
+
+#ifdef CONFIG_CONCURRENT_MODE
+	if(rtw_buddy_adapter_up(padapter) && padapter->adapter_type > PRIMARY_ADAPTER)	
+		pHalData = GET_HAL_DATA(padapter->pbuddy_adapter);				
+#endif //CONFIG_CONCURRENT_MODE
+
+	if (pxmitframe->frame_tag == DATA_FRAMETAG)
+	{
+		ptxdesc->macid = pattrib->mac_id; // CAM_ID(MAC_ID)
+
+		if (pattrib->ampdu_en == _TRUE)
+			ptxdesc->agg_en = 1; // AGG EN
+		else
+			ptxdesc->bk = 1; // AGG BK
+
+		ptxdesc->qsel = pattrib->qsel;
+		ptxdesc->rate_id = pattrib->raid;
+
+		fill_txdesc_sectype(pattrib, ptxdesc);
+
+		ptxdesc->seq = pattrib->seqnum;
+
+		//todo: qos_en
+
+		ptxdesc->userate = 1; // driver uses rate	
+
+		if ((pattrib->ether_type != 0x888e) &&
+			(pattrib->ether_type != 0x0806) &&
+			(pattrib->dhcp_pkt != 1))
+		{
+			// Non EAP & ARP & DHCP type data packet
+
+			fill_txdesc_vcs(pattrib, ptxdesc);
+			fill_txdesc_phy(pattrib, ptxdesc);
+
+			ptxdesc->rtsrate = 8; // RTS Rate=24M
+			ptxdesc->data_ratefb_lmt = 0x1F;
+			ptxdesc->rts_ratefb_lmt = 0xF;
+		#if (RATE_ADAPTIVE_SUPPORT == 1)				
+			if(pattrib->ht_en){
+				ptxdesc->sgi = ODM_RA_GetShortGI_8188E(&pHalData->odmpriv,pattrib->mac_id);
+			}
+			ptxdesc->datarate = ODM_RA_GetDecisionRate_8188E(&pHalData->odmpriv,pattrib->mac_id);			
+			
+	               //for debug
+	               #if 0
+	                if(padapter->fix_rate!= 0xFF){
+					ptxdesc->datarate = padapter->fix_rate;
+				}
+	                #endif
+			#if (POWER_TRAINING_ACTIVE==1)
+			ptxdesc->pwr_status = ODM_RA_GetHwPwrStatus_8188E(&pHalData->odmpriv,pattrib->mac_id);
+			#endif		
+		#else			
+			ptxdesc->datarate = 0x13; //MCS7 
+			ptxdesc->sgi = 1; // SGI
+			if(padapter->fix_rate!= 0xFF){//modify datat by iwpriv
+				ptxdesc->datarate = padapter->fix_rate;				
+			}
+		#endif	
+		
+			
+		}
+		else
+		{
+			// EAP data packet and ARP and DHCP packet.
+			// Use the 1M or 6M data rate to send the EAP/ARP packet.
+			// This will maybe make the handshake smooth.
+
+			ptxdesc->bk = 1; // AGG BK	
+
+			if (pmlmeinfo->preamble_mode == PREAMBLE_SHORT)
+				ptxdesc->data_short = 1;// DATA_SHORT
+
+			ptxdesc->datarate = MRateToHwRate(pmlmeext->tx_rate);
+		}
+
+		ptxdesc->usb_txagg_num = pxmitframe->agg_num;
+	}
+	else if (pxmitframe->frame_tag == MGNT_FRAMETAG)
+	{
+//		RT_TRACE(_module_hal_xmit_c_, _drv_notice_, ("%s: MGNT_FRAMETAG\n", __FUNCTION__));
+
+		ptxdesc->macid = pattrib->mac_id; // CAM_ID(MAC_ID)
+		ptxdesc->qsel = pattrib->qsel;
+		ptxdesc->rate_id = pattrib->raid; // Rate ID
+		ptxdesc->seq = pattrib->seqnum;
+		ptxdesc->userate = 1; // driver uses rate, 1M
+		ptxdesc->rty_lmt_en = 1; // retry limit enable
+		ptxdesc->data_rt_lmt = 6; // retry limit = 6
+
+#ifdef CONFIG_XMIT_ACK
+		//CCX-TXRPT ack for xmit mgmt frames.
+		if (pxmitframe->ack_report) {
+			#ifdef DBG_CCX
+			static u16 ccx_sw = 0x123;
+			txdesc_set_ccx_sw_88e(ptxdesc, ccx_sw);
+			DBG_871X("%s set ccx, sw:0x%03x\n", __func__, ccx_sw);
+			ccx_sw = (ccx_sw+1)%0xfff;
+			#endif
+			ptxdesc->ccx = 1;
+		}
+#endif //CONFIG_XMIT_ACK
+
+#ifdef CONFIG_INTEL_PROXIM
+		if((padapter->proximity.proxim_on==_TRUE)&&(pattrib->intel_proxim==_TRUE)){
+			DBG_871X("\n %s pattrib->rate=%d\n",__FUNCTION__,pattrib->rate);
+			ptxdesc->datarate = pattrib->rate;
+		}
+		else
+#endif
+		{
+			ptxdesc->datarate = MRateToHwRate(pmlmeext->tx_rate);
+		}
+	}
+	else if (pxmitframe->frame_tag == TXAGG_FRAMETAG)
+	{
+		RT_TRACE(_module_hal_xmit_c_, _drv_warning_, ("%s: TXAGG_FRAMETAG\n", __FUNCTION__));
+	}
+#ifdef CONFIG_MP_INCLUDED
+	else if (pxmitframe->frame_tag == MP_FRAMETAG)
+	{
+		struct tx_desc *pdesc;
+
+		pdesc = (struct tx_desc*)ptxdesc;
+		RT_TRACE(_module_hal_xmit_c_, _drv_notice_, ("%s: MP_FRAMETAG\n", __FUNCTION__));
+		fill_txdesc_for_mp(padapter, pdesc);
+
+		pdesc->txdw0 = le32_to_cpu(pdesc->txdw0);
+		pdesc->txdw1 = le32_to_cpu(pdesc->txdw1);
+		pdesc->txdw2 = le32_to_cpu(pdesc->txdw2);
+		pdesc->txdw3 = le32_to_cpu(pdesc->txdw3);
+		pdesc->txdw4 = le32_to_cpu(pdesc->txdw4);
+		pdesc->txdw5 = le32_to_cpu(pdesc->txdw5);
+		pdesc->txdw6 = le32_to_cpu(pdesc->txdw6);
+		pdesc->txdw7 = le32_to_cpu(pdesc->txdw7);
+	}
+#endif // CONFIG_MP_INCLUDED
+	else
+	{
+		RT_TRACE(_module_hal_xmit_c_, _drv_warning_, ("%s: frame_tag=0x%x\n", __FUNCTION__, pxmitframe->frame_tag));
+
+		ptxdesc->macid = 4; // CAM_ID(MAC_ID)
+		ptxdesc->rate_id = 6; // Rate ID
+		ptxdesc->seq = pattrib->seqnum;
+		ptxdesc->userate = 1; // driver uses rate
+		ptxdesc->datarate = MRateToHwRate(pmlmeext->tx_rate);
+	}
+
+	ptxdesc->pktlen = pattrib->last_txcmdsz;
+	if (pxmitframe->frame_tag == DATA_FRAMETAG){
+		#ifdef CONFIG_TX_EARLY_MODE
+		ptxdesc->offset = TXDESC_SIZE +EARLY_MODE_INFO_SIZE ;
+		ptxdesc->pkt_offset = 0x01;
+		#else
+		ptxdesc->offset = TXDESC_SIZE ;
+		ptxdesc->pkt_offset = 0;
+		#endif
+	}
+	else{
+		ptxdesc->offset = TXDESC_SIZE ;
+	}
+	
+	if (bmcst) ptxdesc->bmc = 1;
+	ptxdesc->ls = 1;
+	ptxdesc->fs = 1;
+	ptxdesc->own = 1;
+
+	// 2009.11.05. tynli_test. Suggested by SD4 Filen for FW LPS.
+	// (1) The sequence number of each non-Qos frame / broadcast / multicast /
+	// mgnt frame should be controled by Hw because Fw will also send null data
+	// which we cannot control when Fw LPS enable.
+	// --> default enable non-Qos data sequense number. 2010.06.23. by tynli.
+	// (2) Enable HW SEQ control for beacon packet, because we use Hw beacon.
+	// (3) Use HW Qos SEQ to control the seq num of Ext port non-Qos packets.
+	// 2010.06.23. Added by tynli.
+	if (!pattrib->qos_en)
+	{
+		// Hw set sequence number
+		ptxdesc->hwseq_en = 1; // HWSEQ_EN
+		ptxdesc->hwseq_sel = 0; // HWSEQ_SEL
+	}
+
+}
+
+/*
+ *	Description:
+ *
+ *	Parameters:
+ *		pxmitframe	xmitframe
+ *		pbuf		where to fill tx desc
+ */
+void rtl8188es_update_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf)
+{
+	struct tx_desc *pdesc;
+
+
+	pdesc = (struct tx_desc*)pbuf;
+	_rtw_memset(pdesc, 0, sizeof(struct tx_desc));
+
+	rtl8188es_fill_default_txdesc(pxmitframe, pbuf);
+
+	pdesc->txdw0 = cpu_to_le32(pdesc->txdw0);
+	pdesc->txdw1 = cpu_to_le32(pdesc->txdw1);
+	pdesc->txdw2 = cpu_to_le32(pdesc->txdw2);
+	pdesc->txdw3 = cpu_to_le32(pdesc->txdw3);
+	pdesc->txdw4 = cpu_to_le32(pdesc->txdw4);
+	pdesc->txdw5 = cpu_to_le32(pdesc->txdw5);
+	pdesc->txdw6 = cpu_to_le32(pdesc->txdw6);
+	pdesc->txdw7 = cpu_to_le32(pdesc->txdw7);
+
+	rtl8188e_cal_txdesc_chksum(pdesc);
+}
+
+static inline u32 ffaddr2deviceId(struct dvobj_priv *pdvobj, u32 addr)
+{
+	return pdvobj->Queue2Pipe[addr];
+}
+
+#ifdef CONFIG_SDIO_REDUCE_TX_POLLING
+static u8 rtl8188es_query_tx_freepage(_adapter *padapter, struct xmit_buf *pxmitbuf)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
+	u8	TxRequiredPageNum = 0;
+	u8	DedicatedPgNum = 0;
+	u8	RequiredPublicFreePgNum = 0;
+	u8	PageIdx = 0;
+	u8	CheckStep = 0;
+	u8	bResult = _TRUE;
+	u8	bUpdatePageNum = _FALSE;
+	u32	deviceId;
+
+
+	TxRequiredPageNum = pxmitbuf->pg_num;
+
+	deviceId = ffaddr2deviceId(pdvobjpriv, pxmitbuf->ff_hwaddr);
+
+	// translate fifo addr to queue index
+	switch (deviceId) {
+		case WLAN_TX_HIQ_DEVICE_ID:
+				PageIdx = HI_QUEUE_IDX;
+				break;
+
+		case WLAN_TX_MIQ_DEVICE_ID:
+				PageIdx = MID_QUEUE_IDX;
+				break;
+
+		case WLAN_TX_LOQ_DEVICE_ID:
+				PageIdx = LOW_QUEUE_IDX;
+				break;
+	}
+
+	do {
+		if ((padapter->bSurpriseRemoved == _TRUE) || (padapter->bDriverStopped == _TRUE)){
+			RT_TRACE(_module_hal_xmit_c_, _drv_notice_,
+				 ("%s: bSurpriseRemoved(update TX FIFO page)\n", __FUNCTION__));
+			break;
+		}
+
+		// The number of page which public page is included is available .
+		if ((pHalData->SdioTxFIFOFreePage[PageIdx]+pHalData->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX]) > (TxRequiredPageNum+1)) {
+			DedicatedPgNum = pHalData->SdioTxFIFOFreePage[PageIdx];
+			if (TxRequiredPageNum <= DedicatedPgNum) {
+				pHalData->SdioTxFIFOFreePage[PageIdx] -= TxRequiredPageNum;
+				break;
+			} else {
+				pHalData->SdioTxFIFOFreePage[PageIdx] = 0;
+				RequiredPublicFreePgNum = TxRequiredPageNum - DedicatedPgNum;
+				pHalData->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX] -= RequiredPublicFreePgNum;
+				break;
+			}
+		} else { // Total number of page is NOT available, so update current FIFO status.
+			if (!bUpdatePageNum) {
+				bResult = HalQueryTxBufferStatus8189ESdio(padapter); // Set to default value.
+				bUpdatePageNum = _TRUE;
+			} else {
+				bResult = _FALSE;
+			}
+		}	
+	}while(++CheckStep < 2); // step1: user page variables, step2: physical page number
+
+	RT_TRACE(_module_hal_xmit_c_, _drv_notice_, ("%s(): HIQ(%#x), MIQ(%#x), LOQ(%#x), PUBQ(%#x)\n", 
+			__FUNCTION__,
+			pHalData->SdioTxFIFOFreePage[HI_QUEUE_IDX], 
+			pHalData->SdioTxFIFOFreePage[MID_QUEUE_IDX], 
+			pHalData->SdioTxFIFOFreePage[LOW_QUEUE_IDX], 
+			pHalData->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX]));
+	
+	RT_TRACE(_module_hal_xmit_c_, _drv_notice_, ("%s(): TxRequiredPageNum(%d) is available to send?(%d)\n", 
+			__FUNCTION__, TxRequiredPageNum, bResult));
+
+	return bResult;
+}
+#else
+static u8 rtl8188es_query_tx_freepage(_adapter *padapter, struct xmit_buf *pxmitbuf)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
+	u8	TxRequiredPageNum = 0;
+	u8	DedicatedPgNum = 0;
+	u8	RequiredPublicFreePgNum = 0;
+	u8	PageIdx = 0;
+	u8	bResult = _TRUE;
+	u32	n, deviceId;
+
+	TxRequiredPageNum = pxmitbuf->pg_num;
+
+	deviceId = ffaddr2deviceId(pdvobjpriv, pxmitbuf->ff_hwaddr);
+
+	// translate fifo addr to queue index
+	switch (deviceId) {
+		case WLAN_TX_HIQ_DEVICE_ID:
+				PageIdx = HI_QUEUE_IDX;
+				break;
+
+		case WLAN_TX_MIQ_DEVICE_ID:
+				PageIdx = MID_QUEUE_IDX;
+				break;
+
+		case WLAN_TX_LOQ_DEVICE_ID:
+				PageIdx = LOW_QUEUE_IDX;
+				break;
+	}
+
+	// check if hardware tx fifo page is enough
+	n = 0;
+	do {
+		if ((padapter->bSurpriseRemoved == _TRUE) || (padapter->bDriverStopped == _TRUE)){
+			RT_TRACE(_module_hal_xmit_c_, _drv_notice_,
+				 ("%s: bSurpriseRemoved(update TX FIFO page)\n", __FUNCTION__));
+			break;
+		}
+		
+		// The number of page which public page is included is available .
+		if ((pHalData->SdioTxFIFOFreePage[PageIdx]+pHalData->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX]) > (TxRequiredPageNum+1)) {
+			DedicatedPgNum = pHalData->SdioTxFIFOFreePage[PageIdx];
+			if (TxRequiredPageNum <= DedicatedPgNum) {
+				pHalData->SdioTxFIFOFreePage[PageIdx] -= TxRequiredPageNum;
+				break;
+			} else {
+				pHalData->SdioTxFIFOFreePage[PageIdx] = 0;
+				RequiredPublicFreePgNum = TxRequiredPageNum - DedicatedPgNum;
+				pHalData->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX] -= RequiredPublicFreePgNum;
+				break;
+			}
+		}
+
+		n++;
+		if ((n % 60) == 0) {//or 80
+			//DBG_871X("%s: FIFO starvation!(%d) len=%d agg=%d page=(R)%d(A)%d\n",
+			//	__func__, n, pxmitbuf->len, pxmitbuf->agg_num, pframe->pg_num, freePage[PageIdx] + freePage[PUBLIC_QUEUE_IDX]);
+			rtw_msleep_os(10);
+			rtw_yield_os();
+		}
+
+		// Total number of page is NOT available, so update current FIFO status
+		HalQueryTxBufferStatus8189ESdio(padapter);
+	} while (1);
+
+	return bResult;
+}
+#endif
+
+//todo: static 
+s32 rtl8188es_dequeue_writeport(PADAPTER padapter, u8 *freePage)
+{
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
+	struct xmit_buf *pxmitbuf;
+	PADAPTER pri_padapter = padapter;
+	s32 ret = 0;
+
+#ifdef CONFIG_CONCURRENT_MODE
+	if (padapter->adapter_type > 0)
+		pri_padapter = padapter->pbuddy_adapter;
+
+	if(rtw_buddy_adapter_up(padapter))
+		ret = check_buddy_fwstate( padapter,  _FW_UNDER_SURVEY);
+#endif
+
+	ret = ret || check_fwstate(pmlmepriv, _FW_UNDER_SURVEY);
+
+	if (_TRUE == ret)
+		pxmitbuf = dequeue_pending_xmitbuf_under_survey(pxmitpriv);
+	else
+		pxmitbuf = dequeue_pending_xmitbuf(pxmitpriv);
+
+	if (pxmitbuf == NULL) 
+		return _TRUE;
+
+query_free_page:
+	// check if hardware tx fifo page is enough
+	if( _FALSE == rtl8188es_query_tx_freepage(pri_padapter, pxmitbuf))
+	{
+		rtw_msleep_os(1);
+		goto query_free_page;
+	}
+
+	if ((padapter->bSurpriseRemoved == _TRUE) 
+		|| (padapter->bDriverStopped == _TRUE)
+#ifdef CONFIG_CONCURRENT_MODE
+		||((padapter->pbuddy_adapter) 
+		&& ((padapter->pbuddy_adapter->bSurpriseRemoved) ||(padapter->pbuddy_adapter->bDriverStopped)))
+#endif
+	){
+		RT_TRACE(_module_hal_xmit_c_, _drv_notice_,
+			 ("%s: bSurpriseRemoved(wirte port)\n", __FUNCTION__));
+		goto free_xmitbuf;
+	}
+
+	rtw_write_port(padapter, ffaddr2deviceId(pdvobjpriv, pxmitbuf->ff_hwaddr), pxmitbuf->len, (u8 *)pxmitbuf);
+
+free_xmitbuf:		
+	//rtw_free_xmitframe(pxmitpriv, pframe);
+	//pxmitbuf->priv_data = NULL;
+	rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
+
+#ifdef CONFIG_SDIO_TX_TASKLET
+	tasklet_hi_schedule(&pxmitpriv->xmit_tasklet);
+#endif
+
+	return _FAIL;
+}
+
+/*
+ * Description
+ *	Transmit xmitbuf to hardware tx fifo
+ *
+ * Return
+ *	_SUCCESS	ok
+ *	_FAIL		something error
+ */
+s32 rtl8188es_xmit_buf_handler(PADAPTER padapter)
+{
+	struct mlme_priv *pmlmepriv;
+	struct xmit_priv *pxmitpriv;
+	struct xmit_buf *pxmitbuf;
+	struct xmit_frame *pframe;
+	u8 *freePage;
+	u32 requiredPage;
+	u8 PageIdx , queue_empty;
+	_irqL irql;
+	u32 n;
+	s32 ret;
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+#ifdef CONFIG_CONCURRENT_MODE
+	s32 buddy_rm_stop = _FAIL;
+#endif
+
+	pmlmepriv = &padapter->mlmepriv;
+	pxmitpriv = &padapter->xmitpriv;
+	freePage = pHalData->SdioTxFIFOFreePage;
+
+	ret = _rtw_down_sema(&pxmitpriv->xmit_sema);
+	if (ret == _FAIL) {
+		RT_TRACE(_module_hal_xmit_c_, _drv_emerg_, ("down SdioXmitBufSema fail!\n"));
+		return _FAIL;
+	}
+
+//#ifdef CONFIG_CONCURRENT_MODE
+//	if (padapter->pbuddy_adapter->bup){
+//		if ((padapter->pbuddy_adapter->bSurpriseRemoved == _TRUE) || 
+//			(padapter->pbuddy_adapter->bDriverStopped == _TRUE))
+//			buddy_rm_stop = _TRUE; 
+//	}
+//#endif
+	if ((padapter->bSurpriseRemoved == _TRUE) || 
+		(padapter->bDriverStopped == _TRUE) 
+//#ifdef CONFIG_CONCURRENT_MODE
+//		||(buddy_rm_stop == _TRUE)
+//#endif
+	) {
+
+#ifdef CONFIG_LPS_LCLK
+		rtw_unregister_tx_alive(padapter);
+#endif
+		RT_TRACE(_module_hal_xmit_c_, _drv_notice_,
+				 ("%s: bDriverStopped(%d) bSurpriseRemoved(%d)\n",
+				  __FUNCTION__, padapter->bDriverStopped, padapter->bSurpriseRemoved));
+		return _FAIL;
+	}
+
+#ifdef CONFIG_LPS_LCLK
+	ret = rtw_register_tx_alive(padapter);
+	if (ret != _SUCCESS) return _SUCCESS;
+#endif
+
+	do {
+		queue_empty = rtl8188es_dequeue_writeport(padapter, freePage);
+//	dump secondary adapter xmitbuf 
+#ifdef CONFIG_CONCURRENT_MODE
+		if(rtw_buddy_adapter_up(padapter))
+			queue_empty &= rtl8188es_dequeue_writeport(padapter->pbuddy_adapter, freePage);
+#endif
+
+	} while ( !queue_empty);
+
+#ifdef CONFIG_LPS_LCLK
+	rtw_unregister_tx_alive(padapter);
+#endif
+	return _SUCCESS;
+}
+
+#if 0
+/*
+ * Description:
+ *	Aggregation packets and send to hardware
+ *
+ * Return:
+ *	0	Success
+ *	-1	Hardware resource(TX FIFO) not ready
+ *	-2	Software resource(xmitbuf) not ready
+ */
+#ifdef CONFIG_TX_EARLY_MODE
+#if RTL8188E_EARLY_MODE_PKT_NUM_10 == 1	
+	#define EARLY_MODE_MAX_PKT_NUM	10
+#else
+	#define EARLY_MODE_MAX_PKT_NUM	5
+#endif
+
+
+struct EMInfo{
+	u8 	EMPktNum;
+	u16  EMPktLen[EARLY_MODE_MAX_PKT_NUM];
+};
+
+
+void
+InsertEMContent_8188E(
+	struct EMInfo *pEMInfo,
+	IN pu1Byte	VirtualAddress)
+{
+
+#if RTL8188E_EARLY_MODE_PKT_NUM_10 == 1
+	u1Byte index=0;
+	u4Byte	dwtmp=0;
+#endif
+
+	_rtw_memset(VirtualAddress, 0, EARLY_MODE_INFO_SIZE);
+	if(pEMInfo->EMPktNum==0)
+		return;
+
+	#ifdef DBG_EMINFO
+	{
+		int i;
+		DBG_8192C("\n%s ==> pEMInfo->EMPktNum =%d\n",__FUNCTION__,pEMInfo->EMPktNum);
+		for(i=0;i< EARLY_MODE_MAX_PKT_NUM;i++){
+			DBG_8192C("%s ==> pEMInfo->EMPktLen[%d] =%d\n",__FUNCTION__,i,pEMInfo->EMPktLen[i]);
+		}
+
+	}
+	#endif
+	
+#if RTL8188E_EARLY_MODE_PKT_NUM_10 == 1
+	SET_EARLYMODE_PKTNUM(VirtualAddress, pEMInfo->EMPktNum);
+
+	if(pEMInfo->EMPktNum == 1){
+		dwtmp = pEMInfo->EMPktLen[0];
+	}else{
+		dwtmp = pEMInfo->EMPktLen[0];
+		dwtmp += ((dwtmp%4)?(4-dwtmp%4):0)+4;
+		dwtmp += pEMInfo->EMPktLen[1];
+	}
+	SET_EARLYMODE_LEN0(VirtualAddress, dwtmp);
+	if(pEMInfo->EMPktNum <= 3){
+		dwtmp = pEMInfo->EMPktLen[2];
+	}else{
+		dwtmp = pEMInfo->EMPktLen[2];
+		dwtmp += ((dwtmp%4)?(4-dwtmp%4):0)+4;
+		dwtmp += pEMInfo->EMPktLen[3];
+	}
+	SET_EARLYMODE_LEN1(VirtualAddress, dwtmp);
+	if(pEMInfo->EMPktNum <= 5){
+		dwtmp = pEMInfo->EMPktLen[4];
+	}else{
+		dwtmp = pEMInfo->EMPktLen[4];
+		dwtmp += ((dwtmp%4)?(4-dwtmp%4):0)+4;
+		dwtmp += pEMInfo->EMPktLen[5];
+	}
+	SET_EARLYMODE_LEN2_1(VirtualAddress, dwtmp&0xF);
+	SET_EARLYMODE_LEN2_2(VirtualAddress, dwtmp>>4);
+	if(pEMInfo->EMPktNum <= 7){
+		dwtmp = pEMInfo->EMPktLen[6];
+	}else{
+		dwtmp = pEMInfo->EMPktLen[6];
+		dwtmp += ((dwtmp%4)?(4-dwtmp%4):0)+4;
+		dwtmp += pEMInfo->EMPktLen[7];
+	}
+	SET_EARLYMODE_LEN3(VirtualAddress, dwtmp);
+	if(pEMInfo->EMPktNum <= 9){
+		dwtmp = pEMInfo->EMPktLen[8];
+	}else{
+		dwtmp = pEMInfo->EMPktLen[8];
+		dwtmp += ((dwtmp%4)?(4-dwtmp%4):0)+4;
+		dwtmp += pEMInfo->EMPktLen[9];
+	}
+	SET_EARLYMODE_LEN4(VirtualAddress, dwtmp);
+#else	
+	SET_EARLYMODE_PKTNUM(VirtualAddress, pEMInfo->EMPktNum);
+	SET_EARLYMODE_LEN0(VirtualAddress, pEMInfo->EMPktLen[0]);
+	SET_EARLYMODE_LEN1(VirtualAddress, pEMInfo->EMPktLen[1]);
+	SET_EARLYMODE_LEN2_1(VirtualAddress, pEMInfo->EMPktLen[2]&0xF);
+	SET_EARLYMODE_LEN2_2(VirtualAddress, pEMInfo->EMPktLen[2]>>4);
+	SET_EARLYMODE_LEN3(VirtualAddress, pEMInfo->EMPktLen[3]);
+	SET_EARLYMODE_LEN4(VirtualAddress, pEMInfo->EMPktLen[4]);
+#endif	
+	//RT_PRINT_DATA(COMP_SEND, DBG_LOUD, "EMHdr:", VirtualAddress, 8);
+
+}
+
+
+
+void UpdateEarlyModeInfo8188E(struct xmit_priv *pxmitpriv,struct xmit_buf *pxmitbuf )
+{
+	//_adapter *padapter, struct xmit_frame *pxmitframe,struct tx_servq	*ptxservq
+	int index,j;
+	u16 offset,pktlen;
+	PTXDESC ptxdesc;
+	
+	u8 *pmem,*pEMInfo_mem;
+	s8 node_num_0=0,node_num_1=0;
+	struct EMInfo eminfo;
+	struct agg_pkt_info *paggpkt;
+	struct xmit_frame *pframe = (struct xmit_frame*)pxmitbuf->priv_data;	
+	pmem= pframe->buf_addr;	
+	
+	#ifdef DBG_EMINFO			
+	DBG_8192C("\n%s ==> agg_num:%d\n",__FUNCTION__, pframe->agg_num);
+	for(index=0;index<pframe->agg_num;index++){
+		offset = 	pxmitpriv->agg_pkt[index].offset;
+		pktlen = pxmitpriv->agg_pkt[index].pkt_len;
+		DBG_8192C("%s ==> agg_pkt[%d].offset=%d\n",__FUNCTION__,index,offset);
+		DBG_8192C("%s ==> agg_pkt[%d].pkt_len=%d\n",__FUNCTION__,index,pktlen);
+	}
+	#endif
+	
+	if( pframe->agg_num > EARLY_MODE_MAX_PKT_NUM)
+	{	
+		node_num_0 = pframe->agg_num;
+		node_num_1= EARLY_MODE_MAX_PKT_NUM-1;
+	}
+	
+	for(index=0;index<pframe->agg_num;index++){
+		offset = pxmitpriv->agg_pkt[index].offset;
+		pktlen = pxmitpriv->agg_pkt[index].pkt_len;		
+
+		_rtw_memset(&eminfo,0,sizeof(struct EMInfo));
+		if( pframe->agg_num > EARLY_MODE_MAX_PKT_NUM){
+			if(node_num_0 > EARLY_MODE_MAX_PKT_NUM){
+				eminfo.EMPktNum = EARLY_MODE_MAX_PKT_NUM;
+				node_num_0--;
+			}
+			else{
+				eminfo.EMPktNum = node_num_1;
+				node_num_1--;				
+			}			
+		}
+		else{
+			eminfo.EMPktNum = pframe->agg_num-(index+1);	
+		}				
+		for(j=0;j< eminfo.EMPktNum ;j++){
+			eminfo.EMPktLen[j] = pxmitpriv->agg_pkt[index+1+j].pkt_len+4;//CRC
+		}
+			
+		if(pmem){
+			ptxdesc = (PTXDESC)(pmem+offset);
+			pEMInfo_mem = pmem+offset+TXDESC_SIZE;	
+			#ifdef DBG_EMINFO
+			DBG_8192C("%s ==> desc.pkt_len=%d\n",__FUNCTION__,ptxdesc->pktlen);
+			#endif
+			InsertEMContent_8188E(&eminfo,pEMInfo_mem);
+		}	
+		
+		
+	} 
+	_rtw_memset(pxmitpriv->agg_pkt,0,sizeof(struct agg_pkt_info)*MAX_AGG_PKT_NUM);
+
+}
+#endif
+
+#endif
+
+#ifdef CONFIG_SDIO_TX_TASKLET
+static s32 xmit_xmitframes(PADAPTER padapter, struct xmit_priv *pxmitpriv)
+{
+	s32 ret;
+	_irqL irqL;
+	struct xmit_buf	*pxmitbuf;
+	struct hw_xmit	*phwxmit = pxmitpriv->hwxmits;
+	struct tx_servq	*ptxservq = NULL;
+	_list	*xmitframe_plist = NULL, *xmitframe_phead = NULL;
+	struct xmit_frame	*pxmitframe = NULL, *pfirstframe = NULL;
+	u32	pbuf = 0; // next pkt address
+	u32	pbuf_tail = 0; // last pkt tail
+	u32	txlen = 0; //packet length, except TXDESC_SIZE and PKT_OFFSET
+	u32	total_len = 0;
+	u8	ac_index = 0;
+	u8	bfirst = _TRUE;//first aggregation xmitframe
+	u8	bulkstart = _FALSE;
+#ifdef CONFIG_TX_EARLY_MODE
+	u8	pkt_index=0;
+#endif
+
+	pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv);
+	if (pxmitbuf == NULL) {
+		RT_TRACE(_module_hal_xmit_c_, _drv_err_, ("%s: xmit_buf is not enough!\n", __FUNCTION__));
+		return _FALSE;
+	}
+
+	do {
+		//3 1. pick up first frame
+		if(bfirst)
+		{
+			pxmitframe = rtw_dequeue_xframe(pxmitpriv, pxmitpriv->hwxmits, pxmitpriv->hwxmit_entry);
+			if (pxmitframe == NULL) {
+				// no more xmit frame, release xmit buffer
+				rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
+				return _FALSE;
+			}
+
+			pxmitframe->pxmitbuf = pxmitbuf;
+			pxmitframe->buf_addr = pxmitbuf->pbuf;
+			pxmitbuf->priv_data = pxmitframe;
+			pxmitbuf->ff_hwaddr = rtw_get_ff_hwaddr(pxmitframe);
+
+			pfirstframe = pxmitframe;
+
+			_enter_critical_bh(&pxmitpriv->lock, &irqL);
+			ptxservq = rtw_get_sta_pending(padapter, pfirstframe->attrib.psta, pfirstframe->attrib.priority, (u8 *)(&ac_index));
+			_exit_critical_bh(&pxmitpriv->lock, &irqL);
+		}
+		//3 2. aggregate same priority and same DA(AP or STA) frames
+		else
+		{
+			// dequeue same priority packet from station tx queue
+			_enter_critical_bh(&pxmitpriv->lock, &irqL);
+
+			if (_rtw_queue_empty(&ptxservq->sta_pending) == _FALSE)
+			{
+				xmitframe_phead = get_list_head(&ptxservq->sta_pending);
+				xmitframe_plist = get_next(xmitframe_phead);
+
+				pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);
+
+				// check xmit_buf size enough or not
+				txlen = TXDESC_SIZE +
+				#ifdef CONFIG_TX_EARLY_MODE	
+					EARLY_MODE_INFO_SIZE +
+				#endif
+					rtw_wlan_pkt_size(pxmitframe);
+
+				if (pbuf + _RND8(txlen) > MAX_XMITBUF_SZ)
+				{
+					bulkstart = _TRUE;
+				}
+				else
+				{
+					rtw_list_delete(&pxmitframe->list);
+					ptxservq->qcnt--;
+					phwxmit[ac_index].accnt--;
+
+					//Remove sta node when there is no pending packets.
+					if (_rtw_queue_empty(&ptxservq->sta_pending) == _TRUE)
+						rtw_list_delete(&ptxservq->tx_pending);
+				}
+			}
+			else
+			{
+				bulkstart = _TRUE;
+			}
+
+			_exit_critical_bh(&pxmitpriv->lock, &irqL);
+
+			if(bulkstart)
+			{
+				break;
+			}
+
+			pxmitframe->buf_addr = pxmitbuf->pbuf + pbuf;
+
+			pxmitframe->agg_num = 0; // not first frame of aggregation
+		}
+ 
+		ret = rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe);
+		if (ret == _FAIL) {
+			DBG_871X("%s: coalesce FAIL!", __FUNCTION__);
+			rtw_free_xmitframe(pxmitpriv, pxmitframe);
+			continue;
+		} 
+
+		// always return ndis_packet after rtw_xmitframe_coalesce
+		//rtw_os_xmit_complete(padapter, pxmitframe);
+
+#ifdef CONFIG_TX_EARLY_MODE
+		pxmitpriv->agg_pkt[pkt_index].pkt_len = pxmitframe->attrib.last_txcmdsz;	//get from rtw_xmitframe_coalesce
+		pxmitpriv->agg_pkt[pkt_index].offset = _RND8(pxmitframe->attrib.last_txcmdsz+ TXDESC_SIZE+EARLY_MODE_INFO_SIZE);
+		pkt_index++;
+#endif
+
+		if(bfirst)
+		{
+			txlen = TXDESC_SIZE +
+			#ifdef CONFIG_TX_EARLY_MODE	
+				EARLY_MODE_INFO_SIZE +
+			#endif
+				pxmitframe->attrib.last_txcmdsz;
+
+			total_len = txlen;
+
+			pxmitframe->pg_num = (txlen + 127)/128;
+			pxmitbuf->pg_num = (txlen + 127)/128;
+			pbuf_tail = txlen;
+			pbuf = _RND8(pbuf_tail);
+			bfirst = _FALSE;
+		}
+		else
+		{
+			rtl8188es_update_txdesc(pxmitframe, pxmitframe->buf_addr);
+
+			// don't need xmitframe any more
+			rtw_free_xmitframe(pxmitpriv, pxmitframe);
+
+			pxmitframe->pg_num = (txlen + 127)/128;
+			//pfirstframe->pg_num += pxmitframe->pg_num;
+			pxmitbuf->pg_num += (txlen + 127)/128;
+
+			total_len += txlen;
+
+			// handle pointer and stop condition
+			pbuf_tail = pbuf + txlen;
+			pbuf = _RND8(pbuf_tail);
+
+			pfirstframe->agg_num++;
+			#ifdef SDIO_TX_AGG_MAX
+			if(pfirstframe->agg_num >= SDIO_TX_AGG_MAX)
+				break;
+			#endif
+		}
+	}while(1);
+
+	//3 3. update first frame txdesc
+	rtl8188es_update_txdesc(pfirstframe, pfirstframe->buf_addr);
+#ifdef CONFIG_TX_EARLY_MODE						
+	UpdateEarlyModeInfo8188E(pxmitpriv,pxmitbuf );
+#endif
+
+	//
+	pxmitbuf->agg_num = pfirstframe->agg_num;	
+	pxmitbuf->priv_data = NULL;
+
+	//3 4. write xmit buffer to USB FIFO
+	pxmitbuf->len = pbuf_tail;
+	enqueue_pending_xmitbuf(pxmitpriv, pxmitbuf);
+
+	//3 5. update statisitc
+	rtw_count_tx_stats(padapter, pfirstframe, total_len);
+
+	rtw_free_xmitframe(pxmitpriv, pfirstframe);
+
+	//rtw_yield_os();
+
+	return _TRUE;
+}
+
+void rtl8188es_xmit_tasklet(void *priv)
+{	
+	int ret = _FALSE;
+	_adapter *padapter = (_adapter*)priv;
+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+
+	while(1)
+	{
+		if ((padapter->bDriverStopped == _TRUE)||(padapter->bSurpriseRemoved== _TRUE) || (padapter->bWritePortCancel == _TRUE))
+		{
+			DBG_871X("xmit_tasklet => bDriverStopped or bSurpriseRemoved or bWritePortCancel\n");
+			break;
+		}
+
+		ret = xmit_xmitframes(padapter, pxmitpriv);
+		if(ret==_FALSE)
+			break;
+		
+	}
+}
+#else
+static s32 xmit_xmitframes(PADAPTER padapter, struct xmit_priv *pxmitpriv)
+{
+	u32 err, agg_num=0;
+	u8 pkt_index=0;
+	struct hw_xmit *hwxmits, *phwxmit;
+	u8 idx, hwentry;
+	_irqL irql;
+	struct tx_servq	*ptxservq;
+	_list *sta_plist, *sta_phead, *frame_plist, *frame_phead;
+	struct xmit_frame *pxmitframe;
+	_queue *pframe_queue;
+	struct xmit_buf *pxmitbuf;
+	u32 txlen;
+	s32 ret;
+	int inx[4];
+
+
+	err = 0;
+	hwxmits = pxmitpriv->hwxmits;
+	hwentry = pxmitpriv->hwxmit_entry;
+	ptxservq = NULL;
+	pxmitframe = NULL;
+	pframe_queue = NULL;
+	pxmitbuf = NULL;
+
+	if (padapter->registrypriv.wifi_spec == 1) {
+		for(idx=0; idx<4; idx++)
+			inx[idx] = pxmitpriv->wmm_para_seq[idx];
+	} else {
+		inx[0] = 0; inx[1] = 1; inx[2] = 2; inx[3] = 3;
+	}
+
+	// 0(VO), 1(VI), 2(BE), 3(BK)
+	for (idx = 0; idx < hwentry; idx++) 
+	{
+		phwxmit = hwxmits + inx[idx];
+	
+//		_enter_critical(&hwxmits->sta_queue->lock, &irqL0);
+		_enter_critical_bh(&pxmitpriv->lock, &irql);
+
+		sta_phead = get_list_head(phwxmit->sta_queue);
+		sta_plist = get_next(sta_phead);
+
+		while (rtw_end_of_queue_search(sta_phead, sta_plist) == _FALSE)
+		{
+			ptxservq = LIST_CONTAINOR(sta_plist, struct tx_servq, tx_pending);
+
+			sta_plist = get_next(sta_plist);
+
+			pframe_queue = &ptxservq->sta_pending;
+
+//			_enter_critical(&pframe_queue->lock, &irqL1);
+			//_enter_critical_bh(&pxmitpriv->lock, &irql);
+
+			frame_phead = get_list_head(pframe_queue);
+			frame_plist = get_next(frame_phead);
+
+			while (rtw_end_of_queue_search(frame_phead, frame_plist) == _FALSE)
+			{
+				pxmitframe = LIST_CONTAINOR(frame_plist, struct xmit_frame, list);				
+				// check xmit_buf size enough or not
+				#ifdef CONFIG_TX_EARLY_MODE		
+				txlen = TXDESC_SIZE +EARLY_MODE_INFO_SIZE+ rtw_wlan_pkt_size(pxmitframe);
+				#else
+				txlen = TXDESC_SIZE + rtw_wlan_pkt_size(pxmitframe);
+				#endif
+				if ((NULL == pxmitbuf) ||
+					((pxmitbuf->ptail + txlen) > pxmitbuf->pend)
+				#ifdef SDIO_TX_AGG_MAX
+				|| (agg_num>= SDIO_TX_AGG_MAX)
+				#endif		
+				)
+				{
+					if (pxmitbuf) {
+						struct xmit_frame *pframe;
+						pframe = (struct xmit_frame*)pxmitbuf->priv_data;
+						pframe->agg_num = agg_num;
+						pxmitbuf->agg_num = agg_num;
+						//DBG_8192C("==> agg_num:%d\n",agg_num);
+						rtl8188es_update_txdesc(pframe, pframe->buf_addr);
+						#ifdef CONFIG_TX_EARLY_MODE						
+						UpdateEarlyModeInfo8188E(pxmitpriv, pxmitbuf);
+						#endif
+						rtw_free_xmitframe(pxmitpriv, pframe);
+						pxmitbuf->priv_data = NULL;
+						enqueue_pending_xmitbuf(pxmitpriv, pxmitbuf);
+						//rtw_yield_os();
+					}
+
+					pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv);
+					if (pxmitbuf == NULL) {
+						RT_TRACE(_module_hal_xmit_c_, _drv_err_, ("%s: xmit_buf is not enough!\n", __FUNCTION__));
+						err = -2;
+						break;
+					}
+					agg_num = 0;
+					pkt_index =0;
+				}
+
+				// ok to send, remove frame from queue
+						
+				
+				frame_plist = get_next(frame_plist);
+				rtw_list_delete(&pxmitframe->list);
+				ptxservq->qcnt--;
+				phwxmit->accnt--;
+			
+
+				if (agg_num == 0) {
+					pxmitbuf->ff_hwaddr = rtw_get_ff_hwaddr(pxmitframe);
+					pxmitbuf->priv_data = (u8*)pxmitframe;
+				}
+
+				// coalesce the xmitframe to xmitbuf
+				pxmitframe->pxmitbuf = pxmitbuf;
+				pxmitframe->buf_addr = pxmitbuf->ptail;
+
+				ret = rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe);
+				if (ret == _FAIL) {
+					RT_TRACE(_module_hal_xmit_c_, _drv_err_, ("%s: coalesce FAIL!", __FUNCTION__));
+					// Todo: error handler
+					rtw_free_xmitframe(pxmitpriv, pxmitframe);
+				} else {
+					agg_num++;
+					if (agg_num != 1)
+						rtl8188es_update_txdesc(pxmitframe, pxmitframe->buf_addr);
+					rtw_count_tx_stats(padapter, pxmitframe, pxmitframe->attrib.last_txcmdsz);
+					#ifdef CONFIG_TX_EARLY_MODE		
+					txlen = TXDESC_SIZE+ EARLY_MODE_INFO_SIZE+ pxmitframe->attrib.last_txcmdsz;
+					#else
+					txlen = TXDESC_SIZE + pxmitframe->attrib.last_txcmdsz;
+					#endif
+					pxmitframe->pg_num = (txlen + 127)/128;
+					pxmitbuf->pg_num += (txlen + 127)/128;
+					//if (agg_num != 1)
+						//((struct xmit_frame*)pxmitbuf->priv_data)->pg_num += pxmitframe->pg_num;
+										
+					#ifdef CONFIG_TX_EARLY_MODE
+					pxmitpriv->agg_pkt[pkt_index].pkt_len = pxmitframe->attrib.last_txcmdsz;	//get from rtw_xmitframe_coalesce 	
+					pxmitpriv->agg_pkt[pkt_index].offset = _RND8(pxmitframe->attrib.last_txcmdsz+ TXDESC_SIZE+EARLY_MODE_INFO_SIZE);					
+					#endif
+					
+					pkt_index++;
+					pxmitbuf->ptail += _RND(txlen, 8); // round to 8 bytes alignment
+					pxmitbuf->len = _RND(pxmitbuf->len, 8) + txlen;
+				}
+
+				if (agg_num != 1)
+					rtw_free_xmitframe(pxmitpriv, pxmitframe);
+				pxmitframe = NULL;			
+			}
+
+			if (_rtw_queue_empty(pframe_queue)) {				
+				rtw_list_delete(&ptxservq->tx_pending);
+			}
+
+//			_exit_critical(&pframe_queue->lock, &irqL1);
+			//_exit_critical_bh(&pxmitpriv->lock, &irql);
+
+		}
+
+//		_exit_critical(&hwxmits->sta_queue->lock, &irqL0);
+		_exit_critical_bh(&pxmitpriv->lock, &irql);
+
+		// dump xmit_buf to hw tx fifo
+		if (pxmitbuf)
+		{
+			RT_TRACE(_module_hal_xmit_c_, _drv_notice_, ("pxmitbuf->len=%d enqueue\n",pxmitbuf->len));
+
+			if (pxmitbuf->len > 0) {
+				struct xmit_frame *pframe;
+				pframe = (struct xmit_frame*)pxmitbuf->priv_data;
+				pframe->agg_num = agg_num;
+				pxmitbuf->agg_num = agg_num;
+				rtl8188es_update_txdesc(pframe, pframe->buf_addr);
+				#ifdef CONFIG_TX_EARLY_MODE				
+				UpdateEarlyModeInfo8188E(pxmitpriv,pxmitbuf );
+				#endif
+				rtw_free_xmitframe(pxmitpriv, pframe);
+				pxmitbuf->priv_data = NULL;
+				enqueue_pending_xmitbuf(pxmitpriv, pxmitbuf);
+				rtw_yield_os();
+			}
+			else
+				rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
+			
+			pxmitbuf = NULL;
+			
+		}
+		
+	}
+
+	return err;
+	
+}
+
+/*
+ * Description
+ *	Transmit xmitframe from queue
+ *
+ * Return
+ *	_SUCCESS	ok
+ *	_FAIL		something error
+ */
+s32 rtl8188es_xmit_handler(PADAPTER padapter)
+{
+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv ;
+	s32 ret;
+	_irqL irql;
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+//#ifdef CONFIG_CONCURRENT_MODE
+//	s32 buddy_rm_stop = _FAIL;
+//#endif
+
+
+wait:
+	ret = _rtw_down_sema(&pHalData->SdioXmitSema);
+	if (_FAIL == ret) {
+		RT_TRACE(_module_hal_xmit_c_, _drv_emerg_, ("%s: down sema fail!\n", __FUNCTION__));
+		return _FAIL;
+	}
+
+next:
+//#ifdef CONFIG_CONCURRENT_MODE
+//	if (padapter->pbuddy_adapter){
+//		if ((padapter->pbuddy_adapter->bSurpriseRemoved == _TRUE) || 
+//			(padapter->pbuddy_adapter->bDriverStopped == _TRUE))
+//			buddy_rm_stop = _TRUE; 
+//	}
+//#endif
+	if ((padapter->bSurpriseRemoved == _TRUE) || 
+		(padapter->bDriverStopped == _TRUE) 
+//#ifdef CONFIG_CONCURRENT_MODE
+//		||(buddy_rm_stop == _TRUE)
+//#endif
+	) {
+		RT_TRACE(_module_hal_xmit_c_, _drv_notice_,
+				 ("%s: bDriverStopped(%d) bSurpriseRemoved(%d)\n",
+				  __FUNCTION__, padapter->bDriverStopped, padapter->bSurpriseRemoved));
+		return _FAIL;
+	}
+	_enter_critical_bh(&pxmitpriv->lock, &irql);
+	ret = rtw_txframes_pending(padapter);
+	_exit_critical_bh(&pxmitpriv->lock, &irql);
+	if (ret == 0) {
+		return _SUCCESS;
+	}
+	// dequeue frame and write to hardware
+
+	ret = xmit_xmitframes(padapter, pxmitpriv);
+	if (ret == -2) {
+		rtw_msleep_os(1);
+		goto next;
+	}
+	_enter_critical_bh(&pxmitpriv->lock, &irql);
+	ret = rtw_txframes_pending(padapter);
+	_exit_critical_bh(&pxmitpriv->lock, &irql);
+	if (ret == 1) {
+		rtw_msleep_os(1);
+		goto next;
+	}
+
+	return _SUCCESS;
+}
+
+thread_return rtl8188es_xmit_thread(thread_context context)
+{
+	s32 ret;
+	PADAPTER padapter= (PADAPTER)context;	
+	struct xmit_priv *pxmitpriv= &padapter->xmitpriv;
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	
+	ret = _SUCCESS;
+
+	thread_enter("RTWHALXT");
+
+	DBG_871X("start %s\n", __FUNCTION__);
+
+	do {
+		ret = rtl8188es_xmit_handler(padapter);
+		if (signal_pending(current)) {
+			flush_signals(current);
+		}
+	} while (_SUCCESS == ret);
+
+	_rtw_up_sema(&pHalData->SdioXmitTerminateSema);
+
+	RT_TRACE(_module_hal_xmit_c_, _drv_notice_, ("-%s\n", __FUNCTION__));
+	DBG_871X("exit %s\n", __FUNCTION__);
+
+	thread_exit();
+}
+#endif
+
+#ifdef CONFIG_IOL_IOREG_CFG_DBG	
+#include <rtw_iol.h>
+#endif
+s32 rtl8188es_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe)
+{
+	s32 ret = _SUCCESS;
+	struct pkt_attrib	*pattrib;
+	struct xmit_buf	*pxmitbuf;
+	struct xmit_priv	*pxmitpriv = &padapter->xmitpriv;
+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
+	u8	*pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+	u8 	 pattrib_subtype;
+	
+	RT_TRACE(_module_hal_xmit_c_, _drv_info_, ("+%s\n", __FUNCTION__));
+
+	pattrib = &pmgntframe->attrib;
+	pxmitbuf = pmgntframe->pxmitbuf;
+
+	rtl8188es_update_txdesc(pmgntframe, pmgntframe->buf_addr);
+
+	pxmitbuf->len = TXDESC_SIZE + pattrib->last_txcmdsz;
+	//pmgntframe->pg_num = (pxmitbuf->len + 127)/128; // 128 is tx page size
+	pxmitbuf->pg_num = (pxmitbuf->len + 127)/128; // 128 is tx page size
+	pxmitbuf->ptail = pmgntframe->buf_addr + pxmitbuf->len;
+	pxmitbuf->ff_hwaddr = rtw_get_ff_hwaddr(pmgntframe);
+
+	rtw_count_tx_stats(padapter, pmgntframe, pattrib->last_txcmdsz);
+	pattrib_subtype = pattrib->subtype;		
+	rtw_free_xmitframe(pxmitpriv, pmgntframe);
+
+	pxmitbuf->priv_data = NULL;	
+
+	if((pattrib_subtype == WIFI_BEACON) || (GetFrameSubType(pframe)==WIFI_BEACON)) //dump beacon directly
+	{
+#ifdef CONFIG_IOL_IOREG_CFG_DBG		
+		rtw_IOL_cmd_buf_dump(padapter,pxmitbuf->len,pxmitbuf->pdata);
+#endif	
+
+		rtw_write_port(padapter, ffaddr2deviceId(pdvobjpriv, pxmitbuf->ff_hwaddr), pxmitbuf->len, (u8 *)pxmitbuf);
+		
+		//rtw_free_xmitframe(pxmitpriv, pmgntframe);
+		
+		//pxmitbuf->priv_data = NULL;
+		
+		rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
+	}		
+	else
+	{
+		enqueue_pending_xmitbuf(pxmitpriv, pxmitbuf);
+	}
+
+	if  (ret != _SUCCESS)
+		rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_UNKNOWN);
+
+	return ret;
+}
+
+/*
+ * Description:
+ *	Handle xmitframe(packet) come from rtw_xmit()
+ *
+ * Return:
+ *	_TRUE	dump packet directly ok
+ *	_FALSE	enqueue, temporary can't transmit packets to hardware
+ */
+s32 rtl8188es_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe)
+{
+	struct xmit_priv 	*pxmitpriv = &padapter->xmitpriv;
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	_irqL irql;
+	s32 err;
+
+	//pxmitframe->attrib.qsel = pxmitframe->attrib.priority;
+
+#ifdef CONFIG_80211N_HT
+	if ((pxmitframe->frame_tag == DATA_FRAMETAG) &&
+		(pxmitframe->attrib.ether_type != 0x0806) &&
+		(pxmitframe->attrib.ether_type != 0x888e) &&
+		(pxmitframe->attrib.dhcp_pkt != 1))
+	{
+		if (padapter->mlmepriv.LinkDetectInfo.bBusyTraffic == _TRUE)
+			rtw_issue_addbareq_cmd(padapter, pxmitframe);
+	}
+#endif
+
+	_enter_critical_bh(&pxmitpriv->lock, &irql);
+	err = rtw_xmitframe_enqueue(padapter, pxmitframe);
+	_exit_critical_bh(&pxmitpriv->lock, &irql);
+	if (err != _SUCCESS) {
+		RT_TRACE(_module_hal_xmit_c_, _drv_err_, ("%s: enqueue xmitframe fail\n",__FUNCTION__));
+		rtw_free_xmitframe(pxmitpriv, pxmitframe);
+
+		// Trick, make the statistics correct
+		pxmitpriv->tx_pkts--;
+		pxmitpriv->tx_drop++;
+		return _TRUE;
+	}
+
+#ifdef CONFIG_SDIO_TX_TASKLET
+	tasklet_hi_schedule(&pxmitpriv->xmit_tasklet);
+#else
+	_rtw_up_sema(&pHalData->SdioXmitSema);
+#endif
+
+	return _FALSE;
+}
+
+s32	rtl8188es_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe)
+{
+	struct xmit_priv 	*pxmitpriv = &padapter->xmitpriv;
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	s32 err;
+	
+	if ((err=rtw_xmitframe_enqueue(padapter, pxmitframe)) != _SUCCESS) 
+	{
+		rtw_free_xmitframe(pxmitpriv, pxmitframe);
+
+		// Trick, make the statistics correct
+		pxmitpriv->tx_pkts--;
+		pxmitpriv->tx_drop++;					
+	}
+	else
+	{
+#ifdef CONFIG_SDIO_TX_TASKLET
+		tasklet_hi_schedule(&pxmitpriv->xmit_tasklet);					
+#else
+		_rtw_up_sema(&pHalData->SdioXmitSema);
+#endif
+	}
+	
+	return err;
+	
+}
+
+
+/*
+ * Return
+ *	_SUCCESS	start thread ok
+ *	_FAIL		start thread fail
+ *
+ */
+s32 rtl8188es_init_xmit_priv(PADAPTER padapter)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	struct xmit_priv 	*pxmitpriv = &padapter->xmitpriv;
+
+#ifdef CONFIG_SDIO_TX_TASKLET
+#ifdef PLATFORM_LINUX
+	tasklet_init(&pxmitpriv->xmit_tasklet,
+	     (void(*)(unsigned long))rtl8188es_xmit_tasklet,
+	     (unsigned long)padapter);
+#endif
+#else //CONFIG_SDIO_TX_TASKLET
+
+	_rtw_init_sema(&pHalData->SdioXmitSema, 0);
+	_rtw_init_sema(&pHalData->SdioXmitTerminateSema, 0);
+#endif //CONFIG_SDIO_TX_TASKLET
+
+	_rtw_spinlock_init(&pHalData->SdioTxFIFOFreePageLock);
+
+#ifdef CONFIG_TX_EARLY_MODE
+	pHalData->bEarlyModeEnable = padapter->registrypriv.early_mode;
+#endif
+
+	return _SUCCESS;
+}
+
+void rtl8188es_free_xmit_priv(PADAPTER padapter)
+{
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+
+	_rtw_spinlock_free(&pHalData->SdioTxFIFOFreePageLock);
+}
+
diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/sdio/sdio_halinit.c b/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/sdio/sdio_halinit.c
new file mode 100755
index 00000000..4a607a59
--- /dev/null
+++ b/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/sdio/sdio_halinit.c
@@ -0,0 +1,4179 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#define _SDIO_HALINIT_C_
+
+#include <drv_conf.h>
+#include <osdep_service.h>
+#include <drv_types.h>
+
+#ifndef CONFIG_SDIO_HCI
+#error "CONFIG_SDIO_HCI shall be on!\n"
+#endif
+
+#include <rtw_efuse.h>
+#include <rtl8188e_hal.h>
+#include <rtl8188e_led.h>
+#include <HalPwrSeqCmd.h>
+#include <Hal8188EPwrSeq.h>
+#include <sdio_ops.h>
+
+#ifdef CONFIG_EFUSE_CONFIG_FILE
+#include <linux/fs.h>
+#include <asm/uaccess.h>
+#endif //CONFIG_EFUSE_CONFIG_FILE
+
+
+/*
+ * Description:
+ *	Call this function to make sure power on successfully
+ *
+ * Return:
+ *	_SUCCESS	enable success
+ *	_FAIL	enable fail
+ */
+
+static int PowerOnCheck(PADAPTER padapter)
+{
+	u32	val_offset0, val_offset1, val_offset2, val_offset3;
+	u32 val_mix = 0;
+	u32 res = 0;
+	u8	ret = _FAIL;
+	int index = 0;
+
+	val_offset0 = rtw_read8(padapter, REG_CR);
+	val_offset1 = rtw_read8(padapter, REG_CR+1);
+	val_offset2 = rtw_read8(padapter, REG_CR+2);
+	val_offset3 = rtw_read8(padapter, REG_CR+3);
+
+	if (val_offset0 == 0xEA || val_offset1 == 0xEA ||
+			val_offset2 == 0xEA || val_offset3 ==0xEA) {
+		DBG_871X("%s: power on fail, do Power on again\n", __func__);
+		return ret;
+	}
+
+	val_mix = val_offset3 << 24 | val_mix;
+	val_mix = val_offset2 << 16 | val_mix;
+	val_mix = val_offset1 << 8 | val_mix;
+	val_mix = val_offset0 | val_mix;
+
+	res = rtw_read32(padapter, REG_CR);
+
+	DBG_871X("%s: val_mix:0x%08x, res:0x%08x\n", __func__, val_mix, res);
+
+	while(index < 100) {
+		if (res == val_mix) {
+			DBG_871X("%s: 0x100 the result of cmd52 and cmd53 is the same.\n", __func__);
+			ret = _SUCCESS;
+			break;
+		} else {
+			DBG_871X("%s: 0x100 cmd52 and cmd53 is not the same(index:%d).\n", __func__, index);
+			res = rtw_read32(padapter, REG_CR);
+			index ++;
+			ret = _FAIL;
+		}
+	}
+
+	if (ret) {
+		index = 0;
+		while(index < 100) {
+			rtw_write32(padapter, 0x1B8, 0x12345678);
+			res = rtw_read32(padapter, 0x1B8);
+			if (res == 0x12345678) {
+				DBG_871X("%s: 0x1B8 test Pass.\n", __func__);
+				ret = _SUCCESS;
+				break;
+			} else {
+				index ++;
+				DBG_871X("%s: 0x1B8 test Fail(index: %d).\n", __func__, index);
+				ret = _FAIL;
+			}
+		}
+	} else {
+		DBG_871X("%s: fail at cmd52, cmd53.\n", __func__);
+	}
+	return ret;
+}
+
+#ifdef CONFIG_EXT_CLK
+void EnableGpio5ClockReq(PADAPTER Adapter, u8 in_interrupt, u32 Enable)
+{
+	u32	value32;
+	HAL_DATA_TYPE	*pHalData;
+
+	pHalData = GET_HAL_DATA(Adapter);
+	if(IS_D_CUT(pHalData->VersionID))
+		return;
+
+	//dbgdump("%s Enable:%x time:%d", __RTL_FUNC__, Enable, rtw_get_current_time());
+
+	if(in_interrupt)
+		value32 = _sdio_read32(Adapter, REG_GPIO_PIN_CTRL);
+	else
+    		value32 = rtw_read32(Adapter, REG_GPIO_PIN_CTRL);
+
+	//open GPIO 5
+	if (Enable)
+		value32 |= BIT(13);//5+8
+	else
+		value32 &= ~BIT(13);
+
+	//GPIO 5 out put
+	value32 |= BIT(21);//5+16
+
+	//if (Enable)
+	//	rtw_write8(Adapter, REG_GPIO_PIN_CTRL + 1, 0x20);
+	//else
+	//	rtw_write8(Adapter, REG_GPIO_PIN_CTRL + 1, 0x00);
+
+	if(in_interrupt)
+		_sdio_write32(Adapter, REG_GPIO_PIN_CTRL, value32);
+	else
+		rtw_write32(Adapter, REG_GPIO_PIN_CTRL, value32);
+
+} //end of _rtl8192cs_disable_gpio()
+
+void _InitClockTo26MHz(
+	IN	PADAPTER Adapter
+	)
+{
+	u8 u1temp = 0;
+	HAL_DATA_TYPE	*pHalData;
+
+	pHalData = GET_HAL_DATA(Adapter);
+
+	if(IS_D_CUT(pHalData->VersionID)) {
+		//FW special init
+		u1temp =  rtw_read8(Adapter, REG_XCK_OUT_CTRL);
+		u1temp |= 0x18;
+		rtw_write8(Adapter, REG_XCK_OUT_CTRL, u1temp);
+		MSG_8192C("D cut version\n");
+	}
+
+	EnableGpio5ClockReq(Adapter, _FALSE, 1);
+
+	//0x2c[3:0] = 5 will set clock to 26MHz
+	u1temp = rtw_read8(Adapter, REG_APE_PLL_CTRL_EXT);
+	u1temp = (u1temp & 0xF0) | 0x05;
+	rtw_write8(Adapter, REG_APE_PLL_CTRL_EXT, u1temp);
+}
+#endif
+
+
+static void rtl8188es_interface_configure(PADAPTER padapter)
+{
+	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(padapter);
+	struct dvobj_priv		*pdvobjpriv = adapter_to_dvobj(padapter);
+	struct registry_priv	*pregistrypriv = &padapter->registrypriv;
+	BOOLEAN		bWiFiConfig	= pregistrypriv->wifi_spec;
+
+
+	pdvobjpriv->RtOutPipe[0] = WLAN_TX_HIQ_DEVICE_ID;
+	pdvobjpriv->RtOutPipe[1] = WLAN_TX_MIQ_DEVICE_ID;
+	pdvobjpriv->RtOutPipe[2] = WLAN_TX_LOQ_DEVICE_ID;
+
+	if (bWiFiConfig)
+		pHalData->OutEpNumber = 2;
+	else
+		pHalData->OutEpNumber = SDIO_MAX_TX_QUEUE;
+
+	switch(pHalData->OutEpNumber){
+		case 3:
+			pHalData->OutEpQueueSel=TX_SELE_HQ| TX_SELE_LQ|TX_SELE_NQ;
+			break;
+		case 2:
+			pHalData->OutEpQueueSel=TX_SELE_HQ| TX_SELE_NQ;
+			break;
+		case 1:
+			pHalData->OutEpQueueSel=TX_SELE_HQ;
+			break;
+		default:				
+			break;
+	}
+
+	Hal_MappingOutPipe(padapter, pHalData->OutEpNumber);
+}
+
+/*
+ * Description:
+ *	Call power on sequence to enable card
+ *
+ * Return:
+ *	_SUCCESS	enable success
+ *	_FAIL		enable fail
+ */
+static u8 _CardEnable(PADAPTER padapter)
+{
+	u8 bMacPwrCtrlOn;
+	u8 ret;
+
+	DBG_871X("=>%s\n", __FUNCTION__);
+
+	rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
+	if (bMacPwrCtrlOn == _FALSE)
+	{
+#ifdef CONFIG_PLATFORM_SPRD
+		u8 val8;
+#endif // CONFIG_PLATFORM_SPRD
+
+		// RSV_CTRL 0x1C[7:0] = 0x00
+		// unlock ISO/CLK/Power control register
+		rtw_write8(padapter, REG_RSV_CTRL, 0x0);
+
+#ifdef CONFIG_PLATFORM_SPRD
+#ifdef CONFIG_EXT_CLK
+		_InitClockTo26MHz(padapter);
+#endif //CONFIG_EXT_CLK
+
+		val8 =  rtw_read8(padapter, 0x4);
+		val8 = val8 & ~BIT(5);
+		rtw_write8(padapter, 0x4, val8);
+#endif // CONFIG_PLATFORM_SPRD
+
+		ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, Rtl8188E_NIC_ENABLE_FLOW);
+		if (ret == _SUCCESS) {
+			u8 bMacPwrCtrlOn = _TRUE;
+			rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
+		}
+		else
+		{
+			DBG_871X(KERN_ERR "%s: run power on flow fail\n", __func__);
+			return _FAIL;	
+		}
+		
+	} 
+	else
+	{
+		ret = _SUCCESS;
+	}
+
+	DBG_871X("<=%s\n", __FUNCTION__);
+
+	return ret;
+	
+}
+
+static u32 rtl8188es_InitPowerOn(PADAPTER padapter)
+{
+	u8 value8;
+	u16 value16;
+	u32 value32;
+	u8 ret;
+
+	DBG_871X("=>%s\n", __FUNCTION__);
+
+	ret = _CardEnable(padapter);
+	if (ret == _FAIL) {
+		return ret;
+	}
+
+/*
+	// Radio-Off Pin Trigger
+	value8 = rtw_read8(padapter, REG_GPIO_INTM+1);
+	value8 |= BIT(1); // Enable falling edge triggering interrupt
+	rtw_write8(padapter, REG_GPIO_INTM+1, value8);
+	value8 = rtw_read8(padapter, REG_GPIO_IO_SEL_2+1);
+	value8 |= BIT(1);
+	rtw_write8(padapter, REG_GPIO_IO_SEL_2+1, value8);
+*/
+
+	// Enable power down and GPIO interrupt
+	value16 = rtw_read16(padapter, REG_APS_FSMCO);
+	value16 |= EnPDN; // Enable HW power down and RF on
+	rtw_write16(padapter, REG_APS_FSMCO, value16);
+
+
+	// Enable MAC DMA/WMAC/SCHEDULE/SEC block
+	value16 = rtw_read16(padapter, REG_CR);
+	value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN
+				| PROTOCOL_EN | SCHEDULE_EN | ENSEC | CALTMR_EN);
+	// for SDIO - Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy. Added by tynli. 2011.08.31.
+	
+	rtw_write16(padapter, REG_CR, value16);
+
+
+
+	// Enable CMD53 R/W Operation
+//	bMacPwrCtrlOn = TRUE;
+//	rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, (pu8)(&bMacPwrCtrlOn));
+
+	DBG_871X("<=%s\n", __FUNCTION__);
+	
+	return _SUCCESS;
+	
+}
+
+static void _InitQueueReservedPage(PADAPTER padapter)
+{
+#ifdef RTL8188ES_MAC_LOOPBACK	
+
+//#define MAC_LOOPBACK_PAGE_NUM_PUBQ		0x26
+//#define MAC_LOOPBACK_PAGE_NUM_HPQ		0x0b
+//#define MAC_LOOPBACK_PAGE_NUM_LPQ		0x0b
+//#define MAC_LOOPBACK_PAGE_NUM_NPQ		0x0b // 71 pages=>9088 bytes, 8.875k
+
+	rtw_write16(padapter, REG_RQPN_NPQ, 0x0b0b);
+	rtw_write32(padapter, REG_RQPN, 0x80260b0b);
+	
+#else //TX_PAGE_BOUNDARY_LOOPBACK_MODE
+	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(padapter);
+	struct registry_priv	*pregistrypriv = &padapter->registrypriv;
+	u32			outEPNum	= (u32)pHalData->OutEpNumber;
+	u32			numHQ		= 0;
+	u32			numLQ		= 0;
+	u32			numNQ		= 0;
+	u32			numPubQ;
+	u32			value32;
+	u8			value8;
+	BOOLEAN			bWiFiConfig	= pregistrypriv->wifi_spec;
+
+	if(bWiFiConfig)
+	{
+		if (pHalData->OutEpQueueSel & TX_SELE_HQ)
+		{
+			numHQ =  0x29;
+		}
+
+		if (pHalData->OutEpQueueSel & TX_SELE_LQ)
+		{
+			numLQ = 0x1C;
+		}
+
+		// NOTE: This step shall be proceed before writting REG_RQPN.
+		if (pHalData->OutEpQueueSel & TX_SELE_NQ) {
+			numNQ = 0x1C;
+		}
+		value8 = (u8)_NPQ(numNQ);
+		rtw_write8(padapter, REG_RQPN_NPQ, value8);
+
+		numPubQ = 0xA9 - numHQ - numLQ - numNQ;
+
+		// TX DMA
+		value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
+		rtw_write32(padapter, REG_RQPN, value32);
+	}
+	else
+	{
+		rtw_write16(padapter, REG_RQPN_NPQ, 0x0000);
+		rtw_write32(padapter,REG_RQPN, 0x80a00900);
+	}
+#endif
+	return;	
+}
+
+static void _InitTxBufferBoundary(PADAPTER padapter, u8 txpktbuf_bndy)
+{
+	struct registry_priv *pregistrypriv = &padapter->registrypriv;
+	//HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+
+	//u16	txdmactrl;
+
+	rtw_write8(padapter, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
+	rtw_write8(padapter, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
+	rtw_write8(padapter, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy);
+	rtw_write8(padapter, REG_TRXFF_BNDY, txpktbuf_bndy);
+	rtw_write8(padapter, REG_TDECTRL+1, txpktbuf_bndy);
+
+}
+
+static VOID
+_InitNormalChipRegPriority(
+	IN	PADAPTER	Adapter,
+	IN	u16		beQ,
+	IN	u16		bkQ,
+	IN	u16		viQ,
+	IN	u16		voQ,
+	IN	u16		mgtQ,
+	IN	u16		hiQ
+	)
+{	
+	u16 value16	= (rtw_read16(Adapter, REG_TRXDMA_CTRL) & 0x7);
+
+	value16 |=	_TXDMA_BEQ_MAP(beQ) 	| _TXDMA_BKQ_MAP(bkQ) |
+				_TXDMA_VIQ_MAP(viQ) 	| _TXDMA_VOQ_MAP(voQ) |
+				_TXDMA_MGQ_MAP(mgtQ)| _TXDMA_HIQ_MAP(hiQ);
+
+	rtw_write16(Adapter, REG_TRXDMA_CTRL, value16);
+}
+
+static VOID
+_InitNormalChipOneOutEpPriority(
+	IN	PADAPTER Adapter
+	)
+{
+	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(Adapter);
+
+	u16	value = 0;
+	switch(pHalData->OutEpQueueSel)
+	{
+		case TX_SELE_HQ:
+			value = QUEUE_HIGH;
+			break;
+		case TX_SELE_LQ:
+			value = QUEUE_LOW;
+			break;
+		case TX_SELE_NQ:
+			value = QUEUE_NORMAL;
+			break;
+		default:
+			//RT_ASSERT(FALSE,("Shall not reach here!\n"));
+			break;
+	}
+
+	_InitNormalChipRegPriority(Adapter,
+								value,
+								value,
+								value,
+								value,
+								value,
+								value
+								);
+
+}
+
+static VOID
+_InitNormalChipTwoOutEpPriority(
+	IN	PADAPTER Adapter
+	)
+{
+	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(Adapter);
+	struct registry_priv *pregistrypriv = &Adapter->registrypriv;
+	u16			beQ,bkQ,viQ,voQ,mgtQ,hiQ;
+
+
+	u16	valueHi = 0;
+	u16	valueLow = 0;
+
+	switch(pHalData->OutEpQueueSel)
+	{
+		case (TX_SELE_HQ | TX_SELE_LQ):
+			valueHi = QUEUE_HIGH;
+			valueLow = QUEUE_LOW;
+			break;
+		case (TX_SELE_NQ | TX_SELE_LQ):
+			valueHi = QUEUE_NORMAL;
+			valueLow = QUEUE_LOW;
+			break;
+		case (TX_SELE_HQ | TX_SELE_NQ):
+			valueHi = QUEUE_HIGH;
+			valueLow = QUEUE_NORMAL;
+			break;
+		default:
+			//RT_ASSERT(FALSE,("Shall not reach here!\n"));
+			break;
+	}
+
+	if(!pregistrypriv->wifi_spec ){
+		beQ		= valueLow;
+		bkQ		= valueLow;
+		viQ		= valueHi;
+		voQ		= valueHi;
+		mgtQ	= valueHi;
+		hiQ		= valueHi;
+	}
+	else{//for WMM ,CONFIG_OUT_EP_WIFI_MODE
+		beQ		= valueLow;
+		bkQ		= valueHi;
+		viQ		= valueHi;
+		voQ		= valueLow;
+		mgtQ	= valueHi;
+		hiQ		= valueHi;
+	}
+
+	_InitNormalChipRegPriority(Adapter,beQ,bkQ,viQ,voQ,mgtQ,hiQ);
+
+}
+
+static VOID
+_InitNormalChipThreeOutEpPriority(
+	IN	PADAPTER padapter
+	)
+{
+	struct registry_priv *pregistrypriv = &padapter->registrypriv;
+	u16			beQ, bkQ, viQ, voQ, mgtQ, hiQ;
+
+	if (!pregistrypriv->wifi_spec){// typical setting
+		beQ		= QUEUE_LOW;
+		bkQ 		= QUEUE_LOW;
+		viQ 		= QUEUE_NORMAL;
+		voQ 		= QUEUE_HIGH;
+		mgtQ 	= QUEUE_HIGH;
+		hiQ 		= QUEUE_HIGH;
+	}
+	else {// for WMM
+		beQ		= QUEUE_LOW;
+		bkQ 		= QUEUE_NORMAL;
+		viQ 		= QUEUE_NORMAL;
+		voQ 		= QUEUE_HIGH;
+		mgtQ 	= QUEUE_HIGH;
+		hiQ 		= QUEUE_HIGH;
+	}
+	_InitNormalChipRegPriority(padapter,beQ,bkQ,viQ,voQ,mgtQ,hiQ);
+}
+
+static VOID
+_InitNormalChipQueuePriority(
+	IN	PADAPTER Adapter
+	)
+{
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+
+	switch(pHalData->OutEpNumber)
+	{
+		case 1:
+			_InitNormalChipOneOutEpPriority(Adapter);
+			break;
+		case 2:
+			_InitNormalChipTwoOutEpPriority(Adapter);
+			break;
+		case 3:
+			_InitNormalChipThreeOutEpPriority(Adapter);
+			break;
+		default:
+			//RT_ASSERT(FALSE,("Shall not reach here!\n"));
+			break;
+	}
+
+
+}
+
+
+static void _InitQueuePriority(PADAPTER padapter)
+{
+	_InitNormalChipQueuePriority(padapter);
+}
+
+static void _InitPageBoundary(PADAPTER padapter)
+{
+	// RX Page Boundary	
+	u16 rxff_bndy = MAX_RX_DMA_BUFFER_SIZE_88E-1;
+
+	rtw_write16(padapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
+
+}
+
+static void _InitTransferPageSize(PADAPTER padapter)
+{
+	// Tx page size is always 128.
+
+	u8 value8;
+	value8 = _PSRX(PBP_128) | _PSTX(PBP_128);
+	rtw_write8(padapter, REG_PBP, value8);	
+}
+
+void _InitDriverInfoSize(PADAPTER padapter, u8 drvInfoSize)
+{
+	rtw_write8(padapter, REG_RX_DRVINFO_SZ, drvInfoSize);
+}
+
+void _InitNetworkType(PADAPTER padapter)
+{
+	u32 value32;
+
+	value32 = rtw_read32(padapter, REG_CR);
+
+	// TODO: use the other function to set network type
+//	value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AD_HOC);
+	value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP);
+
+	rtw_write32(padapter, REG_CR, value32);
+}
+
+void _InitWMACSetting(PADAPTER padapter)
+{
+	u16 value16;
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+
+
+	//pHalData->ReceiveConfig = RCR_AAP | RCR_APM | RCR_AM | RCR_AB | RCR_CBSSID_DATA | RCR_CBSSID_BCN | RCR_AMF | RCR_HTC_LOC_CTRL | RCR_APP_PHYSTS | RCR_APP_ICV | RCR_APP_MIC;
+	// don't turn on AAP, it will allow all packets to driver
+	pHalData->ReceiveConfig = RCR_APM | RCR_AM | RCR_AB | RCR_CBSSID_DATA | RCR_CBSSID_BCN | RCR_AMF | RCR_HTC_LOC_CTRL | RCR_APP_PHYST_RXFF | RCR_APP_ICV | RCR_APP_MIC;
+
+	rtw_write32(padapter, REG_RCR, pHalData->ReceiveConfig);
+
+	// Accept all data frames
+	value16 = 0xFFFF;
+	rtw_write16(padapter, REG_RXFLTMAP2, value16);
+
+	// 2010.09.08 hpfan
+	// Since ADF is removed from RCR, ps-poll will not be indicate to driver,
+	// RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll.
+	value16 = 0x400;
+	rtw_write16(padapter, REG_RXFLTMAP1, value16);
+
+	// Accept all management frames
+	value16 = 0xFFFF;
+	rtw_write16(padapter, REG_RXFLTMAP0, value16);
+	
+}
+
+void _InitAdaptiveCtrl(PADAPTER padapter)
+{
+	u16	value16;
+	u32	value32;
+
+	// Response Rate Set
+	value32 = rtw_read32(padapter, REG_RRSR);
+	value32 &= ~RATE_BITMAP_ALL;
+	value32 |= RATE_RRSR_CCK_ONLY_1M;
+	rtw_write32(padapter, REG_RRSR, value32);
+
+	// CF-END Threshold
+	//m_spIoBase->rtw_write8(REG_CFEND_TH, 0x1);
+
+	// SIFS (used in NAV)
+	value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
+	rtw_write16(padapter, REG_SPEC_SIFS, value16);
+
+	// Retry Limit
+	value16 = _LRL(0x30) | _SRL(0x30);
+	rtw_write16(padapter, REG_RL, value16);
+}	
+
+void _InitEDCA(PADAPTER padapter)
+{
+	// Set Spec SIFS (used in NAV)
+	rtw_write16(padapter, REG_SPEC_SIFS, 0x100a);
+	rtw_write16(padapter, REG_MAC_SPEC_SIFS, 0x100a);
+
+	// Set SIFS for CCK
+	rtw_write16(padapter, REG_SIFS_CTX, 0x100a);
+
+	// Set SIFS for OFDM
+	rtw_write16(padapter, REG_SIFS_TRX, 0x100a);
+
+	// TXOP
+	rtw_write32(padapter, REG_EDCA_BE_PARAM, 0x005EA42B);
+	rtw_write32(padapter, REG_EDCA_BK_PARAM, 0x0000A44F);
+	rtw_write32(padapter, REG_EDCA_VI_PARAM, 0x005EA324);
+	rtw_write32(padapter, REG_EDCA_VO_PARAM, 0x002FA226);
+}
+
+void _InitRateFallback(PADAPTER padapter)
+{
+	// Set Data Auto Rate Fallback Retry Count register.
+	rtw_write32(padapter, REG_DARFRC, 0x00000000);
+	rtw_write32(padapter, REG_DARFRC+4, 0x10080404);
+	rtw_write32(padapter, REG_RARFRC, 0x04030201);
+	rtw_write32(padapter, REG_RARFRC+4, 0x08070605);
+
+}
+
+void _InitRetryFunction(PADAPTER padapter)
+{
+	u8	value8;
+
+	value8 = rtw_read8(padapter, REG_FWHW_TXQ_CTRL);
+	value8 |= EN_AMPDU_RTY_NEW;
+	rtw_write8(padapter, REG_FWHW_TXQ_CTRL, value8);
+
+	// Set ACK timeout
+	rtw_write8(padapter, REG_ACKTO, 0x40);
+}
+
+static void HalRxAggr8188ESdio(PADAPTER padapter)
+{
+#if 1
+	struct registry_priv *pregistrypriv;
+	u8	valueDMATimeout;
+	u8	valueDMAPageCount;
+
+
+	pregistrypriv = &padapter->registrypriv;
+
+	if (pregistrypriv->wifi_spec)
+	{
+		// 2010.04.27 hpfan
+		// Adjust RxAggrTimeout to close to zero disable RxAggr, suggested by designer
+		// Timeout value is calculated by 34 / (2^n)
+		valueDMATimeout = 0x0f;
+		valueDMAPageCount = 0x01;
+	}
+	else
+	{
+		valueDMATimeout = 0x06;
+		//valueDMAPageCount = 0x0F;
+		//valueDMATimeout = 0x0a;  
+		valueDMAPageCount = 0x24;
+	}
+
+	rtw_write8(padapter, REG_RXDMA_AGG_PG_TH+1, valueDMATimeout);
+	rtw_write8(padapter, REG_RXDMA_AGG_PG_TH, valueDMAPageCount);
+#endif
+}
+
+void sdio_AggSettingRxUpdate(PADAPTER padapter)
+{
+#if 1
+	//HAL_DATA_TYPE *pHalData;
+	u8 valueDMA;
+
+
+	//pHalData = GET_HAL_DATA(padapter);
+
+	valueDMA = rtw_read8(padapter, REG_TRXDMA_CTRL);
+	valueDMA |= RXDMA_AGG_EN;
+	rtw_write8(padapter, REG_TRXDMA_CTRL, valueDMA);
+
+#if 0
+	switch (RX_PAGE_SIZE_REG_VALUE)
+	{
+		case PBP_64:
+			pHalData->HwRxPageSize = 64;
+			break;
+		case PBP_128:
+			pHalData->HwRxPageSize = 128;
+			break;
+		case PBP_256:
+			pHalData->HwRxPageSize = 256;
+			break;
+		case PBP_512:
+			pHalData->HwRxPageSize = 512;
+			break;
+		case PBP_1024:
+			pHalData->HwRxPageSize = 1024;
+			break;
+		default:
+			RT_TRACE(_module_hci_hal_init_c_, _drv_err_,
+				("%s: RX_PAGE_SIZE_REG_VALUE definition is incorrect!\n", __FUNCTION__));
+			break;
+	}
+#endif
+#endif
+}
+
+void _initSdioAggregationSetting(PADAPTER padapter)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+
+	// Tx aggregation setting
+	//sdio_AggSettingTxUpdate(padapter);
+
+	// Rx aggregation setting
+	HalRxAggr8188ESdio(padapter);
+	sdio_AggSettingRxUpdate(padapter);
+
+	// 201/12/10 MH Add for USB agg mode dynamic switch.
+	pHalData->UsbRxHighSpeedMode = _FALSE;
+}
+
+
+void _InitOperationMode(PADAPTER padapter)
+{
+	PHAL_DATA_TYPE pHalData;
+	struct mlme_ext_priv *pmlmeext;
+	u8				regBwOpMode = 0;
+	u32				regRATR = 0, regRRSR = 0;
+	u8				MinSpaceCfg;
+
+
+	pHalData = GET_HAL_DATA(padapter);
+	pmlmeext = &padapter->mlmeextpriv;
+
+	//1 This part need to modified according to the rate set we filtered!!
+	//
+	// Set RRSR, RATR, and REG_BWOPMODE registers
+	//
+	switch(pmlmeext->cur_wireless_mode)
+	{
+		case WIRELESS_MODE_B:
+			regBwOpMode = BW_OPMODE_20MHZ;
+			regRATR = RATE_ALL_CCK;
+			regRRSR = RATE_ALL_CCK;
+			break;
+		case WIRELESS_MODE_A:
+//			RT_ASSERT(FALSE,("Error wireless a mode\n"));
+#if 0
+			regBwOpMode = BW_OPMODE_5G |BW_OPMODE_20MHZ;
+			regRATR = RATE_ALL_OFDM_AG;
+			regRRSR = RATE_ALL_OFDM_AG;
+#endif
+			break;
+		case WIRELESS_MODE_G:
+			regBwOpMode = BW_OPMODE_20MHZ;
+			regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
+			regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
+			break;
+		case WIRELESS_MODE_AUTO:
+#if 0
+			if (padapter->bInHctTest)
+			{
+				regBwOpMode = BW_OPMODE_20MHZ;
+				regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
+				regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
+			}
+			else
+#endif
+			{
+				regBwOpMode = BW_OPMODE_20MHZ;
+				regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
+				regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
+			}
+			break;
+		case WIRELESS_MODE_N_24G:
+			// It support CCK rate by default.
+			// CCK rate will be filtered out only when associated AP does not support it.
+			regBwOpMode = BW_OPMODE_20MHZ;
+			regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
+			regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
+			break;
+		case WIRELESS_MODE_N_5G:
+//			RT_ASSERT(FALSE,("Error wireless mode"));
+#if 0
+			regBwOpMode = BW_OPMODE_5G;
+			regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
+			regRRSR = RATE_ALL_OFDM_AG;
+#endif
+			break;
+
+		default: //for MacOSX compiler warning.
+			break;
+	}
+
+	rtw_write8(padapter, REG_BWOPMODE, regBwOpMode);
+
+	// For Min Spacing configuration.
+	switch(pHalData->rf_type)
+	{
+		case RF_1T2R:
+		case RF_1T1R:
+			RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Initializepadapter: RF_Type%s\n", (pHalData->rf_type==RF_1T1R? "(1T1R)":"(1T2R)")));
+//			padapter->MgntInfo.MinSpaceCfg = (MAX_MSS_DENSITY_1T<<3);
+			MinSpaceCfg = (MAX_MSS_DENSITY_1T << 3);
+			break;
+		case RF_2T2R:
+		case RF_2T2R_GREEN:
+			RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Initializepadapter:RF_Type(2T2R)\n"));
+//			padapter->MgntInfo.MinSpaceCfg = (MAX_MSS_DENSITY_2T<<3);
+			MinSpaceCfg = (MAX_MSS_DENSITY_2T << 3);
+			break;
+	}
+
+//	rtw_write8(padapter, REG_AMPDU_MIN_SPACE, padapter->MgntInfo.MinSpaceCfg);
+	rtw_write8(padapter, REG_AMPDU_MIN_SPACE, MinSpaceCfg);
+}
+
+
+void _InitBeaconParameters(PADAPTER padapter)
+{
+	PHAL_DATA_TYPE pHalData;
+
+
+	pHalData = GET_HAL_DATA(padapter);
+
+	rtw_write16(padapter, REG_BCN_CTRL, 0x1010);
+
+	// TODO: Remove these magic number
+	rtw_write16(padapter, REG_TBTT_PROHIBIT, 0x6404);// ms
+	rtw_write8(padapter, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME);//ms
+	rtw_write8(padapter, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME);
+
+	// Suggested by designer timchen. Change beacon AIFS to the largest number
+	// beacause test chip does not contension before sending beacon. by tynli. 2009.11.03
+	rtw_write16(padapter, REG_BCNTCFG, 0x660F);
+
+	
+	pHalData->RegBcnCtrlVal = rtw_read8(padapter, REG_BCN_CTRL);
+	pHalData->RegTxPause = rtw_read8(padapter, REG_TXPAUSE); 
+	pHalData->RegFwHwTxQCtrl = rtw_read8(padapter, REG_FWHW_TXQ_CTRL+2);
+	pHalData->RegReg542 = rtw_read8(padapter, REG_TBTT_PROHIBIT+2);
+	pHalData->RegCR_1 = rtw_read8(padapter, REG_CR+1);
+	
+}
+
+void _InitBeaconMaxError(PADAPTER padapter, BOOLEAN InfraMode)
+{
+#ifdef RTL8192CU_ADHOC_WORKAROUND_SETTING
+	rtw_write8(padapter, REG_BCN_MAX_ERR, 0xFF);
+#endif
+}
+
+void _InitInterrupt(PADAPTER padapter)
+{
+
+	//HISR write one to clear
+	rtw_write32(padapter, REG_HISR_88E, 0xFFFFFFFF);
+	
+	// HIMR - turn all off
+	rtw_write32(padapter, REG_HIMR_88E, 0);
+
+	//
+	// Initialize and enable SDIO Host Interrupt.
+	//
+	InitInterrupt8188ESdio(padapter);
+
+
+	//
+	// Initialize and enable system Host Interrupt.
+	//
+	//InitSysInterrupt8188ESdio(Adapter);//TODO:
+	
+	//
+	// Enable SDIO Host Interrupt.
+	//
+	//EnableInterrupt8188ESdio(padapter);//Move to sd_intf_start()/stop
+	
+}
+
+void _InitRDGSetting(PADAPTER padapter)
+{
+	rtw_write8(padapter, REG_RD_CTRL, 0xFF);
+	rtw_write16(padapter, REG_RD_NAV_NXT, 0x200);
+	rtw_write8(padapter, REG_RD_RESP_PKT_TH, 0x05);
+}
+
+
+static void _InitRxSetting(PADAPTER padapter)
+{
+	rtw_write32(padapter, REG_MACID, 0x87654321);
+	rtw_write32(padapter, 0x0700, 0x87654321);
+}
+
+
+static void _InitRFType(PADAPTER padapter)
+{
+	struct registry_priv *pregpriv = &padapter->registrypriv;
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+	//BOOLEAN is92CU = IS_92C_SERIAL(pHalData->VersionID);
+	BOOLEAN	 is2T2R = IS_2T2R(pHalData->VersionID);
+
+#if	DISABLE_BB_RF
+	pHalData->rf_chip	= RF_PSEUDO_11N;
+	return;
+#endif
+
+	pHalData->rf_chip	= RF_6052;
+
+	//if (_FALSE == is92CU) {
+	if(_FALSE == is2T2R){
+		pHalData->rf_type = RF_1T1R;
+		DBG_8192C("Set RF Chip ID to RF_6052 and RF type to 1T1R.\n");
+		return;
+	}
+
+	// TODO: Consider that EEPROM set 92CU to 1T1R later.
+	// Force to overwrite setting according to chip version. Ignore EEPROM setting.
+	//pHalData->RF_Type = is92CU ? RF_2T2R : RF_1T1R;
+	MSG_8192C("Set RF Chip ID to RF_6052 and RF type to %d.\n", pHalData->rf_type);
+}
+
+// Set CCK and OFDM Block "ON"
+static void _BBTurnOnBlock(PADAPTER padapter)
+{
+#if (DISABLE_BB_RF)
+	return;
+#endif
+
+	PHY_SetBBReg(padapter, rFPGA0_RFMOD, bCCKEn, 0x1);
+	PHY_SetBBReg(padapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
+}
+
+#if 0
+static void _InitAntenna_Selection(PADAPTER padapter)
+{
+	rtw_write8(padapter, REG_LEDCFG2, 0x82);
+}
+#endif
+
+static void _InitPABias(PADAPTER padapter)
+{
+	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(padapter);
+	u8			pa_setting;
+	BOOLEAN		is92C = IS_92C_SERIAL(pHalData->VersionID);
+
+	//FIXED PA current issue
+	//efuse_one_byte_read(padapter, 0x1FA, &pa_setting);
+	pa_setting = EFUSE_Read1Byte(padapter, 0x1FA);
+
+	//RT_TRACE(COMP_INIT, DBG_LOUD, ("_InitPABias 0x1FA 0x%x \n",pa_setting));
+
+	if(!(pa_setting & BIT0))
+	{
+		PHY_SetRFReg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0x0F406);
+		PHY_SetRFReg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0x4F406);
+		PHY_SetRFReg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0x8F406);
+		PHY_SetRFReg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0xCF406);
+		//RT_TRACE(COMP_INIT, DBG_LOUD, ("PA BIAS path A\n"));
+	}
+
+	if(!(pa_setting & BIT1) && is92C)
+	{
+		PHY_SetRFReg(padapter,RF_PATH_B, 0x15, 0x0FFFFF, 0x0F406);
+		PHY_SetRFReg(padapter,RF_PATH_B, 0x15, 0x0FFFFF, 0x4F406);
+		PHY_SetRFReg(padapter,RF_PATH_B, 0x15, 0x0FFFFF, 0x8F406);
+		PHY_SetRFReg(padapter,RF_PATH_B, 0x15, 0x0FFFFF, 0xCF406);
+		//RT_TRACE(COMP_INIT, DBG_LOUD, ("PA BIAS path B\n"));
+	}
+
+	if(!(pa_setting & BIT4))
+	{
+		pa_setting = rtw_read8(padapter, 0x16);
+		pa_setting &= 0x0F;
+		rtw_write8(padapter, 0x16, pa_setting | 0x80);
+		rtw_write8(padapter, 0x16, pa_setting | 0x90);
+	}
+}
+
+#if 0
+VOID
+_InitRDGSetting_8188E(
+	IN	PADAPTER Adapter
+	)
+{
+	PlatformEFIOWrite1Byte(Adapter,REG_RD_CTRL,0xFF);
+	PlatformEFIOWrite2Byte(Adapter, REG_RD_NAV_NXT, 0x200);
+	PlatformEFIOWrite1Byte(Adapter,REG_RD_RESP_PKT_TH,0x05);
+}
+#endif
+
+static u32 rtl8188es_hal_init(PADAPTER padapter)
+{
+	s32 ret;
+	u8	txpktbuf_bndy;
+	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(padapter);
+	struct pwrctrl_priv		*pwrctrlpriv = &padapter->pwrctrlpriv;
+	struct registry_priv	*pregistrypriv = &padapter->registrypriv;
+	u8 is92C = IS_92C_SERIAL(pHalData->VersionID);
+	rt_rf_power_state	eRfPowerStateToSet;
+	u8 value8;
+	u16 value16;
+
+	u32 init_start_time = rtw_get_current_time();
+
+#ifdef DBG_HAL_INIT_PROFILING
+	enum HAL_INIT_STAGES {
+		HAL_INIT_STAGES_BEGIN = 0,
+		HAL_INIT_STAGES_INIT_PW_ON,
+		HAL_INIT_STAGES_MISC01,
+		HAL_INIT_STAGES_DOWNLOAD_FW,
+		HAL_INIT_STAGES_MAC,
+		HAL_INIT_STAGES_BB,
+		HAL_INIT_STAGES_RF,	
+		HAL_INIT_STAGES_EFUSE_PATCH,
+		HAL_INIT_STAGES_INIT_LLTT,	
+		
+		HAL_INIT_STAGES_MISC02,
+		HAL_INIT_STAGES_TURN_ON_BLOCK,
+		HAL_INIT_STAGES_INIT_SECURITY,
+		HAL_INIT_STAGES_MISC11,
+		HAL_INIT_STAGES_INIT_HAL_DM,
+		//HAL_INIT_STAGES_RF_PS,
+		HAL_INIT_STAGES_IQK,
+		HAL_INIT_STAGES_PW_TRACK,
+		HAL_INIT_STAGES_LCK,
+		//HAL_INIT_STAGES_MISC21,
+		HAL_INIT_STAGES_INIT_PABIAS,		
+		//HAL_INIT_STAGES_ANTENNA_SEL,
+		HAL_INIT_STAGES_MISC31,
+		HAL_INIT_STAGES_END,
+		HAL_INIT_STAGES_NUM
+	};
+
+	char * hal_init_stages_str[] = {
+		"HAL_INIT_STAGES_BEGIN",
+		"HAL_INIT_STAGES_INIT_PW_ON",
+		"HAL_INIT_STAGES_MISC01",
+		"HAL_INIT_STAGES_DOWNLOAD_FW",		
+		"HAL_INIT_STAGES_MAC",		
+		"HAL_INIT_STAGES_BB",
+		"HAL_INIT_STAGES_RF",
+		"HAL_INIT_STAGES_EFUSE_PATCH",
+		"HAL_INIT_STAGES_INIT_LLTT",
+		"HAL_INIT_STAGES_MISC02",		
+		"HAL_INIT_STAGES_TURN_ON_BLOCK",
+		"HAL_INIT_STAGES_INIT_SECURITY",
+		"HAL_INIT_STAGES_MISC11",
+		"HAL_INIT_STAGES_INIT_HAL_DM",
+		//"HAL_INIT_STAGES_RF_PS",
+		"HAL_INIT_STAGES_IQK",
+		"HAL_INIT_STAGES_PW_TRACK",
+		"HAL_INIT_STAGES_LCK",
+		//"HAL_INIT_STAGES_MISC21",
+		"HAL_INIT_STAGES_INIT_PABIAS"
+		//"HAL_INIT_STAGES_ANTENNA_SEL",
+		"HAL_INIT_STAGES_MISC31",
+		"HAL_INIT_STAGES_END",
+	};	
+
+
+	int hal_init_profiling_i;
+	u32 hal_init_stages_timestamp[HAL_INIT_STAGES_NUM]; //used to record the time of each stage's starting point
+
+	for(hal_init_profiling_i=0;hal_init_profiling_i<HAL_INIT_STAGES_NUM;hal_init_profiling_i++)
+		hal_init_stages_timestamp[hal_init_profiling_i]=0;
+
+	#define HAL_INIT_PROFILE_TAG(stage) hal_init_stages_timestamp[(stage)]=rtw_get_current_time();
+#else
+	#define HAL_INIT_PROFILE_TAG(stage) do {} while(0)
+#endif //DBG_HAL_INIT_PROFILING
+
+	DBG_8192C("+rtl8188es_hal_init\n");
+
+HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BEGIN);
+	// Disable Interrupt first.
+//	rtw_hal_disable_interrupt(padapter);
+//	DisableInterrupt8188ESdio(padapter);
+	
+#ifdef CONFIG_WOWLAN
+	if(rtw_read8(padapter, REG_MCUFWDL)&BIT7 &&
+		(padapter->pwrctrlpriv.wowlan_wake_reason & FWDecisionDisconnect)) {
+		u8 reg_val=0;
+		DBG_8192C("+Reset Entry+\n");
+		rtw_write8(padapter, REG_MCUFWDL, 0x00);
+		_8051Reset88E(padapter);
+		//reset BB
+		reg_val = rtw_read8(padapter, REG_SYS_FUNC_EN);
+		reg_val &= ~(BIT(0) | BIT(1));
+		rtw_write8(padapter, REG_SYS_FUNC_EN, reg_val);
+		//reset RF
+		rtw_write8(padapter, REG_RF_CTRL, 0);
+		//reset TRX path
+		rtw_write16(padapter, REG_CR, 0);
+		//reset MAC, Digital Core
+		reg_val = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
+		reg_val &= ~(BIT(4) | BIT(7));
+		rtw_write8(padapter, REG_SYS_FUNC_EN+1, reg_val);
+		reg_val = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
+		reg_val |= BIT(4) | BIT(7);
+		rtw_write8(padapter, REG_SYS_FUNC_EN+1, reg_val);
+		DBG_8192C("-Reset Entry-\n");
+	}
+#endif //CONFIG_WOWLAN
+
+HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PW_ON);
+	ret = rtl8188es_InitPowerOn(padapter);
+	if (_FAIL == ret) {
+		RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init Power On!\n"));
+		goto exit;
+	}
+	
+	ret = PowerOnCheck(padapter);
+	if (_FAIL == ret ) {
+		DBG_871X("Power on Fail! do it again\n");
+		ret = rtl8188es_InitPowerOn(padapter);
+		if (_FAIL == ret) {
+			DBG_871X("Failed to init Power On!\n");
+			goto exit;
+		}
+	}
+	DBG_871X("Power on ok!\n");
+
+
+HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC01);
+	if (!pregistrypriv->wifi_spec) {
+		txpktbuf_bndy = TX_PAGE_BOUNDARY_88E;
+	} else {
+		// for WMM
+		txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY_88E;
+	}
+	_InitQueueReservedPage(padapter);	
+	_InitQueuePriority(padapter);
+	_InitPageBoundary(padapter);
+	_InitTransferPageSize(padapter);
+#ifdef CONFIG_IOL_IOREG_CFG
+	_InitTxBufferBoundary(padapter, 0);		
+#endif
+	//
+	// Configure SDIO TxRx Control to enable Rx DMA timer masking.
+	// 2010.02.24.
+	//
+	value8 = SdioLocalCmd52Read1Byte(padapter, SDIO_REG_TX_CTRL);
+	SdioLocalCmd52Write1Byte(padapter, SDIO_REG_TX_CTRL, 0x02);
+
+	rtw_write8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HRPWM1, 0);
+	
+HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_DOWNLOAD_FW);
+#if (MP_DRIVER == 1)
+	if (padapter->registrypriv.mp_mode == 1)
+	{
+		_InitRxSetting(padapter);
+	}
+#endif //MP_DRIVER == 1
+	{	
+#if 0
+	padapter->bFWReady = _FALSE; //because no fw for test chip	
+	pHalData->fw_ractrl = _FALSE;
+#else
+#ifdef CONFIG_WOWLAN
+	ret = rtl8188e_FirmwareDownload(padapter, _FALSE);
+#else
+	ret = rtl8188e_FirmwareDownload(padapter);
+#endif //CONFIG_WOWLAN
+
+	if (ret != _SUCCESS) {
+		DBG_871X("%s: Download Firmware failed!!\n", __FUNCTION__);
+		padapter->bFWReady = _FALSE;
+		pHalData->fw_ractrl = _FALSE;
+		goto exit;
+	} else {
+		RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Initializepadapter8192CSdio(): Download Firmware Success!!\n"));
+		padapter->bFWReady = _TRUE;
+		pHalData->fw_ractrl = _FALSE;
+	}
+#endif
+	}
+
+	rtl8188e_InitializeFirmwareVars(padapter);
+
+HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MAC);
+#if (HAL_MAC_ENABLE == 1)
+	ret = PHY_MACConfig8188E(padapter);
+	if(ret != _SUCCESS){
+//		RT_TRACE(COMP_INIT, DBG_LOUD, ("Initializepadapter8192CSdio(): Fail to configure MAC!!\n"));
+		goto exit;
+	}
+#endif
+
+HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BB);
+	//
+	//d. Initialize BB related configurations.
+	//
+#if (HAL_BB_ENABLE == 1)
+	ret = PHY_BBConfig8188E(padapter);
+	if(ret != _SUCCESS){
+//		RT_TRACE(COMP_INIT, DBG_SERIOUS, ("Initializepadapter8192CSdio(): Fail to configure BB!!\n"));
+		goto exit;
+	}
+#endif
+
+
+HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_RF);
+
+#if (HAL_RF_ENABLE == 1)
+	ret = PHY_RFConfig8188E(padapter);
+
+	if(ret != _SUCCESS){
+//		RT_TRACE(COMP_INIT, DBG_LOUD, ("Initializepadapter8192CSdio(): Fail to configure RF!!\n"));
+		goto exit;
+	}
+HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_EFUSE_PATCH);
+#if defined(CONFIG_IOL_EFUSE_PATCH)	
+	ret = rtl8188e_iol_efuse_patch(padapter);
+	if(ret != _SUCCESS){
+		DBG_871X("%s  rtl8188e_iol_efuse_patch failed \n",__FUNCTION__);
+		goto exit;
+	}
+#endif
+	_InitTxBufferBoundary(padapter, txpktbuf_bndy);
+HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_LLTT);
+	ret = InitLLTTable(padapter, txpktbuf_bndy);
+	if (_SUCCESS != ret) {
+		RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init LLT Table!\n"));
+		goto exit;
+	}
+
+#if (RATE_ADAPTIVE_SUPPORT==1)
+	{//Enable TX Report
+		//Enable Tx Report Timer   
+		value8 = rtw_read8(padapter, REG_TX_RPT_CTRL);
+		rtw_write8(padapter,  REG_TX_RPT_CTRL, (value8|BIT1|BIT0));
+		//Set MAX RPT MACID
+		rtw_write8(padapter,  REG_TX_RPT_CTRL+1, 2);//FOR sta mode ,0: bc/mc ,1:AP
+		//Tx RPT Timer. Unit: 32us
+		rtw_write16(padapter, REG_TX_RPT_TIME, 0xCdf0);
+	}
+#endif	
+
+#if 0
+	if(pHTInfo->bRDGEnable){
+		_InitRDGSetting_8188E(Adapter);
+	}
+#endif
+
+#ifdef CONFIG_TX_EARLY_MODE	
+	if( pHalData->bEarlyModeEnable)
+	{
+		RT_TRACE(_module_hci_hal_init_c_, _drv_info_,("EarlyMode Enabled!!!\n"));
+
+		value8 = rtw_read8(padapter, REG_EARLY_MODE_CONTROL);
+#if RTL8188E_EARLY_MODE_PKT_NUM_10 == 1
+		value8 = value8|0x1f;
+#else
+		value8 = value8|0xf;
+#endif
+		rtw_write8(padapter, REG_EARLY_MODE_CONTROL, value8);
+
+		rtw_write8(padapter, REG_EARLY_MODE_CONTROL+3, 0x80);
+
+		value8 = rtw_read8(padapter, REG_TCR+1);
+		value8 = value8|0x40;
+		rtw_write8(padapter,REG_TCR+1, value8);
+	}
+	else
+#endif
+	{
+		rtw_write8(padapter, REG_EARLY_MODE_CONTROL, 0);
+	}
+
+
+#if(SIC_ENABLE == 1)
+	SIC_Init(padapter);
+#endif
+
+
+	if (pwrctrlpriv->reg_rfoff == _TRUE) {
+		pwrctrlpriv->rf_pwrstate = rf_off;
+	}
+
+	// 2010/08/09 MH We need to check if we need to turnon or off RF after detecting
+	// HW GPIO pin. Before PHY_RFConfig8192C.
+	HalDetectPwrDownMode88E(padapter);
+
+
+	// Set RF type for BB/RF configuration
+	_InitRFType(padapter);
+
+	// Save target channel
+	// <Roger_Notes> Current Channel will be updated again later.
+	pHalData->CurrentChannel = 1;
+
+
+
+HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC02);
+	// Get Rx PHY status in order to report RSSI and others.
+	_InitDriverInfoSize(padapter, 4);
+	hal_init_macaddr(padapter);
+	_InitNetworkType(padapter);
+	_InitWMACSetting(padapter);
+	_InitAdaptiveCtrl(padapter);
+	_InitEDCA(padapter);
+	_InitRateFallback(padapter);
+	_InitRetryFunction(padapter);
+	_initSdioAggregationSetting(padapter);
+	_InitOperationMode(padapter);
+	_InitBeaconParameters(padapter);
+	_InitBeaconMaxError(padapter, _TRUE);
+	_InitInterrupt(padapter);
+	
+	// Enable MACTXEN/MACRXEN block
+	value16 = rtw_read16(padapter, REG_CR);
+	value16 |= (MACTXEN | MACRXEN);
+	rtw_write8(padapter, REG_CR, value16);
+
+#if defined(CONFIG_CONCURRENT_MODE) || defined(CONFIG_TX_MCAST2UNI)
+
+#ifdef CONFIG_CHECK_AC_LIFETIME
+	// Enable lifetime check for the four ACs
+	rtw_write8(padapter, REG_LIFETIME_EN, 0x0F);
+#endif	// CONFIG_CHECK_AC_LIFETIME
+
+#ifdef CONFIG_TX_MCAST2UNI
+	rtw_write16(padapter, REG_PKT_VO_VI_LIFE_TIME, 0x0400);	// unit: 256us. 256ms
+	rtw_write16(padapter, REG_PKT_BE_BK_LIFE_TIME, 0x0400);	// unit: 256us. 256ms
+#else	// CONFIG_TX_MCAST2UNI
+	rtw_write16(padapter, REG_PKT_VO_VI_LIFE_TIME, 0x3000);	// unit: 256us. 3s
+	rtw_write16(padapter, REG_PKT_BE_BK_LIFE_TIME, 0x3000);	// unit: 256us. 3s
+#endif	// CONFIG_TX_MCAST2UNI
+#endif	// CONFIG_CONCURRENT_MODE || CONFIG_TX_MCAST2UNI
+
+
+
+	
+#endif //HAL_RF_ENABLE == 1
+	
+
+HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_TURN_ON_BLOCK);
+	_BBTurnOnBlock(padapter);
+
+HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_SECURITY);
+#if 1
+	invalidate_cam_all(padapter);
+#else
+	CamResetAllEntry(padapter);
+	padapter->HalFunc.EnableHWSecCfgHandler(padapter);
+#endif
+
+HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC11);
+	// 2010/12/17 MH We need to set TX power according to EFUSE content at first.
+	PHY_SetTxPowerLevel8188E(padapter, pHalData->CurrentChannel);
+	// Record original value for template. This is arough data, we can only use the data
+	// for power adjust. The value can not be adjustde according to different power!!!
+//	pHalData->OriginalCckTxPwrIdx = pHalData->CurrentCckTxPwrIdx;
+//	pHalData->OriginalOfdm24GTxPwrIdx = pHalData->CurrentOfdm24GTxPwrIdx;
+
+// Move by Neo for USB SS to below setp
+//_RfPowerSave(padapter);
+#if 0 //ANTENNA_SELECTION_STATIC_SETTING
+#if 0
+	if (!IS_92C_SERIAL( pHalData->VersionID) && (pHalData->AntDivCfg!=0))
+#else
+	if (IS_1T1R( pHalData->VersionID) && (pHalData->AntDivCfg!=0))
+#endif
+	{ //for 88CU ,1T1R
+		_InitAntenna_Selection(padapter);
+	}
+#endif
+
+	//
+	// Disable BAR, suggested by Scott
+	// 2010.04.09 add by hpfan
+	//
+	rtw_write32(padapter, REG_BAR_MODE_CTRL, 0x0201ffff);
+
+	// HW SEQ CTRL
+	// set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM.
+	rtw_write8(padapter, REG_HWSEQ_CTRL, 0xFF);
+
+
+#ifdef RTL8188ES_MAC_LOOPBACK
+	value8 = rtw_read8(padapter, REG_SYS_FUNC_EN);
+	value8 &= ~(FEN_BBRSTB|FEN_BB_GLB_RSTn);
+	rtw_write8(padapter, REG_SYS_FUNC_EN, value8);//disable BB, CCK/OFDM
+
+	rtw_write8(padapter, REG_RD_CTRL, 0x0F);
+	rtw_write8(padapter, REG_RD_CTRL+1, 0xCF);
+	//rtw_write8(padapter, REG_TXPKTBUF_WMAC_LBK_BF_HD, 0x80);//to check _InitPageBoundary()
+	rtw_write32(padapter, REG_CR, 0x0b0202ff);//0x100[28:24]=0x01011, enable mac loopback, no HW Security Eng.
+#endif
+
+	
+HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_HAL_DM);
+	//	InitHalDm(padapter);
+	rtl8188e_InitHalDm(padapter);
+		
+
+#if (MP_DRIVER == 1)
+	if (padapter->registrypriv.mp_mode == 1)
+	{
+		padapter->mppriv.channel = pHalData->CurrentChannel;
+		MPT_InitializeAdapter(padapter, padapter->mppriv.channel);
+	}
+	else
+#endif //(MP_DRIVER == 1)
+	{
+	//
+	// 2010/08/11 MH Merge from 8192SE for Minicard init. We need to confirm current radio status
+	// and then decide to enable RF or not.!!!??? For Selective suspend mode. We may not
+	// call init_adapter. May cause some problem??
+	//
+	// Fix the bug that Hw/Sw radio off before S3/S4, the RF off action will not be executed
+	// in MgntActSet_RF_State() after wake up, because the value of pHalData->eRFPowerState
+	// is the same as eRfOff, we should change it to eRfOn after we config RF parameters.
+	// Added by tynli. 2010.03.30.
+	pwrctrlpriv->rf_pwrstate = rf_on;
+	RT_CLEAR_PS_LEVEL(pwrctrlpriv, RT_RF_OFF_LEVL_HALT_NIC);
+
+	// 20100326 Joseph: Copy from GPIOChangeRFWorkItemCallBack() function to check HW radio on/off.
+	// 20100329 Joseph: Revise and integrate the HW/SW radio off code in initialization.
+//	pHalData->bHwRadioOff = _FALSE;
+	pwrctrlpriv->b_hw_radio_off = _FALSE;
+	eRfPowerStateToSet = rf_on;
+
+	// 2010/-8/09 MH For power down module, we need to enable register block contrl reg at 0x1c.
+	// Then enable power down control bit of register 0x04 BIT4 and BIT15 as 1.
+	if(pHalData->pwrdown && eRfPowerStateToSet == rf_off)
+	{
+		// Enable register area 0x0-0xc.
+		rtw_write8(padapter, REG_RSV_CTRL, 0x0);
+
+		//
+		// <Roger_Notes> We should configure HW PDn source for WiFi ONLY, and then
+		// our HW will be set in power-down mode if PDn source from all  functions are configured.
+		// 2010.10.06.
+		//
+		if(IS_HARDWARE_TYPE_8723AS(padapter))
+		{
+			value8 = rtw_read8(padapter, REG_MULTI_FUNC_CTRL);
+			rtw_write8(padapter, REG_MULTI_FUNC_CTRL, (value8|WL_HWPDN_EN));
+		}
+		else
+		{
+			rtw_write16(padapter, REG_APS_FSMCO, 0x8812);
+		}
+	}
+	//DrvIFIndicateCurrentPhyStatus(padapter); // 2010/08/17 MH Disable to prevent BSOD.
+
+	// 2010/08/26 MH Merge from 8192CE.
+	if(pwrctrlpriv->rf_pwrstate == rf_on)
+	{
+	
+HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_IQK);
+		if(pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized){
+//			PHY_IQCalibrate(padapter, _TRUE);
+			PHY_IQCalibrate_8188E(padapter,_TRUE);
+		}
+		else
+		{
+//			PHY_IQCalibrate(padapter, _FALSE);
+			PHY_IQCalibrate_8188E(padapter,_FALSE);
+			pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized = _TRUE;
+		}
+
+//		dm_CheckTXPowerTracking(padapter);
+//		PHY_LCCalibrate(padapter);
+
+HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_PW_TRACK);
+		ODM_TXPowerTrackingCheck(&pHalData->odmpriv );
+
+HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_LCK);
+		PHY_LCCalibrate_8188E(padapter);
+
+		
+	}
+}
+
+HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PABIAS);
+	//if(pHalData->eRFPowerState == eRfOn)
+	{
+		_InitPABias(padapter);
+	}
+
+	// Init BT hw config.
+//	HALBT_InitHwConfig(padapter);
+
+
+HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC31);
+	// 2010/05/20 MH We need to init timer after update setting. Otherwise, we can not get correct inf setting.
+	// 2010/05/18 MH For SE series only now. Init GPIO detect time
+#if 0
+	if(pDevice->RegUsbSS)
+	{
+		RT_TRACE(COMP_INIT, DBG_LOUD, (" call GpioDetectTimerStart\n"));
+		GpioDetectTimerStart(padapter);	// Disable temporarily
+	}
+#endif
+
+	// 2010/08/23 MH According to Alfred's suggestion, we need to to prevent HW enter
+	// suspend mode automatically.
+	//HwSuspendModeEnable92Cu(padapter, FALSE);
+
+	// 2010/12/17 MH For TX power level OID modification from UI.
+//	padapter->HalFunc.GetTxPowerLevelHandler( padapter, &pHalData->DefaultTxPwrDbm );
+	//DbgPrint("pHalData->DefaultTxPwrDbm = %d\n", pHalData->DefaultTxPwrDbm);
+
+//	if(pHalData->SwBeaconType < HAL92CSDIO_DEFAULT_BEACON_TYPE) // The lowest Beacon Type that HW can support
+//		pHalData->SwBeaconType = HAL92CSDIO_DEFAULT_BEACON_TYPE;
+
+	//
+	// Update current Tx FIFO page status.
+	//
+	HalQueryTxBufferStatus8189ESdio(padapter);
+
+
+	if(pregistrypriv->wifi_spec)
+		rtw_write16(padapter,REG_FAST_EDCA_CTRL ,0);
+
+
+	//TODO:Setting HW_VAR_NAV_UPPER !!!!!!!!!!!!!!!!!!!!
+	//rtw_hal_set_hwreg(Adapter, HW_VAR_NAV_UPPER, ((pu1Byte)&NavUpper));
+
+	if(IS_HARDWARE_TYPE_8188ES(padapter))
+	{
+		value8= rtw_read8(padapter, 0x4d3);
+		rtw_write8(padapter, 0x4d3, (value8|0x1));		
+	}
+
+	//pHalData->PreRpwmVal = PlatformEFSdioLocalCmd52Read1Byte(Adapter, SDIO_REG_HRPWM1)&0x80;
+
+
+	// enable Tx report.
+	rtw_write8(padapter,  REG_FWHW_TXQ_CTRL+1, 0x0F);
+/*
+	// Suggested by SD1 pisa. Added by tynli. 2011.10.21.
+	PlatformEFIOWrite1Byte(Adapter, REG_EARLY_MODE_CONTROL+3, 0x01);
+
+*/	//tynli_test_tx_report.
+	rtw_write16(padapter, REG_TX_RPT_TIME, 0x3DF0);
+	//RT_TRACE(COMP_INIT, DBG_TRACE, ("InitializeAdapter8188EUsb() <====\n"));
+
+	
+	//enable tx DMA to drop the redundate data of packet
+	rtw_write16(padapter,REG_TXDMA_OFFSET_CHK, (rtw_read16(padapter,REG_TXDMA_OFFSET_CHK) | DROP_DATA_EN));
+
+//#debug print for checking compile flags
+	//DBG_8192C("RTL8188E_FPGA_TRUE_PHY_VERIFICATION=%d\n", RTL8188E_FPGA_TRUE_PHY_VERIFICATION);
+	DBG_8192C("DISABLE_BB_RF=%d\n", DISABLE_BB_RF);	
+	DBG_8192C("IS_HARDWARE_TYPE_8188ES=%d\n", IS_HARDWARE_TYPE_8188ES(padapter));
+//#
+
+#ifdef CONFIG_PLATFORM_SPRD
+	// For Power Consumption, set all GPIO pin to ouput mode
+	//0x44~0x47 (GPIO 0~7), Note:GPIO5 is enabled for controlling external 26MHz request
+	rtw_write8(padapter, GPIO_IO_SEL, 0xFF);//Reg0x46, set to o/p mode
+
+       //0x42~0x43 (GPIO 8~11)
+	value8 = rtw_read8(padapter, REG_GPIO_IO_SEL);
+	rtw_write8(padapter, REG_GPIO_IO_SEL, (value8<<4)|value8);
+	value8 = rtw_read8(padapter, REG_GPIO_IO_SEL+1);
+	rtw_write8(padapter, REG_GPIO_IO_SEL+1, value8|0x0F);//Reg0x43
+#endif //CONFIG_PLATFORM_SPRD
+
+
+#ifdef CONFIG_XMIT_ACK
+	//ack for xmit mgmt frames.
+	rtw_write32(padapter, REG_FWHW_TXQ_CTRL, rtw_read32(padapter, REG_FWHW_TXQ_CTRL)|BIT(12));
+#endif //CONFIG_XMIT_ACK
+
+
+
+	//RT_TRACE(COMP_INIT, DBG_LOUD, ("<---Initializepadapter8192CSdio()\n"));
+	DBG_8192C("-rtl8188es_hal_init\n");
+
+exit:
+HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_END);
+
+	DBG_871X("%s in %dms\n", __FUNCTION__, rtw_get_passing_time_ms(init_start_time));
+
+	#ifdef DBG_HAL_INIT_PROFILING
+	hal_init_stages_timestamp[HAL_INIT_STAGES_END]=rtw_get_current_time();
+
+	for(hal_init_profiling_i=0;hal_init_profiling_i<HAL_INIT_STAGES_NUM-1;hal_init_profiling_i++) {
+		DBG_871X("DBG_HAL_INIT_PROFILING: %35s, %u, %5u, %5u\n"
+			, hal_init_stages_str[hal_init_profiling_i]
+			, hal_init_stages_timestamp[hal_init_profiling_i]
+			, (hal_init_stages_timestamp[hal_init_profiling_i+1]-hal_init_stages_timestamp[hal_init_profiling_i])
+			, rtw_get_time_interval_ms(hal_init_stages_timestamp[hal_init_profiling_i], hal_init_stages_timestamp[hal_init_profiling_i+1])
+		);
+	}	
+	#endif
+
+	return ret;
+	
+}
+
+static void CardDisableRTL8188ESdio(PADAPTER padapter)
+{
+	u8		u1bTmp;
+	u16		u2bTmp;
+	u32		u4bTmp;
+	u8		bMacPwrCtrlOn;
+	u8		ret;
+#ifdef CONFIG_PLATFORM_SPRD
+	struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
+#endif //CONFIG_PLATFORM_SPRD	
+
+	DBG_871X("=>%s\n", __FUNCTION__);
+
+
+	//Stop Tx Report Timer. 0x4EC[Bit1]=b'0
+	u1bTmp = rtw_read8(padapter, REG_TX_RPT_CTRL);
+	rtw_write8(padapter, REG_TX_RPT_CTRL, u1bTmp&(~BIT1));
+	
+	// stop rx 
+	rtw_write8(padapter,REG_CR, 0x0);
+
+
+#ifdef CONFIG_EXT_CLK //for sprd For Power Consumption.
+	EnableGpio5ClockReq(padapter, _FALSE, 0);	
+#endif //CONFIG_EXT_CLK
+
+#if 1
+	// For Power Consumption.
+	u1bTmp = rtw_read8(padapter, GPIO_IN);
+	rtw_write8(padapter, GPIO_OUT, u1bTmp);
+	rtw_write8(padapter, GPIO_IO_SEL, 0xFF);//Reg0x46
+
+	u1bTmp = rtw_read8(padapter, REG_GPIO_IO_SEL);
+	rtw_write8(padapter, REG_GPIO_IO_SEL, (u1bTmp<<4)|u1bTmp);
+	u1bTmp = rtw_read8(padapter, REG_GPIO_IO_SEL+1);
+	rtw_write8(padapter, REG_GPIO_IO_SEL+1, u1bTmp|0x0F);//Reg0x43
+#endif
+
+
+	// Run LPS WL RFOFF flow	
+	ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, Rtl8188E_NIC_LPS_ENTER_FLOW);
+	if (ret == _FALSE) {
+		DBG_871X("%s: run RF OFF flow fail!\n", __func__);
+	}
+
+	//	==== Reset digital sequence   ======
+
+	u1bTmp = rtw_read8(padapter, REG_MCUFWDL);
+	if ((u1bTmp & RAM_DL_SEL) && padapter->bFWReady) //8051 RAM code
+	{
+		//rtl8723a_FirmwareSelfReset(padapter);
+		//_8051Reset88E(padapter);		
+		
+		// Reset MCU 0x2[10]=0.
+		u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
+		u1bTmp &= ~BIT(2);	// 0x2[10], FEN_CPUEN
+		rtw_write8(padapter, REG_SYS_FUNC_EN+1, u1bTmp);
+	}	
+
+	//u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
+	//u1bTmp &= ~BIT(2);	// 0x2[10], FEN_CPUEN
+	//rtw_write8(padapter, REG_SYS_FUNC_EN+1, u1bTmp);
+
+	// MCUFWDL 0x80[1:0]=0
+	// reset MCU ready status
+	rtw_write8(padapter, REG_MCUFWDL, 0);
+
+	//==== Reset digital sequence end ======
+	
+
+	bMacPwrCtrlOn = _FALSE;	// Disable CMD53 R/W
+	rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
+
+
+/*
+	if((pMgntInfo->RfOffReason & RF_CHANGE_BY_HW) && pHalData->pwrdown)
+	{// Power Down
+		
+		// Card disable power action flow
+		ret = HalPwrSeqCmdParsing(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, Rtl8188E_NIC_PDN_FLOW);	
+	}	
+	else
+*/	
+#ifdef CONFIG_PLATFORM_SPRD
+       // for sprd, it will enable power down mode when enter suspend and remove driver, so needn't call card disable flow.
+       //if(pwrpriv->bInSuspend != _TRUE)
+	if(pwrpriv->bpower_saving == _TRUE) // when  bpower_saving == _TRUE at this moment is only indicate driver is going to IPS Mode. 	
+#endif //CONFIG_PLATFORM_SPRD
+	{ // Non-Power Down
+
+		// Card disable power action flow
+		ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, Rtl8188E_NIC_DISABLE_FLOW);
+
+		 
+		if (ret == _FALSE) {
+			DBG_871X("%s: run CARD DISABLE flow fail!\n", __func__);
+		}
+	}
+
+
+/*
+	// Reset MCU IO Wrapper, added by Roger, 2011.08.30
+	u1bTmp = rtw_read8(padapter, REG_RSV_CTRL+1);
+	u1bTmp &= ~BIT(0);
+	rtw_write8(padapter, REG_RSV_CTRL+1, u1bTmp);
+	u1bTmp = rtw_read8(padapter, REG_RSV_CTRL+1);
+	u1bTmp |= BIT(0);
+	rtw_write8(padapter, REG_RSV_CTRL+1, u1bTmp);
+*/
+
+
+	// RSV_CTRL 0x1C[7:0]=0x0E
+	// lock ISO/CLK/Power control register
+	rtw_write8(padapter, REG_RSV_CTRL, 0x0E);
+
+	padapter->bFWReady = _FALSE;
+	DBG_871X("<=%s\n", __FUNCTION__);
+
+}
+
+static u32 rtl8188es_hal_deinit(PADAPTER padapter)
+{
+	DBG_871X("=>%s\n", __FUNCTION__);
+
+	if (padapter->hw_init_completed == _TRUE)
+		CardDisableRTL8188ESdio(padapter);
+	
+	DBG_871X("<=%s\n", __FUNCTION__);
+
+	return _SUCCESS;
+}
+
+static u32 rtl8188es_inirp_init(PADAPTER padapter)
+{
+	u32 status;
+
+_func_enter_;
+
+	status = _SUCCESS;
+
+_func_exit_;
+
+	return status;
+}
+
+static u32 rtl8188es_inirp_deinit(PADAPTER padapter)
+{
+	RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("+rtl8188es_inirp_deinit\n"));
+
+	RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("-rtl8188es_inirp_deinit\n"));
+
+	return _SUCCESS;
+}
+
+static void rtl8188es_init_default_value(PADAPTER padapter)
+{
+	PHAL_DATA_TYPE pHalData;
+	struct pwrctrl_priv *pwrctrlpriv;
+	struct dm_priv *pdmpriv;
+	u8 i;
+
+	pHalData = GET_HAL_DATA(padapter);
+	pwrctrlpriv = &padapter->pwrctrlpriv;
+	pdmpriv = &pHalData->dmpriv;
+
+
+	//init default value
+	pHalData->fw_ractrl = _FALSE;		
+	if(!pwrctrlpriv->bkeepfwalive)
+		pHalData->LastHMEBoxNum = 0;	
+
+	//init dm default value
+	pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized = _FALSE;
+	pHalData->odmpriv.RFCalibrateInfo.TM_Trigger = 0;//for IQK
+	//pdmpriv->binitialized = _FALSE;
+//	pdmpriv->prv_traffic_idx = 3;
+//	pdmpriv->initialize = 0;
+	pHalData->pwrGroupCnt = 0;
+	pHalData->PGMaxGroup= 13;
+	pHalData->odmpriv.RFCalibrateInfo.ThermalValue_HP_index = 0;
+	for(i = 0; i < HP_THERMAL_NUM; i++)
+		pHalData->odmpriv.RFCalibrateInfo.ThermalValue_HP[i] = 0;
+
+	// interface related variable
+	pHalData->SdioRxFIFOCnt = 0;
+}
+
+//
+//	Description:
+//		We should set Efuse cell selection to WiFi cell in default.
+//
+//	Assumption:
+//		PASSIVE_LEVEL
+//
+//	Added by Roger, 2010.11.23.
+//
+static void _EfuseCellSel(
+	IN	PADAPTER	padapter
+	)
+{
+	//HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+
+	u32			value32;
+
+	//if(INCLUDE_MULTI_FUNC_BT(padapter))
+	{
+		value32 = rtw_read32(padapter, EFUSE_TEST);
+		value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
+		rtw_write32(padapter, EFUSE_TEST, value32);
+	}
+}
+
+static VOID
+_ReadRFType(
+	IN	PADAPTER	Adapter
+	)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
+
+#if DISABLE_BB_RF
+	pHalData->rf_chip = RF_PSEUDO_11N;
+#else
+	pHalData->rf_chip = RF_6052;
+#endif
+}
+
+static void
+Hal_EfuseParsePIDVID_8188ES(
+	IN	PADAPTER		pAdapter,
+	IN	u8*			hwinfo,
+	IN	BOOLEAN			AutoLoadFail
+	)
+{
+//	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
+
+	//
+	// <Roger_Notes> The PID/VID info was parsed from CISTPL_MANFID Tuple in CIS area before.
+	// VID is parsed from Manufacture code field and PID is parsed from Manufacture information field.
+	// 2011.04.01.
+	//
+
+//	RT_TRACE(COMP_INIT, DBG_LOUD, ("EEPROM VID = 0x%4x\n", pHalData->EEPROMVID));
+//	RT_TRACE(COMP_INIT, DBG_LOUD, ("EEPROM PID = 0x%4x\n", pHalData->EEPROMPID));
+}
+
+static void
+Hal_EfuseParseMACAddr_8188ES(
+	IN	PADAPTER		padapter,
+	IN	u8*			hwinfo,
+	IN	BOOLEAN			AutoLoadFail
+	)
+{
+	u16			i, usValue;
+	u8			sMacAddr[6] = {0x00, 0xE0, 0x4C, 0x81, 0x88, 0x77};
+	EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
+
+	if (AutoLoadFail)
+	{
+//		sMacAddr[5] = (u1Byte)GetRandomNumber(1, 254);
+		for (i=0; i<6; i++)
+			pEEPROM->mac_addr[i] = sMacAddr[i];
+	}
+	else
+	{
+		//Read Permanent MAC address
+		_rtw_memcpy(pEEPROM->mac_addr, &hwinfo[EEPROM_MAC_ADDR_88ES], ETH_ALEN);
+
+	}
+//	NicIFSetMacAddress(pAdapter, pAdapter->PermanentAddress);
+
+	DBG_871X("Hal_EfuseParseMACAddr_8188ES: Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n",
+		  pEEPROM->mac_addr[0], pEEPROM->mac_addr[1],
+		  pEEPROM->mac_addr[2], pEEPROM->mac_addr[3],
+		  pEEPROM->mac_addr[4], pEEPROM->mac_addr[5]);
+}
+
+
+#ifdef CONFIG_EFUSE_CONFIG_FILE
+static u32 Hal_readPGDataFromConfigFile(
+	PADAPTER	padapter)
+{
+	u32 i;
+	struct file *fp;
+	mm_segment_t fs;
+	u8 temp[3];
+	loff_t pos = 0;
+	EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
+	u8	*PROMContent = pEEPROM->efuse_eeprom_data;
+
+
+	temp[2] = 0; // add end of string '\0'
+
+	fp = filp_open("/system/etc/wifi/wifi_efuse.map", O_RDWR,  0644);
+	if (IS_ERR(fp)) {
+		pEEPROM->bloadfile_fail_flag = _TRUE;
+		DBG_871X("Error, Efuse configure file doesn't exist.\n");
+		return _FAIL;
+	}
+
+	fs = get_fs();
+	set_fs(KERNEL_DS);
+
+	DBG_871X("Efuse configure file:\n");
+	for (i=0; i<HWSET_MAX_SIZE_88E; i++) {
+		vfs_read(fp, temp, 2, &pos);
+		PROMContent[i] = simple_strtoul(temp, NULL, 16 );
+		pos += 1; // Filter the space character
+		DBG_871X("%02X \n", PROMContent[i]);
+	}
+	DBG_871X("\n");
+	set_fs(fs);
+
+	filp_close(fp, NULL);
+	pEEPROM->bloadfile_fail_flag = _FALSE;
+	return _SUCCESS;
+}
+
+static void
+Hal_ReadMACAddrFromFile_8188ES(
+	PADAPTER		padapter
+	)
+{
+	u32 i;
+	struct file *fp;
+	mm_segment_t fs;
+	u8 source_addr[18];
+	loff_t pos = 0;
+	u32	curtime = rtw_get_current_time();
+	EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
+	u8 *head, *end;
+
+	u8 null_mac_addr[ETH_ALEN] = {0, 0, 0,0, 0, 0};
+	u8 multi_mac_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+
+	_rtw_memset(source_addr, 0, 18);
+	_rtw_memset(pEEPROM->mac_addr, 0, ETH_ALEN);
+
+	fp = filp_open("/data/wifimac.txt", O_RDWR,  0644);
+	if (IS_ERR(fp)) {
+		pEEPROM->bloadmac_fail_flag = _TRUE;
+		DBG_871X("Error, wifi mac address file doesn't exist.\n");
+	} else {
+		fs = get_fs();
+		set_fs(KERNEL_DS);
+
+		DBG_871X("wifi mac address:\n");
+		vfs_read(fp, source_addr, 18, &pos);
+		source_addr[17] = ':';
+
+		head = end = source_addr;
+		for (i=0; i<ETH_ALEN; i++) {
+			while (end && (*end != ':') )
+				end++;
+
+			if (end && (*end == ':') )
+				*end = '\0';
+
+			pEEPROM->mac_addr[i] = simple_strtoul(head, NULL, 16 );
+
+			if (end) {
+				end++;
+				head = end;
+			}
+			DBG_871X("%02x \n", pEEPROM->mac_addr[i]);
+		}
+		DBG_871X("\n");
+		set_fs(fs);
+		pEEPROM->bloadmac_fail_flag = _FALSE;
+		filp_close(fp, NULL);
+	}
+
+	if ( (_rtw_memcmp(pEEPROM->mac_addr, null_mac_addr, ETH_ALEN)) ||
+		(_rtw_memcmp(pEEPROM->mac_addr, multi_mac_addr, ETH_ALEN)) ) {
+		pEEPROM->mac_addr[0] = 0x00;
+		pEEPROM->mac_addr[1] = 0xe0;
+		pEEPROM->mac_addr[2] = 0x4c;
+		pEEPROM->mac_addr[3] = (u8)(curtime & 0xff) ;
+		pEEPROM->mac_addr[4] = (u8)((curtime>>8) & 0xff) ;
+		pEEPROM->mac_addr[5] = (u8)((curtime>>16) & 0xff) ;
+	}
+
+	DBG_871X("Hal_ReadMACAddrFromFile_8188ES: Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n",
+		  pEEPROM->mac_addr[0], pEEPROM->mac_addr[1],
+		  pEEPROM->mac_addr[2], pEEPROM->mac_addr[3],
+		  pEEPROM->mac_addr[4], pEEPROM->mac_addr[5]);
+}
+#endif //CONFIG_EFUSE_CONFIG_FILE
+
+static VOID
+readAdapterInfo_8188ES(
+	IN PADAPTER			padapter
+	)
+{
+	EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
+
+	/* parse the eeprom/efuse content */
+	Hal_EfuseParseIDCode88E(padapter, pEEPROM->efuse_eeprom_data);
+	Hal_EfuseParsePIDVID_8188ES(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
+	
+#ifdef CONFIG_EFUSE_CONFIG_FILE
+	Hal_ReadMACAddrFromFile_8188ES(padapter);
+#else //CONFIG_EFUSE_CONFIG_FILE
+	Hal_EfuseParseMACAddr_8188ES(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
+#endif //CONFIG_EFUSE_CONFIG_FILE
+	
+	Hal_ReadPowerSavingMode88E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
+	Hal_ReadTxPowerInfo88E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
+	Hal_EfuseParseEEPROMVer88E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
+	rtl8188e_EfuseParseChnlPlan(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
+	Hal_EfuseParseXtal_8188E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
+	Hal_EfuseParseCustomerID88E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
+	//Hal_ReadAntennaDiversity88E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
+	Hal_EfuseParseBoardType88E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
+	Hal_ReadThermalMeter_88E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
+	//
+	// The following part initialize some vars by PG info.
+	//
+	Hal_InitChannelPlan(padapter);
+#ifdef CONFIG_WOWLAN
+	Hal_DetectWoWMode(padapter);
+#endif	//CONFIG_WOWLAN
+#ifdef CONFIG_RF_GAIN_OFFSET
+	Hal_ReadRFGainOffset(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
+#endif	//CONFIG_RF_GAIN_OFFSET
+}
+
+static void _ReadPROMContent(
+	IN PADAPTER 		padapter
+	)
+{
+	EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
+	u8			eeValue;
+
+	/* check system boot selection */
+	eeValue = rtw_read8(padapter, REG_9346CR);
+	pEEPROM->EepromOrEfuse = (eeValue & BOOT_FROM_EEPROM) ? _TRUE : _FALSE;
+	pEEPROM->bautoload_fail_flag = (eeValue & EEPROM_EN) ? _FALSE : _TRUE;
+
+	DBG_871X("%s: 9346CR=0x%02X, Boot from %s, Autoload %s\n",
+		  __FUNCTION__, eeValue,
+		  (pEEPROM->EepromOrEfuse ? "EEPROM" : "EFUSE"),
+		  (pEEPROM->bautoload_fail_flag ? "Fail" : "OK"));
+
+//	pHalData->EEType = IS_BOOT_FROM_EEPROM(Adapter) ? EEPROM_93C46 : EEPROM_BOOT_EFUSE;
+
+#ifdef CONFIG_EFUSE_CONFIG_FILE
+	Hal_readPGDataFromConfigFile(padapter);
+#else //CONFIG_EFUSE_CONFIG_FILE
+	Hal_InitPGData88E(padapter);
+#endif //CONFIG_EFUSE_CONFIG_FILE	
+	readAdapterInfo_8188ES(padapter);
+}
+
+static VOID
+_InitOtherVariable(
+	IN PADAPTER 		Adapter
+	)
+{
+	//HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
+
+
+	//if(Adapter->bInHctTest){
+	//	pMgntInfo->PowerSaveControl.bInactivePs = FALSE;
+	//	pMgntInfo->PowerSaveControl.bIPSModeBackup = FALSE;
+	//	pMgntInfo->PowerSaveControl.bLeisurePs = FALSE;
+	//	pMgntInfo->keepAliveLevel = 0;
+	//}
+
+
+}
+
+//
+//	Description:
+//		Read HW adapter information by E-Fuse or EEPROM according CR9346 reported.
+//
+//	Assumption:
+//		PASSIVE_LEVEL (SDIO interface)
+//
+//
+static s32 _ReadAdapterInfo8188ES(PADAPTER padapter)
+{
+	u32 start;
+
+		
+	RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("+_ReadAdapterInfo8188ES\n"));
+
+	// before access eFuse, make sure card enable has been called
+	if(_CardEnable(padapter) == _FAIL)
+	{
+		DBG_871X(KERN_ERR "%s: run power on flow fail\n", __func__);
+		return _FAIL;	
+	}
+
+	start = rtw_get_current_time();
+	
+//	Efuse_InitSomeVar(Adapter);
+//	pHalData->VersionID = ReadChipVersion(Adapter);
+//	_EfuseCellSel(padapter);
+
+	_ReadRFType(padapter);//rf_chip -> _InitRFType()
+	_ReadPROMContent(padapter);
+	
+	// 2010/10/25 MH THe function must be called after borad_type & IC-Version recognize.
+	//ReadSilmComboMode(Adapter);
+	_InitOtherVariable(padapter);
+
+
+	//MSG_8192C("%s()(done), rf_chip=0x%x, rf_type=0x%x\n",  __FUNCTION__, pHalData->rf_chip, pHalData->rf_type);
+	MSG_8192C("<==== ReadAdapterInfo8188ES in %d ms\n", rtw_get_passing_time_ms(start));
+
+	return _SUCCESS;
+}
+
+static void ReadAdapterInfo8188ES(PADAPTER padapter)
+{
+	// Read EEPROM size before call any EEPROM function
+	padapter->EepromAddressSize = GetEEPROMSize8188E(padapter);
+
+	_ReadAdapterInfo8188ES(padapter);
+}
+
+static void ResumeTxBeacon(PADAPTER padapter)
+{
+	HAL_DATA_TYPE*	pHalData = GET_HAL_DATA(padapter);
+
+	// 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value
+	// which should be read from register to a global variable.
+
+	RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("+ResumeTxBeacon\n"));
+
+	rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, (pHalData->RegFwHwTxQCtrl) | BIT6);
+	pHalData->RegFwHwTxQCtrl |= BIT6;
+	rtw_write8(padapter, REG_TBTT_PROHIBIT+1, 0xff);
+	pHalData->RegReg542 |= BIT0;
+	rtw_write8(padapter, REG_TBTT_PROHIBIT+2, pHalData->RegReg542);
+}
+
+static void StopTxBeacon(PADAPTER padapter)
+{
+	HAL_DATA_TYPE*	pHalData = GET_HAL_DATA(padapter);
+
+	// 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value
+	// which should be read from register to a global variable.
+
+	RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("+StopTxBeacon\n"));
+
+	rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, (pHalData->RegFwHwTxQCtrl) & (~BIT6));
+	pHalData->RegFwHwTxQCtrl &= (~BIT6);
+	rtw_write8(padapter, REG_TBTT_PROHIBIT+1, 0x64);
+	pHalData->RegReg542 &= ~(BIT0);
+	rtw_write8(padapter, REG_TBTT_PROHIBIT+2, pHalData->RegReg542);
+
+	CheckFwRsvdPageContent(padapter);  // 2010.06.23. Added by tynli.
+}
+
+// todo static 
+void hw_var_set_opmode(PADAPTER Adapter, u8 variable, u8* val)
+{
+	u8	val8;
+	u8	mode = *((u8 *)val);
+	//HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
+
+#ifdef CONFIG_CONCURRENT_MODE
+	if(Adapter->iface_type == IFACE_PORT1)
+	{
+		// disable Port1 TSF update
+		rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(4));
+		
+		// set net_type
+		val8 = rtw_read8(Adapter, MSR)&0x03;
+		val8 |= (mode<<2);
+		rtw_write8(Adapter, MSR, val8);
+		
+		DBG_871X("%s()-%d mode = %d\n", __FUNCTION__, __LINE__, mode);
+
+		if((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_))
+		{
+			if(!check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE))			
+			{
+				#ifdef CONFIG_INTERRUPT_BASED_TXBCN	
+
+				#ifdef  CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT	
+				rtw_write8(Adapter, REG_DRVERLYINT, 0x05);//restore early int time to 5ms
+				UpdateInterruptMask8188ESdio(Adapter, 0, SDIO_HIMR_BCNERLY_INT_MSK);	
+				#endif // CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
+				
+				#ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR		
+				UpdateInterruptMask8188ESdio(Adapter, 0, (SDIO_HIMR_TXBCNOK_MSK|SDIO_HIMR_TXBCNERR_MSK));	
+				#endif// CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
+					
+				#endif //CONFIG_INTERRUPT_BASED_TXBCN		
+			
+
+				StopTxBeacon(Adapter);
+			}
+			
+			rtw_write8(Adapter,REG_BCN_CTRL_1, 0x19);//disable atim wnd
+			//rtw_write8(Adapter,REG_BCN_CTRL_1, 0x18);
+		}
+		else if((mode == _HW_STATE_ADHOC_) /*|| (mode == _HW_STATE_AP_)*/)
+		{
+			ResumeTxBeacon(Adapter);
+			rtw_write8(Adapter,REG_BCN_CTRL_1, 0x1a);
+		}
+		else if(mode == _HW_STATE_AP_)
+		{
+#ifdef CONFIG_INTERRUPT_BASED_TXBCN			
+			#ifdef  CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
+			UpdateInterruptMask8188ESdio(Adapter, SDIO_HIMR_BCNERLY_INT_MSK, 0);
+			#endif//CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
+
+			#ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR	
+			UpdateInterruptMask8188ESdio(Adapter, (SDIO_HIMR_TXBCNOK_MSK|SDIO_HIMR_TXBCNERR_MSK), 0);
+			#endif//CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
+	
+#endif //CONFIG_INTERRUPT_BASED_TXBCN
+
+			ResumeTxBeacon(Adapter);
+	
+			rtw_write8(Adapter, REG_BCN_CTRL_1, 0x12);
+
+			//enable SW Beacon
+			rtw_write32(Adapter, REG_CR, rtw_read32(Adapter, REG_CR)|BIT(8));
+
+			//Set RCR
+			//rtw_write32(padapter, REG_RCR, 0x70002a8e);//CBSSID_DATA must set to 0
+			rtw_write32(Adapter, REG_RCR, 0x7000208e);//CBSSID_DATA must set to 0,Reject ICV_ERROR packets
+			
+			//enable to rx data frame				
+			rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
+			//enable to rx ps-poll
+			rtw_write16(Adapter, REG_RXFLTMAP1, 0x0400);
+
+			//Beacon Control related register for first time 
+			rtw_write8(Adapter, REG_BCNDMATIM, 0x02); // 2ms		
+
+			//rtw_write8(Adapter, REG_BCN_MAX_ERR, 0xFF);
+			rtw_write8(Adapter, REG_ATIMWND_1, 0x0a); // 10ms for port1
+			rtw_write16(Adapter, REG_BCNTCFG, 0x00);
+			rtw_write16(Adapter, REG_TBTT_PROHIBIT, 0xff04);
+			rtw_write16(Adapter, REG_TSFTR_SYN_OFFSET, 0x7fff);// +32767 (~32ms)
+
+			//reset TSF2	
+			rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(1));
+
+
+			//BIT4 - If set 0, hw will clr bcnq when tx becon ok/fail or port 1
+			rtw_write8(Adapter, REG_MBID_NUM, rtw_read8(Adapter, REG_MBID_NUM)|BIT(3)|BIT(4));
+		       	//enable BCN1 Function for if2
+			//don't enable update TSF1 for if2 (due to TSF update when beacon/probe rsp are received)
+			rtw_write8(Adapter, REG_BCN_CTRL_1, (DIS_TSF_UDT0_NORMAL_CHIP|EN_BCN_FUNCTION | EN_TXBCN_RPT|BIT(1)));
+
+#ifdef CONFIG_CONCURRENT_MODE
+			if(check_buddy_fwstate(Adapter, WIFI_FW_NULL_STATE))
+				rtw_write8(Adapter, REG_BCN_CTRL, 
+					rtw_read8(Adapter, REG_BCN_CTRL) & ~EN_BCN_FUNCTION);
+#endif
+                        //BCN1 TSF will sync to BCN0 TSF with offset(0x518) if if1_sta linked
+			//rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(5));
+			//rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(3));
+					
+			//dis BCN0 ATIM  WND if if1 is station
+			rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(0));
+
+#ifdef CONFIG_TSF_RESET_OFFLOAD
+			// Reset TSF for STA+AP concurrent mode
+			if ( check_buddy_fwstate(Adapter, (WIFI_STATION_STATE|WIFI_ASOC_STATE)) ) {
+				if (reset_tsf(Adapter, IFACE_PORT1) == _FALSE)
+					DBG_871X("ERROR! %s()-%d: Reset port1 TSF fail\n",
+						__FUNCTION__, __LINE__);
+			}
+#endif	// CONFIG_TSF_RESET_OFFLOAD	
+		}
+	}
+	else
+#endif //CONFIG_CONCURRENT_MODE
+	{
+		// disable Port0 TSF update
+		rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4));
+		
+		// set net_type
+		val8 = rtw_read8(Adapter, MSR)&0x0c;
+		val8 |= mode;
+		rtw_write8(Adapter, MSR, val8);
+		
+		DBG_871X("%s()-%d mode = %d\n", __FUNCTION__, __LINE__, mode);
+		
+		if((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_))
+		{
+#ifdef CONFIG_CONCURRENT_MODE
+			if(!check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE))		
+#endif //CONFIG_CONCURRENT_MODE
+			{
+			#ifdef CONFIG_INTERRUPT_BASED_TXBCN	
+				#ifdef  CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
+				rtw_write8(Adapter, REG_DRVERLYINT, 0x05);//restore early int time to 5ms					
+				UpdateInterruptMask8188ESdio(Adapter, 0, SDIO_HIMR_BCNERLY_INT_MSK);	
+				#endif//CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
+				
+				#ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR		
+				UpdateInterruptMask8188ESdio(Adapter, 0, (SDIO_HIMR_TXBCNOK_MSK|SDIO_HIMR_TXBCNERR_MSK));	
+				#endif //CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
+			#endif //CONFIG_INTERRUPT_BASED_TXBCN		
+				StopTxBeacon(Adapter);
+			}
+			
+			rtw_write8(Adapter,REG_BCN_CTRL, 0x19);//disable atim wnd
+			//rtw_write8(Adapter,REG_BCN_CTRL, 0x18);
+		}
+		else if((mode == _HW_STATE_ADHOC_) /*|| (mode == _HW_STATE_AP_)*/)
+		{
+			ResumeTxBeacon(Adapter);
+			rtw_write8(Adapter,REG_BCN_CTRL, 0x1a);
+		}
+		else if(mode == _HW_STATE_AP_)
+		{
+
+#ifdef CONFIG_INTERRUPT_BASED_TXBCN			
+			#ifdef  CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
+			UpdateInterruptMask8188ESdio(Adapter, SDIO_HIMR_BCNERLY_INT_MSK, 0);
+			#endif//CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
+
+			#ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
+			UpdateInterruptMask8188ESdio(Adapter, (SDIO_HIMR_TXBCNOK_MSK|SDIO_HIMR_TXBCNERR_MSK), 0);
+			#endif//CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
+#endif //CONFIG_INTERRUPT_BASED_TXBCN
+
+
+			ResumeTxBeacon(Adapter);
+
+			rtw_write8(Adapter, REG_BCN_CTRL, 0x12);
+
+			//enable SW Beacon
+			rtw_write32(Adapter, REG_CR, rtw_read32(Adapter, REG_CR)|BIT(8));
+
+			//Set RCR
+			//rtw_write32(padapter, REG_RCR, 0x70002a8e);//CBSSID_DATA must set to 0
+			rtw_write32(Adapter, REG_RCR, 0x7000208e);//CBSSID_DATA must set to 0,reject ICV_ERR packet
+			//enable to rx data frame
+			rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
+			//enable to rx ps-poll
+			rtw_write16(Adapter, REG_RXFLTMAP1, 0x0400);
+
+			//Beacon Control related register for first time
+			rtw_write8(Adapter, REG_BCNDMATIM, 0x02); // 2ms			
+			
+			//rtw_write8(Adapter, REG_BCN_MAX_ERR, 0xFF);
+			rtw_write8(Adapter, REG_ATIMWND, 0x0a); // 10ms
+			rtw_write16(Adapter, REG_BCNTCFG, 0x00);
+			rtw_write16(Adapter, REG_TBTT_PROHIBIT, 0xff04);
+			rtw_write16(Adapter, REG_TSFTR_SYN_OFFSET, 0x7fff);// +32767 (~32ms)
+
+			//reset TSF
+			rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(0));
+
+			//BIT3 - If set 0, hw will clr bcnq when tx becon ok/fail or port 0
+			rtw_write8(Adapter, REG_MBID_NUM, rtw_read8(Adapter, REG_MBID_NUM)|BIT(3)|BIT(4));
+	
+		        //enable BCN0 Function for if1
+			//don't enable update TSF0 for if1 (due to TSF update when beacon/probe rsp are received)
+			rtw_write8(Adapter, REG_BCN_CTRL, (DIS_TSF_UDT0_NORMAL_CHIP|EN_BCN_FUNCTION | EN_TXBCN_RPT|BIT(1)));
+
+#ifdef CONFIG_CONCURRENT_MODE
+			if(check_buddy_fwstate(Adapter, WIFI_FW_NULL_STATE))
+				rtw_write8(Adapter, REG_BCN_CTRL_1, 
+					rtw_read8(Adapter, REG_BCN_CTRL_1) & ~EN_BCN_FUNCTION);
+#endif
+
+			//dis BCN1 ATIM  WND if if2 is station
+			rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(0));	
+#ifdef CONFIG_TSF_RESET_OFFLOAD
+			// Reset TSF for STA+AP concurrent mode
+			if ( check_buddy_fwstate(Adapter, (WIFI_STATION_STATE|WIFI_ASOC_STATE)) ) {
+				if (reset_tsf(Adapter, IFACE_PORT0) == _FALSE)
+					DBG_871X("ERROR! %s()-%d: Reset port0 TSF fail\n",
+						__FUNCTION__, __LINE__);
+			}
+#endif	// CONFIG_TSF_RESET_OFFLOAD
+		}
+	}
+
+}
+
+static void hw_var_set_macaddr(PADAPTER Adapter, u8 variable, u8* val)
+{
+	u8 idx = 0;
+	u32 reg_macid;
+
+#ifdef CONFIG_CONCURRENT_MODE
+	if(Adapter->iface_type == IFACE_PORT1)
+	{
+		reg_macid = REG_MACID1;
+	}
+	else
+#endif
+	{
+		reg_macid = REG_MACID;
+	}
+
+	for(idx = 0 ; idx < 6; idx++)
+	{
+		rtw_write8(Adapter, (reg_macid+idx), val[idx]);
+	}
+	
+}
+
+static void hw_var_set_bssid(PADAPTER Adapter, u8 variable, u8* val)
+{
+	u8	idx = 0;
+	u32 reg_bssid;
+
+
+#ifdef CONFIG_CONCURRENT_MODE
+	if(Adapter->iface_type == IFACE_PORT1)
+	{
+		reg_bssid = REG_BSSID1;
+	}
+	else
+#endif
+	{
+		reg_bssid = REG_BSSID;
+	}
+
+printk("hw_var_set_bssid   reg=%x \n", reg_bssid);
+
+	for(idx = 0 ; idx < 6; idx++)
+	{
+		rtw_write8(Adapter, (reg_bssid+idx), val[idx]);
+	}
+
+}
+
+static void hw_var_set_bcn_func(PADAPTER Adapter, u8 variable, u8* val)
+{
+	u32 bcn_ctrl_reg;
+
+#ifdef CONFIG_CONCURRENT_MODE
+	if(Adapter->iface_type == IFACE_PORT1)
+	{
+		bcn_ctrl_reg = REG_BCN_CTRL_1;
+	}	
+	else
+#endif		
+	{		
+		bcn_ctrl_reg = REG_BCN_CTRL;
+	}
+
+	if(*((u8 *)val))
+	{
+		rtw_write8(Adapter, bcn_ctrl_reg, (EN_BCN_FUNCTION | EN_TXBCN_RPT));
+	}
+	else
+	{
+		rtw_write8(Adapter, bcn_ctrl_reg, rtw_read8(Adapter, bcn_ctrl_reg)&(~(EN_BCN_FUNCTION | EN_TXBCN_RPT)));
+	}
+	
+
+}
+
+static void hw_var_set_correct_tsf(PADAPTER Adapter, u8 variable, u8* val)
+{
+#ifdef CONFIG_CONCURRENT_MODE
+	u64	tsf;
+	struct mlme_ext_priv	*pmlmeext = &Adapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	PADAPTER pbuddy_adapter = Adapter->pbuddy_adapter;
+
+	//tsf = pmlmeext->TSFValue - ((u32)pmlmeext->TSFValue % (pmlmeinfo->bcn_interval*1024)) -1024; //us
+	tsf = pmlmeext->TSFValue - rtw_modular64(pmlmeext->TSFValue, (pmlmeinfo->bcn_interval*1024)) -1024; //us
+
+	if(((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE))
+	{				
+		//pHalData->RegTxPause |= STOP_BCNQ;BIT(6)
+		//rtw_write8(Adapter, REG_TXPAUSE, (rtw_read8(Adapter, REG_TXPAUSE)|BIT(6)));
+		StopTxBeacon(Adapter);
+	}
+
+	if(Adapter->iface_type == IFACE_PORT1)
+	{
+		//disable related TSF function
+		rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)&(~BIT(3)));
+							
+		rtw_write32(Adapter, REG_TSFTR1, tsf);
+		rtw_write32(Adapter, REG_TSFTR1+4, tsf>>32);
+		//enable related TSF function
+		rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(3));
+		// Update buddy port's TSF if it is SoftAP for beacon TX issue!
+		if ( (pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE
+			&& check_buddy_fwstate(Adapter, WIFI_AP_STATE)
+		) { 
+			//disable related TSF function
+			rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(3)));
+
+			rtw_write32(Adapter, REG_TSFTR, tsf);
+			rtw_write32(Adapter, REG_TSFTR+4, tsf>>32);
+
+			//enable related TSF function
+			rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(3));
+#ifdef CONFIG_TSF_RESET_OFFLOAD
+		// Update buddy port's TSF(TBTT) if it is SoftAP for beacon TX issue!
+			if (reset_tsf(Adapter, IFACE_PORT0) == _FALSE)
+				DBG_871X("ERROR! %s()-%d: Reset port0 TSF fail\n",
+					__FUNCTION__, __LINE__);
+
+#endif	// CONFIG_TSF_RESET_OFFLOAD	
+		}		
+	
+	}
+	else
+	{
+		//disable related TSF function
+		rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(3)));
+							
+		rtw_write32(Adapter, REG_TSFTR, tsf);
+		rtw_write32(Adapter, REG_TSFTR+4, tsf>>32);
+
+		//enable related TSF function
+		rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(3));		
+		// Update buddy port's TSF if it is SoftAP for beacon TX issue!
+		if ( (pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE
+			&& check_buddy_fwstate(Adapter, WIFI_AP_STATE)
+		) { 
+			//disable related TSF function
+			rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)&(~BIT(3)));
+
+			rtw_write32(Adapter, REG_TSFTR1, tsf);
+			rtw_write32(Adapter, REG_TSFTR1+4, tsf>>32);
+
+			//enable related TSF function
+			rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(3));
+#ifdef CONFIG_TSF_RESET_OFFLOAD
+		// Update buddy port's TSF if it is SoftAP for beacon TX issue!
+			if (reset_tsf(Adapter, IFACE_PORT1) == _FALSE)
+				DBG_871X("ERROR! %s()-%d: Reset port1 TSF fail\n",
+					__FUNCTION__, __LINE__);
+#endif	// CONFIG_TSF_RESET_OFFLOAD
+		}		
+	}
+				
+							
+	if(((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE))
+	{
+		//pHalData->RegTxPause  &= (~STOP_BCNQ);
+		//rtw_write8(Adapter, REG_TXPAUSE, (rtw_read8(Adapter, REG_TXPAUSE)&(~BIT(6))));
+		ResumeTxBeacon(Adapter);
+	}
+#endif
+}
+
+static void hw_var_set_mlme_disconnect(PADAPTER Adapter, u8 variable, u8* val)
+{
+#ifdef CONFIG_CONCURRENT_MODE
+	//HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
+	PADAPTER pbuddy_adapter = Adapter->pbuddy_adapter;
+			
+				
+	if(check_buddy_mlmeinfo_state(Adapter, _HW_STATE_NOLINK_))	
+		rtw_write16(Adapter, REG_RXFLTMAP2, 0x00);
+	
+
+	if(Adapter->iface_type == IFACE_PORT1)
+	{
+		//reset TSF1
+		rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(1));
+
+		//disable update TSF1
+		rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(4));
+	}
+	else
+	{
+		//reset TSF
+		rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(0));
+
+		//disable update TSF
+		rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4));
+	}
+#endif
+}
+
+static void hw_var_set_mlme_sitesurvey(PADAPTER Adapter, u8 variable, u8* val)
+{	
+#ifdef CONFIG_CONCURRENT_MODE	
+	//HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+
+	struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+
+	if(*((u8 *)val))//under sitesurvey
+	{
+		//config RCR to receive different BSSID & not to receive data frame
+		u32 v = rtw_read32(Adapter, REG_RCR);
+		v &= ~(RCR_CBSSID_BCN);
+		rtw_write32(Adapter, REG_RCR, v);
+
+		//disable update TSF
+		if((pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE)
+		{
+			if(Adapter->iface_type == IFACE_PORT1)
+			{
+				rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(4));
+			}
+			else
+			{
+				rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4));
+			}				
+		}
+				
+		if(check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE) &&
+			check_buddy_fwstate(Adapter, _FW_LINKED))		
+		{
+			StopTxBeacon(Adapter);
+		}		
+				
+	}
+	else//sitesurvey done
+	{
+		//enable to rx data frame
+		//write32(Adapter, REG_RCR, read32(padapter, REG_RCR)|RCR_ADF);
+		rtw_write16(Adapter, REG_RXFLTMAP2,0xFFFF);
+
+		//enable update TSF
+		if(Adapter->iface_type == IFACE_PORT1)
+			rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)&(~BIT(4)));
+		else
+			rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4)));
+
+		rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_BCN);
+
+		if(check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE) &&
+			check_buddy_fwstate(Adapter, _FW_LINKED))
+		{
+			ResumeTxBeacon(Adapter);			
+		}
+					
+	}
+#endif			
+}
+
+static void hw_var_set_mlme_join(PADAPTER Adapter, u8 variable, u8* val)
+{
+#ifdef CONFIG_CONCURRENT_MODE
+	u8	RetryLimit = 0x30;
+	u8	type = *((u8 *)val);
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+	struct mlme_priv	*pmlmepriv = &Adapter->mlmepriv;
+
+	if(type == 0) // prepare to join
+	{		
+		if(check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE) &&
+			check_buddy_fwstate(Adapter, _FW_LINKED))		
+		{
+			StopTxBeacon(Adapter);
+		}
+	
+		//enable to rx data frame.Accept all data frame
+		//rtw_write32(padapter, REG_RCR, rtw_read32(padapter, REG_RCR)|RCR_ADF);
+		rtw_write16(Adapter, REG_RXFLTMAP2,0xFFFF);
+
+		if(check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE))
+			rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_BCN);
+		else
+			rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_DATA|RCR_CBSSID_BCN);
+
+		if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)
+		{
+			RetryLimit = (pHalData->CustomerID == RT_CID_CCX) ? 7 : 48;
+		}
+		else // Ad-hoc Mode
+		{
+			RetryLimit = 0x7;
+		}
+	}
+	else if(type == 1) //joinbss_event call back when join res < 0
+	{		
+		if(check_buddy_mlmeinfo_state(Adapter, _HW_STATE_NOLINK_))		
+			rtw_write16(Adapter, REG_RXFLTMAP2,0x00);
+
+		if(check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE) &&
+			check_buddy_fwstate(Adapter, _FW_LINKED))
+		{
+			ResumeTxBeacon(Adapter);			
+			
+			//reset TSF 1/2 after ResumeTxBeacon
+			rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(1)|BIT(0));	
+			
+		}
+	}
+	else if(type == 2) //sta add event call back
+	{
+	 
+		//enable update TSF
+		if(Adapter->iface_type == IFACE_PORT1)
+			rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)&(~BIT(4)));
+		else
+			rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4)));
+		 
+	
+		if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE))
+		{
+			//fixed beacon issue for 8191su...........
+			rtw_write8(Adapter,0x542 ,0x02);
+			RetryLimit = 0x7;
+		}
+
+
+		if(check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE) &&
+			check_buddy_fwstate(Adapter, _FW_LINKED))
+		{
+			ResumeTxBeacon(Adapter);			
+			
+			//reset TSF 1/2 after ResumeTxBeacon
+			rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(1)|BIT(0));
+		}
+		
+	}
+
+	rtw_write16(Adapter, REG_RL, RetryLimit << RETRY_LIMIT_SHORT_SHIFT | RetryLimit << RETRY_LIMIT_LONG_SHIFT);
+	
+#endif
+}
+static void SetHwReg8188ES(PADAPTER Adapter, u8 variable, u8* val)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
+	struct dm_priv	*pdmpriv = &pHalData->dmpriv;
+	DM_ODM_T 		*podmpriv = &pHalData->odmpriv;
+_func_enter_;
+
+	switch(variable)
+	{
+		case HW_VAR_MEDIA_STATUS:
+			{
+				u8 val8;
+
+				val8 = rtw_read8(Adapter, MSR)&0x0c;
+				val8 |= *((u8 *)val);
+				rtw_write8(Adapter, MSR, val8);
+			}
+			break;
+		case HW_VAR_MEDIA_STATUS1:
+			{
+				u8 val8;
+
+				val8 = rtw_read8(Adapter, MSR)&0x03;
+				val8 |= *((u8 *)val) <<2;
+				rtw_write8(Adapter, MSR, val8);
+			}
+			break;
+		case HW_VAR_SET_OPMODE:
+			hw_var_set_opmode(Adapter, variable, val);
+			break;
+		case HW_VAR_MAC_ADDR:
+			hw_var_set_macaddr(Adapter, variable, val);
+			break;
+		case HW_VAR_BSSID:
+			hw_var_set_bssid(Adapter, variable, val);
+			break;
+		case HW_VAR_BASIC_RATE:
+			{
+				u16			BrateCfg = 0;
+				u8			RateIndex = 0;
+
+				// 2007.01.16, by Emily
+				// Select RRSR (in Legacy-OFDM and CCK)
+				// For 8190, we select only 24M, 12M, 6M, 11M, 5.5M, 2M, and 1M from the Basic rate.
+				// We do not use other rates.
+				HalSetBrateCfg( Adapter, val, &BrateCfg );
+				DBG_8192C("HW_VAR_BASIC_RATE: BrateCfg(%#x)\n", BrateCfg);
+
+				//2011.03.30 add by Luke Lee
+				//CCK 2M ACK should be disabled for some BCM and Atheros AP IOT
+				//because CCK 2M has poor TXEVM
+				//CCK 5.5M & 11M ACK should be enabled for better performance
+
+				pHalData->BasicRateSet = BrateCfg = (BrateCfg |0xd) & 0x15d;
+
+				BrateCfg |= 0x01; // default enable 1M ACK rate
+				// Set RRSR rate table.
+				rtw_write8(Adapter, REG_RRSR, BrateCfg&0xff);
+				rtw_write8(Adapter, REG_RRSR+1, (BrateCfg>>8)&0xff);
+				rtw_write8(Adapter, REG_RRSR+2, rtw_read8(Adapter, REG_RRSR+2)&0xf0);
+
+				// Set RTS initial rate
+				while(BrateCfg > 0x1)
+				{
+					BrateCfg = (BrateCfg>> 1);
+					RateIndex++;
+				}
+				// Ziv - Check
+				rtw_write8(Adapter, REG_INIRTS_RATE_SEL, RateIndex);
+			}
+			break;
+		case HW_VAR_TXPAUSE:
+			rtw_write8(Adapter, REG_TXPAUSE, *((u8 *)val));
+			break;
+		case HW_VAR_BCN_FUNC:
+			hw_var_set_bcn_func(Adapter, variable, val);
+			break;
+		case HW_VAR_CORRECT_TSF:
+#ifdef CONFIG_CONCURRENT_MODE
+			hw_var_set_correct_tsf(Adapter, variable, val);
+#else
+			{
+				u64	tsf;
+				struct mlme_ext_priv	*pmlmeext = &Adapter->mlmeextpriv;
+				struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+				//f = pmlmeext->TSFValue - ((u32)pmlmeext->TSFValue % (pmlmeinfo->bcn_interval*1024)) -1024; //us
+				tsf = pmlmeext->TSFValue - rtw_modular64(pmlmeext->TSFValue, (pmlmeinfo->bcn_interval*1024)) - 1024; //us
+
+				if (((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) ||
+					((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE))
+				{
+					//pHalData->RegTxPause |= STOP_BCNQ;BIT(6)
+					//rtw_write8(Adapter, REG_TXPAUSE, (rtw_read8(Adapter, REG_TXPAUSE)|BIT(6)));
+					StopTxBeacon(Adapter);
+				}
+
+				// disable related TSF function
+				rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(3)));
+
+				rtw_write32(Adapter, REG_TSFTR, tsf);
+				rtw_write32(Adapter, REG_TSFTR+4, tsf>>32);
+
+				// enable related TSF function
+				rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(3));
+
+				if (((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) ||
+					((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE))
+				{
+					//pHalData->RegTxPause  &= (~STOP_BCNQ);
+					//rtw_write8(Adapter, REG_TXPAUSE, (rtw_read8(Adapter, REG_TXPAUSE)&(~BIT(6))));
+					ResumeTxBeacon(Adapter);
+				}
+			}
+#endif
+			break;
+		case HW_VAR_CHECK_BSSID:
+			if(*((u8 *)val))
+			{ 
+				rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_DATA|RCR_CBSSID_BCN); 
+			}
+			else
+			{
+				u32	val32;
+
+				val32 = rtw_read32(Adapter, REG_RCR);
+ 
+				val32 &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);
+
+				rtw_write32(Adapter, REG_RCR, val32);
+			}
+			break;
+		case HW_VAR_MLME_DISCONNECT:
+#ifdef CONFIG_CONCURRENT_MODE
+			hw_var_set_mlme_disconnect(Adapter, variable, val);
+#else
+			{
+				//Set RCR to not to receive data frame when NO LINK state
+				//rtw_write32(Adapter, REG_RCR, rtw_read32(padapter, REG_RCR) & ~RCR_ADF);
+				//reject all data frames
+				rtw_write16(Adapter, REG_RXFLTMAP2,0x00);
+
+				//reset TSF
+				rtw_write8(Adapter, REG_DUAL_TSF_RST, (BIT(0)|BIT(1)));
+
+				//disable update TSF
+				rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4));	
+			}
+#endif
+			break;
+		case HW_VAR_MLME_SITESURVEY:
+#ifdef CONFIG_CONCURRENT_MODE
+			hw_var_set_mlme_sitesurvey(Adapter, variable,  val);
+#else
+			if(*((u8 *)val))//under sitesurvey
+			{
+				//config RCR to receive different BSSID & not to receive data frame
+				u32 v = rtw_read32(Adapter, REG_RCR);
+				v &= ~(RCR_CBSSID_BCN);
+				rtw_write32(Adapter, REG_RCR, v);
+				//reject all data frame
+				rtw_write16(Adapter, REG_RXFLTMAP2,0x00);
+
+				//disable update TSF
+				rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4));
+			}
+			else//sitesurvey done
+			{
+				struct mlme_ext_priv	*pmlmeext = &Adapter->mlmeextpriv;
+				struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+				if ((is_client_associated_to_ap(Adapter) == _TRUE) ||
+					((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) )
+				{
+					//enable to rx data frame
+					//rtw_write32(Adapter, REG_RCR, rtw_read32(padapter, REG_RCR)|RCR_ADF);
+					rtw_write16(Adapter, REG_RXFLTMAP2,0xFFFF);
+
+					//enable update TSF
+					rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4)));
+				}
+				else if((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)
+				{
+					//rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_ADF);
+					rtw_write16(Adapter, REG_RXFLTMAP2,0xFFFF);
+
+					//enable update TSF
+					rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4)));
+				}
+
+				if(Adapter->in_cta_test)
+				{
+					if((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)
+					{
+						rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_BCN);
+					}
+					else
+					{
+						u32 v = rtw_read32(Adapter, REG_RCR);
+						v &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN );//| RCR_ADF
+						rtw_write32(Adapter, REG_RCR, v);
+					}
+				}
+				else
+				{
+					rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_BCN);
+				}
+			}
+#endif
+			break;
+		case HW_VAR_MLME_JOIN:
+#ifdef CONFIG_CONCURRENT_MODE
+			hw_var_set_mlme_join(Adapter, variable,  val);
+#else
+			{
+				u8	RetryLimit = 0x30;
+				u8	type = *((u8 *)val);
+				struct mlme_priv	*pmlmepriv = &Adapter->mlmepriv;
+				
+				if(type == 0) // prepare to join
+				{
+					//enable to rx data frame.Accept all data frame
+					//rtw_write32(padapter, REG_RCR, rtw_read32(padapter, REG_RCR)|RCR_ADF);
+					rtw_write16(Adapter, REG_RXFLTMAP2,0xFFFF);
+					if(Adapter->in_cta_test)
+					{
+						u32 v = rtw_read32(Adapter, REG_RCR);
+						v &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN );//| RCR_ADF
+						rtw_write32(Adapter, REG_RCR, v);
+					}
+					else
+					{
+						rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_DATA|RCR_CBSSID_BCN);
+					}
+					if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)
+					{
+						RetryLimit = (pHalData->CustomerID == RT_CID_CCX) ? 7 : 48;
+					}
+					else // Ad-hoc Mode
+					{
+						RetryLimit = 0x7;
+					}
+				}
+				else if(type == 1) //joinbss_event call back when join res < 0
+				{
+					rtw_write16(Adapter, REG_RXFLTMAP2,0x00);
+				}
+				else if(type == 2) //sta add event call back
+				{
+					// enable update TSF
+					rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4)));
+
+					if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE))
+					{
+						RetryLimit = 0x7;
+					}
+				}
+
+				rtw_write16(Adapter, REG_RL, RetryLimit << RETRY_LIMIT_SHORT_SHIFT | RetryLimit << RETRY_LIMIT_LONG_SHIFT);
+			}
+#endif
+			break;
+		case HW_VAR_ON_RCR_AM:
+                        rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_AM);
+                        DBG_871X("%s, %d, RCR= %x \n", __FUNCTION__,__LINE__, rtw_read32(Adapter, REG_RCR));
+                        break;
+              case HW_VAR_OFF_RCR_AM:
+                        rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)& (~RCR_AM));
+                        DBG_871X("%s, %d, RCR= %x \n", __FUNCTION__,__LINE__, rtw_read32(Adapter, REG_RCR));
+                        break;
+		case HW_VAR_BEACON_INTERVAL:
+			rtw_write16(Adapter, REG_BCN_INTERVAL, *((u16 *)val));
+
+#ifdef  CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
+			{
+				struct mlme_ext_priv	*pmlmeext = &Adapter->mlmeextpriv;
+				struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+				u16 bcn_interval = 	*((u16 *)val);
+				if((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE){
+					DBG_8192C("%s==> bcn_interval:%d, eraly_int:%d \n",__FUNCTION__,bcn_interval,bcn_interval>>1);
+					rtw_write8(Adapter, REG_DRVERLYINT, bcn_interval>>1);// 50ms for sdio 
+				}
+				else{
+					
+				}
+			}
+#endif//CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
+
+			break;
+		case HW_VAR_SLOT_TIME:
+			{
+				u8	u1bAIFS, aSifsTime;
+				struct mlme_ext_priv	*pmlmeext = &Adapter->mlmeextpriv;
+				struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+				rtw_write8(Adapter, REG_SLOT, val[0]);
+
+				if(pmlmeinfo->WMM_enable == 0)
+				{
+					if( pmlmeext->cur_wireless_mode == WIRELESS_11B)
+						aSifsTime = 10;
+					else
+						aSifsTime = 16;
+
+					u1bAIFS = aSifsTime + (2 * pmlmeinfo->slotTime);
+
+					// <Roger_EXP> Temporary removed, 2008.06.20.
+					rtw_write8(Adapter, REG_EDCA_VO_PARAM, u1bAIFS);
+					rtw_write8(Adapter, REG_EDCA_VI_PARAM, u1bAIFS);
+					rtw_write8(Adapter, REG_EDCA_BE_PARAM, u1bAIFS);
+					rtw_write8(Adapter, REG_EDCA_BK_PARAM, u1bAIFS);
+				}
+			}
+			break;
+		case HW_VAR_RESP_SIFS:
+			{
+#if 0				
+				// SIFS for OFDM Data ACK
+				rtw_write8(Adapter, REG_SIFS_CTX+1, val[0]);
+				// SIFS for OFDM consecutive tx like CTS data!
+				rtw_write8(Adapter, REG_SIFS_TRX+1, val[1]);
+
+				rtw_write8(Adapter,REG_SPEC_SIFS+1, val[0]);
+				rtw_write8(Adapter,REG_MAC_SPEC_SIFS+1, val[0]);
+
+				// 20100719 Joseph: Revise SIFS setting due to Hardware register definition change.
+				rtw_write8(Adapter, REG_R2T_SIFS+1, val[0]);
+				rtw_write8(Adapter, REG_T2T_SIFS+1, val[0]);
+#else				
+				//SIFS_Timer = 0x0a0a0808;
+				//RESP_SIFS for CCK
+				rtw_write8(Adapter, REG_R2T_SIFS, val[0]); // SIFS_T2T_CCK (0x08)
+				rtw_write8(Adapter, REG_R2T_SIFS+1, val[1]); //SIFS_R2T_CCK(0x08)
+				//RESP_SIFS for OFDM
+				rtw_write8(Adapter, REG_T2T_SIFS, val[2]); //SIFS_T2T_OFDM (0x0a)
+				rtw_write8(Adapter, REG_T2T_SIFS+1, val[3]); //SIFS_R2T_OFDM(0x0a)
+#endif				
+			}
+			break;
+		case HW_VAR_ACK_PREAMBLE:
+			{
+				u8	regTmp;
+				u8	bShortPreamble = *( (PBOOLEAN)val );
+				// Joseph marked out for Netgear 3500 TKIP channel 7 issue.(Temporarily)
+				regTmp = (pHalData->nCur40MhzPrimeSC)<<5;
+				//regTmp = 0;
+				if(bShortPreamble)
+					regTmp |= 0x80;
+
+				rtw_write8(Adapter, REG_RRSR+2, regTmp);
+			}
+			break;
+		case HW_VAR_SEC_CFG:
+#ifdef CONFIG_CONCURRENT_MODE
+			rtw_write8(Adapter, REG_SECCFG, 0x0c|BIT(5));// enable tx enc and rx dec engine, and no key search for MC/BC				
+#else
+			rtw_write8(Adapter, REG_SECCFG, *((u8 *)val));
+#endif
+			break;
+		case HW_VAR_DM_FLAG:
+			podmpriv->SupportAbility = *((u8 *)val);
+			break;
+		case HW_VAR_DM_FUNC_OP:
+			if(val[0])
+			{// save dm flag
+				podmpriv->BK_SupportAbility = podmpriv->SupportAbility;				
+			}
+			else
+			{// restore dm flag
+				podmpriv->SupportAbility = podmpriv->BK_SupportAbility;
+			}
+			break;
+		case HW_VAR_DM_FUNC_SET:
+			if(*((u32 *)val) == DYNAMIC_ALL_FUNC_ENABLE){
+				pdmpriv->DMFlag = pdmpriv->InitDMFlag;
+				podmpriv->SupportAbility = 	pdmpriv->InitODMFlag;
+			}
+			else{
+				podmpriv->SupportAbility |= *((u32 *)val);
+			}
+			break;
+		case HW_VAR_DM_FUNC_CLR:
+			podmpriv->SupportAbility &= *((u32 *)val);
+			break;
+		case HW_VAR_CAM_EMPTY_ENTRY:
+			{
+				u8	ucIndex = *((u8 *)val);
+				u8	i;
+				u32	ulCommand=0;
+				u32	ulContent=0;
+				u32	ulEncAlgo=CAM_AES;
+
+				for(i=0;i<CAM_CONTENT_COUNT;i++)
+				{
+					// filled id in CAM config 2 byte
+					if( i == 0)
+					{
+						ulContent |=(ucIndex & 0x03) | ((u16)(ulEncAlgo)<<2);
+						//ulContent |= CAM_VALID;
+					}
+					else
+					{
+						ulContent = 0;
+					}
+					// polling bit, and No Write enable, and address
+					ulCommand= CAM_CONTENT_COUNT*ucIndex+i;
+					ulCommand= ulCommand | CAM_POLLINIG|CAM_WRITE;
+					// write content 0 is equall to mark invalid
+					rtw_write32(Adapter, WCAMI, ulContent);  //delay_ms(40);
+					//RT_TRACE(COMP_SEC, DBG_LOUD, ("CAM_empty_entry(): WRITE A4: %lx \n",ulContent));
+					rtw_write32(Adapter, RWCAM, ulCommand);  //delay_ms(40);
+					//RT_TRACE(COMP_SEC, DBG_LOUD, ("CAM_empty_entry(): WRITE A0: %lx \n",ulCommand));
+				}
+			}
+			break;
+		case HW_VAR_CAM_INVALID_ALL:
+			rtw_write32(Adapter, RWCAM, BIT(31)|BIT(30));
+			break;
+		case HW_VAR_CAM_WRITE:
+			{
+				u32	cmd;
+				u32	*cam_val = (u32 *)val;
+				rtw_write32(Adapter, WCAMI, cam_val[0]);
+
+				cmd = CAM_POLLINIG | CAM_WRITE | cam_val[1];
+				rtw_write32(Adapter, RWCAM, cmd);
+			}
+			break;
+		case HW_VAR_AC_PARAM_VO:
+			rtw_write32(Adapter, REG_EDCA_VO_PARAM, ((u32 *)(val))[0]);
+			break;
+		case HW_VAR_AC_PARAM_VI:
+			rtw_write32(Adapter, REG_EDCA_VI_PARAM, ((u32 *)(val))[0]);
+			break;
+		case HW_VAR_AC_PARAM_BE:
+			pHalData->AcParam_BE = ((u32 *)(val))[0];
+			rtw_write32(Adapter, REG_EDCA_BE_PARAM, ((u32 *)(val))[0]);
+			break;
+		case HW_VAR_AC_PARAM_BK:
+			rtw_write32(Adapter, REG_EDCA_BK_PARAM, ((u32 *)(val))[0]);
+			break;
+		case HW_VAR_AMPDU_MIN_SPACE:
+			{
+				u8	MinSpacingToSet;
+				u8	SecMinSpace;
+
+				MinSpacingToSet = *((u8 *)val);
+				if(MinSpacingToSet <= 7)
+				{
+					switch(Adapter->securitypriv.dot11PrivacyAlgrthm)
+					{
+						case _NO_PRIVACY_:
+						case _AES_:
+							SecMinSpace = 0;
+							break;
+
+						case _WEP40_:
+						case _WEP104_:
+						case _TKIP_:
+						case _TKIP_WTMIC_:
+							SecMinSpace = 6;
+							break;
+						default:
+							SecMinSpace = 7;
+							break;
+					}
+
+					if(MinSpacingToSet < SecMinSpace){
+						MinSpacingToSet = SecMinSpace;
+					}
+
+					//RT_TRACE(COMP_MLME, DBG_LOUD, ("Set HW_VAR_AMPDU_MIN_SPACE: %#x\n", Adapter->MgntInfo.MinSpaceCfg));
+					rtw_write8(Adapter, REG_AMPDU_MIN_SPACE, (rtw_read8(Adapter, REG_AMPDU_MIN_SPACE) & 0xf8) | MinSpacingToSet);
+				}
+			}
+			break;
+		case HW_VAR_AMPDU_FACTOR:
+			{
+				u8	RegToSet_Normal[4]={0x41,0xa8,0x72, 0xb9};
+				u8	RegToSet_BT[4]={0x31,0x74,0x42, 0x97};
+				u8	FactorToSet;
+				u8	*pRegToSet;
+				u8	index = 0;
+
+#ifdef CONFIG_BT_COEXIST
+				if(	(pHalData->bt_coexist.BT_Coexist) &&
+					(pHalData->bt_coexist.BT_CoexistType == BT_CSR_BC4) )
+					pRegToSet = RegToSet_BT; // 0x97427431;
+				else
+#endif
+					pRegToSet = RegToSet_Normal; // 0xb972a841;
+
+				FactorToSet = *((u8 *)val);
+				if(FactorToSet <= 3)
+				{
+					FactorToSet = (1<<(FactorToSet + 2));
+					if(FactorToSet>0xf)
+						FactorToSet = 0xf;
+
+					for(index=0; index<4; index++)
+					{
+						if((pRegToSet[index] & 0xf0) > (FactorToSet<<4))
+							pRegToSet[index] = (pRegToSet[index] & 0x0f) | (FactorToSet<<4);
+
+						if((pRegToSet[index] & 0x0f) > FactorToSet)
+							pRegToSet[index] = (pRegToSet[index] & 0xf0) | (FactorToSet);
+
+						rtw_write8(Adapter, (REG_AGGLEN_LMT+index), pRegToSet[index]);
+					}
+
+					//RT_TRACE(COMP_MLME, DBG_LOUD, ("Set HW_VAR_AMPDU_FACTOR: %#x\n", FactorToSet));
+				}
+			}
+			break;
+		case HW_VAR_RXDMA_AGG_PG_TH:
+			rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, *((u8 *)val));
+			break;
+		case HW_VAR_SET_RPWM:
+#ifdef CONFIG_LPS_LCLK
+			{
+				u8	ps_state = *((u8 *)val);
+				//rpwm value only use BIT0(clock bit) ,BIT6(Ack bit), and BIT7(Toggle bit) for 88e.
+				//BIT0 value - 1: 32k, 0:40MHz.
+				//BIT6 value - 1: report cpwm value after success set, 0:do not report.
+				//BIT7 value - Toggle bit change.
+				//modify by Thomas. 2012/4/2.
+				ps_state = ps_state & 0xC1;
+
+#ifdef CONFIG_EXT_CLK //for sprd
+				if(ps_state&BIT(6)) // want to leave 32k
+				{
+					//enable ext clock req before leave LPS-32K
+					//DBG_871X("enable ext clock req before leaving LPS-32K\n");					
+					EnableGpio5ClockReq(Adapter, _FALSE, 1);
+				}
+#endif //CONFIG_EXT_CLK
+
+				//DBG_871X("##### Change RPWM value to = %x for switch clk #####\n",ps_state);
+				rtw_write8(Adapter, SDIO_LOCAL_BASE|SDIO_REG_HRPWM1, ps_state);
+			}
+#endif
+			break;
+		case HW_VAR_H2C_FW_PWRMODE:
+			{
+				u8	psmode = (*(u8 *)val);
+
+				// Forece leave RF low power mode for 1T1R to prevent conficting setting in Fw power
+				// saving sequence. 2010.06.07. Added by tynli. Suggested by SD3 yschang.
+				if( (psmode != PS_MODE_ACTIVE) && (!IS_92C_SERIAL(pHalData->VersionID)))
+				{
+					ODM_RF_Saving(podmpriv, _TRUE);
+				}
+				rtl8188e_set_FwPwrMode_cmd(Adapter, psmode);
+			}
+			break;
+		case HW_VAR_H2C_FW_JOINBSSRPT:
+			{
+				u8	mstatus = (*(u8 *)val);
+				rtl8188e_set_FwJoinBssReport_cmd(Adapter, mstatus);
+			}
+			break;
+#ifdef CONFIG_P2P_PS
+		case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
+			{
+				u8	p2p_ps_state = (*(u8 *)val);
+				rtl8188e_set_p2p_ps_offload_cmd(Adapter, p2p_ps_state);
+			}
+			break;
+#endif // CONFIG_P2P_PS
+		case HW_VAR_INITIAL_GAIN:
+			{				
+				DIG_T	*pDigTable = &podmpriv->DM_DigTable;					
+				u32 		rx_gain = ((u32 *)(val))[0];
+		
+				if(rx_gain == 0xff){//restore rx gain					
+					ODM_Write_DIG(podmpriv,pDigTable->BackupIGValue);
+				}
+				else{
+					pDigTable->BackupIGValue = pDigTable->CurIGValue;
+					ODM_Write_DIG(podmpriv,rx_gain);
+				}
+			}		
+			break;
+		case HW_VAR_TRIGGER_GPIO_0:
+//			rtl8192cu_trigger_gpio_0(Adapter);
+			break;
+#ifdef CONFIG_BT_COEXIST
+		case HW_VAR_BT_SET_COEXIST:
+			{
+				u8	bStart = (*(u8 *)val);
+				rtl8192c_set_dm_bt_coexist(Adapter, bStart);
+			}
+			break;
+		case HW_VAR_BT_ISSUE_DELBA:
+			{
+				u8	dir = (*(u8 *)val);
+				rtl8192c_issue_delete_ba(Adapter, dir);
+			}
+			break;
+#endif
+#if (RATE_ADAPTIVE_SUPPORT==1)
+		case HW_VAR_RPT_TIMER_SETTING:
+			{
+				u16	min_rpt_time = (*(u16 *)val);
+
+				//DBG_8192C("==> HW_VAR_ANTENNA_DIVERSITY_SELECT , Ant_(%s)\n",(Optimum_antenna==2)?"A":"B");
+
+				//PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, Optimum_antenna);
+				ODM_RA_Set_TxRPT_Time(podmpriv,min_rpt_time);	
+			}
+			break;
+#endif
+
+#ifdef CONFIG_SW_ANTENNA_DIVERSITY
+		case HW_VAR_ANTENNA_DIVERSITY_LINK:
+			//SwAntDivRestAfterLink8192C(Adapter);
+			ODM_SwAntDivRestAfterLink(podmpriv);
+			break;
+#endif
+#ifdef CONFIG_ANTENNA_DIVERSITY
+		case HW_VAR_ANTENNA_DIVERSITY_SELECT:
+			{
+				u8	Optimum_antenna = (*(u8 *)val);
+				u8 	Ant ; 
+				//switch antenna to Optimum_antenna
+				//DBG_8192C("==> HW_VAR_ANTENNA_DIVERSITY_SELECT , Ant_(%s)\n",(Optimum_antenna==2)?"A":"B");
+				if(pHalData->CurAntenna !=  Optimum_antenna)		
+				{					
+					Ant = (Optimum_antenna==2)?MAIN_ANT:AUX_ANT;
+					ODM_UpdateRxIdleAnt_88E(&pHalData->odmpriv, Ant);
+					
+					pHalData->CurAntenna = Optimum_antenna ;
+					//DBG_8192C("==> HW_VAR_ANTENNA_DIVERSITY_SELECT , Ant_(%s)\n",(Optimum_antenna==2)?"A":"B");
+				}
+			}
+			break;
+#endif
+		case HW_VAR_EFUSE_BYTES: // To set EFUE total used bytes, added by Roger, 2008.12.22.
+			pHalData->EfuseUsedBytes = *((u16 *)val);
+			break;
+		case HW_VAR_FIFO_CLEARN_UP:
+			{				
+				struct pwrctrl_priv *pwrpriv = &Adapter->pwrctrlpriv;
+				u8 trycnt = 100;
+
+				//pause tx
+				rtw_write8(Adapter,REG_TXPAUSE,0xff);
+
+				//keep sn
+				Adapter->xmitpriv.nqos_ssn = rtw_read16(Adapter,REG_NQOS_SEQ);
+
+				//RX DMA stop
+				rtw_write32(Adapter,REG_RXPKT_NUM,(rtw_read32(Adapter,REG_RXPKT_NUM)|RW_RELEASE_EN));
+				do{
+					if(!(rtw_read32(Adapter,REG_RXPKT_NUM)&RXDMA_IDLE))
+						break;
+				}while(trycnt--);
+				if(trycnt ==0)
+					DBG_8192C("Stop RX DMA failed...... \n");
+
+				//RQPN Load 0
+				rtw_write16(Adapter,REG_RQPN_NPQ,0x0);
+				rtw_write32(Adapter,REG_RQPN,0x80000000);
+				rtw_mdelay_os(10);
+
+			}
+			break;
+		case HW_VAR_CHECK_TXBUF:
+#ifdef CONFIG_CONCURRENT_MODE				
+			{
+				int i;
+				u8	RetryLimit = 0x01;
+ 
+				rtw_write16(Adapter, REG_RL, RetryLimit << RETRY_LIMIT_SHORT_SHIFT | RetryLimit << RETRY_LIMIT_LONG_SHIFT); 
+				for(i=0;i<1000;i++)
+				{
+					if(rtw_read32(Adapter, 0x200) != rtw_read32(Adapter, 0x204))
+					{
+						//DBG_871X("packet in tx packet buffer - 0x204=%x, 0x200=%x (%d)\n", rtw_read32(Adapter, 0x204), rtw_read32(Adapter, 0x200), i);
+						rtw_msleep_os(10);
+					}
+					else
+					{
+						DBG_871X("no packet in tx packet buffer (%d)\n", i);
+						break;
+					}
+				}
+
+				RetryLimit = 0x30;	
+				rtw_write16(Adapter, REG_RL, RetryLimit << RETRY_LIMIT_SHORT_SHIFT | RetryLimit << RETRY_LIMIT_LONG_SHIFT);
+			
+			}
+#endif
+			break;
+#ifdef CONFIG_WOWLAN
+		case HW_VAR_WOWLAN:
+		{
+			struct wowlan_ioctl_param *poidparam;
+			struct recv_buf *precvbuf;
+			int res, i;
+			u32 tmp;
+			u16 len = 0;
+			u8 mstatus = (*(u8 *)val);
+			u8 trycnt = 100;
+			u8 data[4];
+
+			poidparam = (struct wowlan_ioctl_param *)val;
+			switch (poidparam->subcode){
+				case WOWLAN_ENABLE:
+					DBG_871X_LEVEL(_drv_always_, "WOWLAN_ENABLE\n");
+
+					SetFwRelatedForWoWLAN8188ES(Adapter, _TRUE);
+
+					//Set Pattern
+					//if(Adapter->pwrctrlpriv.wowlan_pattern==_TRUE)
+					//	rtw_wowlan_reload_pattern(Adapter);
+
+					//RX DMA stop
+					DBG_871X_LEVEL(_drv_always_, "Pause DMA\n");
+					rtw_write32(Adapter,REG_RXPKT_NUM,(rtw_read32(Adapter,REG_RXPKT_NUM)|RW_RELEASE_EN));
+					do{
+						if((rtw_read32(Adapter, REG_RXPKT_NUM)&RXDMA_IDLE)) {
+							DBG_871X_LEVEL(_drv_always_, "RX_DMA_IDLE is true\n");
+							break;
+						} else {
+							// If RX_DMA is not idle, receive one pkt from DMA
+							res = sdio_local_read(Adapter, SDIO_REG_RX0_REQ_LEN, 4, (u8*)&tmp);
+							//len = le16_to_cpu(*(u16*)data);
+							if (tmp == 0){
+								res = sdio_local_read(Adapter, SDIO_REG_HISR, 4, (u8*)&tmp);
+								DBG_871X_LEVEL(_drv_info_, "read SDIO_REG_HISR: 0x%08x\n", tmp);
+							}
+							res = RecvOnePkt(Adapter, tmp);
+							DBG_871X_LEVEL(_drv_always_, "RecvOnePkt Result: %d\n", res);
+						}
+					}while(trycnt--);
+					if(trycnt ==0)
+						DBG_871X_LEVEL(_drv_always_, "Stop RX DMA failed...... \n");
+
+					//Enable CPWM2 only.
+					DBG_871X_LEVEL(_drv_always_, "Enable only CPWM2\n");
+					res = sdio_local_read(Adapter, SDIO_REG_HIMR, 4, (u8*)&tmp);
+					if (!res)
+					    DBG_871X_LEVEL(_drv_info_, "read SDIO_REG_HIMR: 0x%08x\n", tmp);
+					else
+					    DBG_871X_LEVEL(_drv_info_, "sdio_local_read fail\n");
+
+					tmp = SDIO_HIMR_CPWM2_MSK;
+
+					res = sdio_local_write(Adapter, SDIO_REG_HIMR, 4, (u8*)&tmp);
+
+					if (!res){
+					    res = sdio_local_read(Adapter, SDIO_REG_HIMR, 4, (u8*)&tmp);
+					    DBG_871X_LEVEL(_drv_info_, "read again SDIO_REG_HIMR: 0x%08x\n", tmp);
+					}else
+					    DBG_871X_LEVEL(_drv_info_, "sdio_local_write fail\n");
+
+					//Set WOWLAN H2C command.
+					DBG_871X_LEVEL(_drv_always_, "Set WOWLan cmd\n");
+					rtl8188es_set_wowlan_cmd(Adapter, 1);
+
+					mstatus = rtw_read8(Adapter, REG_WOW_CTRL);
+					trycnt = 10;
+
+					while(!(mstatus&BIT1) && trycnt>1) {
+						mstatus = rtw_read8(Adapter, REG_WOW_CTRL);
+						DBG_871X_LEVEL(_drv_always_, "Loop index: %d :0x%02x\n", trycnt, mstatus);
+						trycnt --;
+						rtw_msleep_os(2);
+					}
+
+					Adapter->pwrctrlpriv.wowlan_wake_reason = rtw_read8(Adapter, REG_WOWLAN_WAKE_REASON);
+					DBG_871X_LEVEL(_drv_always_, "wowlan_wake_reason: 0x%02x\n",
+										Adapter->pwrctrlpriv.wowlan_wake_reason);
+					
+					//rtw_msleep_os(10);
+					break;
+				case WOWLAN_DISABLE:
+					DBG_871X_LEVEL(_drv_always_, "WOWLAN_DISABLE\n");
+					trycnt = 10;
+					Adapter->pwrctrlpriv.wowlan_wake_reason = 
+												rtw_read8(Adapter, REG_WOWLAN_WAKE_REASON);
+					DBG_871X_LEVEL(_drv_always_, "wakeup_reason: 0x%02x\n",
+												Adapter->pwrctrlpriv.wowlan_wake_reason);
+					rtl8188es_set_wowlan_cmd(Adapter, 0);
+					mstatus = rtw_read8(Adapter, REG_WOW_CTRL);
+					DBG_871X_LEVEL(_drv_info_, "%s mstatus:0x%02x\n", __func__, mstatus);
+
+					while(mstatus&BIT1 && trycnt>1) {
+						mstatus = rtw_read8(Adapter, REG_WOW_CTRL);
+						DBG_871X_LEVEL(_drv_always_, "Loop index: %d :0x%02x\n", trycnt, mstatus);
+						trycnt --;
+						rtw_msleep_os(2);
+					}
+
+					if (mstatus & BIT1)
+						printk("System did not release RX_DMA\n");
+					else
+						SetFwRelatedForWoWLAN8188ES(Adapter, _FALSE);
+
+					EnableInterrupt8188ESdio(Adapter);
+					rtw_msleep_os(2);
+					if(!(Adapter->pwrctrlpriv.wowlan_wake_reason & FWDecisionDisconnect) ||
+						!(Adapter->pwrctrlpriv.wowlan_wake_reason & Rx_GTK))
+						rtl8188e_set_FwJoinBssReport_cmd(Adapter, 1);
+					//rtw_msleep_os(10);
+					break;
+				default:
+					break;
+			}
+		}
+		break;
+#endif //CONFIG_WOWLAN
+		case HW_VAR_APFM_ON_MAC:
+			pHalData->bMacPwrCtrlOn = *val;
+			DBG_871X("%s: bMacPwrCtrlOn=%d\n", __func__, pHalData->bMacPwrCtrlOn);
+			break;
+#if (RATE_ADAPTIVE_SUPPORT == 1)
+		case HW_VAR_TX_RPT_MAX_MACID:
+			{
+				u8 maxMacid = *val;
+				DBG_8192C("### MacID(%d),Set Max Tx RPT MID(%d)\n",maxMacid,maxMacid+1);
+				rtw_write8(Adapter, REG_TX_RPT_CTRL+1, maxMacid+1);
+			}
+			break;
+#endif	//  (RATE_ADAPTIVE_SUPPORT == 1)		
+		case HW_VAR_H2C_MEDIA_STATUS_RPT:
+			{				
+				rtl8188e_set_FwMediaStatus_cmd(Adapter , (*(u16 *)val));
+			}
+			break;
+		case HW_VAR_BCN_VALID:
+			//BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2, write 1 to clear, Clear by sw
+			rtw_write8(Adapter, REG_TDECTRL+2, rtw_read8(Adapter, REG_TDECTRL+2) | BIT0); 
+			break;
+		default:
+			
+			break;
+	}
+
+_func_exit_;
+}
+
+static void GetHwReg8188ES(PADAPTER padapter, u8 variable, u8 *val)
+{
+	PHAL_DATA_TYPE 	pHalData= GET_HAL_DATA(padapter);
+	DM_ODM_T 		*podmpriv = &pHalData->odmpriv;
+_func_enter_;
+
+	switch (variable)
+	{
+		case HW_VAR_BASIC_RATE:
+			*((u16*)val) = pHalData->BasicRateSet;
+			break;
+
+		case HW_VAR_TXPAUSE:
+			val[0] = rtw_read8(padapter, REG_TXPAUSE);
+			break;
+
+		case HW_VAR_BCN_VALID:
+			//BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2
+			val[0] = (BIT0 & rtw_read8(padapter, REG_TDECTRL+2))?_TRUE:_FALSE;
+			break;
+
+		case HW_VAR_DM_FLAG:
+			val[0] = podmpriv->SupportAbility;
+			break;
+
+		case HW_VAR_RF_TYPE:
+			val[0] = pHalData->rf_type;
+			break;
+
+		case HW_VAR_FWLPS_RF_ON:
+			{
+				//When we halt NIC, we should check if FW LPS is leave.				
+				if ((padapter->bSurpriseRemoved == _TRUE) ||
+					(padapter->pwrctrlpriv.rf_pwrstate == rf_off))
+				{
+					// If it is in HW/SW Radio OFF or IPS state, we do not check Fw LPS Leave,
+					// because Fw is unload.
+					val[0] = _TRUE;
+				}
+				else
+				{
+					u32	valRCR;
+					valRCR = rtw_read32(padapter, REG_RCR);
+					valRCR &= 0x00070000;
+					if(valRCR)
+						val[0] = _FALSE;
+					else
+						val[0] = _TRUE;
+				}
+			}
+			break;
+#ifdef CONFIG_ANTENNA_DIVERSITY
+		case HW_VAR_CURRENT_ANTENNA:
+			val[0] = pHalData->CurAntenna;
+			break;
+#endif
+		case HW_VAR_EFUSE_BYTES: // To get EFUE total used bytes, added by Roger, 2008.12.22.
+			*((u16*)val) = pHalData->EfuseUsedBytes;
+			break;
+
+		case HW_VAR_APFM_ON_MAC:
+			*val = pHalData->bMacPwrCtrlOn;
+			break;
+		case HW_VAR_CHK_HI_QUEUE_EMPTY:
+			*val = ((rtw_read32(padapter, REG_HGQ_INFORMATION)&0x0000ff00)==0) ? _TRUE:_FALSE;
+			break;	
+		default:
+			break;
+	}
+
+_func_exit_;
+}
+
+//
+//	Description:
+//		Query setting of specified variable.
+//
+u8
+GetHalDefVar8188ESDIO(
+	IN	PADAPTER				Adapter,
+	IN	HAL_DEF_VARIABLE		eVariable,
+	IN	PVOID					pValue
+	)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);	
+	u8			bResult = _SUCCESS;
+
+	switch(eVariable)
+	{
+		case HAL_DEF_UNDERCORATEDSMOOTHEDPWDB:
+			{
+				struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
+				struct sta_priv * pstapriv = &Adapter->stapriv;
+				struct sta_info * psta;
+				psta = rtw_get_stainfo(pstapriv, pmlmepriv->cur_network.network.MacAddress);
+				if(psta)
+				{
+					*((int *)pValue) = psta->rssi_stat.UndecoratedSmoothedPWDB;     
+				}
+			}
+
+			break;
+		case HAL_DEF_IS_SUPPORT_ANT_DIV:
+			#ifdef CONFIG_ANTENNA_DIVERSITY
+			*((u8 *)pValue) = (pHalData->AntDivCfg==0)?_FALSE:_TRUE;
+			#endif
+			break;
+		case HAL_DEF_CURRENT_ANTENNA:
+#ifdef CONFIG_ANTENNA_DIVERSITY
+			*(( u8*)pValue) = pHalData->CurAntenna;
+#endif
+			break;
+		case HAL_DEF_DBG_DM_FUNC:
+			*(( u32*)pValue) =pHalData->odmpriv.SupportAbility;
+			break;
+#if (RATE_ADAPTIVE_SUPPORT == 1)
+		case HAL_DEF_RA_DECISION_RATE:
+			{
+				u8 MacID = *((u8*)pValue);
+				*((u8*)pValue) = ODM_RA_GetDecisionRate_8188E(&(pHalData->odmpriv), MacID);
+			}
+			break;
+		
+		case HAL_DEF_RA_SGI:
+			{
+				u8 MacID = *((u8*)pValue);
+				*((u8*)pValue) = ODM_RA_GetShortGI_8188E(&(pHalData->odmpriv), MacID);
+			}
+			break;		
+#endif
+
+
+		case HAL_DEF_PT_PWR_STATUS:
+#if(POWER_TRAINING_ACTIVE==1)	
+			{
+				u8 MacID = *((u8*)pValue);
+				*((u8*)pValue) = ODM_RA_GetHwPwrStatus_8188E(&(pHalData->odmpriv), MacID);
+			}
+#endif //(POWER_TRAINING_ACTIVE==1)
+			break;		
+
+		case HW_VAR_MAX_RX_AMPDU_FACTOR:
+			*(( u32*)pValue) = MAX_AMPDU_FACTOR_16K;
+			break;
+
+		case HW_DEF_RA_INFO_DUMP:
+#if (RATE_ADAPTIVE_SUPPORT == 1)	
+			{
+				u8 entry_id = *((u8*)pValue);	
+				if(check_fwstate(&Adapter->mlmepriv, _FW_LINKED)== _TRUE)
+				{
+					DBG_871X("============ RA status check ===================\n");
+					DBG_8192C("Mac_id:%d ,RateID = %d,RAUseRate = 0x%08x,RateSGI = %d, DecisionRate = 0x%02x ,PTStage = %d\n",
+						entry_id,
+						pHalData->odmpriv.RAInfo[entry_id].RateID,
+						pHalData->odmpriv.RAInfo[entry_id].RAUseRate,
+						pHalData->odmpriv.RAInfo[entry_id].RateSGI,
+						pHalData->odmpriv.RAInfo[entry_id].DecisionRate,
+						pHalData->odmpriv.RAInfo[entry_id].PTStage);
+				}
+			}
+#endif // (RATE_ADAPTIVE_SUPPORT == 1)
+			break;
+
+		case HAL_DEF_DBG_DUMP_RXPKT:
+			*(( u8*)pValue) = pHalData->bDumpRxPkt;
+			break;
+		case HAL_DEF_DBG_DUMP_TXPKT:
+			*(( u8*)pValue) = pHalData->bDumpTxPkt;
+			break;		
+		case HW_DEF_ODM_DBG_FLAG:
+			{
+				u8Byte	DebugComponents = *((u32*)pValue);	
+				PDM_ODM_T	pDM_Odm = &(pHalData->odmpriv);
+				printk("pDM_Odm->DebugComponents = 0x%llx \n",pDM_Odm->DebugComponents );			
+			}
+			break;	
+		default:
+			//RT_TRACE(COMP_INIT, DBG_WARNING, ("GetHalDefVar8188ESDIO(): Unkown variable: %d!\n", eVariable));
+			bResult = _FAIL;
+			break;
+	}
+
+	return bResult;
+}
+
+
+
+
+//
+//	Description:
+//		Change default setting of specified variable.
+//
+u8
+SetHalDefVar8188ESDIO(
+	IN	PADAPTER				Adapter,
+	IN	HAL_DEF_VARIABLE		eVariable,
+	IN	PVOID					pValue
+	)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
+	u8			bResult = _TRUE;
+
+	switch(eVariable)
+	{
+		case HAL_DEF_DBG_DM_FUNC:
+			{
+				u8 dm_func = *(( u8*)pValue);
+				struct dm_priv	*pdmpriv = &pHalData->dmpriv;
+				DM_ODM_T 		*podmpriv = &pHalData->odmpriv;
+				
+				if(dm_func == 0){ //disable all dynamic func
+					podmpriv->SupportAbility = DYNAMIC_FUNC_DISABLE;
+					DBG_8192C("==> Disable all dynamic function...\n");
+				}
+				else if(dm_func == 1){//disable DIG
+					podmpriv->SupportAbility  &= (~DYNAMIC_BB_DIG);
+					DBG_8192C("==> Disable DIG...\n");
+				}
+				else if(dm_func == 2){//disable High power
+					podmpriv->SupportAbility  &= (~DYNAMIC_BB_DYNAMIC_TXPWR);
+				}
+				else if(dm_func == 3){//disable tx power tracking
+					podmpriv->SupportAbility  &= (~DYNAMIC_RF_CALIBRATION);
+					DBG_8192C("==> Disable tx power tracking...\n");
+				}
+				//else if(dm_func == 4){//disable BT coexistence
+				//	pdmpriv->DMFlag &= (~DYNAMIC_FUNC_BT);
+				//}
+				else if(dm_func == 5){//disable antenna diversity
+					podmpriv->SupportAbility  &= (~DYNAMIC_BB_ANT_DIV);
+				}				
+				else if(dm_func == 6){//turn on all dynamic func
+					if(!(podmpriv->SupportAbility  & DYNAMIC_BB_DIG))
+					{						
+						DIG_T	*pDigTable = &podmpriv->DM_DigTable;
+						pDigTable->CurIGValue= rtw_read8(Adapter,0xc50);	
+					}
+					//pdmpriv->DMFlag |= DYNAMIC_FUNC_BT;
+					podmpriv->SupportAbility = DYNAMIC_ALL_FUNC_ENABLE;
+					DBG_8192C("==> Turn on all dynamic function...\n");
+				}			
+			}
+			break;			
+		case HAL_DEF_DBG_DUMP_RXPKT:
+			pHalData->bDumpRxPkt = *(( u8*)pValue);
+			break;
+		case HAL_DEF_DBG_DUMP_TXPKT:
+			pHalData->bDumpTxPkt = *(( u8*)pValue);
+			break;		
+		case HW_DEF_FA_CNT_DUMP:
+			{
+				u8 bRSSIDump = *((u8*)pValue);	
+				PDM_ODM_T		pDM_Odm = &(pHalData->odmpriv);
+				if(bRSSIDump)
+					pDM_Odm->DebugComponents	=	ODM_COMP_DIG|ODM_COMP_FA_CNT	;					
+				else
+					pDM_Odm->DebugComponents	= 0;					
+				
+			}
+			break;
+		case HW_DEF_ODM_DBG_FLAG:
+			{
+				u8Byte	DebugComponents = *((u8Byte*)pValue);	
+				PDM_ODM_T	pDM_Odm = &(pHalData->odmpriv);
+				pDM_Odm->DebugComponents = DebugComponents;			
+			}
+			break;
+		default:
+			//RT_TRACE(COMP_INIT, DBG_TRACE, ("SetHalDefVar819xUsb(): Unkown variable: %d!\n", eVariable));
+			bResult = _FALSE;
+			break;
+	}
+
+	return bResult;
+}
+
+void UpdateHalRAMask8188ESdio(PADAPTER padapter, u32 mac_id, u8 rssi_level)
+{
+	//volatile unsigned int result;
+	u8	init_rate=0;
+	u8	networkType, raid;	
+	u32	mask,rate_bitmap;
+	u8	shortGIrate = _FALSE;
+	int	supportRateNum = 0;
+	struct sta_info	*psta;
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	//struct dm_priv	*pdmpriv = &pHalData->dmpriv;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	WLAN_BSSID_EX 		*cur_network = &(pmlmeinfo->network);
+#ifdef CONFIG_CONCURRENT_MODE
+	if(rtw_buddy_adapter_up(padapter) && padapter->adapter_type > PRIMARY_ADAPTER)	
+		pHalData = GET_HAL_DATA(padapter->pbuddy_adapter);				
+#endif //CONFIG_CONCURRENT_MODE
+
+	if (mac_id >= NUM_STA) //CAM_SIZE
+	{
+		return;
+	}
+
+	psta = pmlmeinfo->FW_sta_info[mac_id].psta;
+	if(psta == NULL)
+	{
+		return;
+	}
+
+	switch (mac_id)
+	{
+		case 0:// for infra mode
+#ifdef CONFIG_CONCURRENT_MODE
+		case 2:// first station uses macid=0, second station uses macid=2
+#endif
+			supportRateNum = rtw_get_rateset_len(cur_network->SupportedRates);
+			networkType = judge_network_type(padapter, cur_network->SupportedRates, supportRateNum) & 0xf;
+			//pmlmeext->cur_wireless_mode = networkType;
+			raid = networktype_to_raid(networkType);
+						
+			mask = update_supported_rate(cur_network->SupportedRates, supportRateNum);
+			mask |= (pmlmeinfo->HT_enable)? update_MSC_rate(&(pmlmeinfo->HT_caps)): 0;
+		
+			
+			if (support_short_GI(padapter, &(pmlmeinfo->HT_caps)))
+			{
+				shortGIrate = _TRUE;
+			}
+			
+			break;
+
+		case 1://for broadcast/multicast
+			supportRateNum = rtw_get_rateset_len(pmlmeinfo->FW_sta_info[mac_id].SupportedRates);
+			if(pmlmeext->cur_wireless_mode & WIRELESS_11B)
+				networkType = WIRELESS_11B;
+			else
+				networkType = WIRELESS_11G;
+			raid = networktype_to_raid(networkType);
+			mask = update_basic_rate(cur_network->SupportedRates, supportRateNum);
+
+
+			break;
+
+		default: //for each sta in IBSS
+			supportRateNum = rtw_get_rateset_len(pmlmeinfo->FW_sta_info[mac_id].SupportedRates);
+			networkType = judge_network_type(padapter, pmlmeinfo->FW_sta_info[mac_id].SupportedRates, supportRateNum) & 0xf;
+			//pmlmeext->cur_wireless_mode = networkType;
+			raid = networktype_to_raid(networkType);			
+			mask = update_supported_rate(cur_network->SupportedRates, supportRateNum);
+			
+			//todo: support HT in IBSS
+			
+			break;
+	}
+	
+	//mask &=0xffffffff;
+	rate_bitmap = 0x0fffffff;	
+#ifdef	CONFIG_ODM_REFRESH_RAMASK
+	{				
+		rate_bitmap = ODM_Get_Rate_Bitmap(&pHalData->odmpriv,mac_id,mask,rssi_level);
+		DBG_8192C("%s => mac_id:%d, networkType:0x%02x, mask:0x%08x\n\t ==> rssi_level:%d, rate_bitmap:0x%08x\n",
+			__FUNCTION__,mac_id,networkType,mask,rssi_level,rate_bitmap);
+	}
+#endif
+	mask &= rate_bitmap; 
+	
+	
+	init_rate = get_highest_rate_idx(mask)&0x3f;
+	
+	if(pHalData->fw_ractrl == _TRUE)
+	{
+		u8 arg = 0;
+
+		//arg = (cam_idx-4)&0x1f;//MACID
+		arg = mac_id&0x1f;//MACID
+		
+		arg |= BIT(7);
+		
+		if (shortGIrate==_TRUE)
+			arg |= BIT(5);
+		mask |= ((raid<<28)&0xf0000000);
+	
+		DBG_871X("update raid entry, mask=0x%x, arg=0x%x\n", mask, arg);
+		psta->ra_mask=mask;
+#ifdef CONFIG_INTEL_PROXIM
+		if(padapter->proximity.proxim_on ==_TRUE){
+			arg &= ~BIT(6);
+		}
+		else {
+			arg |= BIT(6);
+		}
+#endif //CONFIG_INTEL_PROXIM
+		rtl8188e_set_raid_cmd(padapter, mask);	
+		
+	}
+	else
+	{	
+
+#if(RATE_ADAPTIVE_SUPPORT == 1)	
+
+		ODM_RA_UpdateRateInfo_8188E(
+				&(pHalData->odmpriv),
+				mac_id,
+				raid, 
+				mask,
+				shortGIrate
+				);
+
+#endif		
+	}
+
+
+	//set ra_id
+	psta->raid = raid;
+	psta->init_rate = init_rate;
+
+
+}
+
+
+static VOID
+_BeaconFunctionEnable(
+	IN	PADAPTER		padapter,
+	IN	BOOLEAN			Enable,
+	IN	BOOLEAN			Linked
+	)
+{
+	rtw_write8(padapter, REG_BCN_CTRL, (BIT4 | BIT3 | BIT1));
+//	RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("_BeaconFunctionEnable 0x550 0x%x\n", rtw_read8(padapter, 0x550)));
+
+	rtw_write8(padapter, REG_RD_CTRL+1, 0x6F);
+}
+
+void SetBeaconRelatedRegisters8188ESdio(PADAPTER padapter)
+{
+	u32	value32;
+	//HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	u32 bcn_ctrl_reg 		= REG_BCN_CTRL;
+	//reset TSF, enable update TSF, correcting TSF On Beacon
+
+	//REG_BCN_INTERVAL
+	//REG_BCNDMATIM
+	//REG_ATIMWND
+	//REG_TBTT_PROHIBIT
+	//REG_DRVERLYINT
+	//REG_BCN_MAX_ERR
+	//REG_BCNTCFG //(0x510)
+	//REG_DUAL_TSF_RST
+	//REG_BCN_CTRL //(0x550)
+
+
+#ifdef CONFIG_CONCURRENT_MODE
+	if (padapter->iface_type == IFACE_PORT1){
+		bcn_ctrl_reg = REG_BCN_CTRL_1;
+	}
+#endif	
+	//
+	// ATIM window
+	//
+	rtw_write16(padapter, REG_ATIMWND, 2);
+
+	//
+	// Beacon interval (in unit of TU).
+	//
+	rtw_write16(padapter, REG_BCN_INTERVAL, pmlmeinfo->bcn_interval);
+
+	_InitBeaconParameters(padapter);
+
+	rtw_write8(padapter, REG_SLOT, 0x09);
+
+	//
+	// Force beacon frame transmission even after receiving beacon frame from other ad hoc STA
+	//
+	//PlatformEFIOWrite1Byte(Adapter, BCN_ERR_THRESH, 0x0a); // We force beacon sent to prevent unexpect disconnect status in Ad hoc mode
+
+	//
+	// Reset TSF Timer to zero, added by Roger. 2008.06.24
+	//
+	value32 = rtw_read32(padapter, REG_TCR);
+	value32 &= ~TSFRST;
+	rtw_write32(padapter,  REG_TCR, value32);
+
+	value32 |= TSFRST;
+	rtw_write32(padapter, REG_TCR, value32);
+
+	// TODO: Modify later (Find the right parameters)
+	// NOTE: Fix test chip's bug (about contention windows's randomness)
+//	if (OpMode == RT_OP_MODE_IBSS || OpMode == RT_OP_MODE_AP)
+	if (check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE|WIFI_AP_STATE) == _TRUE)
+	{
+		rtw_write8(padapter, REG_RXTSF_OFFSET_CCK, 0x50);
+		rtw_write8(padapter, REG_RXTSF_OFFSET_OFDM, 0x50);
+	}
+
+	_BeaconFunctionEnable(padapter, _TRUE, _TRUE);
+
+	ResumeTxBeacon(padapter);
+	rtw_write8(padapter, bcn_ctrl_reg, rtw_read8(padapter, bcn_ctrl_reg)|BIT(1));
+}
+
+void rtl8188es_set_hal_ops(PADAPTER padapter)
+{
+	struct hal_ops *pHalFunc = &padapter->HalFunc;
+
+_func_enter_;
+
+
+	//set hardware operation functions
+	padapter->HalData = rtw_zmalloc(sizeof(HAL_DATA_TYPE));
+
+	if (padapter->HalData == NULL) {
+		RT_TRACE(_module_hci_hal_init_c_, _drv_err_,
+			 ("can't alloc memory for HAL DATA\n"));		
+	}
+
+
+	padapter->hal_data_sz = sizeof(HAL_DATA_TYPE);
+
+	pHalFunc->hal_power_on = rtl8188es_InitPowerOn;
+	pHalFunc->hal_init = &rtl8188es_hal_init;
+	pHalFunc->hal_deinit = &rtl8188es_hal_deinit;
+
+	pHalFunc->inirp_init = &rtl8188es_inirp_init;
+	pHalFunc->inirp_deinit = &rtl8188es_inirp_deinit;
+
+	pHalFunc->init_xmit_priv = &rtl8188es_init_xmit_priv;
+	pHalFunc->free_xmit_priv = &rtl8188es_free_xmit_priv;
+
+	pHalFunc->init_recv_priv = &rtl8188es_init_recv_priv;
+	pHalFunc->free_recv_priv = &rtl8188es_free_recv_priv;
+
+	pHalFunc->InitSwLeds = &rtl8188es_InitSwLeds;
+	pHalFunc->DeInitSwLeds = &rtl8188es_DeInitSwLeds;
+
+	pHalFunc->init_default_value = &rtl8188es_init_default_value;
+	pHalFunc->intf_chip_configure = &rtl8188es_interface_configure;
+	pHalFunc->read_adapter_info = &ReadAdapterInfo8188ES;
+
+	pHalFunc->enable_interrupt = &EnableInterrupt8188ESdio;
+	pHalFunc->disable_interrupt = &DisableInterrupt8188ESdio;
+
+#ifdef COWFIG_WOWLAN
+	pHalFunc->disable_interrupt = &ClearInterrupt8189ESdio;
+#endif
+
+	pHalFunc->SetHwRegHandler = &SetHwReg8188ES;
+	pHalFunc->GetHwRegHandler = &GetHwReg8188ES;
+
+	pHalFunc->GetHalDefVarHandler = &GetHalDefVar8188ESDIO;
+ 	pHalFunc->SetHalDefVarHandler = &SetHalDefVar8188ESDIO;
+
+	pHalFunc->UpdateRAMaskHandler = &UpdateHalRAMask8188ESdio;
+	pHalFunc->SetBeaconRelatedRegistersHandler = &SetBeaconRelatedRegisters8188ESdio;
+
+	pHalFunc->hal_xmit = &rtl8188es_hal_xmit;
+	pHalFunc->mgnt_xmit = &rtl8188es_mgnt_xmit;
+	pHalFunc->hal_xmitframe_enqueue = &rtl8188es_hal_xmitframe_enqueue;
+
+#ifdef CONFIG_HOSTAPD_MLME
+	pHalFunc->hostap_mgnt_xmit_entry = NULL;
+//	pHalFunc->hostap_mgnt_xmit_entry = &rtl8192cu_hostap_mgnt_xmit_entry;
+#endif
+	rtl8188e_set_hal_ops(pHalFunc);
+_func_exit_;
+
+}
+
diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/sdio/sdio_ops.c b/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/sdio/sdio_ops.c
new file mode 100755
index 00000000..35c94a00
--- /dev/null
+++ b/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/sdio/sdio_ops.c
@@ -0,0 +1,1940 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *******************************************************************************/
+#define _SDIO_OPS_C_
+
+#include <drv_types.h>
+#include <rtl8188e_hal.h>
+#include <rtl8188e_spec.h>
+
+//#define SDIO_DEBUG_IO 1
+
+#define SDIO_ERR_VAL8	0xEA
+#define SDIO_ERR_VAL16	0xEAEA
+#define SDIO_ERR_VAL32	0xEAEAEAEA
+
+extern u8 sd_f0_read8(PSDIO_DATA psdio, u32 addr, s32 *err);
+extern void sd_f0_write8(PSDIO_DATA psdio, u32 addr, s32 *err);
+
+extern s32 _sd_cmd52_read(PSDIO_DATA psdio, u32 addr, u32 cnt, void *pdata);
+extern s32 _sd_cmd52_write(PSDIO_DATA psdio, u32 addr, u32 cnt, void *pdata);
+extern s32 sd_cmd52_read(PSDIO_DATA psdio, u32 addr, u32 cnt, void *pdata);
+extern s32 sd_cmd52_write(PSDIO_DATA psdio, u32 addr, u32 cnt, void *pdata);
+
+extern u8 _sd_read8(PSDIO_DATA psdio, u32 addr, s32 *err);
+extern u8 sd_read8(PSDIO_DATA psdio, u32 addr, s32 *err);
+extern u16 sd_read16(PSDIO_DATA psdio, u32 addr, s32 *err);
+extern u32 _sd_read32(PSDIO_DATA psdio, u32 addr, s32 *err);
+extern u32 sd_read32(PSDIO_DATA psdio, u32 addr, s32 *err);
+extern s32 _sd_read(PSDIO_DATA psdio, u32 addr, u32 cnt, void *pdata);
+extern s32 sd_read(PSDIO_DATA psdio, u32 addr, u32 cnt, void *pdata);
+extern void sd_write8(PSDIO_DATA psdio, u32 addr, u8 v, s32 *err);
+extern void sd_write16(PSDIO_DATA psdio, u32 addr, u16 v, s32 *err);
+extern void _sd_write32(PSDIO_DATA psdio, u32 addr, u32 v, s32 *err);
+extern void sd_write32(PSDIO_DATA psdio, u32 addr, u32 v, s32 *err);
+extern s32 _sd_write(PSDIO_DATA psdio, u32 addr, u32 cnt, void *pdata);
+extern s32 sd_write(PSDIO_DATA psdio, u32 addr, u32 cnt, void *pdata);
+
+#ifdef CONFIG_EXT_CLK
+void EnableGpio5ClockReq(PADAPTER Adapter, u8 in_interrupt, u32 Enable);
+#endif //CONFIG_EXT_CLK
+
+//
+// Description:
+//	The following mapping is for SDIO host local register space.
+//
+// Creadted by Roger, 2011.01.31.
+//
+static void HalSdioGetCmdAddr8723ASdio(
+	IN	PADAPTER			padapter,
+	IN 	u8				DeviceID,
+	IN	u32				Addr,
+	OUT	u32*				pCmdAddr
+	)
+{
+	switch (DeviceID)
+	{
+		case SDIO_LOCAL_DEVICE_ID:
+			*pCmdAddr = ((SDIO_LOCAL_DEVICE_ID << 13) | (Addr & SDIO_LOCAL_MSK));
+			break;
+
+		case WLAN_IOREG_DEVICE_ID:
+			*pCmdAddr = ((WLAN_IOREG_DEVICE_ID << 13) | (Addr & WLAN_IOREG_MSK));
+			break;
+
+		case WLAN_TX_HIQ_DEVICE_ID:
+			*pCmdAddr = ((WLAN_TX_HIQ_DEVICE_ID << 13) | (Addr & WLAN_FIFO_MSK));
+			break;
+
+		case WLAN_TX_MIQ_DEVICE_ID:
+			*pCmdAddr = ((WLAN_TX_MIQ_DEVICE_ID << 13) | (Addr & WLAN_FIFO_MSK));
+			break;
+
+		case WLAN_TX_LOQ_DEVICE_ID:
+			*pCmdAddr = ((WLAN_TX_LOQ_DEVICE_ID << 13) | (Addr & WLAN_FIFO_MSK));
+			break;
+
+		case WLAN_RX0FF_DEVICE_ID:
+			*pCmdAddr = ((WLAN_RX0FF_DEVICE_ID << 13) | (Addr & WLAN_RX0FF_MSK));
+			break;
+
+		default:
+			break;
+	}
+}
+
+static u8 get_deviceid(u32 addr)
+{
+	u8 devideId;
+	u16 pseudoId;
+
+
+	pseudoId = (u16)(addr >> 16);
+	switch (pseudoId)
+	{
+		case 0x1025:
+			devideId = SDIO_LOCAL_DEVICE_ID;
+			break;
+
+		case 0x1026:
+			devideId = WLAN_IOREG_DEVICE_ID;
+			break;
+
+//		case 0x1027:
+//			devideId = SDIO_FIRMWARE_FIFO;
+//			break;
+
+		case 0x1031:
+			devideId = WLAN_TX_HIQ_DEVICE_ID;
+			break;
+
+		case 0x1032:
+			devideId = WLAN_TX_MIQ_DEVICE_ID;
+			break;
+
+		case 0x1033:
+			devideId = WLAN_TX_LOQ_DEVICE_ID;
+			break;
+
+		case 0x1034:
+			devideId = WLAN_RX0FF_DEVICE_ID;
+			break;
+
+		default:
+//			devideId = (u8)((addr >> 13) & 0xF);
+			devideId = WLAN_IOREG_DEVICE_ID;
+			break;
+	}
+
+	return devideId;
+}
+
+/*
+ * Ref:
+ *	HalSdioGetCmdAddr8723ASdio()
+ */
+static u32 _cvrt2ftaddr(const u32 addr, u8 *pdeviceId, u16 *poffset)
+{
+	u8 deviceId;
+	u16 offset;
+	u32 ftaddr;
+
+
+	deviceId = get_deviceid(addr);
+	offset = 0;
+
+	switch (deviceId)
+	{
+		case SDIO_LOCAL_DEVICE_ID:
+			offset = addr & SDIO_LOCAL_MSK;
+			break;
+
+		case WLAN_TX_HIQ_DEVICE_ID:
+		case WLAN_TX_MIQ_DEVICE_ID:
+		case WLAN_TX_LOQ_DEVICE_ID:
+			offset = addr & WLAN_FIFO_MSK;
+			break;
+
+		case WLAN_RX0FF_DEVICE_ID:
+			offset = addr & WLAN_RX0FF_MSK;
+			break;
+
+		case WLAN_IOREG_DEVICE_ID:
+		default:
+			deviceId = WLAN_IOREG_DEVICE_ID;
+			offset = addr & WLAN_IOREG_MSK;
+			break;
+	}
+	ftaddr = (deviceId << 13) | offset;
+
+	if (pdeviceId) *pdeviceId = deviceId;
+	if (poffset) *poffset = offset;
+
+	return ftaddr;
+}
+
+u8 _sdio_read8(PADAPTER padapter, u32 addr)
+{
+	struct dvobj_priv *psdiodev;
+	PSDIO_DATA psdio;
+	u32 ftaddr;
+	u8 val;
+
+_func_enter_;
+
+	//psdiodev = pintfhdl->pintf_dev;
+	//psdio = &psdiodev->intf_data;
+	psdiodev = adapter_to_dvobj(padapter);
+	psdio = &psdiodev->intf_data;
+
+	ftaddr = _cvrt2ftaddr(addr, NULL, NULL);
+	val = _sd_read8(psdio, ftaddr, NULL);
+
+_func_exit_;
+
+	return val;
+}
+
+u8 sdio_read8(struct intf_hdl *pintfhdl, u32 addr)
+{
+	struct dvobj_priv *psdiodev;
+	PSDIO_DATA psdio;
+	u32 ftaddr;
+	u8 val;
+
+_func_enter_;
+
+	psdiodev = pintfhdl->pintf_dev;
+	psdio = &psdiodev->intf_data;
+
+	ftaddr = _cvrt2ftaddr(addr, NULL, NULL);
+	val = sd_read8(psdio, ftaddr, NULL);
+
+_func_exit_;
+
+	return val;
+}
+
+u16 sdio_read16(struct intf_hdl *pintfhdl, u32 addr)
+{
+	struct dvobj_priv *psdiodev;
+	PSDIO_DATA psdio;
+	u32 ftaddr;
+	u16 val;
+
+_func_enter_;
+
+	psdiodev = pintfhdl->pintf_dev;
+	psdio = &psdiodev->intf_data;
+
+	ftaddr = _cvrt2ftaddr(addr, NULL, NULL);
+	sd_cmd52_read(psdio, ftaddr, 2, (u8*)&val);	
+	val = le16_to_cpu(val);
+
+_func_exit_;
+
+	return val;
+}
+
+u32 _sdio_read32(PADAPTER padapter, u32 addr)
+{
+	//PADAPTER padapter;
+	struct dvobj_priv *psdiodev;
+	PSDIO_DATA psdio;
+	u8 bMacPwrCtrlOn;
+	u8 deviceId;
+	u16 offset;
+	u32 ftaddr;
+	u8 shift;
+	u32 val;
+	s32 err;
+
+_func_enter_;
+
+	//padapter = pintfhdl->padapter;
+	//psdiodev = pintfhdl->pintf_dev;
+	psdiodev = adapter_to_dvobj(padapter);
+	psdio = &psdiodev->intf_data;
+
+	ftaddr = _cvrt2ftaddr(addr, &deviceId, &offset);
+
+	rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
+	if (((deviceId == WLAN_IOREG_DEVICE_ID) && (offset < 0x100))
+		|| (_FALSE == bMacPwrCtrlOn)
+#ifdef CONFIG_LPS_LCLK
+		|| (_TRUE == padapter->pwrctrlpriv.bFwCurrentInPSMode)
+#endif
+		)
+        {
+		err = _sd_cmd52_read(psdio, ftaddr, 4, (u8*)&val);
+#ifdef SDIO_DEBUG_IO
+		if (!err) {
+#endif
+			val = le32_to_cpu(val);
+			return val;
+#ifdef SDIO_DEBUG_IO
+		}
+
+		DBG_871X(KERN_ERR "%s: Mac Power off, Read FAIL(%d)! addr=0x%x\n", __func__, err, addr);
+		return SDIO_ERR_VAL32;
+#endif
+	}
+
+	// 4 bytes alignment
+	shift = ftaddr & 0x3;
+	if (shift == 0) {
+		val = _sd_read32(psdio, ftaddr, NULL);
+	} else {
+		u8 *ptmpbuf;
+
+		ptmpbuf = (u8*)rtw_malloc(8);
+		if (NULL == ptmpbuf) {
+			DBG_871X(KERN_ERR "%s: Allocate memory FAIL!(size=8) addr=0x%x\n", __func__, addr);
+			return SDIO_ERR_VAL32;
+		}
+
+		ftaddr &= ~(u16)0x3;
+		_sd_read(psdio, ftaddr, 8, ptmpbuf);
+		_rtw_memcpy(&val, ptmpbuf+shift, 4);
+		val = le32_to_cpu(val);
+
+		rtw_mfree(ptmpbuf, 8);
+	}
+
+_func_exit_;
+
+	return val;
+}
+
+u32 sdio_read32(struct intf_hdl *pintfhdl, u32 addr)
+{
+	PADAPTER padapter;
+	struct dvobj_priv *psdiodev;
+	PSDIO_DATA psdio;
+	u8 bMacPwrCtrlOn;
+	u8 deviceId;
+	u16 offset;
+	u32 ftaddr;
+	u8 shift;
+	u32 val;
+	s32 err;
+
+_func_enter_;
+
+	padapter = pintfhdl->padapter;
+	psdiodev = pintfhdl->pintf_dev;
+	psdio = &psdiodev->intf_data;
+
+	ftaddr = _cvrt2ftaddr(addr, &deviceId, &offset);
+
+        rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
+	if (((deviceId == WLAN_IOREG_DEVICE_ID) && (offset < 0x100))
+		|| (_FALSE == bMacPwrCtrlOn)
+#ifdef CONFIG_LPS_LCLK
+		|| (_TRUE == padapter->pwrctrlpriv.bFwCurrentInPSMode)
+#endif
+		)
+        {
+		err = sd_cmd52_read(psdio, ftaddr, 4, (u8*)&val);
+#ifdef SDIO_DEBUG_IO
+		if (!err) {
+#endif
+			val = le32_to_cpu(val);
+			return val;
+#ifdef SDIO_DEBUG_IO
+		}
+
+		DBG_871X(KERN_ERR "%s: Mac Power off, Read FAIL(%d)! addr=0x%x\n", __func__, err, addr);
+		return SDIO_ERR_VAL32;
+#endif
+	}
+
+	// 4 bytes alignment
+	shift = ftaddr & 0x3;
+	if (shift == 0) {
+		val = sd_read32(psdio, ftaddr, NULL);
+	} else {
+		u8 *ptmpbuf;
+				
+		ptmpbuf = (u8*)rtw_malloc(8);
+		if (NULL == ptmpbuf) {
+			DBG_871X(KERN_ERR "%s: Allocate memory FAIL!(size=8) addr=0x%x\n", __func__, addr);
+			return SDIO_ERR_VAL32;
+		}
+
+		ftaddr &= ~(u16)0x3;
+		sd_read(psdio, ftaddr, 8, ptmpbuf);
+		_rtw_memcpy(&val, ptmpbuf+shift, 4);
+		val = le32_to_cpu(val);
+
+		rtw_mfree(ptmpbuf, 8);
+	}
+
+_func_exit_;
+
+	return val;
+}
+
+s32 sdio_readN(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8* pbuf)
+{
+	PADAPTER padapter;
+	struct dvobj_priv *psdiodev;
+	PSDIO_DATA psdio;
+	u8 bMacPwrCtrlOn;
+	u8 deviceId;
+	u16 offset;
+	u32 ftaddr;
+	u8 shift;
+	s32 err;
+
+_func_enter_;
+
+	padapter = pintfhdl->padapter;
+	psdiodev = pintfhdl->pintf_dev;
+	psdio = &psdiodev->intf_data;
+	err = 0;
+
+	ftaddr = _cvrt2ftaddr(addr, &deviceId, &offset);
+
+	rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
+	if (((deviceId == WLAN_IOREG_DEVICE_ID) && (offset < 0x100))
+		|| (_FALSE == bMacPwrCtrlOn)
+#ifdef CONFIG_LPS_LCLK
+		|| (_TRUE == padapter->pwrctrlpriv.bFwCurrentInPSMode)
+#endif
+		)
+	{
+		err = sd_cmd52_read(psdio, ftaddr, cnt, pbuf);
+		return err;
+	}
+
+	// 4 bytes alignment
+	shift = ftaddr & 0x3;
+	if (shift == 0) {
+		err = sd_read(psdio, ftaddr, cnt, pbuf);
+	} else {
+		u8 *ptmpbuf;
+		u32 n;
+
+		ftaddr &= ~(u16)0x3;
+		n = cnt + shift;
+		ptmpbuf = rtw_malloc(n);
+		if (NULL == ptmpbuf) return -1;
+		err = sd_read(psdio, ftaddr, n, ptmpbuf);
+		if (!err)
+			_rtw_memcpy(pbuf, ptmpbuf+shift, cnt);
+		rtw_mfree(ptmpbuf, n);
+	}
+
+_func_exit_;
+
+	return err;
+}
+
+s32 sdio_write8(struct intf_hdl *pintfhdl, u32 addr, u8 val)
+{
+	struct dvobj_priv *psdiodev;
+	PSDIO_DATA psdio;
+	u32 ftaddr;
+	s32 err;
+
+_func_enter_;
+
+	psdiodev = pintfhdl->pintf_dev;
+	psdio = &psdiodev->intf_data;
+
+	ftaddr = _cvrt2ftaddr(addr, NULL, NULL);
+	sd_write8(psdio, ftaddr, val, &err);
+
+_func_exit_;
+
+	return err;
+}
+
+s32 sdio_write16(struct intf_hdl *pintfhdl, u32 addr, u16 val)
+{
+	struct dvobj_priv *psdiodev;
+	PSDIO_DATA psdio;
+	u32 ftaddr;
+	u8 shift;
+	s32 err;
+
+_func_enter_;
+
+	psdiodev = pintfhdl->pintf_dev;
+	psdio = &psdiodev->intf_data;
+
+	ftaddr = _cvrt2ftaddr(addr, NULL, NULL);
+	val = cpu_to_le16(val);
+	err = sd_cmd52_write(psdio, ftaddr, 2, (u8*)&val);
+
+_func_exit_;
+
+	return err;
+}
+
+s32 _sdio_write32(PADAPTER padapter, u32 addr, u32 val)
+{
+	//PADAPTER padapter;
+	struct dvobj_priv *psdiodev;
+	PSDIO_DATA psdio;
+	u8 bMacPwrCtrlOn;
+	u8 deviceId;
+	u16 offset;
+	u32 ftaddr;
+	u8 shift;
+	s32 err;
+
+_func_enter_;
+
+	//padapter = pintfhdl->padapter;
+	//psdiodev = pintfhdl->pintf_dev;
+	psdiodev = adapter_to_dvobj(padapter);
+	psdio = &psdiodev->intf_data;
+	err = 0;
+
+	ftaddr = _cvrt2ftaddr(addr, &deviceId, &offset);
+
+	rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
+	if (((deviceId == WLAN_IOREG_DEVICE_ID) && (offset < 0x100))
+		|| (_FALSE == bMacPwrCtrlOn)
+#ifdef CONFIG_LPS_LCLK
+		|| (_TRUE == padapter->pwrctrlpriv.bFwCurrentInPSMode)
+#endif
+		)
+	{
+		val = cpu_to_le32(val);
+		err = _sd_cmd52_write(psdio, ftaddr, 4, (u8*)&val);
+		return err;
+	}
+
+	// 4 bytes alignment
+	shift = ftaddr & 0x3;
+#if 1
+	if (shift == 0)
+	{
+		_sd_write32(psdio, ftaddr, val, &err);
+	}
+	else
+	{
+		val = cpu_to_le32(val);
+		err = _sd_cmd52_write(psdio, ftaddr, 4, (u8*)&val);
+	}
+#else
+	if (shift == 0) {
+		sd_write32(psdio, ftaddr, val, &err);
+	} else {
+		u8 *ptmpbuf;
+
+		ptmpbuf = (u8*)rtw_malloc(8);
+		if (NULL == ptmpbuf) return (-1);
+
+		ftaddr &= ~(u16)0x3;
+		err = sd_read(psdio, ftaddr, 8, ptmpbuf);
+		if (err) {
+			_rtw_mfree(ptmpbuf, 8);
+			return err;
+		}
+		val = cpu_to_le32(val);
+		_rtw_memcpy(ptmpbuf+shift, &val, 4);
+		err = sd_write(psdio, ftaddr, 8, ptmpbuf);
+
+		rtw_mfree(ptmpbuf, 8);
+	}
+#endif
+
+_func_exit_;
+
+	return err;
+}
+
+
+s32 sdio_write32(struct intf_hdl *pintfhdl, u32 addr, u32 val)
+{
+	PADAPTER padapter;
+	struct dvobj_priv *psdiodev;
+	PSDIO_DATA psdio;
+	u8 bMacPwrCtrlOn;
+	u8 deviceId;
+	u16 offset;
+	u32 ftaddr;
+	u8 shift;
+	s32 err;
+
+_func_enter_;
+
+	padapter = pintfhdl->padapter;
+	psdiodev = pintfhdl->pintf_dev;
+	psdio = &psdiodev->intf_data;
+	err = 0;
+
+	ftaddr = _cvrt2ftaddr(addr, &deviceId, &offset);
+
+	rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
+	if (((deviceId == WLAN_IOREG_DEVICE_ID) && (offset < 0x100))
+		|| (_FALSE == bMacPwrCtrlOn)
+#ifdef CONFIG_LPS_LCLK
+		|| (_TRUE == padapter->pwrctrlpriv.bFwCurrentInPSMode)
+#endif
+		)
+	{
+		val = cpu_to_le32(val);
+		err = sd_cmd52_write(psdio, ftaddr, 4, (u8*)&val);
+		return err;
+	}
+
+	// 4 bytes alignment
+	shift = ftaddr & 0x3;
+#if 1
+	if (shift == 0)
+	{
+		sd_write32(psdio, ftaddr, val, &err);
+	}
+	else
+	{
+		val = cpu_to_le32(val);
+		err = sd_cmd52_write(psdio, ftaddr, 4, (u8*)&val);
+	}
+#else
+	if (shift == 0) {	
+		sd_write32(psdio, ftaddr, val, &err);
+	} else {
+		u8 *ptmpbuf;
+
+		ptmpbuf = (u8*)rtw_malloc(8);
+		if (NULL == ptmpbuf) return (-1);
+
+		ftaddr &= ~(u16)0x3;
+		err = sd_read(psdio, ftaddr, 8, ptmpbuf);
+		if (err) {
+			_rtw_mfree(ptmpbuf, 8);
+			return err;
+		}
+		val = cpu_to_le32(val);
+		_rtw_memcpy(ptmpbuf+shift, &val, 4);
+		err = sd_write(psdio, ftaddr, 8, ptmpbuf);
+		
+		rtw_mfree(ptmpbuf, 8);
+	}
+#endif	
+
+_func_exit_;
+
+	return err;
+}
+
+s32 sdio_writeN(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8* pbuf)
+{
+	PADAPTER padapter;
+	struct dvobj_priv *psdiodev;
+	PSDIO_DATA psdio;
+	u8 bMacPwrCtrlOn;
+	u8 deviceId;
+	u16 offset;
+	u32 ftaddr;
+	u8 shift;
+	s32 err;
+
+_func_enter_;
+
+	padapter = pintfhdl->padapter;
+	psdiodev = pintfhdl->pintf_dev;
+	psdio = &psdiodev->intf_data;
+	err = 0;
+
+	ftaddr = _cvrt2ftaddr(addr, &deviceId, &offset);
+
+	rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
+	if (((deviceId == WLAN_IOREG_DEVICE_ID) && (offset < 0x100))
+		|| (_FALSE == bMacPwrCtrlOn)
+#ifdef CONFIG_LPS_LCLK
+		|| (_TRUE == padapter->pwrctrlpriv.bFwCurrentInPSMode)
+#endif
+		)
+	{
+		err = sd_cmd52_write(psdio, ftaddr, cnt, pbuf);
+		return err;
+	}
+
+	shift = ftaddr & 0x3;
+	if (shift == 0) {
+		err = sd_write(psdio, ftaddr, cnt, pbuf);
+	} else {
+		u8 *ptmpbuf;
+		u32 n;
+
+		ftaddr &= ~(u16)0x3;
+		n = cnt + shift;
+		ptmpbuf = rtw_malloc(n);
+		if (NULL == ptmpbuf) return -1;
+		err = sd_read(psdio, ftaddr, 4, ptmpbuf);
+		if (err) {
+			rtw_mfree(ptmpbuf, n);
+			return err;
+		}
+		_rtw_memcpy(ptmpbuf+shift, pbuf, cnt);
+		err = sd_write(psdio, ftaddr, n, ptmpbuf);
+		rtw_mfree(ptmpbuf, n);
+	}
+
+_func_exit_;
+
+	return err;
+}
+
+void sdio_read_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem)
+{
+	s32 err;
+
+_func_enter_;
+
+	err = sdio_readN(pintfhdl, addr, cnt, rmem);
+
+_func_exit_;
+}
+
+void sdio_write_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem)
+{
+_func_enter_;
+
+	sdio_writeN(pintfhdl, addr, cnt, wmem);
+
+_func_exit_;
+}
+
+/*
+ * Description:
+ *	Read from RX FIFO
+ *	Round read size to block size,
+ *	and make sure data transfer will be done in one command.
+ *
+ * Parameters:
+ *	pintfhdl	a pointer of intf_hdl
+ *	addr		port ID
+ *	cnt			size to read
+ *	rmem		address to put data
+ *
+ * Return:
+ *	_SUCCESS(1)		Success
+ *	_FAIL(0)		Fail
+ */
+static u32 sdio_read_port(
+	struct intf_hdl *pintfhdl,
+	u32 addr,
+	u32 cnt,
+	u8 *mem)
+{
+	PADAPTER padapter = pintfhdl->padapter;
+	PSDIO_DATA psdio= &adapter_to_dvobj(padapter)->intf_data;
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	s32 err;
+
+	HalSdioGetCmdAddr8723ASdio(padapter, addr, pHalData->SdioRxFIFOCnt++, &addr);
+
+
+	cnt = _RND4(cnt);
+	if (cnt > psdio->block_transfer_len)
+		cnt = _RND(cnt, psdio->block_transfer_len);
+	
+//	cnt = sdio_align_size(cnt);
+
+	err = _sd_read(psdio, addr, cnt, mem);
+	//err = sd_read(psdio, addr, cnt, mem);
+	
+
+
+	if (err) return _FAIL;
+	return _SUCCESS;
+}
+
+/*
+ * Description:
+ *	Write to TX FIFO
+ *	Align write size block size,
+ *	and make sure data could be written in one command.
+ *
+ * Parameters:
+ *	pintfhdl	a pointer of intf_hdl
+ *	addr		port ID
+ *	cnt			size to write
+ *	wmem		data pointer to write
+ *
+ * Return:
+ *	_SUCCESS(1)		Success
+ *	_FAIL(0)		Fail
+ */
+static u32 sdio_write_port(
+	struct intf_hdl *pintfhdl,
+	u32 addr,
+	u32 cnt,
+	u8 *mem)
+{
+	PADAPTER padapter;
+	PSDIO_DATA psdio;
+	s32 err;
+	struct xmit_buf *xmitbuf = (struct xmit_buf *)mem;
+
+	padapter = pintfhdl->padapter;
+	psdio = &adapter_to_dvobj(padapter)->intf_data;
+
+	cnt = _RND4(cnt);
+	HalSdioGetCmdAddr8723ASdio(padapter, addr, cnt >> 2, &addr);
+
+	if (cnt > psdio->block_transfer_len)
+		cnt = _RND(cnt, psdio->block_transfer_len);
+//	cnt = sdio_align_size(cnt);
+
+	err = sd_write(psdio, addr, cnt, xmitbuf->pdata);
+
+	rtw_sctx_done_err(&xmitbuf->sctx,
+		err ? RTW_SCTX_DONE_WRITE_PORT_ERR : RTW_SCTX_DONE_SUCCESS);
+	
+	if (err)
+	{
+		DBG_871X("%s, error=%d\n", __func__, err);
+
+		return _FAIL;
+	}
+	return _SUCCESS;
+}
+
+void sdio_set_intf_ops(struct _io_ops *pops)
+{
+_func_enter_;
+
+	pops->_read8 = &sdio_read8;
+	pops->_read16 = &sdio_read16;
+	pops->_read32 = &sdio_read32;
+	pops->_read_mem = &sdio_read_mem;
+	pops->_read_port = &sdio_read_port;
+
+	pops->_write8 = &sdio_write8;
+	pops->_write16 = &sdio_write16;
+	pops->_write32 = &sdio_write32;
+	pops->_writeN = &sdio_writeN;
+	pops->_write_mem = &sdio_write_mem;
+	pops->_write_port = &sdio_write_port;
+
+_func_exit_;
+}
+
+/*
+ * Todo: align address to 4 bytes.
+ */
+s32 _sdio_local_read(
+	PADAPTER	padapter,
+	u32		addr,
+	u32		cnt,
+	u8		*pbuf)
+{
+	PSDIO_DATA psdio;
+	u8 bMacPwrCtrlOn;
+	s32 err;
+	u8 *ptmpbuf;
+	u32 n;
+
+
+	psdio = &adapter_to_dvobj(padapter)->intf_data;
+
+	HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr);
+
+	rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
+	if ((_FALSE == bMacPwrCtrlOn)
+#ifdef CONFIG_LPS_LCLK
+//		|| (_TRUE == padapter->pwrctrlpriv.bFwCurrentInPSMode)
+#endif
+		)
+	{
+		err = _sd_cmd52_read(psdio, addr, cnt, pbuf);
+		return err;
+	}
+
+        n = RND4(cnt);
+	ptmpbuf = (u8*)rtw_malloc(n);
+	if(!ptmpbuf)
+		return (-1);
+
+	err = _sd_read(psdio, addr, n, ptmpbuf);
+	if (!err)
+		_rtw_memcpy(pbuf, ptmpbuf, cnt);
+
+	if(ptmpbuf)
+		rtw_mfree(ptmpbuf, n);	
+
+	return err;
+}
+
+/*
+ * Todo: align address to 4 bytes.
+ */
+s32 sdio_local_read(
+	PADAPTER	padapter,
+	u32		addr,
+	u32		cnt,
+	u8		*pbuf)
+{
+	PSDIO_DATA psdio;
+	u8 bMacPwrCtrlOn;
+	s32 err;
+	u8 *ptmpbuf;
+	u32 n;
+
+
+	psdio = &adapter_to_dvobj(padapter)->intf_data;
+
+	HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr);
+
+	rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
+	if ((_FALSE == bMacPwrCtrlOn)
+#ifdef CONFIG_LPS_LCLK
+		|| (_TRUE == padapter->pwrctrlpriv.bFwCurrentInPSMode)
+#endif
+		)
+	{
+		err = sd_cmd52_read(psdio, addr, cnt, pbuf);
+		return err;
+	}
+
+        n = RND4(cnt);
+	ptmpbuf = (u8*)rtw_malloc(n);
+	if(!ptmpbuf)
+		return (-1);
+
+	err = sd_read(psdio, addr, n, ptmpbuf);
+	if (!err)
+		_rtw_memcpy(pbuf, ptmpbuf, cnt);
+
+	if(ptmpbuf)
+		rtw_mfree(ptmpbuf, n);	
+
+	return err;
+}
+
+/*
+ * Todo: align address to 4 bytes.
+ */
+s32 _sdio_local_write(
+	PADAPTER	padapter,
+	u32		addr,
+	u32		cnt,
+	u8		*pbuf)
+{
+	PSDIO_DATA psdio;
+	u8 bMacPwrCtrlOn;
+	s32 err;
+	u8 *ptmpbuf;
+
+	if(addr & 0x3)
+		DBG_8192C("%s, address must be 4 bytes alignment\n", __FUNCTION__);
+
+	if(cnt  & 0x3)
+		DBG_8192C("%s, size must be the multiple of 4 \n", __FUNCTION__);
+
+	psdio = &adapter_to_dvobj(padapter)->intf_data;
+
+	HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr);
+
+	rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
+	if ((_FALSE == bMacPwrCtrlOn)
+#ifdef CONFIG_LPS_LCLK
+//		|| (_TRUE == padapter->pwrctrlpriv.bFwCurrentInPSMode)
+#endif
+		)
+	{
+		err = _sd_cmd52_write(psdio, addr, cnt, pbuf);
+		return err;
+	}
+
+        ptmpbuf = (u8*)rtw_malloc(cnt);
+	if(!ptmpbuf)
+		return (-1);
+
+	_rtw_memcpy(ptmpbuf, pbuf, cnt);
+
+	err = _sd_write(psdio, addr, cnt, ptmpbuf);
+	
+	if (ptmpbuf)
+		rtw_mfree(ptmpbuf, cnt);
+
+	return err;
+}
+
+/*
+ * Todo: align address to 4 bytes.
+ */
+s32 sdio_local_write(
+	PADAPTER	padapter,
+	u32		addr,
+	u32		cnt,
+	u8		*pbuf)
+{
+	PSDIO_DATA psdio;
+	u8 bMacPwrCtrlOn;
+	s32 err;
+	u8 *ptmpbuf;
+
+	if(addr & 0x3)
+		DBG_8192C("%s, address must be 4 bytes alignment\n", __FUNCTION__);
+
+	if(cnt  & 0x3)
+		DBG_8192C("%s, size must be the multiple of 4 \n", __FUNCTION__);
+
+	psdio = &adapter_to_dvobj(padapter)->intf_data;
+
+	HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr);
+
+	rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
+	if ((_FALSE == bMacPwrCtrlOn)
+#ifdef CONFIG_LPS_LCLK
+		|| (_TRUE == padapter->pwrctrlpriv.bFwCurrentInPSMode)
+#endif
+		)
+	{
+		err = sd_cmd52_write(psdio, addr, cnt, pbuf);
+		return err;
+	}
+
+        ptmpbuf = (u8*)rtw_malloc(cnt);
+	if(!ptmpbuf)
+		return (-1);
+
+	_rtw_memcpy(ptmpbuf, pbuf, cnt);
+
+	err = sd_write(psdio, addr, cnt, ptmpbuf);
+
+	if (ptmpbuf)
+		rtw_mfree(ptmpbuf, cnt);
+
+	return err;
+}
+
+u8 SdioLocalCmd52Read1Byte(PADAPTER padapter, u32 addr)
+{
+	PSDIO_DATA psdio;
+	u8 val = 0;
+
+
+	psdio = &adapter_to_dvobj(padapter)->intf_data;
+	HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr);
+	sd_cmd52_read(psdio, addr, 1, &val);
+
+	return val;
+}
+
+u16 SdioLocalCmd52Read2Byte(PADAPTER padapter, u32 addr)
+{
+	PSDIO_DATA psdio;
+	u16 val = 0;
+
+
+	psdio = &adapter_to_dvobj(padapter)->intf_data;
+	HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr);
+	sd_cmd52_read(psdio, addr, 2, (u8*)&val);
+
+	val = le16_to_cpu(val);
+
+	return val;
+}
+
+u32 SdioLocalCmd52Read4Byte(PADAPTER padapter, u32 addr)
+{
+	PSDIO_DATA psdio;
+	u32 val = 0;
+
+
+	psdio = &adapter_to_dvobj(padapter)->intf_data;
+	HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr);
+	sd_cmd52_read(psdio, addr, 4, (u8*)&val);
+
+	val = le32_to_cpu(val);
+
+	return val;
+}
+
+u32 SdioLocalCmd53Read4Byte(PADAPTER padapter, u32 addr)
+{
+	PSDIO_DATA psdio;
+	u8 bMacPwrCtrlOn;
+	u32 val;
+
+
+	val = 0;
+	psdio = &adapter_to_dvobj(padapter)->intf_data;
+	HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr);
+	rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
+	if ((_FALSE == bMacPwrCtrlOn)
+#ifdef CONFIG_LPS_LCLK
+		|| (_TRUE == padapter->pwrctrlpriv.bFwCurrentInPSMode)
+#endif
+		)
+	{
+		sd_cmd52_read(psdio, addr, 4, (u8*)&val);
+		val = le32_to_cpu(val);
+	}
+	else
+	val = sd_read32(psdio, addr, NULL);
+
+	return val;
+}
+
+void SdioLocalCmd52Write1Byte(PADAPTER padapter, u32 addr, u8 v)
+{
+	PSDIO_DATA psdio;
+
+
+	psdio = &adapter_to_dvobj(padapter)->intf_data;
+	HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr);
+	sd_cmd52_write(psdio, addr, 1, &v);
+}
+
+void SdioLocalCmd52Write2Byte(PADAPTER padapter, u32 addr, u16 v)
+{
+	PSDIO_DATA psdio;
+
+
+	psdio = &adapter_to_dvobj(padapter)->intf_data;
+	HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr);
+	v = cpu_to_le16(v);
+	sd_cmd52_write(psdio, addr, 2, (u8*)&v);
+}
+
+void SdioLocalCmd52Write4Byte(PADAPTER padapter, u32 addr, u32 v)
+{
+	PSDIO_DATA psdio;
+
+
+	psdio = &adapter_to_dvobj(padapter)->intf_data;
+	HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr);
+	v = cpu_to_le32(v);
+	sd_cmd52_write(psdio, addr, 4, (u8*)&v);
+}
+
+#if 0
+void
+DumpLoggedInterruptHistory8723Sdio(
+	PADAPTER		padapter
+)
+{
+	HAL_DATA_TYPE	*pHalData=GET_HAL_DATA(padapter);
+	u4Byte				DebugLevel = DBG_LOUD;
+
+	if (DBG_Var.DbgPrintIsr == 0)
+		return;
+
+	DBG_ChkDrvResource(padapter);
+
+
+	if(pHalData->InterruptLog.nISR_RX_REQUEST)
+		RT_TRACE(COMP_SEND|COMP_RECV, DebugLevel, ("# RX_REQUEST[%ld]\t\n", pHalData->InterruptLog.nISR_RX_REQUEST));
+
+	if(pHalData->InterruptLog.nISR_AVAL)
+		RT_TRACE(COMP_SEND|COMP_RECV, DebugLevel, ("# AVAL[%ld]\t\n", pHalData->InterruptLog.nISR_AVAL));
+
+	if(pHalData->InterruptLog.nISR_TXERR)
+		RT_TRACE(COMP_SEND|COMP_RECV, DebugLevel, ("# TXERR[%ld]\t\n", pHalData->InterruptLog.nISR_TXERR));
+
+	if(pHalData->InterruptLog.nISR_RXERR)
+		RT_TRACE(COMP_SEND|COMP_RECV, DebugLevel, ("# RXERR[%ld]\t\n", pHalData->InterruptLog.nISR_RXERR));
+
+	if(pHalData->InterruptLog.nISR_TXFOVW)
+		RT_TRACE(COMP_SEND|COMP_RECV, DebugLevel, ("# TXFOVW[%ld]\t\n", pHalData->InterruptLog.nISR_TXFOVW));
+
+	if(pHalData->InterruptLog.nISR_RXFOVW)
+		RT_TRACE(COMP_SEND|COMP_RECV, DebugLevel, ("# RXFOVW[%ld]\t\n", pHalData->InterruptLog.nISR_RXFOVW));
+
+	if(pHalData->InterruptLog.nISR_TXBCNOK)
+		RT_TRACE(COMP_SEND|COMP_RECV, DebugLevel, ("# TXBCNOK[%ld]\t\n", pHalData->InterruptLog.nISR_TXBCNOK));
+
+	if(pHalData->InterruptLog.nISR_TXBCNERR)
+		RT_TRACE(COMP_SEND|COMP_RECV, DebugLevel, ("# TXBCNERR[%ld]\t\n", pHalData->InterruptLog.nISR_TXBCNERR));
+
+	if(pHalData->InterruptLog.nISR_BCNERLY_INT)
+		RT_TRACE(COMP_SEND|COMP_RECV, DebugLevel, ("# BCNERLY_INT[%ld]\t\n", pHalData->InterruptLog.nISR_BCNERLY_INT));
+
+	if(pHalData->InterruptLog.nISR_C2HCMD)
+		RT_TRACE(COMP_SEND|COMP_RECV, DebugLevel, ("# C2HCMD[%ld]\t\n", pHalData->InterruptLog.nISR_C2HCMD));
+
+	if(pHalData->InterruptLog.nISR_CPWM1)
+		RT_TRACE(COMP_SEND|COMP_RECV, DebugLevel, ("# CPWM1L[%ld]\t\n", pHalData->InterruptLog.nISR_CPWM1));
+
+	if(pHalData->InterruptLog.nISR_CPWM2)
+		RT_TRACE(COMP_SEND|COMP_RECV, DebugLevel, ("# CPWM2[%ld]\t\n", pHalData->InterruptLog.nISR_CPWM2));
+
+	if(pHalData->InterruptLog.nISR_HSISR_IND)
+		RT_TRACE(COMP_SEND|COMP_RECV, DebugLevel, ("# HSISR_IND[%ld]\t\n", pHalData->InterruptLog.nISR_HSISR_IND));
+
+	if(pHalData->InterruptLog.nISR_GTINT3_IND)
+		RT_TRACE(COMP_SEND|COMP_RECV, DebugLevel, ("# GTINT3_IND[%ld]\t\n", pHalData->InterruptLog.nISR_GTINT3_IND));
+
+	if(pHalData->InterruptLog.nISR_GTINT4_IND)
+		RT_TRACE(COMP_SEND|COMP_RECV, DebugLevel, ("# GTINT4_IND[%ld]\t\n", pHalData->InterruptLog.nISR_GTINT4_IND));
+
+	if(pHalData->InterruptLog.nISR_PSTIMEOUT)
+		RT_TRACE(COMP_SEND|COMP_RECV, DebugLevel, ("# PSTIMEOUT[%ld]\t\n", pHalData->InterruptLog.nISR_PSTIMEOUT));
+
+	if(pHalData->InterruptLog.nISR_OCPINT)
+		RT_TRACE(COMP_SEND|COMP_RECV, DebugLevel, ("# OCPINT[%ld]\t\n", pHalData->InterruptLog.nISR_OCPINT));
+
+	if(pHalData->InterruptLog.nISR_ATIMEND)
+		RT_TRACE(COMP_SEND|COMP_RECV, DebugLevel, ("# ATIMEND[%ld]\t\n", pHalData->InterruptLog.nISR_ATIMEND));
+
+	if(pHalData->InterruptLog.nISR_ATIMEND_E)
+		RT_TRACE(COMP_SEND|COMP_RECV, DebugLevel, ("# ATIMEND_E[%ld]\t\n", pHalData->InterruptLog.nISR_ATIMEND_E));
+
+	if(pHalData->InterruptLog.nISR_CTWEND)
+		RT_TRACE(COMP_SEND|COMP_RECV, DebugLevel, ("# CTWEND[%ld]\t\n", pHalData->InterruptLog.nISR_CTWEND));
+}
+
+void
+LogInterruptHistory8723Sdio(
+	PADAPTER			padapter,
+	PRT_ISR_CONTENT	pIsrContent
+)
+{
+	HAL_DATA_TYPE	*pHalData=GET_HAL_DATA(padapter);
+
+	if((pHalData->IntrMask[0] & SDIO_HIMR_RX_REQUEST_MSK) &&
+		(pIsrContent->IntArray[0] & SDIO_HISR_RX_REQUEST))
+		pHalData->InterruptLog.nISR_RX_REQUEST ++;
+	if((pHalData->IntrMask[0] & SDIO_HIMR_AVAL_MSK) &&
+		(pIsrContent->IntArray[0] & SDIO_HISR_AVAL))
+		pHalData->InterruptLog.nISR_AVAL++;
+	if((pHalData->IntrMask[0] & SDIO_HIMR_TXERR_MSK) &&
+		(pIsrContent->IntArray[0] & SDIO_HISR_TXERR))
+		pHalData->InterruptLog.nISR_TXERR++;
+	if((pHalData->IntrMask[0] & SDIO_HIMR_RXERR_MSK) &&
+		(pIsrContent->IntArray[0] & SDIO_HISR_RXERR))
+		pHalData->InterruptLog.nISR_RXERR++;
+	if((pHalData->IntrMask[0] & SDIO_HIMR_TXFOVW_MSK) &&
+		(pIsrContent->IntArray[0] & SDIO_HISR_TXFOVW))
+		pHalData->InterruptLog.nISR_TXFOVW++;
+	if((pHalData->IntrMask[0] & SDIO_HIMR_RXFOVW_MSK) &&
+		(pIsrContent->IntArray[0] & SDIO_HISR_RXFOVW))
+		pHalData->InterruptLog.nISR_RXFOVW++;
+	if((pHalData->IntrMask[0] & SDIO_HIMR_TXBCNOK_MSK) &&
+		(pIsrContent->IntArray[0] & SDIO_HISR_TXBCNOK))
+		pHalData->InterruptLog.nISR_TXBCNOK++;
+	if((pHalData->IntrMask[0] & SDIO_HIMR_TXBCNERR_MSK) &&
+		(pIsrContent->IntArray[0] & SDIO_HISR_TXBCNERR))
+		pHalData->InterruptLog.nISR_TXBCNERR++;
+	if((pHalData->IntrMask[0] & SDIO_HIMR_BCNERLY_INT_MSK) &&
+		(pIsrContent->IntArray[0] & SDIO_HISR_BCNERLY_INT))
+		pHalData->InterruptLog.nISR_BCNERLY_INT ++;
+	if((pHalData->IntrMask[0] & SDIO_HIMR_C2HCMD_MSK) &&
+		(pIsrContent->IntArray[0] & SDIO_HISR_C2HCMD))
+		pHalData->InterruptLog.nISR_C2HCMD++;
+	if((pHalData->IntrMask[0] & SDIO_HIMR_CPWM1_MSK) &&
+		(pIsrContent->IntArray[0] & SDIO_HISR_CPWM1))
+		pHalData->InterruptLog.nISR_CPWM1++;
+	if((pHalData->IntrMask[0] & SDIO_HIMR_CPWM2_MSK) &&
+		(pIsrContent->IntArray[0] & SDIO_HISR_CPWM2))
+		pHalData->InterruptLog.nISR_CPWM2++;
+	if((pHalData->IntrMask[0] & SDIO_HIMR_HSISR_IND_MSK) &&
+		(pIsrContent->IntArray[0] & SDIO_HISR_HSISR_IND))
+		pHalData->InterruptLog.nISR_HSISR_IND++;
+	if((pHalData->IntrMask[0] & SDIO_HIMR_GTINT3_IND_MSK) &&
+		(pIsrContent->IntArray[0] & SDIO_HISR_GTINT3_IND))
+		pHalData->InterruptLog.nISR_GTINT3_IND++;
+	if((pHalData->IntrMask[0] & SDIO_HIMR_GTINT4_IND_MSK) &&
+		(pIsrContent->IntArray[0] & SDIO_HISR_GTINT4_IND))
+		pHalData->InterruptLog.nISR_GTINT4_IND++;
+	if((pHalData->IntrMask[0] & SDIO_HIMR_PSTIMEOUT_MSK) &&
+		(pIsrContent->IntArray[0] & SDIO_HISR_PSTIMEOUT))
+		pHalData->InterruptLog.nISR_PSTIMEOUT++;
+	if((pHalData->IntrMask[0] & SDIO_HIMR_OCPINT_MSK) &&
+		(pIsrContent->IntArray[0] & SDIO_HISR_OCPINT))
+		pHalData->InterruptLog.nISR_OCPINT++;
+	if((pHalData->IntrMask[0] & SDIO_HIMR_ATIMEND_MSK) &&
+		(pIsrContent->IntArray[0] & SDIO_HISR_ATIMEND))
+		pHalData->InterruptLog.nISR_ATIMEND++;
+	if((pHalData->IntrMask[0] & SDIO_HIMR_ATIMEND_E_MSK) &&
+		(pIsrContent->IntArray[0] & SDIO_HISR_ATIMEND_E))
+		pHalData->InterruptLog.nISR_ATIMEND_E++;
+	if((pHalData->IntrMask[0] & SDIO_HIMR_CTWEND_MSK) &&
+		(pIsrContent->IntArray[0] & SDIO_HISR_CTWEND))
+		pHalData->InterruptLog.nISR_CTWEND++;
+
+}
+
+void
+DumpHardwareProfile8723Sdio(
+	IN	PADAPTER		padapter
+)
+{
+	DumpLoggedInterruptHistory8723Sdio(padapter);
+}
+#endif
+
+//
+//	Description:
+//		Initialize SDIO Host Interrupt Mask configuration variables for future use.
+//
+//	Assumption:
+//		Using SDIO Local register ONLY for configuration.
+//
+//	Created by Roger, 2011.02.11.
+//
+void InitInterrupt8188ESdio(PADAPTER padapter)
+{
+	HAL_DATA_TYPE *pHalData;
+
+
+	pHalData = GET_HAL_DATA(padapter);
+	pHalData->sdio_himr = (u32)(			\
+								SDIO_HIMR_RX_REQUEST_MSK			|
+//								SDIO_HIMR_AVAL_MSK					|
+//								SDIO_HIMR_TXERR_MSK				|
+//								SDIO_HIMR_RXERR_MSK				|
+//								SDIO_HIMR_TXFOVW_MSK				|
+//								SDIO_HIMR_RXFOVW_MSK				|
+//								SDIO_HIMR_TXBCNOK_MSK				|
+//								SDIO_HIMR_TXBCNERR_MSK			       |
+#ifdef CONFIG_EXT_CLK //for sprd
+								SDIO_HIMR_BCNERLY_INT_MSK			|
+#endif //CONFIG_EXT_CLK
+//								SDIO_HIMR_C2HCMD_MSK				|
+#ifdef CONFIG_LPS_LCLK
+								SDIO_HIMR_CPWM1_MSK				|
+								SDIO_HIMR_CPWM2_MSK				|
+#endif
+//								SDIO_HIMR_HSISR_IND_MSK			|
+//								SDIO_HIMR_GTINT3_IND_MSK			|
+//								SDIO_HIMR_GTINT4_IND_MSK			|
+//								SDIO_HIMR_PSTIMEOUT_MSK			|
+//								SDIO_HIMR_OCPINT_MSK				|
+//								SDIO_HIMR_ATIMEND_MSK				|
+//								SDIO_HIMR_ATIMEND_E_MSK			|
+//								SDIO_HIMR_CTWEND_MSK				|
+								0);
+}
+
+//
+//	Description:
+//		Clear corresponding SDIO Host ISR interrupt service.
+//
+//	Assumption:
+//		Using SDIO Local register ONLY for configuration.
+//
+//	Created by Roger, 2011.02.11.
+//
+void ClearInterrupt8723ASdio(PADAPTER padapter)
+{
+	u32 tmp = 0;
+	tmp = SdioLocalCmd52Read4Byte(padapter, SDIO_REG_HISR);
+	SdioLocalCmd52Write4Byte(padapter, SDIO_REG_HISR, tmp);
+//	padapter->IsrContent.IntArray[0] = 0;
+	padapter->IsrContent = 0;
+}
+
+//
+//	Description:
+//		Enalbe SDIO Host Interrupt Mask configuration on SDIO local domain.
+//
+//	Assumption:
+//		1. Using SDIO Local register ONLY for configuration.
+//		2. PASSIVE LEVEL
+//
+//	Created by Roger, 2011.02.11.
+//
+void EnableInterrupt8188ESdio(PADAPTER padapter)
+{
+	PHAL_DATA_TYPE pHalData;
+	u32 himr;
+
+#ifdef CONFIG_CONCURRENT_MODE
+	if ((padapter->isprimary == _FALSE) && padapter->pbuddy_adapter){
+		padapter = padapter->pbuddy_adapter;
+	}
+#endif
+	pHalData = GET_HAL_DATA(padapter);
+	himr = cpu_to_le32(pHalData->sdio_himr);
+	sdio_local_write(padapter, SDIO_REG_HIMR, 4, (u8*)&himr);
+
+
+	//
+	// <Roger_Notes> There are some C2H CMDs have been sent before system interrupt is enabled, e.g., C2H, CPWM.
+	// So we need to clear all C2H events that FW has notified, otherwise FW won't schedule any commands anymore.
+	// 2011.10.19.
+	//
+	rtw_write8(padapter, REG_C2HEVT_CLEAR, C2H_EVT_HOST_CLOSE);
+
+}
+
+//
+//	Description:
+//		Disable SDIO Host IMR configuration to mask unnecessary interrupt service.
+//
+//	Assumption:
+//		Using SDIO Local register ONLY for configuration.
+//
+//	Created by Roger, 2011.02.11.
+//
+void DisableInterrupt8188ESdio(PADAPTER padapter)
+{
+	u32 himr;
+
+#ifdef CONFIG_CONCURRENT_MODE
+	if ((padapter->isprimary == _FALSE) && padapter->pbuddy_adapter){
+		padapter = padapter->pbuddy_adapter;
+	}
+#endif
+	himr = cpu_to_le32(SDIO_HIMR_DISABLED);
+	sdio_local_write(padapter, SDIO_REG_HIMR, 4, (u8*)&himr);
+
+}
+
+//
+//	Description:
+//		Update SDIO Host Interrupt Mask configuration on SDIO local domain.
+//
+//	Assumption:
+//		1. Using SDIO Local register ONLY for configuration.
+//		2. PASSIVE LEVEL
+//
+//	Created by Roger, 2011.02.11.
+//
+void UpdateInterruptMask8188ESdio(PADAPTER padapter, u32 AddMSR, u32 RemoveMSR)
+{
+	HAL_DATA_TYPE *pHalData;
+
+#ifdef CONFIG_CONCURRENT_MODE
+	if ((padapter->isprimary == _FALSE) && padapter->pbuddy_adapter){
+		padapter = padapter->pbuddy_adapter;
+	}
+#endif
+	pHalData = GET_HAL_DATA(padapter);
+
+	if (AddMSR)
+		pHalData->sdio_himr |= AddMSR;
+
+	if (RemoveMSR)
+		pHalData->sdio_himr &= (~RemoveMSR);
+
+	DisableInterrupt8188ESdio(padapter);
+	EnableInterrupt8188ESdio(padapter);
+}
+
+#ifdef CONFIG_WOWLAN
+void ClearInterrupt8189ESdio(PADAPTER padapter)
+{
+    HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(padapter);
+    u32 v32; 
+
+    pHalData->sdio_hisr &= pHalData->sdio_himr;
+
+    // clear HISR
+    v32 = pHalData->sdio_hisr & MASK_SDIO_HISR_CLEAR;
+    if (v32) {
+        v32 = cpu_to_le32(v32);
+        _sdio_local_write(padapter, SDIO_REG_HISR, 4, (u8*)&v32);
+    }    
+}
+#endif
+
+#ifdef CONFIG_MAC_LOOPBACK_DRIVER
+static void sd_recv_loopback(PADAPTER padapter, u32 size)
+{
+	PLOOPBACKDATA ploopback;
+	u32 readsize, allocsize;
+	u8 *preadbuf;
+
+
+	readsize = size;
+	DBG_8192C("%s: read size=%d\n", __func__, readsize);
+	allocsize = _RND(readsize, adapter_to_dvobj(padapter)->intf_data.block_transfer_len);
+
+	ploopback = padapter->ploopback;
+	if (ploopback) {
+		ploopback->rxsize = readsize;
+		preadbuf = ploopback->rxbuf;
+	}
+	else {
+		preadbuf = rtw_malloc(allocsize);
+		if (preadbuf == NULL) {
+			DBG_8192C("%s: malloc fail size=%d\n", __func__, allocsize);
+			return;
+		}
+	}
+
+//	rtw_read_port(padapter, WLAN_RX0FF_DEVICE_ID, readsize, preadbuf);
+	sdio_read_port(&padapter->iopriv.intf, WLAN_RX0FF_DEVICE_ID, readsize, preadbuf);
+
+	if (ploopback)
+		_rtw_up_sema(&ploopback->sema);
+	else {
+		u32 i;
+
+		DBG_8192C("%s: drop pkt\n", __func__);
+		for (i = 0; i < readsize; i+=4) {
+			DBG_8192C("%08X", *(u32*)(preadbuf + i));
+			if ((i+4) & 0x1F) printk(" ");
+			else printk("\n");
+		}
+		printk("\n");
+		rtw_mfree(preadbuf, allocsize);
+	}
+}
+#endif // CONFIG_MAC_LOOPBACK_DRIVER
+
+#ifdef CONFIG_SDIO_RX_COPY
+static struct recv_buf* sd_recv_rxfifo(PADAPTER padapter, u32 size)
+{
+	u32 readsize, ret;
+	u8 *preadbuf;
+	struct recv_priv *precvpriv;
+	struct recv_buf	*precvbuf;
+
+
+	readsize = size;
+
+	//3 1. alloc recvbuf
+	precvpriv = &padapter->recvpriv;
+	precvbuf = rtw_dequeue_recvbuf(&precvpriv->free_recv_buf_queue);
+	if (precvbuf == NULL) {
+		RT_TRACE(_module_hci_ops_os_c_, _drv_err_, ("%s: alloc recvbuf FAIL!\n", __FUNCTION__));
+		return NULL;
+	}
+
+	//3 2. alloc skb
+	if (precvbuf->pskb == NULL) {
+		SIZE_PTR tmpaddr=0;
+		SIZE_PTR alignment=0;
+
+		DBG_871X("%s: alloc_skb for rx buffer\n", __FUNCTION__);
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) // http://www.mail-archive.com/netdev@vger.kernel.org/msg17214.html
+		precvbuf->pskb = __dev_alloc_skb(MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ, GFP_KERNEL);
+#else
+		precvbuf->pskb = __netdev_alloc_skb(padapter->pnetdev, MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ, GFP_KERNEL);
+#endif
+
+		if(precvbuf->pskb)
+		{
+			precvbuf->pskb->dev = padapter->pnetdev;
+
+			tmpaddr = (SIZE_PTR)precvbuf->pskb->data;
+			alignment = tmpaddr & (RECVBUFF_ALIGN_SZ-1);
+			skb_reserve(precvbuf->pskb, (RECVBUFF_ALIGN_SZ - alignment));
+
+			precvbuf->phead = precvbuf->pskb->head;
+			precvbuf->pdata = precvbuf->pskb->data;
+			precvbuf->ptail = skb_tail_pointer(precvbuf->pskb);
+			precvbuf->pend = skb_end_pointer(precvbuf->pskb);
+			precvbuf->len = 0;
+		}
+
+		if (precvbuf->pskb == NULL) {
+			DBG_871X("%s: alloc_skb fail! read=%d\n", __FUNCTION__, readsize);
+			return NULL;
+		}
+	}
+
+	//3 3. read data from rxfifo
+	preadbuf = precvbuf->pdata;
+//	rtw_read_port(padapter, WLAN_RX0FF_DEVICE_ID, readsize, preadbuf);
+	ret = sdio_read_port(&padapter->iopriv.intf, WLAN_RX0FF_DEVICE_ID, readsize, preadbuf);
+	if (ret == _FAIL) {
+		RT_TRACE(_module_hci_ops_os_c_, _drv_err_, ("%s: read port FAIL!\n", __FUNCTION__));
+		return NULL;
+	}
+	
+
+	//3 4. init recvbuf
+	precvbuf->len = readsize;
+
+	return precvbuf;
+}
+#else
+static struct recv_buf* sd_recv_rxfifo(PADAPTER padapter, u32 size)
+{
+	u32 readsize, allocsize, ret;
+	u8 *preadbuf;
+	_pkt *ppkt;
+	struct recv_priv *precvpriv;
+	struct recv_buf	*precvbuf;
+
+
+	readsize = size;
+
+	//3 1. alloc skb
+	// align to block size
+	allocsize = _RND(readsize, adapter_to_dvobj(padapter)->intf_data.block_transfer_len);
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) // http://www.mail-archive.com/netdev@vger.kernel.org/msg17214.html
+	ppkt = __dev_alloc_skb(allocsize, GFP_KERNEL);
+#else
+	ppkt = __netdev_alloc_skb(padapter->pnetdev, allocsize, GFP_KERNEL);
+#endif
+	if (ppkt == NULL) {
+		RT_TRACE(_module_hci_ops_os_c_, _drv_err_, ("%s: alloc_skb fail! alloc=%d read=%d\n", __FUNCTION__, allocsize, readsize));
+		return NULL;
+	}
+
+	//3 2. read data from rxfifo
+	preadbuf = skb_put(ppkt, readsize);
+//	rtw_read_port(padapter, WLAN_RX0FF_DEVICE_ID, readsize, preadbuf);
+	ret = sdio_read_port(&padapter->iopriv.intf, WLAN_RX0FF_DEVICE_ID, readsize, preadbuf);
+	if (ret == _FAIL) {
+		dev_kfree_skb_any(ppkt);
+		RT_TRACE(_module_hci_ops_os_c_, _drv_err_, ("%s: read port FAIL!\n", __FUNCTION__));
+		return NULL;
+	}
+
+	//3 3. alloc recvbuf
+	precvpriv = &padapter->recvpriv;
+	precvbuf = rtw_dequeue_recvbuf(&precvpriv->free_recv_buf_queue);
+	if (precvbuf == NULL) {
+		dev_kfree_skb_any(ppkt);
+		RT_TRACE(_module_hci_ops_os_c_, _drv_err_, ("%s: alloc recvbuf FAIL!\n", __FUNCTION__));
+		return NULL;
+	}
+
+	//3 4. init recvbuf
+	precvbuf->pskb = ppkt;
+
+	precvbuf->len = ppkt->len;
+
+	precvbuf->phead = ppkt->head;
+	precvbuf->pdata = ppkt->data;
+	precvbuf->ptail = skb_tail_pointer(precvbuf->pskb);
+	precvbuf->pend = skb_end_pointer(precvbuf->pskb);
+
+	return precvbuf;
+}
+#endif
+
+static void sd_rxhandler(PADAPTER padapter, struct recv_buf *precvbuf)
+{
+	struct recv_priv *precvpriv;
+	_queue *ppending_queue;
+
+
+	precvpriv = &padapter->recvpriv;
+	ppending_queue = &precvpriv->recv_buf_pending_queue;
+
+	//3 1. enqueue recvbuf
+	rtw_enqueue_recvbuf(precvbuf, ppending_queue);
+	
+	//3 2. schedule tasklet
+#ifdef PLATFORM_LINUX
+	tasklet_schedule(&precvpriv->recv_tasklet);
+#endif
+}
+
+void sd_int_dpc(PADAPTER padapter)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+
+	if (pHalData->sdio_hisr & SDIO_HISR_CPWM1)
+	{
+		struct reportpwrstate_parm report;
+
+		_sdio_local_read(padapter, SDIO_REG_HCPWM1, 1, &report.state);
+#ifdef CONFIG_LPS_LCLK
+		//88e's cpwm value only change BIT0, so driver need to add PS_STATE_S2 for LPS flow.
+		//modify by Thomas. 2012/4/2.
+
+#ifdef CONFIG_EXT_CLK //for sprd
+		if(report.state & BIT(4)) //indicate FW entering 32k
+		{
+			u8 chk_cnt = 0;
+
+			do{
+				if(_sdio_read8(padapter, 0x90)&BIT(0))//FW in 32k already
+				{
+					struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
+
+					if(pwrpriv->rpwm < PS_STATE_S2)
+					{
+						//DBG_871X("disable ext clk when FW in LPS-32K already!\n");
+						EnableGpio5ClockReq(padapter, _TRUE, 0);
+					}
+
+					break;
+				}
+
+				chk_cnt++;
+
+			}while(chk_cnt<10);
+
+			if(chk_cnt==10)
+			{
+				DBG_871X("polling fw in 32k already, fail!\n");
+			}
+
+		}
+		else //indicate fw leaving 32K
+#endif //CONFIG_EXT_CLK
+		{
+		report.state |= PS_STATE_S2;
+		//cpwm_int_hdl(padapter, &report);
+		_set_workitem(&padapter->pwrctrlpriv.cpwm_event);
+		}
+#endif
+	}
+
+#ifdef CONFIG_WOWLAN
+	if (pHalData->sdio_hisr & SDIO_HISR_CPWM2) {
+		u32	value;
+		value = rtw_read32(padapter, SDIO_LOCAL_BASE+SDIO_REG_HISR);
+		DBG_871X_LEVEL(_drv_always_, "Reset SDIO HISR(0x%08x) original:0x%08x\n",
+			SDIO_LOCAL_BASE+SDIO_REG_HISR, value);
+		value |= BIT19;
+		rtw_write32(padapter, SDIO_LOCAL_BASE+SDIO_REG_HISR, value);
+
+		value = rtw_read8(padapter, SDIO_LOCAL_BASE+SDIO_REG_HIMR+2);
+		DBG_871X_LEVEL(_drv_always_, "Reset SDIO HIMR CPWM2(0x%08x) original:0x%02x\n",
+			SDIO_LOCAL_BASE+SDIO_REG_HIMR + 2, value);
+	}
+#endif
+	if (pHalData->sdio_hisr & SDIO_HISR_TXERR)
+	{
+		u8 *status;
+		u32 addr;
+	
+		status = _rtw_malloc(4);
+		if (status)
+		{
+			addr = REG_TXDMA_STATUS;
+			HalSdioGetCmdAddr8723ASdio(padapter, WLAN_IOREG_DEVICE_ID, addr, &addr);
+			_sd_read(&adapter_to_dvobj(padapter)->intf_data, addr, 4, status);
+			_sd_write(&adapter_to_dvobj(padapter)->intf_data, addr, 4, status);
+			DBG_8192C("%s: SDIO_HISR_TXERR (0x%08x)\n", __func__, le32_to_cpu(*(u32*)status));
+			_rtw_mfree(status, 4);
+		} else {
+			DBG_8192C("%s: SDIO_HISR_TXERR, but can't allocate memory to read status!\n", __func__);
+		}		
+	}
+
+#ifdef CONFIG_INTERRUPT_BASED_TXBCN
+
+	#ifdef  CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
+	if (pHalData->sdio_hisr & SDIO_HISR_BCNERLY_INT)
+	#endif
+	#ifdef  CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
+	if (pHalData->sdio_hisr & (SDIO_HISR_TXBCNOK|SDIO_HISR_TXBCNERR))
+	#endif	
+	{		
+		struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+
+		#if 0 //for debug
+		if (pHalData->sdio_hisr & SDIO_HISR_BCNERLY_INT)
+			DBG_8192C("%s: SDIO_HISR_BCNERLY_INT\n", __func__);
+		
+		if (pHalData->sdio_hisr & SDIO_HISR_TXBCNOK)	
+			DBG_8192C("%s: SDIO_HISR_TXBCNOK\n", __func__);
+	
+		if (pHalData->sdio_hisr & SDIO_HISR_TXBCNERR)	
+			DBG_8192C("%s: SDIO_HISR_TXBCNERR\n", __func__);
+		#endif
+
+		
+		if(check_fwstate(pmlmepriv, WIFI_AP_STATE))
+		{
+			//send_beacon(padapter);
+			if(pmlmepriv->update_bcn == _TRUE)
+			{
+				//tx_beacon_hdl(padapter, NULL);
+				set_tx_beacon_cmd(padapter);
+			}
+		}
+#ifdef CONFIG_CONCURRENT_MODE
+		if(check_buddy_fwstate(padapter, WIFI_AP_STATE))
+		{
+			//send_beacon(padapter);
+			if(padapter->pbuddy_adapter->mlmepriv.update_bcn == _TRUE)
+			{
+				//tx_beacon_hdl(padapter, NULL);
+				set_tx_beacon_cmd(padapter->pbuddy_adapter);
+			}
+		}
+#endif
+	}
+#endif //CONFIG_INTERRUPT_BASED_TXBCN
+
+#ifdef CONFIG_EXT_CLK
+	if (pHalData->sdio_hisr & SDIO_HISR_BCNERLY_INT)
+	{
+		struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+
+		if(check_fwstate(pmlmepriv, _FW_LINKED) && check_fwstate(pmlmepriv, WIFI_STATION_STATE))
+		{
+			//DBG_8192C("BCNERLY_INT for enabling ext clk\n");
+			EnableGpio5ClockReq(padapter, _TRUE, 1);
+		}
+	}
+#endif //CONFIG_EXT_CLK
+
+	if (pHalData->sdio_hisr & SDIO_HISR_C2HCMD)
+	{
+		DBG_8192C("%s: C2H Command\n", __func__);
+	}
+
+	if (pHalData->sdio_hisr & SDIO_HISR_RX_REQUEST)
+	{
+		struct recv_buf *precvbuf;
+
+		//DBG_8192C("%s: RX Request, size=%d\n", __func__, phal->SdioRxFIFOSize);
+		pHalData->sdio_hisr ^= SDIO_HISR_RX_REQUEST;
+#ifdef CONFIG_MAC_LOOPBACK_DRIVER
+		sd_recv_loopback(padapter, pHalData->SdioRxFIFOSize);
+#else
+		do {
+			//Sometimes rx length will be zero. driver need to use cmd53 read again.
+			if(pHalData->SdioRxFIFOSize == 0)
+			{
+				u8 data[4];
+
+				_sdio_local_read(padapter, SDIO_REG_RX0_REQ_LEN, 4, data);
+
+				pHalData->SdioRxFIFOSize = le16_to_cpu(*(u16*)data);
+			}
+
+			if(pHalData->SdioRxFIFOSize)
+			{
+				precvbuf = sd_recv_rxfifo(padapter, pHalData->SdioRxFIFOSize);
+
+				pHalData->SdioRxFIFOSize = 0;
+
+				if (precvbuf)
+					sd_rxhandler(padapter, precvbuf);
+				else
+					break;
+			}
+			else
+				break;
+#ifdef CONFIG_SDIO_DISABLE_RXFIFO_POLLING_LOOP			
+		} while (0);
+#else
+		} while (1);
+#endif
+#endif
+
+	}
+	
+}
+
+void sd_int_hdl(PADAPTER padapter)
+{
+	u8 data[6];
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	if ((padapter->bDriverStopped == _TRUE) ||
+	    (padapter->bSurpriseRemoved == _TRUE))
+		return;
+
+	_sdio_local_read(padapter, SDIO_REG_HISR, 6, data);
+	pHalData->sdio_hisr = le32_to_cpu(*(u32*)data);
+	pHalData->SdioRxFIFOSize = le16_to_cpu(*(u16*)&data[4]);
+
+	if (pHalData->sdio_hisr & pHalData->sdio_himr)
+	{
+		u32 v32;
+
+		pHalData->sdio_hisr &= pHalData->sdio_himr;
+
+		// clear HISR
+		v32 = pHalData->sdio_hisr & MASK_SDIO_HISR_CLEAR;
+		if (v32) {
+			v32 = cpu_to_le32(v32);
+			_sdio_local_write(padapter, SDIO_REG_HISR, 4, (u8*)&v32);
+		}
+
+		sd_int_dpc(padapter);
+		
+	} 
+	else 
+	{
+		RT_TRACE(_module_hci_ops_c_, _drv_err_,
+				("%s: HISR(0x%08x) and HIMR(0x%08x) not match!\n",
+				__FUNCTION__, pHalData->sdio_hisr, pHalData->sdio_himr));
+	}
+	
+}
+
+//
+//	Description:
+//		Query SDIO Local register to query current the number of Free TxPacketBuffer page.
+//
+//	Assumption:
+//		1. Running at PASSIVE_LEVEL
+//		2. RT_TX_SPINLOCK is NOT acquired.
+//
+//	Created by Roger, 2011.01.28.
+//
+u8 HalQueryTxBufferStatus8189ESdio(PADAPTER padapter)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	u32 NumOfFreePage;
+//	_irqL irql;
+
+
+	pHalData = GET_HAL_DATA(padapter);
+
+	NumOfFreePage = SdioLocalCmd53Read4Byte(padapter, SDIO_REG_FREE_TXPG);
+
+//	_enter_critical_bh(&phal->SdioTxFIFOFreePageLock, &irql);
+	_rtw_memcpy(pHalData->SdioTxFIFOFreePage, &NumOfFreePage, 4);
+	RT_TRACE(_module_hci_ops_c_, _drv_notice_,
+			("%s: Free page for HIQ(%#x),MIDQ(%#x),LOWQ(%#x),PUBQ(%#x)\n",
+			__FUNCTION__,
+			pHalData->SdioTxFIFOFreePage[HI_QUEUE_IDX],
+			pHalData->SdioTxFIFOFreePage[MID_QUEUE_IDX],
+			pHalData->SdioTxFIFOFreePage[LOW_QUEUE_IDX],
+			pHalData->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX]));
+//	_exit_critical_bh(&phal->SdioTxFIFOFreePageLock, &irql);
+
+	return _TRUE;
+}
+
+#ifdef CONFIG_WOWLAN
+u8 RecvOnePkt(PADAPTER padapter, u32 size)
+{
+	struct recv_buf *precvbuf;
+	struct dvobj_priv *psddev;
+	PSDIO_DATA psdio_data;
+	struct sdio_func *func;
+
+	u8 res = _FALSE;
+
+	DBG_8192C("+%s: size: %d+\n", __func__, size);
+	
+	if (padapter == NULL) {
+		DBG_8192C(KERN_ERR "%s: padapter is NULL!\n", __func__);
+		return _FALSE;
+	}
+	
+	psddev = padapter->dvobj;
+	psdio_data = &psddev->intf_data;
+	func = psdio_data->func;
+
+	if(size) {
+		sdio_claim_host(func);
+		precvbuf = sd_recv_rxfifo(padapter, size);
+
+		if (precvbuf) {
+			//printk("Completed Recv One Pkt.\n");
+			sd_rxhandler(padapter, precvbuf);
+			res = _TRUE;
+		}else{
+			res = _FALSE;
+		}
+		sdio_release_host(func);
+	}
+	DBG_8192C("-%s-\n", __func__);
+	return res;
+}
+#endif //CONFIG_WOWLAN
diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/usb/rtl8188eu_led.c b/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/usb/rtl8188eu_led.c
new file mode 100755
index 00000000..712965a8
--- /dev/null
+++ b/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/usb/rtl8188eu_led.c
@@ -0,0 +1,170 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+
+#include <drv_conf.h>
+#include <osdep_service.h>
+#include <drv_types.h>
+#include <rtl8188e_hal.h>
+
+//================================================================================
+// LED object.
+//================================================================================
+
+
+//================================================================================
+//	Prototype of protected function.
+//================================================================================
+
+
+//================================================================================
+// LED_819xUsb routines. 
+//================================================================================
+
+//
+//	Description:
+//		Turn on LED according to LedPin specified.
+//
+void
+SwLedOn(
+	_adapter			*padapter, 
+	PLED_871x		pLed
+)
+{
+	u8	LedCfg;
+	//HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+
+	if( (padapter->bSurpriseRemoved == _TRUE) || ( padapter->bDriverStopped == _TRUE))
+	{
+		return;
+	}
+
+	LedCfg = rtw_read8(padapter, REG_LEDCFG2);
+	switch(pLed->LedPin)
+	{	
+		case LED_PIN_LED0:
+			rtw_write8(padapter, REG_LEDCFG2, (LedCfg&0xf0)|BIT5|BIT6); // SW control led0 on.
+			break;
+
+		case LED_PIN_LED1:
+			rtw_write8(padapter, REG_LEDCFG2, (LedCfg&0x0f)|BIT5); // SW control led1 on.
+			break;
+
+		default:
+			break;
+	}
+	
+	pLed->bLedOn = _TRUE;
+}
+
+
+//
+//	Description:
+//		Turn off LED according to LedPin specified.
+//
+void
+SwLedOff(
+	_adapter			*padapter, 
+	PLED_871x		pLed
+)
+{
+	u8	LedCfg;
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+
+	if((padapter->bSurpriseRemoved == _TRUE) || ( padapter->bDriverStopped == _TRUE))	
+	{
+		goto exit;
+	}
+
+
+	LedCfg = rtw_read8(padapter, REG_LEDCFG2);//0x4E
+
+	switch(pLed->LedPin)
+	{
+		case LED_PIN_LED0:
+			if(pHalData->bLedOpenDrain == _TRUE) // Open-drain arrangement for controlling the LED)
+			{
+				LedCfg &= 0x90; // Set to software control.				
+				rtw_write8(padapter, REG_LEDCFG2, (LedCfg|BIT3));				
+				LedCfg = rtw_read8(padapter, REG_MAC_PINMUX_CFG);
+				LedCfg &= 0xFE;
+				rtw_write8(padapter, REG_MAC_PINMUX_CFG, LedCfg);									
+			}
+			else
+			{
+				rtw_write8(padapter, REG_LEDCFG2, (LedCfg|BIT3|BIT5|BIT6));
+			}
+			break;
+
+		case LED_PIN_LED1:
+			LedCfg &= 0x0f; // Set to software control.
+			rtw_write8(padapter, REG_LEDCFG2, (LedCfg|BIT3));
+			break;
+
+		default:
+			break;
+	}
+exit:
+	pLed->bLedOn = _FALSE;
+	
+}
+
+//================================================================================
+// Interface to manipulate LED objects.
+//================================================================================
+
+
+//================================================================================
+// Default LED behavior.
+//================================================================================
+
+//
+//	Description:
+//		Initialize all LED_871x objects.
+//
+void
+rtl8188eu_InitSwLeds(
+	_adapter	*padapter
+	)
+{
+	struct led_priv *pledpriv = &(padapter->ledpriv);
+
+	pledpriv->LedControlHandler = LedControl871x;
+
+	InitLed871x(padapter, &(pledpriv->SwLed0), LED_PIN_LED0);
+
+	InitLed871x(padapter,&(pledpriv->SwLed1), LED_PIN_LED1);
+}
+
+
+//
+//	Description:
+//		DeInitialize all LED_819xUsb objects.
+//
+void
+rtl8188eu_DeInitSwLeds(
+	_adapter	*padapter
+	)
+{
+	struct led_priv	*ledpriv = &(padapter->ledpriv);
+
+	DeInitLed871x( &(ledpriv->SwLed0) );
+	DeInitLed871x( &(ledpriv->SwLed1) );
+}
+
diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/usb/rtl8188eu_recv.c b/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/usb/rtl8188eu_recv.c
new file mode 100755
index 00000000..726c6c8c
--- /dev/null
+++ b/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/usb/rtl8188eu_recv.c
@@ -0,0 +1,239 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#define _RTL8188EU_RECV_C_
+#include <drv_conf.h>
+#include <osdep_service.h>
+#include <drv_types.h>
+#include <recv_osdep.h>
+#include <mlme_osdep.h>
+#include <ip.h>
+#include <if_ether.h>
+#include <ethernet.h>
+
+#include <usb_ops.h>
+
+#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS)
+
+#error "Shall be Linux or Windows, but not both!\n"
+
+#endif
+
+#include <wifi.h>
+#include <circ_buf.h>
+
+#include <rtl8188e_hal.h>
+
+
+void rtl8188eu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf)
+{
+
+	precvbuf->transfer_len = 0;
+
+	precvbuf->len = 0;
+
+	precvbuf->ref_cnt = 0;
+
+	if(precvbuf->pbuf)
+	{
+		precvbuf->pdata = precvbuf->phead = precvbuf->ptail = precvbuf->pbuf;
+		precvbuf->pend = precvbuf->pdata + MAX_RECVBUF_SZ;
+	}
+
+}
+
+int	rtl8188eu_init_recv_priv(_adapter *padapter)
+{
+	struct recv_priv	*precvpriv = &padapter->recvpriv;
+	int	i, res = _SUCCESS;
+	struct recv_buf *precvbuf;
+
+#ifdef CONFIG_RECV_THREAD_MODE	
+	_rtw_init_sema(&precvpriv->recv_sema, 0);//will be removed
+	_rtw_init_sema(&precvpriv->terminate_recvthread_sema, 0);//will be removed
+#endif
+
+#ifdef PLATFORM_LINUX
+	tasklet_init(&precvpriv->recv_tasklet,
+	     (void(*)(unsigned long))rtl8188eu_recv_tasklet,
+	     (unsigned long)padapter);
+#endif
+
+#ifdef CONFIG_USB_INTERRUPT_IN_PIPE
+#ifdef PLATFORM_LINUX
+	precvpriv->int_in_urb = usb_alloc_urb(0, GFP_KERNEL);
+	if(precvpriv->int_in_urb == NULL){
+		res= _FAIL;
+		DBG_8192C("alloc_urb for interrupt in endpoint fail !!!!\n");
+		goto exit;
+	}
+#endif
+	precvpriv->int_in_buf = rtw_zmalloc(INTERRUPT_MSG_FORMAT_LEN);
+	if(precvpriv->int_in_buf == NULL){
+		res= _FAIL;
+		DBG_8192C("alloc_mem for interrupt in endpoint fail !!!!\n");
+		goto exit;
+	}
+#endif
+
+	//init recv_buf
+	_rtw_init_queue(&precvpriv->free_recv_buf_queue);
+
+#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX
+	_rtw_init_queue(&precvpriv->recv_buf_pending_queue);
+#endif	// CONFIG_USE_USB_BUFFER_ALLOC_RX
+
+	precvpriv->pallocated_recv_buf = rtw_zmalloc(NR_RECVBUFF *sizeof(struct recv_buf) + 4);
+	if(precvpriv->pallocated_recv_buf==NULL){
+		res= _FAIL;
+		RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("alloc recv_buf fail!\n"));
+		goto exit;
+	}
+	_rtw_memset(precvpriv->pallocated_recv_buf, 0, NR_RECVBUFF *sizeof(struct recv_buf) + 4);
+
+	precvpriv->precv_buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(precvpriv->pallocated_recv_buf), 4);
+	//precvpriv->precv_buf = precvpriv->pallocated_recv_buf + 4 -
+	//						((uint) (precvpriv->pallocated_recv_buf) &(4-1));
+
+
+	precvbuf = (struct recv_buf*)precvpriv->precv_buf;
+
+	for(i=0; i < NR_RECVBUFF ; i++)
+	{
+		_rtw_init_listhead(&precvbuf->list);
+
+		_rtw_spinlock_init(&precvbuf->recvbuf_lock);
+
+		precvbuf->alloc_sz = MAX_RECVBUF_SZ;
+
+		res = rtw_os_recvbuf_resource_alloc(padapter, precvbuf);
+		if(res==_FAIL)
+			break;
+
+		precvbuf->ref_cnt = 0;
+		precvbuf->adapter =padapter;
+
+
+		//rtw_list_insert_tail(&precvbuf->list, &(precvpriv->free_recv_buf_queue.queue));
+
+		precvbuf++;
+
+	}
+
+	precvpriv->free_recv_buf_queue_cnt = NR_RECVBUFF;
+
+#ifdef PLATFORM_LINUX
+
+	skb_queue_head_init(&precvpriv->rx_skb_queue);
+
+#ifdef CONFIG_PREALLOC_RECV_SKB
+	{
+		int i;
+		SIZE_PTR tmpaddr=0;
+		SIZE_PTR alignment=0;
+		struct sk_buff *pskb=NULL;
+
+		skb_queue_head_init(&precvpriv->free_recv_skb_queue);
+
+		for(i=0; i<NR_PREALLOC_RECV_SKB; i++)
+		{
+
+	#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) // http://www.mail-archive.com/netdev@vger.kernel.org/msg17214.html
+			pskb = __dev_alloc_skb(MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ, GFP_KERNEL);
+	#else
+			pskb = __netdev_alloc_skb(padapter->pnetdev, MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ, GFP_KERNEL);
+	#endif
+
+			if(pskb)
+			{
+				pskb->dev = padapter->pnetdev;
+
+				tmpaddr = (SIZE_PTR)pskb->data;
+				alignment = tmpaddr & (RECVBUFF_ALIGN_SZ-1);
+				skb_reserve(pskb, (RECVBUFF_ALIGN_SZ - alignment));
+
+				skb_queue_tail(&precvpriv->free_recv_skb_queue, pskb);
+			}
+
+			pskb=NULL;
+
+		}
+	}
+#endif
+
+#endif
+
+exit:
+
+	return res;
+
+}
+
+void rtl8188eu_free_recv_priv (_adapter *padapter)
+{
+	int	i;
+	struct recv_buf	*precvbuf;
+	struct recv_priv	*precvpriv = &padapter->recvpriv;
+
+	precvbuf = (struct recv_buf *)precvpriv->precv_buf;
+
+	for(i=0; i < NR_RECVBUFF ; i++)
+	{
+		rtw_os_recvbuf_resource_free(padapter, precvbuf);
+		precvbuf++;
+	}
+
+	if(precvpriv->pallocated_recv_buf)
+		rtw_mfree(precvpriv->pallocated_recv_buf, NR_RECVBUFF *sizeof(struct recv_buf) + 4);
+
+#ifdef CONFIG_USB_INTERRUPT_IN_PIPE
+#ifdef PLATFORM_LINUX
+	if(precvpriv->int_in_urb)
+	{
+		usb_free_urb(precvpriv->int_in_urb);
+	}
+#endif//PLATFORM_LINUX
+
+	if(precvpriv->int_in_buf)
+		rtw_mfree(precvpriv->int_in_buf, INTERRUPT_MSG_FORMAT_LEN);
+#endif//CONFIG_USB_INTERRUPT_IN_PIPE
+
+#ifdef PLATFORM_LINUX
+
+	if (skb_queue_len(&precvpriv->rx_skb_queue)) {
+		DBG_8192C(KERN_WARNING "rx_skb_queue not empty\n");
+	}
+
+	skb_queue_purge(&precvpriv->rx_skb_queue);
+
+#ifdef CONFIG_PREALLOC_RECV_SKB
+
+	if (skb_queue_len(&precvpriv->free_recv_skb_queue)) {
+		DBG_8192C(KERN_WARNING "free_recv_skb_queue not empty, %d\n", skb_queue_len(&precvpriv->free_recv_skb_queue));
+	}
+
+	skb_queue_purge(&precvpriv->free_recv_skb_queue);
+
+#endif
+
+#endif
+
+}
+
+
diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/usb/rtl8188eu_xmit.c b/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/usb/rtl8188eu_xmit.c
new file mode 100755
index 00000000..af09c833
--- /dev/null
+++ b/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/usb/rtl8188eu_xmit.c
@@ -0,0 +1,1374 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#define _RTL8188E_XMIT_C_
+#include <drv_conf.h>
+#include <osdep_service.h>
+#include <drv_types.h>
+#include <rtw_byteorder.h>
+#include <wifi.h>
+#include <osdep_intf.h>
+#include <circ_buf.h>
+#include <usb_ops.h>
+#include <rtl8188e_hal.h>
+
+#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS)
+#error "Shall be Linux or Windows, but not both!\n"
+#endif
+
+s32	rtl8188eu_init_xmit_priv(_adapter *padapter)
+{
+	struct xmit_priv	*pxmitpriv = &padapter->xmitpriv;
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+
+#ifdef PLATFORM_LINUX
+	tasklet_init(&pxmitpriv->xmit_tasklet,
+	     (void(*)(unsigned long))rtl8188eu_xmit_tasklet,
+	     (unsigned long)padapter);
+#endif
+#ifdef CONFIG_TX_EARLY_MODE
+	pHalData->bEarlyModeEnable = padapter->registrypriv.early_mode;
+#endif
+
+	return _SUCCESS;
+}
+
+void	rtl8188eu_free_xmit_priv(_adapter *padapter)
+{
+}
+
+u8 urb_zero_packet_chk(_adapter *padapter, int sz)
+{
+#if 1
+	u8 blnSetTxDescOffset;
+	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(padapter);
+	blnSetTxDescOffset = (((sz + TXDESC_SIZE) %  pHalData->UsbBulkOutSize) ==0)?1:0;
+	
+#else
+
+	struct dvobj_priv	*pdvobj = adapter_to_dvobj(padapter);	
+	if ( pdvobj->ishighspeed )
+	{
+		if ( ( (sz + TXDESC_SIZE) % 512 ) == 0 ) {
+			blnSetTxDescOffset = 1;
+		} else {
+			blnSetTxDescOffset = 0;
+		}
+	}
+	else
+	{
+		if ( ( (sz + TXDESC_SIZE) % 64 ) == 0 ) 	{
+			blnSetTxDescOffset = 1;
+		} else {
+			blnSetTxDescOffset = 0;
+		}
+	}
+#endif	
+	return blnSetTxDescOffset;
+	
+}
+
+void rtl8188eu_cal_txdesc_chksum(struct tx_desc	*ptxdesc)
+{
+		u16	*usPtr = (u16*)ptxdesc;
+		u32 count = 16;		// (32 bytes / 2 bytes per XOR) => 16 times
+		u32 index;
+		u16 checksum = 0;
+
+		//Clear first
+		ptxdesc->txdw7 &= cpu_to_le32(0xffff0000);
+	
+		for(index = 0 ; index < count ; index++){
+			checksum = checksum ^ le16_to_cpu(*(usPtr + index));
+		}
+
+		ptxdesc->txdw7 |= cpu_to_le32(0x0000ffff&checksum);	
+
+}
+//
+// Description: In normal chip, we should send some packet to Hw which will be used by Fw
+//			in FW LPS mode. The function is to fill the Tx descriptor of this packets, then
+//			Fw can tell Hw to send these packet derectly.
+//
+void rtl8188e_fill_fake_txdesc(
+	PADAPTER	padapter,
+	u8*			pDesc,
+	u32			BufferLen,
+	u8			IsPsPoll,
+	u8			IsBTQosNull)
+{
+	struct tx_desc *ptxdesc;
+
+
+	// Clear all status
+	ptxdesc = (struct tx_desc*)pDesc;
+	_rtw_memset(pDesc, 0, TXDESC_SIZE);
+
+	//offset 0
+	ptxdesc->txdw0 |= cpu_to_le32( OWN | FSG | LSG); //own, bFirstSeg, bLastSeg;
+
+	ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE+OFFSET_SZ)<<OFFSET_SHT)&0x00ff0000); //32 bytes for TX Desc
+
+	ptxdesc->txdw0 |= cpu_to_le32(BufferLen&0x0000ffff); // Buffer size + command header
+
+	//offset 4
+	ptxdesc->txdw1 |= cpu_to_le32((QSLT_MGNT<<QSEL_SHT)&0x00001f00); // Fixed queue of Mgnt queue
+
+	//Set NAVUSEHDR to prevent Ps-poll AId filed to be changed to error vlaue by Hw.
+	if (IsPsPoll)
+	{
+		ptxdesc->txdw1 |= cpu_to_le32(NAVUSEHDR);
+	}
+	else
+	{
+		ptxdesc->txdw4 |= cpu_to_le32(BIT(7)); // Hw set sequence number
+		ptxdesc->txdw3 |= cpu_to_le32((8 <<28)); //set bit3 to 1. Suugested by TimChen. 2009.12.29.
+	}
+
+	if (_TRUE == IsBTQosNull)
+	{
+		ptxdesc->txdw2 |= cpu_to_le32(BIT(23)); // BT NULL
+	}
+
+	//offset 16
+	ptxdesc->txdw4 |= cpu_to_le32(BIT(8));//driver uses rate
+
+#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
+	// USB interface drop packet if the checksum of descriptor isn't correct.
+	// Using this checksum can let hardware recovery from packet bulk out error (e.g. Cancel URC, Bulk out error.).
+	rtl8188eu_cal_txdesc_chksum(ptxdesc);
+#endif
+}
+
+void fill_txdesc_sectype(struct pkt_attrib *pattrib, struct tx_desc *ptxdesc)
+{
+	if ((pattrib->encrypt > 0) && !pattrib->bswenc)
+	{
+		switch (pattrib->encrypt)
+		{	
+			//SEC_TYPE : 0:NO_ENC,1:WEP40/TKIP,2:WAPI,3:AES
+			case _WEP40_:
+			case _WEP104_:
+					ptxdesc->txdw1 |= cpu_to_le32((0x01<<SEC_TYPE_SHT)&0x00c00000);
+					ptxdesc->txdw2 |= cpu_to_le32(0x7 << AMPDU_DENSITY_SHT);
+					break;				
+			case _TKIP_:
+			case _TKIP_WTMIC_:	
+					ptxdesc->txdw1 |= cpu_to_le32((0x01<<SEC_TYPE_SHT)&0x00c00000);
+					ptxdesc->txdw2 |= cpu_to_le32(0x7 << AMPDU_DENSITY_SHT);
+					break;
+#ifdef CONFIG_WAPI_SUPPORT
+			case _SMS4_:
+					ptxdesc->txdw1 |= cpu_to_le32((0x02<<SEC_TYPE_SHT)&0x00c00000);
+					ptxdesc->txdw2 |= cpu_to_le32(0x7 << AMPDU_DENSITY_SHT);
+				break;
+#endif
+			case _AES_:
+					ptxdesc->txdw1 |= cpu_to_le32((0x03<<SEC_TYPE_SHT)&0x00c00000);
+					ptxdesc->txdw2 |= cpu_to_le32(0x7 << AMPDU_DENSITY_SHT);
+					break;
+			case _NO_PRIVACY_:
+			default:
+					break;
+		
+		}
+		
+	}
+
+}
+
+void fill_txdesc_vcs(struct pkt_attrib *pattrib, u32 *pdw)
+{
+	//DBG_8192C("cvs_mode=%d\n", pattrib->vcs_mode);	
+
+	switch(pattrib->vcs_mode)
+	{
+		case RTS_CTS:
+			*pdw |= cpu_to_le32(RTS_EN);
+			break;
+		case CTS_TO_SELF:
+			*pdw |= cpu_to_le32(CTS_2_SELF);
+			break;
+		case NONE_VCS:
+		default:
+			break;		
+	}
+
+	if(pattrib->vcs_mode) {
+		*pdw |= cpu_to_le32(HW_RTS_EN);
+
+		// Set RTS BW
+		if(pattrib->ht_en)
+		{
+			*pdw |= (pattrib->bwmode&HT_CHANNEL_WIDTH_40)?	cpu_to_le32(BIT(27)):0;
+
+			if(pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_LOWER)
+				*pdw |= cpu_to_le32((0x01<<28)&0x30000000);
+			else if(pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_UPPER)
+				*pdw |= cpu_to_le32((0x02<<28)&0x30000000);
+			else if(pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE)
+				*pdw |= 0;
+			else
+				*pdw |= cpu_to_le32((0x03<<28)&0x30000000);
+		}
+	}
+}
+
+void fill_txdesc_phy(struct pkt_attrib *pattrib, u32 *pdw)
+{
+	//DBG_8192C("bwmode=%d, ch_off=%d\n", pattrib->bwmode, pattrib->ch_offset);
+
+	if(pattrib->ht_en)
+	{
+		*pdw |= (pattrib->bwmode&HT_CHANNEL_WIDTH_40)?	cpu_to_le32(BIT(25)):0;
+
+		if(pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_LOWER)
+			*pdw |= cpu_to_le32((0x01<<DATA_SC_SHT)&0x003f0000);		
+		else if(pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_UPPER)
+			*pdw |= cpu_to_le32((0x02<<DATA_SC_SHT)&0x003f0000);
+		else if(pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE)
+			*pdw |= 0;
+		else
+			*pdw |= cpu_to_le32((0x03<<DATA_SC_SHT)&0x003f0000);
+	}
+}
+
+
+static s32 update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, s32 sz ,u8 bagg_pkt)
+{	
+      int	pull=0;
+	uint	qsel;
+	u8 data_rate,pwr_status,offset;
+	_adapter			*padapter = pxmitframe->padapter;
+	struct mlme_priv	*pmlmepriv = &padapter->mlmepriv;		
+	struct pkt_attrib	*pattrib = &pxmitframe->attrib;
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	//struct dm_priv	*pdmpriv = &pHalData->dmpriv;
+	struct tx_desc	*ptxdesc = (struct tx_desc *)pmem;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	sint	bmcst = IS_MCAST(pattrib->ra);
+	
+#ifdef CONFIG_P2P
+	struct wifidirect_info*	pwdinfo = &padapter->wdinfo;
+#endif //CONFIG_P2P
+
+#ifdef CONFIG_CONCURRENT_MODE
+	if(rtw_buddy_adapter_up(padapter) && padapter->adapter_type > PRIMARY_ADAPTER)	
+		pHalData = GET_HAL_DATA(padapter->pbuddy_adapter);				
+#endif //CONFIG_CONCURRENT_MODE
+
+#ifndef CONFIG_USE_USB_BUFFER_ALLOC_TX 
+if (padapter->registrypriv.mp_mode == 0)
+{
+	if((!bagg_pkt) &&(urb_zero_packet_chk(padapter, sz)==0))//(sz %512) != 0
+	//if((!bagg_pkt) &&(rtw_usb_bulk_size_boundary(padapter,TXDESC_SIZE+sz)==_FALSE))	
+	{
+		ptxdesc = (struct tx_desc *)(pmem+PACKET_OFFSET_SZ);
+		//DBG_8192C("==> non-agg-pkt,shift pointer...\n");
+		pull = 1;
+	}
+}
+#endif	// CONFIG_USE_USB_BUFFER_ALLOC_TX
+
+	_rtw_memset(ptxdesc, 0, sizeof(struct tx_desc));
+	
+        //4 offset 0
+	ptxdesc->txdw0 |= cpu_to_le32(OWN | FSG | LSG);
+	//DBG_8192C("%s==> pkt_len=%d,bagg_pkt=%02x\n",__FUNCTION__,sz,bagg_pkt);
+	ptxdesc->txdw0 |= cpu_to_le32(sz & 0x0000ffff);//update TXPKTSIZE
+	
+	offset = TXDESC_SIZE + OFFSET_SZ;		
+
+	#ifdef CONFIG_TX_EARLY_MODE	
+	if(bagg_pkt){		
+		offset += EARLY_MODE_INFO_SIZE ;//0x28			
+	}
+	#endif
+	//DBG_8192C("%s==>offset(0x%02x)  \n",__FUNCTION__,offset);
+	ptxdesc->txdw0 |= cpu_to_le32(((offset) << OFFSET_SHT) & 0x00ff0000);//32 bytes for TX Desc
+
+	if (bmcst) ptxdesc->txdw0 |= cpu_to_le32(BMC);
+
+#ifndef CONFIG_USE_USB_BUFFER_ALLOC_TX
+if (padapter->registrypriv.mp_mode == 0)
+{
+	if(!bagg_pkt){
+		if((pull) && (pxmitframe->pkt_offset>0)) {	
+			pxmitframe->pkt_offset = pxmitframe->pkt_offset -1;		
+		}
+	}
+}	
+#endif
+	//DBG_8192C("%s, pkt_offset=0x%02x\n",__FUNCTION__,pxmitframe->pkt_offset);
+
+	// pkt_offset, unit:8 bytes padding
+	if (pxmitframe->pkt_offset > 0)
+		ptxdesc->txdw1 |= cpu_to_le32((pxmitframe->pkt_offset << 26) & 0x7c000000);
+
+	//driver uses rate
+	ptxdesc->txdw4 |= cpu_to_le32(USERATE);//rate control always by driver
+
+	if((pxmitframe->frame_tag&0x0f) == DATA_FRAMETAG)
+	{
+		//DBG_8192C("pxmitframe->frame_tag == DATA_FRAMETAG\n");		
+
+		//offset 4
+		ptxdesc->txdw1 |= cpu_to_le32(pattrib->mac_id&0x3F);
+
+		qsel = (uint)(pattrib->qsel & 0x0000001f);
+		//DBG_8192C("==> macid(%d) qsel:0x%02x \n",pattrib->mac_id,qsel);
+		ptxdesc->txdw1 |= cpu_to_le32((qsel << QSEL_SHT) & 0x00001f00);
+
+		ptxdesc->txdw1 |= cpu_to_le32((pattrib->raid<< RATE_ID_SHT) & 0x000F0000);
+
+		fill_txdesc_sectype(pattrib, ptxdesc);
+
+		if(pattrib->ampdu_en==_TRUE){
+			ptxdesc->txdw2 |= cpu_to_le32(AGG_EN);//AGG EN
+		
+			//SET_TX_DESC_MAX_AGG_NUM_88E(pDesc, 0x1F);
+			//SET_TX_DESC_MCSG1_MAX_LEN_88E(pDesc, 0x6);
+			//SET_TX_DESC_MCSG2_MAX_LEN_88E(pDesc, 0x6);
+			//SET_TX_DESC_MCSG3_MAX_LEN_88E(pDesc, 0x6);
+			//SET_TX_DESC_MCS7_SGI_MAX_LEN_88E(pDesc, 0x6);
+			ptxdesc->txdw6 = 0x6666f800;		
+		}
+		else{
+			ptxdesc->txdw2 |= cpu_to_le32(AGG_BK);//AGG BK
+		}
+		
+		//offset 8
+		
+
+		//offset 12
+		ptxdesc->txdw3 |= cpu_to_le32((pattrib->seqnum<< SEQ_SHT)&0x0FFF0000);
+
+
+		//offset 16 , offset 20
+		if (pattrib->qos_en)
+			ptxdesc->txdw4 |= cpu_to_le32(QOS);//QoS
+
+		//offset 20
+	#ifdef CONFIG_USB_TX_AGGREGATION
+		if (pxmitframe->agg_num > 1){
+			//DBG_8192C("%s agg_num:%d\n",__FUNCTION__,pxmitframe->agg_num );
+			ptxdesc->txdw5 |= cpu_to_le32((pxmitframe->agg_num << USB_TXAGG_NUM_SHT) & 0xFF000000);
+		}
+	#endif
+
+		if ((pattrib->ether_type != 0x888e) &&
+		    (pattrib->ether_type != 0x0806) &&
+		    (pattrib->ether_type != 0x88b4) &&
+		    (pattrib->dhcp_pkt != 1))
+		{
+			//Non EAP & ARP & DHCP type data packet
+              	
+			fill_txdesc_vcs(pattrib, &ptxdesc->txdw4);
+			fill_txdesc_phy(pattrib, &ptxdesc->txdw4);
+
+			ptxdesc->txdw4 |= cpu_to_le32(0x00000008);//RTS Rate=24M
+			ptxdesc->txdw5 |= cpu_to_le32(0x0001ff00);//DATA/RTS  Rate FB LMT			
+
+	#if (RATE_ADAPTIVE_SUPPORT == 1)		
+			if(pattrib->ht_en){
+				if( ODM_RA_GetShortGI_8188E(&pHalData->odmpriv,pattrib->mac_id))
+					ptxdesc->txdw5 |= cpu_to_le32(SGI);//SGI
+			}
+				
+			data_rate =ODM_RA_GetDecisionRate_8188E(&pHalData->odmpriv,pattrib->mac_id);			
+			ptxdesc->txdw5 |= cpu_to_le32(data_rate & 0x3F);
+
+               	//for debug
+               	#if 0
+			if(padapter->fix_rate!= 0xFF){
+				ptxdesc->datarate = padapter->fix_rate;
+			}
+			#endif
+
+			#if (POWER_TRAINING_ACTIVE==1)
+			pwr_status = ODM_RA_GetHwPwrStatus_8188E(&pHalData->odmpriv,pattrib->mac_id);
+			ptxdesc->txdw4 |=cpu_to_le32( (pwr_status & 0x7)<< PWR_STATUS_SHT);
+			#endif //(POWER_TRAINING_ACTIVE==1)
+	#else//if (RATE_ADAPTIVE_SUPPORT == 1)	
+				
+			if(pattrib->ht_en)
+				ptxdesc->txdw5 |= cpu_to_le32(SGI);//SGI
+
+			data_rate = 0x13; //default rate: MCS7									
+			 if(padapter->fix_rate!= 0xFF){//rate control by iwpriv
+				data_rate = padapter->fix_rate;				
+			}
+			ptxdesc->txdw5 |= cpu_to_le32(data_rate & 0x3F); 
+
+	#endif//if (RATE_ADAPTIVE_SUPPORT == 1)				
+
+		}
+		else
+		{
+			// EAP data packet and ARP packet and DHCP.
+			// Use the 1M data rate to send the EAP/ARP packet.
+			// This will maybe make the handshake smooth.
+
+			ptxdesc->txdw2 |= cpu_to_le32(AGG_BK);//AGG BK		   
+
+			if (pmlmeinfo->preamble_mode == PREAMBLE_SHORT)
+				ptxdesc->txdw4 |= cpu_to_le32(BIT(24));// DATA_SHORT
+
+			ptxdesc->txdw5 |= cpu_to_le32(MRateToHwRate(pmlmeext->tx_rate));
+		}
+
+#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX
+		//offset 24
+		if ( pattrib->hw_tcp_csum == 1 ) {
+			// ptxdesc->txdw6 = 0; // clear TCP_CHECKSUM and IP_CHECKSUM. It's zero already!!
+			u8 ip_hdr_offset = 32 + pattrib->hdrlen + pattrib->iv_len + 8;
+			ptxdesc->txdw7 = (1 << 31) | (ip_hdr_offset << 16);
+			DBG_8192C("ptxdesc->txdw7 = %08x\n", ptxdesc->txdw7);
+		}
+#endif
+	}
+	else if((pxmitframe->frame_tag&0x0f)== MGNT_FRAMETAG)
+	{
+		//DBG_8192C("pxmitframe->frame_tag == MGNT_FRAMETAG\n");	
+		
+		//offset 4		
+		ptxdesc->txdw1 |= cpu_to_le32(pattrib->mac_id&0x3f);
+		
+		qsel = (uint)(pattrib->qsel&0x0000001f);
+		ptxdesc->txdw1 |= cpu_to_le32((qsel<<QSEL_SHT)&0x00001f00);
+
+		ptxdesc->txdw1 |= cpu_to_le32((pattrib->raid<< RATE_ID_SHT) & 0x000f0000);
+		
+		//fill_txdesc_sectype(pattrib, ptxdesc);
+		
+		//offset 8		
+#ifdef CONFIG_XMIT_ACK
+		//CCX-TXRPT ack for xmit mgmt frames.
+		if (pxmitframe->ack_report) {
+			#ifdef DBG_CCX
+			static u16 ccx_sw = 0x123;
+			ptxdesc->txdw7 |= cpu_to_le32(((ccx_sw)<<16)&0x0fff0000);
+			DBG_871X("%s set ccx, sw:0x%03x\n", __func__, ccx_sw);
+			ccx_sw = (ccx_sw+1)%0xfff;
+			#endif
+			ptxdesc->txdw2 |= cpu_to_le32(BIT(19));
+		}
+#endif //CONFIG_XMIT_ACK
+
+		//offset 12
+		ptxdesc->txdw3 |= cpu_to_le32((pattrib->seqnum<<SEQ_SHT)&0x0FFF0000);
+				
+		//offset 20
+		ptxdesc->txdw5 |= cpu_to_le32(RTY_LMT_EN);//retry limit enable
+		if(pattrib->retry_ctrl == _TRUE)
+			ptxdesc->txdw5 |= cpu_to_le32(0x00180000);//retry limit = 6
+		else
+			ptxdesc->txdw5 |= cpu_to_le32(0x00300000);//retry limit = 12
+
+#ifdef CONFIG_INTEL_PROXIM
+		if((padapter->proximity.proxim_on==_TRUE)&&(pattrib->intel_proxim==_TRUE)){
+			DBG_871X("\n %s pattrib->rate=%d\n",__FUNCTION__,pattrib->rate);
+			ptxdesc->txdw5 |= cpu_to_le32( pattrib->rate);
+		}
+		else
+#endif
+		{
+			ptxdesc->txdw5 |= cpu_to_le32(MRateToHwRate(pmlmeext->tx_rate));
+		}
+	}
+	else if((pxmitframe->frame_tag&0x0f) == TXAGG_FRAMETAG)
+	{
+		DBG_8192C("pxmitframe->frame_tag == TXAGG_FRAMETAG\n");
+	}
+#ifdef CONFIG_MP_INCLUDED
+	else if(((pxmitframe->frame_tag&0x0f) == MP_FRAMETAG) &&
+			(padapter->registrypriv.mp_mode == 1))
+	{
+		fill_txdesc_for_mp(padapter, ptxdesc);
+	}
+#endif
+	else
+	{
+		DBG_8192C("pxmitframe->frame_tag = %d\n", pxmitframe->frame_tag);
+
+		//offset 4	
+		ptxdesc->txdw1 |= cpu_to_le32((4)&0x3f);//CAM_ID(MAC_ID)
+
+		ptxdesc->txdw1 |= cpu_to_le32((6<< RATE_ID_SHT) & 0x000f0000);//raid
+
+		//offset 8		
+
+		//offset 12
+		ptxdesc->txdw3 |= cpu_to_le32((pattrib->seqnum<<SEQ_SHT)&0x0fff0000);
+
+		//offset 20
+		ptxdesc->txdw5 |= cpu_to_le32(MRateToHwRate(pmlmeext->tx_rate));
+	}
+
+	// 2009.11.05. tynli_test. Suggested by SD4 Filen for FW LPS.
+	// (1) The sequence number of each non-Qos frame / broadcast / multicast /
+	// mgnt frame should be controled by Hw because Fw will also send null data
+	// which we cannot control when Fw LPS enable.
+	// --> default enable non-Qos data sequense number. 2010.06.23. by tynli.
+	// (2) Enable HW SEQ control for beacon packet, because we use Hw beacon.
+	// (3) Use HW Qos SEQ to control the seq num of Ext port non-Qos packets.
+	// 2010.06.23. Added by tynli.
+	if(!pattrib->qos_en)
+	{		
+		//ptxdesc->txdw4 |= cpu_to_le32(BIT(7)); // Hw set sequence number
+		//ptxdesc->txdw3 |= cpu_to_le32((8 <<28)); //set bit3 to 1. Suugested by TimChen. 2009.12.29.
+
+		ptxdesc->txdw3 |= cpu_to_le32(EN_HWSEQ); // Hw set sequence number
+		ptxdesc->txdw4 |= cpu_to_le32(HW_SSN); 	// Hw set sequence number
+		
+	}
+
+#ifdef CONFIG_HW_ANTENNA_DIVERSITY //CONFIG_ANTENNA_DIVERSITY 
+	ODM_SetTxAntByTxInfo_88E(&pHalData->odmpriv, pmem, pattrib->mac_id);
+#endif
+
+	rtl8188eu_cal_txdesc_chksum(ptxdesc);
+	_dbg_dump_tx_info(padapter,pxmitframe->frame_tag,ptxdesc);	
+	return pull;
+		
+}
+
+
+#ifdef CONFIG_XMIT_THREAD_MODE
+/*
+ * Description
+ *	Transmit xmitbuf to hardware tx fifo
+ *
+ * Return
+ *	_SUCCESS	ok
+ *	_FAIL		something error
+ */
+s32 rtl8188eu_xmit_buf_handler(PADAPTER padapter)
+{
+	//PHAL_DATA_TYPE phal;
+	struct xmit_priv *pxmitpriv;
+	struct xmit_buf *pxmitbuf;
+	s32 ret;
+
+
+	//phal = GET_HAL_DATA(padapter);
+	pxmitpriv = &padapter->xmitpriv;
+
+	ret = _rtw_down_sema(&pxmitpriv->xmit_sema);
+	if (_FAIL == ret) {
+		RT_TRACE(_module_hal_xmit_c_, _drv_emerg_,
+				 ("%s: down SdioXmitBufSema fail!\n", __FUNCTION__));
+		return _FAIL;
+	}
+
+	ret = (padapter->bDriverStopped == _TRUE) || (padapter->bSurpriseRemoved == _TRUE);
+	if (ret) {
+		RT_TRACE(_module_hal_xmit_c_, _drv_notice_,
+				 ("%s: bDriverStopped(%d) bSurpriseRemoved(%d)!\n",
+				  __FUNCTION__, padapter->bDriverStopped, padapter->bSurpriseRemoved));
+		return _FAIL;
+	}
+
+	if(check_pending_xmitbuf(pxmitpriv) == _FALSE)
+		return _SUCCESS;
+
+#ifdef CONFIG_LPS_LCLK
+	ret = rtw_register_tx_alive(padapter);
+	if (ret != _SUCCESS) {
+		RT_TRACE(_module_hal_xmit_c_, _drv_notice_,
+				 ("%s: wait to leave LPS_LCLK\n", __FUNCTION__));
+		return _SUCCESS;
+	}
+#endif
+
+	do {
+		pxmitbuf = dequeue_pending_xmitbuf(pxmitpriv);
+		if (pxmitbuf == NULL) break;
+
+		rtw_write_port(padapter, pxmitbuf->ff_hwaddr, pxmitbuf->len, (unsigned char*)pxmitbuf);
+
+	} while (1);
+
+#ifdef CONFIG_LPS_LCLK
+	rtw_unregister_tx_alive(padapter);
+#endif
+
+	return _SUCCESS;
+}
+#endif
+
+#ifdef CONFIG_IOL_IOREG_CFG_DBG
+#include <rtw_iol.h>
+#endif
+//for non-agg data frame or  management frame
+static s32 rtw_dump_xframe(_adapter *padapter, struct xmit_frame *pxmitframe)
+{
+	s32 ret = _SUCCESS;
+	s32 inner_ret = _SUCCESS;
+	int t, sz, w_sz, pull=0;
+	u8 *mem_addr;
+	u32 ff_hwaddr;
+	struct xmit_buf *pxmitbuf = pxmitframe->pxmitbuf;
+	struct pkt_attrib *pattrib = &pxmitframe->attrib;
+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+	struct security_priv *psecuritypriv = &padapter->securitypriv;
+#ifdef CONFIG_80211N_HT
+	if ((pxmitframe->frame_tag == DATA_FRAMETAG) &&
+	    (pxmitframe->attrib.ether_type != 0x0806) &&
+	    (pxmitframe->attrib.ether_type != 0x888e) &&
+	    (pxmitframe->attrib.ether_type != 0x88b4) &&
+	    (pxmitframe->attrib.dhcp_pkt != 1))
+	{
+		rtw_issue_addbareq_cmd(padapter, pxmitframe);
+	}
+#endif //CONFIG_80211N_HT
+	mem_addr = pxmitframe->buf_addr;
+
+       RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_dump_xframe()\n"));
+	
+	for (t = 0; t < pattrib->nr_frags; t++)
+	{
+		if (inner_ret != _SUCCESS && ret == _SUCCESS)
+			ret = _FAIL;
+			
+		if (t != (pattrib->nr_frags - 1))
+		{
+			RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("pattrib->nr_frags=%d\n", pattrib->nr_frags));
+
+			sz = pxmitpriv->frag_len;
+			sz = sz - 4 - (psecuritypriv->sw_encrypt ? 0 : pattrib->icv_len);					
+		}
+		else //no frag
+		{
+			sz = pattrib->last_txcmdsz;
+		}
+
+		pull = update_txdesc(pxmitframe, mem_addr, sz, _FALSE);
+             
+		if(pull)
+		{
+			mem_addr += PACKET_OFFSET_SZ; //pull txdesc head
+			
+			//pxmitbuf ->pbuf = mem_addr;			
+			pxmitframe->buf_addr = mem_addr;
+
+			w_sz = sz + TXDESC_SIZE;
+		}
+		else
+		{
+			w_sz = sz + TXDESC_SIZE + PACKET_OFFSET_SZ;
+		}	
+#ifdef CONFIG_IOL_IOREG_CFG_DBG		
+		rtw_IOL_cmd_buf_dump(padapter,w_sz,pxmitframe->buf_addr);
+#endif		
+		ff_hwaddr = rtw_get_ff_hwaddr(pxmitframe);
+
+#ifdef CONFIG_XMIT_THREAD_MODE
+		pxmitbuf->len = w_sz;
+		pxmitbuf->ff_hwaddr = ff_hwaddr;
+		enqueue_pending_xmitbuf(pxmitpriv, pxmitbuf);
+#else
+		inner_ret = rtw_write_port(padapter, ff_hwaddr, w_sz, (unsigned char*)pxmitbuf);
+#endif
+
+		rtw_count_tx_stats(padapter, pxmitframe, sz);
+
+		RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_write_port, w_sz=%d\n", w_sz));
+		//DBG_8192C("rtw_write_port, w_sz=%d, sz=%d, txdesc_sz=%d, tid=%d\n", w_sz, sz, w_sz-sz, pattrib->priority);      
+
+		mem_addr += w_sz;
+
+		mem_addr = (u8 *)RND4(((SIZE_PTR)(mem_addr)));
+
+	}
+	
+	rtw_free_xmitframe(pxmitpriv, pxmitframe);
+	
+	if  (ret != _SUCCESS)
+		rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_UNKNOWN);
+	
+	return ret;
+}
+
+#ifdef CONFIG_USB_TX_AGGREGATION
+static u32 xmitframe_need_length(struct xmit_frame *pxmitframe)
+{
+	struct pkt_attrib *pattrib = &pxmitframe->attrib;
+
+	u32	len = 0;
+
+	// no consider fragement
+	len = pattrib->hdrlen + pattrib->iv_len +
+		SNAP_SIZE + sizeof(u16) +
+		pattrib->pktlen +
+		((pattrib->bswenc) ? pattrib->icv_len : 0);
+
+	if(pattrib->encrypt ==_TKIP_)
+		len += 8;
+
+	return len;
+}
+
+#define IDEA_CONDITION 1	// check all packets before enqueue
+s32 rtl8188eu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	struct xmit_frame *pxmitframe = NULL;
+	struct xmit_frame *pfirstframe = NULL;
+
+	// aggregate variable
+	struct hw_xmit *phwxmit;
+	struct sta_info *psta = NULL;
+	struct tx_servq *ptxservq = NULL;
+
+	_irqL irqL;
+	_list *xmitframe_plist = NULL, *xmitframe_phead = NULL;
+
+	u32	pbuf;	// next pkt address
+	u32	pbuf_tail;	// last pkt tail
+	u32	len;	// packet length, except TXDESC_SIZE and PKT_OFFSET
+
+	u32	bulkSize = pHalData->UsbBulkOutSize;
+	u8	descCount;
+	u32	bulkPtr;
+
+	// dump frame variable
+	u32 ff_hwaddr;
+
+#ifndef IDEA_CONDITION
+	int res = _SUCCESS;
+#endif
+
+	RT_TRACE(_module_rtl8192c_xmit_c_, _drv_info_, ("+xmitframe_complete\n"));
+
+
+	// check xmitbuffer is ok
+	if (pxmitbuf == NULL) {
+		pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv);
+		if (pxmitbuf == NULL){
+			//DBG_871X("%s #1, connot alloc xmitbuf!!!! \n",__FUNCTION__);
+			return _FALSE;
+		}
+	}
+
+//DBG_8192C("%s ===================================== \n",__FUNCTION__);
+	//3 1. pick up first frame
+	do {
+		rtw_free_xmitframe(pxmitpriv, pxmitframe);
+			
+		pxmitframe = rtw_dequeue_xframe(pxmitpriv, pxmitpriv->hwxmits, pxmitpriv->hwxmit_entry);
+		if (pxmitframe == NULL) {
+			// no more xmit frame, release xmit buffer
+			//DBG_8192C("no more xmit frame ,return\n");
+			rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
+			return _FALSE;
+		}
+
+#ifndef IDEA_CONDITION
+		if (pxmitframe->frame_tag != DATA_FRAMETAG) {
+			RT_TRACE(_module_rtl8192c_xmit_c_, _drv_err_,
+				 ("xmitframe_complete: frame tag(%d) is not DATA_FRAMETAG(%d)!\n",
+				  pxmitframe->frame_tag, DATA_FRAMETAG));
+//			rtw_free_xmitframe(pxmitpriv, pxmitframe);
+			continue;
+		}
+
+		// TID 0~15
+		if ((pxmitframe->attrib.priority < 0) ||
+		    (pxmitframe->attrib.priority > 15)) {
+			RT_TRACE(_module_rtl8192c_xmit_c_, _drv_err_,
+				 ("xmitframe_complete: TID(%d) should be 0~15!\n",
+				  pxmitframe->attrib.priority));
+//			rtw_free_xmitframe(pxmitpriv, pxmitframe);
+			continue;
+		}
+#endif
+		//DBG_8192C("==> pxmitframe->attrib.priority:%d\n",pxmitframe->attrib.priority);
+		pxmitframe->pxmitbuf = pxmitbuf;
+		pxmitframe->buf_addr = pxmitbuf->pbuf;
+		pxmitbuf->priv_data = pxmitframe;
+
+		pxmitframe->agg_num = 1; // alloc xmitframe should assign to 1.
+		#ifdef CONFIG_TX_EARLY_MODE
+		pxmitframe->pkt_offset = 2; // first frame of aggregation, reserve one offset for EM info ,another for usb bulk-out block check
+		#else
+		pxmitframe->pkt_offset = 1; // first frame of aggregation, reserve offset
+		#endif
+
+#ifdef IDEA_CONDITION
+		rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe);
+#else
+		res = rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe);
+		if (res == _FALSE) {
+//			rtw_free_xmitframe(pxmitpriv, pxmitframe);
+			continue;
+		}
+#endif
+
+		// always return ndis_packet after rtw_xmitframe_coalesce
+		rtw_os_xmit_complete(padapter, pxmitframe);
+
+		break;
+	} while (1);
+
+	//3 2. aggregate same priority and same DA(AP or STA) frames
+	pfirstframe = pxmitframe;
+	len = xmitframe_need_length(pfirstframe) + TXDESC_SIZE+(pfirstframe->pkt_offset*PACKET_OFFSET_SZ);
+	pbuf_tail = len;
+	pbuf = _RND8(pbuf_tail);
+
+	// check pkt amount in one bulk
+	descCount = 0;
+	bulkPtr = bulkSize;
+	if (pbuf < bulkPtr)
+		descCount++;
+	else {
+		descCount = 0;
+		bulkPtr = ((pbuf / bulkSize) + 1) * bulkSize; // round to next bulkSize
+	}
+
+	// dequeue same priority packet from station tx queue
+	psta = pfirstframe->attrib.psta;
+	switch (pfirstframe->attrib.priority) {
+		case 1:
+		case 2:
+			ptxservq = &(psta->sta_xmitpriv.bk_q);
+			phwxmit = pxmitpriv->hwxmits + 3;
+			break;
+
+		case 4:
+		case 5:
+			ptxservq = &(psta->sta_xmitpriv.vi_q);
+			phwxmit = pxmitpriv->hwxmits + 1;
+			break;
+
+		case 6:
+		case 7:
+			ptxservq = &(psta->sta_xmitpriv.vo_q);
+			phwxmit = pxmitpriv->hwxmits;
+			break;
+
+		case 0:
+		case 3:
+		default:
+			ptxservq = &(psta->sta_xmitpriv.be_q);
+			phwxmit = pxmitpriv->hwxmits + 2;
+			break;
+	}
+//DBG_8192C("==> pkt_no=%d,pkt_len=%d,len=%d,RND8_LEN=%d,pkt_offset=0x%02x\n",
+	//pxmitframe->agg_num,pxmitframe->attrib.last_txcmdsz,len,pbuf,pxmitframe->pkt_offset );
+
+
+	_enter_critical_bh(&pxmitpriv->lock, &irqL);
+
+	xmitframe_phead = get_list_head(&ptxservq->sta_pending);
+	xmitframe_plist = get_next(xmitframe_phead);
+	
+	while (rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist) == _FALSE)
+	{
+		pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list);
+		xmitframe_plist = get_next(xmitframe_plist);
+
+             pxmitframe->agg_num = 0; // not first frame of aggregation
+		#ifdef CONFIG_TX_EARLY_MODE
+		pxmitframe->pkt_offset = 1;// not first frame of aggregation,reserve offset for EM Info
+		#else
+		pxmitframe->pkt_offset = 0; // not first frame of aggregation, no need to reserve offset
+		#endif	
+
+		len = xmitframe_need_length(pxmitframe) + TXDESC_SIZE +(pxmitframe->pkt_offset*PACKET_OFFSET_SZ);
+		
+		if (_RND8(pbuf + len) > MAX_XMITBUF_SZ)
+		//if (_RND8(pbuf + len) > (MAX_XMITBUF_SZ/2))//to do : for TX TP finial tune , Georgia 2012-0323
+		{
+			//DBG_8192C("%s....len> MAX_XMITBUF_SZ\n",__FUNCTION__);
+			pxmitframe->agg_num = 1;
+			pxmitframe->pkt_offset = 1;			
+			break;		
+		}
+		rtw_list_delete(&pxmitframe->list);
+		ptxservq->qcnt--;
+		phwxmit->accnt--;
+
+#ifndef IDEA_CONDITION
+		// suppose only data frames would be in queue
+		if (pxmitframe->frame_tag != DATA_FRAMETAG) {
+			RT_TRACE(_module_rtl8192c_xmit_c_, _drv_err_,
+				 ("xmitframe_complete: frame tag(%d) is not DATA_FRAMETAG(%d)!\n",
+				  pxmitframe->frame_tag, DATA_FRAMETAG));
+			rtw_free_xmitframe(pxmitpriv, pxmitframe);
+			continue;
+		}
+
+		// TID 0~15
+		if ((pxmitframe->attrib.priority < 0) ||
+		    (pxmitframe->attrib.priority > 15)) {
+			RT_TRACE(_module_rtl8192c_xmit_c_, _drv_err_,
+				 ("xmitframe_complete: TID(%d) should be 0~15!\n",
+				  pxmitframe->attrib.priority));
+			rtw_free_xmitframe(pxmitpriv, pxmitframe);
+			continue;
+		}
+#endif
+
+//		pxmitframe->pxmitbuf = pxmitbuf;
+		pxmitframe->buf_addr = pxmitbuf->pbuf + pbuf;
+	
+#ifdef IDEA_CONDITION
+		rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe);
+#else
+		res = rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe);
+		if (res == _FALSE) {
+			DBG_871X("%s coalesce failed \n",__FUNCTION__);
+			rtw_free_xmitframe(pxmitpriv, pxmitframe);
+			continue;
+		}
+#endif
+		//DBG_8192C("==> pxmitframe->attrib.priority:%d\n",pxmitframe->attrib.priority);
+		// always return ndis_packet after rtw_xmitframe_coalesce
+		rtw_os_xmit_complete(padapter, pxmitframe);
+
+		// (len - TXDESC_SIZE) == pxmitframe->attrib.last_txcmdsz
+		update_txdesc(pxmitframe, pxmitframe->buf_addr, pxmitframe->attrib.last_txcmdsz,_TRUE);
+				
+		// don't need xmitframe any more
+		rtw_free_xmitframe(pxmitpriv, pxmitframe);
+
+		// handle pointer and stop condition
+		pbuf_tail = pbuf + len;
+		pbuf = _RND8(pbuf_tail);
+
+
+		pfirstframe->agg_num++;
+#ifdef CONFIG_TX_EARLY_MODE	
+		pxmitpriv->agg_pkt[pfirstframe->agg_num-1].offset = _RND8(len); 			
+		pxmitpriv->agg_pkt[pfirstframe->agg_num-1].pkt_len = pxmitframe->attrib.last_txcmdsz;						
+#endif
+		if (MAX_TX_AGG_PACKET_NUMBER == pfirstframe->agg_num)
+			break;
+
+		if (pbuf < bulkPtr) {
+			descCount++;
+			if (descCount == pHalData->UsbTxAggDescNum)
+				break;
+		} else {
+			descCount = 0;
+			bulkPtr = ((pbuf / bulkSize) + 1) * bulkSize;
+		}
+	}//end while( aggregate same priority and same DA(AP or STA) frames)
+
+
+	if (_rtw_queue_empty(&ptxservq->sta_pending) == _TRUE)
+		rtw_list_delete(&ptxservq->tx_pending);
+
+	_exit_critical_bh(&pxmitpriv->lock, &irqL);
+#ifdef CONFIG_80211N_HT
+	if ((pfirstframe->attrib.ether_type != 0x0806) &&
+	    (pfirstframe->attrib.ether_type != 0x888e) &&
+	    (pfirstframe->attrib.ether_type != 0x88b4) &&
+	    (pfirstframe->attrib.dhcp_pkt != 1))
+	{
+		rtw_issue_addbareq_cmd(padapter, pfirstframe);
+	}
+#endif //CONFIG_80211N_HT
+#ifndef CONFIG_USE_USB_BUFFER_ALLOC_TX
+	//3 3. update first frame txdesc
+	if ((pbuf_tail % bulkSize) == 0) {
+		// remove pkt_offset
+		pbuf_tail -= PACKET_OFFSET_SZ;
+		pfirstframe->buf_addr += PACKET_OFFSET_SZ;
+		pfirstframe->pkt_offset--;
+		//DBG_8192C("$$$$$ buf size equal to USB block size $$$$$$\n");
+	}
+#endif	// CONFIG_USE_USB_BUFFER_ALLOC_TX
+
+	update_txdesc(pfirstframe, pfirstframe->buf_addr, pfirstframe->attrib.last_txcmdsz,_TRUE);
+		
+        #ifdef CONFIG_TX_EARLY_MODE
+	//prepare EM info for first frame, agg_num value start from 1
+	pxmitpriv->agg_pkt[0].offset = _RND8(pfirstframe->attrib.last_txcmdsz +TXDESC_SIZE +(pfirstframe->pkt_offset*PACKET_OFFSET_SZ));
+	pxmitpriv->agg_pkt[0].pkt_len = pfirstframe->attrib.last_txcmdsz;//get from rtw_xmitframe_coalesce 			
+
+	UpdateEarlyModeInfo8188E(pxmitpriv,pxmitbuf );
+	#endif
+	
+	//3 4. write xmit buffer to USB FIFO
+	ff_hwaddr = rtw_get_ff_hwaddr(pfirstframe);
+//DBG_8192C("%s ===================================== write port,buf_size(%d) \n",__FUNCTION__,pbuf_tail);
+	// xmit address == ((xmit_frame*)pxmitbuf->priv_data)->buf_addr
+	rtw_write_port(padapter, ff_hwaddr, pbuf_tail, (u8*)pxmitbuf);
+
+
+	//3 5. update statisitc
+	pbuf_tail -= (pfirstframe->agg_num * TXDESC_SIZE);
+	pbuf_tail -= (pfirstframe->pkt_offset * PACKET_OFFSET_SZ);
+	
+	
+	rtw_count_tx_stats(padapter, pfirstframe, pbuf_tail);
+
+	rtw_free_xmitframe(pxmitpriv, pfirstframe);
+
+	return _TRUE;
+}
+
+#else
+
+s32 rtl8188eu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf)
+{		
+
+	struct hw_xmit *phwxmits;
+	sint hwentry;
+	struct xmit_frame *pxmitframe=NULL;	
+	int res=_SUCCESS, xcnt = 0;
+
+	phwxmits = pxmitpriv->hwxmits;
+	hwentry = pxmitpriv->hwxmit_entry;
+
+	RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("xmitframe_complete()\n"));
+
+	if(pxmitbuf==NULL)
+	{
+		pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv);		
+		if(!pxmitbuf)
+		{
+			return _FALSE;
+		}			
+	}	
+
+
+	do
+	{		
+		pxmitframe =  rtw_dequeue_xframe(pxmitpriv, phwxmits, hwentry);
+		
+		if(pxmitframe)
+		{
+			pxmitframe->pxmitbuf = pxmitbuf;				
+
+			pxmitframe->buf_addr = pxmitbuf->pbuf;
+
+			pxmitbuf->priv_data = pxmitframe;	
+
+			if((pxmitframe->frame_tag&0x0f) == DATA_FRAMETAG)
+			{	
+				if(pxmitframe->attrib.priority<=15)//TID0~15
+				{
+					res = rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe);
+				}	
+				//DBG_8192C("==> pxmitframe->attrib.priority:%d\n",pxmitframe->attrib.priority);
+				rtw_os_xmit_complete(padapter, pxmitframe);//always return ndis_packet after rtw_xmitframe_coalesce 			
+			}
+
+				
+			RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("xmitframe_complete(): rtw_dump_xframe\n"));
+
+			
+			if(res == _SUCCESS)
+			{
+				rtw_dump_xframe(padapter, pxmitframe);		 
+			}
+			else
+			{
+				rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
+				rtw_free_xmitframe(pxmitpriv, pxmitframe);	
+			}
+	 			 		
+			xcnt++;
+			
+		}
+		else
+		{			
+			rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
+			return _FALSE;
+		}
+
+		break;
+		
+	}while(0/*xcnt < (NR_XMITFRAME >> 3)*/);
+
+	return _TRUE;
+	
+}
+#endif
+
+
+
+static s32 xmitframe_direct(_adapter *padapter, struct xmit_frame *pxmitframe)
+{
+	s32 res = _SUCCESS;
+//DBG_8192C("==> %s \n",__FUNCTION__);
+
+	res = rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe);
+	if (res == _SUCCESS) {
+		rtw_dump_xframe(padapter, pxmitframe);
+	}
+	else{
+		DBG_8192C("==> %s xmitframe_coalsece failed\n",__FUNCTION__);
+	}
+
+	return res;
+}
+
+/*
+ * Return
+ *	_TRUE	dump packet directly
+ *	_FALSE	enqueue packet
+ */
+static s32 pre_xmitframe(_adapter *padapter, struct xmit_frame *pxmitframe)
+{
+        _irqL irqL;
+	s32 res;
+	struct xmit_buf *pxmitbuf = NULL;
+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+	struct pkt_attrib *pattrib = &pxmitframe->attrib;
+	struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+#ifdef CONFIG_CONCURRENT_MODE	
+	PADAPTER pbuddy_adapter = padapter->pbuddy_adapter;
+	struct mlme_priv *pbuddy_mlmepriv = &(pbuddy_adapter->mlmepriv);	
+#endif
+	
+	_enter_critical_bh(&pxmitpriv->lock, &irqL);
+
+//DBG_8192C("==> %s \n",__FUNCTION__);
+
+	if (rtw_txframes_sta_ac_pending(padapter, pattrib) > 0)
+	{
+		//DBG_8192C("enqueue AC(%d)\n",pattrib->priority);
+		goto enqueue;
+	}
+
+
+	if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY|_FW_UNDER_LINKING) == _TRUE)
+		goto enqueue;
+
+#ifdef CONFIG_CONCURRENT_MODE	
+	if (check_fwstate(pbuddy_mlmepriv, _FW_UNDER_SURVEY|_FW_UNDER_LINKING) == _TRUE)
+		goto enqueue;
+#endif
+
+	pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv);
+	if (pxmitbuf == NULL)
+		goto enqueue;
+
+	_exit_critical_bh(&pxmitpriv->lock, &irqL);
+
+	pxmitframe->pxmitbuf = pxmitbuf;
+	pxmitframe->buf_addr = pxmitbuf->pbuf;
+	pxmitbuf->priv_data = pxmitframe;
+
+	if (xmitframe_direct(padapter, pxmitframe) != _SUCCESS) {
+		rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
+		rtw_free_xmitframe(pxmitpriv, pxmitframe);
+	}
+
+	return _TRUE;
+
+enqueue:
+	res = rtw_xmitframe_enqueue(padapter, pxmitframe);
+	_exit_critical_bh(&pxmitpriv->lock, &irqL);
+
+	if (res != _SUCCESS) {
+		RT_TRACE(_module_xmit_osdep_c_, _drv_err_, ("pre_xmitframe: enqueue xmitframe fail\n"));
+		rtw_free_xmitframe(pxmitpriv, pxmitframe);
+
+		// Trick, make the statistics correct
+		pxmitpriv->tx_pkts--;
+		pxmitpriv->tx_drop++;
+		return _TRUE;
+	}
+
+	return _FALSE;
+}
+
+s32 rtl8188eu_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe)
+{
+	return rtw_dump_xframe(padapter, pmgntframe);
+}
+
+/*
+ * Return
+ *	_TRUE	dump packet directly ok
+ *	_FALSE	temporary can't transmit packets to hardware
+ */
+s32 rtl8188eu_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe)
+{
+	return pre_xmitframe(padapter, pxmitframe);
+}
+
+s32	rtl8188eu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe)
+{
+	struct xmit_priv 	*pxmitpriv = &padapter->xmitpriv;
+	s32 err;
+	
+	if ((err=rtw_xmitframe_enqueue(padapter, pxmitframe)) != _SUCCESS) 
+	{
+		rtw_free_xmitframe(pxmitpriv, pxmitframe);
+
+		// Trick, make the statistics correct
+		pxmitpriv->tx_pkts--;
+		pxmitpriv->tx_drop++;					
+	}
+	else
+	{
+#ifdef PLATFORM_LINUX
+		tasklet_hi_schedule(&pxmitpriv->xmit_tasklet);
+#endif
+	}
+	
+	return err;
+	
+}
+
+
+#ifdef  CONFIG_HOSTAPD_MLME
+
+static void rtl8188eu_hostap_mgnt_xmit_cb(struct urb *urb)
+{	
+#ifdef PLATFORM_LINUX
+	struct sk_buff *skb = (struct sk_buff *)urb->context;
+
+	//DBG_8192C("%s\n", __FUNCTION__);
+
+	dev_kfree_skb_any(skb);
+#endif	
+}
+
+s32 rtl8188eu_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt)
+{
+#ifdef PLATFORM_LINUX
+	u16 fc;
+	int rc, len, pipe;	
+	unsigned int bmcst, tid, qsel;
+	struct sk_buff *skb, *pxmit_skb;
+	struct urb *urb;
+	unsigned char *pxmitbuf;
+	struct tx_desc *ptxdesc;
+	struct rtw_ieee80211_hdr *tx_hdr;
+	struct hostapd_priv *phostapdpriv = padapter->phostapdpriv;	
+	struct net_device *pnetdev = padapter->pnetdev;
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+	struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);	
+
+	
+	//DBG_8192C("%s\n", __FUNCTION__);
+
+	skb = pkt;
+	
+	len = skb->len;
+	tx_hdr = (struct rtw_ieee80211_hdr *)(skb->data);
+	fc = le16_to_cpu(tx_hdr->frame_ctl);
+	bmcst = IS_MCAST(tx_hdr->addr1);
+
+	if ((fc & RTW_IEEE80211_FCTL_FTYPE) != RTW_IEEE80211_FTYPE_MGMT)
+		goto _exit;
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) // http://www.mail-archive.com/netdev@vger.kernel.org/msg17214.html
+	pxmit_skb = dev_alloc_skb(len + TXDESC_SIZE);			
+#else			
+	pxmit_skb = netdev_alloc_skb(pnetdev, len + TXDESC_SIZE);
+#endif		
+
+	if(!pxmit_skb)
+		goto _exit;
+
+	pxmitbuf = pxmit_skb->data;
+
+	urb = usb_alloc_urb(0, GFP_ATOMIC);
+	if (!urb) {
+		goto _exit;
+	}
+
+	// ----- fill tx desc -----	
+	ptxdesc = (struct tx_desc *)pxmitbuf;	
+	_rtw_memset(ptxdesc, 0, sizeof(*ptxdesc));
+		
+	//offset 0	
+	ptxdesc->txdw0 |= cpu_to_le32(len&0x0000ffff); 
+	ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE+OFFSET_SZ)<<OFFSET_SHT)&0x00ff0000);//default = 32 bytes for TX Desc
+	ptxdesc->txdw0 |= cpu_to_le32(OWN | FSG | LSG);
+
+	if(bmcst)	
+	{
+		ptxdesc->txdw0 |= cpu_to_le32(BIT(24));
+	}	
+
+	//offset 4	
+	ptxdesc->txdw1 |= cpu_to_le32(0x00);//MAC_ID
+
+	ptxdesc->txdw1 |= cpu_to_le32((0x12<<QSEL_SHT)&0x00001f00);
+
+	ptxdesc->txdw1 |= cpu_to_le32((0x06<< 16) & 0x000f0000);//b mode
+
+	//offset 8			
+
+	//offset 12		
+	ptxdesc->txdw3 |= cpu_to_le32((le16_to_cpu(tx_hdr->seq_ctl)<<16)&0xffff0000);
+
+	//offset 16		
+	ptxdesc->txdw4 |= cpu_to_le32(BIT(8));//driver uses rate
+		
+	//offset 20
+
+
+	//HW append seq
+	ptxdesc->txdw4 |= cpu_to_le32(BIT(7)); // Hw set sequence number
+	ptxdesc->txdw3 |= cpu_to_le32((8 <<28)); //set bit3 to 1. Suugested by TimChen. 2009.12.29.
+	
+
+	rtl8188eu_cal_txdesc_chksum(ptxdesc);
+	// ----- end of fill tx desc -----
+
+	//
+	skb_put(pxmit_skb, len + TXDESC_SIZE);
+	pxmitbuf = pxmitbuf + TXDESC_SIZE;
+	_rtw_memcpy(pxmitbuf, skb->data, len);
+
+	//DBG_8192C("mgnt_xmit, len=%x\n", pxmit_skb->len);
+
+
+	// ----- prepare urb for submit -----
+	
+	//translate DMA FIFO addr to pipehandle
+	//pipe = ffaddr2pipehdl(pdvobj, MGT_QUEUE_INX);
+	pipe = usb_sndbulkpipe(pdvobj->pusbdev, pHalData->Queue2EPNum[(u8)MGT_QUEUE_INX]&0x0f);
+	
+	usb_fill_bulk_urb(urb, pdvobj->pusbdev, pipe,
+			  pxmit_skb->data, pxmit_skb->len, rtl8192cu_hostap_mgnt_xmit_cb, pxmit_skb);
+	
+	urb->transfer_flags |= URB_ZERO_PACKET;
+	usb_anchor_urb(urb, &phostapdpriv->anchored);
+	rc = usb_submit_urb(urb, GFP_ATOMIC);
+	if (rc < 0) {
+		usb_unanchor_urb(urb);
+		kfree_skb(skb);
+	}
+	usb_free_urb(urb);
+
+	
+_exit:	
+	
+	dev_kfree_skb_any(skb);
+
+#endif
+
+	return 0;
+
+}
+#endif
+
diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/usb/usb_halinit.c b/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/usb/usb_halinit.c
new file mode 100755
index 00000000..4d9700b9
--- /dev/null
+++ b/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/usb/usb_halinit.c
@@ -0,0 +1,5330 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#define _HCI_HAL_INIT_C_
+
+#include <drv_conf.h>
+#include <osdep_service.h>
+#include <drv_types.h>
+#include <rtw_efuse.h>
+
+#include <rtl8188e_hal.h>
+#include <rtl8188e_led.h>
+
+#ifdef CONFIG_IOL
+#include <rtw_iol.h>
+#endif
+
+#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS)
+
+#error "Shall be Linux or Windows, but not both!\n"
+
+#endif
+
+#ifndef CONFIG_USB_HCI
+
+#error "CONFIG_USB_HCI shall be on!\n"
+
+#endif
+
+#include <usb_ops.h>
+#include <usb_hal.h>
+#include <usb_osintf.h>
+
+#ifdef CONFIG_EFUSE_CONFIG_FILE
+#include <linux/fs.h>
+#include <asm/uaccess.h>
+#endif //CONFIG_EFUSE_CONFIG_FILE
+
+#if DISABLE_BB_RF
+	#define		HAL_MAC_ENABLE	0
+	#define		HAL_BB_ENABLE		0
+	#define		HAL_RF_ENABLE		0
+#else
+	#define		HAL_MAC_ENABLE	1
+	#define		HAL_BB_ENABLE		1
+	#define		HAL_RF_ENABLE		1
+#endif
+
+
+static VOID
+_ConfigNormalChipOutEP_8188E(
+	IN	PADAPTER	pAdapter,
+	IN	u8		NumOutPipe
+	)
+{	
+	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(pAdapter);
+
+	switch(NumOutPipe){
+		case 	3:
+				pHalData->OutEpQueueSel=TX_SELE_HQ| TX_SELE_LQ|TX_SELE_NQ;
+				pHalData->OutEpNumber=3;
+				break;
+		case 	2:
+				pHalData->OutEpQueueSel=TX_SELE_HQ| TX_SELE_NQ;
+				pHalData->OutEpNumber=2;
+				break;
+		case 	1:
+				pHalData->OutEpQueueSel=TX_SELE_HQ;
+				pHalData->OutEpNumber=1;
+				break;
+		default:				
+				break;
+			
+	}
+	DBG_871X("%s OutEpQueueSel(0x%02x), OutEpNumber(%d) \n",__FUNCTION__,pHalData->OutEpQueueSel,pHalData->OutEpNumber );
+
+}
+
+static BOOLEAN HalUsbSetQueuePipeMapping8188EUsb(
+	IN	PADAPTER	pAdapter,
+	IN	u8		NumInPipe,
+	IN	u8		NumOutPipe
+	)
+{
+	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(pAdapter);
+	BOOLEAN			result		= _FALSE;
+
+	_ConfigNormalChipOutEP_8188E(pAdapter, NumOutPipe);
+	
+	// Normal chip with one IN and one OUT doesn't have interrupt IN EP.
+	if(1 == pHalData->OutEpNumber){
+		if(1 != NumInPipe){
+			return result;
+		}
+	}
+
+	// All config other than above support one Bulk IN and one Interrupt IN.
+	//if(2 != NumInPipe){
+	//	return result;
+	//}
+
+	result = Hal_MappingOutPipe(pAdapter, NumOutPipe);
+	
+	return result;
+
+}
+
+void rtl8188eu_interface_configure(_adapter *padapter)
+{
+	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(padapter);
+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(padapter);
+
+	if (pdvobjpriv->ishighspeed == _TRUE)
+	{
+		pHalData->UsbBulkOutSize = USB_HIGH_SPEED_BULK_SIZE;//512 bytes
+	}
+	else
+	{
+		pHalData->UsbBulkOutSize = USB_FULL_SPEED_BULK_SIZE;//64 bytes
+	}
+
+	pHalData->interfaceIndex = pdvobjpriv->InterfaceNumber;
+
+#ifdef CONFIG_USB_TX_AGGREGATION
+	pHalData->UsbTxAggMode		= 1;
+	pHalData->UsbTxAggDescNum	= 0x6;	// only 4 bits
+#endif
+
+#ifdef CONFIG_USB_RX_AGGREGATION
+	pHalData->UsbRxAggMode		= USB_RX_AGG_DMA;// USB_RX_AGG_DMA;
+	pHalData->UsbRxAggBlockCount	= 8; //unit : 512b
+	pHalData->UsbRxAggBlockTimeout	= 0x6;
+	pHalData->UsbRxAggPageCount	= 48; //uint :128 b //0x0A;	// 10 = MAX_RX_DMA_BUFFER_SIZE/2/pHalData->UsbBulkOutSize
+	pHalData->UsbRxAggPageTimeout	= 0x4; //6, absolute time = 34ms/(2^6)
+#endif
+
+	HalUsbSetQueuePipeMapping8188EUsb(padapter,
+				pdvobjpriv->RtNumInPipes, pdvobjpriv->RtNumOutPipes);
+
+}
+
+static u32 rtl8188eu_InitPowerOn(_adapter *padapter)
+{
+	u16 value16;
+	// HW Power on sequence
+	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(padapter);
+	if(_TRUE == pHalData->bMacPwrCtrlOn)
+		return _SUCCESS;
+	
+	if(!HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, Rtl8188E_NIC_PWR_ON_FLOW))
+	{
+		DBG_871X(KERN_ERR "%s: run power on flow fail\n", __func__);
+		return _FAIL;	
+	}
+
+	// Enable MAC DMA/WMAC/SCHEDULE/SEC block
+	// Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy. Added by tynli. 2011.08.31.
+	rtw_write16(padapter, REG_CR, 0x00);  //suggseted by zhouzhou, by page, 20111230
+
+
+		// Enable MAC DMA/WMAC/SCHEDULE/SEC block
+	value16 = rtw_read16(padapter, REG_CR);
+	value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN
+				| PROTOCOL_EN | SCHEDULE_EN | ENSEC | CALTMR_EN);
+	// for SDIO - Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy. Added by tynli. 2011.08.31.
+	
+	rtw_write16(padapter, REG_CR, value16);
+	pHalData->bMacPwrCtrlOn = _TRUE;
+
+	return _SUCCESS;
+
+}
+
+
+static void _dbg_dump_macreg(_adapter *padapter)
+{
+	u32 offset = 0;
+	u32 val32 = 0;
+	u32 index =0 ;
+	for(index=0;index<64;index++)
+	{
+		offset = index*4;
+		val32 = rtw_read32(padapter,offset);
+		DBG_8192C("offset : 0x%02x ,val:0x%08x\n",offset,val32);
+	}
+}
+
+
+static void _InitPABias(_adapter *padapter)
+{
+	HAL_DATA_TYPE		*pHalData	= GET_HAL_DATA(padapter);
+	u8			pa_setting;
+	BOOLEAN		is92C = IS_92C_SERIAL(pHalData->VersionID);
+	
+	//FIXED PA current issue
+	//efuse_one_byte_read(padapter, 0x1FA, &pa_setting);
+	pa_setting = EFUSE_Read1Byte(padapter, 0x1FA);
+
+	//RT_TRACE(COMP_INIT, DBG_LOUD, ("_InitPABias 0x1FA 0x%x \n",pa_setting));
+
+	if(!(pa_setting & BIT0))
+	{
+		PHY_SetRFReg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0x0F406);
+		PHY_SetRFReg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0x4F406);		
+		PHY_SetRFReg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0x8F406);		
+		PHY_SetRFReg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0xCF406);		
+		//RT_TRACE(COMP_INIT, DBG_LOUD, ("PA BIAS path A\n"));
+	}	
+
+	if(!(pa_setting & BIT1) && is92C)
+	{
+		PHY_SetRFReg(padapter,RF_PATH_B, 0x15, 0x0FFFFF, 0x0F406);
+		PHY_SetRFReg(padapter,RF_PATH_B, 0x15, 0x0FFFFF, 0x4F406);
+		PHY_SetRFReg(padapter,RF_PATH_B, 0x15, 0x0FFFFF, 0x8F406);
+		PHY_SetRFReg(padapter,RF_PATH_B, 0x15, 0x0FFFFF, 0xCF406);
+		//RT_TRACE(COMP_INIT, DBG_LOUD, ("PA BIAS path B\n"));
+	}
+
+	if(!(pa_setting & BIT4))
+	{
+		pa_setting = rtw_read8(padapter, 0x16);
+		pa_setting &= 0x0F;
+		rtw_write8(padapter, 0x16, pa_setting | 0x80);
+		rtw_write8(padapter, 0x16, pa_setting | 0x90);		
+	}
+}
+#ifdef CONFIG_BT_COEXIST
+static void _InitBTCoexist(_adapter *padapter)
+{
+	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(padapter);
+	struct btcoexist_priv	*pbtpriv = &(pHalData->bt_coexist);
+	u8 u1Tmp;
+
+	if(pbtpriv->BT_Coexist && pbtpriv->BT_CoexistType == BT_CSR_BC4)
+	{
+
+//#if MP_DRIVER != 1
+	if (padapter->registrypriv.mp_mode == 0)
+	{	
+		if(pbtpriv->BT_Ant_isolation)
+		{
+			rtw_write8( padapter,REG_GPIO_MUXCFG, 0xa0);
+			DBG_8192C("BT write 0x%x = 0x%x\n", REG_GPIO_MUXCFG, 0xa0);
+		}
+	}
+//#endif		
+
+		u1Tmp = rtw_read8(padapter, 0x4fd) & BIT0;
+		u1Tmp = u1Tmp | 
+				((pbtpriv->BT_Ant_isolation==1)?0:BIT1) | 
+				((pbtpriv->BT_Service==BT_SCO)?0:BIT2);
+		rtw_write8( padapter, 0x4fd, u1Tmp);
+		DBG_8192C("BT write 0x%x = 0x%x for non-isolation\n", 0x4fd, u1Tmp);
+		
+		
+		rtw_write32(padapter, REG_BT_COEX_TABLE+4, 0xaaaa9aaa);
+		DBG_8192C("BT write 0x%x = 0x%x\n", REG_BT_COEX_TABLE+4, 0xaaaa9aaa);
+		
+		rtw_write32(padapter, REG_BT_COEX_TABLE+8, 0xffbd0040);
+		DBG_8192C("BT write 0x%x = 0x%x\n", REG_BT_COEX_TABLE+8, 0xffbd0040);
+
+		rtw_write32(padapter,  REG_BT_COEX_TABLE+0xc, 0x40000010);
+		DBG_8192C("BT write 0x%x = 0x%x\n", REG_BT_COEX_TABLE+0xc, 0x40000010);
+
+		//Config to 1T1R
+		u1Tmp =  rtw_read8(padapter,rOFDM0_TRxPathEnable);
+		u1Tmp &= ~(BIT1);
+		rtw_write8( padapter, rOFDM0_TRxPathEnable, u1Tmp);
+		DBG_8192C("BT write 0xC04 = 0x%x\n", u1Tmp);
+			
+		u1Tmp = rtw_read8(padapter, rOFDM1_TRxPathEnable);
+		u1Tmp &= ~(BIT1);
+		rtw_write8( padapter, rOFDM1_TRxPathEnable, u1Tmp);
+		DBG_8192C("BT write 0xD04 = 0x%x\n", u1Tmp);
+
+	}
+}
+#endif
+
+
+
+//---------------------------------------------------------------
+//
+//	MAC init functions
+//
+//---------------------------------------------------------------
+static VOID
+_SetMacID(
+	IN  PADAPTER Adapter, u8* MacID
+	)
+{
+	u32 i;
+	for(i=0 ; i< MAC_ADDR_LEN ; i++){
+#ifdef  CONFIG_CONCURRENT_MODE		
+		if(Adapter->iface_type == IFACE_PORT1)
+			rtw_write32(Adapter, REG_MACID1+i, MacID[i]);
+		else
+#endif			
+		rtw_write32(Adapter, REG_MACID+i, MacID[i]);
+	}
+}
+
+static VOID
+_SetBSSID(
+	IN  PADAPTER Adapter, u8* BSSID
+	)
+{
+	u32 i;
+	for(i=0 ; i< MAC_ADDR_LEN ; i++){
+#ifdef  CONFIG_CONCURRENT_MODE		
+		if(Adapter->iface_type == IFACE_PORT1)
+			rtw_write32(Adapter, REG_BSSID1+i, BSSID[i]);
+		else
+#endif			
+		rtw_write32(Adapter, REG_BSSID+i, BSSID[i]);
+	}
+}
+
+
+// Shall USB interface init this?
+static VOID
+_InitInterrupt(
+	IN  PADAPTER Adapter
+	)
+{
+	u32	imr,imr_ex;
+	u8  usb_opt;
+	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(Adapter);
+
+	//HISR write one to clear
+	rtw_write32(Adapter, REG_HISR_88E, 0xFFFFFFFF);
+	// HIMR - 	
+	imr = IMR_PSTIMEOUT_88E | IMR_TBDER_88E | IMR_CPWM_88E | IMR_CPWM2_88E ;		
+	rtw_write32(Adapter, REG_HIMR_88E, imr);
+	pHalData->IntrMask[0]=imr;
+	
+	imr_ex = IMR_TXERR_88E | IMR_RXERR_88E | IMR_TXFOVW_88E |IMR_RXFOVW_88E;	
+	rtw_write32(Adapter, REG_HIMRE_88E, imr_ex);
+	pHalData->IntrMask[1]=imr_ex;
+	
+#ifdef CONFIG_SUPPORT_USB_INT
+	// REG_USB_SPECIAL_OPTION - BIT(4)
+	// 0; Use interrupt endpoint to upload interrupt pkt
+	// 1; Use bulk endpoint to upload interrupt pkt,	
+	usb_opt = rtw_read8(Adapter, REG_USB_SPECIAL_OPTION);
+
+
+	if(!adapter_to_dvobj(Adapter)->ishighspeed
+		#ifdef CONFIG_USB_INTERRUPT_IN_PIPE
+		|| pHalData->RtIntInPipe == 0x05
+		#endif
+	)
+		usb_opt = usb_opt & (~INT_BULK_SEL);
+	else	
+		usb_opt = usb_opt | (INT_BULK_SEL);
+
+	rtw_write8(Adapter, REG_USB_SPECIAL_OPTION, usb_opt );			
+
+#endif//CONFIG_SUPPORT_USB_INT
+	
+}
+
+
+static VOID
+_InitQueueReservedPage(
+	IN  PADAPTER Adapter
+	)
+{
+	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(Adapter);
+	struct registry_priv	*pregistrypriv = &Adapter->registrypriv;
+	u32			outEPNum	= (u32)pHalData->OutEpNumber;
+	u32			numHQ		= 0;
+	u32			numLQ		= 0;
+	u32			numNQ		= 0;
+	u32			numPubQ;
+	u32			value32;
+	u8			value8;
+	BOOLEAN			bWiFiConfig	= pregistrypriv->wifi_spec;
+
+	if(bWiFiConfig)
+	{
+		if (pHalData->OutEpQueueSel & TX_SELE_HQ)
+		{
+			numHQ =  0x29;
+		}
+
+		if (pHalData->OutEpQueueSel & TX_SELE_LQ)
+		{
+			numLQ = 0x1C;
+		}
+
+		// NOTE: This step shall be proceed before writting REG_RQPN.
+		if (pHalData->OutEpQueueSel & TX_SELE_NQ) {
+			numNQ = 0x1C;
+		}
+		value8 = (u8)_NPQ(numNQ);
+		rtw_write8(Adapter, REG_RQPN_NPQ, value8);
+
+		numPubQ = 0xA8 - numHQ - numLQ - numNQ;
+
+		// TX DMA
+		value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
+		rtw_write32(Adapter, REG_RQPN, value32);
+	}
+	else
+	{
+		rtw_write16(Adapter,REG_RQPN_NPQ, 0x0000);//Just follow MP Team,??? Georgia 03/28
+		rtw_write16(Adapter,REG_RQPN_NPQ, 0x0d);
+		rtw_write32(Adapter,REG_RQPN, 0x808E000d);//reserve 7 page for LPS	
+	}
+}
+
+static VOID
+_InitTxBufferBoundary(
+	IN PADAPTER Adapter,
+	IN u8 txpktbuf_bndy
+	)
+{	
+	struct registry_priv *pregistrypriv = &Adapter->registrypriv;
+	//HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+
+	//u16	txdmactrl;
+
+	rtw_write8(Adapter, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
+	rtw_write8(Adapter, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
+	rtw_write8(Adapter, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy);
+	rtw_write8(Adapter, REG_TRXFF_BNDY, txpktbuf_bndy);
+	rtw_write8(Adapter, REG_TDECTRL+1, txpktbuf_bndy);
+
+}
+
+static VOID
+_InitPageBoundary(
+	IN  PADAPTER Adapter
+	)
+{
+	// RX Page Boundary	
+	// 	
+	u16 rxff_bndy = MAX_RX_DMA_BUFFER_SIZE_88E-1;
+
+	#if 0
+
+	// RX Page Boundary
+	//srand(static_cast<unsigned int>(time(NULL)) );
+	if(bSupportRemoteWakeUp)
+	{
+		Offset = MAX_RX_DMA_BUFFER_SIZE_88E+MAX_TX_REPORT_BUFFER_SIZE-MAX_SUPPORT_WOL_PATTERN_NUM(Adapter)*WKFMCAM_SIZE;
+		Offset = Offset / 128; // RX page size = 128 byte
+		rxff_bndy= (Offset*128) -1;	
+	}
+	else
+		
+	#endif
+	rtw_write16(Adapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
+}
+
+
+static VOID
+_InitNormalChipRegPriority(
+	IN	PADAPTER	Adapter,
+	IN	u16		beQ,
+	IN	u16		bkQ,
+	IN	u16		viQ,
+	IN	u16		voQ,
+	IN	u16		mgtQ,
+	IN	u16		hiQ
+	)
+{
+	u16 value16	= (rtw_read16(Adapter, REG_TRXDMA_CTRL) & 0x7);
+
+	value16 |=	_TXDMA_BEQ_MAP(beQ) 	| _TXDMA_BKQ_MAP(bkQ) |
+				_TXDMA_VIQ_MAP(viQ) 	| _TXDMA_VOQ_MAP(voQ) |
+				_TXDMA_MGQ_MAP(mgtQ)| _TXDMA_HIQ_MAP(hiQ);
+	
+	rtw_write16(Adapter, REG_TRXDMA_CTRL, value16);
+}
+
+static VOID
+_InitNormalChipOneOutEpPriority(
+	IN	PADAPTER Adapter
+	)
+{
+	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(Adapter);
+
+	u16	value = 0;
+	switch(pHalData->OutEpQueueSel)
+	{
+		case TX_SELE_HQ:
+			value = QUEUE_HIGH;
+			break;
+		case TX_SELE_LQ:
+			value = QUEUE_LOW;
+			break;
+		case TX_SELE_NQ:
+			value = QUEUE_NORMAL;
+			break;
+		default:
+			//RT_ASSERT(FALSE,("Shall not reach here!\n"));
+			break;
+	}
+	
+	_InitNormalChipRegPriority(Adapter,
+								value,
+								value,
+								value,
+								value,
+								value,
+								value
+								);
+
+}
+
+static VOID
+_InitNormalChipTwoOutEpPriority(
+	IN	PADAPTER Adapter
+	)
+{
+	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(Adapter);
+	struct registry_priv *pregistrypriv = &Adapter->registrypriv;
+	u16			beQ,bkQ,viQ,voQ,mgtQ,hiQ;
+	
+
+	u16	valueHi = 0;
+	u16	valueLow = 0;
+	
+	switch(pHalData->OutEpQueueSel)
+	{
+		case (TX_SELE_HQ | TX_SELE_LQ):
+			valueHi = QUEUE_HIGH;
+			valueLow = QUEUE_LOW;
+			break;
+		case (TX_SELE_NQ | TX_SELE_LQ):
+			valueHi = QUEUE_NORMAL;
+			valueLow = QUEUE_LOW;
+			break;
+		case (TX_SELE_HQ | TX_SELE_NQ):
+			valueHi = QUEUE_HIGH;
+			valueLow = QUEUE_NORMAL;
+			break;
+		default:
+			//RT_ASSERT(FALSE,("Shall not reach here!\n"));
+			break;
+	}
+
+	if(!pregistrypriv->wifi_spec ){
+		beQ		= valueLow;
+		bkQ		= valueLow;
+		viQ		= valueHi;
+		voQ		= valueHi;
+		mgtQ	= valueHi; 
+		hiQ		= valueHi;								
+	}
+	else{//for WMM ,CONFIG_OUT_EP_WIFI_MODE
+		beQ		= valueLow;
+		bkQ		= valueHi;		
+		viQ		= valueHi;
+		voQ		= valueLow;
+		mgtQ	= valueHi;
+		hiQ		= valueHi;							
+	}
+
+	_InitNormalChipRegPriority(Adapter,beQ,bkQ,viQ,voQ,mgtQ,hiQ);
+
+}
+
+static VOID
+_InitNormalChipThreeOutEpPriority(
+	IN	PADAPTER Adapter
+	)
+{
+	struct registry_priv *pregistrypriv = &Adapter->registrypriv;
+	u16			beQ,bkQ,viQ,voQ,mgtQ,hiQ;
+
+	if(!pregistrypriv->wifi_spec ){// typical setting
+		beQ		= QUEUE_LOW;
+		bkQ 		= QUEUE_LOW;
+		viQ 		= QUEUE_NORMAL;
+		voQ 		= QUEUE_HIGH;
+		mgtQ 	= QUEUE_HIGH;
+		hiQ 		= QUEUE_HIGH;			
+	}
+	else{// for WMM
+		beQ		= QUEUE_LOW;
+		bkQ 		= QUEUE_NORMAL;
+		viQ 		= QUEUE_NORMAL;
+		voQ 		= QUEUE_HIGH;
+		mgtQ 	= QUEUE_HIGH;
+		hiQ 		= QUEUE_HIGH;			
+	}
+	_InitNormalChipRegPriority(Adapter,beQ,bkQ,viQ,voQ,mgtQ,hiQ);
+}
+
+static VOID
+_InitQueuePriority(
+	IN	PADAPTER Adapter
+	)
+{
+	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(Adapter);
+
+	switch(pHalData->OutEpNumber)
+	{
+		case 1:
+			_InitNormalChipOneOutEpPriority(Adapter);
+			break;
+		case 2:
+			_InitNormalChipTwoOutEpPriority(Adapter);
+			break;
+		case 3:
+			_InitNormalChipThreeOutEpPriority(Adapter);
+			break;
+		default:
+			//RT_ASSERT(FALSE,("Shall not reach here!\n"));
+			break;
+	}
+
+
+}
+
+
+
+static VOID
+_InitHardwareDropIncorrectBulkOut(
+	IN  PADAPTER Adapter
+	)
+{
+	u32	value32 = rtw_read32(Adapter, REG_TXDMA_OFFSET_CHK);
+	value32 |= DROP_DATA_EN;
+	rtw_write32(Adapter, REG_TXDMA_OFFSET_CHK, value32);
+}
+
+static VOID
+_InitNetworkType(
+	IN  PADAPTER Adapter
+	)
+{
+	u32	value32;
+
+	value32 = rtw_read32(Adapter, REG_CR);
+	// TODO: use the other function to set network type
+	value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP);
+
+	rtw_write32(Adapter, REG_CR, value32);
+//	RASSERT(pIoBase->rtw_read8(REG_CR + 2) == 0x2);
+}
+
+static VOID
+_InitTransferPageSize(
+	IN  PADAPTER Adapter
+	)
+{
+	// Tx page size is always 128.
+	
+	u8	value8;
+	value8 = _PSRX(PBP_128) | _PSTX(PBP_128);
+	rtw_write8(Adapter, REG_PBP, value8);
+}
+
+static VOID
+_InitDriverInfoSize(
+	IN  PADAPTER	Adapter,
+	IN	u8		drvInfoSize
+	)
+{
+	rtw_write8(Adapter,REG_RX_DRVINFO_SZ, drvInfoSize);
+}
+
+static VOID
+_InitWMACSetting(
+	IN  PADAPTER Adapter
+	)
+{
+	//u4Byte			value32;
+	//u16			value16;
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
+
+	//pHalData->ReceiveConfig = AAP | APM | AM | AB | APP_ICV | ADF | AMF | APP_FCS | HTC_LOC_CTRL | APP_MIC | APP_PHYSTS;
+	//pHalData->ReceiveConfig = 
+	//RCR_AAP | RCR_APM | RCR_AM | RCR_AB |RCR_CBSSID_DATA| RCR_CBSSID_BCN| RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL | RCR_APP_MIC | RCR_APP_PHYSTS;	  
+	 // don't turn on AAP, it will allow all packets to driver
+        pHalData->ReceiveConfig = RCR_APM | RCR_AM | RCR_AB |RCR_CBSSID_DATA| RCR_CBSSID_BCN| RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL | RCR_APP_MIC | RCR_APP_PHYSTS;	 
+	 
+#if (1 == RTL8188E_RX_PACKET_INCLUDE_CRC)
+	pHalData->ReceiveConfig |= ACRC32;
+#endif
+
+	// some REG_RCR will be modified later by phy_ConfigMACWithHeaderFile()
+	rtw_write32(Adapter, REG_RCR, pHalData->ReceiveConfig);
+
+	// Accept all multicast address
+	rtw_write32(Adapter, REG_MAR, 0xFFFFFFFF);
+	rtw_write32(Adapter, REG_MAR + 4, 0xFFFFFFFF);
+
+
+	// Accept all data frames
+	//value16 = 0xFFFF;
+	//rtw_write16(Adapter, REG_RXFLTMAP2, value16);
+
+	// 2010.09.08 hpfan
+	// Since ADF is removed from RCR, ps-poll will not be indicate to driver,
+	// RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll.
+	//value16 = 0x400;
+	//rtw_write16(Adapter, REG_RXFLTMAP1, value16);
+
+	// Accept all management frames
+	//value16 = 0xFFFF;
+	//rtw_write16(Adapter, REG_RXFLTMAP0, value16);
+
+	//enable RX_SHIFT bits
+	//rtw_write8(Adapter, REG_TRXDMA_CTRL, rtw_read8(Adapter, REG_TRXDMA_CTRL)|BIT(1));	
+
+}
+
+static VOID
+_InitAdaptiveCtrl(
+	IN  PADAPTER Adapter
+	)
+{
+	u16	value16;
+	u32	value32;
+
+	// Response Rate Set
+	value32 = rtw_read32(Adapter, REG_RRSR);
+	value32 &= ~RATE_BITMAP_ALL;
+	value32 |= RATE_RRSR_CCK_ONLY_1M;
+	rtw_write32(Adapter, REG_RRSR, value32);
+
+	// CF-END Threshold
+	//m_spIoBase->rtw_write8(REG_CFEND_TH, 0x1);
+
+	// SIFS (used in NAV)
+	value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
+	rtw_write16(Adapter, REG_SPEC_SIFS, value16);
+
+	// Retry Limit
+	value16 = _LRL(0x30) | _SRL(0x30);
+	rtw_write16(Adapter, REG_RL, value16);
+	
+}
+
+static VOID
+_InitRateFallback(
+	IN  PADAPTER Adapter
+	)
+{
+	// Set Data Auto Rate Fallback Retry Count register.
+	rtw_write32(Adapter, REG_DARFRC, 0x00000000);
+	rtw_write32(Adapter, REG_DARFRC+4, 0x10080404);
+	rtw_write32(Adapter, REG_RARFRC, 0x04030201);
+	rtw_write32(Adapter, REG_RARFRC+4, 0x08070605);
+
+}
+
+
+static VOID
+_InitEDCA(
+	IN  PADAPTER Adapter
+	)
+{
+	// Set Spec SIFS (used in NAV)
+	rtw_write16(Adapter,REG_SPEC_SIFS, 0x100a);
+	rtw_write16(Adapter,REG_MAC_SPEC_SIFS, 0x100a);
+
+	// Set SIFS for CCK
+	rtw_write16(Adapter,REG_SIFS_CTX, 0x100a);	
+
+	// Set SIFS for OFDM
+	rtw_write16(Adapter,REG_SIFS_TRX, 0x100a);
+
+	// TXOP
+	rtw_write32(Adapter, REG_EDCA_BE_PARAM, 0x005EA42B);
+	rtw_write32(Adapter, REG_EDCA_BK_PARAM, 0x0000A44F);
+	rtw_write32(Adapter, REG_EDCA_VI_PARAM, 0x005EA324);
+	rtw_write32(Adapter, REG_EDCA_VO_PARAM, 0x002FA226);
+}
+
+
+static VOID
+_InitBeaconMaxError(
+	IN  PADAPTER	Adapter,
+	IN	BOOLEAN		InfraMode
+	)
+{
+
+}
+
+
+#ifdef CONFIG_LED
+static void _InitHWLed(PADAPTER Adapter)
+{
+	struct led_priv *pledpriv = &(Adapter->ledpriv);
+	
+	if( pledpriv->LedStrategy != HW_LED)
+		return;
+	
+// HW led control
+// to do .... 
+//must consider cases of antenna diversity/ commbo card/solo card/mini card
+
+}
+#endif //CONFIG_LED
+
+static VOID
+_InitRDGSetting(
+	IN	PADAPTER Adapter
+	)
+{
+	rtw_write8(Adapter,REG_RD_CTRL,0xFF);
+	rtw_write16(Adapter, REG_RD_NAV_NXT, 0x200);
+	rtw_write8(Adapter,REG_RD_RESP_PKT_TH,0x05);
+}
+
+static VOID
+_InitRxSetting(
+	IN	PADAPTER Adapter
+	)
+{
+	rtw_write32(Adapter, REG_MACID, 0x87654321);
+	rtw_write32(Adapter, 0x0700, 0x87654321);
+}
+
+static VOID
+_InitRetryFunction(
+	IN  PADAPTER Adapter
+	)
+{
+	u8	value8;
+	
+	value8 = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL);
+	value8 |= EN_AMPDU_RTY_NEW;
+	rtw_write8(Adapter, REG_FWHW_TXQ_CTRL, value8);
+
+	// Set ACK timeout
+	rtw_write8(Adapter, REG_ACKTO, 0x40);
+}
+
+/*-----------------------------------------------------------------------------
+ * Function:	usb_AggSettingTxUpdate()
+ *
+ * Overview:	Seperate TX/RX parameters update independent for TP detection and 
+ *			dynamic TX/RX aggreagtion parameters update.
+ *
+ * Input:			PADAPTER
+ *
+ * Output/Return:	NONE
+ *
+ * Revised History:
+ *	When		Who		Remark
+ *	12/10/2010	MHC		Seperate to smaller function.
+ *
+ *---------------------------------------------------------------------------*/
+static VOID
+usb_AggSettingTxUpdate(
+	IN	PADAPTER			Adapter
+	)
+{
+#ifdef CONFIG_USB_TX_AGGREGATION
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
+	//PMGNT_INFO		pMgntInfo = &(Adapter->MgntInfo);	
+	u32			value32;
+
+	if(Adapter->registrypriv.wifi_spec)
+		pHalData->UsbTxAggMode = _FALSE;
+
+	if(pHalData->UsbTxAggMode){
+		value32 = rtw_read32(Adapter, REG_TDECTRL);
+		value32 = value32 & ~(BLK_DESC_NUM_MASK << BLK_DESC_NUM_SHIFT);
+		value32 |= ((pHalData->UsbTxAggDescNum & BLK_DESC_NUM_MASK) << BLK_DESC_NUM_SHIFT);
+		
+		rtw_write32(Adapter, REG_TDECTRL, value32);
+	}
+	
+#endif
+}	// usb_AggSettingTxUpdate
+
+
+/*-----------------------------------------------------------------------------
+ * Function:	usb_AggSettingRxUpdate()
+ *
+ * Overview:	Seperate TX/RX parameters update independent for TP detection and 
+ *			dynamic TX/RX aggreagtion parameters update.
+ *
+ * Input:			PADAPTER
+ *
+ * Output/Return:	NONE
+ *
+ * Revised History:
+ *	When		Who		Remark
+ *	12/10/2010	MHC		Seperate to smaller function.
+ *
+ *---------------------------------------------------------------------------*/
+static VOID
+usb_AggSettingRxUpdate(
+	IN	PADAPTER			Adapter
+	)
+{
+#ifdef CONFIG_USB_RX_AGGREGATION
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
+	//PMGNT_INFO		pMgntInfo = &(Adapter->MgntInfo);
+	u8			valueDMA;
+	u8			valueUSB;
+
+	valueDMA = rtw_read8(Adapter, REG_TRXDMA_CTRL);
+	valueUSB = rtw_read8(Adapter, REG_USB_SPECIAL_OPTION);
+
+	switch(pHalData->UsbRxAggMode)
+	{
+		case USB_RX_AGG_DMA:
+			valueDMA |= RXDMA_AGG_EN;
+			valueUSB &= ~USB_AGG_EN;
+			break;
+		case USB_RX_AGG_USB:
+			valueDMA &= ~RXDMA_AGG_EN;
+			valueUSB |= USB_AGG_EN;
+			break;
+		case USB_RX_AGG_MIX:
+			valueDMA |= RXDMA_AGG_EN;
+			valueUSB |= USB_AGG_EN;
+			break;
+		case USB_RX_AGG_DISABLE:
+		default:
+			valueDMA &= ~RXDMA_AGG_EN;
+			valueUSB &= ~USB_AGG_EN;
+			break;
+	}
+
+	rtw_write8(Adapter, REG_TRXDMA_CTRL, valueDMA);
+	rtw_write8(Adapter, REG_USB_SPECIAL_OPTION, valueUSB);
+
+	switch(pHalData->UsbRxAggMode)
+	{
+		case USB_RX_AGG_DMA:
+			rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, pHalData->UsbRxAggPageCount);
+			rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH+1, pHalData->UsbRxAggPageTimeout);
+			break;
+		case USB_RX_AGG_USB:
+			rtw_write8(Adapter, REG_USB_AGG_TH, pHalData->UsbRxAggBlockCount);
+			rtw_write8(Adapter, REG_USB_AGG_TO, pHalData->UsbRxAggBlockTimeout);
+			break;
+		case USB_RX_AGG_MIX:
+			rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, pHalData->UsbRxAggPageCount);
+			rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH+1, (pHalData->UsbRxAggPageTimeout& 0x1F));//0x280[12:8]
+			
+			rtw_write8(Adapter, REG_USB_AGG_TH, pHalData->UsbRxAggBlockCount);
+			rtw_write8(Adapter, REG_USB_AGG_TO, pHalData->UsbRxAggBlockTimeout);			
+		
+			break;
+		case USB_RX_AGG_DISABLE:
+		default:
+			// TODO: 
+			break;
+	}
+
+	switch(PBP_128)
+	{
+		case PBP_128:
+			pHalData->HwRxPageSize = 128;
+			break;
+		case PBP_64:
+			pHalData->HwRxPageSize = 64;
+			break;
+		case PBP_256:
+			pHalData->HwRxPageSize = 256;
+			break;
+		case PBP_512:
+			pHalData->HwRxPageSize = 512;
+			break;
+		case PBP_1024:
+			pHalData->HwRxPageSize = 1024;
+			break;
+		default:
+			//RT_ASSERT(FALSE, ("RX_PAGE_SIZE_REG_VALUE definition is incorrect!\n"));
+			break;
+	}
+#endif
+}	// usb_AggSettingRxUpdate
+
+static VOID
+InitUsbAggregationSetting(
+	IN  PADAPTER Adapter
+	)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
+
+	// Tx aggregation setting
+	usb_AggSettingTxUpdate(Adapter);
+
+	// Rx aggregation setting
+	usb_AggSettingRxUpdate(Adapter);
+
+	// 201/12/10 MH Add for USB agg mode dynamic switch.
+	pHalData->UsbRxHighSpeedMode = _FALSE;
+}
+VOID
+HalRxAggr8188EUsb(
+	IN  PADAPTER Adapter,
+	IN BOOLEAN	Value
+	)
+{
+#if 0//USB_RX_AGGREGATION_92C
+
+	PMGNT_INFO		pMgntInfo = &Adapter->MgntInfo;
+	u1Byte			valueDMATimeout;
+	u1Byte			valueDMAPageCount;
+	u1Byte			valueUSBTimeout;
+	u1Byte			valueUSBBlockCount;
+
+	// selection to prevent bad TP.
+	if( IS_WIRELESS_MODE_B(Adapter) || IS_WIRELESS_MODE_G(Adapter) || IS_WIRELESS_MODE_A(Adapter)|| pMgntInfo->bWiFiConfg)
+	{
+		// 2010.04.27 hpfan
+		// Adjust RxAggrTimeout to close to zero disable RxAggr, suggested by designer
+		// Timeout value is calculated by 34 / (2^n)
+		valueDMATimeout = 0x0f;
+		valueDMAPageCount = 0x01;
+		valueUSBTimeout = 0x0f;
+		valueUSBBlockCount = 0x01;
+		rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_PGTO, (pu1Byte)&valueDMATimeout);
+		rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_PGTH, (pu1Byte)&valueDMAPageCount);
+		rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_USBTO, (pu1Byte)&valueUSBTimeout);
+		rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_USBTH, (pu1Byte)&valueUSBBlockCount);
+	}
+	else
+	{
+		rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_USBTO, (pu1Byte)&pMgntInfo->RegRxAggBlockTimeout);
+		rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_USBTH, (pu1Byte)&pMgntInfo->RegRxAggBlockCount);
+	}
+
+#endif
+}
+
+/*-----------------------------------------------------------------------------
+ * Function:	USB_AggModeSwitch()
+ *
+ * Overview:	When RX traffic is more than 40M, we need to adjust some parameters to increase
+ *			RX speed by increasing batch indication size. This will decrease TCP ACK speed, we
+ *			need to monitor the influence of FTP/network share.
+ *			For TX mode, we are still ubder investigation.
+ *
+ * Input:		PADAPTER
+ *
+ * Output:		NONE
+ *
+ * Return:		NONE
+ *
+ * Revised History:
+ *	When		Who		Remark
+ *	12/10/2010	MHC		Create Version 0.  
+ *
+ *---------------------------------------------------------------------------*/
+VOID
+USB_AggModeSwitch(
+	IN	PADAPTER			Adapter
+	)
+{
+#if 0
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
+	PMGNT_INFO		pMgntInfo = &(Adapter->MgntInfo);
+
+	//pHalData->UsbRxHighSpeedMode = FALSE;
+	// How to measure the RX speed? We assume that when traffic is more than 
+	if (pMgntInfo->bRegAggDMEnable == FALSE)
+	{
+		return;	// Inf not support.
+	}
+	
+	
+	if (pMgntInfo->LinkDetectInfo.bHigherBusyRxTraffic == TRUE && 
+		pHalData->UsbRxHighSpeedMode == FALSE)
+	{
+		pHalData->UsbRxHighSpeedMode = TRUE;
+		RT_TRACE(COMP_INIT, DBG_LOUD, ("UsbAggModeSwitchCheck to HIGH\n"));
+	}
+	else if (pMgntInfo->LinkDetectInfo.bHigherBusyRxTraffic == FALSE && 
+		pHalData->UsbRxHighSpeedMode == TRUE)
+	{
+		pHalData->UsbRxHighSpeedMode = FALSE;
+		RT_TRACE(COMP_INIT, DBG_LOUD, ("UsbAggModeSwitchCheck to LOW\n"));
+	}
+	else
+	{
+		return; 
+	}
+	
+
+#if USB_RX_AGGREGATION_92C
+	if (pHalData->UsbRxHighSpeedMode == TRUE)	
+	{
+		// 2010/12/10 MH The parameter is tested by SD1 engineer and SD3 channel emulator.
+		// USB mode
+#if (RT_PLATFORM == PLATFORM_LINUX)
+		if (pMgntInfo->LinkDetectInfo.bTxBusyTraffic)
+		{
+			pHalData->RxAggBlockCount	= 16;
+			pHalData->RxAggBlockTimeout	= 7;
+		}
+		else
+#endif
+		{
+			pHalData->RxAggBlockCount	= 40;
+			pHalData->RxAggBlockTimeout	= 5;
+		}
+		// Mix mode
+		pHalData->RxAggPageCount	= 72;
+		pHalData->RxAggPageTimeout	= 6;		
+	}
+	else
+	{
+		// USB mode
+		pHalData->RxAggBlockCount	= pMgntInfo->RegRxAggBlockCount;
+		pHalData->RxAggBlockTimeout	= pMgntInfo->RegRxAggBlockTimeout;	
+		// Mix mode
+		pHalData->RxAggPageCount		= pMgntInfo->RegRxAggPageCount;
+		pHalData->RxAggPageTimeout	= pMgntInfo->RegRxAggPageTimeout;	
+	}
+
+	if (pHalData->RxAggBlockCount > MAX_RX_AGG_BLKCNT)
+		pHalData->RxAggBlockCount = MAX_RX_AGG_BLKCNT;
+#if (OS_WIN_FROM_VISTA(OS_VERSION)) || (RT_PLATFORM == PLATFORM_LINUX)	// do not support WINXP to prevent usbehci.sys BSOD
+	if (IS_WIRELESS_MODE_N_24G(Adapter) || IS_WIRELESS_MODE_N_5G(Adapter))
+	{
+		//
+		// 2010/12/24 MH According to V1012 QC IOT test, XP BSOD happen when running chariot test
+		// with the aggregation dynamic change!! We need to disable the function to prevent it is broken
+		// in usbehci.sys.
+		//
+		usb_AggSettingRxUpdate_8188E(Adapter);
+
+		// 2010/12/27 MH According to designer's suggstion, we can only modify Timeout value. Otheriwse
+		// there might many HW incorrect behavior, the XP BSOD at usbehci.sys may be relative to the 
+		// issue. Base on the newest test, we can not enable block cnt > 30, otherwise XP usbehci.sys may
+		// BSOD.
+	}
+#endif
+	
+#endif
+#endif
+}	// USB_AggModeSwitch
+
+static VOID
+_InitOperationMode(
+	IN	PADAPTER			Adapter
+	)
+{
+#if 0//gtest
+	PHAL_DATA_TYPE	pHalData = GET_HAL_DATA(Adapter);
+	u1Byte				regBwOpMode = 0;
+	u4Byte				regRATR = 0, regRRSR = 0;
+
+
+	//1 This part need to modified according to the rate set we filtered!!
+	//
+	// Set RRSR, RATR, and REG_BWOPMODE registers
+	//
+	switch(Adapter->RegWirelessMode)
+	{
+		case WIRELESS_MODE_B:
+			regBwOpMode = BW_OPMODE_20MHZ;
+			regRATR = RATE_ALL_CCK;
+			regRRSR = RATE_ALL_CCK;
+			break;
+		case WIRELESS_MODE_A:
+			regBwOpMode = BW_OPMODE_5G |BW_OPMODE_20MHZ;
+			regRATR = RATE_ALL_OFDM_AG;
+			regRRSR = RATE_ALL_OFDM_AG;
+			break;
+		case WIRELESS_MODE_G:
+			regBwOpMode = BW_OPMODE_20MHZ;
+			regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
+			regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
+			break;
+		case WIRELESS_MODE_AUTO:
+			if (Adapter->bInHctTest)
+			{
+			    regBwOpMode = BW_OPMODE_20MHZ;
+			    regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
+			    regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
+			}
+			else
+			{
+			    regBwOpMode = BW_OPMODE_20MHZ;
+			    regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
+			    regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
+			}
+			break;
+		case WIRELESS_MODE_N_24G:
+			// It support CCK rate by default.
+			// CCK rate will be filtered out only when associated AP does not support it.
+			regBwOpMode = BW_OPMODE_20MHZ;
+				regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
+				regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
+			break;
+		case WIRELESS_MODE_N_5G:
+			regBwOpMode = BW_OPMODE_5G;
+			regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
+			regRRSR = RATE_ALL_OFDM_AG;
+			break;
+			
+		default: //for MacOSX compiler warning.
+			break;
+	}
+
+	// Ziv ????????
+	//PlatformEFIOWrite4Byte(Adapter, REG_INIRTS_RATE_SEL, regRRSR);
+	PlatformEFIOWrite1Byte(Adapter, REG_BWOPMODE, regBwOpMode);
+#endif
+}
+
+
+ static VOID
+_InitBeaconParameters(
+	IN  PADAPTER Adapter
+	)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
+
+	rtw_write16(Adapter, REG_BCN_CTRL, 0x1010);
+
+	// TODO: Remove these magic number
+	rtw_write16(Adapter, REG_TBTT_PROHIBIT,0x6404);// ms
+	rtw_write8(Adapter, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME);// 5ms
+	rtw_write8(Adapter, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME); // 2ms
+
+	// Suggested by designer timchen. Change beacon AIFS to the largest number
+	// beacause test chip does not contension before sending beacon. by tynli. 2009.11.03
+	rtw_write16(Adapter, REG_BCNTCFG, 0x660F);
+
+	pHalData->RegBcnCtrlVal = rtw_read8(Adapter, REG_BCN_CTRL);
+	pHalData->RegTxPause = rtw_read8(Adapter, REG_TXPAUSE); 
+	pHalData->RegFwHwTxQCtrl = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL+2);
+	pHalData->RegReg542 = rtw_read8(Adapter, REG_TBTT_PROHIBIT+2);
+	pHalData->RegCR_1 = rtw_read8(Adapter, REG_CR+1);
+}
+
+static VOID
+_InitRFType(
+	IN	PADAPTER Adapter
+	)
+{
+	struct registry_priv	 *pregpriv = &Adapter->registrypriv;
+	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(Adapter);
+	BOOLEAN			is92CU		= IS_92C_SERIAL(pHalData->VersionID);
+
+#if	DISABLE_BB_RF
+	pHalData->rf_chip	= RF_PSEUDO_11N;
+	return;
+#endif
+
+	pHalData->rf_chip	= RF_6052;
+
+	if(_FALSE == is92CU){
+		pHalData->rf_type = RF_1T1R;
+		DBG_8192C("Set RF Chip ID to RF_6052 and RF type to 1T1R.\n");
+		return;
+	}
+
+	// TODO: Consider that EEPROM set 92CU to 1T1R later.
+	// Force to overwrite setting according to chip version. Ignore EEPROM setting.
+	//pHalData->RF_Type = is92CU ? RF_2T2R : RF_1T1R;
+	MSG_8192C("Set RF Chip ID to RF_6052 and RF type to %d.\n", pHalData->rf_type);
+
+}
+
+
+static VOID
+_BeaconFunctionEnable(
+	IN	PADAPTER		Adapter,
+	IN	BOOLEAN			Enable,
+	IN	BOOLEAN			Linked
+	)
+{
+	rtw_write8(Adapter, REG_BCN_CTRL, (BIT4 | BIT3 | BIT1));
+	//SetBcnCtrlReg(Adapter, (BIT4 | BIT3 | BIT1), 0x00);
+	//RT_TRACE(COMP_BEACON, DBG_LOUD, ("_BeaconFunctionEnable 0x550 0x%x\n", PlatformEFIORead1Byte(Adapter, 0x550)));			
+
+	rtw_write8(Adapter, REG_RD_CTRL+1, 0x6F);	
+}
+
+
+// Set CCK and OFDM Block "ON"
+static VOID _BBTurnOnBlock(
+	IN	PADAPTER		Adapter
+	)
+{
+#if (DISABLE_BB_RF)
+	return;
+#endif
+
+	PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bCCKEn, 0x1);
+	PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
+}
+
+static VOID _RfPowerSave(
+	IN	PADAPTER		Adapter
+	)
+{
+#if 0
+	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(Adapter);
+	PMGNT_INFO		pMgntInfo	= &(Adapter->MgntInfo);
+	u1Byte			eRFPath;
+
+#if (DISABLE_BB_RF)
+	return;
+#endif
+
+	if(pMgntInfo->RegRfOff == TRUE){ // User disable RF via registry.
+		RT_TRACE((COMP_INIT|COMP_RF), DBG_LOUD, ("InitializeAdapter8192CUsb(): Turn off RF for RegRfOff.\n"));
+		MgntActSet_RF_State(Adapter, eRfOff, RF_CHANGE_BY_SW);
+		// Those action will be discard in MgntActSet_RF_State because off the same state
+		for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
+			PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x0);
+	}
+	else if(pMgntInfo->RfOffReason > RF_CHANGE_BY_PS){ // H/W or S/W RF OFF before sleep.
+		RT_TRACE((COMP_INIT|COMP_RF), DBG_LOUD, ("InitializeAdapter8192CUsb(): Turn off RF for RfOffReason(%ld).\n", pMgntInfo->RfOffReason));
+		MgntActSet_RF_State(Adapter, eRfOff, pMgntInfo->RfOffReason);
+	}
+	else{
+		pHalData->eRFPowerState = eRfOn;
+		pMgntInfo->RfOffReason = 0; 
+		if(Adapter->bInSetPower || Adapter->bResetInProgress)
+			PlatformUsbEnableInPipes(Adapter);
+		RT_TRACE((COMP_INIT|COMP_RF), DBG_LOUD, ("InitializeAdapter8192CUsb(): RF is on.\n"));
+	}
+#endif
+}
+
+enum {
+	Antenna_Lfet = 1,
+	Antenna_Right = 2,	
+};
+
+static VOID
+_InitAntenna_Selection(IN	PADAPTER Adapter)
+{
+
+	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(Adapter);
+
+	if(pHalData->AntDivCfg==0)
+		return;
+	DBG_8192C("==>  %s ....\n",__FUNCTION__);		
+		
+	rtw_write32(Adapter, REG_LEDCFG0, rtw_read32(Adapter, REG_LEDCFG0)|BIT23);	
+	PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, BIT13, 0x01);
+		
+	if(PHY_QueryBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300) == Antenna_A)
+		pHalData->CurAntenna = Antenna_A;
+	else
+		pHalData->CurAntenna = Antenna_B;
+	DBG_8192C("%s,Cur_ant:(%x)%s\n",__FUNCTION__,pHalData->CurAntenna,(pHalData->CurAntenna == Antenna_A)?"Antenna_A":"Antenna_B");
+			
+
+}
+
+//
+// 2010/08/26 MH Add for selective suspend mode check.
+// If Efuse 0x0e bit1 is not enabled, we can not support selective suspend for Minicard and
+// slim card.
+//
+static VOID
+HalDetectSelectiveSuspendMode(
+	IN PADAPTER				Adapter
+	)
+{
+#if 0
+	u8	tmpvalue;
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
+	struct dvobj_priv	*pdvobjpriv = adapter_to_dvobj(Adapter);
+
+	// If support HW radio detect, we need to enable WOL ability, otherwise, we 
+	// can not use FW to notify host the power state switch.
+	
+	EFUSE_ShadowRead(Adapter, 1, EEPROM_USB_OPTIONAL1, (u32 *)&tmpvalue);
+
+	DBG_8192C("HalDetectSelectiveSuspendMode(): SS ");
+	if(tmpvalue & BIT1)
+	{
+		DBG_8192C("Enable\n");
+	}
+	else
+	{
+		DBG_8192C("Disable\n");
+		pdvobjpriv->RegUsbSS = _FALSE;
+	}
+
+	// 2010/09/01 MH According to Dongle Selective Suspend INF. We can switch SS mode.
+	if (pdvobjpriv->RegUsbSS && !SUPPORT_HW_RADIO_DETECT(pHalData))
+	{
+		//PMGNT_INFO				pMgntInfo = &(Adapter->MgntInfo);
+
+		//if (!pMgntInfo->bRegDongleSS)	
+		//{
+		//	RT_TRACE(COMP_INIT, DBG_LOUD, ("Dongle disable SS\n"));
+			pdvobjpriv->RegUsbSS = _FALSE;
+		//}
+	}
+#endif
+}	// HalDetectSelectiveSuspendMode
+/*-----------------------------------------------------------------------------
+ * Function:	HwSuspendModeEnable92Cu()
+ *
+ * Overview:	HW suspend mode switch.
+ *
+ * Input:		NONE
+ *
+ * Output:	NONE
+ *
+ * Return:	NONE
+ *
+ * Revised History:
+ *	When		Who		Remark
+ *	08/23/2010	MHC		HW suspend mode switch test..
+ *---------------------------------------------------------------------------*/
+static VOID 
+HwSuspendModeEnable_88eu(
+	IN	PADAPTER	pAdapter,
+	IN	u8			Type
+	)
+{
+	//PRT_USB_DEVICE 		pDevice = GET_RT_USB_DEVICE(pAdapter);
+	u16	reg = rtw_read16(pAdapter, REG_GPIO_MUXCFG);	
+
+	//if (!pDevice->RegUsbSS)
+	{
+		return;
+	}
+
+	//
+	// 2010/08/23 MH According to Alfred's suggestion, we need to to prevent HW
+	// to enter suspend mode automatically. Otherwise, it will shut down major power 
+	// domain and 8051 will stop. When we try to enter selective suspend mode, we
+	// need to prevent HW to enter D2 mode aumotmatically. Another way, Host will
+	// issue a S10 signal to power domain. Then it will cleat SIC setting(from Yngli).
+	// We need to enable HW suspend mode when enter S3/S4 or disable. We need 
+	// to disable HW suspend mode for IPS/radio_off.
+	//
+	//RT_TRACE(COMP_RF, DBG_LOUD, ("HwSuspendModeEnable92Cu = %d\n", Type));
+	if (Type == _FALSE)
+	{
+		reg |= BIT14;
+		//RT_TRACE(COMP_RF, DBG_LOUD, ("REG_GPIO_MUXCFG = %x\n", reg));
+		rtw_write16(pAdapter, REG_GPIO_MUXCFG, reg);
+		reg |= BIT12;
+		//RT_TRACE(COMP_RF, DBG_LOUD, ("REG_GPIO_MUXCFG = %x\n", reg));
+		rtw_write16(pAdapter, REG_GPIO_MUXCFG, reg);
+	}
+	else
+	{
+		reg &= (~BIT12);
+		rtw_write16(pAdapter, REG_GPIO_MUXCFG, reg);
+		reg &= (~BIT14);
+		rtw_write16(pAdapter, REG_GPIO_MUXCFG, reg);
+	}
+	
+}	// HwSuspendModeEnable92Cu
+rt_rf_power_state RfOnOffDetect(IN	PADAPTER pAdapter )
+{
+	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(pAdapter);
+	u8	val8;
+	rt_rf_power_state rfpowerstate = rf_off;
+
+	if(pAdapter->pwrctrlpriv.bHWPowerdown)
+	{
+		val8 = rtw_read8(pAdapter, REG_HSISR);
+		DBG_8192C("pwrdown, 0x5c(BIT7)=%02x\n", val8);
+		rfpowerstate = (val8 & BIT7) ? rf_off: rf_on;				
+	}
+	else // rf on/off
+	{
+		rtw_write8(	pAdapter, REG_MAC_PINMUX_CFG,rtw_read8(pAdapter, REG_MAC_PINMUX_CFG)&~(BIT3));
+		val8 = rtw_read8(pAdapter, REG_GPIO_IO_SEL);
+		DBG_8192C("GPIO_IN=%02x\n", val8);
+		rfpowerstate = (val8 & BIT3) ? rf_on : rf_off;	
+	}
+	return rfpowerstate;
+}	// HalDetectPwrDownMode
+
+void _ps_open_RF(_adapter *padapter);
+
+u32 rtl8188eu_hal_init(PADAPTER Adapter)
+{
+	u8	value8 = 0;
+	u16  value16;
+	u8	txpktbuf_bndy;
+	u32	status = _SUCCESS;
+	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(Adapter);
+	struct pwrctrl_priv		*pwrctrlpriv = &Adapter->pwrctrlpriv;
+	struct registry_priv	*pregistrypriv = &Adapter->registrypriv;
+	
+	rt_rf_power_state		eRfPowerStateToSet;
+#ifdef CONFIG_BT_COEXIST
+	struct btcoexist_priv	*pbtpriv = &(pHalData->bt_coexist);
+#endif
+
+	u32 init_start_time = rtw_get_current_time();
+
+
+#ifdef DBG_HAL_INIT_PROFILING
+
+	enum HAL_INIT_STAGES {
+		HAL_INIT_STAGES_BEGIN = 0,
+		HAL_INIT_STAGES_INIT_PW_ON,
+		HAL_INIT_STAGES_MISC01,
+		HAL_INIT_STAGES_DOWNLOAD_FW,
+		HAL_INIT_STAGES_MAC,
+		HAL_INIT_STAGES_BB,
+		HAL_INIT_STAGES_RF,	
+		HAL_INIT_STAGES_EFUSE_PATCH,
+		HAL_INIT_STAGES_INIT_LLTT,	
+		
+		HAL_INIT_STAGES_MISC02,
+		HAL_INIT_STAGES_TURN_ON_BLOCK,
+		HAL_INIT_STAGES_INIT_SECURITY,
+		HAL_INIT_STAGES_MISC11,
+		HAL_INIT_STAGES_INIT_HAL_DM,
+		//HAL_INIT_STAGES_RF_PS,
+		HAL_INIT_STAGES_IQK,
+		HAL_INIT_STAGES_PW_TRACK,
+		HAL_INIT_STAGES_LCK,
+		//HAL_INIT_STAGES_MISC21,
+		//HAL_INIT_STAGES_INIT_PABIAS,
+		#ifdef CONFIG_BT_COEXIST
+		HAL_INIT_STAGES_BT_COEXIST,
+		#endif
+		//HAL_INIT_STAGES_ANTENNA_SEL,
+		//HAL_INIT_STAGES_MISC31,
+		HAL_INIT_STAGES_END,
+		HAL_INIT_STAGES_NUM
+	};
+
+	char * hal_init_stages_str[] = {
+		"HAL_INIT_STAGES_BEGIN",
+		"HAL_INIT_STAGES_INIT_PW_ON",
+		"HAL_INIT_STAGES_MISC01",
+		"HAL_INIT_STAGES_DOWNLOAD_FW",		
+		"HAL_INIT_STAGES_MAC",		
+		"HAL_INIT_STAGES_BB",
+		"HAL_INIT_STAGES_RF",
+		"HAL_INIT_STAGES_EFUSE_PATCH",
+		"HAL_INIT_STAGES_INIT_LLTT",
+		"HAL_INIT_STAGES_MISC02",		
+		"HAL_INIT_STAGES_TURN_ON_BLOCK",
+		"HAL_INIT_STAGES_INIT_SECURITY",
+		"HAL_INIT_STAGES_MISC11",
+		"HAL_INIT_STAGES_INIT_HAL_DM",
+		//"HAL_INIT_STAGES_RF_PS",
+		"HAL_INIT_STAGES_IQK",
+		"HAL_INIT_STAGES_PW_TRACK",
+		"HAL_INIT_STAGES_LCK",
+		//"HAL_INIT_STAGES_MISC21",
+		#ifdef CONFIG_BT_COEXIST
+		"HAL_INIT_STAGES_BT_COEXIST",
+		#endif
+		//"HAL_INIT_STAGES_ANTENNA_SEL",
+		//"HAL_INIT_STAGES_MISC31",
+		"HAL_INIT_STAGES_END",
+	};
+
+	int hal_init_profiling_i;
+	u32 hal_init_stages_timestamp[HAL_INIT_STAGES_NUM]; //used to record the time of each stage's starting point
+
+	for(hal_init_profiling_i=0;hal_init_profiling_i<HAL_INIT_STAGES_NUM;hal_init_profiling_i++)
+		hal_init_stages_timestamp[hal_init_profiling_i]=0;
+
+	#define HAL_INIT_PROFILE_TAG(stage) hal_init_stages_timestamp[(stage)]=rtw_get_current_time();
+#else
+	#define HAL_INIT_PROFILE_TAG(stage) do {} while(0)
+#endif //DBG_HAL_INIT_PROFILING
+
+
+
+_func_enter_;
+	
+HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BEGIN);
+
+#ifdef CONFIG_WOWLAN
+	
+	Adapter->pwrctrlpriv.wowlan_wake_reason = rtw_read8(Adapter, REG_WOWLAN_WAKE_REASON);
+	DBG_8192C("%s wowlan_wake_reason: 0x%02x\n", 
+				__func__, Adapter->pwrctrlpriv.wowlan_wake_reason);
+
+	if(rtw_read8(Adapter, REG_MCUFWDL)&BIT7){ /*&&
+		(Adapter->pwrctrlpriv.wowlan_wake_reason & FWDecisionDisconnect)) {*/
+		u8 reg_val=0;
+		DBG_8192C("+Reset Entry+\n");
+		rtw_write8(Adapter, REG_MCUFWDL, 0x00);
+		_8051Reset88E(Adapter);
+		//reset BB
+		reg_val = rtw_read8(Adapter, REG_SYS_FUNC_EN);
+		reg_val &= ~(BIT(0) | BIT(1));
+		rtw_write8(Adapter, REG_SYS_FUNC_EN, reg_val);
+		//reset RF
+		rtw_write8(Adapter, REG_RF_CTRL, 0);
+		//reset TRX path
+		rtw_write16(Adapter, REG_CR, 0);
+		//reset MAC, Digital Core
+		reg_val = rtw_read8(Adapter, REG_SYS_FUNC_EN+1);
+		reg_val &= ~(BIT(4) | BIT(7));
+		rtw_write8(Adapter, REG_SYS_FUNC_EN+1, reg_val);
+		reg_val = rtw_read8(Adapter, REG_SYS_FUNC_EN+1);
+		reg_val |= BIT(4) | BIT(7);
+		rtw_write8(Adapter, REG_SYS_FUNC_EN+1, reg_val);
+		DBG_8192C("-Reset Entry-\n");
+	}
+#endif //CONFIG_WOWLAN
+
+	if(Adapter->pwrctrlpriv.bkeepfwalive)
+	{
+		_ps_open_RF(Adapter);
+
+		if(pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized){
+//			PHY_IQCalibrate(padapter, _TRUE);
+			PHY_IQCalibrate_8188E(Adapter,_TRUE);
+		}
+		else
+		{
+//			PHY_IQCalibrate(padapter, _FALSE);
+			PHY_IQCalibrate_8188E(Adapter,_FALSE);
+			pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized = _TRUE;
+		}
+
+//		dm_CheckTXPowerTracking(padapter);
+//		PHY_LCCalibrate(padapter);
+		ODM_TXPowerTrackingCheck(&pHalData->odmpriv );
+		PHY_LCCalibrate_8188E(Adapter);
+
+		goto exit;
+	}
+	
+
+HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PW_ON);
+	status = rtl8188eu_InitPowerOn(Adapter);
+	if(status == _FAIL){
+		RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init power on!\n"));
+		goto exit;
+	}
+
+	// Save target channel
+	pHalData->CurrentChannel = 6;//default set to 6
+
+
+	if(pwrctrlpriv->reg_rfoff == _TRUE){
+		pwrctrlpriv->rf_pwrstate = rf_off;
+	}
+
+	// 2010/08/09 MH We need to check if we need to turnon or off RF after detecting
+	// HW GPIO pin. Before PHY_RFConfig8192C.
+	//HalDetectPwrDownMode(Adapter);
+	// 2010/08/26 MH If Efuse does not support sective suspend then disable the function.
+	//HalDetectSelectiveSuspendMode(Adapter);
+
+	if (!pregistrypriv->wifi_spec) {
+		txpktbuf_bndy = TX_PAGE_BOUNDARY_88E;
+	} else {
+		// for WMM
+		txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY_88E;
+	}
+	
+HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC01);
+	_InitQueueReservedPage(Adapter);		
+	_InitQueuePriority(Adapter);
+	_InitPageBoundary(Adapter);	
+	_InitTransferPageSize(Adapter);
+	
+#ifdef CONFIG_IOL_IOREG_CFG
+	_InitTxBufferBoundary(Adapter, 0);		
+#endif
+
+
+
+HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_DOWNLOAD_FW);
+#if (MP_DRIVER == 1)
+	if (Adapter->registrypriv.mp_mode == 1)
+	{
+		_InitRxSetting(Adapter);
+	}
+#endif  //MP_DRIVER == 1
+	{
+	#if 0		
+		Adapter->bFWReady = _FALSE; //because no fw for test chip	
+		pHalData->fw_ractrl = _FALSE;
+	#else
+
+#ifdef CONFIG_WOWLAN
+	status = rtl8188e_FirmwareDownload(Adapter, _FALSE);
+#else
+		status = rtl8188e_FirmwareDownload(Adapter);
+#endif //CONFIG_WOWLAN
+
+		if (status != _SUCCESS) {
+			DBG_871X("%s: Download Firmware failed!!\n", __FUNCTION__);
+			Adapter->bFWReady = _FALSE;
+			pHalData->fw_ractrl = _FALSE;
+			return status;
+		} else {
+			RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Initializepadapter8192CSdio(): Download Firmware Success!!\n"));
+			Adapter->bFWReady = _TRUE;
+			pHalData->fw_ractrl = _FALSE;
+		}
+	#endif
+	}
+
+
+	rtl8188e_InitializeFirmwareVars(Adapter);
+
+
+HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MAC);
+#if (HAL_MAC_ENABLE == 1)
+	status = PHY_MACConfig8188E(Adapter);
+	if(status == _FAIL)
+	{
+		DBG_871X(" ### Failed to init MAC ...... \n ");				
+		goto exit;
+	}
+#endif	
+
+	//
+	//d. Initialize BB related configurations.
+	//
+HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BB);
+#if (HAL_BB_ENABLE == 1)
+	status = PHY_BBConfig8188E(Adapter);
+	if(status == _FAIL)
+	{
+		DBG_871X(" ### Failed to init BB ...... \n ");
+		goto exit;
+	}
+#endif
+
+
+HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_RF);
+#if (HAL_RF_ENABLE == 1)
+	status = PHY_RFConfig8188E(Adapter);	
+	if(status == _FAIL)
+	{
+		DBG_871X(" ### Failed to init RF ...... \n ");
+		goto exit;
+	}
+#endif
+
+HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_EFUSE_PATCH);
+#if defined(CONFIG_IOL_EFUSE_PATCH)		
+	status = rtl8188e_iol_efuse_patch(Adapter);
+	if(status == _FAIL){	
+		DBG_871X("%s  rtl8188e_iol_efuse_patch failed \n",__FUNCTION__);
+		goto exit;
+	}	
+#endif
+
+	_InitTxBufferBoundary(Adapter, txpktbuf_bndy);	
+
+HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_LLTT);
+	status =  InitLLTTable(Adapter, txpktbuf_bndy);
+	if(status == _FAIL){
+		RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init LLT table\n"));
+		goto exit;
+	}
+	
+HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC02);
+	// Get Rx PHY status in order to report RSSI and others.
+	_InitDriverInfoSize(Adapter, DRVINFO_SZ);
+
+	_InitInterrupt(Adapter);
+	hal_init_macaddr(Adapter);//set mac_address
+	_InitNetworkType(Adapter);//set msr	
+	_InitWMACSetting(Adapter);
+	_InitAdaptiveCtrl(Adapter);
+	_InitEDCA(Adapter);
+	//_InitRateFallback(Adapter);//just follow MP Team ???Georgia
+	_InitRetryFunction(Adapter);
+	InitUsbAggregationSetting(Adapter);
+	_InitOperationMode(Adapter);//todo
+	_InitBeaconParameters(Adapter);
+	_InitBeaconMaxError(Adapter, _TRUE);
+
+	//
+	// Init CR MACTXEN, MACRXEN after setting RxFF boundary REG_TRXFF_BNDY to patch
+	// Hw bug which Hw initials RxFF boundry size to a value which is larger than the real Rx buffer size in 88E. 
+	//
+	// Enable MACTXEN/MACRXEN block
+	value16 = rtw_read16(Adapter, REG_CR);
+	value16 |= (MACTXEN | MACRXEN);
+	rtw_write8(Adapter, REG_CR, value16);		
+
+#if ENABLE_USB_DROP_INCORRECT_OUT
+	_InitHardwareDropIncorrectBulkOut(Adapter);
+#endif
+
+	if(pHalData->bRDGEnable){
+		_InitRDGSetting(Adapter);
+	}
+
+#if (RATE_ADAPTIVE_SUPPORT==1)
+	{//Enable TX Report
+		//Enable Tx Report Timer   
+		value8 = rtw_read8(Adapter, REG_TX_RPT_CTRL);
+		rtw_write8(Adapter,  REG_TX_RPT_CTRL, (value8|BIT1|BIT0));
+		//Set MAX RPT MACID
+		rtw_write8(Adapter,  REG_TX_RPT_CTRL+1, 2);//FOR sta mode ,0: bc/mc ,1:AP
+		//Tx RPT Timer. Unit: 32us
+		rtw_write16(Adapter, REG_TX_RPT_TIME, 0xCdf0);
+	}
+#endif	
+
+#if 0
+	if(pHTInfo->bRDGEnable){
+		_InitRDGSetting_8188E(Adapter);
+	}
+#endif
+
+#ifdef CONFIG_TX_EARLY_MODE	
+	if( pHalData->bEarlyModeEnable)
+	{
+		RT_TRACE(_module_hci_hal_init_c_, _drv_info_,("EarlyMode Enabled!!!\n"));
+
+		value8 = rtw_read8(Adapter, REG_EARLY_MODE_CONTROL);
+#if RTL8188E_EARLY_MODE_PKT_NUM_10 == 1
+		value8 = value8|0x1f;
+#else
+		value8 = value8|0xf;
+#endif
+		rtw_write8(Adapter, REG_EARLY_MODE_CONTROL, value8);
+
+		rtw_write8(Adapter, REG_EARLY_MODE_CONTROL+3, 0x80);
+
+		value8 = rtw_read8(Adapter, REG_TCR+1);
+		value8 = value8|0x40;
+		rtw_write8(Adapter,REG_TCR+1, value8);
+	}
+	else
+#endif
+	{
+		rtw_write8(Adapter, REG_EARLY_MODE_CONTROL, 0);
+	}
+	
+#if defined(CONFIG_CONCURRENT_MODE) || defined(CONFIG_TX_MCAST2UNI)
+
+#ifdef CONFIG_CHECK_AC_LIFETIME
+	// Enable lifetime check for the four ACs
+	rtw_write8(Adapter, REG_LIFETIME_EN, 0x0F);
+#endif	// CONFIG_CHECK_AC_LIFETIME
+
+#ifdef CONFIG_TX_MCAST2UNI
+	rtw_write16(Adapter, REG_PKT_VO_VI_LIFE_TIME, 0x0400);	// unit: 256us. 256ms
+	rtw_write16(Adapter, REG_PKT_BE_BK_LIFE_TIME, 0x0400);	// unit: 256us. 256ms
+#else	// CONFIG_TX_MCAST2UNI
+	rtw_write16(Adapter, REG_PKT_VO_VI_LIFE_TIME, 0x3000);	// unit: 256us. 3s
+	rtw_write16(Adapter, REG_PKT_BE_BK_LIFE_TIME, 0x3000);	// unit: 256us. 3s
+#endif	// CONFIG_TX_MCAST2UNI
+#endif	// CONFIG_CONCURRENT_MODE || CONFIG_TX_MCAST2UNI
+	
+
+#ifdef CONFIG_LED
+	_InitHWLed(Adapter);
+#endif //CONFIG_LED
+
+	
+	//
+	// Joseph Note: Keep RfRegChnlVal for later use.
+	//
+	pHalData->RfRegChnlVal[0] = PHY_QueryRFReg(Adapter, (RF_RADIO_PATH_E)0, RF_CHNLBW, bRFRegOffsetMask);
+	pHalData->RfRegChnlVal[1] = PHY_QueryRFReg(Adapter, (RF_RADIO_PATH_E)1, RF_CHNLBW, bRFRegOffsetMask);
+
+HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_TURN_ON_BLOCK);
+	_BBTurnOnBlock(Adapter);
+	//NicIFSetMacAddress(padapter, padapter->PermanentAddress);
+
+HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_SECURITY);
+	invalidate_cam_all(Adapter);
+
+HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC11);
+	// 2010/12/17 MH We need to set TX power according to EFUSE content at first.
+	PHY_SetTxPowerLevel8188E(Adapter, pHalData->CurrentChannel);
+
+// Move by Neo for USB SS to below setp	
+//_RfPowerSave(Adapter);
+
+	_InitAntenna_Selection(Adapter);
+	
+	// 
+	// Disable BAR, suggested by Scott
+	// 2010.04.09 add by hpfan
+	//
+	rtw_write32(Adapter, REG_BAR_MODE_CTRL, 0x0201ffff);
+
+	// HW SEQ CTRL
+	//set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM.
+	rtw_write8(Adapter,REG_HWSEQ_CTRL, 0xFF); 
+
+	if(pregistrypriv->wifi_spec)
+		rtw_write16(Adapter,REG_FAST_EDCA_CTRL ,0);
+
+	//Nav limit , suggest by scott
+	rtw_write8(Adapter, 0x652, 0x0);
+
+HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_HAL_DM);
+	rtl8188e_InitHalDm(Adapter);
+	
+#if (MP_DRIVER == 1)
+	if (Adapter->registrypriv.mp_mode == 1)
+	{
+		Adapter->mppriv.channel = pHalData->CurrentChannel;
+		MPT_InitializeAdapter(Adapter, Adapter->mppriv.channel);
+	}
+	else	
+#endif  //#if (MP_DRIVER == 1)
+	{
+	//
+	// 2010/08/11 MH Merge from 8192SE for Minicard init. We need to confirm current radio status
+	// and then decide to enable RF or not.!!!??? For Selective suspend mode. We may not 
+	// call init_adapter. May cause some problem??
+	//
+	// Fix the bug that Hw/Sw radio off before S3/S4, the RF off action will not be executed 
+	// in MgntActSet_RF_State() after wake up, because the value of pHalData->eRFPowerState 
+	// is the same as eRfOff, we should change it to eRfOn after we config RF parameters.
+	// Added by tynli. 2010.03.30.
+	pwrctrlpriv->rf_pwrstate = rf_on;
+
+#if 0  //to do
+	RT_CLEAR_PS_LEVEL(pwrctrlpriv, RT_RF_OFF_LEVL_HALT_NIC);
+#if 1 //Todo
+	// 20100326 Joseph: Copy from GPIOChangeRFWorkItemCallBack() function to check HW radio on/off.
+	// 20100329 Joseph: Revise and integrate the HW/SW radio off code in initialization.
+
+	eRfPowerStateToSet = (rt_rf_power_state) RfOnOffDetect(Adapter);
+	pwrctrlpriv->rfoff_reason |= eRfPowerStateToSet==rf_on ? RF_CHANGE_BY_INIT : RF_CHANGE_BY_HW;
+	pwrctrlpriv->rfoff_reason |= (pwrctrlpriv->reg_rfoff) ? RF_CHANGE_BY_SW : 0;
+
+	if(pwrctrlpriv->rfoff_reason&RF_CHANGE_BY_HW)
+		pwrctrlpriv->b_hw_radio_off = _TRUE;
+
+	DBG_8192C("eRfPowerStateToSet=%d\n", eRfPowerStateToSet);
+	
+	if(pwrctrlpriv->reg_rfoff == _TRUE)
+	{	// User disable RF via registry.
+		DBG_8192C("InitializeAdapter8192CU(): Turn off RF for RegRfOff.\n");
+		//MgntActSet_RF_State(Adapter, rf_off, RF_CHANGE_BY_SW, _TRUE);
+		
+		// Those action will be discard in MgntActSet_RF_State because off the same state
+		//for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
+			//PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x0);
+	}
+	else if(pwrctrlpriv->rfoff_reason > RF_CHANGE_BY_PS)
+	{	// H/W or S/W RF OFF before sleep.
+		DBG_8192C(" Turn off RF for RfOffReason(%x) ----------\n", pwrctrlpriv->rfoff_reason);
+		//pwrctrlpriv->rfoff_reason = RF_CHANGE_BY_INIT;
+		pwrctrlpriv->rf_pwrstate = rf_on;
+		//MgntActSet_RF_State(Adapter, rf_off, pwrctrlpriv->rfoff_reason, _TRUE);
+	}
+	else
+	{
+		// Perform GPIO polling to find out current RF state. added by Roger, 2010.04.09.
+		if(pHalData->BoardType == BOARD_MINICARD /*&& (Adapter->MgntInfo.PowerSaveControl.bGpioRfSw)*/)
+		{
+			DBG_8192C("InitializeAdapter8192CU(): RF=%d \n", eRfPowerStateToSet);
+			if (eRfPowerStateToSet == rf_off)
+			{				
+				//MgntActSet_RF_State(Adapter, rf_off, RF_CHANGE_BY_HW, _TRUE);
+				pwrctrlpriv->b_hw_radio_off = _TRUE;	
+			}
+			else
+			{
+				pwrctrlpriv->rf_pwrstate = rf_off;
+				pwrctrlpriv->rfoff_reason = RF_CHANGE_BY_INIT; 
+				pwrctrlpriv->b_hw_radio_off = _FALSE;					
+				//MgntActSet_RF_State(Adapter, rf_on, pwrctrlpriv->rfoff_reason, _TRUE);
+			}
+		}	
+		else
+		{
+			pwrctrlpriv->rf_pwrstate = rf_off;
+			pwrctrlpriv->rfoff_reason = RF_CHANGE_BY_INIT; 			
+			//MgntActSet_RF_State(Adapter, rf_on, pwrctrlpriv->rfoff_reason, _TRUE);
+		}
+	
+		pwrctrlpriv->rfoff_reason = 0; 
+		pwrctrlpriv->b_hw_radio_off = _FALSE;
+		pwrctrlpriv->rf_pwrstate = rf_on;
+		rtw_led_control(Adapter, LED_CTL_POWER_ON);
+
+	}
+
+	// 2010/-8/09 MH For power down module, we need to enable register block contrl reg at 0x1c.
+	// Then enable power down control bit of register 0x04 BIT4 and BIT15 as 1.
+	if(pHalData->pwrdown && eRfPowerStateToSet == rf_off)
+	{
+		// Enable register area 0x0-0xc.
+		rtw_write8(Adapter, REG_RSV_CTRL, 0x0);
+
+		//
+		// <Roger_Notes> We should configure HW PDn source for WiFi ONLY, and then
+		// our HW will be set in power-down mode if PDn source from all  functions are configured.
+		// 2010.10.06.
+		//
+		//if(IS_HARDWARE_TYPE_8723AU(Adapter))
+		//{			
+		//	u1bTmp = rtw_read8(Adapter, REG_MULTI_FUNC_CTRL);
+		//	rtw_write8(Adapter, REG_MULTI_FUNC_CTRL, (u1bTmp|WL_HWPDN_EN));
+		//}
+		//else
+		//{
+			rtw_write16(Adapter, REG_APS_FSMCO, 0x8812);
+		//}
+	}
+	//DrvIFIndicateCurrentPhyStatus(Adapter); // 2010/08/17 MH Disable to prevent BSOD.
+#endif
+#endif
+
+
+	// enable Tx report.
+	rtw_write8(Adapter,  REG_FWHW_TXQ_CTRL+1, 0x0F);
+
+	// Suggested by SD1 pisa. Added by tynli. 2011.10.21.
+	rtw_write8(Adapter, REG_EARLY_MODE_CONTROL+3, 0x01);//Pretx_en, for WEP/TKIP SEC
+
+	//tynli_test_tx_report.
+	rtw_write16(Adapter, REG_TX_RPT_TIME, 0x3DF0);
+	//RT_TRACE(COMP_INIT, DBG_TRACE, ("InitializeAdapter8188EUsb() <====\n"));
+
+	//enable tx DMA to drop the redundate data of packet
+	rtw_write16(Adapter,REG_TXDMA_OFFSET_CHK, (rtw_read16(Adapter,REG_TXDMA_OFFSET_CHK) | DROP_DATA_EN));
+	
+HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_IQK);
+	// 2010/08/26 MH Merge from 8192CE.
+	if(pwrctrlpriv->rf_pwrstate == rf_on)
+	{
+		if(pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized){
+			PHY_IQCalibrate_8188E(Adapter,_TRUE);
+		}
+		else
+		{
+			PHY_IQCalibrate_8188E(Adapter,_FALSE);
+			pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized = _TRUE;
+		}
+		
+HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_PW_TRACK);
+		
+		ODM_TXPowerTrackingCheck(&pHalData->odmpriv );
+		
+
+HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_LCK);
+		PHY_LCCalibrate_8188E(Adapter);
+	}
+}
+
+//HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PABIAS);
+//	_InitPABias(Adapter);
+	rtw_write8(Adapter, REG_USB_HRPWM, 0);
+
+#ifdef CONFIG_XMIT_ACK
+	//ack for xmit mgmt frames.
+	rtw_write32(Adapter, REG_FWHW_TXQ_CTRL, rtw_read32(Adapter, REG_FWHW_TXQ_CTRL)|BIT(12));
+#endif //CONFIG_XMIT_ACK
+
+exit:
+HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_END);
+
+	DBG_871X("%s in %dms\n", __FUNCTION__, rtw_get_passing_time_ms(init_start_time));
+
+	#ifdef DBG_HAL_INIT_PROFILING
+	hal_init_stages_timestamp[HAL_INIT_STAGES_END]=rtw_get_current_time();
+
+	for(hal_init_profiling_i=0;hal_init_profiling_i<HAL_INIT_STAGES_NUM-1;hal_init_profiling_i++) {
+		DBG_871X("DBG_HAL_INIT_PROFILING: %35s, %u, %5u, %5u\n"
+			, hal_init_stages_str[hal_init_profiling_i]
+			, hal_init_stages_timestamp[hal_init_profiling_i]
+			, (hal_init_stages_timestamp[hal_init_profiling_i+1]-hal_init_stages_timestamp[hal_init_profiling_i])
+			, rtw_get_time_interval_ms(hal_init_stages_timestamp[hal_init_profiling_i], hal_init_stages_timestamp[hal_init_profiling_i+1])
+		);
+	}	
+	#endif
+
+
+_func_exit_;
+
+	return status;
+}
+
+void _ps_open_RF(_adapter *padapter) {
+	//here call with bRegSSPwrLvl 1, bRegSSPwrLvl 2 needs to be verified
+	//phy_SsPwrSwitch92CU(padapter, rf_on, 1);
+}
+
+void _ps_close_RF(_adapter *padapter){
+	//here call with bRegSSPwrLvl 1, bRegSSPwrLvl 2 needs to be verified
+	//phy_SsPwrSwitch92CU(padapter, rf_off, 1);
+}
+
+
+VOID
+CardDisableRTL8188EU(
+	IN	PADAPTER			Adapter 
+)
+{
+//	PMGNT_INFO	pMgntInfo	= &(Adapter->MgntInfo);
+	u8 	val8;
+	u16	val16;
+	u32	val32;
+	HAL_DATA_TYPE	*pHalData	= GET_HAL_DATA(Adapter);
+
+	RT_TRACE(COMP_INIT, DBG_LOUD, ("CardDisableRTL8188EU\n"));
+
+	//Stop Tx Report Timer. 0x4EC[Bit1]=b'0
+	val8 = rtw_read8(Adapter, REG_TX_RPT_CTRL);
+	rtw_write8(Adapter, REG_TX_RPT_CTRL, val8&(~BIT1));
+
+	// stop rx 
+	rtw_write8(Adapter, REG_CR, 0x0);
+	
+	// Run LPS WL RFOFF flow
+	HalPwrSeqCmdParsing(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, Rtl8188E_NIC_LPS_ENTER_FLOW);
+
+	
+	// 2. 0x1F[7:0] = 0		// turn off RF
+	//rtw_write8(Adapter, REG_RF_CTRL, 0x00);
+
+	val8 = rtw_read8(Adapter, REG_MCUFWDL);
+	if ((val8 & RAM_DL_SEL) && Adapter->bFWReady) //8051 RAM code
+	{
+		//rtl8723a_FirmwareSelfReset(padapter);
+		//_8051Reset88E(padapter);		
+		
+		// Reset MCU 0x2[10]=0.
+		val8 = rtw_read8(Adapter, REG_SYS_FUNC_EN+1);
+		val8 &= ~BIT(2);	// 0x2[10], FEN_CPUEN
+		rtw_write8(Adapter, REG_SYS_FUNC_EN+1, val8);
+	}	
+
+	//val8 = rtw_read8(Adapter, REG_SYS_FUNC_EN+1);
+	//val8 &= ~BIT(2);	// 0x2[10], FEN_CPUEN
+	//rtw_write8(Adapter, REG_SYS_FUNC_EN+1, val8);
+
+	// MCUFWDL 0x80[1:0]=0
+	// reset MCU ready status
+	rtw_write8(Adapter, REG_MCUFWDL, 0);
+
+	//YJ,add,111212
+	//Disable 32k
+	val8 = rtw_read8(Adapter, REG_32K_CTRL);
+	rtw_write8(Adapter, REG_32K_CTRL, val8&(~BIT0));
+	
+	// Card disable power action flow
+	HalPwrSeqCmdParsing(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, Rtl8188E_NIC_DISABLE_FLOW);	
+	
+	// Reset MCU IO Wrapper
+	val8 = rtw_read8(Adapter, REG_RSV_CTRL+1);
+	rtw_write8(Adapter, REG_RSV_CTRL+1, (val8&(~BIT3)));	
+	val8 = rtw_read8(Adapter, REG_RSV_CTRL+1);
+	rtw_write8(Adapter, REG_RSV_CTRL+1, val8|BIT3);
+	
+#if 0
+	// 7. RSV_CTRL 0x1C[7:0] = 0x0E			// lock ISO/CLK/Power control register
+	rtw_write8(Adapter, REG_RSV_CTRL, 0x0e);
+#endif
+#if 1
+	//YJ,test add, 111207. For Power Consumption.
+	val8 = rtw_read8(Adapter, GPIO_IN);
+	rtw_write8(Adapter, GPIO_OUT, val8);
+	rtw_write8(Adapter, GPIO_IO_SEL, 0xFF);//Reg0x46
+
+	val8 = rtw_read8(Adapter, REG_GPIO_IO_SEL);
+	//rtw_write8(Adapter, REG_GPIO_IO_SEL, (val8<<4)|val8);
+	rtw_write8(Adapter, REG_GPIO_IO_SEL, (val8<<4));
+	val8 = rtw_read8(Adapter, REG_GPIO_IO_SEL+1);
+	rtw_write8(Adapter, REG_GPIO_IO_SEL+1, val8|0x0F);//Reg0x43
+	rtw_write32(Adapter, REG_BB_PAD_CTRL, 0x00080808);//set LNA ,TRSW,EX_PA Pin to output mode
+#endif
+	pHalData->bMacPwrCtrlOn = _FALSE;
+	Adapter->bFWReady = _FALSE;
+}
+static void rtl8192cu_hw_power_down(_adapter *padapter)
+{
+	// 2010/-8/09 MH For power down module, we need to enable register block contrl reg at 0x1c.
+	// Then enable power down control bit of register 0x04 BIT4 and BIT15 as 1.
+		
+	// Enable register area 0x0-0xc.
+	rtw_write8(padapter,REG_RSV_CTRL, 0x0);			
+	rtw_write16(padapter, REG_APS_FSMCO, 0x8812);
+}
+
+u32 rtl8188eu_hal_deinit(PADAPTER Adapter)
+ {
+
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
+   	DBG_8192C("==> %s \n",__FUNCTION__);
+
+#ifdef CONFIG_SUPPORT_USB_INT
+	rtw_write32(Adapter, REG_HIMR_88E, IMR_DISABLED_88E);
+	rtw_write32(Adapter, REG_HIMRE_88E, IMR_DISABLED_88E);
+#endif
+	
+ #ifdef SUPPORT_HW_RFOFF_DETECTED
+ 	DBG_8192C("bkeepfwalive(%x)\n",Adapter->pwrctrlpriv.bkeepfwalive);
+ 	if(Adapter->pwrctrlpriv.bkeepfwalive)
+ 	{
+		_ps_close_RF(Adapter);		
+		if((Adapter->pwrctrlpriv.bHWPwrPindetect) && (Adapter->pwrctrlpriv.bHWPowerdown))		
+			rtl8192cu_hw_power_down(Adapter);
+ 	}
+	else
+#endif
+	{
+		if(Adapter->hw_init_completed == _TRUE){
+			CardDisableRTL8188EU(Adapter);
+
+			if((Adapter->pwrctrlpriv.bHWPwrPindetect ) && (Adapter->pwrctrlpriv.bHWPowerdown))		
+				rtl8192cu_hw_power_down(Adapter);
+			
+		}
+	}	
+	return _SUCCESS;
+ }
+
+
+unsigned int rtl8188eu_inirp_init(PADAPTER Adapter)
+{	
+	u8 i;	
+	struct recv_buf *precvbuf;
+	uint	status;
+	struct dvobj_priv *pdev= adapter_to_dvobj(Adapter);
+	struct intf_hdl * pintfhdl=&Adapter->iopriv.intf;
+	struct recv_priv *precvpriv = &(Adapter->recvpriv);	
+	u32 (*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
+#ifdef CONFIG_USB_INTERRUPT_IN_PIPE
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+	u32 (*_read_interrupt)(struct intf_hdl *pintfhdl, u32 addr);
+#endif
+
+_func_enter_;
+
+	_read_port = pintfhdl->io_ops._read_port;
+
+	status = _SUCCESS;
+
+	RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("===> usb_inirp_init \n"));	
+		
+	precvpriv->ff_hwaddr = RECV_BULK_IN_ADDR;
+
+	//issue Rx irp to receive data	
+	precvbuf = (struct recv_buf *)precvpriv->precv_buf;	
+	for(i=0; i<NR_RECVBUFF; i++)
+	{
+		if(_read_port(pintfhdl, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf) == _FALSE )
+		{
+			RT_TRACE(_module_hci_hal_init_c_,_drv_err_,("usb_rx_init: usb_read_port error \n"));
+			status = _FAIL;
+			goto exit;
+		}
+		
+		precvbuf++;		
+		precvpriv->free_recv_buf_queue_cnt--;
+	}
+
+#ifdef CONFIG_USB_INTERRUPT_IN_PIPE
+	if(pHalData->RtIntInPipe != 0x05)
+	{
+		status = _FAIL;
+		DBG_871X("%s =>Warning !! Have not USB Int-IN pipe,  pHalData->RtIntInPipe(%d)!!!\n",__FUNCTION__,pHalData->RtIntInPipe);
+		goto exit;
+	}	
+	_read_interrupt = pintfhdl->io_ops._read_interrupt;
+	if(_read_interrupt(pintfhdl, RECV_INT_IN_ADDR) == _FALSE )
+	{
+		RT_TRACE(_module_hci_hal_init_c_,_drv_err_,("usb_rx_init: usb_read_interrupt error \n"));
+		status = _FAIL;
+	}
+#endif
+
+exit:
+	
+	RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("<=== usb_inirp_init \n"));
+
+_func_exit_;
+
+	return status;
+
+}
+
+unsigned int rtl8188eu_inirp_deinit(PADAPTER Adapter)
+{	
+	RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("\n ===> usb_rx_deinit \n"));
+	
+	rtw_read_port_cancel(Adapter);
+
+	RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("\n <=== usb_rx_deinit \n"));
+
+	return _SUCCESS;
+}
+
+
+
+//-------------------------------------------------------------------------
+//
+//	EEPROM Power index mapping
+//
+//-------------------------------------------------------------------------
+#if 0
+ static VOID
+_ReadPowerValueFromPROM(
+	IN	PTxPowerInfo	pwrInfo,
+	IN	u8*			PROMContent,
+	IN	BOOLEAN			AutoLoadFail
+	)
+{
+	u32 rfPath, eeAddr, group;
+
+	_rtw_memset(pwrInfo, 0, sizeof(TxPowerInfo));
+
+	if(AutoLoadFail){		
+		for(group = 0 ; group < CHANNEL_GROUP_MAX ; group++){
+			for(rfPath = 0 ; rfPath < RF_PATH_MAX ; rfPath++){
+				pwrInfo->CCKIndex[rfPath][group]		= EEPROM_Default_TxPowerLevel;	
+				pwrInfo->HT40_1SIndex[rfPath][group]	= EEPROM_Default_TxPowerLevel;
+				pwrInfo->HT40_2SIndexDiff[rfPath][group]= EEPROM_Default_HT40_2SDiff;
+				pwrInfo->HT20IndexDiff[rfPath][group]	= EEPROM_Default_HT20_Diff;
+				pwrInfo->OFDMIndexDiff[rfPath][group]	= EEPROM_Default_LegacyHTTxPowerDiff;
+				pwrInfo->HT40MaxOffset[rfPath][group]	= EEPROM_Default_HT40_PwrMaxOffset;		
+				pwrInfo->HT20MaxOffset[rfPath][group]	= EEPROM_Default_HT20_PwrMaxOffset;
+			}
+		}
+
+		pwrInfo->TSSI_A = EEPROM_Default_TSSI;
+		pwrInfo->TSSI_B = EEPROM_Default_TSSI;
+		
+		return;
+	}
+	
+	for(rfPath = 0 ; rfPath < RF_PATH_MAX ; rfPath++){
+		for(group = 0 ; group < CHANNEL_GROUP_MAX ; group++){
+			eeAddr = EEPROM_CCK_TX_PWR_INX + (rfPath * 3) + group;
+			pwrInfo->CCKIndex[rfPath][group] = PROMContent[eeAddr];
+
+			eeAddr = EEPROM_HT40_1S_TX_PWR_INX + (rfPath * 3) + group;
+			pwrInfo->HT40_1SIndex[rfPath][group] = PROMContent[eeAddr];
+		}
+	}
+
+	for(group = 0 ; group < CHANNEL_GROUP_MAX ; group++){
+		for(rfPath = 0 ; rfPath < RF_PATH_MAX ; rfPath++){
+			pwrInfo->HT40_2SIndexDiff[rfPath][group] = 
+			(PROMContent[EEPROM_HT40_2S_TX_PWR_INX_DIFF + group] >> (rfPath * 4)) & 0xF;
+
+#if 1
+			pwrInfo->HT20IndexDiff[rfPath][group] =
+			(PROMContent[EEPROM_HT20_TX_PWR_INX_DIFF + group] >> (rfPath * 4)) & 0xF;
+			if(pwrInfo->HT20IndexDiff[rfPath][group] & BIT3)	//4bit sign number to 8 bit sign number
+				pwrInfo->HT20IndexDiff[rfPath][group] |= 0xF0;
+#else
+			pwrInfo->HT20IndexDiff[rfPath][group] =
+			(PROMContent[EEPROM_HT20_TX_PWR_INX_DIFF + group] >> (rfPath * 4)) & 0xF;
+#endif
+
+			pwrInfo->OFDMIndexDiff[rfPath][group] =
+			(PROMContent[EEPROM_OFDM_TX_PWR_INX_DIFF+ group] >> (rfPath * 4)) & 0xF;
+
+			pwrInfo->HT40MaxOffset[rfPath][group] =
+			(PROMContent[EEPROM_HT40_MAX_PWR_OFFSET+ group] >> (rfPath * 4)) & 0xF;
+
+			pwrInfo->HT20MaxOffset[rfPath][group] =
+			(PROMContent[EEPROM_HT20_MAX_PWR_OFFSET+ group] >> (rfPath * 4)) & 0xF;
+		}
+	}
+
+	pwrInfo->TSSI_A = PROMContent[EEPROM_TSSI_A];
+	pwrInfo->TSSI_B = PROMContent[EEPROM_TSSI_B];
+
+}
+
+
+static u32
+_GetChannelGroup(
+	IN	u32	channel
+	)
+{
+	//RT_ASSERT((channel < 14), ("Channel %d no is supported!\n"));
+
+	if(channel < 3){ 	// Channel 1~3
+		return 0;
+	}
+	else if(channel < 9){ // Channel 4~9
+		return 1;
+	}
+
+	return 2;				// Channel 10~14	
+}
+
+
+static VOID
+ReadTxPowerInfo(
+	IN	PADAPTER 		Adapter,
+	IN	u8*			PROMContent,
+	IN	BOOLEAN			AutoLoadFail
+	)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
+	TxPowerInfo		pwrInfo;
+	u32			rfPath, ch, group;
+	u8			pwr, diff;
+
+	_ReadPowerValueFromPROM(&pwrInfo, PROMContent, AutoLoadFail);
+
+	if(!AutoLoadFail)
+		pHalData->bTXPowerDataReadFromEEPORM = _TRUE;
+
+	for(rfPath = 0 ; rfPath < RF_PATH_MAX ; rfPath++){
+		for(ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){
+			group = _GetChannelGroup(ch);
+
+			pHalData->TxPwrLevelCck[rfPath][ch]		= pwrInfo.CCKIndex[rfPath][group];
+			pHalData->TxPwrLevelHT40_1S[rfPath][ch]	= pwrInfo.HT40_1SIndex[rfPath][group];
+
+			pHalData->TxPwrHt20Diff[rfPath][ch]		= pwrInfo.HT20IndexDiff[rfPath][group];
+			pHalData->TxPwrLegacyHtDiff[rfPath][ch]	= pwrInfo.OFDMIndexDiff[rfPath][group];
+			pHalData->PwrGroupHT20[rfPath][ch]		= pwrInfo.HT20MaxOffset[rfPath][group];
+			pHalData->PwrGroupHT40[rfPath][ch]		= pwrInfo.HT40MaxOffset[rfPath][group];
+
+			pwr		= pwrInfo.HT40_1SIndex[rfPath][group];
+			diff	= pwrInfo.HT40_2SIndexDiff[rfPath][group];
+
+			pHalData->TxPwrLevelHT40_2S[rfPath][ch]  = (pwr > diff) ? (pwr - diff) : 0;
+		}
+	}
+
+#if 0 //DBG
+
+	for(rfPath = 0 ; rfPath < RF_PATH_MAX ; rfPath++){
+		for(ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){
+			RTPRINT(FINIT, INIT_TxPower, 
+				("RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n", 
+				rfPath, ch, pHalData->TxPwrLevelCck[rfPath][ch], 
+				pHalData->TxPwrLevelHT40_1S[rfPath][ch], 
+				pHalData->TxPwrLevelHT40_2S[rfPath][ch]));
+
+		}
+	}
+
+	for(ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){
+		RTPRINT(FINIT, INIT_TxPower, ("RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", ch, pHalData->TxPwrHt20Diff[RF_PATH_A][ch]));
+	}
+
+	for(ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){
+		RTPRINT(FINIT, INIT_TxPower, ("RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", ch, pHalData->TxPwrLegacyHtDiff[RF_PATH_A][ch]));
+	}
+	
+	for(ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){
+		RTPRINT(FINIT, INIT_TxPower, ("RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", ch, pHalData->TxPwrHt20Diff[RF_PATH_B][ch]));
+	}
+	
+	for(ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){
+		RTPRINT(FINIT, INIT_TxPower, ("RF-B Legacy to HT40 Diff[%d] = 0x%x\n", ch, pHalData->TxPwrLegacyHtDiff[RF_PATH_B][ch]));
+	}
+	
+#endif
+	// 2010/10/19 MH Add Regulator recognize for CU.
+	if(!AutoLoadFail)
+	{
+		pHalData->EEPROMRegulatory = (PROMContent[RF_OPTION1]&0x7);	//bit0~2
+	}
+	else
+	{
+		pHalData->EEPROMRegulatory = 0;
+	}
+	DBG_8192C("EEPROMRegulatory = 0x%x\n", pHalData->EEPROMRegulatory);
+
+}
+#endif
+
+//-------------------------------------------------------------------
+//
+//	EEPROM/EFUSE Content Parsing
+//
+//-------------------------------------------------------------------
+static void
+_ReadIDs(
+	IN	PADAPTER	Adapter,
+	IN	u8*		PROMContent,
+	IN	BOOLEAN		AutoloadFail
+	)
+{
+#if 0
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
+
+	if(_FALSE == AutoloadFail){
+		// VID, PID 
+		pHalData->EEPROMVID = le16_to_cpu( *(u16 *)&PROMContent[EEPROM_VID]);
+		pHalData->EEPROMPID = le16_to_cpu( *(u16 *)&PROMContent[EEPROM_PID]);
+		
+		// Customer ID, 0x00 and 0xff are reserved for Realtek. 		
+		pHalData->EEPROMCustomerID = *(u8 *)&PROMContent[EEPROM_CUSTOMER_ID];
+		pHalData->EEPROMSubCustomerID = *(u8 *)&PROMContent[EEPROM_SUBCUSTOMER_ID];
+
+	}
+	else{
+		pHalData->EEPROMVID	 = EEPROM_Default_VID;
+		pHalData->EEPROMPID	 = EEPROM_Default_PID;
+
+		// Customer ID, 0x00 and 0xff are reserved for Realtek. 		
+		pHalData->EEPROMCustomerID	= EEPROM_Default_CustomerID;
+		pHalData->EEPROMSubCustomerID = EEPROM_Default_SubCustomerID;
+
+	}
+
+	// For customized behavior.
+	if((pHalData->EEPROMVID == 0x103C) && (pHalData->EEPROMVID == 0x1629))// HP Lite-On for RTL8188CUS Slim Combo.
+		pHalData->CustomerID = RT_CID_819x_HP;
+
+	//	Decide CustomerID according to VID/DID or EEPROM
+	switch(pHalData->EEPROMCustomerID)
+	{
+		case EEPROM_CID_DEFAULT:
+			if((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x3308))
+				pHalData->CustomerID = RT_CID_DLINK;
+			else if((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x3309))
+				pHalData->CustomerID = RT_CID_DLINK;
+			else if((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x330a))
+				pHalData->CustomerID = RT_CID_DLINK;
+			break;
+		case EEPROM_CID_WHQL:
+/*			
+			Adapter->bInHctTest = TRUE;
+
+			pMgntInfo->bSupportTurboMode = FALSE;
+			pMgntInfo->bAutoTurboBy8186 = FALSE;
+
+			pMgntInfo->PowerSaveControl.bInactivePs = FALSE;
+			pMgntInfo->PowerSaveControl.bIPSModeBackup = FALSE;
+			pMgntInfo->PowerSaveControl.bLeisurePs = FALSE;
+				
+			pMgntInfo->keepAliveLevel = 0;
+
+			Adapter->bUnloadDriverwhenS3S4 = FALSE;
+*/				
+			break;
+		default:
+			pHalData->CustomerID = RT_CID_DEFAULT;
+			break;
+			
+	}
+
+	MSG_8192C("EEPROMVID = 0x%04x\n", pHalData->EEPROMVID);
+	MSG_8192C("EEPROMPID = 0x%04x\n", pHalData->EEPROMPID);
+	MSG_8192C("EEPROMCustomerID : 0x%02x\n", pHalData->EEPROMCustomerID);
+	MSG_8192C("EEPROMSubCustomerID: 0x%02x\n", pHalData->EEPROMSubCustomerID);
+
+	MSG_8192C("RT_CustomerID: 0x%02x\n", pHalData->CustomerID);
+#endif
+}
+
+
+static VOID
+_ReadMACAddress(
+	IN	PADAPTER	Adapter,	
+	IN	u8*		PROMContent,
+	IN	BOOLEAN		AutoloadFail
+	)
+{
+#if 0
+	
+	EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter);
+
+	if(_FALSE == AutoloadFail){
+		//Read Permanent MAC address and set value to hardware
+		_rtw_memcpy(pEEPROM->mac_addr, &PROMContent[EEPROM_MAC_ADDR], ETH_ALEN);		
+	}
+	else{
+		//Random assigh MAC address
+		u8 sMacAddr[MAC_ADDR_LEN] = {0x00, 0xE0, 0x4C, 0x81, 0x92, 0x00};
+		//sMacAddr[5] = (u8)GetRandomNumber(1, 254);		
+		_rtw_memcpy(pEEPROM->mac_addr, sMacAddr, ETH_ALEN);	
+	}
+	DBG_8192C("%s MAC Address from EFUSE = "MAC_FMT"\n",__FUNCTION__, MAC_ARG(pEEPROM->mac_addr));
+	//NicIFSetMacAddress(Adapter, Adapter->PermanentAddress);
+	//RT_PRINT_ADDR(COMP_INIT|COMP_EFUSE, DBG_LOUD, "MAC Addr: %s", Adapter->PermanentAddress);
+#endif
+}
+
+static VOID
+_ReadBoardType(
+	IN	PADAPTER	Adapter,	
+	IN	u8*		PROMContent,
+	IN	BOOLEAN		AutoloadFail
+	)
+{
+ 
+}
+
+
+static VOID
+_ReadLEDSetting(
+	IN	PADAPTER	Adapter,	
+	IN	u8*		PROMContent,
+	IN	BOOLEAN		AutoloadFail
+	)
+{
+	struct led_priv *pledpriv = &(Adapter->ledpriv);
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
+#ifdef CONFIG_SW_LED
+	pledpriv->bRegUseLed = _TRUE;
+
+	switch(pHalData->CustomerID)
+	{
+		default:
+			pledpriv->LedStrategy = SW_LED_MODE1;
+			break;
+	}
+	pHalData->bLedOpenDrain = _TRUE;// Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16.
+#else // HW LED
+	pledpriv->LedStrategy = HW_LED;
+#endif //CONFIG_SW_LED
+}
+
+static VOID
+_ReadThermalMeter(
+	IN	PADAPTER	Adapter,	
+	IN	u8* 	PROMContent,
+	IN	BOOLEAN 	AutoloadFail
+	)
+{
+#if 0
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
+	struct dm_priv	*pdmpriv = &pHalData->dmpriv;
+	u8	tempval;
+
+	//
+	// ThermalMeter from EEPROM
+	//
+	if(!AutoloadFail)	
+		tempval = PROMContent[EEPROM_THERMAL_METER];
+	else
+		tempval = EEPROM_Default_ThermalMeter;
+	
+	pHalData->EEPROMThermalMeter = (tempval&0x1f);	//[4:0]
+
+	if(pHalData->EEPROMThermalMeter == 0x1f || AutoloadFail)
+		pdmpriv->bAPKThermalMeterIgnore = _TRUE;
+
+#if 0
+	if(pHalData->EEPROMThermalMeter < 0x06 || pHalData->EEPROMThermalMeter > 0x1c)
+		pHalData->EEPROMThermalMeter = 0x12;
+#endif
+
+	pdmpriv->ThermalMeter[0] = pHalData->EEPROMThermalMeter;
+	
+	//RTPRINT(FINIT, INIT_TxPower, ("ThermalMeter = 0x%x\n", pHalData->EEPROMThermalMeter));
+#endif	
+}
+
+static VOID
+_ReadRFSetting(
+	IN	PADAPTER	Adapter,	
+	IN	u8* 	PROMContent,
+	IN	BOOLEAN 	AutoloadFail
+	)
+{
+}
+
+static void
+_ReadPROMVersion(
+	IN	PADAPTER	Adapter,	
+	IN	u8* 	PROMContent,
+	IN	BOOLEAN 	AutoloadFail
+	)
+{
+#if 0
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
+
+	if(AutoloadFail){
+		pHalData->EEPROMVersion = EEPROM_Default_Version;		
+	}
+	else{
+		pHalData->EEPROMVersion = *(u8 *)&PROMContent[EEPROM_VERSION];
+	}
+#endif
+}
+
+static VOID
+readAntennaDiversity(
+	IN	PADAPTER	pAdapter,
+	IN	u8			*hwinfo,
+	IN	BOOLEAN		AutoLoadFail
+	)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
+	struct registry_priv	*registry_par = &pAdapter->registrypriv;
+
+	pHalData->AntDivCfg = registry_par->antdiv_cfg ;  // 0:OFF , 1:ON,
+#if 0
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
+	struct registry_priv	*registry_par = &pAdapter->registrypriv;
+
+	if(!AutoLoadFail)
+	{
+		// Antenna Diversity setting. 
+		if(registry_par->antdiv_cfg == 2) // 2: From Efuse
+			pHalData->AntDivCfg = (hwinfo[EEPROM_RF_OPT1]&0x18)>>3;
+		else
+			pHalData->AntDivCfg = registry_par->antdiv_cfg ;  // 0:OFF , 1:ON,
+
+		DBG_8192C("### AntDivCfg(%x)\n",pHalData->AntDivCfg);	
+
+		//if(pHalData->EEPROMBluetoothCoexist!=0 && pHalData->EEPROMBluetoothAntNum==Ant_x1)
+		//	pHalData->AntDivCfg = 0;
+	}
+	else
+	{
+		pHalData->AntDivCfg = 0;
+	}
+#endif
+}
+
+static VOID
+hal_InitPGData(
+	IN	PADAPTER	pAdapter,
+	IN	OUT	u8		*PROMContent
+	)
+{
+#if 0
+	EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(pAdapter);
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
+	u32	i;
+	u16	value16;
+
+	if(_FALSE == pEEPROM->bautoload_fail_flag)
+	{ // autoload OK.
+		if (_TRUE == pEEPROM->EepromOrEfuse)
+		{
+			// Read all Content from EEPROM or EFUSE.
+			for(i = 0; i < HWSET_MAX_SIZE_88E; i += 2)
+			{
+				//value16 = EF2Byte(ReadEEprom(pAdapter, (u2Byte) (i>>1)));
+				//*((u16 *)(&PROMContent[i])) = value16; 				
+			}
+		}
+		else
+		{
+			// Read EFUSE real map to shadow.
+			EFUSE_ShadowMapUpdate(pAdapter, EFUSE_WIFI, _FALSE);
+			_rtw_memcpy((void*)PROMContent, (void*)pEEPROM->efuse_eeprom_data, HWSET_MAX_SIZE_88E);
+		}
+	}
+	else
+	{//autoload fail
+		//RT_TRACE(COMP_INIT, DBG_LOUD, ("AutoLoad Fail reported from CR9346!!\n")); 
+		pEEPROM->bautoload_fail_flag = _TRUE;
+		//update to default value 0xFF
+		if (_FALSE == pEEPROM->EepromOrEfuse)		
+		EFUSE_ShadowMapUpdate(pAdapter, EFUSE_WIFI, _FALSE);	
+	}
+#endif
+}
+static void
+Hal_EfuseParsePIDVID_8188EU(
+	IN	PADAPTER		pAdapter,
+	IN	u8*				hwinfo,
+	IN	BOOLEAN			AutoLoadFail
+	)
+{
+
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(pAdapter);
+
+	if( !AutoLoadFail )
+	{
+		// VID, PID 
+		pHalData->EEPROMVID = EF2Byte( *(u16 *)&hwinfo[EEPROM_VID_88EU] );
+		pHalData->EEPROMPID = EF2Byte( *(u16 *)&hwinfo[EEPROM_PID_88EU] );
+		
+		// Customer ID, 0x00 and 0xff are reserved for Realtek. 		
+		pHalData->EEPROMCustomerID = *(u8 *)&hwinfo[EEPROM_CUSTOMERID_88E];
+		pHalData->EEPROMSubCustomerID = EEPROM_Default_SubCustomerID;
+
+	}
+	else
+	{
+		pHalData->EEPROMVID 			= EEPROM_Default_VID;
+		pHalData->EEPROMPID 			= EEPROM_Default_PID;
+
+		// Customer ID, 0x00 and 0xff are reserved for Realtek. 		
+		pHalData->EEPROMCustomerID		= EEPROM_Default_CustomerID;
+		pHalData->EEPROMSubCustomerID	= EEPROM_Default_SubCustomerID;
+
+	}
+
+	DBG_871X("VID = 0x%04X, PID = 0x%04X\n", pHalData->EEPROMVID, pHalData->EEPROMPID);
+	DBG_871X("Customer ID: 0x%02X, SubCustomer ID: 0x%02X\n", pHalData->EEPROMCustomerID, pHalData->EEPROMSubCustomerID);
+}
+
+static void
+Hal_EfuseParseMACAddr_8188EU(
+	IN	PADAPTER		padapter,
+	IN	u8*			hwinfo,
+	IN	BOOLEAN			AutoLoadFail
+	)
+{
+	u16			i, usValue;
+	u8			sMacAddr[6] = {0x00, 0xE0, 0x4C, 0x81, 0x88, 0x02};
+	EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
+
+	if (AutoLoadFail)
+	{
+//		sMacAddr[5] = (u1Byte)GetRandomNumber(1, 254);
+		for (i=0; i<6; i++)
+			pEEPROM->mac_addr[i] = sMacAddr[i];
+	}
+	else
+	{
+		//Read Permanent MAC address
+		_rtw_memcpy(pEEPROM->mac_addr, &hwinfo[EEPROM_MAC_ADDR_88EU], ETH_ALEN);
+
+	}
+//	NicIFSetMacAddress(pAdapter, pAdapter->PermanentAddress);
+
+	RT_TRACE(_module_hci_hal_init_c_, _drv_notice_,
+			("Hal_EfuseParseMACAddr_8188EU: Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n",
+		  pEEPROM->mac_addr[0], pEEPROM->mac_addr[1],
+		  pEEPROM->mac_addr[2], pEEPROM->mac_addr[3],
+		  pEEPROM->mac_addr[4], pEEPROM->mac_addr[5]));
+}
+
+
+static void
+Hal_CustomizeByCustomerID_8188EU(
+	IN	PADAPTER		padapter
+	)
+{
+#if 0
+	PMGNT_INFO		pMgntInfo = &(padapter->MgntInfo);
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+
+	// For customized behavior.
+	if((pHalData->EEPROMVID == 0x103C) && (pHalData->EEPROMVID == 0x1629))// HP Lite-On for RTL8188CUS Slim Combo.
+		pMgntInfo->CustomerID = RT_CID_819x_HP;
+
+	// Decide CustomerID according to VID/DID or EEPROM
+	switch(pHalData->EEPROMCustomerID)
+	{
+		case EEPROM_CID_DEFAULT:
+			if((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x3308))
+				pMgntInfo->CustomerID = RT_CID_DLINK;
+			else if((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x3309))
+				pMgntInfo->CustomerID = RT_CID_DLINK;
+			else if((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x330a))
+				pMgntInfo->CustomerID = RT_CID_DLINK;
+			break;
+		case EEPROM_CID_WHQL:
+			padapter->bInHctTest = TRUE;
+
+			pMgntInfo->bSupportTurboMode = FALSE;
+			pMgntInfo->bAutoTurboBy8186 = FALSE;
+
+			pMgntInfo->PowerSaveControl.bInactivePs = FALSE;
+			pMgntInfo->PowerSaveControl.bIPSModeBackup = FALSE;
+			pMgntInfo->PowerSaveControl.bLeisurePs = FALSE;
+			pMgntInfo->PowerSaveControl.bLeisurePsModeBackup =FALSE;
+			pMgntInfo->keepAliveLevel = 0;
+
+			padapter->bUnloadDriverwhenS3S4 = FALSE;
+			break;
+		default:
+			pMgntInfo->CustomerID = RT_CID_DEFAULT;
+			break;
+
+	}
+
+	RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Mgnt Customer ID: 0x%02x\n", pMgntInfo->CustomerID));
+
+	hal_CustomizedBehavior_8723U(padapter);
+#endif
+}
+
+// Read HW power down mode selection 
+static void _ReadPSSetting(IN PADAPTER Adapter,IN u8*PROMContent,IN u8	AutoloadFail)
+{
+#if 0
+	if(AutoloadFail){
+		Adapter->pwrctrlpriv.bHWPowerdown = _FALSE;
+		Adapter->pwrctrlpriv.bSupportRemoteWakeup = _FALSE;
+	}
+	else	{
+		//if(SUPPORT_HW_RADIO_DETECT(Adapter))
+			Adapter->pwrctrlpriv.bHWPwrPindetect = Adapter->registrypriv.hwpwrp_detect;
+		//else
+			//Adapter->pwrctrlpriv.bHWPwrPindetect = _FALSE;//dongle not support new
+			
+			
+		//hw power down mode selection , 0:rf-off / 1:power down
+
+		if(Adapter->registrypriv.hwpdn_mode==2)
+			Adapter->pwrctrlpriv.bHWPowerdown = (PROMContent[EEPROM_RF_OPT3] & BIT4);
+		else
+			Adapter->pwrctrlpriv.bHWPowerdown = Adapter->registrypriv.hwpdn_mode;
+				
+		// decide hw if support remote wakeup function
+		// if hw supported, 8051 (SIE) will generate WeakUP signal( D+/D- toggle) when autoresume
+		Adapter->pwrctrlpriv.bSupportRemoteWakeup = (PROMContent[EEPROM_TEST_USB_OPT] & BIT1)?_TRUE :_FALSE;
+
+		//if(SUPPORT_HW_RADIO_DETECT(Adapter))	
+			//Adapter->registrypriv.usbss_enable = Adapter->pwrctrlpriv.bSupportRemoteWakeup ;
+		
+		DBG_8192C("%s...bHWPwrPindetect(%x)-bHWPowerdown(%x) ,bSupportRemoteWakeup(%x)\n",__FUNCTION__,
+		Adapter->pwrctrlpriv.bHWPwrPindetect,Adapter->pwrctrlpriv.bHWPowerdown ,Adapter->pwrctrlpriv.bSupportRemoteWakeup);
+
+		DBG_8192C("### PS params=>  power_mgnt(%x),usbss_enable(%x) ###\n",Adapter->registrypriv.power_mgnt,Adapter->registrypriv.usbss_enable);
+		
+	}
+#endif	
+}
+
+#ifdef CONFIG_EFUSE_CONFIG_FILE
+static u32 Hal_readPGDataFromConfigFile(
+	PADAPTER	padapter)
+{
+	u32 i;
+	struct file *fp;
+	mm_segment_t fs;
+	u8 temp[3];
+	loff_t pos = 0;
+	EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
+	u8	*PROMContent = pEEPROM->efuse_eeprom_data;
+
+
+	temp[2] = 0; // add end of string '\0'
+
+	fp = filp_open("/system/etc/wifi/wifi_efuse.map", O_RDWR,  0644);
+	if (IS_ERR(fp)) {
+		pEEPROM->bloadfile_fail_flag = _TRUE;
+		DBG_871X("Error, Efuse configure file doesn't exist.\n");
+		return _FAIL;
+	}
+
+	fs = get_fs();
+	set_fs(KERNEL_DS);
+
+	DBG_871X("Efuse configure file:\n");
+	for (i=0; i<HWSET_MAX_SIZE_88E; i++) {
+		vfs_read(fp, temp, 2, &pos);
+		PROMContent[i] = simple_strtoul(temp, NULL, 16 );
+		pos += 1; // Filter the space character
+		DBG_871X("%02X \n", PROMContent[i]);
+	}
+	DBG_871X("\n");
+	set_fs(fs);
+
+	filp_close(fp, NULL);
+	
+	pEEPROM->bloadfile_fail_flag = _FALSE;
+	
+	return _SUCCESS;
+}
+
+static void
+Hal_ReadMACAddrFromFile_8188EU(
+	PADAPTER		padapter
+	)
+{
+	u32 i;
+	struct file *fp;
+	mm_segment_t fs;
+	u8 source_addr[18];
+	loff_t pos = 0;
+	u32 curtime = rtw_get_current_time();
+	EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
+	u8 *head, *end;
+
+	u8 null_mac_addr[ETH_ALEN] = {0, 0, 0,0, 0, 0};
+	u8 multi_mac_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+	
+	_rtw_memset(source_addr, 0, 18);
+	_rtw_memset(pEEPROM->mac_addr, 0, ETH_ALEN);
+
+	fp = filp_open("/data/wifimac.txt", O_RDWR,  0644);
+	if (IS_ERR(fp)) {
+		pEEPROM->bloadmac_fail_flag = _TRUE;
+		DBG_871X("Error, wifi mac address file doesn't exist.\n");
+	} else {
+		fs = get_fs();
+		set_fs(KERNEL_DS);
+
+		DBG_871X("wifi mac address:\n");
+		vfs_read(fp, source_addr, 18, &pos);
+		source_addr[17] = ':';
+
+		head = end = source_addr;
+		for (i=0; i<ETH_ALEN; i++) {
+			while (end && (*end != ':') )
+				end++;
+
+			if (end && (*end == ':') )
+				*end = '\0';
+
+			pEEPROM->mac_addr[i] = simple_strtoul(head, NULL, 16 );
+
+			if (end) {
+				end++;
+				head = end;
+			}
+			DBG_871X("%02x \n", pEEPROM->mac_addr[i]);
+		}
+		DBG_871X("\n");
+		set_fs(fs);
+		pEEPROM->bloadmac_fail_flag = _FALSE;
+		filp_close(fp, NULL);
+	}
+
+	if ( (_rtw_memcmp(pEEPROM->mac_addr, null_mac_addr, ETH_ALEN)) ||
+		(_rtw_memcmp(pEEPROM->mac_addr, multi_mac_addr, ETH_ALEN)) ) {
+		pEEPROM->mac_addr[0] = 0x00;
+		pEEPROM->mac_addr[1] = 0xe0;
+		pEEPROM->mac_addr[2] = 0x4c;
+		pEEPROM->mac_addr[3] = (u8)(curtime & 0xff) ;
+		pEEPROM->mac_addr[4] = (u8)((curtime>>8) & 0xff) ;
+		pEEPROM->mac_addr[5] = (u8)((curtime>>16) & 0xff) ;
+	}
+
+	DBG_871X("Hal_ReadMACAddrFromFile_8188ES: Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n",
+		  pEEPROM->mac_addr[0], pEEPROM->mac_addr[1],
+		  pEEPROM->mac_addr[2], pEEPROM->mac_addr[3],
+		  pEEPROM->mac_addr[4], pEEPROM->mac_addr[5]);
+}
+#endif //CONFIG_EFUSE_CONFIG_FILE
+
+static VOID
+readAdapterInfo_8188EU(
+	IN	PADAPTER	padapter
+	)
+{
+#if 1
+	EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
+
+	/* parse the eeprom/efuse content */
+	Hal_EfuseParseIDCode88E(padapter, pEEPROM->efuse_eeprom_data);
+	Hal_EfuseParsePIDVID_8188EU(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
+#ifdef CONFIG_EFUSE_CONFIG_FILE
+	Hal_ReadMACAddrFromFile_8188EU(padapter);
+#else //CONFIG_EFUSE_CONFIG_FILE	
+	Hal_EfuseParseMACAddr_8188EU(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
+#endif //CONFIG_EFUSE_CONFIG_FILE	
+
+	Hal_ReadPowerSavingMode88E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
+	Hal_ReadTxPowerInfo88E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);	
+	Hal_EfuseParseEEPROMVer88E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
+	rtl8188e_EfuseParseChnlPlan(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
+	Hal_EfuseParseXtal_8188E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
+	Hal_EfuseParseCustomerID88E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
+	Hal_ReadAntennaDiversity88E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
+	Hal_EfuseParseBoardType88E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
+	Hal_ReadThermalMeter_88E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
+
+	//
+	// The following part initialize some vars by PG info.
+	//
+	Hal_InitChannelPlan(padapter);
+#if defined(CONFIG_WOWLAN) && defined(CONFIG_SDIO_HCI)
+	Hal_DetectWoWMode(padapter);
+#endif //CONFIG_WOWLAN && CONFIG_SDIO_HCI
+	Hal_CustomizeByCustomerID_8188EU(padapter);
+
+	_ReadLEDSetting(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
+
+#else
+
+#ifdef CONFIG_INTEL_PROXIM	
+		/* for intel proximity */
+	if (pHalData->rf_type== RF_1T1R) {
+		Adapter->proximity.proxim_support = _TRUE;
+	} else if (pHalData->rf_type== RF_2T2R) {
+		if ((pHalData->EEPROMPID == 0x8186) &&
+			(pHalData->EEPROMVID== 0x0bda))
+		Adapter->proximity.proxim_support = _TRUE;
+	} else {
+		Adapter->proximity.proxim_support = _FALSE;
+	}
+#endif //CONFIG_INTEL_PROXIM		
+#endif
+}
+
+static void _ReadPROMContent(
+	IN PADAPTER 		Adapter
+	)
+{	
+	EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter);
+	u8			eeValue;
+
+	/* check system boot selection */
+	eeValue = rtw_read8(Adapter, REG_9346CR);
+	pEEPROM->EepromOrEfuse		= (eeValue & BOOT_FROM_EEPROM) ? _TRUE : _FALSE;
+	pEEPROM->bautoload_fail_flag	= (eeValue & EEPROM_EN) ? _FALSE : _TRUE;
+
+
+	DBG_8192C("Boot from %s, Autoload %s !\n", (pEEPROM->EepromOrEfuse ? "EEPROM" : "EFUSE"),
+				(pEEPROM->bautoload_fail_flag ? "Fail" : "OK") );
+
+	//pHalData->EEType = IS_BOOT_FROM_EEPROM(Adapter) ? EEPROM_93C46 : EEPROM_BOOT_EFUSE;
+#ifdef CONFIG_EFUSE_CONFIG_FILE
+	Hal_readPGDataFromConfigFile(Adapter);
+#else //CONFIG_EFUSE_CONFIG_FILE
+	Hal_InitPGData88E(Adapter);
+#endif	//CONFIG_EFUSE_CONFIG_FILE
+	readAdapterInfo_8188EU(Adapter);
+}
+
+
+
+static VOID
+_ReadRFType(
+	IN	PADAPTER	Adapter
+	)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
+
+#if DISABLE_BB_RF
+	pHalData->rf_chip = RF_PSEUDO_11N;
+#else
+	pHalData->rf_chip = RF_6052;
+#endif
+}
+
+static int _ReadAdapterInfo8188EU(PADAPTER	Adapter)
+{
+	//HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
+	u32 start=rtw_get_current_time();
+	
+	MSG_8192C("====> %s\n", __FUNCTION__);
+
+	//Efuse_InitSomeVar(Adapter);
+
+	//if(IS_HARDWARE_TYPE_8723A(Adapter))
+	//	_EfuseCellSel(Adapter);
+
+	_ReadRFType(Adapter);//rf_chip -> _InitRFType()
+	_ReadPROMContent(Adapter);
+
+	//MSG_8192C("%s()(done), rf_chip=0x%x, rf_type=0x%x\n",  __FUNCTION__, pHalData->rf_chip, pHalData->rf_type);
+
+	MSG_8192C("<==== %s in %d ms\n", __FUNCTION__, rtw_get_passing_time_ms(start));
+
+	return _SUCCESS;
+}
+
+
+static void ReadAdapterInfo8188EU(PADAPTER Adapter)
+{
+	// Read EEPROM size before call any EEPROM function	
+	Adapter->EepromAddressSize = GetEEPROMSize8188E(Adapter);
+	
+	_ReadAdapterInfo8188EU(Adapter);
+}
+
+
+#define GPIO_DEBUG_PORT_NUM 0
+static void rtl8192cu_trigger_gpio_0(_adapter *padapter)
+{
+#ifdef CONFIG_USB_SUPPORT_ASYNC_VDN_REQ	
+	u32 gpioctrl;
+	DBG_8192C("==> trigger_gpio_0...\n");
+	rtw_write16_async(padapter,REG_GPIO_PIN_CTRL,0);
+	rtw_write8_async(padapter,REG_GPIO_PIN_CTRL+2,0xFF);
+	gpioctrl = (BIT(GPIO_DEBUG_PORT_NUM)<<24 )|(BIT(GPIO_DEBUG_PORT_NUM)<<16);
+	rtw_write32_async(padapter,REG_GPIO_PIN_CTRL,gpioctrl);
+	gpioctrl |= (BIT(GPIO_DEBUG_PORT_NUM)<<8);
+	rtw_write32_async(padapter,REG_GPIO_PIN_CTRL,gpioctrl);
+	DBG_8192C("<=== trigger_gpio_0...\n");
+#endif
+}
+
+static void ResumeTxBeacon(_adapter *padapter)
+{
+	HAL_DATA_TYPE*	pHalData = GET_HAL_DATA(padapter);	
+
+	// 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value
+	// which should be read from register to a global variable.
+
+	rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, (pHalData->RegFwHwTxQCtrl) | BIT6);
+	pHalData->RegFwHwTxQCtrl |= BIT6;
+	rtw_write8(padapter, REG_TBTT_PROHIBIT+1, 0xff);
+	pHalData->RegReg542 |= BIT0;
+	rtw_write8(padapter, REG_TBTT_PROHIBIT+2, pHalData->RegReg542);
+}
+void UpdateInterruptMask8188EU(PADAPTER padapter,u8 bHIMR0 ,u32 AddMSR, u32 RemoveMSR)
+{
+	HAL_DATA_TYPE *pHalData;
+
+	u32 *himr;
+	pHalData = GET_HAL_DATA(padapter);
+
+	if(bHIMR0)
+		himr = &(pHalData->IntrMask[0]);
+	else
+		himr = &(pHalData->IntrMask[1]);
+	
+	if (AddMSR)
+		*himr |= AddMSR;
+
+	if (RemoveMSR)
+		*himr &= (~RemoveMSR);
+
+	if(bHIMR0)	
+		rtw_write32(padapter, REG_HIMR_88E, *himr);
+	else
+		rtw_write32(padapter, REG_HIMRE_88E, *himr);	
+
+}
+
+static void StopTxBeacon(_adapter *padapter)
+{
+	HAL_DATA_TYPE*	pHalData = GET_HAL_DATA(padapter);
+
+	// 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value
+	// which should be read from register to a global variable.
+
+	rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, (pHalData->RegFwHwTxQCtrl) & (~BIT6));
+	pHalData->RegFwHwTxQCtrl &= (~BIT6);
+	rtw_write8(padapter, REG_TBTT_PROHIBIT+1, 0x64);
+	pHalData->RegReg542 &= ~(BIT0);
+	rtw_write8(padapter, REG_TBTT_PROHIBIT+2, pHalData->RegReg542);
+
+	 //todo: CheckFwRsvdPageContent(Adapter);  // 2010.06.23. Added by tynli.
+
+}
+
+
+static void hw_var_set_opmode(PADAPTER Adapter, u8 variable, u8* val)
+{
+	u8	val8;
+	u8	mode = *((u8 *)val);
+	//HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
+
+#ifdef CONFIG_CONCURRENT_MODE
+	if(Adapter->iface_type == IFACE_PORT1)
+	{
+		// disable Port1 TSF update
+		rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(4));
+		
+		// set net_type
+		val8 = rtw_read8(Adapter, MSR)&0x03;
+		val8 |= (mode<<2);
+		rtw_write8(Adapter, MSR, val8);
+		
+		DBG_871X("%s()-%d mode = %d\n", __FUNCTION__, __LINE__, mode);
+
+		if((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_))
+		{
+			if(!check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE))			
+			{
+				#ifdef CONFIG_INTERRUPT_BASED_TXBCN	
+
+				#ifdef  CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT	
+				rtw_write8(Adapter, REG_DRVERLYINT, 0x05);//restore early int time to 5ms
+				UpdateInterruptMask8188EU(Adapter,_TRUE, 0, IMR_BCNDMAINT0_88E);	
+				#endif // CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
+				
+				#ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR		
+				UpdateInterruptMask8188EU(Adapter,_TRUE ,0, (IMR_TBDER_88E|IMR_TBDOK_88E));	
+				#endif// CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
+					
+				#endif //CONFIG_INTERRUPT_BASED_TXBCN		
+			
+
+				StopTxBeacon(Adapter);
+			}
+			
+			rtw_write8(Adapter,REG_BCN_CTRL_1, 0x19);//disable atim wnd
+			//rtw_write8(Adapter,REG_BCN_CTRL_1, 0x18);
+		}
+		else if((mode == _HW_STATE_ADHOC_) /*|| (mode == _HW_STATE_AP_)*/)
+		{
+			ResumeTxBeacon(Adapter);
+			rtw_write8(Adapter,REG_BCN_CTRL_1, 0x1a);
+		}
+		else if(mode == _HW_STATE_AP_)
+		{
+#ifdef CONFIG_INTERRUPT_BASED_TXBCN			
+			#ifdef  CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
+			UpdateInterruptMask8188EU(Adapter,_TRUE ,IMR_BCNDMAINT0_88E, 0);
+			#endif//CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
+
+			#ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR	
+			UpdateInterruptMask8188EU(Adapter,_TRUE ,(IMR_TBDER_88E|IMR_TBDOK_88E), 0);
+			#endif//CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
+					
+#endif //CONFIG_INTERRUPT_BASED_TXBCN
+
+			ResumeTxBeacon(Adapter);
+					
+			rtw_write8(Adapter, REG_BCN_CTRL_1, 0x12);
+
+			//Set RCR
+			//rtw_write32(padapter, REG_RCR, 0x70002a8e);//CBSSID_DATA must set to 0
+			//rtw_write32(Adapter, REG_RCR, 0x7000228e);//CBSSID_DATA must set to 0
+			rtw_write32(Adapter, REG_RCR, 0x7000208e);//CBSSID_DATA must set to 0,reject ICV_ERR packet
+			//enable to rx data frame				
+			rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
+			//enable to rx ps-poll
+			rtw_write16(Adapter, REG_RXFLTMAP1, 0x0400);
+
+			//Beacon Control related register for first time 
+			rtw_write8(Adapter, REG_BCNDMATIM, 0x02); // 2ms		
+
+			//rtw_write8(Adapter, REG_BCN_MAX_ERR, 0xFF);
+			rtw_write8(Adapter, REG_ATIMWND_1, 0x0a); // 10ms for port1
+			rtw_write16(Adapter, REG_BCNTCFG, 0x00);
+			rtw_write16(Adapter, REG_TBTT_PROHIBIT, 0xff04);
+			rtw_write16(Adapter, REG_TSFTR_SYN_OFFSET, 0x7fff);// +32767 (~32ms)
+	
+			//reset TSF2	
+			rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(1));
+
+
+			//BIT4 - If set 0, hw will clr bcnq when tx becon ok/fail or port 1
+			rtw_write8(Adapter, REG_MBID_NUM, rtw_read8(Adapter, REG_MBID_NUM)|BIT(3)|BIT(4));
+		       	//enable BCN1 Function for if2
+			//don't enable update TSF1 for if2 (due to TSF update when beacon/probe rsp are received)
+			rtw_write8(Adapter, REG_BCN_CTRL_1, (DIS_TSF_UDT0_NORMAL_CHIP|EN_BCN_FUNCTION | EN_TXBCN_RPT|BIT(1)));
+
+#ifdef CONFIG_CONCURRENT_MODE
+			if(check_buddy_fwstate(Adapter, WIFI_FW_NULL_STATE))
+				rtw_write8(Adapter, REG_BCN_CTRL, 
+					rtw_read8(Adapter, REG_BCN_CTRL) & ~EN_BCN_FUNCTION);
+#endif
+                        //BCN1 TSF will sync to BCN0 TSF with offset(0x518) if if1_sta linked
+			//rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(5));
+			//rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(3));
+					
+			//dis BCN0 ATIM  WND if if1 is station
+			rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(0));
+
+#ifdef CONFIG_TSF_RESET_OFFLOAD
+			// Reset TSF for STA+AP concurrent mode
+			if ( check_buddy_fwstate(Adapter, (WIFI_STATION_STATE|WIFI_ASOC_STATE)) ) {
+				if (reset_tsf(Adapter, IFACE_PORT1) == _FALSE)
+					DBG_871X("ERROR! %s()-%d: Reset port1 TSF fail\n",
+						__FUNCTION__, __LINE__);
+			}
+#endif	// CONFIG_TSF_RESET_OFFLOAD	
+		}
+	}
+	else
+#endif //CONFIG_CONCURRENT_MODE
+	{
+		// disable Port0 TSF update
+		rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4));
+		
+		// set net_type
+		val8 = rtw_read8(Adapter, MSR)&0x0c;
+		val8 |= mode;
+		rtw_write8(Adapter, MSR, val8);
+		
+		DBG_871X("%s()-%d mode = %d\n", __FUNCTION__, __LINE__, mode);
+		
+		if((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_))
+		{
+#ifdef CONFIG_CONCURRENT_MODE
+			if(!check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE))		
+#endif //CONFIG_CONCURRENT_MODE
+			{
+			#ifdef CONFIG_INTERRUPT_BASED_TXBCN	
+				#ifdef  CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
+				rtw_write8(Adapter, REG_DRVERLYINT, 0x05);//restore early int time to 5ms					
+				UpdateInterruptMask8188EU(Adapter,_TRUE, 0, IMR_BCNDMAINT0_88E);	
+				#endif//CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
+				
+				#ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR		
+				UpdateInterruptMask8188EU(Adapter,_TRUE ,0, (IMR_TBDER_88E|IMR_TBDOK_88E));	
+				#endif //CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
+					
+			#endif //CONFIG_INTERRUPT_BASED_TXBCN		
+				StopTxBeacon(Adapter);
+			}
+			
+			rtw_write8(Adapter,REG_BCN_CTRL, 0x19);//disable atim wnd
+			//rtw_write8(Adapter,REG_BCN_CTRL, 0x18);
+		}
+		else if((mode == _HW_STATE_ADHOC_) /*|| (mode == _HW_STATE_AP_)*/)
+		{
+			ResumeTxBeacon(Adapter);
+			rtw_write8(Adapter,REG_BCN_CTRL, 0x1a);
+		}
+		else if(mode == _HW_STATE_AP_)
+		{
+
+#ifdef CONFIG_INTERRUPT_BASED_TXBCN			
+			#ifdef  CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
+			UpdateInterruptMask8188EU(Adapter,_TRUE ,IMR_BCNDMAINT0_88E, 0);
+			#endif//CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
+
+			#ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR	
+			UpdateInterruptMask8188EU(Adapter,_TRUE ,(IMR_TBDER_88E|IMR_TBDOK_88E), 0);
+			#endif//CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
+					
+#endif //CONFIG_INTERRUPT_BASED_TXBCN
+
+
+			ResumeTxBeacon(Adapter);
+
+			rtw_write8(Adapter, REG_BCN_CTRL, 0x12);
+
+			//Set RCR
+			//rtw_write32(padapter, REG_RCR, 0x70002a8e);//CBSSID_DATA must set to 0
+			//rtw_write32(Adapter, REG_RCR, 0x7000228e);//CBSSID_DATA must set to 0
+			rtw_write32(Adapter, REG_RCR, 0x7000208e);//CBSSID_DATA must set to 0,reject ICV_ERR packet
+			//enable to rx data frame
+			rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
+			//enable to rx ps-poll
+			rtw_write16(Adapter, REG_RXFLTMAP1, 0x0400);
+
+			//Beacon Control related register for first time
+			rtw_write8(Adapter, REG_BCNDMATIM, 0x02); // 2ms			
+			
+			//rtw_write8(Adapter, REG_BCN_MAX_ERR, 0xFF);
+			rtw_write8(Adapter, REG_ATIMWND, 0x0a); // 10ms
+			rtw_write16(Adapter, REG_BCNTCFG, 0x00);
+			rtw_write16(Adapter, REG_TBTT_PROHIBIT, 0xff04);
+			rtw_write16(Adapter, REG_TSFTR_SYN_OFFSET, 0x7fff);// +32767 (~32ms)
+
+			//reset TSF
+			rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(0));
+
+			//BIT3 - If set 0, hw will clr bcnq when tx becon ok/fail or port 0
+			rtw_write8(Adapter, REG_MBID_NUM, rtw_read8(Adapter, REG_MBID_NUM)|BIT(3)|BIT(4));
+	
+		        //enable BCN0 Function for if1
+			//don't enable update TSF0 for if1 (due to TSF update when beacon/probe rsp are received)
+			#if defined(CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR)
+			rtw_write8(Adapter, REG_BCN_CTRL, (DIS_TSF_UDT0_NORMAL_CHIP|EN_BCN_FUNCTION | EN_TXBCN_RPT|BIT(1)));
+			#else
+			rtw_write8(Adapter, REG_BCN_CTRL, (DIS_TSF_UDT0_NORMAL_CHIP|EN_BCN_FUNCTION |BIT(1)));
+			#endif
+
+#ifdef CONFIG_CONCURRENT_MODE
+			if(check_buddy_fwstate(Adapter, WIFI_FW_NULL_STATE))
+				rtw_write8(Adapter, REG_BCN_CTRL_1, 
+					rtw_read8(Adapter, REG_BCN_CTRL_1) & ~EN_BCN_FUNCTION);
+#endif
+
+			//dis BCN1 ATIM  WND if if2 is station
+			rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(0));	
+#ifdef CONFIG_TSF_RESET_OFFLOAD
+			// Reset TSF for STA+AP concurrent mode
+			if ( check_buddy_fwstate(Adapter, (WIFI_STATION_STATE|WIFI_ASOC_STATE)) ) {
+				if (reset_tsf(Adapter, IFACE_PORT0) == _FALSE)
+					DBG_871X("ERROR! %s()-%d: Reset port0 TSF fail\n",
+						__FUNCTION__, __LINE__);
+			}
+#endif	// CONFIG_TSF_RESET_OFFLOAD
+		}
+	}
+
+}
+
+static void hw_var_set_macaddr(PADAPTER Adapter, u8 variable, u8* val)
+{
+	u8 idx = 0;
+	u32 reg_macid;
+
+#ifdef CONFIG_CONCURRENT_MODE
+	if(Adapter->iface_type == IFACE_PORT1)
+	{
+		reg_macid = REG_MACID1;
+	}
+	else
+#endif
+	{
+		reg_macid = REG_MACID;
+	}
+
+	for(idx = 0 ; idx < 6; idx++)
+	{
+		rtw_write8(Adapter, (reg_macid+idx), val[idx]);
+	}
+	
+}
+
+static void hw_var_set_bssid(PADAPTER Adapter, u8 variable, u8* val)
+{
+	u8	idx = 0;
+	u32 reg_bssid;
+
+#ifdef CONFIG_CONCURRENT_MODE
+	if(Adapter->iface_type == IFACE_PORT1)
+	{
+		reg_bssid = REG_BSSID1;
+	}
+	else
+#endif
+	{
+		reg_bssid = REG_BSSID;
+	}
+
+	for(idx = 0 ; idx < 6; idx++)
+	{
+		rtw_write8(Adapter, (reg_bssid+idx), val[idx]);
+	}
+
+}
+
+static void hw_var_set_bcn_func(PADAPTER Adapter, u8 variable, u8* val)
+{
+	u32 bcn_ctrl_reg;
+
+#ifdef CONFIG_CONCURRENT_MODE
+	if(Adapter->iface_type == IFACE_PORT1)
+	{
+		bcn_ctrl_reg = REG_BCN_CTRL_1;
+	}	
+	else
+#endif		
+	{		
+		bcn_ctrl_reg = REG_BCN_CTRL;
+	}
+
+	if(*((u8 *)val))
+	{
+		rtw_write8(Adapter, bcn_ctrl_reg, (EN_BCN_FUNCTION | EN_TXBCN_RPT));
+	}
+	else
+	{
+		rtw_write8(Adapter, bcn_ctrl_reg, rtw_read8(Adapter, bcn_ctrl_reg)&(~(EN_BCN_FUNCTION | EN_TXBCN_RPT)));
+	}
+	
+
+}
+
+static void hw_var_set_correct_tsf(PADAPTER Adapter, u8 variable, u8* val)
+{
+#ifdef CONFIG_CONCURRENT_MODE
+	u64	tsf;
+	struct mlme_ext_priv	*pmlmeext = &Adapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	PADAPTER pbuddy_adapter = Adapter->pbuddy_adapter;
+
+	//tsf = pmlmeext->TSFValue - ((u32)pmlmeext->TSFValue % (pmlmeinfo->bcn_interval*1024)) -1024; //us
+	tsf = pmlmeext->TSFValue - rtw_modular64(pmlmeext->TSFValue, (pmlmeinfo->bcn_interval*1024)) -1024; //us
+
+	if(((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE))
+	{				
+		//pHalData->RegTxPause |= STOP_BCNQ;BIT(6)
+		//rtw_write8(Adapter, REG_TXPAUSE, (rtw_read8(Adapter, REG_TXPAUSE)|BIT(6)));
+		StopTxBeacon(Adapter);
+	}
+
+	if(Adapter->iface_type == IFACE_PORT1)
+	{
+		//disable related TSF function
+		rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)&(~BIT(3)));
+							
+		rtw_write32(Adapter, REG_TSFTR1, tsf);
+		rtw_write32(Adapter, REG_TSFTR1+4, tsf>>32);
+
+
+		//enable related TSF function
+		rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(3));	
+
+		// Update buddy port's TSF if it is SoftAP for beacon TX issue!
+		if ( (pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE
+			&& check_buddy_fwstate(Adapter, WIFI_AP_STATE)
+		) { 
+			//disable related TSF function
+			rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(3)));
+
+			rtw_write32(Adapter, REG_TSFTR, tsf);
+			rtw_write32(Adapter, REG_TSFTR+4, tsf>>32);
+
+			//enable related TSF function
+			rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(3));
+#ifdef CONFIG_TSF_RESET_OFFLOAD
+		// Update buddy port's TSF(TBTT) if it is SoftAP for beacon TX issue!
+			if (reset_tsf(Adapter, IFACE_PORT0) == _FALSE)
+				DBG_871X("ERROR! %s()-%d: Reset port0 TSF fail\n",
+					__FUNCTION__, __LINE__);
+
+#endif	// CONFIG_TSF_RESET_OFFLOAD	
+		}		
+
+		
+	}
+	else
+	{
+		//disable related TSF function
+		rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(3)));
+							
+		rtw_write32(Adapter, REG_TSFTR, tsf);
+		rtw_write32(Adapter, REG_TSFTR+4, tsf>>32);
+
+		//enable related TSF function
+		rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(3));
+		
+		// Update buddy port's TSF if it is SoftAP for beacon TX issue!
+		if ( (pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE
+			&& check_buddy_fwstate(Adapter, WIFI_AP_STATE)
+		) { 
+			//disable related TSF function
+			rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)&(~BIT(3)));
+
+			rtw_write32(Adapter, REG_TSFTR1, tsf);
+			rtw_write32(Adapter, REG_TSFTR1+4, tsf>>32);
+
+			//enable related TSF function
+			rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(3));
+#ifdef CONFIG_TSF_RESET_OFFLOAD
+		// Update buddy port's TSF if it is SoftAP for beacon TX issue!
+			if (reset_tsf(Adapter, IFACE_PORT1) == _FALSE)
+				DBG_871X("ERROR! %s()-%d: Reset port1 TSF fail\n",
+					__FUNCTION__, __LINE__);
+#endif	// CONFIG_TSF_RESET_OFFLOAD
+		}		
+
+	}
+				
+							
+	if(((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE))
+	{
+		//pHalData->RegTxPause  &= (~STOP_BCNQ);
+		//rtw_write8(Adapter, REG_TXPAUSE, (rtw_read8(Adapter, REG_TXPAUSE)&(~BIT(6))));
+		ResumeTxBeacon(Adapter);
+	}
+#endif
+}
+
+static void hw_var_set_mlme_disconnect(PADAPTER Adapter, u8 variable, u8* val)
+{
+#ifdef CONFIG_CONCURRENT_MODE
+	//HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
+	PADAPTER pbuddy_adapter = Adapter->pbuddy_adapter;
+			
+				
+	if(check_buddy_mlmeinfo_state(Adapter, _HW_STATE_NOLINK_))	
+		rtw_write16(Adapter, REG_RXFLTMAP2, 0x00);
+	
+
+	if(Adapter->iface_type == IFACE_PORT1)
+	{
+		//reset TSF1
+		rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(1));
+
+		//disable update TSF1
+		rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(4));
+	}
+	else
+	{
+		//reset TSF
+		rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(0));
+
+		//disable update TSF
+		rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4));
+	}
+#endif
+}
+
+static void hw_var_set_mlme_sitesurvey(PADAPTER Adapter, u8 variable, u8* val)
+{	
+#ifdef CONFIG_CONCURRENT_MODE	
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+
+	struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
+	struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+
+	if(*((u8 *)val))//under sitesurvey
+	{
+		//config RCR to receive different BSSID & not to receive data frame
+		u32 v = rtw_read32(Adapter, REG_RCR);
+		v &= ~(RCR_CBSSID_BCN);
+		rtw_write32(Adapter, REG_RCR, v);
+
+		//disable update TSF
+		if((pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE)
+		{
+			if(Adapter->iface_type == IFACE_PORT1)
+			{
+				rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(4));
+			}
+			else
+			{
+				rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4));
+			}				
+		}
+				
+		if(check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE) &&
+			check_buddy_fwstate(Adapter, _FW_LINKED))		
+		{
+			StopTxBeacon(Adapter);
+		}
+	}
+	else//sitesurvey done
+	{
+		//enable to rx data frame
+		//write32(Adapter, REG_RCR, read32(padapter, REG_RCR)|RCR_ADF);
+		rtw_write16(Adapter, REG_RXFLTMAP2,0xFFFF);
+
+		//enable update TSF
+		if(Adapter->iface_type == IFACE_PORT1)
+			rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)&(~BIT(4)));
+		else
+			rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4)));
+
+		rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_BCN);
+					
+		if(check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE) &&
+			check_buddy_fwstate(Adapter, _FW_LINKED))
+		{
+			ResumeTxBeacon(Adapter);			
+		}
+	}
+#endif			
+}
+
+static void hw_var_set_mlme_join(PADAPTER Adapter, u8 variable, u8* val)
+{
+#ifdef CONFIG_CONCURRENT_MODE
+	u8	RetryLimit = 0x30;
+	u8	type = *((u8 *)val);
+	HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+	struct mlme_priv	*pmlmepriv = &Adapter->mlmepriv;
+
+	if(type == 0) // prepare to join
+	{		
+		if(check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE) &&
+			check_buddy_fwstate(Adapter, _FW_LINKED))		
+		{
+			StopTxBeacon(Adapter);
+		}
+	
+		//enable to rx data frame.Accept all data frame
+		//rtw_write32(padapter, REG_RCR, rtw_read32(padapter, REG_RCR)|RCR_ADF);
+		rtw_write16(Adapter, REG_RXFLTMAP2,0xFFFF);
+
+		if(check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE))
+			rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_BCN);
+		else
+			rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_DATA|RCR_CBSSID_BCN);
+
+		if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)
+		{
+			RetryLimit = (pHalData->CustomerID == RT_CID_CCX) ? 7 : 48;
+		}
+		else // Ad-hoc Mode
+		{
+			RetryLimit = 0x7;
+		}
+	}
+	else if(type == 1) //joinbss_event call back when join res < 0
+	{		
+		if(check_buddy_mlmeinfo_state(Adapter, _HW_STATE_NOLINK_))		
+			rtw_write16(Adapter, REG_RXFLTMAP2,0x00);
+
+		if(check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE) &&
+			check_buddy_fwstate(Adapter, _FW_LINKED))
+		{
+			ResumeTxBeacon(Adapter);			
+			
+			//reset TSF 1/2 after ResumeTxBeacon
+			rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(1)|BIT(0));	
+			
+		}
+	}
+	else if(type == 2) //sta add event call back
+	{
+	 
+		//enable update TSF
+		if(Adapter->iface_type == IFACE_PORT1)
+			rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)&(~BIT(4)));
+		else
+			rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4)));
+		 
+	
+		if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE))
+		{
+			//fixed beacon issue for 8191su...........
+			rtw_write8(Adapter,0x542 ,0x02);
+			RetryLimit = 0x7;
+		}
+
+
+		if(check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE) &&
+			check_buddy_fwstate(Adapter, _FW_LINKED))
+		{
+			ResumeTxBeacon(Adapter);			
+			
+			//reset TSF 1/2 after ResumeTxBeacon
+			rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(1)|BIT(0));
+		}
+		
+	}
+
+	rtw_write16(Adapter, REG_RL, RetryLimit << RETRY_LIMIT_SHORT_SHIFT | RetryLimit << RETRY_LIMIT_LONG_SHIFT);
+	
+#endif
+}
+
+void SetHwReg8188EU(PADAPTER Adapter, u8 variable, u8* val)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
+	struct dm_priv	*pdmpriv = &pHalData->dmpriv;
+	DM_ODM_T 		*podmpriv = &pHalData->odmpriv;
+_func_enter_;
+
+	switch(variable)
+	{
+		case HW_VAR_MEDIA_STATUS:
+			{
+				u8 val8;
+
+				val8 = rtw_read8(Adapter, MSR)&0x0c;
+				val8 |= *((u8 *)val);
+				rtw_write8(Adapter, MSR, val8);
+			}
+			break;
+		case HW_VAR_MEDIA_STATUS1:
+			{
+				u8 val8;
+				
+				val8 = rtw_read8(Adapter, MSR)&0x03;
+				val8 |= *((u8 *)val) <<2;
+				rtw_write8(Adapter, MSR, val8);
+			}
+			break;
+		case HW_VAR_SET_OPMODE:
+			hw_var_set_opmode(Adapter, variable, val);
+			break;
+		case HW_VAR_MAC_ADDR:
+			hw_var_set_macaddr(Adapter, variable, val);			
+			break;
+		case HW_VAR_BSSID:
+			hw_var_set_bssid(Adapter, variable, val);
+			break;
+		case HW_VAR_BASIC_RATE:
+			{
+				u16			BrateCfg = 0;
+				u8			RateIndex = 0;
+
+				// 2007.01.16, by Emily
+				// Select RRSR (in Legacy-OFDM and CCK)
+				// For 8190, we select only 24M, 12M, 6M, 11M, 5.5M, 2M, and 1M from the Basic rate.
+				// We do not use other rates.
+				HalSetBrateCfg( Adapter, val, &BrateCfg );
+				DBG_8192C("HW_VAR_BASIC_RATE: BrateCfg(%#x)\n", BrateCfg);
+
+				//2011.03.30 add by Luke Lee
+				//CCK 2M ACK should be disabled for some BCM and Atheros AP IOT
+				//because CCK 2M has poor TXEVM
+				//CCK 5.5M & 11M ACK should be enabled for better performance
+
+				pHalData->BasicRateSet = BrateCfg = (BrateCfg |0xd) & 0x15d;
+
+				BrateCfg |= 0x01; // default enable 1M ACK rate
+				// Set RRSR rate table.
+				rtw_write8(Adapter, REG_RRSR, BrateCfg&0xff);
+				rtw_write8(Adapter, REG_RRSR+1, (BrateCfg>>8)&0xff);
+				rtw_write8(Adapter, REG_RRSR+2, rtw_read8(Adapter, REG_RRSR+2)&0xf0);
+
+				// Set RTS initial rate
+				while(BrateCfg > 0x1)
+				{
+					BrateCfg = (BrateCfg>> 1);
+					RateIndex++;
+				}
+				// Ziv - Check
+				rtw_write8(Adapter, REG_INIRTS_RATE_SEL, RateIndex);
+			}
+			break;
+		case HW_VAR_TXPAUSE:
+			rtw_write8(Adapter, REG_TXPAUSE, *((u8 *)val));	
+			break;
+		case HW_VAR_BCN_FUNC:
+			hw_var_set_bcn_func(Adapter, variable, val);
+			break;
+		case HW_VAR_CORRECT_TSF:
+#ifdef CONFIG_CONCURRENT_MODE
+			hw_var_set_correct_tsf(Adapter, variable, val);
+#else			
+			{
+				u64	tsf;
+				struct mlme_ext_priv	*pmlmeext = &Adapter->mlmeextpriv;
+				struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+				//tsf = pmlmeext->TSFValue - ((u32)pmlmeext->TSFValue % (pmlmeinfo->bcn_interval*1024)) -1024; //us
+				tsf = pmlmeext->TSFValue - rtw_modular64(pmlmeext->TSFValue, (pmlmeinfo->bcn_interval*1024)) -1024; //us
+
+				if(((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE))
+				{				
+					//pHalData->RegTxPause |= STOP_BCNQ;BIT(6)
+					//rtw_write8(Adapter, REG_TXPAUSE, (rtw_read8(Adapter, REG_TXPAUSE)|BIT(6)));
+					StopTxBeacon(Adapter);
+				}
+
+				//disable related TSF function
+				rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(3)));
+							
+				rtw_write32(Adapter, REG_TSFTR, tsf);
+				rtw_write32(Adapter, REG_TSFTR+4, tsf>>32);
+
+				//enable related TSF function
+				rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(3));
+				
+							
+				if(((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE))
+				{
+					//pHalData->RegTxPause  &= (~STOP_BCNQ);
+					//rtw_write8(Adapter, REG_TXPAUSE, (rtw_read8(Adapter, REG_TXPAUSE)&(~BIT(6))));
+					ResumeTxBeacon(Adapter);
+				}
+			}
+#endif
+			break;
+		case HW_VAR_CHECK_BSSID:
+			if(*((u8 *)val))
+			{ 
+				rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_DATA|RCR_CBSSID_BCN); 
+			}
+			else
+			{
+				u32	val32;
+
+				val32 = rtw_read32(Adapter, REG_RCR);
+ 
+				val32 &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);
+
+				rtw_write32(Adapter, REG_RCR, val32);
+			}
+			break;
+		case HW_VAR_MLME_DISCONNECT:
+#ifdef CONFIG_CONCURRENT_MODE
+			hw_var_set_mlme_disconnect(Adapter, variable, val);
+#else
+			{
+				//Set RCR to not to receive data frame when NO LINK state
+				//rtw_write32(Adapter, REG_RCR, rtw_read32(padapter, REG_RCR) & ~RCR_ADF);
+				//reject all data frames
+				rtw_write16(Adapter, REG_RXFLTMAP2,0x00);
+
+				//reset TSF
+				rtw_write8(Adapter, REG_DUAL_TSF_RST, (BIT(0)|BIT(1)));
+
+				//disable update TSF
+				rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4));	
+			}
+#endif
+			break;
+		case HW_VAR_MLME_SITESURVEY:
+#ifdef CONFIG_CONCURRENT_MODE
+			hw_var_set_mlme_sitesurvey(Adapter, variable,  val);
+#else
+			if(*((u8 *)val))//under sitesurvey
+			{
+				//config RCR to receive different BSSID & not to receive data frame
+				u32 v = rtw_read32(Adapter, REG_RCR);
+				v &= ~(RCR_CBSSID_BCN);
+				rtw_write32(Adapter, REG_RCR, v);
+				//reject all data frame
+				rtw_write16(Adapter, REG_RXFLTMAP2,0x00);
+
+				//disable update TSF
+				rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4));
+			}
+			else//sitesurvey done
+			{
+				struct mlme_ext_priv	*pmlmeext = &Adapter->mlmeextpriv;
+				struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+
+				if ((is_client_associated_to_ap(Adapter) == _TRUE) ||
+					((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) )
+				{
+					//enable to rx data frame
+					//rtw_write32(Adapter, REG_RCR, rtw_read32(padapter, REG_RCR)|RCR_ADF);
+					rtw_write16(Adapter, REG_RXFLTMAP2,0xFFFF);
+
+					//enable update TSF
+					rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4)));
+				}
+				else if((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)
+				{
+					//rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_ADF);
+					rtw_write16(Adapter, REG_RXFLTMAP2,0xFFFF);
+
+					//enable update TSF
+					rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4)));
+				}
+
+				if((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)
+					rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_BCN);
+				else
+				{
+					if(Adapter->in_cta_test)
+					{
+						u32 v = rtw_read32(Adapter, REG_RCR);
+						v &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN );//| RCR_ADF
+						rtw_write32(Adapter, REG_RCR, v);
+					}
+					else
+					{
+						rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_BCN);
+					}
+				}
+			}
+#endif			
+			break;
+		case HW_VAR_MLME_JOIN:
+#ifdef CONFIG_CONCURRENT_MODE
+			hw_var_set_mlme_join(Adapter, variable,  val);
+#else
+			{
+				u8	RetryLimit = 0x30;
+				u8	type = *((u8 *)val);
+				struct mlme_priv	*pmlmepriv = &Adapter->mlmepriv;
+				
+				if(type == 0) // prepare to join
+				{
+					//enable to rx data frame.Accept all data frame
+					//rtw_write32(padapter, REG_RCR, rtw_read32(padapter, REG_RCR)|RCR_ADF);
+					rtw_write16(Adapter, REG_RXFLTMAP2,0xFFFF);
+
+					if(Adapter->in_cta_test)
+					{
+						u32 v = rtw_read32(Adapter, REG_RCR);
+						v &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN );//| RCR_ADF
+						rtw_write32(Adapter, REG_RCR, v);
+					}
+					else
+					{
+						rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_DATA|RCR_CBSSID_BCN);
+					}
+
+					if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)
+					{
+						RetryLimit = (pHalData->CustomerID == RT_CID_CCX) ? 7 : 48;
+					}
+					else // Ad-hoc Mode
+					{
+						RetryLimit = 0x7;
+					}
+				}
+				else if(type == 1) //joinbss_event call back when join res < 0
+				{
+					rtw_write16(Adapter, REG_RXFLTMAP2,0x00);
+				}
+				else if(type == 2) //sta add event call back
+				{
+					//enable update TSF
+					rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4)));
+
+					if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE))
+					{
+						RetryLimit = 0x7;
+					}
+				}
+
+				rtw_write16(Adapter, REG_RL, RetryLimit << RETRY_LIMIT_SHORT_SHIFT | RetryLimit << RETRY_LIMIT_LONG_SHIFT);
+			}
+#endif
+			break;
+		case HW_VAR_ON_RCR_AM:
+                        rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_AM);
+                        DBG_871X("%s, %d, RCR= %x \n", __FUNCTION__,__LINE__, rtw_read32(Adapter, REG_RCR));
+                        break;
+              case HW_VAR_OFF_RCR_AM:
+                        rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)& (~RCR_AM));
+                        DBG_871X("%s, %d, RCR= %x \n", __FUNCTION__,__LINE__, rtw_read32(Adapter, REG_RCR));
+                        break;
+		case HW_VAR_BEACON_INTERVAL:
+			rtw_write16(Adapter, REG_BCN_INTERVAL, *((u16 *)val));
+#ifdef  CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
+			{
+				struct mlme_ext_priv	*pmlmeext = &Adapter->mlmeextpriv;
+				struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+				u16 bcn_interval = 	*((u16 *)val);
+				if((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE){
+					DBG_8192C("%s==> bcn_interval:%d, eraly_int:%d \n",__FUNCTION__,bcn_interval,bcn_interval>>1);
+					rtw_write8(Adapter, REG_DRVERLYINT, bcn_interval>>1);// 50ms for sdio 
+				}			
+			}
+#endif//CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
+
+			break;
+		case HW_VAR_SLOT_TIME:
+			{
+				u8	u1bAIFS, aSifsTime;
+				struct mlme_ext_priv	*pmlmeext = &Adapter->mlmeextpriv;
+				struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+				
+				rtw_write8(Adapter, REG_SLOT, val[0]);
+
+				if(pmlmeinfo->WMM_enable == 0)
+				{
+					if( pmlmeext->cur_wireless_mode == WIRELESS_11B)
+						aSifsTime = 10;
+					else
+						aSifsTime = 16;
+					
+					u1bAIFS = aSifsTime + (2 * pmlmeinfo->slotTime);
+					
+					// <Roger_EXP> Temporary removed, 2008.06.20.
+					rtw_write8(Adapter, REG_EDCA_VO_PARAM, u1bAIFS);
+					rtw_write8(Adapter, REG_EDCA_VI_PARAM, u1bAIFS);
+					rtw_write8(Adapter, REG_EDCA_BE_PARAM, u1bAIFS);
+					rtw_write8(Adapter, REG_EDCA_BK_PARAM, u1bAIFS);
+				}
+			}
+			break;
+		case HW_VAR_RESP_SIFS:
+			{
+#if 0				
+				// SIFS for OFDM Data ACK
+				rtw_write8(Adapter, REG_SIFS_CTX+1, val[0]);
+				// SIFS for OFDM consecutive tx like CTS data!
+				rtw_write8(Adapter, REG_SIFS_TRX+1, val[1]);
+				
+				rtw_write8(Adapter,REG_SPEC_SIFS+1, val[0]);
+				rtw_write8(Adapter,REG_MAC_SPEC_SIFS+1, val[0]);
+
+				// 20100719 Joseph: Revise SIFS setting due to Hardware register definition change.
+				rtw_write8(Adapter, REG_R2T_SIFS+1, val[0]);
+				rtw_write8(Adapter, REG_T2T_SIFS+1, val[0]);
+#else
+
+				//SIFS_Timer = 0x0a0a0808;
+				//RESP_SIFS for CCK
+				rtw_write8(Adapter, REG_R2T_SIFS, val[0]); // SIFS_T2T_CCK (0x08)
+				rtw_write8(Adapter, REG_R2T_SIFS+1, val[1]); //SIFS_R2T_CCK(0x08)
+				//RESP_SIFS for OFDM
+				rtw_write8(Adapter, REG_T2T_SIFS, val[2]); //SIFS_T2T_OFDM (0x0a)
+				rtw_write8(Adapter, REG_T2T_SIFS+1, val[3]); //SIFS_R2T_OFDM(0x0a)
+#endif				
+			}
+			break;
+		case HW_VAR_ACK_PREAMBLE:
+			{
+				u8	regTmp;
+				u8	bShortPreamble = *( (PBOOLEAN)val );
+				// Joseph marked out for Netgear 3500 TKIP channel 7 issue.(Temporarily)
+				regTmp = (pHalData->nCur40MhzPrimeSC)<<5;
+				//regTmp = 0;
+				if(bShortPreamble)
+					regTmp |= 0x80;
+
+				rtw_write8(Adapter, REG_RRSR+2, regTmp);
+			}
+			break;
+		case HW_VAR_SEC_CFG:
+#ifdef CONFIG_CONCURRENT_MODE
+			rtw_write8(Adapter, REG_SECCFG, 0x0c|BIT(5));// enable tx enc and rx dec engine, and no key search for MC/BC				
+#else
+			rtw_write8(Adapter, REG_SECCFG, *((u8 *)val));
+#endif
+			break;
+		case HW_VAR_DM_FLAG:
+			podmpriv->SupportAbility = *((u8 *)val);
+			break;
+		case HW_VAR_DM_FUNC_OP:
+			if(val[0])
+			{// save dm flag
+				podmpriv->BK_SupportAbility = podmpriv->SupportAbility;				
+			}
+			else
+			{// restore dm flag
+				podmpriv->SupportAbility = podmpriv->BK_SupportAbility;
+			}
+			break;
+		case HW_VAR_DM_FUNC_SET:
+			if(*((u32 *)val) == DYNAMIC_ALL_FUNC_ENABLE){
+				pdmpriv->DMFlag = pdmpriv->InitDMFlag;
+				podmpriv->SupportAbility = 	pdmpriv->InitODMFlag;
+			}
+			else{
+				podmpriv->SupportAbility |= *((u32 *)val);
+			}
+			break;
+		case HW_VAR_DM_FUNC_CLR:
+			podmpriv->SupportAbility &= *((u32 *)val);
+			break;
+
+		case HW_VAR_CAM_EMPTY_ENTRY:
+			{
+				u8	ucIndex = *((u8 *)val);
+				u8	i;
+				u32	ulCommand=0;
+				u32	ulContent=0;
+				u32	ulEncAlgo=CAM_AES;
+
+				for(i=0;i<CAM_CONTENT_COUNT;i++)
+				{
+					// filled id in CAM config 2 byte
+					if( i == 0)
+					{
+						ulContent |=(ucIndex & 0x03) | ((u16)(ulEncAlgo)<<2);
+						//ulContent |= CAM_VALID;
+					}
+					else
+					{
+						ulContent = 0;
+					}
+					// polling bit, and No Write enable, and address
+					ulCommand= CAM_CONTENT_COUNT*ucIndex+i;
+					ulCommand= ulCommand | CAM_POLLINIG|CAM_WRITE;
+					// write content 0 is equall to mark invalid
+					rtw_write32(Adapter, WCAMI, ulContent);  //delay_ms(40);
+					//RT_TRACE(COMP_SEC, DBG_LOUD, ("CAM_empty_entry(): WRITE A4: %lx \n",ulContent));
+					rtw_write32(Adapter, RWCAM, ulCommand);  //delay_ms(40);
+					//RT_TRACE(COMP_SEC, DBG_LOUD, ("CAM_empty_entry(): WRITE A0: %lx \n",ulCommand));
+				}
+			}
+			break;
+		case HW_VAR_CAM_INVALID_ALL:
+			rtw_write32(Adapter, RWCAM, BIT(31)|BIT(30));
+			break;
+		case HW_VAR_CAM_WRITE:
+			{
+				u32	cmd;
+				u32	*cam_val = (u32 *)val;
+				rtw_write32(Adapter, WCAMI, cam_val[0]);
+				
+				cmd = CAM_POLLINIG | CAM_WRITE | cam_val[1];
+				rtw_write32(Adapter, RWCAM, cmd);
+			}
+			break;
+		case HW_VAR_AC_PARAM_VO:
+			rtw_write32(Adapter, REG_EDCA_VO_PARAM, ((u32 *)(val))[0]);
+			break;
+		case HW_VAR_AC_PARAM_VI:
+			rtw_write32(Adapter, REG_EDCA_VI_PARAM, ((u32 *)(val))[0]);
+			break;
+		case HW_VAR_AC_PARAM_BE:
+			pHalData->AcParam_BE = ((u32 *)(val))[0];
+			rtw_write32(Adapter, REG_EDCA_BE_PARAM, ((u32 *)(val))[0]);
+			break;
+		case HW_VAR_AC_PARAM_BK:
+			rtw_write32(Adapter, REG_EDCA_BK_PARAM, ((u32 *)(val))[0]);
+			break;
+		case HW_VAR_ACM_CTRL:
+			{
+				u8	acm_ctrl = *((u8 *)val);
+				u8	AcmCtrl = rtw_read8( Adapter, REG_ACMHWCTRL);
+
+				if(acm_ctrl > 1)
+					AcmCtrl = AcmCtrl | 0x1;
+
+				if(acm_ctrl & BIT(3))
+					AcmCtrl |= AcmHw_VoqEn;
+				else
+					AcmCtrl &= (~AcmHw_VoqEn);
+
+				if(acm_ctrl & BIT(2))
+					AcmCtrl |= AcmHw_ViqEn;
+				else
+					AcmCtrl &= (~AcmHw_ViqEn);
+
+				if(acm_ctrl & BIT(1))
+					AcmCtrl |= AcmHw_BeqEn;
+				else
+					AcmCtrl &= (~AcmHw_BeqEn);
+
+				DBG_871X("[HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl );
+				rtw_write8(Adapter, REG_ACMHWCTRL, AcmCtrl );
+			}
+			break;
+		case HW_VAR_AMPDU_MIN_SPACE:
+			{
+				u8	MinSpacingToSet;
+				u8	SecMinSpace;
+
+				MinSpacingToSet = *((u8 *)val);
+				if(MinSpacingToSet <= 7)
+				{
+					switch(Adapter->securitypriv.dot11PrivacyAlgrthm)
+					{
+						case _NO_PRIVACY_:
+						case _AES_:
+							SecMinSpace = 0;
+							break;
+
+						case _WEP40_:
+						case _WEP104_:
+						case _TKIP_:
+						case _TKIP_WTMIC_:
+							SecMinSpace = 6;
+							break;
+						default:
+							SecMinSpace = 7;
+							break;
+					}
+
+					if(MinSpacingToSet < SecMinSpace){
+						MinSpacingToSet = SecMinSpace;
+					}
+
+					//RT_TRACE(COMP_MLME, DBG_LOUD, ("Set HW_VAR_AMPDU_MIN_SPACE: %#x\n", Adapter->MgntInfo.MinSpaceCfg));
+					rtw_write8(Adapter, REG_AMPDU_MIN_SPACE, (rtw_read8(Adapter, REG_AMPDU_MIN_SPACE) & 0xf8) | MinSpacingToSet);
+				}
+			}
+			break;
+		case HW_VAR_AMPDU_FACTOR:
+			{
+				u8	RegToSet_Normal[4]={0x41,0xa8,0x72, 0xb9};
+				u8	RegToSet_BT[4]={0x31,0x74,0x42, 0x97};
+				u8	FactorToSet;
+				u8	*pRegToSet;
+				u8	index = 0;
+
+#ifdef CONFIG_BT_COEXIST
+				if(	(pHalData->bt_coexist.BT_Coexist) &&
+					(pHalData->bt_coexist.BT_CoexistType == BT_CSR_BC4) )
+					pRegToSet = RegToSet_BT; // 0x97427431;
+				else
+#endif
+					pRegToSet = RegToSet_Normal; // 0xb972a841;
+
+				FactorToSet = *((u8 *)val);
+				if(FactorToSet <= 3)
+				{
+					FactorToSet = (1<<(FactorToSet + 2));
+					if(FactorToSet>0xf)
+						FactorToSet = 0xf;
+
+					for(index=0; index<4; index++)
+					{
+						if((pRegToSet[index] & 0xf0) > (FactorToSet<<4))
+							pRegToSet[index] = (pRegToSet[index] & 0x0f) | (FactorToSet<<4);
+					
+						if((pRegToSet[index] & 0x0f) > FactorToSet)
+							pRegToSet[index] = (pRegToSet[index] & 0xf0) | (FactorToSet);
+						
+						rtw_write8(Adapter, (REG_AGGLEN_LMT+index), pRegToSet[index]);
+					}
+
+					//RT_TRACE(COMP_MLME, DBG_LOUD, ("Set HW_VAR_AMPDU_FACTOR: %#x\n", FactorToSet));
+				}
+			}
+			break;
+		case HW_VAR_RXDMA_AGG_PG_TH:
+			#ifdef CONFIG_USB_RX_AGGREGATION
+			{
+				u8	threshold = *((u8 *)val);
+				if( threshold == 0)
+				{
+					threshold = pHalData->UsbRxAggPageCount;
+				}
+				rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, threshold);
+			}
+			#endif
+			break;
+		case HW_VAR_SET_RPWM:
+#ifdef CONFIG_LPS_LCLK
+			{
+				u8	ps_state = *((u8 *)val);
+				//rpwm value only use BIT0(clock bit) ,BIT6(Ack bit), and BIT7(Toggle bit) for 88e.
+				//BIT0 value - 1: 32k, 0:40MHz.
+				//BIT6 value - 1: report cpwm value after success set, 0:do not report.
+				//BIT7 value - Toggle bit change.
+				//modify by Thomas. 2012/4/2.
+				ps_state = ps_state & 0xC1;
+				//DBG_871X("##### Change RPWM value to = %x for switch clk #####\n",ps_state);
+				rtw_write8(Adapter, REG_USB_HRPWM, ps_state);
+			}
+#endif
+			break;
+		case HW_VAR_H2C_FW_PWRMODE:
+			{
+				u8	psmode = (*(u8 *)val);
+			
+				// Forece leave RF low power mode for 1T1R to prevent conficting setting in Fw power
+				// saving sequence. 2010.06.07. Added by tynli. Suggested by SD3 yschang.
+				if( (psmode != PS_MODE_ACTIVE) && (!IS_92C_SERIAL(pHalData->VersionID)))
+				{
+					ODM_RF_Saving(podmpriv, _TRUE);
+				}
+				rtl8188e_set_FwPwrMode_cmd(Adapter, psmode);
+			}
+			break;
+		case HW_VAR_H2C_FW_JOINBSSRPT:
+		    {
+				u8	mstatus = (*(u8 *)val);
+				rtl8188e_set_FwJoinBssReport_cmd(Adapter, mstatus);
+			}
+			break;
+#ifdef CONFIG_P2P_PS
+		case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
+			{
+				u8	p2p_ps_state = (*(u8 *)val);
+				rtl8188e_set_p2p_ps_offload_cmd(Adapter, p2p_ps_state);
+			}
+			break;
+#endif //CONFIG_P2P_PS
+#ifdef CONFIG_TDLS
+		case HW_VAR_TDLS_WRCR:
+			rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)&(~RCR_CBSSID_DATA ));
+			break;
+		case HW_VAR_TDLS_INIT_CH_SEN:
+			{
+				rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)&(~ RCR_CBSSID_DATA )&(~RCR_CBSSID_BCN ));
+				rtw_write16(Adapter, REG_RXFLTMAP2,0xffff);
+
+				//disable update TSF
+				rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4));
+			}
+			break;
+		case HW_VAR_TDLS_DONE_CH_SEN:
+			{
+				//enable update TSF
+				rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~ BIT(4)));
+				rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|(RCR_CBSSID_BCN ));
+			}
+			break;
+		case HW_VAR_TDLS_RS_RCR:
+			rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|(RCR_CBSSID_DATA));
+			break;
+#endif //CONFIG_TDLS
+		case HW_VAR_INITIAL_GAIN:
+			{				
+				DIG_T	*pDigTable = &podmpriv->DM_DigTable;					
+				u32 		rx_gain = ((u32 *)(val))[0];
+		
+				if(rx_gain == 0xff){//restore rx gain					
+					ODM_Write_DIG(podmpriv,pDigTable->BackupIGValue);
+				}
+				else{
+					pDigTable->BackupIGValue = pDigTable->CurIGValue;
+					ODM_Write_DIG(podmpriv,rx_gain);
+				}
+			}
+			break;
+		case HW_VAR_TRIGGER_GPIO_0:
+			rtl8192cu_trigger_gpio_0(Adapter);
+			break;
+#ifdef CONFIG_BT_COEXIST
+		case HW_VAR_BT_SET_COEXIST:
+			{
+				u8	bStart = (*(u8 *)val);
+				rtl8192c_set_dm_bt_coexist(Adapter, bStart);
+			}
+			break;
+		case HW_VAR_BT_ISSUE_DELBA:
+			{
+				u8	dir = (*(u8 *)val);
+				rtl8192c_issue_delete_ba(Adapter, dir);
+			}
+			break;
+#endif
+#if (RATE_ADAPTIVE_SUPPORT==1)
+		case HW_VAR_RPT_TIMER_SETTING:
+			{
+				u16	min_rpt_time = (*(u16 *)val);
+				ODM_RA_Set_TxRPT_Time(podmpriv,min_rpt_time);	
+			}
+			break;
+#endif
+#ifdef CONFIG_SW_ANTENNA_DIVERSITY
+
+		case HW_VAR_ANTENNA_DIVERSITY_LINK:
+			//odm_SwAntDivRestAfterLink8192C(Adapter);
+			ODM_SwAntDivRestAfterLink(podmpriv);
+			break;
+#endif			
+#ifdef CONFIG_ANTENNA_DIVERSITY
+		case HW_VAR_ANTENNA_DIVERSITY_SELECT:
+			{
+				u8	Optimum_antenna = (*(u8 *)val);
+				u8 	Ant ; 
+				//switch antenna to Optimum_antenna
+				//DBG_8192C("==> HW_VAR_ANTENNA_DIVERSITY_SELECT , Ant_(%s)\n",(Optimum_antenna==2)?"A":"B");
+				if(pHalData->CurAntenna !=  Optimum_antenna)		
+				{					
+					Ant = (Optimum_antenna==2)?MAIN_ANT:AUX_ANT;
+					ODM_UpdateRxIdleAnt_88E(&pHalData->odmpriv, Ant);
+					
+					pHalData->CurAntenna = Optimum_antenna ;
+					//DBG_8192C("==> HW_VAR_ANTENNA_DIVERSITY_SELECT , Ant_(%s)\n",(Optimum_antenna==2)?"A":"B");
+				}
+			}
+			break;
+#endif
+		case HW_VAR_EFUSE_BYTES: // To set EFUE total used bytes, added by Roger, 2008.12.22.
+			pHalData->EfuseUsedBytes = *((u16 *)val);			
+			break;
+		case HW_VAR_FIFO_CLEARN_UP:
+			{				
+				struct pwrctrl_priv *pwrpriv = &Adapter->pwrctrlpriv;
+				u8 trycnt = 100;	
+				
+				//pause tx
+				rtw_write8(Adapter,REG_TXPAUSE,0xff);
+			
+				//keep sn
+				Adapter->xmitpriv.nqos_ssn = rtw_read16(Adapter,REG_NQOS_SEQ);
+
+				if(pwrpriv->bkeepfwalive != _TRUE)
+				{
+					//RX DMA stop
+					rtw_write32(Adapter,REG_RXPKT_NUM,(rtw_read32(Adapter,REG_RXPKT_NUM)|RW_RELEASE_EN));
+					do{
+						if(!(rtw_read32(Adapter,REG_RXPKT_NUM)&RXDMA_IDLE))
+							break;
+					}while(trycnt--);
+					if(trycnt ==0)
+						DBG_8192C("Stop RX DMA failed...... \n");
+
+					//RQPN Load 0
+					rtw_write16(Adapter,REG_RQPN_NPQ,0x0);
+					rtw_write32(Adapter,REG_RQPN,0x80000000);
+					rtw_mdelay_os(10);
+				}
+			}
+			break;
+		case HW_VAR_CHECK_TXBUF:
+#ifdef CONFIG_CONCURRENT_MODE				
+			{
+				int i;
+				u8	RetryLimit = 0x01;
+				
+				rtw_write16(Adapter, REG_RL, RetryLimit << RETRY_LIMIT_SHORT_SHIFT | RetryLimit << RETRY_LIMIT_LONG_SHIFT);
+		
+				for(i=0;i<1000;i++)
+				{
+					if(rtw_read32(Adapter, 0x200) != rtw_read32(Adapter, 0x204))
+					{
+						//DBG_871X("packet in tx packet buffer - 0x204=%x, 0x200=%x (%d)\n", rtw_read32(Adapter, 0x204), rtw_read32(Adapter, 0x200), i);
+						rtw_msleep_os(10);
+					}
+					else
+					{
+						DBG_871X("no packet in tx packet buffer (%d)\n", i);
+						break;
+					}
+				}
+
+				RetryLimit = 0x30;	
+				rtw_write16(Adapter, REG_RL, RetryLimit << RETRY_LIMIT_SHORT_SHIFT | RetryLimit << RETRY_LIMIT_LONG_SHIFT);
+		
+			}
+#endif
+			break;
+
+	case HW_VAR_APFM_ON_MAC:
+			pHalData->bMacPwrCtrlOn = *val;
+			DBG_871X("%s: bMacPwrCtrlOn=%d\n", __func__, pHalData->bMacPwrCtrlOn);
+			break;
+
+#ifdef CONFIG_WOWLAN
+		case HW_VAR_WOWLAN:
+		{
+			struct wowlan_ioctl_param *poidparam;
+			struct recv_buf *precvbuf;
+			int res, i;
+			u32 tmp;
+			u16 len = 0;
+			u8 mstatus = (*(u8 *)val);
+			u8 trycnt = 100;
+			u8 data[4];
+
+			poidparam = (struct wowlan_ioctl_param *)val;
+			switch (poidparam->subcode){
+				case WOWLAN_ENABLE:
+					DBG_871X_LEVEL(_drv_always_, "WOWLAN_ENABLE\n");
+
+					SetFwRelatedForWoWLAN8188ES(Adapter, _TRUE);
+
+					//Set Pattern
+					//if(Adapter->pwrctrlpriv.wowlan_pattern==_TRUE)
+					//	rtw_wowlan_reload_pattern(Adapter);
+
+					//RX DMA stop
+					DBG_871X_LEVEL(_drv_always_, "Pause DMA\n");
+					rtw_write32(Adapter,REG_RXPKT_NUM,(rtw_read32(Adapter,REG_RXPKT_NUM)|RW_RELEASE_EN));
+					do{
+						if((rtw_read32(Adapter, REG_RXPKT_NUM)&RXDMA_IDLE)) {
+							DBG_871X_LEVEL(_drv_always_, "RX_DMA_IDLE is true\n");
+							break;
+						} else {
+							// If RX_DMA is not idle, receive one pkt from DMA
+							DBG_871X_LEVEL(_drv_always_, "RX_DMA_IDLE is not true\n");
+						}
+					}while(trycnt--);
+					if(trycnt ==0)
+						DBG_871X_LEVEL(_drv_always_, "Stop RX DMA failed...... \n");
+
+					//Set WOWLAN H2C command.
+					DBG_871X_LEVEL(_drv_always_, "Set WOWLan cmd\n");
+					rtl8188es_set_wowlan_cmd(Adapter, 1);
+
+					mstatus = rtw_read8(Adapter, REG_WOW_CTRL);
+					trycnt = 10;
+
+					while(!(mstatus&BIT1) && trycnt>1) {
+						mstatus = rtw_read8(Adapter, REG_WOW_CTRL);
+						DBG_871X_LEVEL(_drv_always_, "Loop index: %d :0x%02x\n", trycnt, mstatus);
+						trycnt --;
+						rtw_msleep_os(2);
+					}
+
+					Adapter->pwrctrlpriv.wowlan_wake_reason = rtw_read8(Adapter, REG_WOWLAN_WAKE_REASON);
+					DBG_871X_LEVEL(_drv_always_, "wowlan_wake_reason: 0x%02x\n",
+										Adapter->pwrctrlpriv.wowlan_wake_reason);
+
+					/* Invoid SE0 reset signal during suspending*/
+					rtw_write8(Adapter, REG_RSV_CTRL, 0x20);
+					rtw_write8(Adapter, REG_RSV_CTRL, 0x60);
+
+					//rtw_msleep_os(10);
+					break;
+				case WOWLAN_DISABLE:
+					DBG_871X_LEVEL(_drv_always_, "WOWLAN_DISABLE\n");
+					trycnt = 10;
+					rtl8188es_set_wowlan_cmd(Adapter, 0);
+					mstatus = rtw_read8(Adapter, REG_WOW_CTRL);
+					DBG_871X_LEVEL(_drv_info_, "%s mstatus:0x%02x\n", __func__, mstatus);
+
+					while(mstatus&BIT1 && trycnt>1) {
+						mstatus = rtw_read8(Adapter, REG_WOW_CTRL);
+						DBG_871X_LEVEL(_drv_always_, "Loop index: %d :0x%02x\n", trycnt, mstatus);
+						trycnt --;
+						rtw_msleep_os(2);
+					}
+
+					if (mstatus & BIT1)
+						printk("System did not release RX_DMA\n");
+					else
+						SetFwRelatedForWoWLAN8188ES(Adapter, _FALSE);
+
+					rtw_msleep_os(2);
+					if(!(Adapter->pwrctrlpriv.wowlan_wake_reason & FWDecisionDisconnect))
+						rtl8188e_set_FwJoinBssReport_cmd(Adapter, 1);
+					//rtw_msleep_os(10);
+					break;
+				default:
+					break;
+			}
+		}
+		break;
+#endif //CONFIG_WOWLAN
+
+
+	#if (RATE_ADAPTIVE_SUPPORT == 1)
+		case HW_VAR_TX_RPT_MAX_MACID:
+			{
+				u8 maxMacid = *val;
+				DBG_871X("### MacID(%d),Set Max Tx RPT MID(%d)\n",maxMacid,maxMacid+1);
+				rtw_write8(Adapter, REG_TX_RPT_CTRL+1, maxMacid+1);
+			}
+			break;
+	#endif		
+		case HW_VAR_H2C_MEDIA_STATUS_RPT:
+			{				
+				rtl8188e_set_FwMediaStatus_cmd(Adapter , (*(u16 *)val));
+			}
+			break;
+		case HW_VAR_BCN_VALID:
+			//BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2, write 1 to clear, Clear by sw
+			rtw_write8(Adapter, REG_TDECTRL+2, rtw_read8(Adapter, REG_TDECTRL+2) | BIT0); 
+			break;
+		default:
+			
+			break;
+	}
+
+_func_exit_;
+}
+
+void GetHwReg8188EU(PADAPTER Adapter, u8 variable, u8* val)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
+	DM_ODM_T 		*podmpriv = &pHalData->odmpriv;
+_func_enter_;
+
+	switch(variable)
+	{
+		case HW_VAR_BASIC_RATE:
+			*((u16 *)(val)) = pHalData->BasicRateSet;
+		case HW_VAR_TXPAUSE:
+			val[0] = rtw_read8(Adapter, REG_TXPAUSE);
+			break;
+		case HW_VAR_BCN_VALID:
+			//BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2
+			val[0] = (BIT0 & rtw_read8(Adapter, REG_TDECTRL+2))?_TRUE:_FALSE;
+			break;
+		case HW_VAR_DM_FLAG:
+			val[0] = podmpriv->SupportAbility;
+			break;
+		case HW_VAR_RF_TYPE:
+			val[0] = pHalData->rf_type;
+			break;
+		case HW_VAR_FWLPS_RF_ON:
+			{
+				//When we halt NIC, we should check if FW LPS is leave.
+				if(Adapter->pwrctrlpriv.rf_pwrstate == rf_off)
+				{
+					// If it is in HW/SW Radio OFF or IPS state, we do not check Fw LPS Leave,
+					// because Fw is unload.
+					val[0] = _TRUE;
+				}
+				else
+				{
+					u32 valRCR;
+					valRCR = rtw_read32(Adapter, REG_RCR);
+					valRCR &= 0x00070000;
+					if(valRCR)
+						val[0] = _FALSE;
+					else
+						val[0] = _TRUE;
+				}
+			}
+			break;
+#ifdef CONFIG_ANTENNA_DIVERSITY
+		case HW_VAR_CURRENT_ANTENNA:
+			val[0] = pHalData->CurAntenna;
+			break;
+#endif
+		case HW_VAR_EFUSE_BYTES: // To get EFUE total used bytes, added by Roger, 2008.12.22.
+			*((u16 *)(val)) = pHalData->EfuseUsedBytes;	
+			break;
+		case HW_VAR_APFM_ON_MAC:
+			*val = pHalData->bMacPwrCtrlOn;
+			break;
+		case HW_VAR_CHK_HI_QUEUE_EMPTY:
+			*val = ((rtw_read32(Adapter, REG_HGQ_INFORMATION)&0x0000ff00)==0) ? _TRUE:_FALSE;
+			break;
+
+		case HW_VAR_READ_LLT_TAB:
+			{
+				Read_LLT_Tab(Adapter);
+			}
+			break;	
+		default:
+			break;
+	}
+
+_func_exit_;
+}
+
+//
+//	Description: 
+//		Query setting of specified variable.
+//
+u8
+GetHalDefVar8188EUsb(
+	IN	PADAPTER				Adapter,
+	IN	HAL_DEF_VARIABLE		eVariable,
+	IN	PVOID					pValue
+	)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
+	u8			bResult = _SUCCESS;
+
+	switch(eVariable)
+	{
+		case HAL_DEF_UNDERCORATEDSMOOTHEDPWDB:
+#if 1 //trunk
+			{
+				struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
+				struct sta_priv * pstapriv = &Adapter->stapriv;
+				struct sta_info * psta;
+				psta = rtw_get_stainfo(pstapriv, pmlmepriv->cur_network.network.MacAddress);
+				if(psta)
+				{
+					*((int *)pValue) = psta->rssi_stat.UndecoratedSmoothedPWDB;     
+				}
+			}
+#else //V4 branch
+				if(check_fwstate(&Adapter->mlmepriv, WIFI_STATION_STATE) == _TRUE){
+						*((int *)pValue) = pHalData->dmpriv.UndecoratedSmoothedPWDB;
+				}
+				else{
+    
+				}
+#endif
+			break;
+		case HAL_DEF_IS_SUPPORT_ANT_DIV:
+#ifdef CONFIG_ANTENNA_DIVERSITY
+			*((u8 *)pValue) = (pHalData->AntDivCfg==0)?_FALSE:_TRUE;
+#endif
+			break;			
+		case HAL_DEF_CURRENT_ANTENNA:
+#ifdef CONFIG_ANTENNA_DIVERSITY
+			*(( u8*)pValue) = pHalData->CurAntenna;			
+#endif
+			break;
+		case HAL_DEF_DRVINFO_SZ:
+			*(( u32*)pValue) = DRVINFO_SZ;
+			break;
+		case HAL_DEF_MAX_RECVBUF_SZ:
+			*(( u32*)pValue) = MAX_RECVBUF_SZ;
+			break;
+		case HAL_DEF_RX_PACKET_OFFSET:
+			*(( u32*)pValue) = RXDESC_SIZE + DRVINFO_SZ;
+			break;
+		
+		case HAL_DEF_DBG_DM_FUNC:
+			*(( u32*)pValue) =pHalData->odmpriv.SupportAbility;
+			break;
+#if (RATE_ADAPTIVE_SUPPORT == 1)
+		case HAL_DEF_RA_DECISION_RATE:
+			{
+				u8 MacID = *((u8*)pValue);
+				*((u8*)pValue) = ODM_RA_GetDecisionRate_8188E(&(pHalData->odmpriv), MacID);
+			}
+			break;
+
+		case HAL_DEF_RA_SGI:
+			{
+				u8 MacID = *((u8*)pValue);
+				*((u8*)pValue) = ODM_RA_GetShortGI_8188E(&(pHalData->odmpriv), MacID);
+			}
+			break;		
+#endif
+
+ 
+		case HAL_DEF_PT_PWR_STATUS:
+#if(POWER_TRAINING_ACTIVE==1)
+			{
+				u8 MacID = *((u8*)pValue);
+				*((u8*)pValue) = ODM_RA_GetHwPwrStatus_8188E(&(pHalData->odmpriv), MacID);
+			}
+#endif//(POWER_TRAINING_ACTIVE==1)
+			break;		
+
+		case HW_VAR_MAX_RX_AMPDU_FACTOR:
+			*(( u32*)pValue) = MAX_AMPDU_FACTOR_64K;
+			break;
+			
+                case HW_DEF_RA_INFO_DUMP:
+#if (RATE_ADAPTIVE_SUPPORT == 1)	
+			{
+				u8 entry_id = *((u8*)pValue);
+				if(check_fwstate(&Adapter->mlmepriv, _FW_LINKED)== _TRUE)
+				{
+					DBG_871X("============ RA status check ===================\n");
+					DBG_8192C("Mac_id:%d ,RateID = %d,RAUseRate = 0x%08x,RateSGI = %d, DecisionRate = 0x%02x ,PTStage = %d\n",
+						entry_id,
+						pHalData->odmpriv.RAInfo[entry_id].RateID,
+						pHalData->odmpriv.RAInfo[entry_id].RAUseRate,
+						pHalData->odmpriv.RAInfo[entry_id].RateSGI,
+						pHalData->odmpriv.RAInfo[entry_id].DecisionRate,
+						pHalData->odmpriv.RAInfo[entry_id].PTStage);
+				}
+			}
+#endif	//(RATE_ADAPTIVE_SUPPORT == 1)
+			break;
+		case HW_DEF_ODM_DBG_FLAG:
+			{
+				u8Byte	DebugComponents = *((u32*)pValue);	
+				PDM_ODM_T	pDM_Odm = &(pHalData->odmpriv);
+				printk("pDM_Odm->DebugComponents = 0x%llx \n",pDM_Odm->DebugComponents );			
+			}
+			break;
+			
+		case HAL_DEF_DBG_DUMP_RXPKT:
+			*(( u8*)pValue) = pHalData->bDumpRxPkt;
+			break;
+		case HAL_DEF_DBG_DUMP_TXPKT:
+			*(( u8*)pValue) = pHalData->bDumpTxPkt;
+			break;
+
+		default:
+			//RT_TRACE(COMP_INIT, DBG_WARNING, ("GetHalDefVar8188EUsb(): Unkown variable: %d!\n", eVariable));
+			bResult = _FAIL;
+			break;
+	}
+
+	return bResult;
+}
+
+
+
+
+//
+//	Description:
+//		Change default setting of specified variable.
+//
+u8
+SetHalDefVar8188EUsb(
+	IN	PADAPTER				Adapter,
+	IN	HAL_DEF_VARIABLE		eVariable,
+	IN	PVOID					pValue
+	)
+{
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(Adapter);
+	u8			bResult = _SUCCESS;
+
+	switch(eVariable)
+	{
+		case HAL_DEF_DBG_DM_FUNC:
+			{
+				u8 dm_func = *(( u8*)pValue);
+				struct dm_priv	*pdmpriv = &pHalData->dmpriv;
+				DM_ODM_T 		*podmpriv = &pHalData->odmpriv;
+				
+				if(dm_func == 0){ //disable all dynamic func
+					podmpriv->SupportAbility = DYNAMIC_FUNC_DISABLE;
+					DBG_8192C("==> Disable all dynamic function...\n");
+				}
+				else if(dm_func == 1){//disable DIG
+					podmpriv->SupportAbility  &= (~DYNAMIC_BB_DIG);
+					DBG_8192C("==> Disable DIG...\n");
+				}
+				else if(dm_func == 2){//disable High power
+					podmpriv->SupportAbility  &= (~DYNAMIC_BB_DYNAMIC_TXPWR);
+				}
+				else if(dm_func == 3){//disable tx power tracking
+					podmpriv->SupportAbility  &= (~DYNAMIC_RF_CALIBRATION);
+					DBG_8192C("==> Disable tx power tracking...\n");
+				}
+				//else if(dm_func == 4){//disable BT coexistence
+				//	pdmpriv->DMFlag &= (~DYNAMIC_FUNC_BT);
+				//}
+				else if(dm_func == 5){//disable antenna diversity
+					podmpriv->SupportAbility  &= (~DYNAMIC_BB_ANT_DIV);
+				}				
+				else if(dm_func == 6){//turn on all dynamic func
+					if(!(podmpriv->SupportAbility  & DYNAMIC_BB_DIG))
+					{						
+						DIG_T	*pDigTable = &podmpriv->DM_DigTable;
+						pDigTable->CurIGValue= rtw_read8(Adapter,0xc50);	
+					}
+					//pdmpriv->DMFlag |= DYNAMIC_FUNC_BT;
+					podmpriv->SupportAbility = DYNAMIC_ALL_FUNC_ENABLE;
+					DBG_8192C("==> Turn on all dynamic function...\n");
+				}			
+			}
+			break;
+		case HAL_DEF_DBG_DUMP_RXPKT:
+			pHalData->bDumpRxPkt = *(( u8*)pValue);
+			break;
+		case HAL_DEF_DBG_DUMP_TXPKT:
+			pHalData->bDumpTxPkt = *(( u8*)pValue);
+			break;				
+		case HW_DEF_FA_CNT_DUMP:
+			{
+				u8 bRSSIDump = *((u8*)pValue);	
+				PDM_ODM_T		pDM_Odm = &(pHalData->odmpriv);
+				if(bRSSIDump)
+					pDM_Odm->DebugComponents	=	ODM_COMP_DIG|ODM_COMP_FA_CNT	;					
+				else
+					pDM_Odm->DebugComponents	= 0;					
+				
+			}
+			break;
+		case HW_DEF_ODM_DBG_FLAG:
+			{
+				u8Byte	DebugComponents = *((u8Byte*)pValue);
+				PDM_ODM_T	pDM_Odm = &(pHalData->odmpriv);
+				pDM_Odm->DebugComponents = DebugComponents;			
+			}
+			break;
+
+		default:
+			//RT_TRACE(COMP_INIT, DBG_TRACE, ("SetHalDefVar819xUsb(): Unkown variable: %d!\n", eVariable));
+			bResult = _FAIL;
+			break;
+	}
+
+	return bResult;
+}
+/*
+u32  _update_92cu_basic_rate(_adapter *padapter, unsigned int mask)
+{
+	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(padapter);
+#ifdef CONFIG_BT_COEXIST
+	struct btcoexist_priv	*pbtpriv = &(pHalData->bt_coexist);
+#endif
+	unsigned int BrateCfg = 0;
+
+#ifdef CONFIG_BT_COEXIST
+	if(	(pbtpriv->BT_Coexist) &&	(pbtpriv->BT_CoexistType == BT_CSR_BC4)	)
+	{
+		BrateCfg = mask  & 0x151;
+		//DBG_8192C("BT temp disable cck 2/5.5/11M, (0x%x = 0x%x)\n", REG_RRSR, BrateCfg & 0x151);
+	}
+	else
+#endif
+	{
+		//if(pHalData->VersionID != VERSION_TEST_CHIP_88C)
+			BrateCfg = mask  & 0x15F;
+		//else	//for 88CU 46PING setting, Disable CCK 2M, 5.5M, Others must tuning
+		//	BrateCfg = mask  & 0x159;
+	}
+
+	BrateCfg |= 0x01; // default enable 1M ACK rate					
+
+	return BrateCfg;
+}
+*/
+void _update_response_rate(_adapter *padapter,unsigned int mask)
+{
+	u8	RateIndex = 0;
+	// Set RRSR rate table.
+	rtw_write8(padapter, REG_RRSR, mask&0xff);
+	rtw_write8(padapter,REG_RRSR+1, (mask>>8)&0xff);
+
+	// Set RTS initial rate
+	while(mask > 0x1)
+	{
+		mask = (mask>> 1);
+		RateIndex++;
+	}
+	rtw_write8(padapter, REG_INIRTS_RATE_SEL, RateIndex);
+}
+
+void UpdateHalRAMask8188EUsb(PADAPTER padapter, u32 mac_id, u8 rssi_level)
+{
+	//volatile unsigned int result;
+	u8	init_rate=0;
+	u8	networkType, raid;	
+	u32	mask,rate_bitmap;
+	u8	shortGIrate = _FALSE;
+	int	supportRateNum = 0;
+	struct sta_info	*psta;
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	//struct dm_priv	*pdmpriv = &pHalData->dmpriv;
+	struct mlme_ext_priv	*pmlmeext = &padapter->mlmeextpriv;
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	WLAN_BSSID_EX 		*cur_network = &(pmlmeinfo->network);
+#ifdef CONFIG_CONCURRENT_MODE
+	if(rtw_buddy_adapter_up(padapter) && padapter->adapter_type > PRIMARY_ADAPTER)	
+		pHalData = GET_HAL_DATA(padapter->pbuddy_adapter);				
+#endif //CONFIG_CONCURRENT_MODE
+
+	if (mac_id >= NUM_STA) //CAM_SIZE
+	{
+		return;
+	}
+
+	psta = pmlmeinfo->FW_sta_info[mac_id].psta;
+	if(psta == NULL)
+	{
+		return;
+	}
+
+	switch (mac_id)
+	{
+		case 0:// for infra mode
+#ifdef CONFIG_CONCURRENT_MODE
+		case 2:// first station uses macid=0, second station uses macid=2
+#endif
+			supportRateNum = rtw_get_rateset_len(cur_network->SupportedRates);
+			networkType = judge_network_type(padapter, cur_network->SupportedRates, supportRateNum) & 0xf;
+			//pmlmeext->cur_wireless_mode = networkType;
+			raid = networktype_to_raid(networkType);
+						
+			mask = update_supported_rate(cur_network->SupportedRates, supportRateNum);
+			mask |= (pmlmeinfo->HT_enable)? update_MSC_rate(&(pmlmeinfo->HT_caps)): 0;
+		
+			
+			if (support_short_GI(padapter, &(pmlmeinfo->HT_caps)))
+			{
+				shortGIrate = _TRUE;
+			}
+			
+			break;
+
+		case 1://for broadcast/multicast
+			supportRateNum = rtw_get_rateset_len(pmlmeinfo->FW_sta_info[mac_id].SupportedRates);
+			if(pmlmeext->cur_wireless_mode & WIRELESS_11B)
+				networkType = WIRELESS_11B;
+			else
+				networkType = WIRELESS_11G;
+			raid = networktype_to_raid(networkType);
+			mask = update_basic_rate(cur_network->SupportedRates, supportRateNum);
+
+
+			break;
+
+		default: //for each sta in IBSS
+			supportRateNum = rtw_get_rateset_len(pmlmeinfo->FW_sta_info[mac_id].SupportedRates);
+			networkType = judge_network_type(padapter, pmlmeinfo->FW_sta_info[mac_id].SupportedRates, supportRateNum) & 0xf;
+			//pmlmeext->cur_wireless_mode = networkType;
+			raid = networktype_to_raid(networkType);			
+			mask = update_supported_rate(cur_network->SupportedRates, supportRateNum);
+			
+			//todo: support HT in IBSS
+			
+			break;
+	}
+	
+	//mask &=0x0fffffff;
+	rate_bitmap = 0x0fffffff;	
+#ifdef	CONFIG_ODM_REFRESH_RAMASK
+	{				
+		rate_bitmap = ODM_Get_Rate_Bitmap(&pHalData->odmpriv,mac_id,mask,rssi_level);
+		printk("%s => mac_id:%d, networkType:0x%02x, mask:0x%08x\n\t ==> rssi_level:%d, rate_bitmap:0x%08x\n",
+			__FUNCTION__,mac_id,networkType,mask,rssi_level,rate_bitmap);
+	}
+#endif
+	
+	mask &= rate_bitmap; 
+	
+	init_rate = get_highest_rate_idx(mask)&0x3f;
+	
+	if(pHalData->fw_ractrl == _TRUE)
+	{
+		u8 arg = 0;
+
+		//arg = (cam_idx-4)&0x1f;//MACID
+		arg = mac_id&0x1f;//MACID
+		
+		arg |= BIT(7);
+		
+		if (shortGIrate==_TRUE)
+			arg |= BIT(5);
+		mask |= ((raid<<28)&0xf0000000);
+		DBG_871X("update raid entry, mask=0x%x, arg=0x%x\n", mask, arg);
+		psta->ra_mask=mask;
+#ifdef CONFIG_INTEL_PROXIM
+		if(padapter->proximity.proxim_on ==_TRUE){
+			arg &= ~BIT(6);
+		}
+		else {
+			arg |= BIT(6);
+		}
+#endif //CONFIG_INTEL_PROXIM
+		mask |= ((raid<<28)&0xf0000000);
+
+		//to do 
+		/*
+		*(pu4Byte)&RateMask=EF4Byte((ratr_bitmap&0x0fffffff) | (ratr_index<<28));
+		RateMask[4] = macId | (bShortGI?0x20:0x00) | 0x80;
+		*/	
+		rtl8188e_set_raid_cmd(padapter, mask);	
+		
+	}
+	else
+	{	
+
+#if(RATE_ADAPTIVE_SUPPORT == 1)	
+
+		ODM_RA_UpdateRateInfo_8188E(
+				&(pHalData->odmpriv),
+				mac_id,
+				raid, 
+				mask,
+				shortGIrate
+				);
+
+#endif		
+	}
+
+
+	//set ra_id
+	psta->raid = raid;
+	psta->init_rate = init_rate;
+
+
+}
+
+
+void SetBeaconRelatedRegisters8188EUsb(PADAPTER padapter)
+{
+	u32	value32;
+	//HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	struct mlme_ext_priv	*pmlmeext = &(padapter->mlmeextpriv);
+	struct mlme_ext_info	*pmlmeinfo = &(pmlmeext->mlmext_info);
+	u32 bcn_ctrl_reg 			= REG_BCN_CTRL;
+	//reset TSF, enable update TSF, correcting TSF On Beacon 
+	
+	//REG_BCN_INTERVAL
+	//REG_BCNDMATIM
+	//REG_ATIMWND
+	//REG_TBTT_PROHIBIT
+	//REG_DRVERLYINT
+	//REG_BCN_MAX_ERR	
+	//REG_BCNTCFG //(0x510)
+	//REG_DUAL_TSF_RST
+	//REG_BCN_CTRL //(0x550) 
+
+	//BCN interval
+#ifdef CONFIG_CONCURRENT_MODE
+        	if (padapter->iface_type == IFACE_PORT1){
+		bcn_ctrl_reg = REG_BCN_CTRL_1;
+        	}
+#endif	
+	rtw_write16(padapter, REG_BCN_INTERVAL, pmlmeinfo->bcn_interval);
+	rtw_write8(padapter, REG_ATIMWND, 0x02);// 2ms
+
+	_InitBeaconParameters(padapter);
+
+	rtw_write8(padapter, REG_SLOT, 0x09);
+
+	value32 =rtw_read32(padapter, REG_TCR); 
+	value32 &= ~TSFRST;
+	rtw_write32(padapter,  REG_TCR, value32); 
+
+	value32 |= TSFRST;
+	rtw_write32(padapter, REG_TCR, value32); 
+
+	// NOTE: Fix test chip's bug (about contention windows's randomness)
+	rtw_write8(padapter,  REG_RXTSF_OFFSET_CCK, 0x50);
+	rtw_write8(padapter, REG_RXTSF_OFFSET_OFDM, 0x50);
+
+	_BeaconFunctionEnable(padapter, _TRUE, _TRUE);
+
+	ResumeTxBeacon(padapter);
+
+	//rtw_write8(padapter, 0x422, rtw_read8(padapter, 0x422)|BIT(6));
+	
+	//rtw_write8(padapter, 0x541, 0xff);
+
+	//rtw_write8(padapter, 0x542, rtw_read8(padapter, 0x541)|BIT(0));
+
+	rtw_write8(padapter, bcn_ctrl_reg, rtw_read8(padapter, bcn_ctrl_reg)|BIT(1));
+
+}
+
+static void rtl8188eu_init_default_value(_adapter * padapter)
+{
+	PHAL_DATA_TYPE pHalData;
+	struct pwrctrl_priv *pwrctrlpriv;
+	struct dm_priv *pdmpriv;
+	u8 i;
+
+	pHalData = GET_HAL_DATA(padapter);
+	pwrctrlpriv = &padapter->pwrctrlpriv;
+	pdmpriv = &pHalData->dmpriv;
+
+
+	//init default value
+	pHalData->fw_ractrl = _FALSE;		
+	if(!pwrctrlpriv->bkeepfwalive)
+		pHalData->LastHMEBoxNum = 0;	
+
+	//init dm default value
+	pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized = _FALSE;
+	pHalData->odmpriv.RFCalibrateInfo.TM_Trigger = 0;//for IQK
+	//pdmpriv->binitialized = _FALSE;
+//	pdmpriv->prv_traffic_idx = 3;
+//	pdmpriv->initialize = 0;
+	pHalData->pwrGroupCnt = 0;
+	pHalData->PGMaxGroup= 13;
+	pHalData->odmpriv.RFCalibrateInfo.ThermalValue_HP_index = 0;
+	for(i = 0; i < HP_THERMAL_NUM; i++)
+		pHalData->odmpriv.RFCalibrateInfo.ThermalValue_HP[i] = 0;
+}
+
+static u8 rtl8188eu_ps_func(PADAPTER Adapter,HAL_INTF_PS_FUNC efunc_id, u8 *val)
+{	
+	u8 bResult = _TRUE;
+	switch(efunc_id){
+
+		#if defined(CONFIG_AUTOSUSPEND) && defined(SUPPORT_HW_RFOFF_DETECTED)
+		case HAL_USB_SELECT_SUSPEND:
+			{
+				u8 bfwpoll = *(( u8*)val);
+				//rtl8188e_set_FwSelectSuspend_cmd(Adapter,bfwpoll ,500);//note fw to support hw power down ping detect
+			}
+			break;
+		#endif //CONFIG_AUTOSUSPEND && SUPPORT_HW_RFOFF_DETECTED
+
+		default:
+			break;
+	}
+	return bResult;
+}
+
+void rtl8188eu_set_hal_ops(_adapter * padapter)
+{
+	struct hal_ops	*pHalFunc = &padapter->HalFunc;
+
+_func_enter_;
+
+	padapter->HalData = rtw_zmalloc(sizeof(HAL_DATA_TYPE));
+	if(padapter->HalData == NULL){
+		DBG_8192C("cant not alloc memory for HAL DATA \n");
+	}
+	//_rtw_memset(padapter->HalData, 0, sizeof(HAL_DATA_TYPE));
+	padapter->hal_data_sz = sizeof(HAL_DATA_TYPE);
+
+	pHalFunc->hal_power_on = rtl8188eu_InitPowerOn;
+	pHalFunc->hal_init = &rtl8188eu_hal_init;
+	pHalFunc->hal_deinit = &rtl8188eu_hal_deinit;
+
+	//pHalFunc->free_hal_data = &rtl8192c_free_hal_data;
+
+	pHalFunc->inirp_init = &rtl8188eu_inirp_init;
+	pHalFunc->inirp_deinit = &rtl8188eu_inirp_deinit;
+
+	pHalFunc->init_xmit_priv = &rtl8188eu_init_xmit_priv;
+	pHalFunc->free_xmit_priv = &rtl8188eu_free_xmit_priv;
+
+	pHalFunc->init_recv_priv = &rtl8188eu_init_recv_priv;
+	pHalFunc->free_recv_priv = &rtl8188eu_free_recv_priv;
+#ifdef CONFIG_SW_LED
+	pHalFunc->InitSwLeds = &rtl8188eu_InitSwLeds;
+	pHalFunc->DeInitSwLeds = &rtl8188eu_DeInitSwLeds;
+#else //case of hw led or no led
+	pHalFunc->InitSwLeds = NULL;
+	pHalFunc->DeInitSwLeds = NULL;	
+#endif//CONFIG_SW_LED
+	
+	pHalFunc->init_default_value = &rtl8188eu_init_default_value;
+	pHalFunc->intf_chip_configure = &rtl8188eu_interface_configure;
+	pHalFunc->read_adapter_info = &ReadAdapterInfo8188EU;
+
+	//pHalFunc->set_bwmode_handler = &PHY_SetBWMode8192C;
+	//pHalFunc->set_channel_handler = &PHY_SwChnl8192C;
+
+	//pHalFunc->hal_dm_watchdog = &rtl8192c_HalDmWatchDog;
+
+
+	pHalFunc->SetHwRegHandler = &SetHwReg8188EU;
+	pHalFunc->GetHwRegHandler = &GetHwReg8188EU;
+  	pHalFunc->GetHalDefVarHandler = &GetHalDefVar8188EUsb;
+ 	pHalFunc->SetHalDefVarHandler = &SetHalDefVar8188EUsb;
+
+	pHalFunc->UpdateRAMaskHandler = &UpdateHalRAMask8188EUsb;
+	pHalFunc->SetBeaconRelatedRegistersHandler = &SetBeaconRelatedRegisters8188EUsb;
+
+	//pHalFunc->Add_RateATid = &rtl8192c_Add_RateATid;
+
+	pHalFunc->hal_xmit = &rtl8188eu_hal_xmit;
+	pHalFunc->mgnt_xmit = &rtl8188eu_mgnt_xmit;
+	pHalFunc->hal_xmitframe_enqueue = &rtl8188eu_hal_xmitframe_enqueue;
+
+
+#ifdef CONFIG_HOSTAPD_MLME
+	pHalFunc->hostap_mgnt_xmit_entry = &rtl8188eu_hostap_mgnt_xmit_entry;
+#endif
+	pHalFunc->interface_ps_func = &rtl8188eu_ps_func;
+
+	rtl8188e_set_hal_ops(pHalFunc);
+_func_exit_;
+
+}
+
diff --git a/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/usb/usb_ops_linux.c b/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/usb/usb_ops_linux.c
new file mode 100755
index 00000000..79962d3b
--- /dev/null
+++ b/drivers/net/wireless/rtl8188E_8192E/hal/rtl8188e/usb/usb_ops_linux.c
@@ -0,0 +1,1765 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#define _HCI_OPS_OS_C_
+
+#include <drv_conf.h>
+#include <osdep_service.h>
+#include <drv_types.h>
+#include <osdep_intf.h>
+#include <usb_ops.h>
+#include <circ_buf.h>
+#include <recv_osdep.h>
+#include <rtl8188e_hal.h>
+
+#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS)
+
+#error "Shall be Linux or Windows, but not both!\n"
+
+#endif
+
+static int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u16 index, void *pdata, u16 len, u8 requesttype)
+{
+	_adapter	*padapter = pintfhdl->padapter;
+	struct dvobj_priv  *pdvobjpriv = adapter_to_dvobj(padapter);
+	struct usb_device *udev=pdvobjpriv->pusbdev;
+
+	unsigned int pipe;
+	int status = 0;
+	u32 tmp_buflen=0;
+	u8 reqtype;
+	u8 *pIo_buf;
+	int vendorreq_times = 0;
+
+	#ifdef CONFIG_USB_VENDOR_REQ_BUFFER_DYNAMIC_ALLOCATE
+	u8 *tmp_buf;
+	#else // use stack memory
+	u8 tmp_buf[MAX_USB_IO_CTL_SIZE];
+	#endif
+
+#ifdef CONFIG_CONCURRENT_MODE
+	if(padapter->adapter_type > PRIMARY_ADAPTER)
+	{
+		padapter = padapter->pbuddy_adapter;
+		pdvobjpriv = adapter_to_dvobj(padapter);
+		udev = pdvobjpriv->pusbdev;
+	}
+#endif
+
+	//DBG_871X("%s %s:%d\n",__FUNCTION__, current->comm, current->pid);
+
+	if((padapter->bSurpriseRemoved) ||(padapter->pwrctrlpriv.pnp_bstop_trx)){
+		RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usbctrl_vendorreq:(padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n"));
+		status = -EPERM; 
+		goto exit;
+	}	
+
+	if(len>MAX_VENDOR_REQ_CMD_SIZE){
+		DBG_8192C( "[%s] Buffer len error ,vendor request failed\n", __FUNCTION__ );
+		status = -EINVAL;
+		goto exit;
+	}	
+
+	#ifdef CONFIG_USB_VENDOR_REQ_MUTEX
+	_enter_critical_mutex(&pdvobjpriv->usb_vendor_req_mutex, NULL);
+	#endif
+	
+	
+	// Acquire IO memory for vendorreq
+#ifdef CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC
+	pIo_buf = pdvobjpriv->usb_vendor_req_buf;
+#else
+	#ifdef CONFIG_USB_VENDOR_REQ_BUFFER_DYNAMIC_ALLOCATE
+	tmp_buf = rtw_malloc( (u32) len + ALIGNMENT_UNIT);
+	tmp_buflen =  (u32)len + ALIGNMENT_UNIT;
+	#else // use stack memory
+	tmp_buflen = MAX_USB_IO_CTL_SIZE;
+	#endif
+
+	// Added by Albert 2010/02/09
+	// For mstar platform, mstar suggests the address for USB IO should be 16 bytes alignment.
+	// Trying to fix it here.
+	pIo_buf = (tmp_buf==NULL)?NULL:tmp_buf + ALIGNMENT_UNIT -((SIZE_PTR)(tmp_buf) & 0x0f );	
+#endif
+
+	if ( pIo_buf== NULL) {
+		DBG_8192C( "[%s] pIo_buf == NULL \n", __FUNCTION__ );
+		status = -ENOMEM;
+		goto release_mutex;
+	}
+	
+	while(++vendorreq_times<= MAX_USBCTRL_VENDORREQ_TIMES)
+	{
+		_rtw_memset(pIo_buf, 0, len);
+		
+		if (requesttype == 0x01)
+		{
+			pipe = usb_rcvctrlpipe(udev, 0);//read_in
+			reqtype =  REALTEK_USB_VENQT_READ;		
+		} 
+		else 
+		{
+			pipe = usb_sndctrlpipe(udev, 0);//write_out
+			reqtype =  REALTEK_USB_VENQT_WRITE;		
+			_rtw_memcpy( pIo_buf, pdata, len);
+		}		
+	
+		#if 0
+		//timeout test for firmware downloading
+		status = rtw_usb_control_msg(udev, pipe, request, reqtype, value, index, pIo_buf, len
+			, (value == FW_8188E_START_ADDRESS) ?RTW_USB_CONTROL_MSG_TIMEOUT_TEST : RTW_USB_CONTROL_MSG_TIMEOUT
+		);
+		#else
+		status = rtw_usb_control_msg(udev, pipe, request, reqtype, value, index, pIo_buf, len, RTW_USB_CONTROL_MSG_TIMEOUT);
+		#endif
+	
+		if ( status == len)   // Success this control transfer.
+		{
+			rtw_reset_continual_urb_error(pdvobjpriv);
+			if ( requesttype == 0x01 )
+			{   // For Control read transfer, we have to copy the read data from pIo_buf to pdata.
+				_rtw_memcpy( pdata, pIo_buf,  len );
+			}
+		}
+		else { // error cases
+			DBG_8192C("reg 0x%x, usb %s %u fail, status:%d value=0x%x, vendorreq_times:%d\n"
+				, value,(requesttype == 0x01)?"read":"write" , len, status, *(u32*)pdata, vendorreq_times);
+			
+			if (status < 0) {
+				if(status == (-ESHUTDOWN)	|| status == -ENODEV	)
+				{			
+					padapter->bSurpriseRemoved = _TRUE;
+				} else {
+					#ifdef DBG_CONFIG_ERROR_DETECT
+					{
+						HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+						pHalData->srestpriv.Wifi_Error_Status = USB_VEN_REQ_CMD_FAIL;
+					}
+					#endif
+				}
+			}
+			else // status != len && status >= 0
+			{
+				if(status > 0) {
+					if ( requesttype == 0x01 )
+					{   // For Control read transfer, we have to copy the read data from pIo_buf to pdata.
+						_rtw_memcpy( pdata, pIo_buf,  len );
+					}
+				}
+			}
+
+			if(rtw_inc_and_chk_continual_urb_error(pdvobjpriv) == _TRUE ){
+				padapter->bSurpriseRemoved = _TRUE;
+				break;
+			}
+	
+		}
+	
+		// firmware download is checksumed, don't retry
+		if( (value >= FW_8188E_START_ADDRESS && value <= FW_8188E_END_ADDRESS) || status == len )
+			break;
+	
+	}
+	
+	// release IO memory used by vendorreq
+	#ifdef CONFIG_USB_VENDOR_REQ_BUFFER_DYNAMIC_ALLOCATE
+	rtw_mfree(tmp_buf, tmp_buflen);
+	#endif
+
+release_mutex:
+	#ifdef CONFIG_USB_VENDOR_REQ_MUTEX
+	_exit_critical_mutex(&pdvobjpriv->usb_vendor_req_mutex, NULL);
+	#endif
+exit:
+	return status;
+
+}
+
+static u8 usb_read8(struct intf_hdl *pintfhdl, u32 addr)
+{
+	u8 request;
+	u8 requesttype;
+	u16 wvalue;
+	u16 index;
+	u16 len;
+	u8 data=0;
+	
+	_func_enter_;
+
+	request = 0x05;
+	requesttype = 0x01;//read_in
+	index = 0;//n/a
+
+	wvalue = (u16)(addr&0x0000ffff);
+	len = 1;	
+	
+	usbctrl_vendorreq(pintfhdl, request, wvalue, index, &data, len, requesttype);
+
+	_func_exit_;
+
+	return data;
+		
+}
+
+static u16 usb_read16(struct intf_hdl *pintfhdl, u32 addr)
+{       
+	u8 request;
+	u8 requesttype;
+	u16 wvalue;
+	u16 index;
+	u16 len;
+	u16 data=0;
+	
+	_func_enter_;
+
+	request = 0x05;
+	requesttype = 0x01;//read_in
+	index = 0;//n/a
+
+	wvalue = (u16)(addr&0x0000ffff);
+	len = 2;	
+	
+	usbctrl_vendorreq(pintfhdl, request, wvalue, index, &data, len, requesttype);
+
+	_func_exit_;
+
+	return data;
+	
+}
+
+static u32 usb_read32(struct intf_hdl *pintfhdl, u32 addr)
+{
+	u8 request;
+	u8 requesttype;
+	u16 wvalue;
+	u16 index;
+	u16 len;
+	u32 data=0;
+	
+	_func_enter_;
+
+	request = 0x05;
+	requesttype = 0x01;//read_in
+	index = 0;//n/a
+
+	wvalue = (u16)(addr&0x0000ffff);
+	len = 4;	
+	
+	usbctrl_vendorreq(pintfhdl, request, wvalue, index, &data, len, requesttype);
+
+	_func_exit_;
+
+	return data;
+	
+}
+
+static int usb_write8(struct intf_hdl *pintfhdl, u32 addr, u8 val)
+{
+	u8 request;
+	u8 requesttype;
+	u16 wvalue;
+	u16 index;
+	u16 len;
+	u8 data;
+	int ret;
+	
+	_func_enter_;
+
+	request = 0x05;
+	requesttype = 0x00;//write_out
+	index = 0;//n/a
+
+	wvalue = (u16)(addr&0x0000ffff);
+	len = 1;
+	
+	data = val;	
+	
+	 ret = usbctrl_vendorreq(pintfhdl, request, wvalue, index, &data, len, requesttype);
+	
+	_func_exit_;
+	
+	return ret;
+	
+}
+
+static int usb_write16(struct intf_hdl *pintfhdl, u32 addr, u16 val)
+{	
+	u8 request;
+	u8 requesttype;
+	u16 wvalue;
+	u16 index;
+	u16 len;
+	u16 data;
+	int ret;
+	
+	_func_enter_;
+
+	request = 0x05;
+	requesttype = 0x00;//write_out
+	index = 0;//n/a
+
+	wvalue = (u16)(addr&0x0000ffff);
+	len = 2;
+	
+	data = val;
+		
+	ret = usbctrl_vendorreq(pintfhdl, request, wvalue, index, &data, len, requesttype);
+	
+	_func_exit_;
+	
+	return ret;
+	
+}
+
+static int usb_write32(struct intf_hdl *pintfhdl, u32 addr, u32 val)
+{
+	u8 request;
+	u8 requesttype;
+	u16 wvalue;
+	u16 index;
+	u16 len;
+	u32 data;
+	int ret;
+	
+	_func_enter_;
+
+	request = 0x05;
+	requesttype = 0x00;//write_out
+	index = 0;//n/a
+
+	wvalue = (u16)(addr&0x0000ffff);
+	len = 4;
+	data =val;		
+
+	ret =usbctrl_vendorreq(pintfhdl, request, wvalue, index, &data, len, requesttype);
+	
+	_func_exit_;
+	
+	return ret;
+	
+}
+
+static int usb_writeN(struct intf_hdl *pintfhdl, u32 addr, u32 length, u8 *pdata)
+{
+	u8 request;
+	u8 requesttype;
+	u16 wvalue;
+	u16 index;
+	u16 len;
+	u8 buf[VENDOR_CMD_MAX_DATA_LEN]={0};
+	int ret;
+	
+	_func_enter_;
+
+	request = 0x05;
+	requesttype = 0x00;//write_out
+	index = 0;//n/a
+
+	wvalue = (u16)(addr&0x0000ffff);
+	len = length;
+	 _rtw_memcpy(buf, pdata, len );
+	
+	ret = usbctrl_vendorreq(pintfhdl, request, wvalue, index, buf, len, requesttype);
+	
+	_func_exit_;
+	
+	return ret;
+	
+}
+
+#ifdef CONFIG_SUPPORT_USB_INT
+void interrupt_handler_8188eu(_adapter *padapter,u16 pkt_len,u8 *pbuf)
+{	
+	HAL_DATA_TYPE	*pHalData=GET_HAL_DATA(padapter);
+	struct reportpwrstate_parm pwr_rpt;
+	
+	if ( pkt_len != INTERRUPT_MSG_FORMAT_LEN )
+	{
+		DBG_8192C("%s Invalid interrupt content length (%d)!\n", __FUNCTION__, pkt_len);
+		return ;
+	}
+
+	// HISR 
+	_rtw_memcpy(&(pHalData->IntArray[0]), &(pbuf[USB_INTR_CONTENT_HISR_OFFSET]), 4);
+	_rtw_memcpy(&(pHalData->IntArray[1]), &(pbuf[USB_INTR_CONTENT_HISRE_OFFSET]), 4);
+
+	#if 0 //DBG
+	{
+		u32 hisr=0 ,hisr_ex=0;
+		_rtw_memcpy(&hisr,&(pHalData->IntArray[0]),4);
+		hisr = le32_to_cpu(hisr);	
+		
+		_rtw_memcpy(&hisr_ex,&(pHalData->IntArray[1]),4);
+		hisr_ex = le32_to_cpu(hisr_ex);
+		
+		if((hisr != 0) || (hisr_ex!=0))
+			DBG_871X("===> %s hisr:0x%08x ,hisr_ex:0x%08x \n",__FUNCTION__,hisr,hisr_ex);
+	}
+	#endif
+
+
+#ifdef CONFIG_LPS_LCLK
+	if(  pHalData->IntArray[0]  & IMR_CPWM_88E )
+	{
+		_rtw_memcpy(&pwr_rpt.state, &(pbuf[USB_INTR_CONTENT_CPWM1_OFFSET]), 1);
+		//_rtw_memcpy(&pwr_rpt.state2, &(pbuf[USB_INTR_CONTENT_CPWM2_OFFSET]), 1);
+
+		//88e's cpwm value only change BIT0, so driver need to add PS_STATE_S2 for LPS flow.		
+		pwr_rpt.state |= PS_STATE_S2;		
+		_set_workitem(&padapter->pwrctrlpriv.cpwm_event);
+	}
+#endif//CONFIG_LPS_LCLK
+
+#ifdef CONFIG_INTERRUPT_BASED_TXBCN
+
+	#ifdef  CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
+	if (pHalData->IntArray[0] & IMR_BCNDMAINT0_88E)
+	#endif
+	#ifdef  CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
+	if (pHalData->IntArray[0] & (IMR_TBDER_88E|IMR_TBDOK_88E))
+	#endif	
+	{		
+		struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+		#if 0
+		if(pHalData->IntArray[0] & IMR_BCNDMAINT0_88E)
+			DBG_8192C("%s: HISR_BCNERLY_INT\n", __func__);
+		if(pHalData->IntArray[0] & IMR_TBDOK_88E)
+			DBG_8192C("%s: HISR_TXBCNOK\n", __func__);
+		if(pHalData->IntArray[0] & IMR_TBDER_88E)
+			DBG_8192C("%s: HISR_TXBCNERR\n", __func__);
+		#endif
+		
+
+		if(check_fwstate(pmlmepriv, WIFI_AP_STATE))
+		{
+			//send_beacon(padapter);
+			if(pmlmepriv->update_bcn == _TRUE)
+			{
+				//tx_beacon_hdl(padapter, NULL);
+				set_tx_beacon_cmd(padapter);
+			}
+		}
+#ifdef CONFIG_CONCURRENT_MODE
+		if(check_buddy_fwstate(padapter, WIFI_AP_STATE))
+		{
+			//send_beacon(padapter);
+			if(padapter->pbuddy_adapter->mlmepriv.update_bcn == _TRUE)
+			{
+				//tx_beacon_hdl(padapter, NULL);
+				set_tx_beacon_cmd(padapter->pbuddy_adapter);
+			}
+		}
+#endif
+		
+	}
+#endif //CONFIG_INTERRUPT_BASED_TXBCN
+
+
+
+
+#ifdef DBG_CONFIG_ERROR_DETECT_INT
+	if(  pHalData->IntArray[1]  & IMR_TXERR_88E )
+		DBG_871X("===> %s Tx Error Flag Interrupt Status \n",__FUNCTION__);
+	if(  pHalData->IntArray[1]  & IMR_RXERR_88E )
+		DBG_871X("===> %s Rx Error Flag INT Status \n",__FUNCTION__);
+	if(  pHalData->IntArray[1]  & IMR_TXFOVW_88E )
+		DBG_871X("===> %s Transmit FIFO Overflow \n",__FUNCTION__);
+	if(  pHalData->IntArray[1]  & IMR_RXFOVW_88E )
+		DBG_871X("===> %s Receive FIFO Overflow \n",__FUNCTION__);	
+#endif//DBG_CONFIG_ERROR_DETECT_INT
+
+
+	// C2H Event 
+	if(pbuf[0]!= 0){
+		_rtw_memcpy(&(pHalData->C2hArray[0]), &(pbuf[USB_INTR_CONTENT_C2H_OFFSET]), 16);		
+		//rtw_c2h_wk_cmd(padapter); to do..
+	}		
+		
+}
+#endif
+				
+#ifdef CONFIG_USB_INTERRUPT_IN_PIPE
+static void usb_read_interrupt_complete(struct urb *purb, struct pt_regs *regs)
+{
+	int	err;
+	_adapter		*padapter = (_adapter	 *)purb->context;
+
+	if(padapter->bSurpriseRemoved || padapter->bDriverStopped||padapter->bReadPortCancel)
+	{
+		DBG_8192C("%s() RX Warning! bDriverStopped(%d) OR bSurpriseRemoved(%d) bReadPortCancel(%d)\n", 
+		__FUNCTION__,padapter->bDriverStopped, padapter->bSurpriseRemoved,padapter->bReadPortCancel);
+
+		return;
+	}
+		
+	if(purb->status==0)//SUCCESS
+	{
+		if (purb->actual_length > INTERRUPT_MSG_FORMAT_LEN)
+		{
+			DBG_8192C("usb_read_interrupt_complete: purb->actual_length > INTERRUPT_MSG_FORMAT_LEN(%d)\n",INTERRUPT_MSG_FORMAT_LEN);			
+		}
+
+		interrupt_handler_8188eu(padapter, purb->actual_length,purb->transfer_buffer );
+		
+		err = usb_submit_urb(purb, GFP_ATOMIC);
+		if((err) && (err != (-EPERM)))
+		{
+			DBG_8192C("cannot submit interrupt in-token(err = 0x%08x),urb_status = %d\n",err, purb->status);
+		}
+	}
+	else
+	{
+		DBG_8192C("###=> usb_read_interrupt_complete => urb status(%d)\n", purb->status);
+
+		switch(purb->status) {
+			case -EINVAL:
+			case -EPIPE:			
+			case -ENODEV:
+			case -ESHUTDOWN:
+				//padapter->bSurpriseRemoved=_TRUE;
+				RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bSurpriseRemoved=TRUE\n"));
+			case -ENOENT:
+				padapter->bDriverStopped=_TRUE;			
+				RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bDriverStopped=TRUE\n"));
+				break;
+			case -EPROTO:
+				break;
+			case -EINPROGRESS:
+				DBG_8192C("ERROR: URB IS IN PROGRESS!/n");
+				break;
+			default:
+				break;				
+		}
+	}	
+
+}
+
+static u32 usb_read_interrupt(struct intf_hdl *pintfhdl, u32 addr)
+{
+	int	err;
+	unsigned int pipe;
+	u32	ret = _SUCCESS;
+	_adapter			*adapter = pintfhdl->padapter;
+	struct dvobj_priv	*pdvobj = adapter_to_dvobj(adapter);
+	struct recv_priv	*precvpriv = &adapter->recvpriv;
+	struct usb_device	*pusbd = pdvobj->pusbdev;
+
+_func_enter_;
+
+	//translate DMA FIFO addr to pipehandle
+	pipe = ffaddr2pipehdl(pdvobj, addr);
+
+	usb_fill_int_urb(precvpriv->int_in_urb, pusbd, pipe, 
+					precvpriv->int_in_buf,
+            				INTERRUPT_MSG_FORMAT_LEN,
+            				usb_read_interrupt_complete,
+            				adapter,
+            				1);
+
+	err = usb_submit_urb(precvpriv->int_in_urb, GFP_ATOMIC);
+	if((err) && (err != (-EPERM)))
+	{
+		DBG_8192C("cannot submit interrupt in-token(err = 0x%08x),urb_status = %d\n",err, precvpriv->int_in_urb->status);
+		ret = _FAIL;
+	}
+
+_func_exit_;
+
+	return ret;
+}
+#endif
+
+static s32 pre_recv_entry(union recv_frame *precvframe, struct recv_stat *prxstat, struct phy_stat *pphy_status)
+{	
+	s32 ret=_SUCCESS;
+#ifdef CONFIG_CONCURRENT_MODE	
+	u8 *primary_myid, *secondary_myid, *paddr1;
+	union recv_frame	*precvframe_if2 = NULL;
+	_adapter *primary_padapter = precvframe->u.hdr.adapter;
+	_adapter *secondary_padapter = primary_padapter->pbuddy_adapter;
+	struct recv_priv *precvpriv = &primary_padapter->recvpriv;
+	_queue *pfree_recv_queue = &precvpriv->free_recv_queue;
+	u8	*pbuf = precvframe->u.hdr.rx_data;
+	
+	if(!secondary_padapter)
+		return ret;
+	
+	paddr1 = GetAddr1Ptr(precvframe->u.hdr.rx_data);		
+
+	if(IS_MCAST(paddr1) == _FALSE)//unicast packets
+	{
+		//primary_myid = myid(&primary_padapter->eeprompriv);
+		secondary_myid = myid(&secondary_padapter->eeprompriv);
+
+		if(_rtw_memcmp(paddr1, secondary_myid, ETH_ALEN))
+		{			
+			//change to secondary interface
+			precvframe->u.hdr.adapter = secondary_padapter;
+		}	
+
+		//ret = recv_entry(precvframe);
+
+	}
+	else // Handle BC/MC Packets	
+	{
+		
+		u8 clone = _TRUE;
+#if 0		
+		u8 type, subtype, *paddr2, *paddr3;
+	
+		type =  GetFrameType(pbuf);
+		subtype = GetFrameSubType(pbuf); //bit(7)~bit(2)
+		
+		switch (type)
+		{
+			case WIFI_MGT_TYPE: //Handle BC/MC mgnt Packets
+				if(subtype == WIFI_BEACON)
+				{
+					paddr3 = GetAddr3Ptr(precvframe->u.hdr.rx_data);
+				
+					if (check_fwstate(&secondary_padapter->mlmepriv, _FW_LINKED) &&
+						_rtw_memcmp(paddr3, get_bssid(&secondary_padapter->mlmepriv), ETH_ALEN))
+					{
+						//change to secondary interface
+						precvframe->u.hdr.adapter = secondary_padapter;
+						clone = _FALSE;
+					}
+
+					if(check_fwstate(&primary_padapter->mlmepriv, _FW_LINKED) &&
+						_rtw_memcmp(paddr3, get_bssid(&primary_padapter->mlmepriv), ETH_ALEN))
+					{
+						if(clone==_FALSE)
+						{
+							clone = _TRUE;									
+						}	
+						else
+						{
+							clone = _FALSE;
+						}
+
+						precvframe->u.hdr.adapter = primary_padapter;	
+					}
+
+					if(check_fwstate(&primary_padapter->mlmepriv, _FW_UNDER_SURVEY|_FW_UNDER_LINKING) ||
+						check_fwstate(&secondary_padapter->mlmepriv, _FW_UNDER_SURVEY|_FW_UNDER_LINKING))
+					{
+						clone = _TRUE;
+						precvframe->u.hdr.adapter = primary_padapter;	
+					}
+				
+				}
+				else if(subtype == WIFI_PROBEREQ)
+				{
+					//probe req frame is only for interface2
+					//change to secondary interface
+					precvframe->u.hdr.adapter = secondary_padapter;
+					clone = _FALSE;
+				}			
+				break;
+			case WIFI_CTRL_TYPE: // Handle BC/MC ctrl Packets
+			
+				break;
+			case WIFI_DATA_TYPE: //Handle BC/MC data Packets
+					//Notes: AP MODE never rx BC/MC data packets
+			
+				paddr2 = GetAddr2Ptr(precvframe->u.hdr.rx_data);
+
+				if(_rtw_memcmp(paddr2, get_bssid(&secondary_padapter->mlmepriv), ETH_ALEN))
+				{
+					//change to secondary interface
+					precvframe->u.hdr.adapter = secondary_padapter;
+					clone = _FALSE;
+				}
+
+				break;
+			default:
+			
+				break;			
+		}
+#endif
+
+		if(_TRUE == clone)
+		{
+			//clone/copy to if2
+			u8 shift_sz = 0;
+			u32 alloc_sz, skb_len;		
+			_pkt	 *pkt_copy = NULL;
+			struct rx_pkt_attrib *pattrib = NULL;
+		
+			precvframe_if2 = rtw_alloc_recvframe(pfree_recv_queue);
+			if(precvframe_if2)
+			{
+				precvframe_if2->u.hdr.adapter = secondary_padapter;
+		
+				_rtw_init_listhead(&precvframe_if2->u.hdr.list);	
+				precvframe_if2->u.hdr.precvbuf = NULL;	//can't access the precvbuf for new arch.
+				precvframe_if2->u.hdr.len=0;
+
+				_rtw_memcpy(&precvframe_if2->u.hdr.attrib, &precvframe->u.hdr.attrib, sizeof(struct rx_pkt_attrib));
+
+				pattrib = &precvframe_if2->u.hdr.attrib;
+
+				//	Modified by Albert 20101213
+				//	For 8 bytes IP header alignment.
+				if (pattrib->qos)	//	Qos data, wireless lan header length is 26
+				{
+					shift_sz = 6;
+				}
+				else
+				{
+					shift_sz = 0;
+				}
+
+				skb_len = pattrib->pkt_len;
+
+				// for first fragment packet, driver need allocate 1536+drvinfo_sz+RXDESC_SIZE to defrag packet.
+				// modify alloc_sz for recvive crc error packet by thomas 2011-06-02
+				if((pattrib->mfrag == 1)&&(pattrib->frag_num == 0)){
+					//alloc_sz = 1664;	//1664 is 128 alignment.
+					if(skb_len <= 1650)
+						alloc_sz = 1664;
+					else
+						alloc_sz = skb_len + 14;
+				}
+				else {
+					alloc_sz = skb_len;
+					//	6 is for IP header 8 bytes alignment in QoS packet case.
+					//	8 is for skb->data 4 bytes alignment.
+					alloc_sz += 14;
+				}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) // http://www.mail-archive.com/netdev@vger.kernel.org/msg17214.html
+				pkt_copy = dev_alloc_skb(alloc_sz);
+#else			
+				pkt_copy = netdev_alloc_skb(secondary_padapter->pnetdev, alloc_sz);
+#endif		
+				if(pkt_copy)
+				{
+					pkt_copy->dev = secondary_padapter->pnetdev;
+					precvframe_if2->u.hdr.pkt = pkt_copy;
+					precvframe_if2->u.hdr.rx_head = pkt_copy->data;
+					precvframe_if2->u.hdr.rx_end = pkt_copy->data + alloc_sz;
+					skb_reserve( pkt_copy, 8 - ((SIZE_PTR)( pkt_copy->data ) & 7 ));//force pkt_copy->data at 8-byte alignment address
+					skb_reserve( pkt_copy, shift_sz );//force ip_hdr at 8-byte alignment address according to shift_sz.
+					_rtw_memcpy(pkt_copy->data, pbuf, skb_len);
+					precvframe_if2->u.hdr.rx_data = precvframe_if2->u.hdr.rx_tail = pkt_copy->data;
+					
+			
+					recvframe_put(precvframe_if2, skb_len);
+					if (pattrib->physt) 
+						update_recvframe_phyinfo_88e(precvframe_if2, (struct phy_stat*)pphy_status);
+					ret = rtw_recv_entry(precvframe_if2);			
+
+				} 
+				else {
+					rtw_free_recvframe(precvframe_if2, pfree_recv_queue);
+					DBG_8192C("%s()-%d: alloc_skb() failed!\n", __FUNCTION__, __LINE__);	
+				}
+
+			}
+			
+		}
+		
+	}
+	if (precvframe->u.hdr.attrib.physt)
+		update_recvframe_phyinfo_88e(precvframe, (struct phy_stat*)pphy_status);	
+	ret = rtw_recv_entry(precvframe);
+
+#endif
+
+	return ret;
+
+}
+
+#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX
+static int recvbuf2recvframe(_adapter *padapter, struct recv_buf *precvbuf)
+{
+	u8	*pbuf;
+	u8	shift_sz = 0;
+	u16	pkt_cnt, drvinfo_sz;
+	u32	pkt_offset, skb_len, alloc_sz;
+	s32	transfer_len;
+	struct recv_stat	*prxstat;
+	struct phy_stat	*pphy_status = NULL;
+	_pkt				*pkt_copy = NULL;
+	union recv_frame	*precvframe = NULL;
+	struct rx_pkt_attrib	*pattrib = NULL;
+	HAL_DATA_TYPE		*pHalData = GET_HAL_DATA(padapter);
+	struct recv_priv	*precvpriv = &padapter->recvpriv;
+	_queue			*pfree_recv_queue = &precvpriv->free_recv_queue;
+
+
+	transfer_len = (s32)precvbuf->transfer_len;	
+	pbuf = precvbuf->pbuf;
+
+	prxstat = (struct recv_stat *)pbuf;	
+	pkt_cnt = (le32_to_cpu(prxstat->rxdw2)>>16) & 0xff;
+
+#if 0 //temp remove when disable usb rx aggregation
+	if((pkt_cnt > 10) || (pkt_cnt < 1) || (transfer_len<RXDESC_SIZE) ||(pkt_len<=0))
+	{		
+		return _FAIL;
+	}
+#endif
+	
+	do{		
+		RT_TRACE(_module_rtl871x_recv_c_, _drv_info_,
+			 ("recvbuf2recvframe: rxdesc=offsset 0:0x%08x, 4:0x%08x, 8:0x%08x, C:0x%08x\n",
+			  prxstat->rxdw0, prxstat->rxdw1, prxstat->rxdw2, prxstat->rxdw4));
+
+		prxstat = (struct recv_stat *)pbuf;
+
+		precvframe = rtw_alloc_recvframe(pfree_recv_queue);
+		if(precvframe==NULL)
+		{
+			RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("recvbuf2recvframe: precvframe==NULL\n"));
+			DBG_8192C("%s()-%d: rtw_alloc_recvframe() failed! RX Drop!\n", __FUNCTION__, __LINE__);	
+			goto _exit_recvbuf2recvframe;
+		}
+
+		_rtw_init_listhead(&precvframe->u.hdr.list);	
+		precvframe->u.hdr.precvbuf = NULL;	//can't access the precvbuf for new arch.
+		precvframe->u.hdr.len=0;
+
+		//rtl8192c_query_rx_desc_status(precvframe, prxstat);
+		update_recvframe_attrib_88e(precvframe, prxstat);
+
+		pattrib = &precvframe->u.hdr.attrib;
+		
+#ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV			
+		//if(pattrib->pkt_len>2000){
+		//	printk("%s: RX Warning!pkt_len= %d, data rate=0x%02x \n", __FUNCTION__,pattrib->pkt_len,pattrib->mcs_rate);	
+		//}
+#endif					
+		if ((pattrib->crc_err) || (pattrib->icv_err))
+		{
+			
+				DBG_8192C("%s: RX Warning! crc_err=%d icv_err=%d, skip!\n", __FUNCTION__, pattrib->crc_err, pattrib->icv_err);
+#ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV		
+				printk("%s: RX Warning!pkt_len= %d, data rate=0x%02x \n", __FUNCTION__,pattrib->pkt_len,pattrib->mcs_rate);
+#endif
+			
+			rtw_free_recvframe(precvframe, pfree_recv_queue);
+			goto _exit_recvbuf2recvframe;
+		}
+			
+		
+		if( (pattrib->physt) && (pattrib->pkt_rpt_type == NORMAL_RX))
+		{
+			pphy_status = (struct phy_stat *)(pbuf + RXDESC_OFFSET);
+		}
+
+		pkt_offset = RXDESC_SIZE + pattrib->drvinfo_sz + pattrib->shift_sz + pattrib->pkt_len;
+
+		if((pattrib->pkt_len<=0) || (pkt_offset>transfer_len))
+		{	
+			RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("recvbuf2recvframe: pkt_len<=0\n"));
+			DBG_8192C("%s()-%d: RX Warning!\n", __FUNCTION__, __LINE__);	
+			rtw_free_recvframe(precvframe, pfree_recv_queue);
+			goto _exit_recvbuf2recvframe;
+		}
+
+		//	Modified by Albert 20101213
+		//	For 8 bytes IP header alignment.
+		if (pattrib->qos)	//	Qos data, wireless lan header length is 26
+		{
+			shift_sz = 6;
+		}
+		else
+		{
+			shift_sz = 0;
+		}
+
+		skb_len = pattrib->pkt_len;
+
+		// for first fragment packet, driver need allocate 1536+drvinfo_sz+RXDESC_SIZE to defrag packet.
+		// modify alloc_sz for recvive crc error packet by thomas 2011-06-02
+		if((pattrib->mfrag == 1)&&(pattrib->frag_num == 0)){
+			//alloc_sz = 1664;	//1664 is 128 alignment.
+			if(skb_len <= 1650)
+				alloc_sz = 1664;
+			else
+				alloc_sz = skb_len + 14;
+		}
+		else {
+			alloc_sz = skb_len;
+			//	6 is for IP header 8 bytes alignment in QoS packet case.
+			//	8 is for skb->data 4 bytes alignment.
+			alloc_sz += 14;
+		}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) // http://www.mail-archive.com/netdev@vger.kernel.org/msg17214.html
+		pkt_copy = dev_alloc_skb(alloc_sz);
+#else			
+		pkt_copy = netdev_alloc_skb(padapter->pnetdev, alloc_sz);
+#endif		
+		if(pkt_copy)
+		{
+			pkt_copy->dev = padapter->pnetdev;
+			precvframe->u.hdr.pkt = pkt_copy;
+			precvframe->u.hdr.rx_head = pkt_copy->data;
+			precvframe->u.hdr.rx_end = pkt_copy->data + alloc_sz;
+			skb_reserve( pkt_copy, 8 - ((SIZE_PTR)( pkt_copy->data ) & 7 ));//force pkt_copy->data at 8-byte alignment address
+			skb_reserve( pkt_copy, shift_sz );//force ip_hdr at 8-byte alignment address according to shift_sz.
+			_rtw_memcpy(pkt_copy->data, (pbuf + pattrib->drvinfo_sz + RXDESC_SIZE), skb_len);
+			precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail = pkt_copy->data;
+		}
+		else
+		{
+			DBG_8192C("recvbuf2recvframe:can not allocate memory for skb copy\n");
+			//precvframe->u.hdr.pkt = skb_clone(pskb, GFP_ATOMIC);
+			//precvframe->u.hdr.rx_head = precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail = pbuf;
+			//precvframe->u.hdr.rx_end = pbuf + (pkt_offset>1612?pkt_offset:1612);
+
+			precvframe->u.hdr.pkt = NULL;
+			rtw_free_recvframe(precvframe, pfree_recv_queue);
+
+			goto _exit_recvbuf2recvframe;
+		}
+
+		recvframe_put(precvframe, skb_len);
+		//recvframe_pull(precvframe, drvinfo_sz + RXDESC_SIZE);	
+
+#ifdef CONFIG_USB_RX_AGGREGATION
+		switch(pHalData->UsbRxAggMode)
+		{
+			case USB_RX_AGG_DMA:
+			case USB_RX_AGG_MIX:
+				pkt_offset = (u16)_RND128(pkt_offset);
+				break;
+				case USB_RX_AGG_USB:
+				pkt_offset = (u16)_RND4(pkt_offset);
+				break;
+			case USB_RX_AGG_DISABLE:			
+			default:				
+				break;
+		}
+#endif
+
+		if(pattrib->pkt_rpt_type == NORMAL_RX)//Normal rx packet
+		{
+#ifdef CONFIG_CONCURRENT_MODE
+			if(rtw_buddy_adapter_up(padapter))
+			{
+				if(pre_recv_entry(precvframe, prxstat, pphy_status) != _SUCCESS)
+				{
+					RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,
+						("recvbuf2recvframe: recv_entry(precvframe) != _SUCCESS\n"));
+				}
+			}
+			else
+#endif				
+			{
+				if (pattrib->physt) 
+					update_recvframe_phyinfo_88e(precvframe, (struct phy_stat*)pphy_status);
+				if(rtw_recv_entry(precvframe) != _SUCCESS)
+				{
+					RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,
+						("recvbuf2recvframe: rtw_recv_entry(precvframe) != _SUCCESS\n"));
+				}
+			}
+
+		}
+		else{ // pkt_rpt_type == TX_REPORT1-CCX, TX_REPORT2-TX RTP,HIS_REPORT-USB HISR RTP
+				
+			//enqueue recvframe to txrtp queue
+			if(pattrib->pkt_rpt_type == TX_REPORT1){
+				//DBG_8192C("rx CCX \n");
+				//CCX-TXRPT ack for xmit mgmt frames.
+				handle_txrpt_ccx_88e(padapter, precvframe->u.hdr.rx_data);
+				
+			}
+			else if(pattrib->pkt_rpt_type == TX_REPORT2){
+				//DBG_8192C("rx TX RPT \n");
+				ODM_RA_TxRPT2Handle_8188E(
+							&pHalData->odmpriv,
+							precvframe->u.hdr.rx_data,
+							pattrib->pkt_len,
+							pattrib->MacIDValidEntry[0],
+							pattrib->MacIDValidEntry[1]
+							);
+				
+			}
+			else if(pattrib->pkt_rpt_type == HIS_REPORT)
+			{
+				//DBG_8192C("%s , rx USB HISR \n",__FUNCTION__);
+				#ifdef CONFIG_SUPPORT_USB_INT
+				interrupt_handler_8188eu(padapter,pattrib->pkt_len,precvframe->u.hdr.rx_data);
+				#endif
+			}				
+			rtw_free_recvframe(precvframe, pfree_recv_queue);			
+			
+		}	
+
+		pkt_cnt--;
+		transfer_len -= pkt_offset;
+		pbuf += pkt_offset;	
+		precvframe = NULL;
+		pkt_copy = NULL;
+
+		if(transfer_len>0 && pkt_cnt==0)
+			pkt_cnt = (le32_to_cpu(prxstat->rxdw2)>>16) & 0xff;
+
+	}while((transfer_len>0) && (pkt_cnt>0));
+
+_exit_recvbuf2recvframe:
+
+	return _SUCCESS;
+}
+
+void rtl8188eu_recv_tasklet(void *priv)
+{	
+	struct recv_buf *precvbuf = NULL;
+	_adapter	*padapter = (_adapter*)priv;
+	struct recv_priv	*precvpriv = &padapter->recvpriv;
+
+	while (NULL != (precvbuf = rtw_dequeue_recvbuf(&precvpriv->recv_buf_pending_queue)))
+	{
+		if ((padapter->bDriverStopped == _TRUE)||(padapter->bSurpriseRemoved== _TRUE))
+		{
+			DBG_8192C("recv_tasklet => bDriverStopped or bSurpriseRemoved \n");
+			
+			break;
+		}
+		
+
+		recvbuf2recvframe(padapter, precvbuf);
+
+		rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf);
+	}	
+	
+}
+
+static void usb_read_port_complete(struct urb *purb, struct pt_regs *regs)
+{	
+	struct recv_buf	*precvbuf = (struct recv_buf *)purb->context;	
+	_adapter 			*padapter =(_adapter *)precvbuf->adapter;
+	struct recv_priv	*precvpriv = &padapter->recvpriv;
+
+	RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete!!!\n"));
+	
+	precvpriv->rx_pending_cnt --;
+		
+	if(padapter->bSurpriseRemoved || padapter->bDriverStopped||padapter->bReadPortCancel)
+	{
+		RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bDriverStopped(%d) OR bSurpriseRemoved(%d)\n", padapter->bDriverStopped, padapter->bSurpriseRemoved));		
+		DBG_8192C("%s() RX Warning! bDriverStopped(%d) OR bSurpriseRemoved(%d) bReadPortCancel(%d)\n", 
+		__FUNCTION__,padapter->bDriverStopped, padapter->bSurpriseRemoved,padapter->bReadPortCancel);	
+		goto exit;
+	}
+
+	if(purb->status==0)//SUCCESS
+	{
+		if ((purb->actual_length > MAX_RECVBUF_SZ) || (purb->actual_length < RXDESC_SIZE))
+		{
+			RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete: (purb->actual_length > MAX_RECVBUF_SZ) || (purb->actual_length < RXDESC_SIZE)\n"));
+
+			rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf);
+		}
+		else 
+		{			
+			rtw_reset_continual_urb_error(adapter_to_dvobj(padapter));
+			
+			precvbuf->transfer_len = purb->actual_length;	
+
+			//rtw_enqueue_rx_transfer_buffer(precvpriv, rx_transfer_buf);			
+			rtw_enqueue_recvbuf(precvbuf, &precvpriv->recv_buf_pending_queue);
+
+			tasklet_schedule(&precvpriv->recv_tasklet);			
+		}		
+	}
+	else
+	{
+		RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete : purb->status(%d) != 0 \n", purb->status));
+	
+		DBG_8192C("###=> usb_read_port_complete => urb status(%d)\n", purb->status);
+
+		if(rtw_inc_and_chk_continual_urb_error(adapter_to_dvobj(padapter)) == _TRUE ){
+			padapter->bSurpriseRemoved = _TRUE;
+		}
+
+		switch(purb->status) {
+			case -EINVAL:
+			case -EPIPE:			
+			case -ENODEV:
+			case -ESHUTDOWN:
+				//padapter->bSurpriseRemoved=_TRUE;
+				RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bSurpriseRemoved=TRUE\n"));
+			case -ENOENT:
+				padapter->bDriverStopped=_TRUE;			
+				RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bDriverStopped=TRUE\n"));
+				break;
+			case -EPROTO:
+			case -EILSEQ:
+			case -ETIME:
+			case -ECOMM:
+			case -EOVERFLOW:
+				#ifdef DBG_CONFIG_ERROR_DETECT	
+				{	
+					HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+					pHalData->srestpriv.Wifi_Error_Status = USB_READ_PORT_FAIL;			
+				}
+				#endif
+				rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf);			
+				break;
+			case -EINPROGRESS:
+				DBG_8192C("ERROR: URB IS IN PROGRESS!/n");
+				break;
+			default:
+				break;				
+		}
+		
+	}	
+
+exit:	
+	
+_func_exit_;
+	
+}
+
+static u32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem)
+{		
+	int err;
+	unsigned int pipe;
+	u32 ret = _SUCCESS;
+	PURB purb = NULL;	
+	struct recv_buf	*precvbuf = (struct recv_buf *)rmem;
+	_adapter		*adapter = pintfhdl->padapter;
+	struct dvobj_priv	*pdvobj = adapter_to_dvobj(adapter);
+	struct recv_priv	*precvpriv = &adapter->recvpriv;
+	struct usb_device	*pusbd = pdvobj->pusbdev;
+
+_func_enter_;
+	
+	if(adapter->bDriverStopped || adapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)
+	{
+		RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port:( padapter->bDriverStopped ||padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n"));
+		return _FAIL;
+	}
+
+	if(precvbuf !=NULL)
+	{	
+		rtl8188eu_init_recvbuf(adapter, precvbuf);
+
+		if(precvbuf->pbuf)
+		{			
+			precvpriv->rx_pending_cnt++;
+		
+			purb = precvbuf->purb;		
+
+			//translate DMA FIFO addr to pipehandle
+			pipe = ffaddr2pipehdl(pdvobj, addr);	
+
+			usb_fill_bulk_urb(purb, pusbd, pipe, 
+						precvbuf->pbuf,
+                				MAX_RECVBUF_SZ,
+                				usb_read_port_complete,
+                				precvbuf);//context is precvbuf
+
+			purb->transfer_dma = precvbuf->dma_transfer_addr;
+			purb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP;								
+
+			err = usb_submit_urb(purb, GFP_ATOMIC);	
+			if((err) && (err != (-EPERM)))
+			{
+				RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("cannot submit rx in-token(err=0x%.8x), URB_STATUS =0x%.8x", err, purb->status));
+				DBG_8192C("cannot submit rx in-token(err = 0x%08x),urb_status = %d\n",err,purb->status);
+				ret = _FAIL;
+			}
+			
+		}
+			
+	}
+	else
+	{
+		RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port:precvbuf ==NULL\n"));
+		ret = _FAIL;
+	}
+
+_func_exit_;
+
+	return ret;
+}
+#else	// CONFIG_USE_USB_BUFFER_ALLOC_RX
+static int recvbuf2recvframe(_adapter *padapter, _pkt *pskb)
+{
+	u8	*pbuf;
+	u8	shift_sz = 0;
+	u16	pkt_cnt;
+	u32	pkt_offset, skb_len, alloc_sz;
+	s32	transfer_len;
+	struct recv_stat	*prxstat;
+	struct phy_stat	*pphy_status = NULL;
+	_pkt				*pkt_copy = NULL;
+	union recv_frame	*precvframe = NULL;
+	struct rx_pkt_attrib	*pattrib = NULL;
+	HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+	struct recv_priv	*precvpriv = &padapter->recvpriv;
+	_queue			*pfree_recv_queue = &precvpriv->free_recv_queue;
+
+
+	transfer_len = (s32)pskb->len;	
+	pbuf = pskb->data;
+
+	prxstat = (struct recv_stat *)pbuf;	
+	pkt_cnt = (le32_to_cpu(prxstat->rxdw2)>>16) & 0xff;
+
+#if 0 //temp remove when disable usb rx aggregation
+	if((pkt_cnt > 10) || (pkt_cnt < 1) || (transfer_len<RXDESC_SIZE) ||(pkt_len<=0))
+	{		
+		return _FAIL;
+	}
+#endif
+	do{		
+		RT_TRACE(_module_rtl871x_recv_c_, _drv_info_,
+			 ("recvbuf2recvframe: rxdesc=offsset 0:0x%08x, 4:0x%08x, 8:0x%08x, C:0x%08x\n",
+			  prxstat->rxdw0, prxstat->rxdw1, prxstat->rxdw2, prxstat->rxdw4));
+
+		prxstat = (struct recv_stat *)pbuf;
+
+		precvframe = rtw_alloc_recvframe(pfree_recv_queue);
+		if(precvframe==NULL)
+		{
+			RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("recvbuf2recvframe: precvframe==NULL\n"));
+			DBG_8192C("%s()-%d: rtw_alloc_recvframe() failed! RX Drop!\n", __FUNCTION__, __LINE__);	
+			goto _exit_recvbuf2recvframe;
+		}
+
+		_rtw_init_listhead(&precvframe->u.hdr.list);	
+		precvframe->u.hdr.precvbuf = NULL;	//can't access the precvbuf for new arch.
+		precvframe->u.hdr.len=0;
+
+		//rtl8192c_query_rx_desc_status(precvframe, prxstat);
+		update_recvframe_attrib_88e(precvframe, prxstat);
+
+		pattrib = &precvframe->u.hdr.attrib;		
+				
+		if ((pattrib->crc_err) || (pattrib->icv_err))
+		{
+			DBG_8192C("%s: RX Warning! crc_err=%d icv_err=%d, skip!\n", __FUNCTION__, pattrib->crc_err, pattrib->icv_err);
+
+			rtw_free_recvframe(precvframe, pfree_recv_queue);
+			goto _exit_recvbuf2recvframe;
+		}
+
+		if( (pattrib->physt) && (pattrib->pkt_rpt_type == NORMAL_RX))
+		{
+			pphy_status = (struct phy_stat *)(pbuf + RXDESC_OFFSET);
+		}
+
+		pkt_offset = RXDESC_SIZE + pattrib->drvinfo_sz + pattrib->shift_sz + pattrib->pkt_len;
+
+		if((pattrib->pkt_len<=0) || (pkt_offset>transfer_len))
+		{	
+			RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("recvbuf2recvframe: pkt_len<=0\n"));
+			DBG_8192C("%s()-%d: RX Warning!,pkt_len<=0 or pkt_offset> transfoer_len \n", __FUNCTION__, __LINE__);	
+			rtw_free_recvframe(precvframe, pfree_recv_queue);
+			goto _exit_recvbuf2recvframe;
+		}
+	
+		//	Modified by Albert 20101213
+		//	For 8 bytes IP header alignment.
+		if (pattrib->qos)	//	Qos data, wireless lan header length is 26
+		{
+			shift_sz = 6;
+		}
+		else
+		{
+			shift_sz = 0;
+		}
+
+		skb_len = pattrib->pkt_len;
+
+		// for first fragment packet, driver need allocate 1536+drvinfo_sz+RXDESC_SIZE to defrag packet.
+		// modify alloc_sz for recvive crc error packet by thomas 2011-06-02
+		if((pattrib->mfrag == 1)&&(pattrib->frag_num == 0)){
+			//alloc_sz = 1664;	//1664 is 128 alignment.
+			if(skb_len <= 1650)
+				alloc_sz = 1664;
+			else
+				alloc_sz = skb_len + 14;
+		}
+		else {
+			alloc_sz = skb_len;
+			//	6 is for IP header 8 bytes alignment in QoS packet case.
+			//	8 is for skb->data 4 bytes alignment.
+			alloc_sz += 14;
+		}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) // http://www.mail-archive.com/netdev@vger.kernel.org/msg17214.html
+		pkt_copy = dev_alloc_skb(alloc_sz);
+#else			
+		pkt_copy = netdev_alloc_skb(padapter->pnetdev, alloc_sz);
+#endif		
+		if(pkt_copy)
+		{
+			pkt_copy->dev = padapter->pnetdev;
+			precvframe->u.hdr.pkt = pkt_copy;
+			precvframe->u.hdr.rx_head = pkt_copy->data;
+			precvframe->u.hdr.rx_end = pkt_copy->data + alloc_sz;
+			skb_reserve( pkt_copy, 8 - ((SIZE_PTR)( pkt_copy->data ) & 7 ));//force pkt_copy->data at 8-byte alignment address
+			skb_reserve( pkt_copy, shift_sz );//force ip_hdr at 8-byte alignment address according to shift_sz.
+			_rtw_memcpy(pkt_copy->data, (pbuf + pattrib->drvinfo_sz + RXDESC_SIZE), skb_len);
+			precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail = pkt_copy->data;
+		}
+		else
+		{
+			if((pattrib->mfrag == 1)&&(pattrib->frag_num == 0))
+			{				
+				DBG_8192C("recvbuf2recvframe: alloc_skb fail , drop frag frame \n");
+				rtw_free_recvframe(precvframe, pfree_recv_queue);
+				goto _exit_recvbuf2recvframe;
+			}
+			
+			precvframe->u.hdr.pkt = skb_clone(pskb, GFP_ATOMIC);
+			if(precvframe->u.hdr.pkt)
+			{
+				precvframe->u.hdr.rx_head = precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail 
+					= pbuf+ pattrib->drvinfo_sz + RXDESC_SIZE;
+				precvframe->u.hdr.rx_end =  pbuf +pattrib->drvinfo_sz + RXDESC_SIZE+ alloc_sz;
+			}
+			else
+			{
+				DBG_8192C("recvbuf2recvframe: skb_clone fail\n");
+				rtw_free_recvframe(precvframe, pfree_recv_queue);
+				goto _exit_recvbuf2recvframe;
+			}
+			
+		}
+
+		recvframe_put(precvframe, skb_len);
+		//recvframe_pull(precvframe, drvinfo_sz + RXDESC_SIZE);	
+
+#ifdef CONFIG_USB_RX_AGGREGATION
+		switch(pHalData->UsbRxAggMode)
+		{
+			case USB_RX_AGG_DMA:
+			case USB_RX_AGG_MIX:
+				pkt_offset = (u16)_RND128(pkt_offset);
+				break;
+				case USB_RX_AGG_USB:
+				pkt_offset = (u16)_RND4(pkt_offset);
+				break;
+			case USB_RX_AGG_DISABLE:			
+			default:				
+				break;
+		}
+#endif
+
+		if(pattrib->pkt_rpt_type == NORMAL_RX)//Normal rx packet
+		{
+#ifdef CONFIG_CONCURRENT_MODE
+			if(rtw_buddy_adapter_up(padapter))
+			{
+				if(pre_recv_entry(precvframe, prxstat, pphy_status) != _SUCCESS)
+				{
+					RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,
+						("recvbuf2recvframe: recv_entry(precvframe) != _SUCCESS\n"));
+				}
+			}
+			else
+#endif
+			{
+				if (pattrib->physt) 
+					update_recvframe_phyinfo_88e(precvframe, (struct phy_stat*)pphy_status);
+				if(rtw_recv_entry(precvframe) != _SUCCESS)
+				{
+					RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,
+						("recvbuf2recvframe: rtw_recv_entry(precvframe) != _SUCCESS\n"));
+				}
+			}
+		}
+		else{ // pkt_rpt_type == TX_REPORT1-CCX, TX_REPORT2-TX RTP,HIS_REPORT-USB HISR RTP
+				
+			//enqueue recvframe to txrtp queue
+			if(pattrib->pkt_rpt_type == TX_REPORT1){
+				//DBG_8192C("rx CCX \n");
+				//CCX-TXRPT ack for xmit mgmt frames.
+				handle_txrpt_ccx_88e(padapter, precvframe->u.hdr.rx_data);
+			}
+			else if(pattrib->pkt_rpt_type == TX_REPORT2){
+				//DBG_8192C("rx TX RPT \n");
+				ODM_RA_TxRPT2Handle_8188E(
+							&pHalData->odmpriv,
+							precvframe->u.hdr.rx_data,
+							pattrib->pkt_len,
+							pattrib->MacIDValidEntry[0],
+							pattrib->MacIDValidEntry[1]
+							);
+				
+			}
+			else if(pattrib->pkt_rpt_type == HIS_REPORT)
+			{
+				//DBG_8192C("%s , rx USB HISR \n",__FUNCTION__);
+				#ifdef CONFIG_SUPPORT_USB_INT
+				interrupt_handler_8188eu(padapter,pattrib->pkt_len,precvframe->u.hdr.rx_data);
+				#endif
+			}				
+			rtw_free_recvframe(precvframe, pfree_recv_queue);			
+			
+		}
+	
+		pkt_cnt--;
+		transfer_len -= pkt_offset;
+		pbuf += pkt_offset;	
+		precvframe = NULL;
+		pkt_copy = NULL;
+
+		if(transfer_len>0 && pkt_cnt==0)
+			pkt_cnt = (le32_to_cpu(prxstat->rxdw2)>>16) & 0xff;
+
+	}while((transfer_len>0) && (pkt_cnt>0));
+
+_exit_recvbuf2recvframe:
+
+	return _SUCCESS;	
+}
+
+void rtl8188eu_recv_tasklet(void *priv)
+{
+	_pkt			*pskb;
+	_adapter		*padapter = (_adapter*)priv;
+	struct recv_priv	*precvpriv = &padapter->recvpriv;
+	
+	while (NULL != (pskb = skb_dequeue(&precvpriv->rx_skb_queue)))
+	{
+		if ((padapter->bDriverStopped == _TRUE)||(padapter->bSurpriseRemoved== _TRUE))
+		{
+			DBG_8192C("recv_tasklet => bDriverStopped or bSurpriseRemoved \n");
+			dev_kfree_skb_any(pskb);
+			break;
+		}
+	
+		recvbuf2recvframe(padapter, pskb);
+
+#ifdef CONFIG_PREALLOC_RECV_SKB
+
+		skb_reset_tail_pointer(pskb);
+
+		pskb->len = 0;
+		
+		skb_queue_tail(&precvpriv->free_recv_skb_queue, pskb);
+		
+#else
+		dev_kfree_skb_any(pskb);
+#endif
+				
+	}
+	
+}
+
+
+static void usb_read_port_complete(struct urb *purb, struct pt_regs *regs)
+{
+	_irqL irqL;
+	uint isevt, *pbuf;
+	struct recv_buf	*precvbuf = (struct recv_buf *)purb->context;	
+	_adapter 			*padapter =(_adapter *)precvbuf->adapter;
+	struct recv_priv	*precvpriv = &padapter->recvpriv;	
+	
+	RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete!!!\n"));
+	
+	//_enter_critical(&precvpriv->lock, &irqL);
+	//precvbuf->irp_pending=_FALSE;
+	//precvpriv->rx_pending_cnt --;
+	//_exit_critical(&precvpriv->lock, &irqL);
+		
+	precvpriv->rx_pending_cnt --;
+		
+	//if(precvpriv->rx_pending_cnt== 0)
+	//{		
+	//	RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete: rx_pending_cnt== 0, set allrxreturnevt!\n"));
+	//	_rtw_up_sema(&precvpriv->allrxreturnevt);	
+	//}
+
+	if(padapter->bSurpriseRemoved || padapter->bDriverStopped||padapter->bReadPortCancel)
+	{
+		RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bDriverStopped(%d) OR bSurpriseRemoved(%d)\n", padapter->bDriverStopped, padapter->bSurpriseRemoved));		
+		
+	#ifdef CONFIG_PREALLOC_RECV_SKB
+		precvbuf->reuse = _TRUE;
+	#else
+		if(precvbuf->pskb){
+			DBG_8192C("==> free skb(%p)\n",precvbuf->pskb);
+			dev_kfree_skb_any(precvbuf->pskb);				
+		}	
+	#endif
+		DBG_8192C("%s() RX Warning! bDriverStopped(%d) OR bSurpriseRemoved(%d) bReadPortCancel(%d)\n", 
+		__FUNCTION__,padapter->bDriverStopped, padapter->bSurpriseRemoved,padapter->bReadPortCancel);	
+		goto exit;
+	}
+
+	if(purb->status==0)//SUCCESS
+	{
+		if ((purb->actual_length > MAX_RECVBUF_SZ) || (purb->actual_length < RXDESC_SIZE))
+		{
+			RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete: (purb->actual_length > MAX_RECVBUF_SZ) || (purb->actual_length < RXDESC_SIZE)\n"));
+			precvbuf->reuse = _TRUE;
+			rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf);
+			DBG_8192C("%s()-%d: RX Warning!\n", __FUNCTION__, __LINE__);	
+		}
+		else 
+		{	
+			rtw_reset_continual_urb_error(adapter_to_dvobj(padapter));
+			
+			precvbuf->transfer_len = purb->actual_length;			
+			skb_put(precvbuf->pskb, purb->actual_length);	
+			skb_queue_tail(&precvpriv->rx_skb_queue, precvbuf->pskb);
+
+			if (skb_queue_len(&precvpriv->rx_skb_queue)<=1)
+				tasklet_schedule(&precvpriv->recv_tasklet);
+
+			precvbuf->pskb = NULL;
+			precvbuf->reuse = _FALSE;
+			rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf);			
+		}		
+	}
+	else
+	{
+		RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete : purb->status(%d) != 0 \n", purb->status));
+	
+		DBG_8192C("###=> usb_read_port_complete => urb status(%d)\n", purb->status);
+
+		if(rtw_inc_and_chk_continual_urb_error(adapter_to_dvobj(padapter)) == _TRUE ){
+			padapter->bSurpriseRemoved = _TRUE;
+		}
+
+		switch(purb->status) {
+			case -EINVAL:
+			case -EPIPE:			
+			case -ENODEV:
+			case -ESHUTDOWN:
+				//padapter->bSurpriseRemoved=_TRUE;
+				RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bSurpriseRemoved=TRUE\n"));
+			case -ENOENT:
+				padapter->bDriverStopped=_TRUE;			
+				RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bDriverStopped=TRUE\n"));
+				break;
+			case -EPROTO:
+			case -EILSEQ:
+			case -ETIME:
+			case -ECOMM:
+			case -EOVERFLOW:
+				#ifdef DBG_CONFIG_ERROR_DETECT	
+				{	
+					HAL_DATA_TYPE	*pHalData = GET_HAL_DATA(padapter);
+					pHalData->srestpriv.Wifi_Error_Status = USB_READ_PORT_FAIL;			
+				}
+				#endif
+				precvbuf->reuse = _TRUE;
+				rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf);			
+				break;
+			case -EINPROGRESS:
+				DBG_8192C("ERROR: URB IS IN PROGRESS!/n");
+				break;
+			default:
+				break;				
+		}
+		
+	}	
+
+exit:	
+	
+_func_exit_;
+	
+}
+
+static u32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem)
+{	
+	_irqL irqL;
+	int err;
+	unsigned int pipe;
+	SIZE_PTR tmpaddr=0;
+	SIZE_PTR alignment=0;
+	u32 ret = _SUCCESS;
+	PURB purb = NULL;
+	struct recv_buf	*precvbuf = (struct recv_buf *)rmem;
+	_adapter		*adapter = pintfhdl->padapter;
+	struct dvobj_priv	*pdvobj = adapter_to_dvobj(adapter);
+	struct recv_priv	*precvpriv = &adapter->recvpriv;
+	struct usb_device	*pusbd = pdvobj->pusbdev;
+	
+
+_func_enter_;
+	
+	if(adapter->bDriverStopped || adapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)
+	{
+		RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port:( padapter->bDriverStopped ||padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n"));
+		return _FAIL;
+	}
+
+#ifdef CONFIG_PREALLOC_RECV_SKB
+	if((precvbuf->reuse == _FALSE) || (precvbuf->pskb == NULL))
+	{
+		if (NULL != (precvbuf->pskb = skb_dequeue(&precvpriv->free_recv_skb_queue)))
+		{
+			precvbuf->reuse = _TRUE;
+		}
+	}
+#endif
+	
+
+	if(precvbuf !=NULL)
+	{	
+		rtl8188eu_init_recvbuf(adapter, precvbuf);		
+
+		//re-assign for linux based on skb
+		if((precvbuf->reuse == _FALSE) || (precvbuf->pskb == NULL))
+		{
+			//precvbuf->pskb = alloc_skb(MAX_RECVBUF_SZ, GFP_ATOMIC);//don't use this after v2.6.25
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) // http://www.mail-archive.com/netdev@vger.kernel.org/msg17214.html
+			precvbuf->pskb = dev_alloc_skb(MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ);
+#else			
+			precvbuf->pskb = netdev_alloc_skb(adapter->pnetdev, MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ);
+#endif			
+			if(precvbuf->pskb == NULL)		
+			{
+				RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("init_recvbuf(): alloc_skb fail!\n"));
+				DBG_8192C("#### usb_read_port() alloc_skb fail!#####\n");
+				return _FAIL;
+			}	
+
+			tmpaddr = (SIZE_PTR)precvbuf->pskb->data;
+	        	alignment = tmpaddr & (RECVBUFF_ALIGN_SZ-1);
+			skb_reserve(precvbuf->pskb, (RECVBUFF_ALIGN_SZ - alignment));
+
+			precvbuf->phead = precvbuf->pskb->head;
+		   	precvbuf->pdata = precvbuf->pskb->data;
+			precvbuf->ptail = skb_tail_pointer(precvbuf->pskb);
+			precvbuf->pend = skb_end_pointer(precvbuf->pskb);
+			precvbuf->pbuf = precvbuf->pskb->data;
+		}	
+		else//reuse skb
+		{
+			precvbuf->phead = precvbuf->pskb->head;
+			precvbuf->pdata = precvbuf->pskb->data;
+			precvbuf->ptail = skb_tail_pointer(precvbuf->pskb);
+			precvbuf->pend = skb_end_pointer(precvbuf->pskb);
+       		precvbuf->pbuf = precvbuf->pskb->data;
+
+			precvbuf->reuse = _FALSE;
+		}
+
+		//_enter_critical(&precvpriv->lock, &irqL);
+		//precvpriv->rx_pending_cnt++;
+		//precvbuf->irp_pending = _TRUE;
+		//_exit_critical(&precvpriv->lock, &irqL);
+
+		precvpriv->rx_pending_cnt++;
+
+		purb = precvbuf->purb;
+
+		//translate DMA FIFO addr to pipehandle
+		pipe = ffaddr2pipehdl(pdvobj, addr);
+
+		usb_fill_bulk_urb(purb, pusbd, pipe, 
+						precvbuf->pbuf,
+                				MAX_RECVBUF_SZ,
+                				usb_read_port_complete,
+                				precvbuf);//context is precvbuf
+
+		err = usb_submit_urb(purb, GFP_ATOMIC);
+		if((err) && (err != (-EPERM)))
+		{
+			RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("cannot submit rx in-token(err=0x%.8x), URB_STATUS =0x%.8x", err, purb->status));
+			DBG_8192C("cannot submit rx in-token(err = 0x%08x),urb_status = %d\n",err,purb->status);
+			ret = _FAIL;
+		}
+	}
+	else
+	{
+		RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port:precvbuf ==NULL\n"));
+		ret = _FAIL;
+	}
+
+_func_exit_;
+
+	return ret;
+}
+#endif	// CONFIG_USE_USB_BUFFER_ALLOC_RX
+
+void rtl8188eu_xmit_tasklet(void *priv)
+{	
+	int ret = _FALSE;
+	_adapter *padapter = (_adapter*)priv;
+	struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+
+	if(check_fwstate(&padapter->mlmepriv, _FW_UNDER_SURVEY) == _TRUE)
+		return;
+
+	while(1)
+	{
+		if ((padapter->bDriverStopped == _TRUE)||(padapter->bSurpriseRemoved== _TRUE) || (padapter->bWritePortCancel == _TRUE))
+		{
+			DBG_8192C("xmit_tasklet => bDriverStopped or bSurpriseRemoved or bWritePortCancel\n");
+			break;
+		}
+
+		ret = rtl8188eu_xmitframe_complete(padapter, pxmitpriv, NULL);
+
+		if(ret==_FALSE)
+			break;
+		
+	}
+	
+}
+
+void rtl8188eu_set_intf_ops(struct _io_ops	*pops)
+{		
+	_func_enter_;		
+
+	_rtw_memset((u8 *)pops, 0, sizeof(struct _io_ops));	
+
+	pops->_read8 = &usb_read8;
+	pops->_read16 = &usb_read16;
+	pops->_read32 = &usb_read32;
+	pops->_read_mem = &usb_read_mem;
+	pops->_read_port = &usb_read_port;	
+	
+	pops->_write8 = &usb_write8;
+	pops->_write16 = &usb_write16;
+	pops->_write32 = &usb_write32;
+	pops->_writeN = &usb_writeN;
+	
+#ifdef CONFIG_USB_SUPPORT_ASYNC_VDN_REQ	
+	pops->_write8_async= &usb_async_write8;
+	pops->_write16_async = &usb_async_write16;
+	pops->_write32_async = &usb_async_write32;
+#endif	
+	pops->_write_mem = &usb_write_mem;
+	pops->_write_port = &usb_write_port;
+
+	pops->_read_port_cancel = &usb_read_port_cancel;
+	pops->_write_port_cancel = &usb_write_port_cancel;
+
+#ifdef CONFIG_USB_INTERRUPT_IN_PIPE
+	pops->_read_interrupt = &usb_read_interrupt;
+#endif
+
+	_func_exit_;
+
+}
+
+void rtl8188eu_set_hw_type(_adapter *padapter)
+{
+	padapter->chip_type = RTL8188E;
+	padapter->HardwareType = HARDWARE_TYPE_RTL8188EU;
+	DBG_871X("CHIP TYPE: RTL8188E\n");
+}
+