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| author | Srikant Patnaik | 2015-01-11 12:28:04 +0530 |
|---|---|---|
| committer | Srikant Patnaik | 2015-01-11 12:28:04 +0530 |
| commit | 871480933a1c28f8a9fed4c4d34d06c439a7a422 (patch) | |
| tree | 8718f573808810c2a1e8cb8fb6ac469093ca2784 /arch/arm/mach-sa1100/include/mach/debug-macro.S | |
| parent | 9d40ac5867b9aefe0722bc1f110b965ff294d30d (diff) | |
| download | FOSSEE-netbook-kernel-source-871480933a1c28f8a9fed4c4d34d06c439a7a422.tar.gz FOSSEE-netbook-kernel-source-871480933a1c28f8a9fed4c4d34d06c439a7a422.tar.bz2 FOSSEE-netbook-kernel-source-871480933a1c28f8a9fed4c4d34d06c439a7a422.zip | |
Moved, renamed, and deleted files
The original directory structure was scattered and unorganized.
Changes are basically to make it look like kernel structure.
Diffstat (limited to 'arch/arm/mach-sa1100/include/mach/debug-macro.S')
| -rw-r--r-- | arch/arm/mach-sa1100/include/mach/debug-macro.S | 62 |
1 files changed, 62 insertions, 0 deletions
diff --git a/arch/arm/mach-sa1100/include/mach/debug-macro.S b/arch/arm/mach-sa1100/include/mach/debug-macro.S new file mode 100644 index 00000000..530772d9 --- /dev/null +++ b/arch/arm/mach-sa1100/include/mach/debug-macro.S @@ -0,0 +1,62 @@ +/* arch/arm/mach-sa1100/include/mach/debug-macro.S + * + * Debugging macro include header + * + * Copyright (C) 1994-1999 Russell King + * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * +*/ +#include <mach/hardware.h> + + .macro addruart, rp, rv, tmp + mrc p15, 0, \rp, c1, c0 + tst \rp, #1 @ MMU enabled? + moveq \rp, #0x80000000 @ physical base address + movne \rp, #0xf8000000 @ virtual address + + @ We probe for the active serial port here, coherently with + @ the comment in arch/arm/mach-sa1100/include/mach/uncompress.h. + @ We assume r1 can be clobbered. + + @ see if Ser3 is active + add \rp, \rp, #0x00050000 + ldr \rv, [\rp, #UTCR3] + tst \rv, #UTCR3_TXE + + @ if Ser3 is inactive, then try Ser1 + addeq \rp, \rp, #(0x00010000 - 0x00050000) + ldreq \rv, [\rp, #UTCR3] + tsteq \rv, #UTCR3_TXE + + @ if Ser1 is inactive, then try Ser2 + addeq \rp, \rp, #(0x00030000 - 0x00010000) + ldreq \rv, [\rp, #UTCR3] + tsteq \rv, #UTCR3_TXE + + @ clear top bits, and generate both phys and virt addresses + lsl \rp, \rp, #8 + lsr \rp, \rp, #8 + orr \rv, \rp, #0xf8000000 @ virtual + orr \rp, \rp, #0x80000000 @ physical + + .endm + + .macro senduart,rd,rx + str \rd, [\rx, #UTDR] + .endm + + .macro waituart,rd,rx +1001: ldr \rd, [\rx, #UTSR1] + tst \rd, #UTSR1_TNF + beq 1001b + .endm + + .macro busyuart,rd,rx +1001: ldr \rd, [\rx, #UTSR1] + tst \rd, #UTSR1_TBY + bne 1001b + .endm |