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| author | Srikant Patnaik | 2015-01-11 12:28:04 +0530 |
|---|---|---|
| committer | Srikant Patnaik | 2015-01-11 12:28:04 +0530 |
| commit | 871480933a1c28f8a9fed4c4d34d06c439a7a422 (patch) | |
| tree | 8718f573808810c2a1e8cb8fb6ac469093ca2784 /ANDROID_3.4.5/include/video | |
| parent | 9d40ac5867b9aefe0722bc1f110b965ff294d30d (diff) | |
| download | FOSSEE-netbook-kernel-source-871480933a1c28f8a9fed4c4d34d06c439a7a422.tar.gz FOSSEE-netbook-kernel-source-871480933a1c28f8a9fed4c4d34d06c439a7a422.tar.bz2 FOSSEE-netbook-kernel-source-871480933a1c28f8a9fed4c4d34d06c439a7a422.zip | |
Moved, renamed, and deleted files
The original directory structure was scattered and unorganized.
Changes are basically to make it look like kernel structure.
Diffstat (limited to 'ANDROID_3.4.5/include/video')
52 files changed, 0 insertions, 12529 deletions
diff --git a/ANDROID_3.4.5/include/video/Kbuild b/ANDROID_3.4.5/include/video/Kbuild deleted file mode 100644 index ad3e622c..00000000 --- a/ANDROID_3.4.5/include/video/Kbuild +++ /dev/null @@ -1,3 +0,0 @@ -header-y += edid.h -header-y += sisfb.h -header-y += uvesafb.h diff --git a/ANDROID_3.4.5/include/video/atmel_lcdc.h b/ANDROID_3.4.5/include/video/atmel_lcdc.h deleted file mode 100644 index 28447f15..00000000 --- a/ANDROID_3.4.5/include/video/atmel_lcdc.h +++ /dev/null @@ -1,219 +0,0 @@ -/* - * Header file for AT91/AT32 LCD Controller - * - * Data structure and register user interface - * - * Copyright (C) 2007 Atmel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ATMEL_LCDC_H__ -#define __ATMEL_LCDC_H__ - -#include <linux/workqueue.h> - -/* Way LCD wires are connected to the chip: - * Some Atmel chips use BGR color mode (instead of standard RGB) - * A swapped wiring onboard can bring to RGB mode. - */ -#define ATMEL_LCDC_WIRING_BGR 0 -#define ATMEL_LCDC_WIRING_RGB 1 -#define ATMEL_LCDC_WIRING_RGB555 2 - - - /* LCD Controller info data structure, stored in device platform_data */ -struct atmel_lcdfb_info { - spinlock_t lock; - struct fb_info *info; - void __iomem *mmio; - int irq_base; - struct work_struct task; - - unsigned int guard_time; - unsigned int smem_len; - struct platform_device *pdev; - struct clk *bus_clk; - struct clk *lcdc_clk; - -#ifdef CONFIG_BACKLIGHT_ATMEL_LCDC - struct backlight_device *backlight; - u8 bl_power; -#endif - bool lcdcon_is_backlight; - bool lcdcon_pol_negative; - u8 saved_lcdcon; - - u8 default_bpp; - u8 lcd_wiring_mode; - unsigned int default_lcdcon2; - unsigned int default_dmacon; - void (*atmel_lcdfb_power_control)(int on); - struct fb_monspecs *default_monspecs; - u32 pseudo_palette[16]; -}; - -#define ATMEL_LCDC_DMABADDR1 0x00 -#define ATMEL_LCDC_DMABADDR2 0x04 -#define ATMEL_LCDC_DMAFRMPT1 0x08 -#define ATMEL_LCDC_DMAFRMPT2 0x0c -#define ATMEL_LCDC_DMAFRMADD1 0x10 -#define ATMEL_LCDC_DMAFRMADD2 0x14 - -#define ATMEL_LCDC_DMAFRMCFG 0x18 -#define ATMEL_LCDC_FRSIZE (0x7fffff << 0) -#define ATMEL_LCDC_BLENGTH_OFFSET 24 -#define ATMEL_LCDC_BLENGTH (0x7f << ATMEL_LCDC_BLENGTH_OFFSET) - -#define ATMEL_LCDC_DMACON 0x1c -#define ATMEL_LCDC_DMAEN (0x1 << 0) -#define ATMEL_LCDC_DMARST (0x1 << 1) -#define ATMEL_LCDC_DMABUSY (0x1 << 2) -#define ATMEL_LCDC_DMAUPDT (0x1 << 3) -#define ATMEL_LCDC_DMA2DEN (0x1 << 4) - -#define ATMEL_LCDC_DMA2DCFG 0x20 -#define ATMEL_LCDC_ADDRINC_OFFSET 0 -#define ATMEL_LCDC_ADDRINC (0xffff) -#define ATMEL_LCDC_PIXELOFF_OFFSET 24 -#define ATMEL_LCDC_PIXELOFF (0x1f << 24) - -#define ATMEL_LCDC_LCDCON1 0x0800 -#define ATMEL_LCDC_BYPASS (1 << 0) -#define ATMEL_LCDC_CLKVAL_OFFSET 12 -#define ATMEL_LCDC_CLKVAL (0x1ff << ATMEL_LCDC_CLKVAL_OFFSET) -#define ATMEL_LCDC_LINCNT (0x7ff << 21) - -#define ATMEL_LCDC_LCDCON2 0x0804 -#define ATMEL_LCDC_DISTYPE (3 << 0) -#define ATMEL_LCDC_DISTYPE_STNMONO (0 << 0) -#define ATMEL_LCDC_DISTYPE_STNCOLOR (1 << 0) -#define ATMEL_LCDC_DISTYPE_TFT (2 << 0) -#define ATMEL_LCDC_SCANMOD (1 << 2) -#define ATMEL_LCDC_SCANMOD_SINGLE (0 << 2) -#define ATMEL_LCDC_SCANMOD_DUAL (1 << 2) -#define ATMEL_LCDC_IFWIDTH (3 << 3) -#define ATMEL_LCDC_IFWIDTH_4 (0 << 3) -#define ATMEL_LCDC_IFWIDTH_8 (1 << 3) -#define ATMEL_LCDC_IFWIDTH_16 (2 << 3) -#define ATMEL_LCDC_PIXELSIZE (7 << 5) -#define ATMEL_LCDC_PIXELSIZE_1 (0 << 5) -#define ATMEL_LCDC_PIXELSIZE_2 (1 << 5) -#define ATMEL_LCDC_PIXELSIZE_4 (2 << 5) -#define ATMEL_LCDC_PIXELSIZE_8 (3 << 5) -#define ATMEL_LCDC_PIXELSIZE_16 (4 << 5) -#define ATMEL_LCDC_PIXELSIZE_24 (5 << 5) -#define ATMEL_LCDC_PIXELSIZE_32 (6 << 5) -#define ATMEL_LCDC_INVVD (1 << 8) -#define ATMEL_LCDC_INVVD_NORMAL (0 << 8) -#define ATMEL_LCDC_INVVD_INVERTED (1 << 8) -#define ATMEL_LCDC_INVFRAME (1 << 9 ) -#define ATMEL_LCDC_INVFRAME_NORMAL (0 << 9) -#define ATMEL_LCDC_INVFRAME_INVERTED (1 << 9) -#define ATMEL_LCDC_INVLINE (1 << 10) -#define ATMEL_LCDC_INVLINE_NORMAL (0 << 10) -#define ATMEL_LCDC_INVLINE_INVERTED (1 << 10) -#define ATMEL_LCDC_INVCLK (1 << 11) -#define ATMEL_LCDC_INVCLK_NORMAL (0 << 11) -#define ATMEL_LCDC_INVCLK_INVERTED (1 << 11) -#define ATMEL_LCDC_INVDVAL (1 << 12) -#define ATMEL_LCDC_INVDVAL_NORMAL (0 << 12) -#define ATMEL_LCDC_INVDVAL_INVERTED (1 << 12) -#define ATMEL_LCDC_CLKMOD (1 << 15) -#define ATMEL_LCDC_CLKMOD_ACTIVEDISPLAY (0 << 15) -#define ATMEL_LCDC_CLKMOD_ALWAYSACTIVE (1 << 15) -#define ATMEL_LCDC_MEMOR (1 << 31) -#define ATMEL_LCDC_MEMOR_BIG (0 << 31) -#define ATMEL_LCDC_MEMOR_LITTLE (1 << 31) - -#define ATMEL_LCDC_TIM1 0x0808 -#define ATMEL_LCDC_VFP (0xffU << 0) -#define ATMEL_LCDC_VBP_OFFSET 8 -#define ATMEL_LCDC_VBP (0xffU << ATMEL_LCDC_VBP_OFFSET) -#define ATMEL_LCDC_VPW_OFFSET 16 -#define ATMEL_LCDC_VPW (0x3fU << ATMEL_LCDC_VPW_OFFSET) -#define ATMEL_LCDC_VHDLY_OFFSET 24 -#define ATMEL_LCDC_VHDLY (0xfU << ATMEL_LCDC_VHDLY_OFFSET) - -#define ATMEL_LCDC_TIM2 0x080c -#define ATMEL_LCDC_HBP (0xffU << 0) -#define ATMEL_LCDC_HPW_OFFSET 8 -#define ATMEL_LCDC_HPW (0x3fU << ATMEL_LCDC_HPW_OFFSET) -#define ATMEL_LCDC_HFP_OFFSET 21 -#define ATMEL_LCDC_HFP (0x7ffU << ATMEL_LCDC_HFP_OFFSET) - -#define ATMEL_LCDC_LCDFRMCFG 0x0810 -#define ATMEL_LCDC_LINEVAL (0x7ff << 0) -#define ATMEL_LCDC_HOZVAL_OFFSET 21 -#define ATMEL_LCDC_HOZVAL (0x7ff << ATMEL_LCDC_HOZVAL_OFFSET) - -#define ATMEL_LCDC_FIFO 0x0814 -#define ATMEL_LCDC_FIFOTH (0xffff) - -#define ATMEL_LCDC_MVAL 0x0818 - -#define ATMEL_LCDC_DP1_2 0x081c -#define ATMEL_LCDC_DP4_7 0x0820 -#define ATMEL_LCDC_DP3_5 0x0824 -#define ATMEL_LCDC_DP2_3 0x0828 -#define ATMEL_LCDC_DP5_7 0x082c -#define ATMEL_LCDC_DP3_4 0x0830 -#define ATMEL_LCDC_DP4_5 0x0834 -#define ATMEL_LCDC_DP6_7 0x0838 -#define ATMEL_LCDC_DP1_2_VAL (0xff) -#define ATMEL_LCDC_DP4_7_VAL (0xfffffff) -#define ATMEL_LCDC_DP3_5_VAL (0xfffff) -#define ATMEL_LCDC_DP2_3_VAL (0xfff) -#define ATMEL_LCDC_DP5_7_VAL (0xfffffff) -#define ATMEL_LCDC_DP3_4_VAL (0xffff) -#define ATMEL_LCDC_DP4_5_VAL (0xfffff) -#define ATMEL_LCDC_DP6_7_VAL (0xfffffff) - -#define ATMEL_LCDC_PWRCON 0x083c -#define ATMEL_LCDC_PWR (1 << 0) -#define ATMEL_LCDC_GUARDT_OFFSET 1 -#define ATMEL_LCDC_GUARDT (0x7f << ATMEL_LCDC_GUARDT_OFFSET) -#define ATMEL_LCDC_BUSY (1 << 31) - -#define ATMEL_LCDC_CONTRAST_CTR 0x0840 -#define ATMEL_LCDC_PS (3 << 0) -#define ATMEL_LCDC_PS_DIV1 (0 << 0) -#define ATMEL_LCDC_PS_DIV2 (1 << 0) -#define ATMEL_LCDC_PS_DIV4 (2 << 0) -#define ATMEL_LCDC_PS_DIV8 (3 << 0) -#define ATMEL_LCDC_POL (1 << 2) -#define ATMEL_LCDC_POL_NEGATIVE (0 << 2) -#define ATMEL_LCDC_POL_POSITIVE (1 << 2) -#define ATMEL_LCDC_ENA (1 << 3) -#define ATMEL_LCDC_ENA_PWMDISABLE (0 << 3) -#define ATMEL_LCDC_ENA_PWMENABLE (1 << 3) - -#define ATMEL_LCDC_CONTRAST_VAL 0x0844 -#define ATMEL_LCDC_CVAL (0xff) - -#define ATMEL_LCDC_IER 0x0848 -#define ATMEL_LCDC_IDR 0x084c -#define ATMEL_LCDC_IMR 0x0850 -#define ATMEL_LCDC_ISR 0x0854 -#define ATMEL_LCDC_ICR 0x0858 -#define ATMEL_LCDC_LNI (1 << 0) -#define ATMEL_LCDC_LSTLNI (1 << 1) -#define ATMEL_LCDC_EOFI (1 << 2) -#define ATMEL_LCDC_UFLWI (1 << 4) -#define ATMEL_LCDC_OWRI (1 << 5) -#define ATMEL_LCDC_MERI (1 << 6) - -#define ATMEL_LCDC_LUT(n) (0x0c00 + ((n)*4)) - -#endif /* __ATMEL_LCDC_H__ */ diff --git a/ANDROID_3.4.5/include/video/aty128.h b/ANDROID_3.4.5/include/video/aty128.h deleted file mode 100644 index f0851e3b..00000000 --- a/ANDROID_3.4.5/include/video/aty128.h +++ /dev/null @@ -1,422 +0,0 @@ -/* $Id: aty128.h,v 1.1 1999/10/12 11:00:40 geert Exp $ - * linux/drivers/video/aty128.h - * Register definitions for ATI Rage128 boards - * - * Anthony Tong <atong@uiuc.edu>, 1999 - * Brad Douglas <brad@neruo.com>, 2000 - */ - -#ifndef REG_RAGE128_H -#define REG_RAGE128_H - -#define CLOCK_CNTL_INDEX 0x0008 -#define CLOCK_CNTL_DATA 0x000c -#define BIOS_0_SCRATCH 0x0010 -#define BUS_CNTL 0x0030 -#define BUS_CNTL1 0x0034 -#define GEN_INT_CNTL 0x0040 -#define CRTC_GEN_CNTL 0x0050 -#define CRTC_EXT_CNTL 0x0054 -#define DAC_CNTL 0x0058 -#define I2C_CNTL_1 0x0094 -#define PALETTE_INDEX 0x00b0 -#define PALETTE_DATA 0x00b4 -#define CNFG_CNTL 0x00e0 -#define GEN_RESET_CNTL 0x00f0 -#define CNFG_MEMSIZE 0x00f8 -#define MEM_CNTL 0x0140 -#define MEM_POWER_MISC 0x015c -#define AGP_BASE 0x0170 -#define AGP_CNTL 0x0174 -#define AGP_APER_OFFSET 0x0178 -#define PCI_GART_PAGE 0x017c -#define PC_NGUI_MODE 0x0180 -#define PC_NGUI_CTLSTAT 0x0184 -#define MPP_TB_CONFIG 0x01C0 -#define MPP_GP_CONFIG 0x01C8 -#define VIPH_CONTROL 0x01D0 -#define CRTC_H_TOTAL_DISP 0x0200 -#define CRTC_H_SYNC_STRT_WID 0x0204 -#define CRTC_V_TOTAL_DISP 0x0208 -#define CRTC_V_SYNC_STRT_WID 0x020c -#define CRTC_VLINE_CRNT_VLINE 0x0210 -#define CRTC_CRNT_FRAME 0x0214 -#define CRTC_GUI_TRIG_VLINE 0x0218 -#define CRTC_OFFSET 0x0224 -#define CRTC_OFFSET_CNTL 0x0228 -#define CRTC_PITCH 0x022c -#define OVR_CLR 0x0230 -#define OVR_WID_LEFT_RIGHT 0x0234 -#define OVR_WID_TOP_BOTTOM 0x0238 -#define LVDS_GEN_CNTL 0x02d0 -#define DDA_CONFIG 0x02e0 -#define DDA_ON_OFF 0x02e4 -#define VGA_DDA_CONFIG 0x02e8 -#define VGA_DDA_ON_OFF 0x02ec -#define CRTC2_H_TOTAL_DISP 0x0300 -#define CRTC2_H_SYNC_STRT_WID 0x0304 -#define CRTC2_V_TOTAL_DISP 0x0308 -#define CRTC2_V_SYNC_STRT_WID 0x030c -#define CRTC2_VLINE_CRNT_VLINE 0x0310 -#define CRTC2_CRNT_FRAME 0x0314 -#define CRTC2_GUI_TRIG_VLINE 0x0318 -#define CRTC2_OFFSET 0x0324 -#define CRTC2_OFFSET_CNTL 0x0328 -#define CRTC2_PITCH 0x032c -#define DDA2_CONFIG 0x03e0 -#define DDA2_ON_OFF 0x03e4 -#define CRTC2_GEN_CNTL 0x03f8 -#define CRTC2_STATUS 0x03fc -#define OV0_SCALE_CNTL 0x0420 -#define SUBPIC_CNTL 0x0540 -#define PM4_BUFFER_OFFSET 0x0700 -#define PM4_BUFFER_CNTL 0x0704 -#define PM4_BUFFER_WM_CNTL 0x0708 -#define PM4_BUFFER_DL_RPTR_ADDR 0x070c -#define PM4_BUFFER_DL_RPTR 0x0710 -#define PM4_BUFFER_DL_WPTR 0x0714 -#define PM4_VC_FPU_SETUP 0x071c -#define PM4_FPU_CNTL 0x0720 -#define PM4_VC_FORMAT 0x0724 -#define PM4_VC_CNTL 0x0728 -#define PM4_VC_I01 0x072c -#define PM4_VC_VLOFF 0x0730 -#define PM4_VC_VLSIZE 0x0734 -#define PM4_IW_INDOFF 0x0738 -#define PM4_IW_INDSIZE 0x073c -#define PM4_FPU_FPX0 0x0740 -#define PM4_FPU_FPY0 0x0744 -#define PM4_FPU_FPX1 0x0748 -#define PM4_FPU_FPY1 0x074c -#define PM4_FPU_FPX2 0x0750 -#define PM4_FPU_FPY2 0x0754 -#define PM4_FPU_FPY3 0x0758 -#define PM4_FPU_FPY4 0x075c -#define PM4_FPU_FPY5 0x0760 -#define PM4_FPU_FPY6 0x0764 -#define PM4_FPU_FPR 0x0768 -#define PM4_FPU_FPG 0x076c -#define PM4_FPU_FPB 0x0770 -#define PM4_FPU_FPA 0x0774 -#define PM4_FPU_INTXY0 0x0780 -#define PM4_FPU_INTXY1 0x0784 -#define PM4_FPU_INTXY2 0x0788 -#define PM4_FPU_INTARGB 0x078c -#define PM4_FPU_FPTWICEAREA 0x0790 -#define PM4_FPU_DMAJOR01 0x0794 -#define PM4_FPU_DMAJOR12 0x0798 -#define PM4_FPU_DMAJOR02 0x079c -#define PM4_FPU_STAT 0x07a0 -#define PM4_STAT 0x07b8 -#define PM4_TEST_CNTL 0x07d0 -#define PM4_MICROCODE_ADDR 0x07d4 -#define PM4_MICROCODE_RADDR 0x07d8 -#define PM4_MICROCODE_DATAH 0x07dc -#define PM4_MICROCODE_DATAL 0x07e0 -#define PM4_CMDFIFO_ADDR 0x07e4 -#define PM4_CMDFIFO_DATAH 0x07e8 -#define PM4_CMDFIFO_DATAL 0x07ec -#define PM4_BUFFER_ADDR 0x07f0 -#define PM4_BUFFER_DATAH 0x07f4 -#define PM4_BUFFER_DATAL 0x07f8 -#define PM4_MICRO_CNTL 0x07fc -#define CAP0_TRIG_CNTL 0x0950 -#define CAP1_TRIG_CNTL 0x09c0 - -/****************************************************************************** - * GUI Block Memory Mapped Registers * - * These registers are FIFOed. * - *****************************************************************************/ -#define PM4_FIFO_DATA_EVEN 0x1000 -#define PM4_FIFO_DATA_ODD 0x1004 - -#define DST_OFFSET 0x1404 -#define DST_PITCH 0x1408 -#define DST_WIDTH 0x140c -#define DST_HEIGHT 0x1410 -#define SRC_X 0x1414 -#define SRC_Y 0x1418 -#define DST_X 0x141c -#define DST_Y 0x1420 -#define SRC_PITCH_OFFSET 0x1428 -#define DST_PITCH_OFFSET 0x142c -#define SRC_Y_X 0x1434 -#define DST_Y_X 0x1438 -#define DST_HEIGHT_WIDTH 0x143c -#define DP_GUI_MASTER_CNTL 0x146c -#define BRUSH_SCALE 0x1470 -#define BRUSH_Y_X 0x1474 -#define DP_BRUSH_BKGD_CLR 0x1478 -#define DP_BRUSH_FRGD_CLR 0x147c -#define DST_WIDTH_X 0x1588 -#define DST_HEIGHT_WIDTH_8 0x158c -#define SRC_X_Y 0x1590 -#define DST_X_Y 0x1594 -#define DST_WIDTH_HEIGHT 0x1598 -#define DST_WIDTH_X_INCY 0x159c -#define DST_HEIGHT_Y 0x15a0 -#define DST_X_SUB 0x15a4 -#define DST_Y_SUB 0x15a8 -#define SRC_OFFSET 0x15ac -#define SRC_PITCH 0x15b0 -#define DST_HEIGHT_WIDTH_BW 0x15b4 -#define CLR_CMP_CNTL 0x15c0 -#define CLR_CMP_CLR_SRC 0x15c4 -#define CLR_CMP_CLR_DST 0x15c8 -#define CLR_CMP_MASK 0x15cc -#define DP_SRC_FRGD_CLR 0x15d8 -#define DP_SRC_BKGD_CLR 0x15dc -#define DST_BRES_ERR 0x1628 -#define DST_BRES_INC 0x162c -#define DST_BRES_DEC 0x1630 -#define DST_BRES_LNTH 0x1634 -#define DST_BRES_LNTH_SUB 0x1638 -#define SC_LEFT 0x1640 -#define SC_RIGHT 0x1644 -#define SC_TOP 0x1648 -#define SC_BOTTOM 0x164c -#define SRC_SC_RIGHT 0x1654 -#define SRC_SC_BOTTOM 0x165c -#define GUI_DEBUG0 0x16a0 -#define GUI_DEBUG1 0x16a4 -#define GUI_TIMEOUT 0x16b0 -#define GUI_TIMEOUT0 0x16b4 -#define GUI_TIMEOUT1 0x16b8 -#define GUI_PROBE 0x16bc -#define DP_CNTL 0x16c0 -#define DP_DATATYPE 0x16c4 -#define DP_MIX 0x16c8 -#define DP_WRITE_MASK 0x16cc -#define DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0 -#define DEFAULT_OFFSET 0x16e0 -#define DEFAULT_PITCH 0x16e4 -#define DEFAULT_SC_BOTTOM_RIGHT 0x16e8 -#define SC_TOP_LEFT 0x16ec -#define SC_BOTTOM_RIGHT 0x16f0 -#define SRC_SC_BOTTOM_RIGHT 0x16f4 -#define WAIT_UNTIL 0x1720 -#define CACHE_CNTL 0x1724 -#define GUI_STAT 0x1740 -#define PC_GUI_MODE 0x1744 -#define PC_GUI_CTLSTAT 0x1748 -#define PC_DEBUG_MODE 0x1760 -#define BRES_DST_ERR_DEC 0x1780 -#define TRAIL_BRES_T12_ERR_DEC 0x1784 -#define TRAIL_BRES_T12_INC 0x1788 -#define DP_T12_CNTL 0x178c -#define DST_BRES_T1_LNTH 0x1790 -#define DST_BRES_T2_LNTH 0x1794 -#define SCALE_SRC_HEIGHT_WIDTH 0x1994 -#define SCALE_OFFSET_0 0x1998 -#define SCALE_PITCH 0x199c -#define SCALE_X_INC 0x19a0 -#define SCALE_Y_INC 0x19a4 -#define SCALE_HACC 0x19a8 -#define SCALE_VACC 0x19ac -#define SCALE_DST_X_Y 0x19b0 -#define SCALE_DST_HEIGHT_WIDTH 0x19b4 -#define SCALE_3D_CNTL 0x1a00 -#define SCALE_3D_DATATYPE 0x1a20 -#define SETUP_CNTL 0x1bc4 -#define SOLID_COLOR 0x1bc8 -#define WINDOW_XY_OFFSET 0x1bcc -#define DRAW_LINE_POINT 0x1bd0 -#define SETUP_CNTL_PM4 0x1bd4 -#define DST_PITCH_OFFSET_C 0x1c80 -#define DP_GUI_MASTER_CNTL_C 0x1c84 -#define SC_TOP_LEFT_C 0x1c88 -#define SC_BOTTOM_RIGHT_C 0x1c8c - -#define CLR_CMP_MASK_3D 0x1A28 -#define MISC_3D_STATE_CNTL_REG 0x1CA0 -#define MC_SRC1_CNTL 0x19D8 -#define TEX_CNTL 0x1800 - -/* CONSTANTS */ -#define GUI_ACTIVE 0x80000000 -#define ENGINE_IDLE 0x0 - -#define PLL_WR_EN 0x00000080 - -#define CLK_PIN_CNTL 0x0001 -#define PPLL_CNTL 0x0002 -#define PPLL_REF_DIV 0x0003 -#define PPLL_DIV_0 0x0004 -#define PPLL_DIV_1 0x0005 -#define PPLL_DIV_2 0x0006 -#define PPLL_DIV_3 0x0007 -#define VCLK_ECP_CNTL 0x0008 -#define HTOTAL_CNTL 0x0009 -#define X_MPLL_REF_FB_DIV 0x000a -#define XPLL_CNTL 0x000b -#define XDLL_CNTL 0x000c -#define XCLK_CNTL 0x000d -#define MPLL_CNTL 0x000e -#define MCLK_CNTL 0x000f -#define AGP_PLL_CNTL 0x0010 -#define FCP_CNTL 0x0012 -#define PLL_TEST_CNTL 0x0013 -#define P2PLL_CNTL 0x002a -#define P2PLL_REF_DIV 0x002b -#define P2PLL_DIV_0 0x002b -#define POWER_MANAGEMENT 0x002f - -#define PPLL_RESET 0x01 -#define PPLL_ATOMIC_UPDATE_EN 0x10000 -#define PPLL_VGA_ATOMIC_UPDATE_EN 0x20000 -#define PPLL_REF_DIV_MASK 0x3FF -#define PPLL_FB3_DIV_MASK 0x7FF -#define PPLL_POST3_DIV_MASK 0x70000 -#define PPLL_ATOMIC_UPDATE_R 0x8000 -#define PPLL_ATOMIC_UPDATE_W 0x8000 -#define MEM_CFG_TYPE_MASK 0x3 -#define XCLK_SRC_SEL_MASK 0x7 -#define XPLL_FB_DIV_MASK 0xFF00 -#define X_MPLL_REF_DIV_MASK 0xFF - -/* CRTC control values (CRTC_GEN_CNTL) */ -#define CRTC_CSYNC_EN 0x00000010 - -#define CRTC2_DBL_SCAN_EN 0x00000001 -#define CRTC2_DISPLAY_DIS 0x00800000 -#define CRTC2_FIFO_EXTSENSE 0x00200000 -#define CRTC2_ICON_EN 0x00100000 -#define CRTC2_CUR_EN 0x00010000 -#define CRTC2_EN 0x02000000 -#define CRTC2_DISP_REQ_EN_B 0x04000000 - -#define CRTC_PIX_WIDTH_MASK 0x00000700 -#define CRTC_PIX_WIDTH_4BPP 0x00000100 -#define CRTC_PIX_WIDTH_8BPP 0x00000200 -#define CRTC_PIX_WIDTH_15BPP 0x00000300 -#define CRTC_PIX_WIDTH_16BPP 0x00000400 -#define CRTC_PIX_WIDTH_24BPP 0x00000500 -#define CRTC_PIX_WIDTH_32BPP 0x00000600 - -/* DAC_CNTL bit constants */ -#define DAC_8BIT_EN 0x00000100 -#define DAC_MASK 0xFF000000 -#define DAC_BLANKING 0x00000004 -#define DAC_RANGE_CNTL 0x00000003 -#define DAC_CLK_SEL 0x00000010 -#define DAC_PALETTE_ACCESS_CNTL 0x00000020 -#define DAC_PALETTE2_SNOOP_EN 0x00000040 -#define DAC_PDWN 0x00008000 - -/* CRTC_EXT_CNTL */ -#define CRT_CRTC_ON 0x00008000 - -/* GEN_RESET_CNTL bit constants */ -#define SOFT_RESET_GUI 0x00000001 -#define SOFT_RESET_VCLK 0x00000100 -#define SOFT_RESET_PCLK 0x00000200 -#define SOFT_RESET_ECP 0x00000400 -#define SOFT_RESET_DISPENG_XCLK 0x00000800 - -/* PC_GUI_CTLSTAT bit constants */ -#define PC_BUSY_INIT 0x10000000 -#define PC_BUSY_GUI 0x20000000 -#define PC_BUSY_NGUI 0x40000000 -#define PC_BUSY 0x80000000 - -#define BUS_MASTER_DIS 0x00000040 -#define PM4_BUFFER_CNTL_NONPM4 0x00000000 - -/* DP_DATATYPE bit constants */ -#define DST_8BPP 0x00000002 -#define DST_15BPP 0x00000003 -#define DST_16BPP 0x00000004 -#define DST_24BPP 0x00000005 -#define DST_32BPP 0x00000006 - -#define BRUSH_SOLIDCOLOR 0x00000d00 - -/* DP_GUI_MASTER_CNTL bit constants */ -#define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000 -#define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000 -#define GMC_SRC_CLIP_DEFAULT 0x00000000 -#define GMC_DST_CLIP_DEFAULT 0x00000000 -#define GMC_BRUSH_SOLIDCOLOR 0x000000d0 -#define GMC_SRC_DSTCOLOR 0x00003000 -#define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000 -#define GMC_DP_SRC_RECT 0x02000000 -#define GMC_3D_FCN_EN_CLR 0x00000000 -#define GMC_AUX_CLIP_CLEAR 0x20000000 -#define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000 -#define GMC_WRITE_MASK_SET 0x40000000 -#define GMC_DP_CONVERSION_TEMP_6500 0x00000000 - -/* DP_GUI_MASTER_CNTL ROP3 named constants */ -#define ROP3_PATCOPY 0x00f00000 -#define ROP3_SRCCOPY 0x00cc0000 - -#define SRC_DSTCOLOR 0x00030000 - -/* DP_CNTL bit constants */ -#define DST_X_RIGHT_TO_LEFT 0x00000000 -#define DST_X_LEFT_TO_RIGHT 0x00000001 -#define DST_Y_BOTTOM_TO_TOP 0x00000000 -#define DST_Y_TOP_TO_BOTTOM 0x00000002 -#define DST_X_MAJOR 0x00000000 -#define DST_Y_MAJOR 0x00000004 -#define DST_X_TILE 0x00000008 -#define DST_Y_TILE 0x00000010 -#define DST_LAST_PEL 0x00000020 -#define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000 -#define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040 -#define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000 -#define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080 -#define DST_BRES_SIGN 0x00000100 -#define DST_HOST_BIG_ENDIAN_EN 0x00000200 -#define DST_POLYLINE_NONLAST 0x00008000 -#define DST_RASTER_STALL 0x00010000 -#define DST_POLY_EDGE 0x00040000 - -/* DP_MIX bit constants */ -#define DP_SRC_RECT 0x00000200 -#define DP_SRC_HOST 0x00000300 -#define DP_SRC_HOST_BYTEALIGN 0x00000400 - -/* LVDS_GEN_CNTL constants */ -#define LVDS_BL_MOD_LEVEL_MASK 0x0000ff00 -#define LVDS_BL_MOD_LEVEL_SHIFT 8 -#define LVDS_BL_MOD_EN 0x00010000 -#define LVDS_DIGION 0x00040000 -#define LVDS_BLON 0x00080000 -#define LVDS_ON 0x00000001 -#define LVDS_DISPLAY_DIS 0x00000002 -#define LVDS_PANEL_TYPE_2PIX_PER_CLK 0x00000004 -#define LVDS_PANEL_24BITS_TFT 0x00000008 -#define LVDS_FRAME_MOD_NO 0x00000000 -#define LVDS_FRAME_MOD_2_LEVELS 0x00000010 -#define LVDS_FRAME_MOD_4_LEVELS 0x00000020 -#define LVDS_RST_FM 0x00000040 -#define LVDS_EN 0x00000080 - -/* CRTC2_GEN_CNTL constants */ -#define CRTC2_EN 0x02000000 - -/* POWER_MANAGEMENT constants */ -#define PWR_MGT_ON 0x00000001 -#define PWR_MGT_MODE_MASK 0x00000006 -#define PWR_MGT_MODE_PIN 0x00000000 -#define PWR_MGT_MODE_REGISTER 0x00000002 -#define PWR_MGT_MODE_TIMER 0x00000004 -#define PWR_MGT_MODE_PCI 0x00000006 -#define PWR_MGT_AUTO_PWR_UP_EN 0x00000008 -#define PWR_MGT_ACTIVITY_PIN_ON 0x00000010 -#define PWR_MGT_STANDBY_POL 0x00000020 -#define PWR_MGT_SUSPEND_POL 0x00000040 -#define PWR_MGT_SELF_REFRESH 0x00000080 -#define PWR_MGT_ACTIVITY_PIN_EN 0x00000100 -#define PWR_MGT_KEYBD_SNOOP 0x00000200 -#define PWR_MGT_TRISTATE_MEM_EN 0x00000800 -#define PWR_MGT_SELW4MS 0x00001000 -#define PWR_MGT_SLOWDOWN_MCLK 0x00002000 - -#define PMI_PMSCR_REG 0x60 - -/* used by ATI bug fix for hardware ROM */ -#define RAGE128_MPP_TB_CONFIG 0x01c0 - -#endif /* REG_RAGE128_H */ diff --git a/ANDROID_3.4.5/include/video/broadsheetfb.h b/ANDROID_3.4.5/include/video/broadsheetfb.h deleted file mode 100644 index 548d28f4..00000000 --- a/ANDROID_3.4.5/include/video/broadsheetfb.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * broadsheetfb.h - definitions for the broadsheet framebuffer driver - * - * Copyright (C) 2008 by Jaya Kumar - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive for - * more details. - * - */ - -#ifndef _LINUX_BROADSHEETFB_H_ -#define _LINUX_BROADSHEETFB_H_ - -/* Broadsheet command defines */ -#define BS_CMD_INIT_SYS_RUN 0x06 -#define BS_CMD_INIT_DSPE_CFG 0x09 -#define BS_CMD_INIT_DSPE_TMG 0x0A -#define BS_CMD_INIT_ROTMODE 0x0B -#define BS_CMD_RD_REG 0x10 -#define BS_CMD_WR_REG 0x11 -#define BS_CMD_LD_IMG 0x20 -#define BS_CMD_LD_IMG_AREA 0x22 -#define BS_CMD_LD_IMG_END 0x23 -#define BS_CMD_WAIT_DSPE_TRG 0x28 -#define BS_CMD_WAIT_DSPE_FREND 0x29 -#define BS_CMD_RD_WFM_INFO 0x30 -#define BS_CMD_UPD_INIT 0x32 -#define BS_CMD_UPD_FULL 0x33 -#define BS_CMD_UPD_GDRV_CLR 0x37 - -/* Broadsheet register interface defines */ -#define BS_REG_REV 0x00 -#define BS_REG_PRC 0x02 - -/* Broadsheet pin interface specific defines */ -#define BS_CS 0x01 -#define BS_DC 0x02 -#define BS_WR 0x03 - -/* Broadsheet IO interface specific defines */ -#define BS_MMIO_CMD 0x01 -#define BS_MMIO_DATA 0x02 - -/* struct used by broadsheet. board specific stuff comes from *board */ -struct broadsheetfb_par { - struct fb_info *info; - struct broadsheet_board *board; - void (*write_reg)(struct broadsheetfb_par *, u16 reg, u16 val); - u16 (*read_reg)(struct broadsheetfb_par *, u16 reg); - wait_queue_head_t waitq; - int panel_index; - struct mutex io_lock; -}; - -/* board specific routines */ -struct broadsheet_board { - struct module *owner; - int (*init)(struct broadsheetfb_par *); - int (*wait_for_rdy)(struct broadsheetfb_par *); - void (*cleanup)(struct broadsheetfb_par *); - int (*get_panel_type)(void); - int (*setup_irq)(struct fb_info *); - - /* Functions for boards that use GPIO */ - void (*set_ctl)(struct broadsheetfb_par *, unsigned char, u8); - void (*set_hdb)(struct broadsheetfb_par *, u16); - u16 (*get_hdb)(struct broadsheetfb_par *); - - /* Functions for boards that have specialized MMIO */ - void (*mmio_write)(struct broadsheetfb_par *, int type, u16); - u16 (*mmio_read)(struct broadsheetfb_par *); -}; -#endif diff --git a/ANDROID_3.4.5/include/video/cirrus.h b/ANDROID_3.4.5/include/video/cirrus.h deleted file mode 100644 index 9a5e9ee3..00000000 --- a/ANDROID_3.4.5/include/video/cirrus.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * drivers/video/clgenfb.h - Cirrus Logic chipset constants - * - * Copyright 1999 Jeff Garzik <jgarzik@pobox.com> - * - * Original clgenfb author: Frank Neumann - * - * Based on retz3fb.c and clgen.c: - * Copyright (C) 1997 Jes Sorensen - * Copyright (C) 1996 Frank Neumann - * - *************************************************************** - * - * Format this code with GNU indent '-kr -i8 -pcs' options. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - * - */ - -#ifndef __CLGENFB_H__ -#define __CLGENFB_H__ - -/* OLD COMMENT: definitions for Piccolo/SD64 VGA controller chip */ -/* OLD COMMENT: these definitions might most of the time also work */ -/* OLD COMMENT: for other CL-GD542x/543x based boards.. */ - -/*** External/General Registers ***/ -#define CL_POS102 0x102 /* POS102 register */ -#define CL_VSSM 0x46e8 /* Adapter Sleep */ -#define CL_VSSM2 0x3c3 /* Motherboard Sleep */ - -/*** VGA Sequencer Registers ***/ -/* the following are from the "extension registers" group */ -#define CL_SEQR6 0x6 /* Unlock ALL Extensions */ -#define CL_SEQR7 0x7 /* Extended Sequencer Mode */ -#define CL_SEQR8 0x8 /* EEPROM Control */ -#define CL_SEQR9 0x9 /* Scratch Pad 0 (do not access!) */ -#define CL_SEQRA 0xa /* Scratch Pad 1 (do not access!) */ -#define CL_SEQRB 0xb /* VCLK0 Numerator */ -#define CL_SEQRC 0xc /* VCLK1 Numerator */ -#define CL_SEQRD 0xd /* VCLK2 Numerator */ -#define CL_SEQRE 0xe /* VCLK3 Numerator */ -#define CL_SEQRF 0xf /* DRAM Control */ -#define CL_SEQR10 0x10 /* Graphics Cursor X Position */ -#define CL_SEQR11 0x11 /* Graphics Cursor Y Position */ -#define CL_SEQR12 0x12 /* Graphics Cursor Attributes */ -#define CL_SEQR13 0x13 /* Graphics Cursor Pattern Address Offset */ -#define CL_SEQR14 0x14 /* Scratch Pad 2 (CL-GD5426/'28 Only) (do not access!) */ -#define CL_SEQR15 0x15 /* Scratch Pad 3 (CL-GD5426/'28 Only) (do not access!) */ -#define CL_SEQR16 0x16 /* Performance Tuning (CL-GD5424/'26/'28 Only) */ -#define CL_SEQR17 0x17 /* Configuration ReadBack and Extended Control (CL-GF5428 Only) */ -#define CL_SEQR18 0x18 /* Signature Generator Control (Not CL-GD5420) */ -#define CL_SEQR19 0x19 /* Signature Generator Result Low Byte (Not CL-GD5420) */ -#define CL_SEQR1A 0x1a /* Signature Generator Result High Byte (Not CL-GD5420) */ -#define CL_SEQR1B 0x1b /* VCLK0 Denominator and Post-Scalar Value */ -#define CL_SEQR1C 0x1c /* VCLK1 Denominator and Post-Scalar Value */ -#define CL_SEQR1D 0x1d /* VCLK2 Denominator and Post-Scalar Value */ -#define CL_SEQR1E 0x1e /* VCLK3 Denominator and Post-Scalar Value */ -#define CL_SEQR1F 0x1f /* BIOS ROM write enable and MCLK Select */ - -/*** CRT Controller Registers ***/ -#define CL_CRT22 0x22 /* Graphics Data Latches ReadBack */ -#define CL_CRT24 0x24 /* Attribute Controller Toggle ReadBack */ -#define CL_CRT26 0x26 /* Attribute Controller Index ReadBack */ -/* the following are from the "extension registers" group */ -#define CL_CRT19 0x19 /* Interlace End */ -#define CL_CRT1A 0x1a /* Interlace Control */ -#define CL_CRT1B 0x1b /* Extended Display Controls */ -#define CL_CRT1C 0x1c /* Sync adjust and genlock register */ -#define CL_CRT1D 0x1d /* Overlay Extended Control register */ -#define CL_CRT1E 0x1e /* Another overflow register */ -#define CL_CRT25 0x25 /* Part Status Register */ -#define CL_CRT27 0x27 /* ID Register */ -#define CL_CRT51 0x51 /* P4 disable "flicker fixer" */ - -/*** Graphics Controller Registers ***/ -/* the following are from the "extension registers" group */ -#define CL_GR9 0x9 /* Offset Register 0 */ -#define CL_GRA 0xa /* Offset Register 1 */ -#define CL_GRB 0xb /* Graphics Controller Mode Extensions */ -#define CL_GRC 0xc /* Color Key (CL-GD5424/'26/'28 Only) */ -#define CL_GRD 0xd /* Color Key Mask (CL-GD5424/'26/'28 Only) */ -#define CL_GRE 0xe /* Miscellaneous Control (Cl-GD5428 Only) */ -#define CL_GRF 0xf /* Display Compression Control register */ -#define CL_GR10 0x10 /* 16-bit Pixel BG Color High Byte (Not CL-GD5420) */ -#define CL_GR11 0x11 /* 16-bit Pixel FG Color High Byte (Not CL-GD5420) */ -#define CL_GR12 0x12 /* Background Color Byte 2 Register */ -#define CL_GR13 0x13 /* Foreground Color Byte 2 Register */ -#define CL_GR14 0x14 /* Background Color Byte 3 Register */ -#define CL_GR15 0x15 /* Foreground Color Byte 3 Register */ -/* the following are CL-GD5426/'28 specific blitter registers */ -#define CL_GR20 0x20 /* BLT Width Low */ -#define CL_GR21 0x21 /* BLT Width High */ -#define CL_GR22 0x22 /* BLT Height Low */ -#define CL_GR23 0x23 /* BLT Height High */ -#define CL_GR24 0x24 /* BLT Destination Pitch Low */ -#define CL_GR25 0x25 /* BLT Destination Pitch High */ -#define CL_GR26 0x26 /* BLT Source Pitch Low */ -#define CL_GR27 0x27 /* BLT Source Pitch High */ -#define CL_GR28 0x28 /* BLT Destination Start Low */ -#define CL_GR29 0x29 /* BLT Destination Start Mid */ -#define CL_GR2A 0x2a /* BLT Destination Start High */ -#define CL_GR2C 0x2c /* BLT Source Start Low */ -#define CL_GR2D 0x2d /* BLT Source Start Mid */ -#define CL_GR2E 0x2e /* BLT Source Start High */ -#define CL_GR2F 0x2f /* Picasso IV Blitter compat mode..? */ -#define CL_GR30 0x30 /* BLT Mode */ -#define CL_GR31 0x31 /* BLT Start/Status */ -#define CL_GR32 0x32 /* BLT Raster Operation */ -#define CL_GR33 0x33 /* another P4 "compat" register.. */ -#define CL_GR34 0x34 /* Transparent Color Select Low */ -#define CL_GR35 0x35 /* Transparent Color Select High */ -#define CL_GR38 0x38 /* Source Transparent Color Mask Low */ -#define CL_GR39 0x39 /* Source Transparent Color Mask High */ - -/*** Attribute Controller Registers ***/ -#define CL_AR33 0x33 /* The "real" Pixel Panning register (?) */ -#define CL_AR34 0x34 /* TEST */ - -#endif /* __CLGENFB_H__ */ diff --git a/ANDROID_3.4.5/include/video/cvisionppc.h b/ANDROID_3.4.5/include/video/cvisionppc.h deleted file mode 100644 index 11250eee..00000000 --- a/ANDROID_3.4.5/include/video/cvisionppc.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Phase5 CybervisionPPC (TVP4020) definitions for the Permedia2 framebuffer - * driver. - * - * Copyright (c) 1998-1999 Ilario Nardinocchi (nardinoc@CS.UniBO.IT) - * -------------------------------------------------------------------------- - * $Id: cvisionppc.h,v 1.8 1999/01/28 13:18:07 illo Exp $ - * -------------------------------------------------------------------------- - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -#ifndef CVISIONPPC_H -#define CVISIONPPC_H - -#ifndef PM2FB_H -#include "pm2fb.h" -#endif - -struct cvppc_par { - unsigned char* pci_config; - unsigned char* pci_bridge; - u32 user_flags; -}; - -#define CSPPC_PCI_BRIDGE 0xfffe0000 -#define CSPPC_BRIDGE_ENDIAN 0x0000 -#define CSPPC_BRIDGE_INT 0x0010 - -#define CVPPC_PCI_CONFIG 0xfffc0000 -#define CVPPC_ROM_ADDRESS 0xe2000001 -#define CVPPC_REGS_REGION 0xef000000 -#define CVPPC_FB_APERTURE_ONE 0xe0000000 -#define CVPPC_FB_APERTURE_TWO 0xe1000000 -#define CVPPC_FB_SIZE 0x00800000 -#define CVPPC_MEM_CONFIG_OLD 0xed61fcaa /* FIXME Fujitsu?? */ -#define CVPPC_MEM_CONFIG_NEW 0xed41c532 /* FIXME USA?? */ -#define CVPPC_MEMCLOCK 83000 /* in KHz */ - -/* CVPPC_BRIDGE_ENDIAN */ -#define CSPPCF_BRIDGE_BIG_ENDIAN 0x02 - -/* CVPPC_BRIDGE_INT */ -#define CSPPCF_BRIDGE_ACTIVE_INT2 0x01 - -#endif /* CVISIONPPC_H */ - -/***************************************************************************** - * That's all folks! - *****************************************************************************/ diff --git a/ANDROID_3.4.5/include/video/da8xx-fb.h b/ANDROID_3.4.5/include/video/da8xx-fb.h deleted file mode 100644 index 89d43b3d..00000000 --- a/ANDROID_3.4.5/include/video/da8xx-fb.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Header file for TI DA8XX LCD controller platform data. - * - * Copyright (C) 2008-2009 MontaVista Software Inc. - * Copyright (C) 2008-2009 Texas Instruments Inc - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#ifndef DA8XX_FB_H -#define DA8XX_FB_H - -enum panel_type { - QVGA = 0 -}; - -enum panel_shade { - MONOCHROME = 0, - COLOR_ACTIVE, - COLOR_PASSIVE, -}; - -enum raster_load_mode { - LOAD_DATA = 1, - LOAD_PALETTE, -}; - -struct display_panel { - enum panel_type panel_type; /* QVGA */ - int max_bpp; - int min_bpp; - enum panel_shade panel_shade; -}; - -struct da8xx_lcdc_platform_data { - const char manu_name[10]; - void *controller_data; - const char type[25]; - void (*panel_power_ctrl)(int); -}; - -struct lcd_ctrl_config { - const struct display_panel *p_disp_panel; - - /* AC Bias Pin Frequency */ - int ac_bias; - - /* AC Bias Pin Transitions per Interrupt */ - int ac_bias_intrpt; - - /* DMA burst size */ - int dma_burst_sz; - - /* Bits per pixel */ - int bpp; - - /* FIFO DMA Request Delay */ - int fdd; - - /* TFT Alternative Signal Mapping (Only for active) */ - unsigned char tft_alt_mode; - - /* 12 Bit Per Pixel (5-6-5) Mode (Only for passive) */ - unsigned char stn_565_mode; - - /* Mono 8-bit Mode: 1=D0-D7 or 0=D0-D3 */ - unsigned char mono_8bit_mode; - - /* Invert line clock */ - unsigned char invert_line_clock; - - /* Invert frame clock */ - unsigned char invert_frm_clock; - - /* Horizontal and Vertical Sync Edge: 0=rising 1=falling */ - unsigned char sync_edge; - - /* Horizontal and Vertical Sync: Control: 0=ignore */ - unsigned char sync_ctrl; - - /* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */ - unsigned char raster_order; -}; - -struct lcd_sync_arg { - int back_porch; - int front_porch; - int pulse_width; -}; - -/* ioctls */ -#define FBIOGET_CONTRAST _IOR('F', 1, int) -#define FBIOPUT_CONTRAST _IOW('F', 2, int) -#define FBIGET_BRIGHTNESS _IOR('F', 3, int) -#define FBIPUT_BRIGHTNESS _IOW('F', 3, int) -#define FBIGET_COLOR _IOR('F', 5, int) -#define FBIPUT_COLOR _IOW('F', 6, int) -#define FBIPUT_HSYNC _IOW('F', 9, int) -#define FBIPUT_VSYNC _IOW('F', 10, int) - -#endif /* ifndef DA8XX_FB_H */ - diff --git a/ANDROID_3.4.5/include/video/edid.h b/ANDROID_3.4.5/include/video/edid.h deleted file mode 100644 index c5f19870..00000000 --- a/ANDROID_3.4.5/include/video/edid.h +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef __linux_video_edid_h__ -#define __linux_video_edid_h__ - -struct edid_info { - unsigned char dummy[128]; -}; - -#ifdef __KERNEL__ -#ifdef CONFIG_X86 -extern struct edid_info edid_info; -#endif -#endif - -#endif /* __linux_video_edid_h__ */ diff --git a/ANDROID_3.4.5/include/video/epson1355.h b/ANDROID_3.4.5/include/video/epson1355.h deleted file mode 100644 index 9759f299..00000000 --- a/ANDROID_3.4.5/include/video/epson1355.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * include/video/epson13xx.h -- Epson 13xx frame buffer - * - * Copyright (C) Hewlett-Packard Company. All rights reserved. - * - * Written by Christopher Hoover <ch@hpl.hp.com> - * - */ - -#ifndef _EPSON13XX_H_ -#define _EPSON13XX_H_ - -#define REG_REVISION_CODE 0x00 -#define REG_MEMORY_CONFIG 0x01 -#define REG_PANEL_TYPE 0x02 -#define REG_MOD_RATE 0x03 -#define REG_HORZ_DISP_WIDTH 0x04 -#define REG_HORZ_NONDISP_PERIOD 0x05 -#define REG_HRTC_START_POSITION 0x06 -#define REG_HRTC_PULSE_WIDTH 0x07 -#define REG_VERT_DISP_HEIGHT0 0x08 -#define REG_VERT_DISP_HEIGHT1 0x09 -#define REG_VERT_NONDISP_PERIOD 0x0A -#define REG_VRTC_START_POSITION 0x0B -#define REG_VRTC_PULSE_WIDTH 0x0C -#define REG_DISPLAY_MODE 0x0D -#define REG_SCRN1_LINE_COMPARE0 0x0E -#define REG_SCRN1_LINE_COMPARE1 0x0F -#define REG_SCRN1_DISP_START_ADDR0 0x10 -#define REG_SCRN1_DISP_START_ADDR1 0x11 -#define REG_SCRN1_DISP_START_ADDR2 0x12 -#define REG_SCRN2_DISP_START_ADDR0 0x13 -#define REG_SCRN2_DISP_START_ADDR1 0x14 -#define REG_SCRN2_DISP_START_ADDR2 0x15 -#define REG_MEM_ADDR_OFFSET0 0x16 -#define REG_MEM_ADDR_OFFSET1 0x17 -#define REG_PIXEL_PANNING 0x18 -#define REG_CLOCK_CONFIG 0x19 -#define REG_POWER_SAVE_CONFIG 0x1A -#define REG_MISC 0x1B -#define REG_MD_CONFIG_READBACK0 0x1C -#define REG_MD_CONFIG_READBACK1 0x1D -#define REG_GPIO_CONFIG0 0x1E -#define REG_GPIO_CONFIG1 0x1F -#define REG_GPIO_CONTROL0 0x20 -#define REG_GPIO_CONTROL1 0x21 -#define REG_PERF_ENHANCEMENT0 0x22 -#define REG_PERF_ENHANCEMENT1 0x23 -#define REG_LUT_ADDR 0x24 -#define REG_RESERVED_1 0x25 -#define REG_LUT_DATA 0x26 -#define REG_INK_CURSOR_CONTROL 0x27 -#define REG_CURSOR_X_POSITION0 0x28 -#define REG_CURSOR_X_POSITION1 0x29 -#define REG_CURSOR_Y_POSITION0 0x2A -#define REG_CURSOR_Y_POSITION1 0x2B -#define REG_INK_CURSOR_COLOR0_0 0x2C -#define REG_INK_CURSOR_COLOR0_1 0x2D -#define REG_INK_CURSOR_COLOR1_0 0x2E -#define REG_INK_CURSOR_COLOR1_1 0x2F -#define REG_INK_CURSOR_START_ADDR 0x30 -#define REG_ALTERNATE_FRM 0x31 - -#endif diff --git a/ANDROID_3.4.5/include/video/exynos_dp.h b/ANDROID_3.4.5/include/video/exynos_dp.h deleted file mode 100644 index 8847a9d6..00000000 --- a/ANDROID_3.4.5/include/video/exynos_dp.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * Samsung SoC DP device support - * - * Copyright (C) 2012 Samsung Electronics Co., Ltd. - * Author: Jingoo Han <jg1.han@samsung.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef _EXYNOS_DP_H -#define _EXYNOS_DP_H - -#define DP_TIMEOUT_LOOP_COUNT 100 -#define MAX_CR_LOOP 5 -#define MAX_EQ_LOOP 4 - -enum link_rate_type { - LINK_RATE_1_62GBPS = 0x06, - LINK_RATE_2_70GBPS = 0x0a -}; - -enum link_lane_count_type { - LANE_COUNT1 = 1, - LANE_COUNT2 = 2, - LANE_COUNT4 = 4 -}; - -enum link_training_state { - START, - CLOCK_RECOVERY, - EQUALIZER_TRAINING, - FINISHED, - FAILED -}; - -enum voltage_swing_level { - VOLTAGE_LEVEL_0, - VOLTAGE_LEVEL_1, - VOLTAGE_LEVEL_2, - VOLTAGE_LEVEL_3, -}; - -enum pre_emphasis_level { - PRE_EMPHASIS_LEVEL_0, - PRE_EMPHASIS_LEVEL_1, - PRE_EMPHASIS_LEVEL_2, - PRE_EMPHASIS_LEVEL_3, -}; - -enum pattern_set { - PRBS7, - D10_2, - TRAINING_PTN1, - TRAINING_PTN2, - DP_NONE -}; - -enum color_space { - COLOR_RGB, - COLOR_YCBCR422, - COLOR_YCBCR444 -}; - -enum color_depth { - COLOR_6, - COLOR_8, - COLOR_10, - COLOR_12 -}; - -enum color_coefficient { - COLOR_YCBCR601, - COLOR_YCBCR709 -}; - -enum dynamic_range { - VESA, - CEA -}; - -enum pll_status { - PLL_UNLOCKED, - PLL_LOCKED -}; - -enum clock_recovery_m_value_type { - CALCULATED_M, - REGISTER_M -}; - -enum video_timing_recognition_type { - VIDEO_TIMING_FROM_CAPTURE, - VIDEO_TIMING_FROM_REGISTER -}; - -enum analog_power_block { - AUX_BLOCK, - CH0_BLOCK, - CH1_BLOCK, - CH2_BLOCK, - CH3_BLOCK, - ANALOG_TOTAL, - POWER_ALL -}; - -struct video_info { - char *name; - - bool h_sync_polarity; - bool v_sync_polarity; - bool interlaced; - - enum color_space color_space; - enum dynamic_range dynamic_range; - enum color_coefficient ycbcr_coeff; - enum color_depth color_depth; - - enum link_rate_type link_rate; - enum link_lane_count_type lane_count; -}; - -struct exynos_dp_platdata { - struct video_info *video_info; - - void (*phy_init)(void); - void (*phy_exit)(void); -}; - -#endif /* _EXYNOS_DP_H */ diff --git a/ANDROID_3.4.5/include/video/exynos_mipi_dsim.h b/ANDROID_3.4.5/include/video/exynos_mipi_dsim.h deleted file mode 100644 index 772c7705..00000000 --- a/ANDROID_3.4.5/include/video/exynos_mipi_dsim.h +++ /dev/null @@ -1,359 +0,0 @@ -/* include/video/exynos_mipi_dsim.h - * - * Platform data header for Samsung SoC MIPI-DSIM. - * - * Copyright (c) 2012 Samsung Electronics Co., Ltd - * - * InKi Dae <inki.dae@samsung.com> - * Donghwa Lee <dh09.lee@samsung.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef _EXYNOS_MIPI_DSIM_H -#define _EXYNOS_MIPI_DSIM_H - -#include <linux/device.h> -#include <linux/fb.h> - -#define PANEL_NAME_SIZE (32) - -/* - * Enumerate display interface type. - * - * DSIM_COMMAND means cpu interface and rgb interface for DSIM_VIDEO. - * - * P.S. MIPI DSI Master has two display controller intefaces, RGB Interface - * for main display and CPU Interface(same as I80 Interface) for main - * and sub display. - */ -enum mipi_dsim_interface_type { - DSIM_COMMAND, - DSIM_VIDEO -}; - -enum mipi_dsim_virtual_ch_no { - DSIM_VIRTUAL_CH_0, - DSIM_VIRTUAL_CH_1, - DSIM_VIRTUAL_CH_2, - DSIM_VIRTUAL_CH_3 -}; - -enum mipi_dsim_burst_mode_type { - DSIM_NON_BURST_SYNC_EVENT, - DSIM_BURST_SYNC_EVENT, - DSIM_NON_BURST_SYNC_PULSE, - DSIM_BURST, - DSIM_NON_VIDEO_MODE -}; - -enum mipi_dsim_no_of_data_lane { - DSIM_DATA_LANE_1, - DSIM_DATA_LANE_2, - DSIM_DATA_LANE_3, - DSIM_DATA_LANE_4 -}; - -enum mipi_dsim_byte_clk_src { - DSIM_PLL_OUT_DIV8, - DSIM_EXT_CLK_DIV8, - DSIM_EXT_CLK_BYPASS -}; - -enum mipi_dsim_pixel_format { - DSIM_CMD_3BPP, - DSIM_CMD_8BPP, - DSIM_CMD_12BPP, - DSIM_CMD_16BPP, - DSIM_VID_16BPP_565, - DSIM_VID_18BPP_666PACKED, - DSIM_18BPP_666LOOSELYPACKED, - DSIM_24BPP_888 -}; - -/* - * struct mipi_dsim_config - interface for configuring mipi-dsi controller. - * - * @auto_flush: enable or disable Auto flush of MD FIFO using VSYNC pulse. - * @eot_disable: enable or disable EoT packet in HS mode. - * @auto_vertical_cnt: specifies auto vertical count mode. - * in Video mode, the vertical line transition uses line counter - * configured by VSA, VBP, and Vertical resolution. - * If this bit is set to '1', the line counter does not use VSA and VBP - * registers.(in command mode, this variable is ignored) - * @hse: set horizontal sync event mode. - * In VSYNC pulse and Vporch area, MIPI DSI master transfers only HSYNC - * start packet to MIPI DSI slave at MIPI DSI spec1.1r02. - * this bit transfers HSYNC end packet in VSYNC pulse and Vporch area - * (in mommand mode, this variable is ignored) - * @hfp: specifies HFP disable mode. - * if this variable is set, DSI master ignores HFP area in VIDEO mode. - * (in command mode, this variable is ignored) - * @hbp: specifies HBP disable mode. - * if this variable is set, DSI master ignores HBP area in VIDEO mode. - * (in command mode, this variable is ignored) - * @hsa: specifies HSA disable mode. - * if this variable is set, DSI master ignores HSA area in VIDEO mode. - * (in command mode, this variable is ignored) - * @cma_allow: specifies the number of horizontal lines, where command packet - * transmission is allowed after Stable VFP period. - * @e_interface: specifies interface to be used.(CPU or RGB interface) - * @e_virtual_ch: specifies virtual channel number that main or - * sub diaplsy uses. - * @e_pixel_format: specifies pixel stream format for main or sub display. - * @e_burst_mode: selects Burst mode in Video mode. - * in Non-burst mode, RGB data area is filled with RGB data and NULL - * packets, according to input bandwidth of RGB interface. - * In Burst mode, RGB data area is filled with RGB data only. - * @e_no_data_lane: specifies data lane count to be used by Master. - * @e_byte_clk: select byte clock source. (it must be DSIM_PLL_OUT_DIV8) - * DSIM_EXT_CLK_DIV8 and DSIM_EXT_CLK_BYPASSS are not supported. - * @pll_stable_time: specifies the PLL Timer for stability of the ganerated - * clock(System clock cycle base) - * if the timer value goes to 0x00000000, the clock stable bit of status - * and interrupt register is set. - * @esc_clk: specifies escape clock frequency for getting the escape clock - * prescaler value. - * @stop_holding_cnt: specifies the interval value between transmitting - * read packet(or write "set_tear_on" command) and BTA request. - * after transmitting read packet or write "set_tear_on" command, - * BTA requests to D-PHY automatically. this counter value specifies - * the interval between them. - * @bta_timeout: specifies the timer for BTA. - * this register specifies time out from BTA request to change - * the direction with respect to Tx escape clock. - * @rx_timeout: specifies the timer for LP Rx mode timeout. - * this register specifies time out on how long RxValid deasserts, - * after RxLpdt asserts with respect to Tx escape clock. - * - RxValid specifies Rx data valid indicator. - * - RxLpdt specifies an indicator that D-PHY is under RxLpdt mode. - * - RxValid and RxLpdt specifies signal from D-PHY. - */ -struct mipi_dsim_config { - unsigned char auto_flush; - unsigned char eot_disable; - - unsigned char auto_vertical_cnt; - unsigned char hse; - unsigned char hfp; - unsigned char hbp; - unsigned char hsa; - unsigned char cmd_allow; - - enum mipi_dsim_interface_type e_interface; - enum mipi_dsim_virtual_ch_no e_virtual_ch; - enum mipi_dsim_pixel_format e_pixel_format; - enum mipi_dsim_burst_mode_type e_burst_mode; - enum mipi_dsim_no_of_data_lane e_no_data_lane; - enum mipi_dsim_byte_clk_src e_byte_clk; - - /* - * =========================================== - * | P | M | S | MHz | - * ------------------------------------------- - * | 3 | 100 | 3 | 100 | - * | 3 | 100 | 2 | 200 | - * | 3 | 63 | 1 | 252 | - * | 4 | 100 | 1 | 300 | - * | 4 | 110 | 1 | 330 | - * | 12 | 350 | 1 | 350 | - * | 3 | 100 | 1 | 400 | - * | 4 | 150 | 1 | 450 | - * | 6 | 118 | 1 | 472 | - * | 3 | 120 | 1 | 480 | - * | 12 | 250 | 0 | 500 | - * | 4 | 100 | 0 | 600 | - * | 3 | 81 | 0 | 648 | - * | 3 | 88 | 0 | 704 | - * | 3 | 90 | 0 | 720 | - * | 3 | 100 | 0 | 800 | - * | 12 | 425 | 0 | 850 | - * | 4 | 150 | 0 | 900 | - * | 12 | 475 | 0 | 950 | - * | 6 | 250 | 0 | 1000 | - * ------------------------------------------- - */ - - /* - * pms could be calculated as the following. - * M * 24 / P * 2 ^ S = MHz - */ - unsigned char p; - unsigned short m; - unsigned char s; - - unsigned int pll_stable_time; - unsigned long esc_clk; - - unsigned short stop_holding_cnt; - unsigned char bta_timeout; - unsigned short rx_timeout; -}; - -/* - * struct mipi_dsim_device - global interface for mipi-dsi driver. - * - * @dev: driver model representation of the device. - * @id: unique device id. - * @clock: pointer to MIPI-DSI clock of clock framework. - * @irq: interrupt number to MIPI-DSI controller. - * @reg_base: base address to memory mapped SRF of MIPI-DSI controller. - * (virtual address) - * @lock: the mutex protecting this data structure. - * @dsim_info: infomation for configuring mipi-dsi controller. - * @master_ops: callbacks to mipi-dsi operations. - * @dsim_lcd_dev: pointer to activated ddi device. - * (it would be registered by mipi-dsi driver.) - * @dsim_lcd_drv: pointer to activated_ddi driver. - * (it would be registered by mipi-dsi driver.) - * @lcd_info: pointer to mipi_lcd_info structure. - * @state: specifies status of MIPI-DSI controller. - * the status could be RESET, INIT, STOP, HSCLKEN and ULPS. - * @data_lane: specifiec enabled data lane number. - * this variable would be set by driver according to e_no_data_lane - * automatically. - * @e_clk_src: select byte clock source. - * @pd: pointer to MIPI-DSI driver platform data. - */ -struct mipi_dsim_device { - struct device *dev; - int id; - struct resource *res; - struct clk *clock; - unsigned int irq; - void __iomem *reg_base; - struct mutex lock; - - struct mipi_dsim_config *dsim_config; - struct mipi_dsim_master_ops *master_ops; - struct mipi_dsim_lcd_device *dsim_lcd_dev; - struct mipi_dsim_lcd_driver *dsim_lcd_drv; - - unsigned int state; - unsigned int data_lane; - unsigned int e_clk_src; - bool suspended; - - struct mipi_dsim_platform_data *pd; -}; - -/* - * struct mipi_dsim_platform_data - interface to platform data - * for mipi-dsi driver. - * - * @lcd_panel_name: specifies lcd panel name registered to mipi-dsi driver. - * lcd panel driver searched would be actived. - * @dsim_config: pointer of structure for configuring mipi-dsi controller. - * @enabled: indicate whether mipi controller got enabled or not. - * @lcd_panel_info: pointer for lcd panel specific structure. - * this structure specifies width, height, timing and polarity and so on. - * @phy_enable: pointer to a callback controlling D-PHY enable/reset - */ -struct mipi_dsim_platform_data { - char lcd_panel_name[PANEL_NAME_SIZE]; - - struct mipi_dsim_config *dsim_config; - unsigned int enabled; - void *lcd_panel_info; - - int (*phy_enable)(struct platform_device *pdev, bool on); -}; - -/* - * struct mipi_dsim_master_ops - callbacks to mipi-dsi operations. - * - * @cmd_write: transfer command to lcd panel at LP mode. - * @cmd_read: read command from rx register. - * @get_dsim_frame_done: get the status that all screen data have been - * transferred to mipi-dsi. - * @clear_dsim_frame_done: clear frame done status. - * @get_fb_frame_done: get frame done status of display controller. - * @trigger: trigger display controller. - * - this one would be used only in case of CPU mode. - * @set_early_blank_mode: set framebuffer blank mode. - * - this callback should be called prior to fb_blank() by a client driver - * only if needing. - * @set_blank_mode: set framebuffer blank mode. - * - this callback should be called after fb_blank() by a client driver - * only if needing. - */ - -struct mipi_dsim_master_ops { - int (*cmd_write)(struct mipi_dsim_device *dsim, unsigned int data_id, - const unsigned char *data0, unsigned int data1); - int (*cmd_read)(struct mipi_dsim_device *dsim, unsigned int data_id, - unsigned int data0, unsigned int req_size, u8 *rx_buf); - int (*get_dsim_frame_done)(struct mipi_dsim_device *dsim); - int (*clear_dsim_frame_done)(struct mipi_dsim_device *dsim); - - int (*get_fb_frame_done)(struct fb_info *info); - void (*trigger)(struct fb_info *info); - int (*set_early_blank_mode)(struct mipi_dsim_device *dsim, int power); - int (*set_blank_mode)(struct mipi_dsim_device *dsim, int power); -}; - -/* - * device structure for mipi-dsi based lcd panel. - * - * @name: name of the device to use with this device, or an - * alias for that name. - * @dev: driver model representation of the device. - * @id: id of device to be registered. - * @bus_id: bus id for identifing connected bus - * and this bus id should be same as id of mipi_dsim_device. - * @irq: irq number for signaling when framebuffer transfer of - * lcd panel module is completed. - * this irq would be used only for MIPI-DSI based CPU mode lcd panel. - * @master: pointer to mipi-dsi master device object. - * @platform_data: lcd panel specific platform data. - */ -struct mipi_dsim_lcd_device { - char *name; - struct device dev; - int id; - int bus_id; - int irq; - - struct mipi_dsim_device *master; - void *platform_data; -}; - -/* - * driver structure for mipi-dsi based lcd panel. - * - * this structure should be registered by lcd panel driver. - * mipi-dsi driver seeks lcd panel registered through name field - * and calls these callback functions in appropriate time. - * - * @name: name of the driver to use with this device, or an - * alias for that name. - * @id: id of driver to be registered. - * this id would be used for finding device object registered. - */ -struct mipi_dsim_lcd_driver { - char *name; - int id; - - void (*power_on)(struct mipi_dsim_lcd_device *dsim_dev, int enable); - void (*set_sequence)(struct mipi_dsim_lcd_device *dsim_dev); - int (*probe)(struct mipi_dsim_lcd_device *dsim_dev); - int (*remove)(struct mipi_dsim_lcd_device *dsim_dev); - void (*shutdown)(struct mipi_dsim_lcd_device *dsim_dev); - int (*suspend)(struct mipi_dsim_lcd_device *dsim_dev); - int (*resume)(struct mipi_dsim_lcd_device *dsim_dev); -}; - -/* - * register mipi_dsim_lcd_device to mipi-dsi master. - */ -int exynos_mipi_dsi_register_lcd_device(struct mipi_dsim_lcd_device - *lcd_dev); -/** - * register mipi_dsim_lcd_driver object defined by lcd panel driver - * to mipi-dsi driver. - */ -int exynos_mipi_dsi_register_lcd_driver(struct mipi_dsim_lcd_driver - *lcd_drv); -#endif /* _EXYNOS_MIPI_DSIM_H */ diff --git a/ANDROID_3.4.5/include/video/gbe.h b/ANDROID_3.4.5/include/video/gbe.h deleted file mode 100644 index ad510284..00000000 --- a/ANDROID_3.4.5/include/video/gbe.h +++ /dev/null @@ -1,317 +0,0 @@ -/* - * include/video/gbe.h -- SGI GBE (Graphics Back End) - * - * Copyright (C) 1999 Silicon Graphics, Inc. (Jeffrey Newquist) - * - * This file is subject to the terms and conditions of the GNU General Public - * License version 2 as published by the Free Software Foundation. - */ - -#ifndef __GBE_H__ -#define __GBE_H__ - -struct sgi_gbe { - volatile uint32_t ctrlstat; /* general control */ - volatile uint32_t dotclock; /* dot clock PLL control */ - volatile uint32_t i2c; /* crt I2C control */ - volatile uint32_t sysclk; /* system clock PLL control */ - volatile uint32_t i2cfp; /* flat panel I2C control */ - volatile uint32_t id; /* device id/chip revision */ - volatile uint32_t config; /* power on configuration [1] */ - volatile uint32_t bist; /* internal bist status [1] */ - uint32_t _pad0[0x010000/4 - 8]; - volatile uint32_t vt_xy; /* current dot coords */ - volatile uint32_t vt_xymax; /* maximum dot coords */ - volatile uint32_t vt_vsync; /* vsync on/off */ - volatile uint32_t vt_hsync; /* hsync on/off */ - volatile uint32_t vt_vblank; /* vblank on/off */ - volatile uint32_t vt_hblank; /* hblank on/off */ - volatile uint32_t vt_flags; /* polarity of vt signals */ - volatile uint32_t vt_f2rf_lock; /* f2rf & framelck y coord */ - volatile uint32_t vt_intr01; /* intr 0,1 y coords */ - volatile uint32_t vt_intr23; /* intr 2,3 y coords */ - volatile uint32_t fp_hdrv; /* flat panel hdrv on/off */ - volatile uint32_t fp_vdrv; /* flat panel vdrv on/off */ - volatile uint32_t fp_de; /* flat panel de on/off */ - volatile uint32_t vt_hpixen; /* intrnl horiz pixel on/off */ - volatile uint32_t vt_vpixen; /* intrnl vert pixel on/off */ - volatile uint32_t vt_hcmap; /* cmap write (horiz) */ - volatile uint32_t vt_vcmap; /* cmap write (vert) */ - volatile uint32_t did_start_xy; /* eol/f did/xy reset val */ - volatile uint32_t crs_start_xy; /* eol/f crs/xy reset val */ - volatile uint32_t vc_start_xy; /* eol/f vc/xy reset val */ - uint32_t _pad1[0xffb0/4]; - volatile uint32_t ovr_width_tile;/*overlay plane ctrl 0 */ - volatile uint32_t ovr_inhwctrl; /* overlay plane ctrl 1 */ - volatile uint32_t ovr_control; /* overlay plane ctrl 1 */ - uint32_t _pad2[0xfff4/4]; - volatile uint32_t frm_size_tile;/* normal plane ctrl 0 */ - volatile uint32_t frm_size_pixel;/*normal plane ctrl 1 */ - volatile uint32_t frm_inhwctrl; /* normal plane ctrl 2 */ - volatile uint32_t frm_control; /* normal plane ctrl 3 */ - uint32_t _pad3[0xfff0/4]; - volatile uint32_t did_inhwctrl; /* DID control */ - volatile uint32_t did_control; /* DID shadow */ - uint32_t _pad4[0x7ff8/4]; - volatile uint32_t mode_regs[32];/* WID table */ - uint32_t _pad5[0x7f80/4]; - volatile uint32_t cmap[6144]; /* color map */ - uint32_t _pad6[0x2000/4]; - volatile uint32_t cm_fifo; /* color map fifo status */ - uint32_t _pad7[0x7ffc/4]; - volatile uint32_t gmap[256]; /* gamma map */ - uint32_t _pad8[0x7c00/4]; - volatile uint32_t gmap10[1024]; /* gamma map */ - uint32_t _pad9[0x7000/4]; - volatile uint32_t crs_pos; /* cusror control 0 */ - volatile uint32_t crs_ctl; /* cusror control 1 */ - volatile uint32_t crs_cmap[3]; /* crs cmap */ - uint32_t _pad10[0x7fec/4]; - volatile uint32_t crs_glyph[64];/* crs glyph */ - uint32_t _pad11[0x7f00/4]; - volatile uint32_t vc_0; /* video capture crtl 0 */ - volatile uint32_t vc_1; /* video capture crtl 1 */ - volatile uint32_t vc_2; /* video capture crtl 2 */ - volatile uint32_t vc_3; /* video capture crtl 3 */ - volatile uint32_t vc_4; /* video capture crtl 4 */ - volatile uint32_t vc_5; /* video capture crtl 5 */ - volatile uint32_t vc_6; /* video capture crtl 6 */ - volatile uint32_t vc_7; /* video capture crtl 7 */ - volatile uint32_t vc_8; /* video capture crtl 8 */ -}; - -#define MASK(msb, lsb) \ - ( (((u32)1<<((msb)-(lsb)+1))-1) << (lsb) ) -#define GET(v, msb, lsb) \ - ( ((u32)(v) & MASK(msb,lsb)) >> (lsb) ) -#define SET(v, f, msb, lsb) \ - ( (v) = ((v)&~MASK(msb,lsb)) | (( (u32)(f)<<(lsb) ) & MASK(msb,lsb)) ) - -#define GET_GBE_FIELD(reg, field, v) \ - GET((v), GBE_##reg##_##field##_MSB, GBE_##reg##_##field##_LSB) -#define SET_GBE_FIELD(reg, field, v, f) \ - SET((v), (f), GBE_##reg##_##field##_MSB, GBE_##reg##_##field##_LSB) - -/* - * Bit mask information - */ -#define GBE_CTRLSTAT_CHIPID_MSB 3 -#define GBE_CTRLSTAT_CHIPID_LSB 0 -#define GBE_CTRLSTAT_SENSE_N_MSB 4 -#define GBE_CTRLSTAT_SENSE_N_LSB 4 -#define GBE_CTRLSTAT_PCLKSEL_MSB 29 -#define GBE_CTRLSTAT_PCLKSEL_LSB 28 - -#define GBE_DOTCLK_M_MSB 7 -#define GBE_DOTCLK_M_LSB 0 -#define GBE_DOTCLK_N_MSB 13 -#define GBE_DOTCLK_N_LSB 8 -#define GBE_DOTCLK_P_MSB 15 -#define GBE_DOTCLK_P_LSB 14 -#define GBE_DOTCLK_RUN_MSB 20 -#define GBE_DOTCLK_RUN_LSB 20 - -#define GBE_VT_XY_Y_MSB 23 -#define GBE_VT_XY_Y_LSB 12 -#define GBE_VT_XY_X_MSB 11 -#define GBE_VT_XY_X_LSB 0 -#define GBE_VT_XY_FREEZE_MSB 31 -#define GBE_VT_XY_FREEZE_LSB 31 - -#define GBE_FP_VDRV_ON_MSB 23 -#define GBE_FP_VDRV_ON_LSB 12 -#define GBE_FP_VDRV_OFF_MSB 11 -#define GBE_FP_VDRV_OFF_LSB 0 - -#define GBE_FP_HDRV_ON_MSB 23 -#define GBE_FP_HDRV_ON_LSB 12 -#define GBE_FP_HDRV_OFF_MSB 11 -#define GBE_FP_HDRV_OFF_LSB 0 - -#define GBE_FP_DE_ON_MSB 23 -#define GBE_FP_DE_ON_LSB 12 -#define GBE_FP_DE_OFF_MSB 11 -#define GBE_FP_DE_OFF_LSB 0 - -#define GBE_VT_VSYNC_VSYNC_ON_MSB 23 -#define GBE_VT_VSYNC_VSYNC_ON_LSB 12 -#define GBE_VT_VSYNC_VSYNC_OFF_MSB 11 -#define GBE_VT_VSYNC_VSYNC_OFF_LSB 0 - -#define GBE_VT_HSYNC_HSYNC_ON_MSB 23 -#define GBE_VT_HSYNC_HSYNC_ON_LSB 12 -#define GBE_VT_HSYNC_HSYNC_OFF_MSB 11 -#define GBE_VT_HSYNC_HSYNC_OFF_LSB 0 - -#define GBE_VT_VBLANK_VBLANK_ON_MSB 23 -#define GBE_VT_VBLANK_VBLANK_ON_LSB 12 -#define GBE_VT_VBLANK_VBLANK_OFF_MSB 11 -#define GBE_VT_VBLANK_VBLANK_OFF_LSB 0 - -#define GBE_VT_HBLANK_HBLANK_ON_MSB 23 -#define GBE_VT_HBLANK_HBLANK_ON_LSB 12 -#define GBE_VT_HBLANK_HBLANK_OFF_MSB 11 -#define GBE_VT_HBLANK_HBLANK_OFF_LSB 0 - -#define GBE_VT_FLAGS_F2RF_HIGH_MSB 6 -#define GBE_VT_FLAGS_F2RF_HIGH_LSB 6 -#define GBE_VT_FLAGS_SYNC_LOW_MSB 5 -#define GBE_VT_FLAGS_SYNC_LOW_LSB 5 -#define GBE_VT_FLAGS_SYNC_HIGH_MSB 4 -#define GBE_VT_FLAGS_SYNC_HIGH_LSB 4 -#define GBE_VT_FLAGS_HDRV_LOW_MSB 3 -#define GBE_VT_FLAGS_HDRV_LOW_LSB 3 -#define GBE_VT_FLAGS_HDRV_INVERT_MSB 2 -#define GBE_VT_FLAGS_HDRV_INVERT_LSB 2 -#define GBE_VT_FLAGS_VDRV_LOW_MSB 1 -#define GBE_VT_FLAGS_VDRV_LOW_LSB 1 -#define GBE_VT_FLAGS_VDRV_INVERT_MSB 0 -#define GBE_VT_FLAGS_VDRV_INVERT_LSB 0 - -#define GBE_VT_VCMAP_VCMAP_ON_MSB 23 -#define GBE_VT_VCMAP_VCMAP_ON_LSB 12 -#define GBE_VT_VCMAP_VCMAP_OFF_MSB 11 -#define GBE_VT_VCMAP_VCMAP_OFF_LSB 0 - -#define GBE_VT_HCMAP_HCMAP_ON_MSB 23 -#define GBE_VT_HCMAP_HCMAP_ON_LSB 12 -#define GBE_VT_HCMAP_HCMAP_OFF_MSB 11 -#define GBE_VT_HCMAP_HCMAP_OFF_LSB 0 - -#define GBE_VT_XYMAX_MAXX_MSB 11 -#define GBE_VT_XYMAX_MAXX_LSB 0 -#define GBE_VT_XYMAX_MAXY_MSB 23 -#define GBE_VT_XYMAX_MAXY_LSB 12 - -#define GBE_VT_HPIXEN_HPIXEN_ON_MSB 23 -#define GBE_VT_HPIXEN_HPIXEN_ON_LSB 12 -#define GBE_VT_HPIXEN_HPIXEN_OFF_MSB 11 -#define GBE_VT_HPIXEN_HPIXEN_OFF_LSB 0 - -#define GBE_VT_VPIXEN_VPIXEN_ON_MSB 23 -#define GBE_VT_VPIXEN_VPIXEN_ON_LSB 12 -#define GBE_VT_VPIXEN_VPIXEN_OFF_MSB 11 -#define GBE_VT_VPIXEN_VPIXEN_OFF_LSB 0 - -#define GBE_OVR_CONTROL_OVR_DMA_ENABLE_MSB 0 -#define GBE_OVR_CONTROL_OVR_DMA_ENABLE_LSB 0 - -#define GBE_OVR_INHWCTRL_OVR_DMA_ENABLE_MSB 0 -#define GBE_OVR_INHWCTRL_OVR_DMA_ENABLE_LSB 0 - -#define GBE_OVR_WIDTH_TILE_OVR_FIFO_RESET_MSB 13 -#define GBE_OVR_WIDTH_TILE_OVR_FIFO_RESET_LSB 13 - -#define GBE_FRM_CONTROL_FRM_DMA_ENABLE_MSB 0 -#define GBE_FRM_CONTROL_FRM_DMA_ENABLE_LSB 0 -#define GBE_FRM_CONTROL_FRM_TILE_PTR_MSB 31 -#define GBE_FRM_CONTROL_FRM_TILE_PTR_LSB 9 -#define GBE_FRM_CONTROL_FRM_LINEAR_MSB 1 -#define GBE_FRM_CONTROL_FRM_LINEAR_LSB 1 - -#define GBE_FRM_INHWCTRL_FRM_DMA_ENABLE_MSB 0 -#define GBE_FRM_INHWCTRL_FRM_DMA_ENABLE_LSB 0 - -#define GBE_FRM_SIZE_TILE_FRM_WIDTH_TILE_MSB 12 -#define GBE_FRM_SIZE_TILE_FRM_WIDTH_TILE_LSB 5 -#define GBE_FRM_SIZE_TILE_FRM_RHS_MSB 4 -#define GBE_FRM_SIZE_TILE_FRM_RHS_LSB 0 -#define GBE_FRM_SIZE_TILE_FRM_DEPTH_MSB 14 -#define GBE_FRM_SIZE_TILE_FRM_DEPTH_LSB 13 -#define GBE_FRM_SIZE_TILE_FRM_FIFO_RESET_MSB 15 -#define GBE_FRM_SIZE_TILE_FRM_FIFO_RESET_LSB 15 - -#define GBE_FRM_SIZE_PIXEL_FB_HEIGHT_PIX_MSB 31 -#define GBE_FRM_SIZE_PIXEL_FB_HEIGHT_PIX_LSB 16 - -#define GBE_DID_CONTROL_DID_DMA_ENABLE_MSB 0 -#define GBE_DID_CONTROL_DID_DMA_ENABLE_LSB 0 -#define GBE_DID_INHWCTRL_DID_DMA_ENABLE_MSB 0 -#define GBE_DID_INHWCTRL_DID_DMA_ENABLE_LSB 0 - -#define GBE_DID_START_XY_DID_STARTY_MSB 23 -#define GBE_DID_START_XY_DID_STARTY_LSB 12 -#define GBE_DID_START_XY_DID_STARTX_MSB 11 -#define GBE_DID_START_XY_DID_STARTX_LSB 0 - -#define GBE_CRS_START_XY_CRS_STARTY_MSB 23 -#define GBE_CRS_START_XY_CRS_STARTY_LSB 12 -#define GBE_CRS_START_XY_CRS_STARTX_MSB 11 -#define GBE_CRS_START_XY_CRS_STARTX_LSB 0 - -#define GBE_WID_AUX_MSB 12 -#define GBE_WID_AUX_LSB 11 -#define GBE_WID_GAMMA_MSB 10 -#define GBE_WID_GAMMA_LSB 10 -#define GBE_WID_CM_MSB 9 -#define GBE_WID_CM_LSB 5 -#define GBE_WID_TYP_MSB 4 -#define GBE_WID_TYP_LSB 2 -#define GBE_WID_BUF_MSB 1 -#define GBE_WID_BUF_LSB 0 - -#define GBE_VC_START_XY_VC_STARTY_MSB 23 -#define GBE_VC_START_XY_VC_STARTY_LSB 12 -#define GBE_VC_START_XY_VC_STARTX_MSB 11 -#define GBE_VC_START_XY_VC_STARTX_LSB 0 - -/* Constants */ - -#define GBE_FRM_DEPTH_8 0 -#define GBE_FRM_DEPTH_16 1 -#define GBE_FRM_DEPTH_32 2 - -#define GBE_CMODE_I8 0 -#define GBE_CMODE_I12 1 -#define GBE_CMODE_RG3B2 2 -#define GBE_CMODE_RGB4 3 -#define GBE_CMODE_ARGB5 4 -#define GBE_CMODE_RGB8 5 -#define GBE_CMODE_RGBA5 6 -#define GBE_CMODE_RGB10 7 - -#define GBE_BMODE_BOTH 3 - -#define GBE_CRS_MAGIC 54 -#define GBE_PIXEN_MAGIC_ON 19 -#define GBE_PIXEN_MAGIC_OFF 2 - -#define GBE_TLB_SIZE 128 - -/* [1] - only GBE revision 2 and later */ - -/* - * Video Timing Data Structure - */ - -struct gbe_timing_info { - int flags; - short width; /* Monitor resolution */ - short height; - int fields_sec; /* fields/sec (Hz -3 dec. places */ - int cfreq; /* pixel clock frequency (MHz -3 dec. places) */ - short htotal; /* Horizontal total pixels */ - short hblank_start; /* Horizontal blank start */ - short hblank_end; /* Horizontal blank end */ - short hsync_start; /* Horizontal sync start */ - short hsync_end; /* Horizontal sync end */ - short vtotal; /* Vertical total lines */ - short vblank_start; /* Vertical blank start */ - short vblank_end; /* Vertical blank end */ - short vsync_start; /* Vertical sync start */ - short vsync_end; /* Vertical sync end */ - short pll_m; /* PLL M parameter */ - short pll_n; /* PLL P parameter */ - short pll_p; /* PLL N parameter */ -}; - -/* Defines for gbe_vof_info_t flags */ - -#define GBE_VOF_UNKNOWNMON 1 -#define GBE_VOF_STEREO 2 -#define GBE_VOF_DO_GENSYNC 4 /* enable incoming sync */ -#define GBE_VOF_SYNC_ON_GREEN 8 /* sync on green */ -#define GBE_VOF_FLATPANEL 0x1000 /* FLATPANEL Timing */ -#define GBE_VOF_MAGICKEY 0x2000 /* Backdoor key */ - -#endif /* ! __GBE_H__ */ diff --git a/ANDROID_3.4.5/include/video/hecubafb.h b/ANDROID_3.4.5/include/video/hecubafb.h deleted file mode 100644 index 7b995233..00000000 --- a/ANDROID_3.4.5/include/video/hecubafb.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * hecubafb.h - definitions for the hecuba framebuffer driver - * - * Copyright (C) 2008 by Jaya Kumar - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive for - * more details. - * - */ - -#ifndef _LINUX_HECUBAFB_H_ -#define _LINUX_HECUBAFB_H_ - -/* Apollo controller specific defines */ -#define APOLLO_START_NEW_IMG 0xA0 -#define APOLLO_STOP_IMG_DATA 0xA1 -#define APOLLO_DISPLAY_IMG 0xA2 -#define APOLLO_ERASE_DISPLAY 0xA3 -#define APOLLO_INIT_DISPLAY 0xA4 - -/* Hecuba interface specific defines */ -#define HCB_WUP_BIT 0x01 -#define HCB_DS_BIT 0x02 -#define HCB_RW_BIT 0x04 -#define HCB_CD_BIT 0x08 -#define HCB_ACK_BIT 0x80 - -/* struct used by hecuba. board specific stuff comes from *board */ -struct hecubafb_par { - struct fb_info *info; - struct hecuba_board *board; - void (*send_command)(struct hecubafb_par *, unsigned char); - void (*send_data)(struct hecubafb_par *, unsigned char); -}; - -/* board specific routines -board drivers can implement wait_for_ack with interrupts if desired. if -wait_for_ack is called with clear=0, then go to sleep and return when ack -goes hi or if wait_for_ack with clear=1, then return when ack goes lo */ -struct hecuba_board { - struct module *owner; - void (*remove)(struct hecubafb_par *); - void (*set_ctl)(struct hecubafb_par *, unsigned char, unsigned char); - void (*set_data)(struct hecubafb_par *, unsigned char); - void (*wait_for_ack)(struct hecubafb_par *, int); - int (*init)(struct hecubafb_par *); -}; - - -#endif diff --git a/ANDROID_3.4.5/include/video/iga.h b/ANDROID_3.4.5/include/video/iga.h deleted file mode 100644 index 5a48f165..00000000 --- a/ANDROID_3.4.5/include/video/iga.h +++ /dev/null @@ -1,24 +0,0 @@ -/* $Id: iga.h,v 1.2 1999/09/11 22:56:31 zaitcev Exp $ - * iga1682.h: Sparc/PCI iga1682 driver constants etc. - * - * Copyleft 1998 V. Roganov and G. Raiko - */ - -#ifndef _IGA1682_H -#define _IGA1682_H 1 - -#define IGA_ATTR_CTL 0x3C0 -#define IGA_IDX_VGA_OVERSCAN 0x11 -#define DAC_W_INDEX 0x03C8 -#define DAC_DATA 0x03C9 -#define IGA_EXT_CNTRL 0x3CE -#define IGA_IDX_EXT_BUS_CNTL 0x30 -#define MEM_SIZE_ALIAS 0x3 -#define MEM_SIZE_1M 0x0 -#define MEM_SIZE_2M 0x1 -#define MEM_SIZE_4M 0x2 -#define MEM_SIZE_RESERVED 0x3 -#define IGA_IDX_OVERSCAN_COLOR 0x58 -#define IGA_IDX_EXT_MEM_2 0x72 - -#endif /* !(_IGA1682_H) */ diff --git a/ANDROID_3.4.5/include/video/ili9320.h b/ANDROID_3.4.5/include/video/ili9320.h deleted file mode 100644 index e5d1622e..00000000 --- a/ANDROID_3.4.5/include/video/ili9320.h +++ /dev/null @@ -1,201 +0,0 @@ -/* include/video/ili9320.c - * - * ILI9320 LCD controller configuration control. - * - * Copyright 2007 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * http://armlinux.simtec.co.uk/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#define ILI9320_REG(x) (x) - -#define ILI9320_INDEX ILI9320_REG(0x00) - -#define ILI9320_OSCILATION ILI9320_REG(0x00) -#define ILI9320_DRIVER ILI9320_REG(0x01) -#define ILI9320_DRIVEWAVE ILI9320_REG(0x02) -#define ILI9320_ENTRYMODE ILI9320_REG(0x03) -#define ILI9320_RESIZING ILI9320_REG(0x04) -#define ILI9320_DISPLAY1 ILI9320_REG(0x07) -#define ILI9320_DISPLAY2 ILI9320_REG(0x08) -#define ILI9320_DISPLAY3 ILI9320_REG(0x09) -#define ILI9320_DISPLAY4 ILI9320_REG(0x0A) -#define ILI9320_RGB_IF1 ILI9320_REG(0x0C) -#define ILI9320_FRAMEMAKER ILI9320_REG(0x0D) -#define ILI9320_RGB_IF2 ILI9320_REG(0x0F) - -#define ILI9320_POWER1 ILI9320_REG(0x10) -#define ILI9320_POWER2 ILI9320_REG(0x11) -#define ILI9320_POWER3 ILI9320_REG(0x12) -#define ILI9320_POWER4 ILI9320_REG(0x13) -#define ILI9320_GRAM_HORIZ_ADDR ILI9320_REG(0x20) -#define ILI9320_GRAM_VERT_ADD ILI9320_REG(0x21) -#define ILI9320_POWER7 ILI9320_REG(0x29) -#define ILI9320_FRAME_RATE_COLOUR ILI9320_REG(0x2B) - -#define ILI9320_GAMMA1 ILI9320_REG(0x30) -#define ILI9320_GAMMA2 ILI9320_REG(0x31) -#define ILI9320_GAMMA3 ILI9320_REG(0x32) -#define ILI9320_GAMMA4 ILI9320_REG(0x35) -#define ILI9320_GAMMA5 ILI9320_REG(0x36) -#define ILI9320_GAMMA6 ILI9320_REG(0x37) -#define ILI9320_GAMMA7 ILI9320_REG(0x38) -#define ILI9320_GAMMA8 ILI9320_REG(0x39) -#define ILI9320_GAMMA9 ILI9320_REG(0x3C) -#define ILI9320_GAMMA10 ILI9320_REG(0x3D) - -#define ILI9320_HORIZ_START ILI9320_REG(0x50) -#define ILI9320_HORIZ_END ILI9320_REG(0x51) -#define ILI9320_VERT_START ILI9320_REG(0x52) -#define ILI9320_VERT_END ILI9320_REG(0x53) - -#define ILI9320_DRIVER2 ILI9320_REG(0x60) -#define ILI9320_BASE_IMAGE ILI9320_REG(0x61) -#define ILI9320_VERT_SCROLL ILI9320_REG(0x6a) - -#define ILI9320_PARTIAL1_POSITION ILI9320_REG(0x80) -#define ILI9320_PARTIAL1_START ILI9320_REG(0x81) -#define ILI9320_PARTIAL1_END ILI9320_REG(0x82) -#define ILI9320_PARTIAL2_POSITION ILI9320_REG(0x83) -#define ILI9320_PARTIAL2_START ILI9320_REG(0x84) -#define ILI9320_PARTIAL2_END ILI9320_REG(0x85) - -#define ILI9320_INTERFACE1 ILI9320_REG(0x90) -#define ILI9320_INTERFACE2 ILI9320_REG(0x92) -#define ILI9320_INTERFACE3 ILI9320_REG(0x93) -#define ILI9320_INTERFACE4 ILI9320_REG(0x95) -#define ILI9320_INTERFACE5 ILI9320_REG(0x97) -#define ILI9320_INTERFACE6 ILI9320_REG(0x98) - -/* Register contents definitions. */ - -#define ILI9320_OSCILATION_OSC (1 << 0) - -#define ILI9320_DRIVER_SS (1 << 8) -#define ILI9320_DRIVER_SM (1 << 10) - -#define ILI9320_DRIVEWAVE_EOR (1 << 8) -#define ILI9320_DRIVEWAVE_BC (1 << 9) -#define ILI9320_DRIVEWAVE_MUSTSET (1 << 10) - -#define ILI9320_ENTRYMODE_AM (1 << 3) -#define ILI9320_ENTRYMODE_ID(x) ((x) << 4) -#define ILI9320_ENTRYMODE_ORG (1 << 7) -#define ILI9320_ENTRYMODE_HWM (1 << 8) -#define ILI9320_ENTRYMODE_BGR (1 << 12) -#define ILI9320_ENTRYMODE_DFM (1 << 14) -#define ILI9320_ENTRYMODE_TRI (1 << 15) - - -#define ILI9320_RESIZING_RSZ(x) ((x) << 0) -#define ILI9320_RESIZING_RCH(x) ((x) << 4) -#define ILI9320_RESIZING_RCV(x) ((x) << 8) - - -#define ILI9320_DISPLAY1_D(x) ((x) << 0) -#define ILI9320_DISPLAY1_CL (1 << 3) -#define ILI9320_DISPLAY1_DTE (1 << 4) -#define ILI9320_DISPLAY1_GON (1 << 5) -#define ILI9320_DISPLAY1_BASEE (1 << 8) -#define ILI9320_DISPLAY1_PTDE(x) ((x) << 12) - - -#define ILI9320_DISPLAY2_BP(x) ((x) << 0) -#define ILI9320_DISPLAY2_FP(x) ((x) << 8) - - -#define ILI9320_RGBIF1_RIM_RGB18 (0 << 0) -#define ILI9320_RGBIF1_RIM_RGB16 (1 << 0) -#define ILI9320_RGBIF1_RIM_RGB6 (2 << 0) - -#define ILI9320_RGBIF1_CLK_INT (0 << 4) -#define ILI9320_RGBIF1_CLK_RGBIF (1 << 4) -#define ILI9320_RGBIF1_CLK_VSYNC (2 << 4) - -#define ILI9320_RGBIF1_RM (1 << 8) - -#define ILI9320_RGBIF1_ENC_FRAMES(x) (((x) - 1)<< 13) - -#define ILI9320_RGBIF2_DPL (1 << 0) -#define ILI9320_RGBIF2_EPL (1 << 1) -#define ILI9320_RGBIF2_HSPL (1 << 3) -#define ILI9320_RGBIF2_VSPL (1 << 4) - - -#define ILI9320_POWER1_SLP (1 << 1) -#define ILI9320_POWER1_DSTB (1 << 2) -#define ILI9320_POWER1_AP(x) ((x) << 4) -#define ILI9320_POWER1_APE (1 << 7) -#define ILI9320_POWER1_BT(x) ((x) << 8) -#define ILI9320_POWER1_SAP (1 << 12) - - -#define ILI9320_POWER2_VC(x) ((x) << 0) -#define ILI9320_POWER2_DC0(x) ((x) << 4) -#define ILI9320_POWER2_DC1(x) ((x) << 8) - - -#define ILI9320_POWER3_VRH(x) ((x) << 0) -#define ILI9320_POWER3_PON (1 << 4) -#define ILI9320_POWER3_VCMR (1 << 8) - - -#define ILI9320_POWER4_VREOUT(x) ((x) << 8) - - -#define ILI9320_DRIVER2_SCNL(x) ((x) << 0) -#define ILI9320_DRIVER2_NL(x) ((x) << 8) -#define ILI9320_DRIVER2_GS (1 << 15) - - -#define ILI9320_BASEIMAGE_REV (1 << 0) -#define ILI9320_BASEIMAGE_VLE (1 << 1) -#define ILI9320_BASEIMAGE_NDL (1 << 2) - - -#define ILI9320_INTERFACE4_RTNE(x) (x) -#define ILI9320_INTERFACE4_DIVE(x) ((x) << 8) - -/* SPI interface definitions */ - -#define ILI9320_SPI_IDCODE (0x70) -#define ILI9320_SPI_ID(x) ((x) << 2) -#define ILI9320_SPI_READ (0x01) -#define ILI9320_SPI_WRITE (0x00) -#define ILI9320_SPI_DATA (0x02) -#define ILI9320_SPI_INDEX (0x00) - -/* platform data to pass configuration from lcd */ - -enum ili9320_suspend { - ILI9320_SUSPEND_OFF, - ILI9320_SUSPEND_DEEP, -}; - -struct ili9320_platdata { - unsigned short hsize; - unsigned short vsize; - - enum ili9320_suspend suspend; - - /* set the reset line, 0 = reset asserted, 1 = normal */ - void (*reset)(unsigned int val); - - unsigned short entry_mode; - unsigned short display2; - unsigned short display3; - unsigned short display4; - unsigned short rgb_if1; - unsigned short rgb_if2; - unsigned short interface2; - unsigned short interface3; - unsigned short interface4; - unsigned short interface5; - unsigned short interface6; -}; - diff --git a/ANDROID_3.4.5/include/video/kyro.h b/ANDROID_3.4.5/include/video/kyro.h deleted file mode 100644 index c563968e..00000000 --- a/ANDROID_3.4.5/include/video/kyro.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - * linux/drivers/video/kyro/kryo.h - * - * Copyright (C) 2002 STMicroelectronics - * Copyright (C) 2004 Paul Mundt - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -#ifndef _KYRO_H -#define _KYRO_H - -struct kyrofb_info { - void __iomem *regbase; - - u32 palette[16]; - u32 HTot; /* Hor Total Time */ - u32 HFP; /* Hor Front Porch */ - u32 HST; /* Hor Sync Time */ - u32 HBP; /* Hor Back Porch */ - s32 HSP; /* Hor Sync Polarity */ - u32 VTot; /* Ver Total Time */ - u32 VFP; /* Ver Front Porch */ - u32 VST; /* Ver Sync Time */ - u32 VBP; /* Ver Back Porch */ - s32 VSP; /* Ver Sync Polarity */ - u32 XRES; /* X Resolution */ - u32 YRES; /* Y Resolution */ - u32 VFREQ; /* Ver Frequency */ - u32 PIXCLK; /* Pixel Clock */ - u32 HCLK; /* Hor Clock */ - - /* Useful to hold depth here for Linux */ - u8 PIXDEPTH; - -#ifdef CONFIG_MTRR - int mtrr_handle; -#endif -}; - -extern int kyro_dev_init(void); -extern void kyro_dev_reset(void); - -extern unsigned char *kyro_dev_physical_fb_ptr(void); -extern unsigned char *kyro_dev_virtual_fb_ptr(void); -extern void *kyro_dev_physical_regs_ptr(void); -extern void *kyro_dev_virtual_regs_ptr(void); -extern unsigned int kyro_dev_fb_size(void); -extern unsigned int kyro_dev_regs_size(void); - -extern u32 kyro_dev_overlay_offset(void); - -/* - * benedict.gaster@superh.com - * Added the follow IOCTLS for the creation of overlay services... - */ -#define KYRO_IOC_MAGIC 'k' - -#define KYRO_IOCTL_OVERLAY_CREATE _IO(KYRO_IOC_MAGIC, 0) -#define KYRO_IOCTL_OVERLAY_VIEWPORT_SET _IO(KYRO_IOC_MAGIC, 1) -#define KYRO_IOCTL_SET_VIDEO_MODE _IO(KYRO_IOC_MAGIC, 2) -#define KYRO_IOCTL_UVSTRIDE _IO(KYRO_IOC_MAGIC, 3) -#define KYRO_IOCTL_OVERLAY_OFFSET _IO(KYRO_IOC_MAGIC, 4) -#define KYRO_IOCTL_STRIDE _IO(KYRO_IOC_MAGIC, 5) - -/* - * The follow 3 structures are used to pass data from user space into the kernel - * for the creation of overlay surfaces and setting the video mode. - */ -typedef struct _OVERLAY_CREATE { - u32 ulWidth; - u32 ulHeight; - int bLinear; -} overlay_create; - -typedef struct _OVERLAY_VIEWPORT_SET { - u32 xOrgin; - u32 yOrgin; - u32 xSize; - u32 ySize; -} overlay_viewport_set; - -typedef struct _SET_VIDEO_MODE { - u32 ulWidth; - u32 ulHeight; - u32 ulScan; - u8 displayDepth; - int bLinear; -} set_video_mode; - -#endif /* _KYRO_H */ diff --git a/ANDROID_3.4.5/include/video/mach64.h b/ANDROID_3.4.5/include/video/mach64.h deleted file mode 100644 index 89e91c0c..00000000 --- a/ANDROID_3.4.5/include/video/mach64.h +++ /dev/null @@ -1,1378 +0,0 @@ -/* - * ATI Mach64 Register Definitions - * - * Copyright (C) 1997 Michael AK Tesch - * written with much help from Jon Howell - * - * Updated for 3D RAGE PRO and 3D RAGE Mobility by Geert Uytterhoeven - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -/* - * most of the rest of this file comes from ATI sample code - */ -#ifndef REGMACH64_H -#define REGMACH64_H - -/* NON-GUI MEMORY MAPPED Registers - expressed in BYTE offsets */ - -/* Accelerator CRTC */ -#define CRTC_H_TOTAL_DISP 0x0000 /* Dword offset 0_00 */ -#define CRTC2_H_TOTAL_DISP 0x0000 /* Dword offset 0_00 */ -#define CRTC_H_SYNC_STRT_WID 0x0004 /* Dword offset 0_01 */ -#define CRTC2_H_SYNC_STRT_WID 0x0004 /* Dword offset 0_01 */ -#define CRTC_H_SYNC_STRT 0x0004 -#define CRTC2_H_SYNC_STRT 0x0004 -#define CRTC_H_SYNC_DLY 0x0005 -#define CRTC2_H_SYNC_DLY 0x0005 -#define CRTC_H_SYNC_WID 0x0006 -#define CRTC2_H_SYNC_WID 0x0006 -#define CRTC_V_TOTAL_DISP 0x0008 /* Dword offset 0_02 */ -#define CRTC2_V_TOTAL_DISP 0x0008 /* Dword offset 0_02 */ -#define CRTC_V_TOTAL 0x0008 -#define CRTC2_V_TOTAL 0x0008 -#define CRTC_V_DISP 0x000A -#define CRTC2_V_DISP 0x000A -#define CRTC_V_SYNC_STRT_WID 0x000C /* Dword offset 0_03 */ -#define CRTC2_V_SYNC_STRT_WID 0x000C /* Dword offset 0_03 */ -#define CRTC_V_SYNC_STRT 0x000C -#define CRTC2_V_SYNC_STRT 0x000C -#define CRTC_V_SYNC_WID 0x000E -#define CRTC2_V_SYNC_WID 0x000E -#define CRTC_VLINE_CRNT_VLINE 0x0010 /* Dword offset 0_04 */ -#define CRTC2_VLINE_CRNT_VLINE 0x0010 /* Dword offset 0_04 */ -#define CRTC_OFF_PITCH 0x0014 /* Dword offset 0_05 */ -#define CRTC_OFFSET 0x0014 -#define CRTC_PITCH 0x0016 -#define CRTC_INT_CNTL 0x0018 /* Dword offset 0_06 */ -#define CRTC_GEN_CNTL 0x001C /* Dword offset 0_07 */ -#define CRTC_PIX_WIDTH 0x001D -#define CRTC_FIFO 0x001E -#define CRTC_EXT_DISP 0x001F - -/* Memory Buffer Control */ -#define DSP_CONFIG 0x0020 /* Dword offset 0_08 */ -#define PM_DSP_CONFIG 0x0020 /* Dword offset 0_08 (Mobility Only) */ -#define DSP_ON_OFF 0x0024 /* Dword offset 0_09 */ -#define PM_DSP_ON_OFF 0x0024 /* Dword offset 0_09 (Mobility Only) */ -#define TIMER_CONFIG 0x0028 /* Dword offset 0_0A */ -#define MEM_BUF_CNTL 0x002C /* Dword offset 0_0B */ -#define MEM_ADDR_CONFIG 0x0034 /* Dword offset 0_0D */ - -/* Accelerator CRTC */ -#define CRT_TRAP 0x0038 /* Dword offset 0_0E */ - -#define I2C_CNTL_0 0x003C /* Dword offset 0_0F */ - -#define DSTN_CONTROL_LG 0x003C /* Dword offset 0_0F (LG) */ - -/* Overscan */ -#define OVR_CLR 0x0040 /* Dword offset 0_10 */ -#define OVR2_CLR 0x0040 /* Dword offset 0_10 */ -#define OVR_WID_LEFT_RIGHT 0x0044 /* Dword offset 0_11 */ -#define OVR2_WID_LEFT_RIGHT 0x0044 /* Dword offset 0_11 */ -#define OVR_WID_TOP_BOTTOM 0x0048 /* Dword offset 0_12 */ -#define OVR2_WID_TOP_BOTTOM 0x0048 /* Dword offset 0_12 */ - -/* Memory Buffer Control */ -#define VGA_DSP_CONFIG 0x004C /* Dword offset 0_13 */ -#define PM_VGA_DSP_CONFIG 0x004C /* Dword offset 0_13 (Mobility Only) */ -#define VGA_DSP_ON_OFF 0x0050 /* Dword offset 0_14 */ -#define PM_VGA_DSP_ON_OFF 0x0050 /* Dword offset 0_14 (Mobility Only) */ -#define DSP2_CONFIG 0x0054 /* Dword offset 0_15 */ -#define PM_DSP2_CONFIG 0x0054 /* Dword offset 0_15 (Mobility Only) */ -#define DSP2_ON_OFF 0x0058 /* Dword offset 0_16 */ -#define PM_DSP2_ON_OFF 0x0058 /* Dword offset 0_16 (Mobility Only) */ - -/* Accelerator CRTC */ -#define CRTC2_OFF_PITCH 0x005C /* Dword offset 0_17 */ - -/* Hardware Cursor */ -#define CUR_CLR0 0x0060 /* Dword offset 0_18 */ -#define CUR2_CLR0 0x0060 /* Dword offset 0_18 */ -#define CUR_CLR1 0x0064 /* Dword offset 0_19 */ -#define CUR2_CLR1 0x0064 /* Dword offset 0_19 */ -#define CUR_OFFSET 0x0068 /* Dword offset 0_1A */ -#define CUR2_OFFSET 0x0068 /* Dword offset 0_1A */ -#define CUR_HORZ_VERT_POSN 0x006C /* Dword offset 0_1B */ -#define CUR2_HORZ_VERT_POSN 0x006C /* Dword offset 0_1B */ -#define CUR_HORZ_VERT_OFF 0x0070 /* Dword offset 0_1C */ -#define CUR2_HORZ_VERT_OFF 0x0070 /* Dword offset 0_1C */ - -#define CNFG_PANEL_LG 0x0074 /* Dword offset 0_1D (LG) */ - -/* General I/O Control */ -#define GP_IO 0x0078 /* Dword offset 0_1E */ - -/* Test and Debug */ -#define HW_DEBUG 0x007C /* Dword offset 0_1F */ - -/* Scratch Pad and Test */ -#define SCRATCH_REG0 0x0080 /* Dword offset 0_20 */ -#define SCRATCH_REG1 0x0084 /* Dword offset 0_21 */ -#define SCRATCH_REG2 0x0088 /* Dword offset 0_22 */ -#define SCRATCH_REG3 0x008C /* Dword offset 0_23 */ - -/* Clock Control */ -#define CLOCK_CNTL 0x0090 /* Dword offset 0_24 */ -/* CLOCK_CNTL register constants CT LAYOUT */ -#define CLOCK_SEL 0x0f -#define CLOCK_SEL_INTERNAL 0x03 -#define CLOCK_SEL_EXTERNAL 0x0c -#define CLOCK_DIV 0x30 -#define CLOCK_DIV1 0x00 -#define CLOCK_DIV2 0x10 -#define CLOCK_DIV4 0x20 -#define CLOCK_STROBE 0x40 -/* ? 0x80 */ -/* CLOCK_CNTL register constants GX LAYOUT */ -#define CLOCK_BIT 0x04 /* For ICS2595 */ -#define CLOCK_PULSE 0x08 /* For ICS2595 */ -/*#define CLOCK_STROBE 0x40 dito as CT */ -#define CLOCK_DATA 0x80 - -/* For internal PLL(CT) start */ -#define CLOCK_CNTL_ADDR CLOCK_CNTL + 1 -#define PLL_WR_EN 0x02 -#define PLL_ADDR 0xfc -#define CLOCK_CNTL_DATA CLOCK_CNTL + 2 -#define PLL_DATA 0xff -/* For internal PLL(CT) end */ - -#define CLOCK_SEL_CNTL 0x0090 /* Dword offset 0_24 */ - -/* Configuration */ -#define CNFG_STAT1 0x0094 /* Dword offset 0_25 */ -#define CNFG_STAT2 0x0098 /* Dword offset 0_26 */ - -/* Bus Control */ -#define BUS_CNTL 0x00A0 /* Dword offset 0_28 */ - -#define LCD_INDEX 0x00A4 /* Dword offset 0_29 */ -#define LCD_DATA 0x00A8 /* Dword offset 0_2A */ - -#define HFB_PITCH_ADDR_LG 0x00A8 /* Dword offset 0_2A (LG) */ - -/* Memory Control */ -#define EXT_MEM_CNTL 0x00AC /* Dword offset 0_2B */ -#define MEM_CNTL 0x00B0 /* Dword offset 0_2C */ -#define MEM_VGA_WP_SEL 0x00B4 /* Dword offset 0_2D */ -#define MEM_VGA_RP_SEL 0x00B8 /* Dword offset 0_2E */ - -#define I2C_CNTL_1 0x00BC /* Dword offset 0_2F */ - -#define LT_GIO_LG 0x00BC /* Dword offset 0_2F (LG) */ - -/* DAC Control */ -#define DAC_REGS 0x00C0 /* Dword offset 0_30 */ -#define DAC_W_INDEX 0x00C0 /* Dword offset 0_30 */ -#define DAC_DATA 0x00C1 /* Dword offset 0_30 */ -#define DAC_MASK 0x00C2 /* Dword offset 0_30 */ -#define DAC_R_INDEX 0x00C3 /* Dword offset 0_30 */ -#define DAC_CNTL 0x00C4 /* Dword offset 0_31 */ - -#define EXT_DAC_REGS 0x00C8 /* Dword offset 0_32 */ - -#define HORZ_STRETCHING_LG 0x00C8 /* Dword offset 0_32 (LG) */ -#define VERT_STRETCHING_LG 0x00CC /* Dword offset 0_33 (LG) */ - -/* Test and Debug */ -#define GEN_TEST_CNTL 0x00D0 /* Dword offset 0_34 */ - -/* Custom Macros */ -#define CUSTOM_MACRO_CNTL 0x00D4 /* Dword offset 0_35 */ - -#define LCD_GEN_CNTL_LG 0x00D4 /* Dword offset 0_35 (LG) */ -#define POWER_MANAGEMENT_LG 0x00D8 /* Dword offset 0_36 (LG) */ - -/* Configuration */ -#define CNFG_CNTL 0x00DC /* Dword offset 0_37 (CT, ET, VT) */ -#define CNFG_CHIP_ID 0x00E0 /* Dword offset 0_38 */ -#define CNFG_STAT0 0x00E4 /* Dword offset 0_39 */ - -/* Test and Debug */ -#define CRC_SIG 0x00E8 /* Dword offset 0_3A */ -#define CRC2_SIG 0x00E8 /* Dword offset 0_3A */ - - -/* GUI MEMORY MAPPED Registers */ - -/* Draw Engine Destination Trajectory */ -#define DST_OFF_PITCH 0x0100 /* Dword offset 0_40 */ -#define DST_X 0x0104 /* Dword offset 0_41 */ -#define DST_Y 0x0108 /* Dword offset 0_42 */ -#define DST_Y_X 0x010C /* Dword offset 0_43 */ -#define DST_WIDTH 0x0110 /* Dword offset 0_44 */ -#define DST_HEIGHT 0x0114 /* Dword offset 0_45 */ -#define DST_HEIGHT_WIDTH 0x0118 /* Dword offset 0_46 */ -#define DST_X_WIDTH 0x011C /* Dword offset 0_47 */ -#define DST_BRES_LNTH 0x0120 /* Dword offset 0_48 */ -#define DST_BRES_ERR 0x0124 /* Dword offset 0_49 */ -#define DST_BRES_INC 0x0128 /* Dword offset 0_4A */ -#define DST_BRES_DEC 0x012C /* Dword offset 0_4B */ -#define DST_CNTL 0x0130 /* Dword offset 0_4C */ -#define DST_Y_X__ALIAS__ 0x0134 /* Dword offset 0_4D */ -#define TRAIL_BRES_ERR 0x0138 /* Dword offset 0_4E */ -#define TRAIL_BRES_INC 0x013C /* Dword offset 0_4F */ -#define TRAIL_BRES_DEC 0x0140 /* Dword offset 0_50 */ -#define LEAD_BRES_LNTH 0x0144 /* Dword offset 0_51 */ -#define Z_OFF_PITCH 0x0148 /* Dword offset 0_52 */ -#define Z_CNTL 0x014C /* Dword offset 0_53 */ -#define ALPHA_TST_CNTL 0x0150 /* Dword offset 0_54 */ -#define SECONDARY_STW_EXP 0x0158 /* Dword offset 0_56 */ -#define SECONDARY_S_X_INC 0x015C /* Dword offset 0_57 */ -#define SECONDARY_S_Y_INC 0x0160 /* Dword offset 0_58 */ -#define SECONDARY_S_START 0x0164 /* Dword offset 0_59 */ -#define SECONDARY_W_X_INC 0x0168 /* Dword offset 0_5A */ -#define SECONDARY_W_Y_INC 0x016C /* Dword offset 0_5B */ -#define SECONDARY_W_START 0x0170 /* Dword offset 0_5C */ -#define SECONDARY_T_X_INC 0x0174 /* Dword offset 0_5D */ -#define SECONDARY_T_Y_INC 0x0178 /* Dword offset 0_5E */ -#define SECONDARY_T_START 0x017C /* Dword offset 0_5F */ - -/* Draw Engine Source Trajectory */ -#define SRC_OFF_PITCH 0x0180 /* Dword offset 0_60 */ -#define SRC_X 0x0184 /* Dword offset 0_61 */ -#define SRC_Y 0x0188 /* Dword offset 0_62 */ -#define SRC_Y_X 0x018C /* Dword offset 0_63 */ -#define SRC_WIDTH1 0x0190 /* Dword offset 0_64 */ -#define SRC_HEIGHT1 0x0194 /* Dword offset 0_65 */ -#define SRC_HEIGHT1_WIDTH1 0x0198 /* Dword offset 0_66 */ -#define SRC_X_START 0x019C /* Dword offset 0_67 */ -#define SRC_Y_START 0x01A0 /* Dword offset 0_68 */ -#define SRC_Y_X_START 0x01A4 /* Dword offset 0_69 */ -#define SRC_WIDTH2 0x01A8 /* Dword offset 0_6A */ -#define SRC_HEIGHT2 0x01AC /* Dword offset 0_6B */ -#define SRC_HEIGHT2_WIDTH2 0x01B0 /* Dword offset 0_6C */ -#define SRC_CNTL 0x01B4 /* Dword offset 0_6D */ - -#define SCALE_OFF 0x01C0 /* Dword offset 0_70 */ -#define SECONDARY_SCALE_OFF 0x01C4 /* Dword offset 0_71 */ - -#define TEX_0_OFF 0x01C0 /* Dword offset 0_70 */ -#define TEX_1_OFF 0x01C4 /* Dword offset 0_71 */ -#define TEX_2_OFF 0x01C8 /* Dword offset 0_72 */ -#define TEX_3_OFF 0x01CC /* Dword offset 0_73 */ -#define TEX_4_OFF 0x01D0 /* Dword offset 0_74 */ -#define TEX_5_OFF 0x01D4 /* Dword offset 0_75 */ -#define TEX_6_OFF 0x01D8 /* Dword offset 0_76 */ -#define TEX_7_OFF 0x01DC /* Dword offset 0_77 */ - -#define SCALE_WIDTH 0x01DC /* Dword offset 0_77 */ -#define SCALE_HEIGHT 0x01E0 /* Dword offset 0_78 */ - -#define TEX_8_OFF 0x01E0 /* Dword offset 0_78 */ -#define TEX_9_OFF 0x01E4 /* Dword offset 0_79 */ -#define TEX_10_OFF 0x01E8 /* Dword offset 0_7A */ -#define S_Y_INC 0x01EC /* Dword offset 0_7B */ - -#define SCALE_PITCH 0x01EC /* Dword offset 0_7B */ -#define SCALE_X_INC 0x01F0 /* Dword offset 0_7C */ - -#define RED_X_INC 0x01F0 /* Dword offset 0_7C */ -#define GREEN_X_INC 0x01F4 /* Dword offset 0_7D */ - -#define SCALE_Y_INC 0x01F4 /* Dword offset 0_7D */ -#define SCALE_VACC 0x01F8 /* Dword offset 0_7E */ -#define SCALE_3D_CNTL 0x01FC /* Dword offset 0_7F */ - -/* Host Data */ -#define HOST_DATA0 0x0200 /* Dword offset 0_80 */ -#define HOST_DATA1 0x0204 /* Dword offset 0_81 */ -#define HOST_DATA2 0x0208 /* Dword offset 0_82 */ -#define HOST_DATA3 0x020C /* Dword offset 0_83 */ -#define HOST_DATA4 0x0210 /* Dword offset 0_84 */ -#define HOST_DATA5 0x0214 /* Dword offset 0_85 */ -#define HOST_DATA6 0x0218 /* Dword offset 0_86 */ -#define HOST_DATA7 0x021C /* Dword offset 0_87 */ -#define HOST_DATA8 0x0220 /* Dword offset 0_88 */ -#define HOST_DATA9 0x0224 /* Dword offset 0_89 */ -#define HOST_DATAA 0x0228 /* Dword offset 0_8A */ -#define HOST_DATAB 0x022C /* Dword offset 0_8B */ -#define HOST_DATAC 0x0230 /* Dword offset 0_8C */ -#define HOST_DATAD 0x0234 /* Dword offset 0_8D */ -#define HOST_DATAE 0x0238 /* Dword offset 0_8E */ -#define HOST_DATAF 0x023C /* Dword offset 0_8F */ -#define HOST_CNTL 0x0240 /* Dword offset 0_90 */ - -/* GUI Bus Mastering */ -#define BM_HOSTDATA 0x0244 /* Dword offset 0_91 */ -#define BM_ADDR 0x0248 /* Dword offset 0_92 */ -#define BM_DATA 0x0248 /* Dword offset 0_92 */ -#define BM_GUI_TABLE_CMD 0x024C /* Dword offset 0_93 */ - -/* Pattern */ -#define PAT_REG0 0x0280 /* Dword offset 0_A0 */ -#define PAT_REG1 0x0284 /* Dword offset 0_A1 */ -#define PAT_CNTL 0x0288 /* Dword offset 0_A2 */ - -/* Scissors */ -#define SC_LEFT 0x02A0 /* Dword offset 0_A8 */ -#define SC_RIGHT 0x02A4 /* Dword offset 0_A9 */ -#define SC_LEFT_RIGHT 0x02A8 /* Dword offset 0_AA */ -#define SC_TOP 0x02AC /* Dword offset 0_AB */ -#define SC_BOTTOM 0x02B0 /* Dword offset 0_AC */ -#define SC_TOP_BOTTOM 0x02B4 /* Dword offset 0_AD */ - -/* Data Path */ -#define USR1_DST_OFF_PITCH 0x02B8 /* Dword offset 0_AE */ -#define USR2_DST_OFF_PITCH 0x02BC /* Dword offset 0_AF */ -#define DP_BKGD_CLR 0x02C0 /* Dword offset 0_B0 */ -#define DP_FOG_CLR 0x02C4 /* Dword offset 0_B1 */ -#define DP_FRGD_CLR 0x02C4 /* Dword offset 0_B1 */ -#define DP_WRITE_MASK 0x02C8 /* Dword offset 0_B2 */ -#define DP_CHAIN_MASK 0x02CC /* Dword offset 0_B3 */ -#define DP_PIX_WIDTH 0x02D0 /* Dword offset 0_B4 */ -#define DP_MIX 0x02D4 /* Dword offset 0_B5 */ -#define DP_SRC 0x02D8 /* Dword offset 0_B6 */ -#define DP_FRGD_CLR_MIX 0x02DC /* Dword offset 0_B7 */ -#define DP_FRGD_BKGD_CLR 0x02E0 /* Dword offset 0_B8 */ - -/* Draw Engine Destination Trajectory */ -#define DST_X_Y 0x02E8 /* Dword offset 0_BA */ -#define DST_WIDTH_HEIGHT 0x02EC /* Dword offset 0_BB */ - -/* Data Path */ -#define USR_DST_PICTH 0x02F0 /* Dword offset 0_BC */ -#define DP_SET_GUI_ENGINE2 0x02F8 /* Dword offset 0_BE */ -#define DP_SET_GUI_ENGINE 0x02FC /* Dword offset 0_BF */ - -/* Color Compare */ -#define CLR_CMP_CLR 0x0300 /* Dword offset 0_C0 */ -#define CLR_CMP_MASK 0x0304 /* Dword offset 0_C1 */ -#define CLR_CMP_CNTL 0x0308 /* Dword offset 0_C2 */ - -/* Command FIFO */ -#define FIFO_STAT 0x0310 /* Dword offset 0_C4 */ - -#define CONTEXT_MASK 0x0320 /* Dword offset 0_C8 */ -#define CONTEXT_LOAD_CNTL 0x032C /* Dword offset 0_CB */ - -/* Engine Control */ -#define GUI_TRAJ_CNTL 0x0330 /* Dword offset 0_CC */ - -/* Engine Status/FIFO */ -#define GUI_STAT 0x0338 /* Dword offset 0_CE */ - -#define TEX_PALETTE_INDEX 0x0340 /* Dword offset 0_D0 */ -#define STW_EXP 0x0344 /* Dword offset 0_D1 */ -#define LOG_MAX_INC 0x0348 /* Dword offset 0_D2 */ -#define S_X_INC 0x034C /* Dword offset 0_D3 */ -#define S_Y_INC__ALIAS__ 0x0350 /* Dword offset 0_D4 */ - -#define SCALE_PITCH__ALIAS__ 0x0350 /* Dword offset 0_D4 */ - -#define S_START 0x0354 /* Dword offset 0_D5 */ -#define W_X_INC 0x0358 /* Dword offset 0_D6 */ -#define W_Y_INC 0x035C /* Dword offset 0_D7 */ -#define W_START 0x0360 /* Dword offset 0_D8 */ -#define T_X_INC 0x0364 /* Dword offset 0_D9 */ -#define T_Y_INC 0x0368 /* Dword offset 0_DA */ - -#define SECONDARY_SCALE_PITCH 0x0368 /* Dword offset 0_DA */ - -#define T_START 0x036C /* Dword offset 0_DB */ -#define TEX_SIZE_PITCH 0x0370 /* Dword offset 0_DC */ -#define TEX_CNTL 0x0374 /* Dword offset 0_DD */ -#define SECONDARY_TEX_OFFSET 0x0378 /* Dword offset 0_DE */ -#define TEX_PALETTE 0x037C /* Dword offset 0_DF */ - -#define SCALE_PITCH_BOTH 0x0380 /* Dword offset 0_E0 */ -#define SECONDARY_SCALE_OFF_ACC 0x0384 /* Dword offset 0_E1 */ -#define SCALE_OFF_ACC 0x0388 /* Dword offset 0_E2 */ -#define SCALE_DST_Y_X 0x038C /* Dword offset 0_E3 */ - -/* Draw Engine Destination Trajectory */ -#define COMPOSITE_SHADOW_ID 0x0398 /* Dword offset 0_E6 */ - -#define SECONDARY_SCALE_X_INC 0x039C /* Dword offset 0_E7 */ - -#define SPECULAR_RED_X_INC 0x039C /* Dword offset 0_E7 */ -#define SPECULAR_RED_Y_INC 0x03A0 /* Dword offset 0_E8 */ -#define SPECULAR_RED_START 0x03A4 /* Dword offset 0_E9 */ - -#define SECONDARY_SCALE_HACC 0x03A4 /* Dword offset 0_E9 */ - -#define SPECULAR_GREEN_X_INC 0x03A8 /* Dword offset 0_EA */ -#define SPECULAR_GREEN_Y_INC 0x03AC /* Dword offset 0_EB */ -#define SPECULAR_GREEN_START 0x03B0 /* Dword offset 0_EC */ -#define SPECULAR_BLUE_X_INC 0x03B4 /* Dword offset 0_ED */ -#define SPECULAR_BLUE_Y_INC 0x03B8 /* Dword offset 0_EE */ -#define SPECULAR_BLUE_START 0x03BC /* Dword offset 0_EF */ - -#define SCALE_X_INC__ALIAS__ 0x03C0 /* Dword offset 0_F0 */ - -#define RED_X_INC__ALIAS__ 0x03C0 /* Dword offset 0_F0 */ -#define RED_Y_INC 0x03C4 /* Dword offset 0_F1 */ -#define RED_START 0x03C8 /* Dword offset 0_F2 */ - -#define SCALE_HACC 0x03C8 /* Dword offset 0_F2 */ -#define SCALE_Y_INC__ALIAS__ 0x03CC /* Dword offset 0_F3 */ - -#define GREEN_X_INC__ALIAS__ 0x03CC /* Dword offset 0_F3 */ -#define GREEN_Y_INC 0x03D0 /* Dword offset 0_F4 */ - -#define SECONDARY_SCALE_Y_INC 0x03D0 /* Dword offset 0_F4 */ -#define SECONDARY_SCALE_VACC 0x03D4 /* Dword offset 0_F5 */ - -#define GREEN_START 0x03D4 /* Dword offset 0_F5 */ -#define BLUE_X_INC 0x03D8 /* Dword offset 0_F6 */ -#define BLUE_Y_INC 0x03DC /* Dword offset 0_F7 */ -#define BLUE_START 0x03E0 /* Dword offset 0_F8 */ -#define Z_X_INC 0x03E4 /* Dword offset 0_F9 */ -#define Z_Y_INC 0x03E8 /* Dword offset 0_FA */ -#define Z_START 0x03EC /* Dword offset 0_FB */ -#define ALPHA_X_INC 0x03F0 /* Dword offset 0_FC */ -#define FOG_X_INC 0x03F0 /* Dword offset 0_FC */ -#define ALPHA_Y_INC 0x03F4 /* Dword offset 0_FD */ -#define FOG_Y_INC 0x03F4 /* Dword offset 0_FD */ -#define ALPHA_START 0x03F8 /* Dword offset 0_FE */ -#define FOG_START 0x03F8 /* Dword offset 0_FE */ - -#define OVERLAY_Y_X_START 0x0400 /* Dword offset 1_00 */ -#define OVERLAY_Y_X_END 0x0404 /* Dword offset 1_01 */ -#define OVERLAY_VIDEO_KEY_CLR 0x0408 /* Dword offset 1_02 */ -#define OVERLAY_VIDEO_KEY_MSK 0x040C /* Dword offset 1_03 */ -#define OVERLAY_GRAPHICS_KEY_CLR 0x0410 /* Dword offset 1_04 */ -#define OVERLAY_GRAPHICS_KEY_MSK 0x0414 /* Dword offset 1_05 */ -#define OVERLAY_KEY_CNTL 0x0418 /* Dword offset 1_06 */ - -#define OVERLAY_SCALE_INC 0x0420 /* Dword offset 1_08 */ -#define OVERLAY_SCALE_CNTL 0x0424 /* Dword offset 1_09 */ -#define SCALER_HEIGHT_WIDTH 0x0428 /* Dword offset 1_0A */ -#define SCALER_TEST 0x042C /* Dword offset 1_0B */ -#define SCALER_BUF0_OFFSET 0x0434 /* Dword offset 1_0D */ -#define SCALER_BUF1_OFFSET 0x0438 /* Dword offset 1_0E */ -#define SCALE_BUF_PITCH 0x043C /* Dword offset 1_0F */ - -#define CAPTURE_START_END 0x0440 /* Dword offset 1_10 */ -#define CAPTURE_X_WIDTH 0x0444 /* Dword offset 1_11 */ -#define VIDEO_FORMAT 0x0448 /* Dword offset 1_12 */ -#define VBI_START_END 0x044C /* Dword offset 1_13 */ -#define CAPTURE_CONFIG 0x0450 /* Dword offset 1_14 */ -#define TRIG_CNTL 0x0454 /* Dword offset 1_15 */ - -#define OVERLAY_EXCLUSIVE_HORZ 0x0458 /* Dword offset 1_16 */ -#define OVERLAY_EXCLUSIVE_VERT 0x045C /* Dword offset 1_17 */ - -#define VAL_WIDTH 0x0460 /* Dword offset 1_18 */ -#define CAPTURE_DEBUG 0x0464 /* Dword offset 1_19 */ -#define VIDEO_SYNC_TEST 0x0468 /* Dword offset 1_1A */ - -/* GenLocking */ -#define SNAPSHOT_VH_COUNTS 0x0470 /* Dword offset 1_1C */ -#define SNAPSHOT_F_COUNT 0x0474 /* Dword offset 1_1D */ -#define N_VIF_COUNT 0x0478 /* Dword offset 1_1E */ -#define SNAPSHOT_VIF_COUNT 0x047C /* Dword offset 1_1F */ - -#define CAPTURE_BUF0_OFFSET 0x0480 /* Dword offset 1_20 */ -#define CAPTURE_BUF1_OFFSET 0x0484 /* Dword offset 1_21 */ -#define CAPTURE_BUF_PITCH 0x0488 /* Dword offset 1_22 */ - -/* GenLocking */ -#define SNAPSHOT2_VH_COUNTS 0x04B0 /* Dword offset 1_2C */ -#define SNAPSHOT2_F_COUNT 0x04B4 /* Dword offset 1_2D */ -#define N_VIF2_COUNT 0x04B8 /* Dword offset 1_2E */ -#define SNAPSHOT2_VIF_COUNT 0x04BC /* Dword offset 1_2F */ - -#define MPP_CONFIG 0x04C0 /* Dword offset 1_30 */ -#define MPP_STROBE_SEQ 0x04C4 /* Dword offset 1_31 */ -#define MPP_ADDR 0x04C8 /* Dword offset 1_32 */ -#define MPP_DATA 0x04CC /* Dword offset 1_33 */ -#define TVO_CNTL 0x0500 /* Dword offset 1_40 */ - -/* Test and Debug */ -#define CRT_HORZ_VERT_LOAD 0x0544 /* Dword offset 1_51 */ - -/* AGP */ -#define AGP_BASE 0x0548 /* Dword offset 1_52 */ -#define AGP_CNTL 0x054C /* Dword offset 1_53 */ - -#define SCALER_COLOUR_CNTL 0x0550 /* Dword offset 1_54 */ -#define SCALER_H_COEFF0 0x0554 /* Dword offset 1_55 */ -#define SCALER_H_COEFF1 0x0558 /* Dword offset 1_56 */ -#define SCALER_H_COEFF2 0x055C /* Dword offset 1_57 */ -#define SCALER_H_COEFF3 0x0560 /* Dword offset 1_58 */ -#define SCALER_H_COEFF4 0x0564 /* Dword offset 1_59 */ - -/* Command FIFO */ -#define GUI_CMDFIFO_DEBUG 0x0570 /* Dword offset 1_5C */ -#define GUI_CMDFIFO_DATA 0x0574 /* Dword offset 1_5D */ -#define GUI_CNTL 0x0578 /* Dword offset 1_5E */ - -/* Bus Mastering */ -#define BM_FRAME_BUF_OFFSET 0x0580 /* Dword offset 1_60 */ -#define BM_SYSTEM_MEM_ADDR 0x0584 /* Dword offset 1_61 */ -#define BM_COMMAND 0x0588 /* Dword offset 1_62 */ -#define BM_STATUS 0x058C /* Dword offset 1_63 */ -#define BM_GUI_TABLE 0x05B8 /* Dword offset 1_6E */ -#define BM_SYSTEM_TABLE 0x05BC /* Dword offset 1_6F */ - -#define SCALER_BUF0_OFFSET_U 0x05D4 /* Dword offset 1_75 */ -#define SCALER_BUF0_OFFSET_V 0x05D8 /* Dword offset 1_76 */ -#define SCALER_BUF1_OFFSET_U 0x05DC /* Dword offset 1_77 */ -#define SCALER_BUF1_OFFSET_V 0x05E0 /* Dword offset 1_78 */ - -/* Setup Engine */ -#define VERTEX_1_S 0x0640 /* Dword offset 1_90 */ -#define VERTEX_1_T 0x0644 /* Dword offset 1_91 */ -#define VERTEX_1_W 0x0648 /* Dword offset 1_92 */ -#define VERTEX_1_SPEC_ARGB 0x064C /* Dword offset 1_93 */ -#define VERTEX_1_Z 0x0650 /* Dword offset 1_94 */ -#define VERTEX_1_ARGB 0x0654 /* Dword offset 1_95 */ -#define VERTEX_1_X_Y 0x0658 /* Dword offset 1_96 */ -#define ONE_OVER_AREA 0x065C /* Dword offset 1_97 */ -#define VERTEX_2_S 0x0660 /* Dword offset 1_98 */ -#define VERTEX_2_T 0x0664 /* Dword offset 1_99 */ -#define VERTEX_2_W 0x0668 /* Dword offset 1_9A */ -#define VERTEX_2_SPEC_ARGB 0x066C /* Dword offset 1_9B */ -#define VERTEX_2_Z 0x0670 /* Dword offset 1_9C */ -#define VERTEX_2_ARGB 0x0674 /* Dword offset 1_9D */ -#define VERTEX_2_X_Y 0x0678 /* Dword offset 1_9E */ -#define ONE_OVER_AREA 0x065C /* Dword offset 1_9F */ -#define VERTEX_3_S 0x0680 /* Dword offset 1_A0 */ -#define VERTEX_3_T 0x0684 /* Dword offset 1_A1 */ -#define VERTEX_3_W 0x0688 /* Dword offset 1_A2 */ -#define VERTEX_3_SPEC_ARGB 0x068C /* Dword offset 1_A3 */ -#define VERTEX_3_Z 0x0690 /* Dword offset 1_A4 */ -#define VERTEX_3_ARGB 0x0694 /* Dword offset 1_A5 */ -#define VERTEX_3_X_Y 0x0698 /* Dword offset 1_A6 */ -#define ONE_OVER_AREA 0x065C /* Dword offset 1_A7 */ -#define VERTEX_1_S 0x0640 /* Dword offset 1_AB */ -#define VERTEX_1_T 0x0644 /* Dword offset 1_AC */ -#define VERTEX_1_W 0x0648 /* Dword offset 1_AD */ -#define VERTEX_2_S 0x0660 /* Dword offset 1_AE */ -#define VERTEX_2_T 0x0664 /* Dword offset 1_AF */ -#define VERTEX_2_W 0x0668 /* Dword offset 1_B0 */ -#define VERTEX_3_SECONDARY_S 0x06C0 /* Dword offset 1_B0 */ -#define VERTEX_3_S 0x0680 /* Dword offset 1_B1 */ -#define VERTEX_3_SECONDARY_T 0x06C4 /* Dword offset 1_B1 */ -#define VERTEX_3_T 0x0684 /* Dword offset 1_B2 */ -#define VERTEX_3_SECONDARY_W 0x06C8 /* Dword offset 1_B2 */ -#define VERTEX_3_W 0x0688 /* Dword offset 1_B3 */ -#define VERTEX_1_SPEC_ARGB 0x064C /* Dword offset 1_B4 */ -#define VERTEX_2_SPEC_ARGB 0x066C /* Dword offset 1_B5 */ -#define VERTEX_3_SPEC_ARGB 0x068C /* Dword offset 1_B6 */ -#define VERTEX_1_Z 0x0650 /* Dword offset 1_B7 */ -#define VERTEX_2_Z 0x0670 /* Dword offset 1_B8 */ -#define VERTEX_3_Z 0x0690 /* Dword offset 1_B9 */ -#define VERTEX_1_ARGB 0x0654 /* Dword offset 1_BA */ -#define VERTEX_2_ARGB 0x0674 /* Dword offset 1_BB */ -#define VERTEX_3_ARGB 0x0694 /* Dword offset 1_BC */ -#define VERTEX_1_X_Y 0x0658 /* Dword offset 1_BD */ -#define VERTEX_2_X_Y 0x0678 /* Dword offset 1_BE */ -#define VERTEX_3_X_Y 0x0698 /* Dword offset 1_BF */ -#define ONE_OVER_AREA_UC 0x0700 /* Dword offset 1_C0 */ -#define SETUP_CNTL 0x0704 /* Dword offset 1_C1 */ -#define VERTEX_1_SECONDARY_S 0x0728 /* Dword offset 1_CA */ -#define VERTEX_1_SECONDARY_T 0x072C /* Dword offset 1_CB */ -#define VERTEX_1_SECONDARY_W 0x0730 /* Dword offset 1_CC */ -#define VERTEX_2_SECONDARY_S 0x0734 /* Dword offset 1_CD */ -#define VERTEX_2_SECONDARY_T 0x0738 /* Dword offset 1_CE */ -#define VERTEX_2_SECONDARY_W 0x073C /* Dword offset 1_CF */ - - -#define GTC_3D_RESET_DELAY 3 /* 3D engine reset delay in ms */ - -/* CRTC control values (mostly CRTC_GEN_CNTL) */ - -#define CRTC_H_SYNC_NEG 0x00200000 -#define CRTC_V_SYNC_NEG 0x00200000 - -#define CRTC_DBL_SCAN_EN 0x00000001 -#define CRTC_INTERLACE_EN 0x00000002 -#define CRTC_HSYNC_DIS 0x00000004 -#define CRTC_VSYNC_DIS 0x00000008 -#define CRTC_CSYNC_EN 0x00000010 -#define CRTC_PIX_BY_2_EN 0x00000020 /* unused on RAGE */ -#define CRTC_DISPLAY_DIS 0x00000040 -#define CRTC_VGA_XOVERSCAN 0x00000080 - -#define CRTC_PIX_WIDTH_MASK 0x00000700 -#define CRTC_PIX_WIDTH_4BPP 0x00000100 -#define CRTC_PIX_WIDTH_8BPP 0x00000200 -#define CRTC_PIX_WIDTH_15BPP 0x00000300 -#define CRTC_PIX_WIDTH_16BPP 0x00000400 -#define CRTC_PIX_WIDTH_24BPP 0x00000500 -#define CRTC_PIX_WIDTH_32BPP 0x00000600 - -#define CRTC_BYTE_PIX_ORDER 0x00000800 -#define CRTC_PIX_ORDER_MSN_LSN 0x00000000 -#define CRTC_PIX_ORDER_LSN_MSN 0x00000800 - -#define CRTC_VSYNC_INT_EN 0x00001000ul /* XC/XL */ -#define CRTC_VSYNC_INT 0x00002000ul /* XC/XL */ -#define CRTC_FIFO_OVERFILL 0x0000c000ul /* VT/GT */ -#define CRTC2_VSYNC_INT_EN 0x00004000ul /* XC/XL */ -#define CRTC2_VSYNC_INT 0x00008000ul /* XC/XL */ - -#define CRTC_FIFO_LWM 0x000f0000 -#define CRTC_HVSYNC_IO_DRIVE 0x00010000 /* XC/XL */ -#define CRTC2_PIX_WIDTH 0x000e0000 /* LTPro */ - -#define CRTC_VGA_128KAP_PAGING 0x00100000 -#define CRTC_VFC_SYNC_TRISTATE 0x00200000 /* VTB/GTB/LT */ -#define CRTC2_EN 0x00200000 /* LTPro */ -#define CRTC_LOCK_REGS 0x00400000 -#define CRTC_SYNC_TRISTATE 0x00800000 - -#define CRTC_EXT_DISP_EN 0x01000000 -#define CRTC_EN 0x02000000 -#define CRTC_DISP_REQ_EN 0x04000000 -#define CRTC_VGA_LINEAR 0x08000000 -#define CRTC_VSYNC_FALL_EDGE 0x10000000 -#define CRTC_VGA_TEXT_132 0x20000000 -#define CRTC_CNT_EN 0x40000000 -#define CRTC_CUR_B_TEST 0x80000000 - -#define CRTC_CRNT_VLINE 0x07f00000 - -#define CRTC_PRESERVED_MASK 0x0001f000 - -#define CRTC_VBLANK 0x00000001 -#define CRTC_VBLANK_INT_EN 0x00000002 -#define CRTC_VBLANK_INT 0x00000004 -#define CRTC_VBLANK_INT_AK CRTC_VBLANK_INT -#define CRTC_VLINE_INT_EN 0x00000008 -#define CRTC_VLINE_INT 0x00000010 -#define CRTC_VLINE_INT_AK CRTC_VLINE_INT -#define CRTC_VLINE_SYNC 0x00000020 -#define CRTC_FRAME 0x00000040 -#define SNAPSHOT_INT_EN 0x00000080 -#define SNAPSHOT_INT 0x00000100 -#define SNAPSHOT_INT_AK SNAPSHOT_INT -#define I2C_INT_EN 0x00000200 -#define I2C_INT 0x00000400 -#define I2C_INT_AK I2C_INT -#define CRTC2_VBLANK 0x00000800 -#define CRTC2_VBLANK_INT_EN 0x00001000 -#define CRTC2_VBLANK_INT 0x00002000 -#define CRTC2_VBLANK_INT_AK CRTC2_VBLANK_INT -#define CRTC2_VLINE_INT_EN 0x00004000 -#define CRTC2_VLINE_INT 0x00008000 -#define CRTC2_VLINE_INT_AK CRTC2_VLINE_INT -#define CAPBUF0_INT_EN 0x00010000 -#define CAPBUF0_INT 0x00020000 -#define CAPBUF0_INT_AK CAPBUF0_INT -#define CAPBUF1_INT_EN 0x00040000 -#define CAPBUF1_INT 0x00080000 -#define CAPBUF1_INT_AK CAPBUF1_INT -#define OVERLAY_EOF_INT_EN 0x00100000 -#define OVERLAY_EOF_INT 0x00200000 -#define OVERLAY_EOF_INT_AK OVERLAY_EOF_INT -#define ONESHOT_CAP_INT_EN 0x00400000 -#define ONESHOT_CAP_INT 0x00800000 -#define ONESHOT_CAP_INT_AK ONESHOT_CAP_INT -#define BUSMASTER_EOL_INT_EN 0x01000000 -#define BUSMASTER_EOL_INT 0x02000000 -#define BUSMASTER_EOL_INT_AK BUSMASTER_EOL_INT -#define GP_INT_EN 0x04000000 -#define GP_INT 0x08000000 -#define GP_INT_AK GP_INT -#define CRTC2_VLINE_SYNC 0x10000000 -#define SNAPSHOT2_INT_EN 0x20000000 -#define SNAPSHOT2_INT 0x40000000 -#define SNAPSHOT2_INT_AK SNAPSHOT2_INT -#define VBLANK_BIT2_INT 0x80000000 -#define VBLANK_BIT2_INT_AK VBLANK_BIT2_INT - -#define CRTC_INT_EN_MASK (CRTC_VBLANK_INT_EN | \ - CRTC_VLINE_INT_EN | \ - SNAPSHOT_INT_EN | \ - I2C_INT_EN | \ - CRTC2_VBLANK_INT_EN | \ - CRTC2_VLINE_INT_EN | \ - CAPBUF0_INT_EN | \ - CAPBUF1_INT_EN | \ - OVERLAY_EOF_INT_EN | \ - ONESHOT_CAP_INT_EN | \ - BUSMASTER_EOL_INT_EN | \ - GP_INT_EN | \ - SNAPSHOT2_INT_EN) - -/* DAC control values */ - -#define DAC_EXT_SEL_RS2 0x01 -#define DAC_EXT_SEL_RS3 0x02 -#define DAC_8BIT_EN 0x00000100 -#define DAC_PIX_DLY_MASK 0x00000600 -#define DAC_PIX_DLY_0NS 0x00000000 -#define DAC_PIX_DLY_2NS 0x00000200 -#define DAC_PIX_DLY_4NS 0x00000400 -#define DAC_BLANK_ADJ_MASK 0x00001800 -#define DAC_BLANK_ADJ_0 0x00000000 -#define DAC_BLANK_ADJ_1 0x00000800 -#define DAC_BLANK_ADJ_2 0x00001000 - -/* DAC control values (my source XL/XC Register reference) */ -#define DAC_OUTPUT_MASK 0x00000001 /* 0 - PAL, 1 - NTSC */ -#define DAC_MISTERY_BIT 0x00000002 /* PS2 ? RS343 ?, EXTRA_BRIGHT for GT */ -#define DAC_BLANKING 0x00000004 -#define DAC_CMP_DISABLE 0x00000008 -#define DAC1_CLK_SEL 0x00000010 -#define PALETTE_ACCESS_CNTL 0x00000020 -#define PALETTE2_SNOOP_EN 0x00000040 -#define DAC_CMP_OUTPUT 0x00000080 /* read only */ -/* #define DAC_8BIT_EN is ok */ -#define CRT_SENSE 0x00000800 /* read only */ -#define CRT_DETECTION_ON 0x00001000 -#define DAC_VGA_ADR_EN 0x00002000 -#define DAC_FEA_CON_EN 0x00004000 -#define DAC_PDWN 0x00008000 -#define DAC_TYPE_MASK 0x00070000 /* read only */ - - - -/* Mix control values */ - -#define MIX_NOT_DST 0x0000 -#define MIX_0 0x0001 -#define MIX_1 0x0002 -#define MIX_DST 0x0003 -#define MIX_NOT_SRC 0x0004 -#define MIX_XOR 0x0005 -#define MIX_XNOR 0x0006 -#define MIX_SRC 0x0007 -#define MIX_NAND 0x0008 -#define MIX_NOT_SRC_OR_DST 0x0009 -#define MIX_SRC_OR_NOT_DST 0x000a -#define MIX_OR 0x000b -#define MIX_AND 0x000c -#define MIX_SRC_AND_NOT_DST 0x000d -#define MIX_NOT_SRC_AND_DST 0x000e -#define MIX_NOR 0x000f - -/* Maximum engine dimensions */ -#define ENGINE_MIN_X 0 -#define ENGINE_MIN_Y 0 -#define ENGINE_MAX_X 4095 -#define ENGINE_MAX_Y 16383 - -/* Mach64 engine bit constants - these are typically ORed together */ - -/* BUS_CNTL register constants */ -#define BUS_APER_REG_DIS 0x00000010 -#define BUS_FIFO_ERR_ACK 0x00200000 -#define BUS_HOST_ERR_ACK 0x00800000 - -/* GEN_TEST_CNTL register constants */ -#define GEN_OVR_OUTPUT_EN 0x20 -#define HWCURSOR_ENABLE 0x80 -#define GUI_ENGINE_ENABLE 0x100 -#define BLOCK_WRITE_ENABLE 0x200 - -/* DSP_CONFIG register constants */ -#define DSP_XCLKS_PER_QW 0x00003fff -#define DSP_LOOP_LATENCY 0x000f0000 -#define DSP_PRECISION 0x00700000 - -/* DSP_ON_OFF register constants */ -#define DSP_OFF 0x000007ff -#define DSP_ON 0x07ff0000 -#define VGA_DSP_OFF DSP_OFF -#define VGA_DSP_ON DSP_ON -#define VGA_DSP_XCLKS_PER_QW DSP_XCLKS_PER_QW - -/* PLL register indices and fields */ -#define MPLL_CNTL 0x00 -#define PLL_PC_GAIN 0x07 -#define PLL_VC_GAIN 0x18 -#define PLL_DUTY_CYC 0xE0 -#define VPLL_CNTL 0x01 -#define PLL_REF_DIV 0x02 -#define PLL_GEN_CNTL 0x03 -#define PLL_OVERRIDE 0x01 /* PLL_SLEEP */ -#define PLL_MCLK_RST 0x02 /* PLL_MRESET */ -#define OSC_EN 0x04 -#define EXT_CLK_EN 0x08 -#define FORCE_DCLK_TRI_STATE 0x08 /* VT4 -> */ -#define MCLK_SRC_SEL 0x70 -#define EXT_CLK_CNTL 0x80 -#define DLL_PWDN 0x80 /* VT4 -> */ -#define MCLK_FB_DIV 0x04 -#define PLL_VCLK_CNTL 0x05 -#define PLL_VCLK_SRC_SEL 0x03 -#define PLL_VCLK_RST 0x04 -#define PLL_VCLK_INVERT 0x08 -#define VCLK_POST_DIV 0x06 -#define VCLK0_POST 0x03 -#define VCLK1_POST 0x0C -#define VCLK2_POST 0x30 -#define VCLK3_POST 0xC0 -#define VCLK0_FB_DIV 0x07 -#define VCLK1_FB_DIV 0x08 -#define VCLK2_FB_DIV 0x09 -#define VCLK3_FB_DIV 0x0A -#define PLL_EXT_CNTL 0x0B -#define PLL_XCLK_MCLK_RATIO 0x03 -#define PLL_XCLK_SRC_SEL 0x07 -#define PLL_MFB_TIMES_4_2B 0x08 -#define PLL_VCLK0_XDIV 0x10 -#define PLL_VCLK1_XDIV 0x20 -#define PLL_VCLK2_XDIV 0x40 -#define PLL_VCLK3_XDIV 0x80 -#define DLL_CNTL 0x0C -#define DLL1_CNTL 0x0C -#define VFC_CNTL 0x0D -#define PLL_TEST_CNTL 0x0E -#define PLL_TEST_COUNT 0x0F -#define LVDS_CNTL0 0x10 -#define LVDS_CNTL1 0x11 -#define AGP1_CNTL 0x12 -#define AGP2_CNTL 0x13 -#define DLL2_CNTL 0x14 -#define SCLK_FB_DIV 0x15 -#define SPLL_CNTL1 0x16 -#define SPLL_CNTL2 0x17 -#define APLL_STRAPS 0x18 -#define EXT_VPLL_CNTL 0x19 -#define EXT_VPLL_EN 0x04 -#define EXT_VPLL_VGA_EN 0x08 -#define EXT_VPLL_INSYNC 0x10 -#define EXT_VPLL_REF_DIV 0x1A -#define EXT_VPLL_FB_DIV 0x1B -#define EXT_VPLL_MSB 0x1C -#define HTOTAL_CNTL 0x1D -#define BYTE_CLK_CNTL 0x1E -#define TV_PLL_CNTL1 0x1F -#define TV_PLL_CNTL2 0x20 -#define TV_PLL_CNTL 0x21 -#define EXT_TV_PLL 0x22 -#define V2PLL_CNTL 0x23 -#define PLL_V2CLK_CNTL 0x24 -#define EXT_V2PLL_REF_DIV 0x25 -#define EXT_V2PLL_FB_DIV 0x26 -#define EXT_V2PLL_MSB 0x27 -#define HTOTAL2_CNTL 0x28 -#define PLL_YCLK_CNTL 0x29 -#define PM_DYN_CLK_CNTL 0x2A - -/* CNFG_CNTL register constants */ -#define APERTURE_4M_ENABLE 1 -#define APERTURE_8M_ENABLE 2 -#define VGA_APERTURE_ENABLE 4 - -/* CNFG_STAT0 register constants (GX, CX) */ -#define CFG_BUS_TYPE 0x00000007 -#define CFG_MEM_TYPE 0x00000038 -#define CFG_INIT_DAC_TYPE 0x00000e00 - -/* CNFG_STAT0 register constants (CT, ET, VT) */ -#define CFG_MEM_TYPE_xT 0x00000007 - -#define ISA 0 -#define EISA 1 -#define LOCAL_BUS 6 -#define PCI 7 - -/* Memory types for GX, CX */ -#define DRAMx4 0 -#define VRAMx16 1 -#define VRAMx16ssr 2 -#define DRAMx16 3 -#define GraphicsDRAMx16 4 -#define EnhancedVRAMx16 5 -#define EnhancedVRAMx16ssr 6 - -/* Memory types for CT, ET, VT, GT */ -#define DRAM 1 -#define EDO 2 -#define PSEUDO_EDO 3 -#define SDRAM 4 -#define SGRAM 5 -#define WRAM 6 -#define SDRAM32 6 - -#define DAC_INTERNAL 0x00 -#define DAC_IBMRGB514 0x01 -#define DAC_ATI68875 0x02 -#define DAC_TVP3026_A 0x72 -#define DAC_BT476 0x03 -#define DAC_BT481 0x04 -#define DAC_ATT20C491 0x14 -#define DAC_SC15026 0x24 -#define DAC_MU9C1880 0x34 -#define DAC_IMSG174 0x44 -#define DAC_ATI68860_B 0x05 -#define DAC_ATI68860_C 0x15 -#define DAC_TVP3026_B 0x75 -#define DAC_STG1700 0x06 -#define DAC_ATT498 0x16 -#define DAC_STG1702 0x07 -#define DAC_SC15021 0x17 -#define DAC_ATT21C498 0x27 -#define DAC_STG1703 0x37 -#define DAC_CH8398 0x47 -#define DAC_ATT20C408 0x57 - -#define CLK_ATI18818_0 0 -#define CLK_ATI18818_1 1 -#define CLK_STG1703 2 -#define CLK_CH8398 3 -#define CLK_INTERNAL 4 -#define CLK_ATT20C408 5 -#define CLK_IBMRGB514 6 - -/* MEM_CNTL register constants */ -#define MEM_SIZE_ALIAS 0x00000007 -#define MEM_SIZE_512K 0x00000000 -#define MEM_SIZE_1M 0x00000001 -#define MEM_SIZE_2M 0x00000002 -#define MEM_SIZE_4M 0x00000003 -#define MEM_SIZE_6M 0x00000004 -#define MEM_SIZE_8M 0x00000005 -#define MEM_SIZE_ALIAS_GTB 0x0000000F -#define MEM_SIZE_2M_GTB 0x00000003 -#define MEM_SIZE_4M_GTB 0x00000007 -#define MEM_SIZE_6M_GTB 0x00000009 -#define MEM_SIZE_8M_GTB 0x0000000B -#define MEM_BNDRY 0x00030000 -#define MEM_BNDRY_0K 0x00000000 -#define MEM_BNDRY_256K 0x00010000 -#define MEM_BNDRY_512K 0x00020000 -#define MEM_BNDRY_1M 0x00030000 -#define MEM_BNDRY_EN 0x00040000 - -#define ONE_MB 0x100000 -/* ATI PCI constants */ -#define PCI_ATI_VENDOR_ID 0x1002 - - -/* CNFG_CHIP_ID register constants */ -#define CFG_CHIP_TYPE 0x0000FFFF -#define CFG_CHIP_CLASS 0x00FF0000 -#define CFG_CHIP_REV 0xFF000000 -#define CFG_CHIP_MAJOR 0x07000000 -#define CFG_CHIP_FND_ID 0x38000000 -#define CFG_CHIP_MINOR 0xC0000000 - - -/* Chip IDs read from CNFG_CHIP_ID */ - -/* mach64GX family */ -#define GX_CHIP_ID 0xD7 /* mach64GX (ATI888GX00) */ -#define CX_CHIP_ID 0x57 /* mach64CX (ATI888CX00) */ - -#define GX_PCI_ID 0x4758 /* mach64GX (ATI888GX00) */ -#define CX_PCI_ID 0x4358 /* mach64CX (ATI888CX00) */ - -/* mach64CT family */ -#define CT_CHIP_ID 0x4354 /* mach64CT (ATI264CT) */ -#define ET_CHIP_ID 0x4554 /* mach64ET (ATI264ET) */ - -/* mach64CT family / mach64VT class */ -#define VT_CHIP_ID 0x5654 /* mach64VT (ATI264VT) */ -#define VU_CHIP_ID 0x5655 /* mach64VTB (ATI264VTB) */ -#define VV_CHIP_ID 0x5656 /* mach64VT4 (ATI264VT4) */ - -/* mach64CT family / mach64GT (3D RAGE) class */ -#define LB_CHIP_ID 0x4c42 /* RAGE LT PRO, AGP */ -#define LD_CHIP_ID 0x4c44 /* RAGE LT PRO */ -#define LG_CHIP_ID 0x4c47 /* RAGE LT */ -#define LI_CHIP_ID 0x4c49 /* RAGE LT PRO */ -#define LP_CHIP_ID 0x4c50 /* RAGE LT PRO */ -#define LT_CHIP_ID 0x4c54 /* RAGE LT */ - -/* mach64CT family / (Rage XL) class */ -#define GR_CHIP_ID 0x4752 /* RAGE XL, BGA, PCI33 */ -#define GS_CHIP_ID 0x4753 /* RAGE XL, PQFP, PCI33 */ -#define GM_CHIP_ID 0x474d /* RAGE XL, BGA, AGP 1x,2x */ -#define GN_CHIP_ID 0x474e /* RAGE XL, PQFP,AGP 1x,2x */ -#define GO_CHIP_ID 0x474f /* RAGE XL, BGA, PCI66 */ -#define GL_CHIP_ID 0x474c /* RAGE XL, PQFP, PCI66 */ - -#define IS_XL(id) ((id)==GR_CHIP_ID || (id)==GS_CHIP_ID || \ - (id)==GM_CHIP_ID || (id)==GN_CHIP_ID || \ - (id)==GO_CHIP_ID || (id)==GL_CHIP_ID) - -#define GT_CHIP_ID 0x4754 /* RAGE (GT) */ -#define GU_CHIP_ID 0x4755 /* RAGE II/II+ (GTB) */ -#define GV_CHIP_ID 0x4756 /* RAGE IIC, PCI */ -#define GW_CHIP_ID 0x4757 /* RAGE IIC, AGP */ -#define GZ_CHIP_ID 0x475a /* RAGE IIC, AGP */ -#define GB_CHIP_ID 0x4742 /* RAGE PRO, BGA, AGP 1x and 2x */ -#define GD_CHIP_ID 0x4744 /* RAGE PRO, BGA, AGP 1x only */ -#define GI_CHIP_ID 0x4749 /* RAGE PRO, BGA, PCI33 only */ -#define GP_CHIP_ID 0x4750 /* RAGE PRO, PQFP, PCI33, full 3D */ -#define GQ_CHIP_ID 0x4751 /* RAGE PRO, PQFP, PCI33, limited 3D */ - -#define LM_CHIP_ID 0x4c4d /* RAGE Mobility AGP, full function */ -#define LN_CHIP_ID 0x4c4e /* RAGE Mobility AGP */ -#define LR_CHIP_ID 0x4c52 /* RAGE Mobility PCI, full function */ -#define LS_CHIP_ID 0x4c53 /* RAGE Mobility PCI */ - -#define IS_MOBILITY(id) ((id)==LM_CHIP_ID || (id)==LN_CHIP_ID || \ - (id)==LR_CHIP_ID || (id)==LS_CHIP_ID) -/* Mach64 major ASIC revisions */ -#define MACH64_ASIC_NEC_VT_A3 0x08 -#define MACH64_ASIC_NEC_VT_A4 0x48 -#define MACH64_ASIC_SGS_VT_A4 0x40 -#define MACH64_ASIC_SGS_VT_B1S1 0x01 -#define MACH64_ASIC_SGS_GT_B1S1 0x01 -#define MACH64_ASIC_SGS_GT_B1S2 0x41 -#define MACH64_ASIC_UMC_GT_B2U1 0x1a -#define MACH64_ASIC_UMC_GT_B2U2 0x5a -#define MACH64_ASIC_UMC_VT_B2U3 0x9a -#define MACH64_ASIC_UMC_GT_B2U3 0x9a -#define MACH64_ASIC_UMC_R3B_D_P_A1 0x1b -#define MACH64_ASIC_UMC_R3B_D_P_A2 0x5b -#define MACH64_ASIC_UMC_R3B_D_P_A3 0x1c -#define MACH64_ASIC_UMC_R3B_D_P_A4 0x5c - -/* Mach64 foundries */ -#define MACH64_FND_SGS 0 -#define MACH64_FND_NEC 1 -#define MACH64_FND_UMC 3 - -/* Mach64 chip types */ -#define MACH64_UNKNOWN 0 -#define MACH64_GX 1 -#define MACH64_CX 2 -#define MACH64_CT 3Restore -#define MACH64_ET 4 -#define MACH64_VT 5 -#define MACH64_GT 6 - -/* DST_CNTL register constants */ -#define DST_X_RIGHT_TO_LEFT 0 -#define DST_X_LEFT_TO_RIGHT 1 -#define DST_Y_BOTTOM_TO_TOP 0 -#define DST_Y_TOP_TO_BOTTOM 2 -#define DST_X_MAJOR 0 -#define DST_Y_MAJOR 4 -#define DST_X_TILE 8 -#define DST_Y_TILE 0x10 -#define DST_LAST_PEL 0x20 -#define DST_POLYGON_ENABLE 0x40 -#define DST_24_ROTATION_ENABLE 0x80 - -/* SRC_CNTL register constants */ -#define SRC_PATTERN_ENABLE 1 -#define SRC_ROTATION_ENABLE 2 -#define SRC_LINEAR_ENABLE 4 -#define SRC_BYTE_ALIGN 8 -#define SRC_LINE_X_RIGHT_TO_LEFT 0 -#define SRC_LINE_X_LEFT_TO_RIGHT 0x10 - -/* HOST_CNTL register constants */ -#define HOST_BYTE_ALIGN 1 - -/* GUI_TRAJ_CNTL register constants */ -#define PAT_MONO_8x8_ENABLE 0x01000000 -#define PAT_CLR_4x2_ENABLE 0x02000000 -#define PAT_CLR_8x1_ENABLE 0x04000000 - -/* DP_CHAIN_MASK register constants */ -#define DP_CHAIN_4BPP 0x8888 -#define DP_CHAIN_7BPP 0xD2D2 -#define DP_CHAIN_8BPP 0x8080 -#define DP_CHAIN_8BPP_RGB 0x9292 -#define DP_CHAIN_15BPP 0x4210 -#define DP_CHAIN_16BPP 0x8410 -#define DP_CHAIN_24BPP 0x8080 -#define DP_CHAIN_32BPP 0x8080 - -/* DP_PIX_WIDTH register constants */ -#define DST_1BPP 0x0 -#define DST_4BPP 0x1 -#define DST_8BPP 0x2 -#define DST_15BPP 0x3 -#define DST_16BPP 0x4 -#define DST_24BPP 0x5 -#define DST_32BPP 0x6 -#define DST_MASK 0xF -#define SRC_1BPP 0x000 -#define SRC_4BPP 0x100 -#define SRC_8BPP 0x200 -#define SRC_15BPP 0x300 -#define SRC_16BPP 0x400 -#define SRC_24BPP 0x500 -#define SRC_32BPP 0x600 -#define SRC_MASK 0xF00 -#define DP_HOST_TRIPLE_EN 0x2000 -#define HOST_1BPP 0x00000 -#define HOST_4BPP 0x10000 -#define HOST_8BPP 0x20000 -#define HOST_15BPP 0x30000 -#define HOST_16BPP 0x40000 -#define HOST_24BPP 0x50000 -#define HOST_32BPP 0x60000 -#define HOST_MASK 0xF0000 -#define BYTE_ORDER_MSB_TO_LSB 0 -#define BYTE_ORDER_LSB_TO_MSB 0x1000000 -#define BYTE_ORDER_MASK 0x1000000 - -/* DP_MIX register constants */ -#define BKGD_MIX_NOT_D 0 -#define BKGD_MIX_ZERO 1 -#define BKGD_MIX_ONE 2 -#define BKGD_MIX_D 3 -#define BKGD_MIX_NOT_S 4 -#define BKGD_MIX_D_XOR_S 5 -#define BKGD_MIX_NOT_D_XOR_S 6 -#define BKGD_MIX_S 7 -#define BKGD_MIX_NOT_D_OR_NOT_S 8 -#define BKGD_MIX_D_OR_NOT_S 9 -#define BKGD_MIX_NOT_D_OR_S 10 -#define BKGD_MIX_D_OR_S 11 -#define BKGD_MIX_D_AND_S 12 -#define BKGD_MIX_NOT_D_AND_S 13 -#define BKGD_MIX_D_AND_NOT_S 14 -#define BKGD_MIX_NOT_D_AND_NOT_S 15 -#define BKGD_MIX_D_PLUS_S_DIV2 0x17 -#define FRGD_MIX_NOT_D 0 -#define FRGD_MIX_ZERO 0x10000 -#define FRGD_MIX_ONE 0x20000 -#define FRGD_MIX_D 0x30000 -#define FRGD_MIX_NOT_S 0x40000 -#define FRGD_MIX_D_XOR_S 0x50000 -#define FRGD_MIX_NOT_D_XOR_S 0x60000 -#define FRGD_MIX_S 0x70000 -#define FRGD_MIX_NOT_D_OR_NOT_S 0x80000 -#define FRGD_MIX_D_OR_NOT_S 0x90000 -#define FRGD_MIX_NOT_D_OR_S 0xa0000 -#define FRGD_MIX_D_OR_S 0xb0000 -#define FRGD_MIX_D_AND_S 0xc0000 -#define FRGD_MIX_NOT_D_AND_S 0xd0000 -#define FRGD_MIX_D_AND_NOT_S 0xe0000 -#define FRGD_MIX_NOT_D_AND_NOT_S 0xf0000 -#define FRGD_MIX_D_PLUS_S_DIV2 0x170000 - -/* DP_SRC register constants */ -#define BKGD_SRC_BKGD_CLR 0 -#define BKGD_SRC_FRGD_CLR 1 -#define BKGD_SRC_HOST 2 -#define BKGD_SRC_BLIT 3 -#define BKGD_SRC_PATTERN 4 -#define FRGD_SRC_BKGD_CLR 0 -#define FRGD_SRC_FRGD_CLR 0x100 -#define FRGD_SRC_HOST 0x200 -#define FRGD_SRC_BLIT 0x300 -#define FRGD_SRC_PATTERN 0x400 -#define MONO_SRC_ONE 0 -#define MONO_SRC_PATTERN 0x10000 -#define MONO_SRC_HOST 0x20000 -#define MONO_SRC_BLIT 0x30000 - -/* CLR_CMP_CNTL register constants */ -#define COMPARE_FALSE 0 -#define COMPARE_TRUE 1 -#define COMPARE_NOT_EQUAL 4 -#define COMPARE_EQUAL 5 -#define COMPARE_DESTINATION 0 -#define COMPARE_SOURCE 0x1000000 - -/* FIFO_STAT register constants */ -#define FIFO_ERR 0x80000000 - -/* CONTEXT_LOAD_CNTL constants */ -#define CONTEXT_NO_LOAD 0 -#define CONTEXT_LOAD 0x10000 -#define CONTEXT_LOAD_AND_DO_FILL 0x20000 -#define CONTEXT_LOAD_AND_DO_LINE 0x30000 -#define CONTEXT_EXECUTE 0 -#define CONTEXT_CMD_DISABLE 0x80000000 - -/* GUI_STAT register constants */ -#define ENGINE_IDLE 0 -#define ENGINE_BUSY 1 -#define SCISSOR_LEFT_FLAG 0x10 -#define SCISSOR_RIGHT_FLAG 0x20 -#define SCISSOR_TOP_FLAG 0x40 -#define SCISSOR_BOTTOM_FLAG 0x80 - -/* ATI VGA Extended Regsiters */ -#define sioATIEXT 0x1ce -#define bioATIEXT 0x3ce - -#define ATI2E 0xae -#define ATI32 0xb2 -#define ATI36 0xb6 - -/* VGA Graphics Controller Registers */ -#define R_GENMO 0x3cc -#define VGAGRA 0x3ce -#define GRA06 0x06 - -/* VGA Seququencer Registers */ -#define VGASEQ 0x3c4 -#define SEQ02 0x02 -#define SEQ04 0x04 - -#define MACH64_MAX_X ENGINE_MAX_X -#define MACH64_MAX_Y ENGINE_MAX_Y - -#define INC_X 0x0020 -#define INC_Y 0x0080 - -#define RGB16_555 0x0000 -#define RGB16_565 0x0040 -#define RGB16_655 0x0080 -#define RGB16_664 0x00c0 - -#define POLY_TEXT_TYPE 0x0001 -#define IMAGE_TEXT_TYPE 0x0002 -#define TEXT_TYPE_8_BIT 0x0004 -#define TEXT_TYPE_16_BIT 0x0008 -#define POLY_TEXT_TYPE_8 (POLY_TEXT_TYPE | TEXT_TYPE_8_BIT) -#define IMAGE_TEXT_TYPE_8 (IMAGE_TEXT_TYPE | TEXT_TYPE_8_BIT) -#define POLY_TEXT_TYPE_16 (POLY_TEXT_TYPE | TEXT_TYPE_16_BIT) -#define IMAGE_TEXT_TYPE_16 (IMAGE_TEXT_TYPE | TEXT_TYPE_16_BIT) - -#define MACH64_NUM_CLOCKS 16 -#define MACH64_NUM_FREQS 50 - -/* Power Management register constants (LT & LT Pro) */ -#define PWR_MGT_ON 0x00000001 -#define PWR_MGT_MODE_MASK 0x00000006 -#define AUTO_PWR_UP 0x00000008 -#define USE_F32KHZ 0x00000400 -#define TRISTATE_MEM_EN 0x00000800 -#define SELF_REFRESH 0x00000080 -#define PWR_BLON 0x02000000 -#define STANDBY_NOW 0x10000000 -#define SUSPEND_NOW 0x20000000 -#define PWR_MGT_STATUS_MASK 0xC0000000 -#define PWR_MGT_STATUS_SUSPEND 0x80000000 - -/* PM Mode constants */ -#define PWR_MGT_MODE_PIN 0x00000000 -#define PWR_MGT_MODE_REG 0x00000002 -#define PWR_MGT_MODE_TIMER 0x00000004 -#define PWR_MGT_MODE_PCI 0x00000006 - -/* LCD registers (LT Pro) */ - -/* LCD Index register */ -#define LCD_INDEX_MASK 0x0000003F -#define LCD_DISPLAY_DIS 0x00000100 -#define LCD_SRC_SEL 0x00000200 -#define CRTC2_DISPLAY_DIS 0x00000400 - -/* LCD register indices */ -#define CNFG_PANEL 0x00 -#define LCD_GEN_CNTL 0x01 -#define DSTN_CONTROL 0x02 -#define HFB_PITCH_ADDR 0x03 -#define HORZ_STRETCHING 0x04 -#define VERT_STRETCHING 0x05 -#define EXT_VERT_STRETCH 0x06 -#define LT_GIO 0x07 -#define POWER_MANAGEMENT 0x08 -#define ZVGPIO 0x09 -#define ICON_CLR0 0x0A -#define ICON_CLR1 0x0B -#define ICON_OFFSET 0x0C -#define ICON_HORZ_VERT_POSN 0x0D -#define ICON_HORZ_VERT_OFF 0x0E -#define ICON2_CLR0 0x0F -#define ICON2_CLR1 0x10 -#define ICON2_OFFSET 0x11 -#define ICON2_HORZ_VERT_POSN 0x12 -#define ICON2_HORZ_VERT_OFF 0x13 -#define LCD_MISC_CNTL 0x14 -#define APC_CNTL 0x1C -#define POWER_MANAGEMENT_2 0x1D -#define ALPHA_BLENDING 0x25 -#define PORTRAIT_GEN_CNTL 0x26 -#define APC_CTRL_IO 0x27 -#define TEST_IO 0x28 -#define TEST_OUTPUTS 0x29 -#define DP1_MEM_ACCESS 0x2A -#define DP0_MEM_ACCESS 0x2B -#define DP0_DEBUG_A 0x2C -#define DP0_DEBUG_B 0x2D -#define DP1_DEBUG_A 0x2E -#define DP1_DEBUG_B 0x2F -#define DPCTRL_DEBUG_A 0x30 -#define DPCTRL_DEBUG_B 0x31 -#define MEMBLK_DEBUG 0x32 -#define APC_LUT_AB 0x33 -#define APC_LUT_CD 0x34 -#define APC_LUT_EF 0x35 -#define APC_LUT_GH 0x36 -#define APC_LUT_IJ 0x37 -#define APC_LUT_KL 0x38 -#define APC_LUT_MN 0x39 -#define APC_LUT_OP 0x3A - -/* Values in LCD_GEN_CTRL */ -#define CRT_ON 0x00000001ul -#define LCD_ON 0x00000002ul -#define HORZ_DIVBY2_EN 0x00000004ul -#define DONT_DS_ICON 0x00000008ul -#define LOCK_8DOT 0x00000010ul -#define ICON_ENABLE 0x00000020ul -#define DONT_SHADOW_VPAR 0x00000040ul -#define V2CLK_PM_EN 0x00000080ul -#define RST_FM 0x00000100ul -#define DISABLE_PCLK_RESET 0x00000200ul /* XC/XL */ -#define DIS_HOR_CRT_DIVBY2 0x00000400ul -#define SCLK_SEL 0x00000800ul -#define SCLK_DELAY 0x0000f000ul -#define TVCLK_PM_EN 0x00010000ul -#define VCLK_DAC_PM_EN 0x00020000ul -#define VCLK_LCD_OFF 0x00040000ul -#define SELECT_WAIT_4MS 0x00080000ul -#define XTALIN_PM_EN 0x00080000ul /* XC/XL */ -#define V2CLK_DAC_PM_EN 0x00100000ul -#define LVDS_EN 0x00200000ul -#define LVDS_PLL_EN 0x00400000ul -#define LVDS_PLL_RESET 0x00800000ul -#define LVDS_RESERVED_BITS 0x07000000ul -#define CRTC_RW_SELECT 0x08000000ul /* LTPro */ -#define USE_SHADOWED_VEND 0x10000000ul -#define USE_SHADOWED_ROWCUR 0x20000000ul -#define SHADOW_EN 0x40000000ul -#define SHADOW_RW_EN 0x80000000ul - -#define LCD_SET_PRIMARY_MASK 0x07FFFBFBul - -/* Values in HORZ_STRETCHING */ -#define HORZ_STRETCH_BLEND 0x00000ffful -#define HORZ_STRETCH_RATIO 0x0000fffful -#define HORZ_STRETCH_LOOP 0x00070000ul -#define HORZ_STRETCH_LOOP09 0x00000000ul -#define HORZ_STRETCH_LOOP11 0x00010000ul -#define HORZ_STRETCH_LOOP12 0x00020000ul -#define HORZ_STRETCH_LOOP14 0x00030000ul -#define HORZ_STRETCH_LOOP15 0x00040000ul -/* ? 0x00050000ul */ -/* ? 0x00060000ul */ -/* ? 0x00070000ul */ -/* ? 0x00080000ul */ -#define HORZ_PANEL_SIZE 0x0ff00000ul /* XC/XL */ -/* ? 0x10000000ul */ -#define AUTO_HORZ_RATIO 0x20000000ul /* XC/XL */ -#define HORZ_STRETCH_MODE 0x40000000ul -#define HORZ_STRETCH_EN 0x80000000ul - -/* Values in VERT_STRETCHING */ -#define VERT_STRETCH_RATIO0 0x000003fful -#define VERT_STRETCH_RATIO1 0x000ffc00ul -#define VERT_STRETCH_RATIO2 0x3ff00000ul -#define VERT_STRETCH_USE0 0x40000000ul -#define VERT_STRETCH_EN 0x80000000ul - -/* Values in EXT_VERT_STRETCH */ -#define VERT_STRETCH_RATIO3 0x000003fful -#define FORCE_DAC_DATA 0x000000fful -#define FORCE_DAC_DATA_SEL 0x00000300ul -#define VERT_STRETCH_MODE 0x00000400ul -#define VERT_PANEL_SIZE 0x003ff800ul -#define AUTO_VERT_RATIO 0x00400000ul -#define USE_AUTO_FP_POS 0x00800000ul -#define USE_AUTO_LCD_VSYNC 0x01000000ul -/* ? 0xfe000000ul */ - -/* Values in LCD_MISC_CNTL */ -#define BIAS_MOD_LEVEL_MASK 0x0000ff00 -#define BIAS_MOD_LEVEL_SHIFT 8 -#define BLMOD_EN 0x00010000 -#define BIASMOD_EN 0x00020000 - -#endif /* REGMACH64_H */ diff --git a/ANDROID_3.4.5/include/video/maxinefb.h b/ANDROID_3.4.5/include/video/maxinefb.h deleted file mode 100644 index 6aeb4acc..00000000 --- a/ANDROID_3.4.5/include/video/maxinefb.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * linux/drivers/video/maxinefb.h - * - * DECstation 5000/xx onboard framebuffer support, Copyright (C) 1999 by - * Michael Engel <engel@unix-ag.org> and Karsten Merker <merker@guug.de> - * This file is subject to the terms and conditions of the GNU General - * Public License. See the file COPYING in the main directory of this - * archive for more details. - */ - -#include <asm/addrspace.h> - -/* - * IMS332 video controller register base address - */ -#define MAXINEFB_IMS332_ADDRESS KSEG1ADDR(0x1c140000) - -/* - * Begin of DECstation 5000/xx onboard framebuffer memory, default resolution - * is 1024x768x8 - */ -#define DS5000_xx_ONBOARD_FBMEM_START KSEG1ADDR(0x0a000000) - -/* - * The IMS 332 video controller used in the DECstation 5000/xx series - * uses 32 bits wide registers; the following defines declare the - * register numbers, to get the real offset, these have to be multiplied - * by four. - */ - -#define IMS332_REG_CURSOR_RAM 0x200 /* hardware cursor bitmap */ - -/* - * The color palette entries have the form 0x00BBGGRR - */ -#define IMS332_REG_COLOR_PALETTE 0x100 /* color palette, 256 entries */ -#define IMS332_REG_CURSOR_COLOR_PALETTE 0x0a1 /* cursor color palette, */ - /* 3 entries */ diff --git a/ANDROID_3.4.5/include/video/mbxfb.h b/ANDROID_3.4.5/include/video/mbxfb.h deleted file mode 100644 index ea18961f..00000000 --- a/ANDROID_3.4.5/include/video/mbxfb.h +++ /dev/null @@ -1,98 +0,0 @@ -#ifndef __MBX_FB_H -#define __MBX_FB_H - -#include <asm/ioctl.h> -#include <asm/types.h> - -struct mbxfb_val { - unsigned int defval; - unsigned int min; - unsigned int max; -}; - -struct fb_info; - -struct mbxfb_platform_data { - /* Screen info */ - struct mbxfb_val xres; - struct mbxfb_val yres; - struct mbxfb_val bpp; - - /* Memory info */ - unsigned long memsize; /* if 0 use ODFB? */ - unsigned long timings1; - unsigned long timings2; - unsigned long timings3; - - int (*probe)(struct fb_info *fb); - int (*remove)(struct fb_info *fb); -}; - -/* planar */ -#define MBXFB_FMT_YUV16 0 -#define MBXFB_FMT_YUV12 1 - -/* packed */ -#define MBXFB_FMT_UY0VY1 2 -#define MBXFB_FMT_VY0UY1 3 -#define MBXFB_FMT_Y0UY1V 4 -#define MBXFB_FMT_Y0VY1U 5 -struct mbxfb_overlaySetup { - __u32 enable; - __u32 x, y; - __u32 width, height; - __u32 fmt; - __u32 mem_offset; - __u32 scaled_width; - __u32 scaled_height; - - /* Filled by the driver */ - __u32 U_offset; - __u32 V_offset; - - __u16 Y_stride; - __u16 UV_stride; -}; - -#define MBXFB_ALPHABLEND_NONE 0 -#define MBXFB_ALPHABLEND_GLOBAL 1 -#define MBXFB_ALPHABLEND_PIXEL 2 - -#define MBXFB_COLORKEY_DISABLED 0 -#define MBXFB_COLORKEY_PREVIOUS 1 -#define MBXFB_COLORKEY_CURRENT 2 -struct mbxfb_alphaCtl { - __u8 overlay_blend_mode; - __u8 overlay_colorkey_mode; - __u8 overlay_global_alpha; - __u32 overlay_colorkey; - __u32 overlay_colorkey_mask; - - __u8 graphics_blend_mode; - __u8 graphics_colorkey_mode; - __u8 graphics_global_alpha; - __u32 graphics_colorkey; - __u32 graphics_colorkey_mask; -}; - -#define MBXFB_PLANE_GRAPHICS 0 -#define MBXFB_PLANE_VIDEO 1 -struct mbxfb_planeorder { - __u8 bottom; - __u8 top; -}; - -struct mbxfb_reg { - __u32 addr; /* offset from 0x03fe 0000 */ - __u32 val; /* value */ - __u32 mask; /* which bits to touch (for write) */ -}; - -#define MBXFB_IOCX_OVERLAY _IOWR(0xF4, 0x00,struct mbxfb_overlaySetup) -#define MBXFB_IOCG_ALPHA _IOR(0xF4, 0x01,struct mbxfb_alphaCtl) -#define MBXFB_IOCS_ALPHA _IOW(0xF4, 0x02,struct mbxfb_alphaCtl) -#define MBXFB_IOCS_PLANEORDER _IOR(0xF4, 0x03,struct mbxfb_planeorder) -#define MBXFB_IOCS_REG _IOW(0xF4, 0x04,struct mbxfb_reg) -#define MBXFB_IOCX_REG _IOWR(0xF4, 0x05,struct mbxfb_reg) - -#endif /* __MBX_FB_H */ diff --git a/ANDROID_3.4.5/include/video/metronomefb.h b/ANDROID_3.4.5/include/video/metronomefb.h deleted file mode 100644 index 9863f4b6..00000000 --- a/ANDROID_3.4.5/include/video/metronomefb.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * metronomefb.h - definitions for the metronome framebuffer driver - * - * Copyright (C) 2008 by Jaya Kumar - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive for - * more details. - * - */ - -#ifndef _LINUX_METRONOMEFB_H_ -#define _LINUX_METRONOMEFB_H_ - -/* command structure used by metronome controller */ -struct metromem_cmd { - u16 opcode; - u16 args[((64-2)/2)]; - u16 csum; -}; - -/* struct used by metronome. board specific stuff comes from *board */ -struct metronomefb_par { - struct metromem_cmd *metromem_cmd; - unsigned char *metromem_wfm; - unsigned char *metromem_img; - u16 *metromem_img_csum; - u16 *csum_table; - dma_addr_t metromem_dma; - struct fb_info *info; - struct metronome_board *board; - wait_queue_head_t waitq; - u8 frame_count; - int extra_size; - int dt; -}; - -/* board specific routines and data */ -struct metronome_board { - struct module *owner; /* the platform device */ - void (*set_rst)(struct metronomefb_par *, int); - void (*set_stdby)(struct metronomefb_par *, int); - void (*cleanup)(struct metronomefb_par *); - int (*met_wait_event)(struct metronomefb_par *); - int (*met_wait_event_intr)(struct metronomefb_par *); - int (*setup_irq)(struct fb_info *); - int (*setup_fb)(struct metronomefb_par *); - int (*setup_io)(struct metronomefb_par *); - int (*get_panel_type)(void); - unsigned char *metromem; - int fw; - int fh; - int wfm_size; - struct fb_info *host_fbinfo; /* the host LCD controller's fbi */ -}; - -#endif diff --git a/ANDROID_3.4.5/include/video/mipi_display.h b/ANDROID_3.4.5/include/video/mipi_display.h deleted file mode 100644 index ddcc8ca7..00000000 --- a/ANDROID_3.4.5/include/video/mipi_display.h +++ /dev/null @@ -1,130 +0,0 @@ -/* - * Defines for Mobile Industry Processor Interface (MIPI(R)) - * Display Working Group standards: DSI, DCS, DBI, DPI - * - * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de> - * Copyright (C) 2006 Nokia Corporation - * Author: Imre Deak <imre.deak@nokia.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef MIPI_DISPLAY_H -#define MIPI_DISPLAY_H - -/* MIPI DSI Processor-to-Peripheral transaction types */ -enum { - MIPI_DSI_V_SYNC_START = 0x01, - MIPI_DSI_V_SYNC_END = 0x11, - MIPI_DSI_H_SYNC_START = 0x21, - MIPI_DSI_H_SYNC_END = 0x31, - - MIPI_DSI_COLOR_MODE_OFF = 0x02, - MIPI_DSI_COLOR_MODE_ON = 0x12, - MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22, - MIPI_DSI_TURN_ON_PERIPHERAL = 0x32, - - MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM = 0x03, - MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM = 0x13, - MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM = 0x23, - - MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM = 0x04, - MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM = 0x14, - MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM = 0x24, - - MIPI_DSI_DCS_SHORT_WRITE = 0x05, - MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15, - - MIPI_DSI_DCS_READ = 0x06, - - MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37, - - MIPI_DSI_END_OF_TRANSMISSION = 0x08, - - MIPI_DSI_NULL_PACKET = 0x09, - MIPI_DSI_BLANKING_PACKET = 0x19, - MIPI_DSI_GENERIC_LONG_WRITE = 0x29, - MIPI_DSI_DCS_LONG_WRITE = 0x39, - - MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c, - MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c, - MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c, - - MIPI_DSI_PACKED_PIXEL_STREAM_30 = 0x0d, - MIPI_DSI_PACKED_PIXEL_STREAM_36 = 0x1d, - MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12 = 0x3d, - - MIPI_DSI_PACKED_PIXEL_STREAM_16 = 0x0e, - MIPI_DSI_PACKED_PIXEL_STREAM_18 = 0x1e, - MIPI_DSI_PIXEL_STREAM_3BYTE_18 = 0x2e, - MIPI_DSI_PACKED_PIXEL_STREAM_24 = 0x3e, -}; - -/* MIPI DSI Peripheral-to-Processor transaction types */ -enum { - MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT = 0x02, - MIPI_DSI_RX_END_OF_TRANSMISSION = 0x08, - MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE = 0x11, - MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE = 0x12, - MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE = 0x1a, - MIPI_DSI_RX_DCS_LONG_READ_RESPONSE = 0x1c, - MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE = 0x21, - MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE = 0x22, -}; - -/* MIPI DCS commands */ -enum { - MIPI_DCS_NOP = 0x00, - MIPI_DCS_SOFT_RESET = 0x01, - MIPI_DCS_GET_DISPLAY_ID = 0x04, - MIPI_DCS_GET_RED_CHANNEL = 0x06, - MIPI_DCS_GET_GREEN_CHANNEL = 0x07, - MIPI_DCS_GET_BLUE_CHANNEL = 0x08, - MIPI_DCS_GET_DISPLAY_STATUS = 0x09, - MIPI_DCS_GET_POWER_MODE = 0x0A, - MIPI_DCS_GET_ADDRESS_MODE = 0x0B, - MIPI_DCS_GET_PIXEL_FORMAT = 0x0C, - MIPI_DCS_GET_DISPLAY_MODE = 0x0D, - MIPI_DCS_GET_SIGNAL_MODE = 0x0E, - MIPI_DCS_GET_DIAGNOSTIC_RESULT = 0x0F, - MIPI_DCS_ENTER_SLEEP_MODE = 0x10, - MIPI_DCS_EXIT_SLEEP_MODE = 0x11, - MIPI_DCS_ENTER_PARTIAL_MODE = 0x12, - MIPI_DCS_ENTER_NORMAL_MODE = 0x13, - MIPI_DCS_EXIT_INVERT_MODE = 0x20, - MIPI_DCS_ENTER_INVERT_MODE = 0x21, - MIPI_DCS_SET_GAMMA_CURVE = 0x26, - MIPI_DCS_SET_DISPLAY_OFF = 0x28, - MIPI_DCS_SET_DISPLAY_ON = 0x29, - MIPI_DCS_SET_COLUMN_ADDRESS = 0x2A, - MIPI_DCS_SET_PAGE_ADDRESS = 0x2B, - MIPI_DCS_WRITE_MEMORY_START = 0x2C, - MIPI_DCS_WRITE_LUT = 0x2D, - MIPI_DCS_READ_MEMORY_START = 0x2E, - MIPI_DCS_SET_PARTIAL_AREA = 0x30, - MIPI_DCS_SET_SCROLL_AREA = 0x33, - MIPI_DCS_SET_TEAR_OFF = 0x34, - MIPI_DCS_SET_TEAR_ON = 0x35, - MIPI_DCS_SET_ADDRESS_MODE = 0x36, - MIPI_DCS_SET_SCROLL_START = 0x37, - MIPI_DCS_EXIT_IDLE_MODE = 0x38, - MIPI_DCS_ENTER_IDLE_MODE = 0x39, - MIPI_DCS_SET_PIXEL_FORMAT = 0x3A, - MIPI_DCS_WRITE_MEMORY_CONTINUE = 0x3C, - MIPI_DCS_READ_MEMORY_CONTINUE = 0x3E, - MIPI_DCS_SET_TEAR_SCANLINE = 0x44, - MIPI_DCS_GET_SCANLINE = 0x45, - MIPI_DCS_READ_DDB_START = 0xA1, - MIPI_DCS_READ_DDB_CONTINUE = 0xA8, -}; - -/* MIPI DCS pixel formats */ -#define MIPI_DCS_PIXEL_FMT_24BIT 7 -#define MIPI_DCS_PIXEL_FMT_18BIT 6 -#define MIPI_DCS_PIXEL_FMT_16BIT 5 -#define MIPI_DCS_PIXEL_FMT_12BIT 3 -#define MIPI_DCS_PIXEL_FMT_8BIT 2 -#define MIPI_DCS_PIXEL_FMT_3BIT 1 - -#endif diff --git a/ANDROID_3.4.5/include/video/neomagic.h b/ANDROID_3.4.5/include/video/neomagic.h deleted file mode 100644 index bc5013e8..00000000 --- a/ANDROID_3.4.5/include/video/neomagic.h +++ /dev/null @@ -1,192 +0,0 @@ -/* - * linux/include/video/neo_reg.h -- NeoMagic Framebuffer Driver - * - * Copyright (c) 2001 Denis Oliver Kropp <dok@convergence.de> - * - * This file is subject to the terms and conditions of the GNU General - * Public License. See the file COPYING in the main directory of this - * archive for more details. - */ - -#define NEO_BS0_BLT_BUSY 0x00000001 -#define NEO_BS0_FIFO_AVAIL 0x00000002 -#define NEO_BS0_FIFO_PEND 0x00000004 - -#define NEO_BC0_DST_Y_DEC 0x00000001 -#define NEO_BC0_X_DEC 0x00000002 -#define NEO_BC0_SRC_TRANS 0x00000004 -#define NEO_BC0_SRC_IS_FG 0x00000008 -#define NEO_BC0_SRC_Y_DEC 0x00000010 -#define NEO_BC0_FILL_PAT 0x00000020 -#define NEO_BC0_SRC_MONO 0x00000040 -#define NEO_BC0_SYS_TO_VID 0x00000080 - -#define NEO_BC1_DEPTH8 0x00000100 -#define NEO_BC1_DEPTH16 0x00000200 -#define NEO_BC1_X_320 0x00000400 -#define NEO_BC1_X_640 0x00000800 -#define NEO_BC1_X_800 0x00000c00 -#define NEO_BC1_X_1024 0x00001000 -#define NEO_BC1_X_1152 0x00001400 -#define NEO_BC1_X_1280 0x00001800 -#define NEO_BC1_X_1600 0x00001c00 -#define NEO_BC1_DST_TRANS 0x00002000 -#define NEO_BC1_MSTR_BLT 0x00004000 -#define NEO_BC1_FILTER_Z 0x00008000 - -#define NEO_BC2_WR_TR_DST 0x00800000 - -#define NEO_BC3_SRC_XY_ADDR 0x01000000 -#define NEO_BC3_DST_XY_ADDR 0x02000000 -#define NEO_BC3_CLIP_ON 0x04000000 -#define NEO_BC3_FIFO_EN 0x08000000 -#define NEO_BC3_BLT_ON_ADDR 0x10000000 -#define NEO_BC3_SKIP_MAPPING 0x80000000 - -#define NEO_MODE1_DEPTH8 0x0100 -#define NEO_MODE1_DEPTH16 0x0200 -#define NEO_MODE1_DEPTH24 0x0300 -#define NEO_MODE1_X_320 0x0400 -#define NEO_MODE1_X_640 0x0800 -#define NEO_MODE1_X_800 0x0c00 -#define NEO_MODE1_X_1024 0x1000 -#define NEO_MODE1_X_1152 0x1400 -#define NEO_MODE1_X_1280 0x1800 -#define NEO_MODE1_X_1600 0x1c00 -#define NEO_MODE1_BLT_ON_ADDR 0x2000 - -/* These are offseted in MMIO space by par->CursorOff */ -#define NEOREG_CURSCNTL 0x00 -#define NEOREG_CURSX 0x04 -#define NEOREG_CURSY 0x08 -#define NEOREG_CURSBGCOLOR 0x0C -#define NEOREG_CURSFGCOLOR 0x10 -#define NEOREG_CURSMEMPOS 0x14 - -#define NEO_CURS_DISABLE 0x00000000 -#define NEO_CURS_ENABLE 0x00000001 -#define NEO_ICON64_ENABLE 0x00000008 -#define NEO_ICON128_ENABLE 0x0000000C -#define NEO_ICON_BLANK 0x00000010 - -#define NEO_GR01_SUPPRESS_VSYNC 0x10 -#define NEO_GR01_SUPPRESS_HSYNC 0x20 - -#ifdef __KERNEL__ - -#ifdef NEOFB_DEBUG -# define DBG(x) printk (KERN_DEBUG "neofb: %s\n", (x)); -#else -# define DBG(x) -#endif - -#define PCI_CHIP_NM2070 0x0001 -#define PCI_CHIP_NM2090 0x0002 -#define PCI_CHIP_NM2093 0x0003 -#define PCI_CHIP_NM2097 0x0083 -#define PCI_CHIP_NM2160 0x0004 -#define PCI_CHIP_NM2200 0x0005 -#define PCI_CHIP_NM2230 0x0025 -#define PCI_CHIP_NM2360 0x0006 -#define PCI_CHIP_NM2380 0x0016 - -/* --------------------------------------------------------------------- */ - -typedef volatile struct { - __u32 bltStat; - __u32 bltCntl; - __u32 xpColor; - __u32 fgColor; - __u32 bgColor; - __u32 pitch; - __u32 clipLT; - __u32 clipRB; - __u32 srcBitOffset; - __u32 srcStart; - __u32 reserved0; - __u32 dstStart; - __u32 xyExt; - - __u32 reserved1[19]; - - __u32 pageCntl; - __u32 pageBase; - __u32 postBase; - __u32 postPtr; - __u32 dataPtr; -} Neo2200; - -#define MMIO_SIZE 0x200000 - -#define NEO_EXT_CR_MAX 0x85 -#define NEO_EXT_GR_MAX 0xC7 - -struct neofb_par { - struct vgastate state; - unsigned int ref_count; - - unsigned char MiscOutReg; /* Misc */ - unsigned char CRTC[25]; /* Crtc Controller */ - unsigned char Sequencer[5]; /* Video Sequencer */ - unsigned char Graphics[9]; /* Video Graphics */ - unsigned char Attribute[21]; /* Video Attribute */ - - unsigned char GeneralLockReg; - unsigned char ExtCRTDispAddr; - unsigned char ExtCRTOffset; - unsigned char SysIfaceCntl1; - unsigned char SysIfaceCntl2; - unsigned char ExtColorModeSelect; - unsigned char biosMode; - - unsigned char PanelDispCntlReg1; - unsigned char PanelDispCntlReg2; - unsigned char PanelDispCntlReg3; - unsigned char PanelDispCntlRegRead; - unsigned char PanelVertCenterReg1; - unsigned char PanelVertCenterReg2; - unsigned char PanelVertCenterReg3; - unsigned char PanelVertCenterReg4; - unsigned char PanelVertCenterReg5; - unsigned char PanelHorizCenterReg1; - unsigned char PanelHorizCenterReg2; - unsigned char PanelHorizCenterReg3; - unsigned char PanelHorizCenterReg4; - unsigned char PanelHorizCenterReg5; - - int ProgramVCLK; - unsigned char VCLK3NumeratorLow; - unsigned char VCLK3NumeratorHigh; - unsigned char VCLK3Denominator; - unsigned char VerticalExt; - -#ifdef CONFIG_MTRR - int mtrr; -#endif - u8 __iomem *mmio_vbase; - u8 cursorOff; - u8 *cursorPad; /* Must die !! */ - - Neo2200 __iomem *neo2200; - - /* Panels size */ - int NeoPanelWidth; - int NeoPanelHeight; - - int maxClock; - - int pci_burst; - int lcd_stretch; - int internal_display; - int external_display; - int libretto; - u32 palette[16]; -}; - -typedef struct { - int x_res; - int y_res; - int mode; -} biosMode; - -#endif diff --git a/ANDROID_3.4.5/include/video/newport.h b/ANDROID_3.4.5/include/video/newport.h deleted file mode 100644 index de980a3b..00000000 --- a/ANDROID_3.4.5/include/video/newport.h +++ /dev/null @@ -1,583 +0,0 @@ -/* $Id: newport.h,v 1.5 1999/08/04 06:01:51 ulfc Exp $ - * - * newport.h: Defines and register layout for NEWPORT graphics - * hardware. - * - * Copyright (C) 1996 David S. Miller (davem@davemloft.net) - * - * Ulf Carlsson - Compatibility with the IRIX structures added - */ - -#ifndef _SGI_NEWPORT_H -#define _SGI_NEWPORT_H - - -typedef volatile unsigned int npireg_t; - -union npfloat { - volatile float flt; - npireg_t word; -}; - -typedef union npfloat npfreg_t; - -union np_dcb { - npireg_t byword; - struct { volatile unsigned short s0, s1; } byshort; - struct { volatile unsigned char b0, b1, b2, b3; } bybytes; -}; - -struct newport_rexregs { - npireg_t drawmode1; /* GL extra mode bits */ - -#define DM1_PLANES 0x00000007 -#define DM1_NOPLANES 0x00000000 -#define DM1_RGBPLANES 0x00000001 -#define DM1_RGBAPLANES 0x00000002 -#define DM1_OLAYPLANES 0x00000004 -#define DM1_PUPPLANES 0x00000005 -#define DM1_CIDPLANES 0x00000006 - -#define NPORT_DMODE1_DDMASK 0x00000018 -#define NPORT_DMODE1_DD4 0x00000000 -#define NPORT_DMODE1_DD8 0x00000008 -#define NPORT_DMODE1_DD12 0x00000010 -#define NPORT_DMODE1_DD24 0x00000018 -#define NPORT_DMODE1_DSRC 0x00000020 -#define NPORT_DMODE1_YFLIP 0x00000040 -#define NPORT_DMODE1_RWPCKD 0x00000080 -#define NPORT_DMODE1_HDMASK 0x00000300 -#define NPORT_DMODE1_HD4 0x00000000 -#define NPORT_DMODE1_HD8 0x00000100 -#define NPORT_DMODE1_HD12 0x00000200 -#define NPORT_DMODE1_HD32 0x00000300 -#define NPORT_DMODE1_RWDBL 0x00000400 -#define NPORT_DMODE1_ESWAP 0x00000800 /* Endian swap */ -#define NPORT_DMODE1_CCMASK 0x00007000 -#define NPORT_DMODE1_CCLT 0x00001000 -#define NPORT_DMODE1_CCEQ 0x00002000 -#define NPORT_DMODE1_CCGT 0x00004000 -#define NPORT_DMODE1_RGBMD 0x00008000 -#define NPORT_DMODE1_DENAB 0x00010000 /* Dither enable */ -#define NPORT_DMODE1_FCLR 0x00020000 /* Fast clear */ -#define NPORT_DMODE1_BENAB 0x00040000 /* Blend enable */ -#define NPORT_DMODE1_SFMASK 0x00380000 -#define NPORT_DMODE1_SF0 0x00000000 -#define NPORT_DMODE1_SF1 0x00080000 -#define NPORT_DMODE1_SFDC 0x00100000 -#define NPORT_DMODE1_SFMDC 0x00180000 -#define NPORT_DMODE1_SFSA 0x00200000 -#define NPORT_DMODE1_SFMSA 0x00280000 -#define NPORT_DMODE1_DFMASK 0x01c00000 -#define NPORT_DMODE1_DF0 0x00000000 -#define NPORT_DMODE1_DF1 0x00400000 -#define NPORT_DMODE1_DFSC 0x00800000 -#define NPORT_DMODE1_DFMSC 0x00c00000 -#define NPORT_DMODE1_DFSA 0x01000000 -#define NPORT_DMODE1_DFMSA 0x01400000 -#define NPORT_DMODE1_BBENAB 0x02000000 /* Back blend enable */ -#define NPORT_DMODE1_PFENAB 0x04000000 /* Pre-fetch enable */ -#define NPORT_DMODE1_ABLEND 0x08000000 /* Alpha blend */ -#define NPORT_DMODE1_LOMASK 0xf0000000 -#define NPORT_DMODE1_LOZERO 0x00000000 -#define NPORT_DMODE1_LOAND 0x10000000 -#define NPORT_DMODE1_LOANDR 0x20000000 -#define NPORT_DMODE1_LOSRC 0x30000000 -#define NPORT_DMODE1_LOANDI 0x40000000 -#define NPORT_DMODE1_LODST 0x50000000 -#define NPORT_DMODE1_LOXOR 0x60000000 -#define NPORT_DMODE1_LOOR 0x70000000 -#define NPORT_DMODE1_LONOR 0x80000000 -#define NPORT_DMODE1_LOXNOR 0x90000000 -#define NPORT_DMODE1_LONDST 0xa0000000 -#define NPORT_DMODE1_LOORR 0xb0000000 -#define NPORT_DMODE1_LONSRC 0xc0000000 -#define NPORT_DMODE1_LOORI 0xd0000000 -#define NPORT_DMODE1_LONAND 0xe0000000 -#define NPORT_DMODE1_LOONE 0xf0000000 - - npireg_t drawmode0; /* REX command register */ - - /* These bits define the graphics opcode being performed. */ -#define NPORT_DMODE0_OPMASK 0x00000003 /* Opcode mask */ -#define NPORT_DMODE0_NOP 0x00000000 /* No operation */ -#define NPORT_DMODE0_RD 0x00000001 /* Read operation */ -#define NPORT_DMODE0_DRAW 0x00000002 /* Draw operation */ -#define NPORT_DMODE0_S2S 0x00000003 /* Screen to screen operation */ - - /* The following decide what addressing mode(s) are to be used */ -#define NPORT_DMODE0_AMMASK 0x0000001c /* Address mode mask */ -#define NPORT_DMODE0_SPAN 0x00000000 /* Spanning address mode */ -#define NPORT_DMODE0_BLOCK 0x00000004 /* Block address mode */ -#define NPORT_DMODE0_ILINE 0x00000008 /* Iline address mode */ -#define NPORT_DMODE0_FLINE 0x0000000c /* Fline address mode */ -#define NPORT_DMODE0_ALINE 0x00000010 /* Aline address mode */ -#define NPORT_DMODE0_TLINE 0x00000014 /* Tline address mode */ -#define NPORT_DMODE0_BLINE 0x00000018 /* Bline address mode */ - - /* And now some misc. operation control bits. */ -#define NPORT_DMODE0_DOSETUP 0x00000020 -#define NPORT_DMODE0_CHOST 0x00000040 -#define NPORT_DMODE0_AHOST 0x00000080 -#define NPORT_DMODE0_STOPX 0x00000100 -#define NPORT_DMODE0_STOPY 0x00000200 -#define NPORT_DMODE0_SK1ST 0x00000400 -#define NPORT_DMODE0_SKLST 0x00000800 -#define NPORT_DMODE0_ZPENAB 0x00001000 -#define NPORT_DMODE0_LISPENAB 0x00002000 -#define NPORT_DMODE0_LISLST 0x00004000 -#define NPORT_DMODE0_L32 0x00008000 -#define NPORT_DMODE0_ZOPQ 0x00010000 -#define NPORT_DMODE0_LISOPQ 0x00020000 -#define NPORT_DMODE0_SHADE 0x00040000 -#define NPORT_DMODE0_LRONLY 0x00080000 -#define NPORT_DMODE0_XYOFF 0x00100000 -#define NPORT_DMODE0_CLAMP 0x00200000 -#define NPORT_DMODE0_ENDPF 0x00400000 -#define NPORT_DMODE0_YSTR 0x00800000 - - npireg_t lsmode; /* Mode for line stipple ops */ - npireg_t lspattern; /* Pattern for line stipple ops */ - npireg_t lspatsave; /* Backup save pattern */ - npireg_t zpattern; /* Pixel zpattern */ - npireg_t colorback; /* Background color */ - npireg_t colorvram; /* Clear color for fast vram */ - npireg_t alpharef; /* Reference value for afunctions */ - unsigned int pad0; - npireg_t smask0x; /* Window GL relative screen mask 0 */ - npireg_t smask0y; /* Window GL relative screen mask 0 */ - npireg_t _setup; - npireg_t _stepz; - npireg_t _lsrestore; - npireg_t _lssave; - - unsigned int _pad1[0x30]; - - /* Iterators, full state for context switch */ - npfreg_t _xstart; /* X-start point (current) */ - npfreg_t _ystart; /* Y-start point (current) */ - npfreg_t _xend; /* x-end point */ - npfreg_t _yend; /* y-end point */ - npireg_t xsave; /* copy of xstart integer value for BLOCk addressing MODE */ - npireg_t xymove; /* x.y offset from xstart, ystart for relative operations */ - npfreg_t bresd; - npfreg_t bress1; - npireg_t bresoctinc1; - volatile int bresrndinc2; - npireg_t brese1; - npireg_t bress2; - npireg_t aweight0; - npireg_t aweight1; - npfreg_t xstartf; - npfreg_t ystartf; - npfreg_t xendf; - npfreg_t yendf; - npireg_t xstarti; - npfreg_t xendf1; - npireg_t xystarti; - npireg_t xyendi; - npireg_t xstartendi; - - unsigned int _unused2[0x29]; - - npfreg_t colorred; - npfreg_t coloralpha; - npfreg_t colorgrn; - npfreg_t colorblue; - npfreg_t slopered; - npfreg_t slopealpha; - npfreg_t slopegrn; - npfreg_t slopeblue; - npireg_t wrmask; - npireg_t colori; - npfreg_t colorx; - npfreg_t slopered1; - npireg_t hostrw0; - npireg_t hostrw1; - npireg_t dcbmode; -#define NPORT_DMODE_WMASK 0x00000003 -#define NPORT_DMODE_W4 0x00000000 -#define NPORT_DMODE_W1 0x00000001 -#define NPORT_DMODE_W2 0x00000002 -#define NPORT_DMODE_W3 0x00000003 -#define NPORT_DMODE_EDPACK 0x00000004 -#define NPORT_DMODE_ECINC 0x00000008 -#define NPORT_DMODE_CMASK 0x00000070 -#define NPORT_DMODE_AMASK 0x00000780 -#define NPORT_DMODE_AVC2 0x00000000 -#define NPORT_DMODE_ACMALL 0x00000080 -#define NPORT_DMODE_ACM0 0x00000100 -#define NPORT_DMODE_ACM1 0x00000180 -#define NPORT_DMODE_AXMALL 0x00000200 -#define NPORT_DMODE_AXM0 0x00000280 -#define NPORT_DMODE_AXM1 0x00000300 -#define NPORT_DMODE_ABT 0x00000380 -#define NPORT_DMODE_AVCC1 0x00000400 -#define NPORT_DMODE_AVAB1 0x00000480 -#define NPORT_DMODE_ALG3V0 0x00000500 -#define NPORT_DMODE_A1562 0x00000580 -#define NPORT_DMODE_ESACK 0x00000800 -#define NPORT_DMODE_EASACK 0x00001000 -#define NPORT_DMODE_CWMASK 0x0003e000 -#define NPORT_DMODE_CHMASK 0x007c0000 -#define NPORT_DMODE_CSMASK 0x0f800000 -#define NPORT_DMODE_SENDIAN 0x10000000 - - unsigned int _unused3; - - union np_dcb dcbdata0; - npireg_t dcbdata1; -}; - -struct newport_cregs { - npireg_t smask1x; - npireg_t smask1y; - npireg_t smask2x; - npireg_t smask2y; - npireg_t smask3x; - npireg_t smask3y; - npireg_t smask4x; - npireg_t smask4y; - npireg_t topscan; - npireg_t xywin; - npireg_t clipmode; -#define NPORT_CMODE_SM0 0x00000001 -#define NPORT_CMODE_SM1 0x00000002 -#define NPORT_CMODE_SM2 0x00000004 -#define NPORT_CMODE_SM3 0x00000008 -#define NPORT_CMODE_SM4 0x00000010 -#define NPORT_CMODE_CMSK 0x00001e00 - - unsigned int _unused0; - unsigned int config; -#define NPORT_CFG_G32MD 0x00000001 -#define NPORT_CFG_BWIDTH 0x00000002 -#define NPORT_CFG_ERCVR 0x00000004 -#define NPORT_CFG_BDMSK 0x00000078 -#define NPORT_CFG_BFAINT 0x00000080 -#define NPORT_CFG_GDMSK 0x00001f80 -#define NPORT_CFG_GD0 0x00000100 -#define NPORT_CFG_GD1 0x00000200 -#define NPORT_CFG_GD2 0x00000400 -#define NPORT_CFG_GD3 0x00000800 -#define NPORT_CFG_GD4 0x00001000 -#define NPORT_CFG_GFAINT 0x00002000 -#define NPORT_CFG_TOMSK 0x0001c000 -#define NPORT_CFG_VRMSK 0x000e0000 -#define NPORT_CFG_FBTYP 0x00100000 - - npireg_t _unused1; - npireg_t status; -#define NPORT_STAT_VERS 0x00000007 -#define NPORT_STAT_GBUSY 0x00000008 -#define NPORT_STAT_BBUSY 0x00000010 -#define NPORT_STAT_VRINT 0x00000020 -#define NPORT_STAT_VIDINT 0x00000040 -#define NPORT_STAT_GLMSK 0x00001f80 -#define NPORT_STAT_BLMSK 0x0007e000 -#define NPORT_STAT_BFIRQ 0x00080000 -#define NPORT_STAT_GFIRQ 0x00100000 - - npireg_t ustatus; - npireg_t dcbreset; -}; - -struct newport_regs { - struct newport_rexregs set; - unsigned int _unused0[0x16e]; - struct newport_rexregs go; - unsigned int _unused1[0x22e]; - struct newport_cregs cset; - unsigned int _unused2[0x1ef]; - struct newport_cregs cgo; -}; - -typedef struct { - unsigned int drawmode1; - unsigned int drawmode0; - unsigned int lsmode; - unsigned int lspattern; - unsigned int lspatsave; - unsigned int zpattern; - unsigned int colorback; - unsigned int colorvram; - unsigned int alpharef; - unsigned int smask0x; - unsigned int smask0y; - unsigned int _xstart; - unsigned int _ystart; - unsigned int _xend; - unsigned int _yend; - unsigned int xsave; - unsigned int xymove; - unsigned int bresd; - unsigned int bress1; - unsigned int bresoctinc1; - unsigned int bresrndinc2; - unsigned int brese1; - unsigned int bress2; - - unsigned int aweight0; - unsigned int aweight1; - unsigned int colorred; - unsigned int coloralpha; - unsigned int colorgrn; - unsigned int colorblue; - unsigned int slopered; - unsigned int slopealpha; - unsigned int slopegrn; - unsigned int slopeblue; - unsigned int wrmask; - unsigned int hostrw0; - unsigned int hostrw1; - - /* configregs */ - - unsigned int smask1x; - unsigned int smask1y; - unsigned int smask2x; - unsigned int smask2y; - unsigned int smask3x; - unsigned int smask3y; - unsigned int smask4x; - unsigned int smask4y; - unsigned int topscan; - unsigned int xywin; - unsigned int clipmode; - unsigned int config; - - /* dcb registers */ - unsigned int dcbmode; - unsigned int dcbdata0; - unsigned int dcbdata1; -} newport_ctx; - -/* Reading/writing VC2 registers. */ -#define VC2_REGADDR_INDEX 0x00000000 -#define VC2_REGADDR_IREG 0x00000010 -#define VC2_REGADDR_RAM 0x00000030 -#define VC2_PROTOCOL (NPORT_DMODE_EASACK | 0x00800000 | 0x00040000) - -#define VC2_VLINET_ADDR 0x000 -#define VC2_VFRAMET_ADDR 0x400 -#define VC2_CGLYPH_ADDR 0x500 - -/* Now the Indexed registers of the VC2. */ -#define VC2_IREG_VENTRY 0x00 -#define VC2_IREG_CENTRY 0x01 -#define VC2_IREG_CURSX 0x02 -#define VC2_IREG_CURSY 0x03 -#define VC2_IREG_CCURSX 0x04 -#define VC2_IREG_DENTRY 0x05 -#define VC2_IREG_SLEN 0x06 -#define VC2_IREG_RADDR 0x07 -#define VC2_IREG_VFPTR 0x08 -#define VC2_IREG_VLSPTR 0x09 -#define VC2_IREG_VLIR 0x0a -#define VC2_IREG_VLCTR 0x0b -#define VC2_IREG_CTPTR 0x0c -#define VC2_IREG_WCURSY 0x0d -#define VC2_IREG_DFPTR 0x0e -#define VC2_IREG_DLTPTR 0x0f -#define VC2_IREG_CONTROL 0x10 -#define VC2_IREG_CONFIG 0x20 - -static inline void newport_vc2_set(struct newport_regs *regs, - unsigned char vc2ireg, - unsigned short val) -{ - regs->set.dcbmode = (NPORT_DMODE_AVC2 | VC2_REGADDR_INDEX | NPORT_DMODE_W3 | - NPORT_DMODE_ECINC | VC2_PROTOCOL); - regs->set.dcbdata0.byword = (vc2ireg << 24) | (val << 8); -} - -static inline unsigned short newport_vc2_get(struct newport_regs *regs, - unsigned char vc2ireg) -{ - regs->set.dcbmode = (NPORT_DMODE_AVC2 | VC2_REGADDR_INDEX | NPORT_DMODE_W1 | - NPORT_DMODE_ECINC | VC2_PROTOCOL); - regs->set.dcbdata0.bybytes.b3 = vc2ireg; - regs->set.dcbmode = (NPORT_DMODE_AVC2 | VC2_REGADDR_IREG | NPORT_DMODE_W2 | - NPORT_DMODE_ECINC | VC2_PROTOCOL); - return regs->set.dcbdata0.byshort.s1; -} - -/* VC2 Control register bits */ -#define VC2_CTRL_EVIRQ 0x0001 -#define VC2_CTRL_EDISP 0x0002 -#define VC2_CTRL_EVIDEO 0x0004 -#define VC2_CTRL_EDIDS 0x0008 -#define VC2_CTRL_ECURS 0x0010 -#define VC2_CTRL_EGSYNC 0x0020 -#define VC2_CTRL_EILACE 0x0040 -#define VC2_CTRL_ECDISP 0x0080 -#define VC2_CTRL_ECCURS 0x0100 -#define VC2_CTRL_ECG64 0x0200 -#define VC2_CTRL_GLSEL 0x0400 - -/* Controlling the color map on NEWPORT. */ -#define NCMAP_REGADDR_AREG 0x00000000 -#define NCMAP_REGADDR_ALO 0x00000000 -#define NCMAP_REGADDR_AHI 0x00000010 -#define NCMAP_REGADDR_PBUF 0x00000020 -#define NCMAP_REGADDR_CREG 0x00000030 -#define NCMAP_REGADDR_SREG 0x00000040 -#define NCMAP_REGADDR_RREG 0x00000060 -#define NCMAP_PROTOCOL (0x00008000 | 0x00040000 | 0x00800000) - -static __inline__ void newport_cmap_setaddr(struct newport_regs *regs, - unsigned short addr) -{ - regs->set.dcbmode = (NPORT_DMODE_ACMALL | NCMAP_PROTOCOL | - NPORT_DMODE_SENDIAN | NPORT_DMODE_ECINC | - NCMAP_REGADDR_AREG | NPORT_DMODE_W2); - regs->set.dcbdata0.byshort.s1 = addr; - regs->set.dcbmode = (NPORT_DMODE_ACMALL | NCMAP_PROTOCOL | - NCMAP_REGADDR_PBUF | NPORT_DMODE_W3); -} - -static __inline__ void newport_cmap_setrgb(struct newport_regs *regs, - unsigned char red, - unsigned char green, - unsigned char blue) -{ - regs->set.dcbdata0.byword = - (red << 24) | - (green << 16) | - (blue << 8); -} - -/* Miscellaneous NEWPORT routines. */ -#define BUSY_TIMEOUT 100000 -static __inline__ int newport_wait(struct newport_regs *regs) -{ - int t = BUSY_TIMEOUT; - - while (--t) - if (!(regs->cset.status & NPORT_STAT_GBUSY)) - break; - return !t; -} - -static __inline__ int newport_bfwait(struct newport_regs *regs) -{ - int t = BUSY_TIMEOUT; - - while (--t) - if(!(regs->cset.status & NPORT_STAT_BBUSY)) - break; - return !t; -} - -/* - * DCBMODE register defines: - */ - -/* Width of the data being transferred for each DCBDATA[01] word */ -#define DCB_DATAWIDTH_4 0x0 -#define DCB_DATAWIDTH_1 0x1 -#define DCB_DATAWIDTH_2 0x2 -#define DCB_DATAWIDTH_3 0x3 - -/* If set, all of DCBDATA will be moved, otherwise only DATAWIDTH bytes */ -#define DCB_ENDATAPACK (1 << 2) - -/* Enables DCBCRS auto increment after each DCB transfer */ -#define DCB_ENCRSINC (1 << 3) - -/* shift for accessing the control register select address (DBCCRS, 3 bits) */ -#define DCB_CRS_SHIFT 4 - -/* DCBADDR (4 bits): display bus slave address */ -#define DCB_ADDR_SHIFT 7 -#define DCB_VC2 (0 << DCB_ADDR_SHIFT) -#define DCB_CMAP_ALL (1 << DCB_ADDR_SHIFT) -#define DCB_CMAP0 (2 << DCB_ADDR_SHIFT) -#define DCB_CMAP1 (3 << DCB_ADDR_SHIFT) -#define DCB_XMAP_ALL (4 << DCB_ADDR_SHIFT) -#define DCB_XMAP0 (5 << DCB_ADDR_SHIFT) -#define DCB_XMAP1 (6 << DCB_ADDR_SHIFT) -#define DCB_BT445 (7 << DCB_ADDR_SHIFT) -#define DCB_VCC1 (8 << DCB_ADDR_SHIFT) -#define DCB_VAB1 (9 << DCB_ADDR_SHIFT) -#define DCB_LG3_BDVERS0 (10 << DCB_ADDR_SHIFT) -#define DCB_LG3_ICS1562 (11 << DCB_ADDR_SHIFT) -#define DCB_RESERVED (15 << DCB_ADDR_SHIFT) - -/* DCB protocol ack types */ -#define DCB_ENSYNCACK (1 << 11) -#define DCB_ENASYNCACK (1 << 12) - -#define DCB_CSWIDTH_SHIFT 13 -#define DCB_CSHOLD_SHIFT 18 -#define DCB_CSSETUP_SHIFT 23 - -/* XMAP9 specific defines */ -/* XMAP9 -- registers as seen on the DCBMODE register*/ -# define XM9_CRS_CONFIG (0 << DCB_CRS_SHIFT) -# define XM9_PUPMODE (1 << 0) -# define XM9_ODD_PIXEL (1 << 1) -# define XM9_8_BITPLANES (1 << 2) -# define XM9_SLOW_DCB (1 << 3) -# define XM9_VIDEO_RGBMAP_MASK (3 << 4) -# define XM9_EXPRESS_VIDEO (1 << 6) -# define XM9_VIDEO_OPTION (1 << 7) -# define XM9_CRS_REVISION (1 << DCB_CRS_SHIFT) -# define XM9_CRS_FIFO_AVAIL (2 << DCB_CRS_SHIFT) -# define XM9_FIFO_0_AVAIL 0 -# define XM9_FIFO_1_AVAIL 1 -# define XM9_FIFO_2_AVAIL 3 -# define XM9_FIFO_3_AVAIL 2 -# define XM9_FIFO_FULL XM9_FIFO_0_AVAIL -# define XM9_FIFO_EMPTY XM9_FIFO_3_AVAIL -# define XM9_CRS_CURS_CMAP_MSB (3 << DCB_CRS_SHIFT) -# define XM9_CRS_PUP_CMAP_MSB (4 << DCB_CRS_SHIFT) -# define XM9_CRS_MODE_REG_DATA (5 << DCB_CRS_SHIFT) -# define XM9_CRS_MODE_REG_INDEX (7 << DCB_CRS_SHIFT) - - -#define DCB_CYCLES(setup,hold,width) \ - ((hold << DCB_CSHOLD_SHIFT) | \ - (setup << DCB_CSSETUP_SHIFT)| \ - (width << DCB_CSWIDTH_SHIFT)) - -#define W_DCB_XMAP9_PROTOCOL DCB_CYCLES (2, 1, 0) -#define WSLOW_DCB_XMAP9_PROTOCOL DCB_CYCLES (5, 5, 0) -#define WAYSLOW_DCB_XMAP9_PROTOCOL DCB_CYCLES (12, 12, 0) -#define R_DCB_XMAP9_PROTOCOL DCB_CYCLES (2, 1, 3) - -static __inline__ void -xmap9FIFOWait (struct newport_regs *rex) -{ - rex->set.dcbmode = DCB_XMAP0 | XM9_CRS_FIFO_AVAIL | - DCB_DATAWIDTH_1 | R_DCB_XMAP9_PROTOCOL; - newport_bfwait (rex); - - while ((rex->set.dcbdata0.bybytes.b3 & 3) != XM9_FIFO_EMPTY) - ; -} - -static __inline__ void -xmap9SetModeReg (struct newport_regs *rex, unsigned int modereg, unsigned int data24, int cfreq) -{ - if (cfreq > 119) - rex->set.dcbmode = DCB_XMAP_ALL | XM9_CRS_MODE_REG_DATA | - DCB_DATAWIDTH_4 | W_DCB_XMAP9_PROTOCOL; - else if (cfreq > 59) - rex->set.dcbmode = DCB_XMAP_ALL | XM9_CRS_MODE_REG_DATA | - DCB_DATAWIDTH_4 | WSLOW_DCB_XMAP9_PROTOCOL; - else - rex->set.dcbmode = DCB_XMAP_ALL | XM9_CRS_MODE_REG_DATA | - DCB_DATAWIDTH_4 | WAYSLOW_DCB_XMAP9_PROTOCOL; - rex->set.dcbdata0.byword = ((modereg) << 24) | (data24 & 0xffffff); -} - -#define BT445_PROTOCOL DCB_CYCLES(1,1,3) - -#define BT445_CSR_ADDR_REG (0 << DCB_CRS_SHIFT) -#define BT445_CSR_REVISION (2 << DCB_CRS_SHIFT) - -#define BT445_REVISION_REG 0x01 - -#endif /* !(_SGI_NEWPORT_H) */ - diff --git a/ANDROID_3.4.5/include/video/omap-panel-dvi.h b/ANDROID_3.4.5/include/video/omap-panel-dvi.h deleted file mode 100644 index 87ad567b..00000000 --- a/ANDROID_3.4.5/include/video/omap-panel-dvi.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Header for DVI output driver - * - * Copyright (C) 2011 Texas Instruments Inc - * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef __OMAP_PANEL_DVI_H -#define __OMAP_PANEL_DVI_H - -struct omap_dss_device; - -/** - * struct panel_dvi_platform_data - panel driver configuration data - * @platform_enable: platform specific panel enable function - * @platform_disable: platform specific panel disable function - * @i2c_bus_num: i2c bus id for the panel - */ -struct panel_dvi_platform_data { - int (*platform_enable)(struct omap_dss_device *dssdev); - void (*platform_disable)(struct omap_dss_device *dssdev); - u16 i2c_bus_num; -}; - -#endif /* __OMAP_PANEL_DVI_H */ diff --git a/ANDROID_3.4.5/include/video/omap-panel-generic-dpi.h b/ANDROID_3.4.5/include/video/omap-panel-generic-dpi.h deleted file mode 100644 index 127e3f20..00000000 --- a/ANDROID_3.4.5/include/video/omap-panel-generic-dpi.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Header for generic DPI panel driver - * - * Copyright (C) 2010 Canonical Ltd. - * Author: Bryan Wu <bryan.wu@canonical.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef __OMAP_PANEL_GENERIC_DPI_H -#define __OMAP_PANEL_GENERIC_DPI_H - -struct omap_dss_device; - -/** - * struct panel_generic_dpi_data - panel driver configuration data - * @name: panel name - * @platform_enable: platform specific panel enable function - * @platform_disable: platform specific panel disable function - */ -struct panel_generic_dpi_data { - const char *name; - int (*platform_enable)(struct omap_dss_device *dssdev); - void (*platform_disable)(struct omap_dss_device *dssdev); -}; - -#endif /* __OMAP_PANEL_GENERIC_DPI_H */ diff --git a/ANDROID_3.4.5/include/video/omap-panel-n8x0.h b/ANDROID_3.4.5/include/video/omap-panel-n8x0.h deleted file mode 100644 index 50a1302e..00000000 --- a/ANDROID_3.4.5/include/video/omap-panel-n8x0.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef __OMAP_PANEL_N8X0_H -#define __OMAP_PANEL_N8X0_H - -struct omap_dss_device; - -struct panel_n8x0_data { - int (*platform_enable)(struct omap_dss_device *dssdev); - void (*platform_disable)(struct omap_dss_device *dssdev); - int panel_reset; - int ctrl_pwrdown; - - int (*set_backlight)(struct omap_dss_device *dssdev, int level); -}; - -#endif diff --git a/ANDROID_3.4.5/include/video/omap-panel-nokia-dsi.h b/ANDROID_3.4.5/include/video/omap-panel-nokia-dsi.h deleted file mode 100644 index 7dc71f9c..00000000 --- a/ANDROID_3.4.5/include/video/omap-panel-nokia-dsi.h +++ /dev/null @@ -1,29 +0,0 @@ -#ifndef __OMAP_NOKIA_DSI_PANEL_H -#define __OMAP_NOKIA_DSI_PANEL_H - -struct omap_dss_device; - -/** - * struct nokia_dsi_panel_data - Nokia DSI panel driver configuration - * @name: panel name - * @use_ext_te: use external TE - * @ext_te_gpio: external TE GPIO - * @esd_interval: interval of ESD checks, 0 = disabled (ms) - * @ulps_timeout: time to wait before entering ULPS, 0 = disabled (ms) - * @use_dsi_backlight: true if panel uses DSI command to control backlight - */ -struct nokia_dsi_panel_data { - const char *name; - - int reset_gpio; - - bool use_ext_te; - int ext_te_gpio; - - unsigned esd_interval; - unsigned ulps_timeout; - - bool use_dsi_backlight; -}; - -#endif /* __OMAP_NOKIA_DSI_PANEL_H */ diff --git a/ANDROID_3.4.5/include/video/omap-panel-picodlp.h b/ANDROID_3.4.5/include/video/omap-panel-picodlp.h deleted file mode 100644 index 1c342ef6..00000000 --- a/ANDROID_3.4.5/include/video/omap-panel-picodlp.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * panel data for picodlp panel - * - * Copyright (C) 2011 Texas Instruments - * - * Author: Mayuresh Janorkar <mayur@ti.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef __PANEL_PICODLP_H -#define __PANEL_PICODLP_H -/** - * struct : picodlp panel data - * picodlp_adapter_id: i2c_adapter number for picodlp - */ -struct picodlp_panel_data { - int picodlp_adapter_id; - int emu_done_gpio; - int pwrgood_gpio; -}; -#endif /* __PANEL_PICODLP_H */ diff --git a/ANDROID_3.4.5/include/video/omapdss.h b/ANDROID_3.4.5/include/video/omapdss.h deleted file mode 100644 index 483f67ca..00000000 --- a/ANDROID_3.4.5/include/video/omapdss.h +++ /dev/null @@ -1,715 +0,0 @@ -/* - * Copyright (C) 2008 Nokia Corporation - * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef __OMAP_OMAPDSS_H -#define __OMAP_OMAPDSS_H - -#include <linux/list.h> -#include <linux/kobject.h> -#include <linux/device.h> - -#define DISPC_IRQ_FRAMEDONE (1 << 0) -#define DISPC_IRQ_VSYNC (1 << 1) -#define DISPC_IRQ_EVSYNC_EVEN (1 << 2) -#define DISPC_IRQ_EVSYNC_ODD (1 << 3) -#define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4) -#define DISPC_IRQ_PROG_LINE_NUM (1 << 5) -#define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6) -#define DISPC_IRQ_GFX_END_WIN (1 << 7) -#define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8) -#define DISPC_IRQ_OCP_ERR (1 << 9) -#define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10) -#define DISPC_IRQ_VID1_END_WIN (1 << 11) -#define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12) -#define DISPC_IRQ_VID2_END_WIN (1 << 13) -#define DISPC_IRQ_SYNC_LOST (1 << 14) -#define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15) -#define DISPC_IRQ_WAKEUP (1 << 16) -#define DISPC_IRQ_SYNC_LOST2 (1 << 17) -#define DISPC_IRQ_VSYNC2 (1 << 18) -#define DISPC_IRQ_VID3_END_WIN (1 << 19) -#define DISPC_IRQ_VID3_FIFO_UNDERFLOW (1 << 20) -#define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21) -#define DISPC_IRQ_FRAMEDONE2 (1 << 22) -#define DISPC_IRQ_FRAMEDONEWB (1 << 23) -#define DISPC_IRQ_FRAMEDONETV (1 << 24) -#define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25) - -struct omap_dss_device; -struct omap_overlay_manager; - -enum omap_display_type { - OMAP_DISPLAY_TYPE_NONE = 0, - OMAP_DISPLAY_TYPE_DPI = 1 << 0, - OMAP_DISPLAY_TYPE_DBI = 1 << 1, - OMAP_DISPLAY_TYPE_SDI = 1 << 2, - OMAP_DISPLAY_TYPE_DSI = 1 << 3, - OMAP_DISPLAY_TYPE_VENC = 1 << 4, - OMAP_DISPLAY_TYPE_HDMI = 1 << 5, -}; - -enum omap_plane { - OMAP_DSS_GFX = 0, - OMAP_DSS_VIDEO1 = 1, - OMAP_DSS_VIDEO2 = 2, - OMAP_DSS_VIDEO3 = 3, -}; - -enum omap_channel { - OMAP_DSS_CHANNEL_LCD = 0, - OMAP_DSS_CHANNEL_DIGIT = 1, - OMAP_DSS_CHANNEL_LCD2 = 2, -}; - -enum omap_color_mode { - OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */ - OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */ - OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */ - OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */ - OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */ - OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */ - OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */ - OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */ - OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */ - OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */ - OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */ - OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */ - OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */ - OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */ - OMAP_DSS_COLOR_NV12 = 1 << 14, /* NV12 format: YUV 4:2:0 */ - OMAP_DSS_COLOR_RGBA16 = 1 << 15, /* RGBA16 - 4444 */ - OMAP_DSS_COLOR_RGBX16 = 1 << 16, /* RGBx16 - 4444 */ - OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, /* ARGB16 - 1555 */ - OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */ -}; - -enum omap_lcd_display_type { - OMAP_DSS_LCD_DISPLAY_STN, - OMAP_DSS_LCD_DISPLAY_TFT, -}; - -enum omap_dss_load_mode { - OMAP_DSS_LOAD_CLUT_AND_FRAME = 0, - OMAP_DSS_LOAD_CLUT_ONLY = 1, - OMAP_DSS_LOAD_FRAME_ONLY = 2, - OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3, -}; - -enum omap_dss_trans_key_type { - OMAP_DSS_COLOR_KEY_GFX_DST = 0, - OMAP_DSS_COLOR_KEY_VID_SRC = 1, -}; - -enum omap_rfbi_te_mode { - OMAP_DSS_RFBI_TE_MODE_1 = 1, - OMAP_DSS_RFBI_TE_MODE_2 = 2, -}; - -enum omap_panel_config { - OMAP_DSS_LCD_IVS = 1<<0, - OMAP_DSS_LCD_IHS = 1<<1, - OMAP_DSS_LCD_IPC = 1<<2, - OMAP_DSS_LCD_IEO = 1<<3, - OMAP_DSS_LCD_RF = 1<<4, - OMAP_DSS_LCD_ONOFF = 1<<5, - - OMAP_DSS_LCD_TFT = 1<<20, -}; - -enum omap_dss_venc_type { - OMAP_DSS_VENC_TYPE_COMPOSITE, - OMAP_DSS_VENC_TYPE_SVIDEO, -}; - -enum omap_dss_dsi_pixel_format { - OMAP_DSS_DSI_FMT_RGB888, - OMAP_DSS_DSI_FMT_RGB666, - OMAP_DSS_DSI_FMT_RGB666_PACKED, - OMAP_DSS_DSI_FMT_RGB565, -}; - -enum omap_dss_dsi_mode { - OMAP_DSS_DSI_CMD_MODE = 0, - OMAP_DSS_DSI_VIDEO_MODE, -}; - -enum omap_display_caps { - OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0, - OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1, -}; - -enum omap_dss_display_state { - OMAP_DSS_DISPLAY_DISABLED = 0, - OMAP_DSS_DISPLAY_ACTIVE, - OMAP_DSS_DISPLAY_SUSPENDED, -}; - -/* XXX perhaps this should be removed */ -enum omap_dss_overlay_managers { - OMAP_DSS_OVL_MGR_LCD, - OMAP_DSS_OVL_MGR_TV, - OMAP_DSS_OVL_MGR_LCD2, -}; - -enum omap_dss_rotation_type { - OMAP_DSS_ROT_DMA = 0, - OMAP_DSS_ROT_VRFB = 1, -}; - -/* clockwise rotation angle */ -enum omap_dss_rotation_angle { - OMAP_DSS_ROT_0 = 0, - OMAP_DSS_ROT_90 = 1, - OMAP_DSS_ROT_180 = 2, - OMAP_DSS_ROT_270 = 3, -}; - -enum omap_overlay_caps { - OMAP_DSS_OVL_CAP_SCALE = 1 << 0, - OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1, - OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2, - OMAP_DSS_OVL_CAP_ZORDER = 1 << 3, -}; - -enum omap_overlay_manager_caps { - OMAP_DSS_DUMMY_VALUE, /* add a dummy value to prevent compiler error */ -}; - -enum omap_dss_clk_source { - OMAP_DSS_CLK_SRC_FCK = 0, /* OMAP2/3: DSS1_ALWON_FCLK - * OMAP4: DSS_FCLK */ - OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK - * OMAP4: PLL1_CLK1 */ - OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK - * OMAP4: PLL1_CLK2 */ - OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC, /* OMAP4: PLL2_CLK1 */ - OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, /* OMAP4: PLL2_CLK2 */ -}; - -enum omap_hdmi_flags { - OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP = 1 << 0, -}; - -/* RFBI */ - -struct rfbi_timings { - int cs_on_time; - int cs_off_time; - int we_on_time; - int we_off_time; - int re_on_time; - int re_off_time; - int we_cycle_time; - int re_cycle_time; - int cs_pulse_width; - int access_time; - - int clk_div; - - u32 tim[5]; /* set by rfbi_convert_timings() */ - - int converted; -}; - -void omap_rfbi_write_command(const void *buf, u32 len); -void omap_rfbi_read_data(void *buf, u32 len); -void omap_rfbi_write_data(const void *buf, u32 len); -void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width, - u16 x, u16 y, - u16 w, u16 h); -int omap_rfbi_enable_te(bool enable, unsigned line); -int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode, - unsigned hs_pulse_time, unsigned vs_pulse_time, - int hs_pol_inv, int vs_pol_inv, int extif_div); -void rfbi_bus_lock(void); -void rfbi_bus_unlock(void); - -/* DSI */ - -struct omap_dss_dsi_videomode_data { - /* DSI video mode blanking data */ - /* Unit: byte clock cycles */ - u16 hsa; - u16 hfp; - u16 hbp; - /* Unit: line clocks */ - u16 vsa; - u16 vfp; - u16 vbp; - - /* DSI blanking modes */ - int blanking_mode; - int hsa_blanking_mode; - int hbp_blanking_mode; - int hfp_blanking_mode; - - /* Video port sync events */ - int vp_de_pol; - int vp_hsync_pol; - int vp_vsync_pol; - bool vp_vsync_end; - bool vp_hsync_end; - - bool ddr_clk_always_on; - int window_sync; -}; - -void dsi_bus_lock(struct omap_dss_device *dssdev); -void dsi_bus_unlock(struct omap_dss_device *dssdev); -int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data, - int len); -int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data, - int len); -int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd); -int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel); -int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, - u8 param); -int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel, - u8 param); -int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel, - u8 param1, u8 param2); -int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel, - u8 *data, int len); -int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel, - u8 *data, int len); -int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, - u8 *buf, int buflen); -int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf, - int buflen); -int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param, - u8 *buf, int buflen); -int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel, - u8 param1, u8 param2, u8 *buf, int buflen); -int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel, - u16 len); -int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel); -int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel); -int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel); -void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel); - -/* Board specific data */ -struct omap_dss_board_info { - int (*get_context_loss_count)(struct device *dev); - int num_devices; - struct omap_dss_device **devices; - struct omap_dss_device *default_device; - int (*dsi_enable_pads)(int dsi_id, unsigned lane_mask); - void (*dsi_disable_pads)(int dsi_id, unsigned lane_mask); -}; - -/* Init with the board info */ -extern int omap_display_init(struct omap_dss_board_info *board_data); -/* HDMI mux init*/ -extern int omap_hdmi_init(enum omap_hdmi_flags flags); - -struct omap_display_platform_data { - struct omap_dss_board_info *board_data; - /* TODO: Additional members to be added when PM is considered */ -}; - -struct omap_video_timings { - /* Unit: pixels */ - u16 x_res; - /* Unit: pixels */ - u16 y_res; - /* Unit: KHz */ - u32 pixel_clock; - /* Unit: pixel clocks */ - u16 hsw; /* Horizontal synchronization pulse width */ - /* Unit: pixel clocks */ - u16 hfp; /* Horizontal front porch */ - /* Unit: pixel clocks */ - u16 hbp; /* Horizontal back porch */ - /* Unit: line clocks */ - u16 vsw; /* Vertical synchronization pulse width */ - /* Unit: line clocks */ - u16 vfp; /* Vertical front porch */ - /* Unit: line clocks */ - u16 vbp; /* Vertical back porch */ -}; - -#ifdef CONFIG_OMAP2_DSS_VENC -/* Hardcoded timings for tv modes. Venc only uses these to - * identify the mode, and does not actually use the configs - * itself. However, the configs should be something that - * a normal monitor can also show */ -extern const struct omap_video_timings omap_dss_pal_timings; -extern const struct omap_video_timings omap_dss_ntsc_timings; -#endif - -struct omap_dss_cpr_coefs { - s16 rr, rg, rb; - s16 gr, gg, gb; - s16 br, bg, bb; -}; - -struct omap_overlay_info { - u32 paddr; - u32 p_uv_addr; /* for NV12 format */ - u16 screen_width; - u16 width; - u16 height; - enum omap_color_mode color_mode; - u8 rotation; - enum omap_dss_rotation_type rotation_type; - bool mirror; - - u16 pos_x; - u16 pos_y; - u16 out_width; /* if 0, out_width == width */ - u16 out_height; /* if 0, out_height == height */ - u8 global_alpha; - u8 pre_mult_alpha; - u8 zorder; -}; - -struct omap_overlay { - struct kobject kobj; - struct list_head list; - - /* static fields */ - const char *name; - enum omap_plane id; - enum omap_color_mode supported_modes; - enum omap_overlay_caps caps; - - /* dynamic fields */ - struct omap_overlay_manager *manager; - - /* - * The following functions do not block: - * - * is_enabled - * set_overlay_info - * get_overlay_info - * - * The rest of the functions may block and cannot be called from - * interrupt context - */ - - int (*enable)(struct omap_overlay *ovl); - int (*disable)(struct omap_overlay *ovl); - bool (*is_enabled)(struct omap_overlay *ovl); - - int (*set_manager)(struct omap_overlay *ovl, - struct omap_overlay_manager *mgr); - int (*unset_manager)(struct omap_overlay *ovl); - - int (*set_overlay_info)(struct omap_overlay *ovl, - struct omap_overlay_info *info); - void (*get_overlay_info)(struct omap_overlay *ovl, - struct omap_overlay_info *info); - - int (*wait_for_go)(struct omap_overlay *ovl); -}; - -struct omap_overlay_manager_info { - u32 default_color; - - enum omap_dss_trans_key_type trans_key_type; - u32 trans_key; - bool trans_enabled; - - bool partial_alpha_enabled; - - bool cpr_enable; - struct omap_dss_cpr_coefs cpr_coefs; -}; - -struct omap_overlay_manager { - struct kobject kobj; - - /* static fields */ - const char *name; - enum omap_channel id; - enum omap_overlay_manager_caps caps; - struct list_head overlays; - enum omap_display_type supported_displays; - - /* dynamic fields */ - struct omap_dss_device *device; - - /* - * The following functions do not block: - * - * set_manager_info - * get_manager_info - * apply - * - * The rest of the functions may block and cannot be called from - * interrupt context - */ - - int (*set_device)(struct omap_overlay_manager *mgr, - struct omap_dss_device *dssdev); - int (*unset_device)(struct omap_overlay_manager *mgr); - - int (*set_manager_info)(struct omap_overlay_manager *mgr, - struct omap_overlay_manager_info *info); - void (*get_manager_info)(struct omap_overlay_manager *mgr, - struct omap_overlay_manager_info *info); - - int (*apply)(struct omap_overlay_manager *mgr); - int (*wait_for_go)(struct omap_overlay_manager *mgr); - int (*wait_for_vsync)(struct omap_overlay_manager *mgr); -}; - -struct omap_dss_device { - struct device dev; - - enum omap_display_type type; - - enum omap_channel channel; - - union { - struct { - u8 data_lines; - } dpi; - - struct { - u8 channel; - u8 data_lines; - } rfbi; - - struct { - u8 datapairs; - } sdi; - - struct { - u8 clk_lane; - u8 clk_pol; - u8 data1_lane; - u8 data1_pol; - u8 data2_lane; - u8 data2_pol; - u8 data3_lane; - u8 data3_pol; - u8 data4_lane; - u8 data4_pol; - - int module; - - bool ext_te; - u8 ext_te_gpio; - } dsi; - - struct { - enum omap_dss_venc_type type; - bool invert_polarity; - } venc; - } phy; - - struct { - struct { - struct { - u16 lck_div; - u16 pck_div; - enum omap_dss_clk_source lcd_clk_src; - } channel; - - enum omap_dss_clk_source dispc_fclk_src; - } dispc; - - struct { - /* regn is one greater than TRM's REGN value */ - u16 regn; - u16 regm; - u16 regm_dispc; - u16 regm_dsi; - - u16 lp_clk_div; - enum omap_dss_clk_source dsi_fclk_src; - } dsi; - - struct { - /* regn is one greater than TRM's REGN value */ - u16 regn; - u16 regm2; - } hdmi; - } clocks; - - struct { - struct omap_video_timings timings; - - int acbi; /* ac-bias pin transitions per interrupt */ - /* Unit: line clocks */ - int acb; /* ac-bias pin frequency */ - - enum omap_panel_config config; - - enum omap_dss_dsi_pixel_format dsi_pix_fmt; - enum omap_dss_dsi_mode dsi_mode; - struct omap_dss_dsi_videomode_data dsi_vm_data; - } panel; - - struct { - u8 pixel_size; - struct rfbi_timings rfbi_timings; - } ctrl; - - int reset_gpio; - - int max_backlight_level; - - const char *name; - - /* used to match device to driver */ - const char *driver_name; - - void *data; - - struct omap_dss_driver *driver; - - /* helper variable for driver suspend/resume */ - bool activate_after_resume; - - enum omap_display_caps caps; - - struct omap_overlay_manager *manager; - - enum omap_dss_display_state state; - - /* platform specific */ - int (*platform_enable)(struct omap_dss_device *dssdev); - void (*platform_disable)(struct omap_dss_device *dssdev); - int (*set_backlight)(struct omap_dss_device *dssdev, int level); - int (*get_backlight)(struct omap_dss_device *dssdev); -}; - -struct omap_dss_hdmi_data -{ - int hpd_gpio; -}; - -struct omap_dss_driver { - struct device_driver driver; - - int (*probe)(struct omap_dss_device *); - void (*remove)(struct omap_dss_device *); - - int (*enable)(struct omap_dss_device *display); - void (*disable)(struct omap_dss_device *display); - int (*suspend)(struct omap_dss_device *display); - int (*resume)(struct omap_dss_device *display); - int (*run_test)(struct omap_dss_device *display, int test); - - int (*update)(struct omap_dss_device *dssdev, - u16 x, u16 y, u16 w, u16 h); - int (*sync)(struct omap_dss_device *dssdev); - - int (*enable_te)(struct omap_dss_device *dssdev, bool enable); - int (*get_te)(struct omap_dss_device *dssdev); - - u8 (*get_rotate)(struct omap_dss_device *dssdev); - int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate); - - bool (*get_mirror)(struct omap_dss_device *dssdev); - int (*set_mirror)(struct omap_dss_device *dssdev, bool enable); - - int (*memory_read)(struct omap_dss_device *dssdev, - void *buf, size_t size, - u16 x, u16 y, u16 w, u16 h); - - void (*get_resolution)(struct omap_dss_device *dssdev, - u16 *xres, u16 *yres); - void (*get_dimensions)(struct omap_dss_device *dssdev, - u32 *width, u32 *height); - int (*get_recommended_bpp)(struct omap_dss_device *dssdev); - - int (*check_timings)(struct omap_dss_device *dssdev, - struct omap_video_timings *timings); - void (*set_timings)(struct omap_dss_device *dssdev, - struct omap_video_timings *timings); - void (*get_timings)(struct omap_dss_device *dssdev, - struct omap_video_timings *timings); - - int (*set_wss)(struct omap_dss_device *dssdev, u32 wss); - u32 (*get_wss)(struct omap_dss_device *dssdev); - - int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len); - bool (*detect)(struct omap_dss_device *dssdev); -}; - -int omap_dss_register_driver(struct omap_dss_driver *); -void omap_dss_unregister_driver(struct omap_dss_driver *); - -void omap_dss_get_device(struct omap_dss_device *dssdev); -void omap_dss_put_device(struct omap_dss_device *dssdev); -#define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL) -struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from); -struct omap_dss_device *omap_dss_find_device(void *data, - int (*match)(struct omap_dss_device *dssdev, void *data)); - -int omap_dss_start_device(struct omap_dss_device *dssdev); -void omap_dss_stop_device(struct omap_dss_device *dssdev); - -int omap_dss_get_num_overlay_managers(void); -struct omap_overlay_manager *omap_dss_get_overlay_manager(int num); - -int omap_dss_get_num_overlays(void); -struct omap_overlay *omap_dss_get_overlay(int num); - -void omapdss_default_get_resolution(struct omap_dss_device *dssdev, - u16 *xres, u16 *yres); -int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev); - -typedef void (*omap_dispc_isr_t) (void *arg, u32 mask); -int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask); -int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask); - -int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout); -int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask, - unsigned long timeout); - -#define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver) -#define to_dss_device(x) container_of((x), struct omap_dss_device, dev) - -void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel, - bool enable); -int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable); - -int omap_dsi_update(struct omap_dss_device *dssdev, int channel, - void (*callback)(int, void *), void *data); -int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel); -int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id); -void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel); - -int omapdss_dsi_display_enable(struct omap_dss_device *dssdev); -void omapdss_dsi_display_disable(struct omap_dss_device *dssdev, - bool disconnect_lanes, bool enter_ulps); - -int omapdss_dpi_display_enable(struct omap_dss_device *dssdev); -void omapdss_dpi_display_disable(struct omap_dss_device *dssdev); -void dpi_set_timings(struct omap_dss_device *dssdev, - struct omap_video_timings *timings); -int dpi_check_timings(struct omap_dss_device *dssdev, - struct omap_video_timings *timings); - -int omapdss_sdi_display_enable(struct omap_dss_device *dssdev); -void omapdss_sdi_display_disable(struct omap_dss_device *dssdev); - -int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev); -void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev); -int omap_rfbi_prepare_update(struct omap_dss_device *dssdev, - u16 *x, u16 *y, u16 *w, u16 *h); -int omap_rfbi_update(struct omap_dss_device *dssdev, - u16 x, u16 y, u16 w, u16 h, - void (*callback)(void *), void *data); -int omap_rfbi_configure(struct omap_dss_device *dssdev, int pixel_size, - int data_lines); - -#endif diff --git a/ANDROID_3.4.5/include/video/permedia2.h b/ANDROID_3.4.5/include/video/permedia2.h deleted file mode 100644 index 9ce9adbf..00000000 --- a/ANDROID_3.4.5/include/video/permedia2.h +++ /dev/null @@ -1,254 +0,0 @@ -/* - * Permedia2 framebuffer driver definitions. - * Copyright (c) 1998-2000 Ilario Nardinocchi (nardinoc@CS.UniBO.IT) - * -------------------------------------------------------------------------- - * $Id: pm2fb.h,v 1.26 2000/09/19 00:11:53 illo Exp $ - * -------------------------------------------------------------------------- - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -#ifndef PM2FB_H -#define PM2FB_H - -#define PM2_REFERENCE_CLOCK 14318 /* in KHz */ -#define PM2_MAX_PIXCLOCK 230000 /* in KHz */ -#define PM2_REGS_SIZE 0x10000 - -#define PM2TAG(r) (u32 )(((r)-0x8000)>>3) - -/***************************************************************************** - * Permedia2 registers used in the framebuffer - *****************************************************************************/ - -#define PM2R_RESET_STATUS 0x0000 -#define PM2R_IN_FIFO_SPACE 0x0018 -#define PM2R_OUT_FIFO_WORDS 0x0020 -#define PM2R_APERTURE_ONE 0x0050 -#define PM2R_APERTURE_TWO 0x0058 -#define PM2R_FIFO_DISCON 0x0068 -#define PM2R_CHIP_CONFIG 0x0070 - -#define PM2R_REBOOT 0x1000 -#define PM2R_MEM_CONTROL 0x1040 -#define PM2R_BOOT_ADDRESS 0x1080 -#define PM2R_MEM_CONFIG 0x10c0 -#define PM2R_BYPASS_WRITE_MASK 0x1100 -#define PM2R_FRAMEBUFFER_WRITE_MASK 0x1140 - -#define PM2R_OUT_FIFO 0x2000 - -#define PM2R_SCREEN_BASE 0x3000 -#define PM2R_SCREEN_STRIDE 0x3008 -#define PM2R_H_TOTAL 0x3010 -#define PM2R_HG_END 0x3018 -#define PM2R_HB_END 0x3020 -#define PM2R_HS_START 0x3028 -#define PM2R_HS_END 0x3030 -#define PM2R_V_TOTAL 0x3038 -#define PM2R_VB_END 0x3040 -#define PM2R_VS_START 0x3048 -#define PM2R_VS_END 0x3050 -#define PM2R_VIDEO_CONTROL 0x3058 -#define PM2R_LINE_COUNT 0x3070 -#define PM2R_FIFO_CONTROL 0x3078 - -#define PM2R_RD_PALETTE_WRITE_ADDRESS 0x4000 -#define PM2R_RD_PALETTE_DATA 0x4008 -#define PM2R_RD_PIXEL_MASK 0x4010 -#define PM2R_RD_PALETTE_READ_ADDRESS 0x4018 -#define PM2R_RD_CURSOR_COLOR_ADDRESS 0x4020 -#define PM2R_RD_CURSOR_COLOR_DATA 0x4028 -#define PM2R_RD_INDEXED_DATA 0x4050 -#define PM2R_RD_CURSOR_DATA 0x4058 -#define PM2R_RD_CURSOR_X_LSB 0x4060 -#define PM2R_RD_CURSOR_X_MSB 0x4068 -#define PM2R_RD_CURSOR_Y_LSB 0x4070 -#define PM2R_RD_CURSOR_Y_MSB 0x4078 - -#define PM2R_START_X_DOM 0x8000 -#define PM2R_D_X_DOM 0x8008 -#define PM2R_START_X_SUB 0x8010 -#define PM2R_D_X_SUB 0x8018 -#define PM2R_START_Y 0x8020 -#define PM2R_D_Y 0x8028 -#define PM2R_COUNT 0x8030 -#define PM2R_RENDER 0x8038 -#define PM2R_BIT_MASK_PATTERN 0x8068 -#define PM2R_RASTERIZER_MODE 0x80a0 -#define PM2R_RECTANGLE_ORIGIN 0x80d0 -#define PM2R_RECTANGLE_SIZE 0x80d8 -#define PM2R_PACKED_DATA_LIMITS 0x8150 -#define PM2R_SCISSOR_MODE 0x8180 -#define PM2R_SCISSOR_MIN_XY 0x8188 -#define PM2R_SCISSOR_MAX_XY 0x8190 -#define PM2R_SCREEN_SIZE 0x8198 -#define PM2R_AREA_STIPPLE_MODE 0x81a0 -#define PM2R_WINDOW_ORIGIN 0x81c8 -#define PM2R_TEXTURE_ADDRESS_MODE 0x8380 -#define PM2R_TEXTURE_MAP_FORMAT 0x8588 -#define PM2R_TEXTURE_DATA_FORMAT 0x8590 -#define PM2R_TEXTURE_READ_MODE 0x8670 -#define PM2R_TEXEL_LUT_MODE 0x8678 -#define PM2R_TEXTURE_COLOR_MODE 0x8680 -#define PM2R_FOG_MODE 0x8690 -#define PM2R_TEXEL0 0x8760 -#define PM2R_COLOR_DDA_MODE 0x87e0 -#define PM2R_CONSTANT_COLOR 0x87e8 -#define PM2R_ALPHA_BLEND_MODE 0x8810 -#define PM2R_DITHER_MODE 0x8818 -#define PM2R_FB_SOFT_WRITE_MASK 0x8820 -#define PM2R_LOGICAL_OP_MODE 0x8828 -#define PM2R_LB_READ_MODE 0x8880 -#define PM2R_LB_READ_FORMAT 0x8888 -#define PM2R_LB_SOURCE_OFFSET 0x8890 -#define PM2R_LB_WINDOW_BASE 0x88b8 -#define PM2R_LB_WRITE_FORMAT 0x88c8 -#define PM2R_STENCIL_MODE 0x8988 -#define PM2R_DEPTH_MODE 0x89a0 -#define PM2R_FB_READ_MODE 0x8a80 -#define PM2R_FB_SOURCE_OFFSET 0x8a88 -#define PM2R_FB_PIXEL_OFFSET 0x8a90 -#define PM2R_FB_WINDOW_BASE 0x8ab0 -#define PM2R_FB_WRITE_MODE 0x8ab8 -#define PM2R_FB_HARD_WRITE_MASK 0x8ac0 -#define PM2R_FB_BLOCK_COLOR 0x8ac8 -#define PM2R_FB_READ_PIXEL 0x8ad0 -#define PM2R_FILTER_MODE 0x8c00 -#define PM2R_SYNC 0x8c40 -#define PM2R_YUV_MODE 0x8f00 -#define PM2R_STATISTICS_MODE 0x8c08 -#define PM2R_FB_SOURCE_DELTA 0x8d88 -#define PM2R_CONFIG 0x8d90 -#define PM2R_DELTA_MODE 0x9300 - -/* Permedia2v */ -#define PM2VR_RD_INDEX_LOW 0x4020 -#define PM2VR_RD_INDEX_HIGH 0x4028 -#define PM2VR_RD_INDEXED_DATA 0x4030 - -/* Permedia2 RAMDAC indexed registers */ -#define PM2I_RD_CURSOR_CONTROL 0x06 -#define PM2I_RD_COLOR_MODE 0x18 -#define PM2I_RD_MODE_CONTROL 0x19 -#define PM2I_RD_MISC_CONTROL 0x1e -#define PM2I_RD_PIXEL_CLOCK_A1 0x20 -#define PM2I_RD_PIXEL_CLOCK_A2 0x21 -#define PM2I_RD_PIXEL_CLOCK_A3 0x22 -#define PM2I_RD_PIXEL_CLOCK_STATUS 0x29 -#define PM2I_RD_MEMORY_CLOCK_1 0x30 -#define PM2I_RD_MEMORY_CLOCK_2 0x31 -#define PM2I_RD_MEMORY_CLOCK_3 0x32 -#define PM2I_RD_MEMORY_CLOCK_STATUS 0x33 -#define PM2I_RD_COLOR_KEY_CONTROL 0x40 -#define PM2I_RD_OVERLAY_KEY 0x41 -#define PM2I_RD_RED_KEY 0x42 -#define PM2I_RD_GREEN_KEY 0x43 -#define PM2I_RD_BLUE_KEY 0x44 - -/* Permedia2v extensions */ -#define PM2VI_RD_MISC_CONTROL 0x000 -#define PM2VI_RD_SYNC_CONTROL 0x001 -#define PM2VI_RD_DAC_CONTROL 0x002 -#define PM2VI_RD_PIXEL_SIZE 0x003 -#define PM2VI_RD_COLOR_FORMAT 0x004 -#define PM2VI_RD_CURSOR_MODE 0x005 -#define PM2VI_RD_CURSOR_X_LOW 0x007 -#define PM2VI_RD_CURSOR_X_HIGH 0x008 -#define PM2VI_RD_CURSOR_Y_LOW 0x009 -#define PM2VI_RD_CURSOR_Y_HIGH 0x00A -#define PM2VI_RD_CURSOR_X_HOT 0x00B -#define PM2VI_RD_CURSOR_Y_HOT 0x00C -#define PM2VI_RD_OVERLAY_KEY 0x00D -#define PM2VI_RD_CLK0_PRESCALE 0x201 -#define PM2VI_RD_CLK0_FEEDBACK 0x202 -#define PM2VI_RD_CLK0_POSTSCALE 0x203 -#define PM2VI_RD_CLK1_PRESCALE 0x204 -#define PM2VI_RD_CLK1_FEEDBACK 0x205 -#define PM2VI_RD_CLK1_POSTSCALE 0x206 -#define PM2VI_RD_MCLK_CONTROL 0x20D -#define PM2VI_RD_MCLK_PRESCALE 0x20E -#define PM2VI_RD_MCLK_FEEDBACK 0x20F -#define PM2VI_RD_MCLK_POSTSCALE 0x210 -#define PM2VI_RD_CURSOR_PALETTE 0x303 -#define PM2VI_RD_CURSOR_PATTERN 0x400 - -/* Fields and flags */ -#define PM2F_RENDER_AREASTIPPLE (1L<<0) -#define PM2F_RENDER_FASTFILL (1L<<3) -#define PM2F_RENDER_PRIMITIVE_MASK (3L<<6) -#define PM2F_RENDER_LINE 0 -#define PM2F_RENDER_TRAPEZOID (1L<<6) -#define PM2F_RENDER_POINT (2L<<6) -#define PM2F_RENDER_RECTANGLE (3L<<6) -#define PM2F_RENDER_SYNC_ON_BIT_MASK (1L<<11) -#define PM2F_RENDER_TEXTURE_ENABLE (1L<<13) -#define PM2F_SYNCHRONIZATION (1L<<10) -#define PM2F_PLL_LOCKED 0x10 -#define PM2F_BEING_RESET (1L<<31) -#define PM2F_DATATYPE_COLOR 0x8000 -#define PM2F_VGA_ENABLE 0x02 -#define PM2F_VGA_FIXED 0x04 -#define PM2F_FB_WRITE_ENABLE 0x01 -#define PM2F_FB_READ_SOURCE_ENABLE 0x0200 -#define PM2F_RD_PALETTE_WIDTH_8 0x02 -#define PM2F_PART_PROD_MASK 0x01ff -#define PM2F_SCREEN_SCISSOR_ENABLE 0x02 -#define PM2F_DATA_64_ENABLE 0x00010000 -#define PM2F_BLANK_LOW 0x02 -#define PM2F_HSYNC_MASK 0x18 -#define PM2F_VSYNC_MASK 0x60 -#define PM2F_HSYNC_ACT_HIGH 0x08 -#define PM2F_HSYNC_FORCED_LOW 0x10 -#define PM2F_HSYNC_ACT_LOW 0x18 -#define PM2F_VSYNC_ACT_HIGH 0x20 -#define PM2F_VSYNC_FORCED_LOW 0x40 -#define PM2F_VSYNC_ACT_LOW 0x60 -#define PM2F_LINE_DOUBLE 0x04 -#define PM2F_VIDEO_ENABLE 0x01 -#define PM2F_RD_PIXELFORMAT_SVGA 0x01 -#define PM2F_RD_PIXELFORMAT_RGB232OFFSET 0x02 -#define PM2F_RD_PIXELFORMAT_RGBA2321 0x03 -#define PM2F_RD_PIXELFORMAT_RGBA5551 0x04 -#define PM2F_RD_PIXELFORMAT_RGBA4444 0x05 -#define PM2F_RD_PIXELFORMAT_RGB565 0x06 -#define PM2F_RD_PIXELFORMAT_RGBA8888 0x08 -#define PM2F_RD_PIXELFORMAT_RGB888 0x09 -#define PM2F_RD_GUI_ACTIVE 0x10 -#define PM2F_RD_COLOR_MODE_RGB 0x20 -#define PM2F_DELTA_ORDER_RGB (1L<<18) -#define PM2F_RD_TRUECOLOR 0x80 -#define PM2F_NO_ALPHA_BUFFER 0x10 -#define PM2F_TEXTEL_SIZE_16 0x00080000 -#define PM2F_TEXTEL_SIZE_32 0x00100000 -#define PM2F_TEXTEL_SIZE_4 0x00180000 -#define PM2F_TEXTEL_SIZE_24 0x00200000 -#define PM2F_INCREASE_X (1L<<21) -#define PM2F_INCREASE_Y (1L<<22) -#define PM2F_CONFIG_FB_WRITE_ENABLE (1L<<3) -#define PM2F_CONFIG_FB_PACKED_DATA (1L<<2) -#define PM2F_CONFIG_FB_READ_DEST_ENABLE (1L<<1) -#define PM2F_CONFIG_FB_READ_SOURCE_ENABLE (1L<<0) -#define PM2F_COLOR_KEY_TEST_OFF (1L<<4) -#define PM2F_MEM_CONFIG_RAM_MASK (3L<<29) -#define PM2F_MEM_BANKS_1 0L -#define PM2F_MEM_BANKS_2 (1L<<29) -#define PM2F_MEM_BANKS_3 (2L<<29) -#define PM2F_MEM_BANKS_4 (3L<<29) -#define PM2F_APERTURE_STANDARD 0 -#define PM2F_APERTURE_BYTESWAP 1 -#define PM2F_APERTURE_HALFWORDSWAP 2 -#define PM2F_CURSORMODE_CURSOR_ENABLE (1 << 0) -#define PM2F_CURSORMODE_TYPE_X (1 << 4) - -typedef enum { - PM2_TYPE_PERMEDIA2, - PM2_TYPE_PERMEDIA2V -} pm2type_t; - -#endif /* PM2FB_H */ - -/***************************************************************************** - * That's all folks! - *****************************************************************************/ diff --git a/ANDROID_3.4.5/include/video/platform_lcd.h b/ANDROID_3.4.5/include/video/platform_lcd.h deleted file mode 100644 index ad3bdfe7..00000000 --- a/ANDROID_3.4.5/include/video/platform_lcd.h +++ /dev/null @@ -1,21 +0,0 @@ -/* include/video/platform_lcd.h - * - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * Generic platform-device LCD power control interface. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * -*/ - -struct plat_lcd_data; -struct fb_info; - -struct plat_lcd_data { - void (*set_power)(struct plat_lcd_data *, unsigned int power); - int (*match_fb)(struct plat_lcd_data *, struct fb_info *); -}; - diff --git a/ANDROID_3.4.5/include/video/pm3fb.h b/ANDROID_3.4.5/include/video/pm3fb.h deleted file mode 100644 index 2b85134f..00000000 --- a/ANDROID_3.4.5/include/video/pm3fb.h +++ /dev/null @@ -1,1061 +0,0 @@ -/* - * linux/drivers/video/pm3fb.h -- 3DLabs Permedia3 frame buffer device - * - * Copyright (C) 2001 Romain Dolbeau <dolbeau@irisa.fr> - * Copyright (C) 2001 Sven Luther, <luther@dpt-info.u-strasbg.fr> - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive for - * more details. - */ - -#ifndef PM3FB_H -#define PM3FB_H - -/********************************************** -* GLINT Permedia3 Control Status registers * -***********************************************/ -/* Control Status Registers */ -#define PM3ResetStatus 0x0000 -#define PM3IntEnable 0x0008 -#define PM3IntFlags 0x0010 -#define PM3InFIFOSpace 0x0018 -#define PM3OutFIFOWords 0x0020 -#define PM3DMAAddress 0x0028 -#define PM3DMACount 0x0030 -#define PM3ErrorFlags 0x0038 -#define PM3VClkCtl 0x0040 -#define PM3TestRegister 0x0048 -#define PM3Aperture0 0x0050 -#define PM3Aperture1 0x0058 -#define PM3DMAControl 0x0060 -#define PM3FIFODis 0x0068 -#define PM3ChipConfig 0x0070 -#define PM3AGPControl 0x0078 - -#define PM3GPOutDMAAddress 0x0080 -#define PM3PCIFeedbackCount 0x0088 -#define PM3PCIAbortStatus 0x0090 -#define PM3PCIAbortAddress 0x0098 - -#define PM3PCIPLLStatus 0x00f0 - -#define PM3HostTextureAddress 0x0100 -#define PM3TextureDownloadControl 0x0108 -#define PM3TextureOperation 0x0110 -#define PM3LogicalTexturePage 0x0118 -#define PM3TexDMAAddress 0x0120 -#define PM3TexFIFOSpace 0x0128 - -/********************************************** -* GLINT Permedia3 Region 0 Bypass Controls * -***********************************************/ -#define PM3ByAperture1Mode 0x0300 - #define PM3ByApertureMode_BYTESWAP_ABCD (0 << 0) - #define PM3ByApertureMode_BYTESWAP_BADC (1 << 0) - #define PM3ByApertureMode_BYTESWAP_CDAB (2 << 0) - #define PM3ByApertureMode_BYTESWAP_DCBA (3 << 0) - #define PM3ByApertureMode_PATCH_ENABLE (1 << 2) - #define PM3ByApertureMode_FORMAT_RAW (0 << 3) - #define PM3ByApertureMode_FORMAT_YUYV (1 << 3) - #define PM3ByApertureMode_FORMAT_UYVY (2 << 3) - #define PM3ByApertureMode_PIXELSIZE_8BIT (0 << 5) - #define PM3ByApertureMode_PIXELSIZE_16BIT (1 << 5) - #define PM3ByApertureMode_PIXELSIZE_32BIT (2 << 5) - #define PM3ByApertureMode_PIXELSIZE_MASK (3 << 5) - #define PM3ByApertureMode_EFFECTIVE_STRIDE_1024 (0 << 7) - #define PM3ByApertureMode_EFFECTIVE_STRIDE_2048 (1 << 7) - #define PM3ByApertureMode_EFFECTIVE_STRIDE_4096 (2 << 7) - #define PM3ByApertureMode_EFFECTIVE_STRIDE_8192 (3 << 7) - #define PM3ByApertureMode_PATCH_OFFSET_X(off) (((off) & 0x7f) << 9) - #define PM3ByApertureMode_PATCH_OFFSET_Y(off) (((off) & 0x7f) << 16) - #define PM3ByApertureMode_FRAMEBUFFER (0 << 21) - #define PM3ByApertureMode_LOCALBUFFER (1 << 21) - #define PM3ByApertureMode_DOUBLE_WRITE_OFF (0 << 22) - #define PM3ByApertureMode_DOUBLE_WRITE_1MB (1 << 22) - #define PM3ByApertureMode_DOUBLE_WRITE_2MB (2 << 22) - #define PM3ByApertureMode_DOUBLE_WRITE_4MB (3 << 22) - #define PM3ByApertureMode_DOUBLE_WRITE_8MB (4 << 22) - #define PM3ByApertureMode_DOUBLE_WRITE_16MB (5 << 22) - #define PM3ByApertureMode_DOUBLE_WRITE_32MB (6 << 22) - -#define PM3ByAperture2Mode 0x0328 - -/********************************************** -* GLINT Permedia3 Memory Control (0x1000) * -***********************************************/ -#define PM3MemCounter 0x1000 -#define PM3MemBypassWriteMask 0x1008 -#define PM3MemScratch 0x1010 -#define PM3LocalMemCaps 0x1018 - #define PM3LocalMemCaps_NoWriteMask (1 << 28) -#define PM3LocalMemTimings 0x1020 -#define PM3LocalMemControl 0x1028 -#define PM3LocalMemRefresh 0x1030 -#define PM3LocalMemPowerDown 0x1038 -#define PM3RemoteMemControl 0x1100 - -/********************************************** -* GLINT Permedia3 Video Control (0x3000) * -***********************************************/ - -#define PM3ScreenBase 0x3000 -#define PM3ScreenStride 0x3008 -#define PM3HTotal 0x3010 -#define PM3HgEnd 0x3018 -#define PM3HbEnd 0x3020 -#define PM3HsStart 0x3028 -#define PM3HsEnd 0x3030 -#define PM3VTotal 0x3038 -#define PM3VbEnd 0x3040 -#define PM3VsStart 0x3048 -#define PM3VsEnd 0x3050 -#define PM3VideoControl 0x3058 - #define PM3VideoControl_ENABLE (1 << 0) - #define PM3VideoControl_BLANK_ACTIVE_HIGH (0 << 1) - #define PM3VideoControl_BLANK_ACTIVE_LOW (1 << 1) - #define PM3VideoControl_LINE_DOUBLE_OFF (0 << 2) - #define PM3VideoControl_LINE_DOUBLE_ON (1 << 2) - #define PM3VideoControl_HSYNC_FORCE_HIGH (0 << 3) - #define PM3VideoControl_HSYNC_ACTIVE_HIGH (1 << 3) - #define PM3VideoControl_HSYNC_FORCE_LOW (2 << 3) - #define PM3VideoControl_HSYNC_ACTIVE_LOW (3 << 3) - #define PM3VideoControl_HSYNC_MASK (3 << 3) - #define PM3VideoControl_VSYNC_FORCE_HIGH (0 << 5) - #define PM3VideoControl_VSYNC_ACTIVE_HIGH (1 << 5) - #define PM3VideoControl_VSYNC_FORCE_LOW (2 << 5) - #define PM3VideoControl_VSYNC_ACTIVE_LOW (3 << 5) - #define PM3VideoControl_VSYNC_MASK (3 << 5) - #define PM3VideoControl_BYTE_DOUBLE_OFF (0 << 7) - #define PM3VideoControl_BYTE_DOUBLE_ON (1 << 7) - #define PM3VideoControl_BUFFER_SWAP_SYNCON_FRAMEBLANK (0 << 9) - #define PM3VideoControl_BUFFER_SWAP_FREE_RUNNING (1 << 9) - #define PM3VideoControl_BUFFER_SWAP_LIMITETO_FRAMERATE (2 << 9) - #define PM3VideoControl_STEREO_ENABLE (1 << 11) - #define PM3VideoControl_RIGHT_EYE_ACTIVE_HIGH (0 << 12) - #define PM3VideoControl_RIGHT_EYE_ACTIVE_LOW (1 << 12) - #define PM3VideoControl_VIDEO_EXT_LOW (0 << 14) - #define PM3VideoControl_VIDEO_EXT_HIGH (1 << 14) - #define PM3VideoControl_SYNC_MODE_INDEPENDENT (0 << 16) - #define PM3VideoControl_SYNC_MODE_SYNCTO_VSA (1 << 16) - #define PM3VideoControl_SYNC_MODE_SYNCTO_VSB (2 << 16) - #define PM3VideoControl_PATCH_ENABLE (1 << 18) - #define PM3VideoControl_PIXELSIZE_8BIT (0 << 19) - #define PM3VideoControl_PIXELSIZE_16BIT (1 << 19) - #define PM3VideoControl_PIXELSIZE_32BIT (2 << 19) - #define PM3VideoControl_DISPLAY_ENABLE (1 << 21) - #define PM3VideoControl_PATCH_OFFSET_X(off) (((off) & 0x3f) << 22) - #define PM3VideoControl_PATCH_OFFSET_Y(off) (((off) & 0x3f) << 28) -#define PM3InterruptLine 0x3060 -#define PM3DisplayData 0x3068 -#define PM3VerticalLineCount 0x3070 -#define PM3FifoControl 0x3078 -#define PM3ScreenBaseRight 0x3080 -#define PM3MiscControl 0x3088 - -#define PM3VideoOverlayUpdate 0x3100 - #define PM3VideoOverlayUpdate_ENABLE (1 << 0) -#define PM3VideoOverlayMode 0x3108 - #define PM3VideoOverlayMode_ENABLE (1 << 0) - #define PM3VideoOverlayMode_BUFFERSYNC_MANUAL (0 << 1) - #define PM3VideoOverlayMode_BUFFERSYNC_VIDEOSTREAMA (1 << 1) - #define PM3VideoOverlayMode_BUFFERSYNC_VIDEOSTREAMB (2 << 1) - #define PM3VideoOverlayMode_FIELDPOLARITY_NORMAL (0 << 4) - #define PM3VideoOverlayMode_FIELDPOLARITY_INVERT (1 << 4) - #define PM3VideoOverlayMode_PIXELSIZE_8BIT (0 << 5) - #define PM3VideoOverlayMode_PIXELSIZE_16BIT (1 << 5) - #define PM3VideoOverlayMode_PIXELSIZE_32BIT (2 << 5) - #define PM3VideoOverlayMode_COLORFORMAT_RGB8888 \ - ((0 << 7)|(1 << 12)|(2 << 5)) - #define PM3VideoOverlayMode_COLORFORMAT_RGB4444 \ - ((1 << 7)|(1 << 12)|(1 << 5)) - #define PM3VideoOverlayMode_COLORFORMAT_RGB5551 \ - ((2 << 7)|(1 << 12)|(1 << 5)) - #define PM3VideoOverlayMode_COLORFORMAT_RGB565 \ - ((3 << 7)|(1 << 12)|(1 << 5)) - #define PM3VideoOverlayMode_COLORFORMAT_RGB332 \ - ((4 << 7)|(1 << 12)|(0 << 5)) - #define PM3VideoOverlayMode_COLORFORMAT_BGR8888 \ - ((0 << 7)|(2 << 5)) - #define PM3VideoOverlayMode_COLORFORMAT_BGR4444 \ - ((1 << 7)|(1 << 5)) - #define PM3VideoOverlayMode_COLORFORMAT_BGR5551 \ - ((2 << 7)|(1 << 5)) - #define PM3VideoOverlayMode_COLORFORMAT_BGR565 \ - ((3 << 7)|(1 << 5)) - #define PM3VideoOverlayMode_COLORFORMAT_BGR332 \ - ((4 << 7)|(0 << 5)) - #define PM3VideoOverlayMode_COLORFORMAT_CI8 \ - ((5 << 7)|(1 << 12)|(0 << 5)) - #define PM3VideoOverlayMode_COLORFORMAT_VUY444 \ - ((2 << 10)|(1 << 12)|(2 << 5)) - #define PM3VideoOverlayMode_COLORFORMAT_YUV444 \ - ((2 << 10)|(2 << 5)) - #define PM3VideoOverlayMode_COLORFORMAT_VUY422 \ - ((1 << 10)|(1 << 12)|(1 << 5)) - #define PM3VideoOverlayMode_COLORFORMAT_YUV422 \ - ((1 << 10)|(1 << 5)) - #define PM3VideoOverlayMode_COLORORDER_BGR (0 << 12) - #define PM3VideoOverlayMode_COLORORDER_RGB (1 << 12) - #define PM3VideoOverlayMode_LINEARCOLOREXT_OFF (0 << 13) - #define PM3VideoOverlayMode_LINEARCOLOREXT_ON (1 << 13) - #define PM3VideoOverlayMode_FILTER_MASK (3 << 14) - #define PM3VideoOverlayMode_FILTER_OFF (0 << 14) - #define PM3VideoOverlayMode_FILTER_FULL (1 << 14) - #define PM3VideoOverlayMode_FILTER_PARTIAL (2 << 14) - #define PM3VideoOverlayMode_DEINTERLACE_OFF (0 << 16) - #define PM3VideoOverlayMode_DEINTERLACE_BOB (1 << 16) - #define PM3VideoOverlayMode_PATCHMODE_OFF (0 << 18) - #define PM3VideoOverlayMode_PATCHMODE_ON (1 << 18) - #define PM3VideoOverlayMode_FLIP_VIDEO (0 << 20) - #define PM3VideoOverlayMode_FLIP_VIDEOSTREAMA (1 << 20) - #define PM3VideoOverlayMode_FLIP_VIDEOSTREAMB (2 << 20) - #define PM3VideoOverlayMode_MIRROR_MASK (3 << 23) - #define PM3VideoOverlayMode_MIRRORX_OFF (0 << 23) - #define PM3VideoOverlayMode_MIRRORX_ON (1 << 23) - #define PM3VideoOverlayMode_MIRRORY_OFF (0 << 24) - #define PM3VideoOverlayMode_MIRRORY_ON (1 << 24) -#define PM3VideoOverlayFifoControl 0x3110 -#define PM3VideoOverlayIndex 0x3118 -#define PM3VideoOverlayBase0 0x3120 -#define PM3VideoOverlayBase1 0x3128 -#define PM3VideoOverlayBase2 0x3130 -#define PM3VideoOverlayStride 0x3138 - #define PM3VideoOverlayStride_STRIDE(s) (((s) & 0xfff) << 0) -#define PM3VideoOverlayWidth 0x3140 - #define PM3VideoOverlayWidth_WIDTH(w) (((w) & 0xfff) << 0) -#define PM3VideoOverlayHeight 0x3148 - #define PM3VideoOverlayHeight_HEIGHT(h) (((h) & 0xfff) << 0) -#define PM3VideoOverlayOrigin 0x3150 - #define PM3VideoOverlayOrigin_XORIGIN(x) (((x) & 0xfff) << 0) - #define PM3VideoOverlayOrigin_YORIGIN(y) (((y) & 0xfff) << 16) -#define PM3VideoOverlayShrinkXDelta 0x3158 - #define PM3VideoOverlayShrinkXDelta_NONE (1 << 16) - #define PM3VideoOverlayShrinkXDelta_DELTA(s,d) \ - ((((s) << 16)/(d)) & 0x0ffffff0) -#define PM3VideoOverlayZoomXDelta 0x3160 - #define PM3VideoOverlayZoomXDelta_NONE (1 << 16) - #define PM3VideoOverlayZoomXDelta_DELTA(s,d) \ - ((((s) << 16)/(d)) & 0x0001fff0) -#define PM3VideoOverlayYDelta 0x3168 - #define PM3VideoOverlayYDelta_NONE (1 << 16) - #define PM3VideoOverlayYDelta_DELTA(s,d) \ - ((((s) << 16)/(d)) & 0x0ffffff0) -#define PM3VideoOverlayFieldOffset 0x3170 -#define PM3VideoOverlayStatus 0x3178 - -/********************************************** -* GLINT Permedia3 RAMDAC Registers (0x4000) * -***********************************************/ -/* Direct Registers */ -#define PM3RD_PaletteWriteAddress 0x4000 -#define PM3RD_PaletteData 0x4008 -#define PM3RD_PixelMask 0x4010 -#define PM3RD_PaletteReadAddress 0x4018 - -#define PM3RD_IndexLow 0x4020 -#define PM3RD_IndexHigh 0x4028 -#define PM3RD_IndexedData 0x4030 -#define PM3RD_IndexControl 0x4038 - #define PM3RD_IndexControl_AUTOINCREMENT_ENABLE (1 << 0) - -/* Indirect Registers */ -#define PM3RD_MiscControl 0x000 - #define PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE (1 << 0) - #define PM3RD_MiscControl_PIXELDOUBLE_ENABLE (1 << 1) - #define PM3RD_MiscControl_LASTREAD_ADDR_ENABLE (1 << 2) - #define PM3RD_MiscControl_DIRECTCOLOR_ENABLE (1 << 3) - #define PM3RD_MiscControl_OVERLAY_ENABLE (1 << 4) - #define PM3RD_MiscControl_PIXELDOUBLE_BUFFER_ENABLE (1 << 5) - #define PM3RD_MiscControl_VSB_OUTPUT_ENABLE (1 << 6) - #define PM3RD_MiscControl_STEREODOUBLE_BUFFER_ENABLE (1 << 7) -#define PM3RD_SyncControl 0x001 - #define PM3RD_SyncControl_HSYNC_ACTIVE_LOW (0 << 0) - #define PM3RD_SyncControl_HSYNC_ACTIVE_HIGH (1 << 0) - #define PM3RD_SyncControl_HSYNC_FORCE_ACTIVE (3 << 0) - #define PM3RD_SyncControl_HSYNC_FORCE_INACTIVE (4 << 0) - #define PM3RD_SyncControl_HSYNC_TRI_STATE (2 << 0) - #define PM3RD_SyncControl_VSYNC_ACTIVE_LOW (0 << 3) - #define PM3RD_SyncControl_VSYNC_ACTIVE_HIGH (1 << 3) - #define PM3RD_SyncControl_VSYNC_TRI_STATE (2 << 3) - #define PM3RD_SyncControl_VSYNC_FORCE_ACTIVE (3 << 3) - #define PM3RD_SyncControl_VSYNC_FORCE_INACTIVE (4 << 3) - #define PM3RD_SyncControl_HSYNC_OVERRIDE_SETBY_HSYNC (0 << 6) - #define PM3RD_SyncControl_HSYNC_OVERRIDE_FORCE_HIGH (1 << 6) - #define PM3RD_SyncControl_VSYNC_OVERRIDE_SETBY_VSYNC (0 << 7) - #define PM3RD_SyncControl_VSYNC_OVERRIDE_FORCE_HIGH (1 << 7) -#define PM3RD_DACControl 0x002 - #define PM3RD_DACControl_DAC_POWER_ON (0 << 0) - #define PM3RD_DACControl_DAC_POWER_OFF (1 << 0) - #define PM3RD_DACControl_SYNC_ON_GREEN_ENABLE (1 << 3) - #define PM3RD_DACControl_BLANK_RED_DAC_ENABLE (1 << 4) - #define PM3RD_DACControl_BLANK_GREEN_DAC_ENABLE (1 << 5) - #define PM3RD_DACControl_BLANK_BLUE_DAC_ENABLE (1 << 6) - #define PM3RD_DACControl_BLANK_PEDESTAL_ENABLE (1 << 7) -#define PM3RD_PixelSize 0x003 - #define PM3RD_PixelSize_24_BIT_PIXELS (4 << 0) - #define PM3RD_PixelSize_32_BIT_PIXELS (2 << 0) - #define PM3RD_PixelSize_16_BIT_PIXELS (1 << 0) - #define PM3RD_PixelSize_8_BIT_PIXELS (0 << 0) -#define PM3RD_ColorFormat 0x004 - #define PM3RD_ColorFormat_LINEAR_COLOR_EXT_ENABLE (1 << 6) - #define PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW (1 << 5) - #define PM3RD_ColorFormat_COLOR_ORDER_RED_LOW (0 << 5) - #define PM3RD_ColorFormat_COLOR_FORMAT_MASK (0x1f << 0) - #define PM3RD_ColorFormat_8888_COLOR (0 << 0) - #define PM3RD_ColorFormat_5551_FRONT_COLOR (1 << 0) - #define PM3RD_ColorFormat_4444_COLOR (2 << 0) - #define PM3RD_ColorFormat_332_FRONT_COLOR (5 << 0) - #define PM3RD_ColorFormat_332_BACK_COLOR (6 << 0) - #define PM3RD_ColorFormat_2321_FRONT_COLOR (9 << 0) - #define PM3RD_ColorFormat_2321_BACK_COLOR (10 << 0) - #define PM3RD_ColorFormat_232_FRONTOFF_COLOR (11 << 0) - #define PM3RD_ColorFormat_232_BACKOFF_COLOR (12 << 0) - #define PM3RD_ColorFormat_5551_BACK_COLOR (13 << 0) - #define PM3RD_ColorFormat_CI8_COLOR (14 << 0) - #define PM3RD_ColorFormat_565_FRONT_COLOR (16 << 0) - #define PM3RD_ColorFormat_565_BACK_COLOR (17 << 0) -#define PM3RD_CursorMode 0x005 - #define PM3RD_CursorMode_CURSOR_ENABLE (1 << 0) - #define PM3RD_CursorMode_FORMAT_64x64_2BPE_P0123 (0 << 2) - #define PM3RD_CursorMode_FORMAT_32x32_2BPE_P0 (1 << 2) - #define PM3RD_CursorMode_FORMAT_32x32_2BPE_P1 (2 << 2) - #define PM3RD_CursorMode_FORMAT_32x32_2BPE_P2 (3 << 2) - #define PM3RD_CursorMode_FORMAT_32x32_2BPE_P3 (4 << 2) - #define PM3RD_CursorMode_FORMAT_32x32_4BPE_P01 (5 << 2) - #define PM3RD_CursorMode_FORMAT_32x32_4BPE_P23 (6 << 2) - #define PM3RD_CursorMode_TYPE_MS (0 << 4) - #define PM3RD_CursorMode_TYPE_X (1 << 4) - #define PM3RD_CursorMode_REVERSE_PIXEL_ORDER_ENABLE (1 << 6) - #define PM3RD_CursorMode_REVERSE_PIXEL_ORDER_3_COLOR (2 << 6) - #define PM3RD_CursorMode_REVERSE_PIXEL_ORDER_15_COLOR (3 << 6) -#define PM3RD_CursorControl 0x006 - #define PM3RD_CursorControl_DOUBLE_X_ENABLED (1 << 0) - #define PM3RD_CursorControl_DOUBLE_Y_ENABLED (1 << 1) - #define PM3RD_CursorControl_READBACK_POS_ENABLED (1 << 2) - -#define PM3RD_CursorXLow 0x007 -#define PM3RD_CursorXHigh 0x008 -#define PM3RD_CursorYLow 0x009 -#define PM3RD_CursorYHigh 0x00a -#define PM3RD_CursorHotSpotX 0x00b -#define PM3RD_CursorHotSpotY 0x00c -#define PM3RD_OverlayKey 0x00d -#define PM3RD_Pan 0x00e - #define PM3RD_Pan_ENABLE (1 << 0) - #define PM3RD_Pan_GATE_ENABLE (1 << 1) -#define PM3RD_Sense 0x00f - -#define PM3RD_CheckControl 0x018 - #define PM3RD_CheckControl_PIXEL_ENABLED (1 << 0) - #define PM3RD_CheckControl_LUT_ENABLED (1 << 1) -#define PM3RD_CheckPixelRed 0x019 -#define PM3RD_CheckPixelGreen 0x01a -#define PM3RD_CheckPixelBlue 0x01b -#define PM3RD_CheckLUTRed 0x01c -#define PM3RD_CheckLUTGreen 0x01d -#define PM3RD_CheckLUTBlue 0x01e -#define PM3RD_Scratch 0x01f - -#define PM3RD_VideoOverlayControl 0x020 - #define PM3RD_VideoOverlayControl_ENABLE (1 << 0) - #define PM3RD_VideoOverlayControl_MODE_MASK (3 << 1) - #define PM3RD_VideoOverlayControl_MODE_MAINKEY (0 << 1) - #define PM3RD_VideoOverlayControl_MODE_OVERLAYKEY (1 << 1) - #define PM3RD_VideoOverlayControl_MODE_ALWAYS (2 << 1) - #define PM3RD_VideoOverlayControl_MODE_BLEND (3 << 1) - #define PM3RD_VideoOverlayControl_DIRECTCOLOR_ENABLED (1 << 3) - #define PM3RD_VideoOverlayControl_BLENDSRC_MAIN (0 << 4) - #define PM3RD_VideoOverlayControl_BLENDSRC_REGISTER (1 << 4) - #define PM3RD_VideoOverlayControl_KEY_COLOR (0 << 5) - #define PM3RD_VideoOverlayControl_KEY_ALPHA (1 << 5) -#define PM3RD_VideoOverlayXStartLow 0x021 -#define PM3RD_VideoOverlayXStartHigh 0x022 -#define PM3RD_VideoOverlayYStartLow 0x023 -#define PM3RD_VideoOverlayYStartHigh 0x024 -#define PM3RD_VideoOverlayXEndLow 0x025 -#define PM3RD_VideoOverlayXEndHigh 0x026 -#define PM3RD_VideoOverlayYEndLow 0x027 -#define PM3RD_VideoOverlayYEndHigh 0x028 -#define PM3RD_VideoOverlayKeyR 0x029 -#define PM3RD_VideoOverlayKeyG 0x02a -#define PM3RD_VideoOverlayKeyB 0x02b -#define PM3RD_VideoOverlayBlend 0x02c - #define PM3RD_VideoOverlayBlend_FACTOR_0_PERCENT (0 << 6) - #define PM3RD_VideoOverlayBlend_FACTOR_25_PERCENT (1 << 6) - #define PM3RD_VideoOverlayBlend_FACTOR_75_PERCENT (2 << 6) - #define PM3RD_VideoOverlayBlend_FACTOR_100_PERCENT (3 << 6) - -#define PM3RD_DClkSetup1 0x1f0 -#define PM3RD_DClkSetup2 0x1f1 -#define PM3RD_KClkSetup1 0x1f2 -#define PM3RD_KClkSetup2 0x1f3 - -#define PM3RD_DClkControl 0x200 - #define PM3RD_DClkControl_SOURCE_PLL (0 << 4) - #define PM3RD_DClkControl_SOURCE_VSA (1 << 4) - #define PM3RD_DClkControl_SOURCE_VSB (2 << 4) - #define PM3RD_DClkControl_SOURCE_EXT (3 << 4) - #define PM3RD_DClkControl_STATE_RUN (2 << 2) - #define PM3RD_DClkControl_STATE_HIGH (1 << 2) - #define PM3RD_DClkControl_STATE_LOW (0 << 2) - #define PM3RD_DClkControl_LOCKED (1 << 1) - #define PM3RD_DClkControl_NOT_LOCKED (0 << 1) - #define PM3RD_DClkControl_ENABLE (1 << 0) -#define PM3RD_DClk0PreScale 0x201 -#define PM3RD_DClk0FeedbackScale 0x202 -#define PM3RD_DClk0PostScale 0x203 - #define PM3_REF_CLOCK 14318 -#define PM3RD_DClk1PreScale 0x204 -#define PM3RD_DClk1FeedbackScale 0x205 -#define PM3RD_DClk1PostScale 0x206 -#define PM3RD_DClk2PreScale 0x207 -#define PM3RD_DClk2FeedbackScale 0x208 -#define PM3RD_DClk2PostScale 0x209 -#define PM3RD_DClk3PreScale 0x20a -#define PM3RD_DClk3FeedbackScale 0x20b -#define PM3RD_DClk3PostScale 0x20c -#define PM3RD_KClkControl 0x20d - #define PM3RD_KClkControl_ENABLE (1 << 0) - #define PM3RD_KClkControl_NOT_LOCKED (0 << 1) - #define PM3RD_KClkControl_LOCKED (1 << 1) - #define PM3RD_KClkControl_STATE_LOW (0 << 2) - #define PM3RD_KClkControl_STATE_HIGH (1 << 2) - #define PM3RD_KClkControl_STATE_RUN (2 << 2) - #define PM3RD_KClkControl_STATE_LOW_POWER (3 << 2) - #define PM3RD_KClkControl_SOURCE_PCLK (0 << 4) - #define PM3RD_KClkControl_SOURCE_HALF_PCLK (1 << 4) - #define PM3RD_KClkControl_SOURCE_PLL (2 << 4) -#define PM3RD_KClkPreScale 0x20e -#define PM3RD_KClkFeedbackScale 0x20f -#define PM3RD_KClkPostScale 0x210 -#define PM3RD_MClkControl 0x211 - #define PM3RD_MClkControl_ENABLE (1 << 0) - #define PM3RD_MClkControl_NOT_LOCKED (0 << 1) - #define PM3RD_MClkControl_LOCKED (1 << 1) - #define PM3RD_MClkControl_STATE_LOW (0 << 2) - #define PM3RD_MClkControl_STATE_HIGH (1 << 2) - #define PM3RD_MClkControl_STATE_RUN (2 << 2) - #define PM3RD_MClkControl_STATE_LOW_POWER (3 << 2) - #define PM3RD_MClkControl_SOURCE_PCLK (0 << 4) - #define PM3RD_MClkControl_SOURCE_HALF_PCLK (1 << 4) - #define PM3RD_MClkControl_SOURCE_HALF_EXT (3 << 4) - #define PM3RD_MClkControl_SOURCE_EXT (4 << 4) - #define PM3RD_MClkControl_SOURCE_HALF_KCLK (5 << 4) - #define PM3RD_MClkControl_SOURCE_KCLK (6 << 4) -#define PM3RD_MClkPreScale 0x212 -#define PM3RD_MClkFeedbackScale 0x213 -#define PM3RD_MClkPostScale 0x214 -#define PM3RD_SClkControl 0x215 - #define PM3RD_SClkControl_ENABLE (1 << 0) - #define PM3RD_SClkControl_NOT_LOCKED (0 << 1) - #define PM3RD_SClkControl_LOCKED (1 << 1) - #define PM3RD_SClkControl_STATE_LOW (0 << 2) - #define PM3RD_SClkControl_STATE_HIGH (1 << 2) - #define PM3RD_SClkControl_STATE_RUN (2 << 2) - #define PM3RD_SClkControl_STATE_LOW_POWER (3 << 2) - #define PM3RD_SClkControl_SOURCE_PCLK (0 << 4) - #define PM3RD_SClkControl_SOURCE_HALF_PCLK (1 << 4) - #define PM3RD_SClkControl_SOURCE_HALF_EXT (3 << 4) - #define PM3RD_SClkControl_SOURCE_EXT (4 << 4) - #define PM3RD_SClkControl_SOURCE_HALF_KCLK (5 << 4) - #define PM3RD_SClkControl_SOURCE_KCLK (6 << 4) -#define PM3RD_SClkPreScale 0x216 -#define PM3RD_SClkFeedbackScale 0x217 -#define PM3RD_SClkPostScale 0x218 - -#define PM3RD_CursorPalette(p) (0x303 + (p)) -#define PM3RD_CursorPattern(p) (0x400 + (p)) -/****************************************************** -* GLINT Permedia3 Video Streaming Registers (0x5000) * -*******************************************************/ - -#define PM3VSConfiguration 0x5800 - -/********************************************** -* GLINT Permedia3 Core Registers (0x8000+) * -***********************************************/ -#define PM3AALineWidth 0x94c0 -#define PM3AAPointsize 0x94a0 -#define PM3AlphaBlendAlphaMode 0xafa8 -#define PM3AlphaBlendAlphaModeAnd 0xad30 -#define PM3AlphaBlendAlphaModeOr 0xad38 -#define PM3AlphaBlendColorMode 0xafa0 -#define PM3AlphaBlendColorModeAnd 0xacb0 -#define PM3AlphaBlendColorModeOr 0xacb8 -#define PM3AlphaDestColor 0xaf88 -#define PM3AlphaSourceColor 0xaf80 -#define PM3AlphaTestMode 0x8800 -#define PM3AlphaTestModeAnd 0xabf0 -#define PM3AlphaTestModeOr 0xabf8 -#define PM3AntialiasMode 0x8808 -#define PM3AntialiasModeAnd 0xac00 -#define PM3AntialiasModeOr 0xac08 -/* ... */ -#define PM3BackgroundColor 0xb0c8 -/* ... */ -#define PM3ColorDDAMode 0x87e0 -#define PM3ColorDDAModeAnd 0xabe0 -#define PM3ColorDDAModeOr 0xabe8 -#define PM3CommandInterrupt 0xa990 -#define PM3ConstantColorDDA 0xafb0 - #define PM3ConstantColorDDA_R(r) ((r) & 0xff) - #define PM3ConstantColorDDA_G(g) (((g) & 0xff) << 8) - #define PM3ConstantColorDDA_B(b) (((b) & 0xff) << 16) - #define PM3ConstantColorDDA_A(a) (((a) & 0xff) << 24) -#define PM3ContextData 0x8dd0 -#define PM3ContextDump 0x8dc0 -#define PM3ContextRestore 0x8dc8 -#define PM3Continue 0x8058 -#define PM3ContinueNewDom 0x8048 -#define PM3ContinueNewLine 0x8040 -#define PM3ContinueNewSub 0x8050 -#define PM3Count 0x8030 -/* ... */ -#define PM3DeltaControl 0x9350 -#define PM3DeltaControlAnd 0xab20 -#define PM3DeltaControlOr 0xab28 -#define PM3DeltaMode 0x9300 -#define PM3DeltaModeAnd 0xaad0 -#define PM3DeltaModeOr 0xaad8 -/* ... */ -#define PM3DitherMode 0x8818 -#define PM3DitherModeAnd 0xacd0 -#define PM3DitherModeOr 0xacd8 -/* ... */ -#define PM3dXDom 0x8008 -#define PM3dXSub 0x8018 -#define PM3dY 0x8028 -/* ... */ -#define PM3FBBlockColor 0x8ac8 -#define PM3FBBlockColor0 0xb060 -#define PM3FBBlockColor1 0xb068 -#define PM3FBBlockColor2 0xb070 -#define PM3FBBlockColor3 0xb078 -#define PM3FBBlockColorBack 0xb0a0 -#define PM3FBBlockColorBack0 0xb080 -#define PM3FBBlockColorBack1 0xb088 -#define PM3FBBlockColorBack2 0xb090 -#define PM3FBBlockColorBack3 0xb098 -#define PM3FBColor 0x8a98 -#define PM3FBDestReadBufferAddr0 0xae80 -#define PM3FBDestReadBufferAddr1 0xae88 -#define PM3FBDestReadBufferAddr2 0xae90 -#define PM3FBDestReadBufferAddr3 0xae98 -#define PM3FBDestReadBufferOffset0 0xaea0 -#define PM3FBDestReadBufferOffset1 0xaea8 -#define PM3FBDestReadBufferOffset2 0xaeb0 -#define PM3FBDestReadBufferOffset3 0xaeb8 - #define PM3FBDestReadBufferOffset_XOffset(x) ((x) & 0xffff) - #define PM3FBDestReadBufferOffset_YOffset(y) (((y) & 0xffff) << 16) -#define PM3FBDestReadBufferWidth0 0xaec0 -#define PM3FBDestReadBufferWidth1 0xaec8 -#define PM3FBDestReadBufferWidth2 0xaed0 -#define PM3FBDestReadBufferWidth3 0xaed8 - #define PM3FBDestReadBufferWidth_Width(w) ((w) & 0x0fff) - -#define PM3FBDestReadEnables 0xaee8 -#define PM3FBDestReadEnablesAnd 0xad20 -#define PM3FBDestReadEnablesOr 0xad28 - #define PM3FBDestReadEnables_E(e) ((e) & 0xff) - #define PM3FBDestReadEnables_E0 (1 << 0) - #define PM3FBDestReadEnables_E1 (1 << 1) - #define PM3FBDestReadEnables_E2 (1 << 2) - #define PM3FBDestReadEnables_E3 (1 << 3) - #define PM3FBDestReadEnables_E4 (1 << 4) - #define PM3FBDestReadEnables_E5 (1 << 5) - #define PM3FBDestReadEnables_E6 (1 << 6) - #define PM3FBDestReadEnables_E7 (1 << 7) - #define PM3FBDestReadEnables_R(r) (((r) & 0xff) << 8) - #define PM3FBDestReadEnables_R0 (1 << 8) - #define PM3FBDestReadEnables_R1 (1 << 9) - #define PM3FBDestReadEnables_R2 (1 << 10) - #define PM3FBDestReadEnables_R3 (1 << 11) - #define PM3FBDestReadEnables_R4 (1 << 12) - #define PM3FBDestReadEnables_R5 (1 << 13) - #define PM3FBDestReadEnables_R6 (1 << 14) - #define PM3FBDestReadEnables_R7 (1 << 15) - #define PM3FBDestReadEnables_ReferenceAlpha(a) (((a) & 0xff) << 24) - -#define PM3FBDestReadMode 0xaee0 -#define PM3FBDestReadModeAnd 0xac90 -#define PM3FBDestReadModeOr 0xac98 - #define PM3FBDestReadMode_ReadDisable (0 << 0) - #define PM3FBDestReadMode_ReadEnable (1 << 0) - #define PM3FBDestReadMode_StripePitch(sp) (((sp) & 0x7) << 2) - #define PM3FBDestReadMode_StripeHeight(sh) (((sh) & 0x7) << 7) - #define PM3FBDestReadMode_Enable0 (1 << 8) - #define PM3FBDestReadMode_Enable1 (1 << 9) - #define PM3FBDestReadMode_Enable2 (1 << 10) - #define PM3FBDestReadMode_Enable3 (1 << 11) - #define PM3FBDestReadMode_Layout0(l) (((l) & 0x3) << 12) - #define PM3FBDestReadMode_Layout1(l) (((l) & 0x3) << 14) - #define PM3FBDestReadMode_Layout2(l) (((l) & 0x3) << 16) - #define PM3FBDestReadMode_Layout3(l) (((l) & 0x3) << 18) - #define PM3FBDestReadMode_Origin0 (1 << 20) - #define PM3FBDestReadMode_Origin1 (1 << 21) - #define PM3FBDestReadMode_Origin2 (1 << 22) - #define PM3FBDestReadMode_Origin3 (1 << 23) - #define PM3FBDestReadMode_Blocking (1 << 24) - #define PM3FBDestReadMode_UseReadEnabled (1 << 26) - #define PM3FBDestReadMode_AlphaFiltering (1 << 27) - -#define PM3FBHardwareWriteMask 0x8ac0 -#define PM3FBSoftwareWriteMask 0x8820 -#define PM3FBData 0x8aa0 -#define PM3FBSourceData 0x8aa8 -#define PM3FBSourceReadBufferAddr 0xaf08 -#define PM3FBSourceReadBufferOffset 0xaf10 - #define PM3FBSourceReadBufferOffset_XOffset(x) ((x) & 0xffff) - #define PM3FBSourceReadBufferOffset_YOffset(y) (((y) & 0xffff) << 16) -#define PM3FBSourceReadBufferWidth 0xaf18 - #define PM3FBSourceReadBufferWidth_Width(w) ((w) & 0x0fff) -#define PM3FBSourceReadMode 0xaf00 -#define PM3FBSourceReadModeAnd 0xaca0 -#define PM3FBSourceReadModeOr 0xaca8 - #define PM3FBSourceReadMode_ReadDisable (0 << 0) - #define PM3FBSourceReadMode_ReadEnable (1 << 0) - #define PM3FBSourceReadMode_StripePitch(sp) (((sp) & 0x7) << 2) - #define PM3FBSourceReadMode_StripeHeight(sh) (((sh) & 0x7) << 7) - #define PM3FBSourceReadMode_Layout(l) (((l) & 0x3) << 8) - #define PM3FBSourceReadMode_Origin (1 << 10) - #define PM3FBSourceReadMode_Blocking (1 << 11) - #define PM3FBSourceReadMode_UserTexelCoord (1 << 13) - #define PM3FBSourceReadMode_WrapXEnable (1 << 14) - #define PM3FBSourceReadMode_WrapYEnable (1 << 15) - #define PM3FBSourceReadMode_WrapX(w) (((w) & 0xf) << 16) - #define PM3FBSourceReadMode_WrapY(w) (((w) & 0xf) << 20) - #define PM3FBSourceReadMode_ExternalSourceData (1 << 24) -#define PM3FBWriteBufferAddr0 0xb000 -#define PM3FBWriteBufferAddr1 0xb008 -#define PM3FBWriteBufferAddr2 0xb010 -#define PM3FBWriteBufferAddr3 0xb018 - -#define PM3FBWriteBufferOffset0 0xb020 -#define PM3FBWriteBufferOffset1 0xb028 -#define PM3FBWriteBufferOffset2 0xb030 -#define PM3FBWriteBufferOffset3 0xb038 - #define PM3FBWriteBufferOffset_XOffset(x) ((x) & 0xffff) - #define PM3FBWriteBufferOffset_YOffset(y) (((y) & 0xffff) << 16) - -#define PM3FBWriteBufferWidth0 0xb040 -#define PM3FBWriteBufferWidth1 0xb048 -#define PM3FBWriteBufferWidth2 0xb050 -#define PM3FBWriteBufferWidth3 0xb058 - #define PM3FBWriteBufferWidth_Width(w) ((w) & 0x0fff) - -#define PM3FBWriteMode 0x8ab8 -#define PM3FBWriteModeAnd 0xacf0 -#define PM3FBWriteModeOr 0xacf8 - #define PM3FBWriteMode_WriteDisable (0 << 0) - #define PM3FBWriteMode_WriteEnable (1 << 0) - #define PM3FBWriteMode_Replicate (1 << 4) - #define PM3FBWriteMode_OpaqueSpan (1 << 5) - #define PM3FBWriteMode_StripePitch(p) (((p) & 0x7) << 6) - #define PM3FBWriteMode_StripeHeight(h) (((h) & 0x7) << 9) - #define PM3FBWriteMode_Enable0 (1 << 12) - #define PM3FBWriteMode_Enable1 (1 << 13) - #define PM3FBWriteMode_Enable2 (1 << 14) - #define PM3FBWriteMode_Enable3 (1 << 15) - #define PM3FBWriteMode_Layout0(l) (((l) & 0x3) << 16) - #define PM3FBWriteMode_Layout1(l) (((l) & 0x3) << 18) - #define PM3FBWriteMode_Layout2(l) (((l) & 0x3) << 20) - #define PM3FBWriteMode_Layout3(l) (((l) & 0x3) << 22) - #define PM3FBWriteMode_Origin0 (1 << 24) - #define PM3FBWriteMode_Origin1 (1 << 25) - #define PM3FBWriteMode_Origin2 (1 << 26) - #define PM3FBWriteMode_Origin3 (1 << 27) -#define PM3ForegroundColor 0xb0c0 -/* ... */ -#define PM3GIDMode 0xb538 -#define PM3GIDModeAnd 0xb5b0 -#define PM3GIDModeOr 0xb5b8 -/* ... */ -#define PM3LBDestReadBufferAddr 0xb510 -#define PM3LBDestReadBufferOffset 0xb518 -#define PM3LBDestReadEnables 0xb508 -#define PM3LBDestReadEnablesAnd 0xb590 -#define PM3LBDestReadEnablesOr 0xb598 -#define PM3LBDestReadMode 0xb500 -#define PM3LBDestReadModeAnd 0xb580 -#define PM3LBDestReadModeOr 0xb588 - #define PM3LBDestReadMode_Disable (0 << 0) - #define PM3LBDestReadMode_Enable (1 << 0) - #define PM3LBDestReadMode_StripePitch(p) (((p) & 0x7) << 2) - #define PM3LBDestReadMode_StripeHeight(h) (((h) & 0x7) << 5) - #define PM3LBDestReadMode_Layout (1 << 8) - #define PM3LBDestReadMode_Origin (1 << 9) - #define PM3LBDestReadMode_UserReadEnables (1 << 10) - #define PM3LBDestReadMode_Packed16 (1 << 11) - #define PM3LBDestReadMode_Width(w) (((w) & 0xfff) << 12) -#define PM3LBReadFormat 0x8888 - #define PM3LBReadFormat_DepthWidth(w) (((w) & 0x3) << 0) - #define PM3LBReadFormat_StencilWidth(w) (((w) & 0xf) << 2) - #define PM3LBReadFormat_StencilPosition(p) (((p) & 0x1f) << 6) - #define PM3LBReadFormat_FCPWidth(w) (((w) & 0xf) << 11) - #define PM3LBReadFormat_FCPPosition(p) (((p) & 0x1f) << 15) - #define PM3LBReadFormat_GIDWidth(w) (((w) & 0x7) << 20) - #define PM3LBReadFormat_GIDPosition(p) (((p) & 0x1f) << 23) -#define PM3LBSourceReadBufferAddr 0xb528 -#define PM3LBSourceReadBufferOffset 0xb530 -#define PM3LBSourceReadMode 0xb520 -#define PM3LBSourceReadModeAnd 0xb5a0 -#define PM3LBSourceReadModeOr 0xb5a8 - #define PM3LBSourceReadMode_Enable (1 << 0) - #define PM3LBSourceReadMode_StripePitch(p) (((p) & 0x7) << 2) - #define PM3LBSourceReadMode_StripeHeight(h) (((h) & 0x7) << 5) - #define PM3LBSourceReadMode_Layout (1 << 8) - #define PM3LBSourceReadMode_Origin (1 << 9) - #define PM3LBSourceReadMode_Packed16 (1 << 10) - #define PM3LBSourceReadMode_Width(w) (((w) & 0xfff) << 11) -#define PM3LBStencil 0x88a8 -#define PM3LBWriteBufferAddr 0xb540 -#define PM3LBWriteBufferOffset 0xb548 -#define PM3LBWriteFormat 0x88c8 - #define PM3LBWriteFormat_DepthWidth(w) (((w) & 0x3) << 0) - #define PM3LBWriteFormat_StencilWidth(w) (((w) & 0xf) << 2) - #define PM3LBWriteFormat_StencilPosition(p) (((p) & 0x1f) << 6) - #define PM3LBWriteFormat_GIDWidth(w) (((w) & 0x7) << 20) - #define PM3LBWriteFormat_GIDPosition(p) (((p) & 0x1f) << 23) -#define PM3LBWriteMode 0x88c0 -#define PM3LBWriteModeAnd 0xac80 -#define PM3LBWriteModeOr 0xac88 - #define PM3LBWriteMode_WriteDisable (0 << 0) - #define PM3LBWriteMode_WriteEnable (1 << 0) - #define PM3LBWriteMode_StripePitch(p) (((p) & 0x7) << 3) - #define PM3LBWriteMode_StripeHeight(h) (((h) & 0x7) << 6) - #define PM3LBWriteMode_Layout (1 << 9) - #define PM3LBWriteMode_Origin (1 << 10) - #define PM3LBWriteMode_Packed16 (1 << 11) - #define PM3LBWriteMode_Width(w) (((w) & 0xfff) << 12) -/* ... */ -#define PM3LineStippleMode 0x81a8 -#define PM3LineStippleModeAnd 0xabc0 -#define PM3LineStippleModeOr 0xabc8 -#define PM3LoadLineStippleCounters 0x81b0 -/* ... */ -#define PM3LogicalOpMode 0x8828 -#define PM3LogicalOpModeAnd 0xace0 -#define PM3LogicalOpModeOr 0xace8 - #define PM3LogicalOpMode_Disable (0 << 0) - #define PM3LogicalOpMode_Enable (1 << 0) - #define PM3LogicalOpMode_LogicOp(op) (((op) & 0xf) << 1) - #define PM3LogicalOpMode_UseConstantWriteData_Disable (0 << 5) - #define PM3LogicalOpMode_UseConstantWriteData_Enable (1 << 5) - #define PM3LogicalOpMode_Background_Disable (0 << 6) - #define PM3LogicalOpMode_Background_Enable (1 << 6) - #define PM3LogicalOpMode_Background_LogicOp(op) (((op) & 0xf) << 7) - #define PM3LogicalOpMode_UseConstantSource_Disable (0 << 11) - #define PM3LogicalOpMode_UseConstantSource_Enable (1 << 11) -/* ... */ -#define PM3LUT 0x8e80 -#define PM3LUTAddress 0x84d0 -#define PM3LUTData 0x84c8 -#define PM3LUTIndex 0x84c0 -#define PM3LUTMode 0xb378 -#define PM3LUTModeAnd 0xad70 -#define PM3LUTModeOr 0xad78 -#define PM3LUTTransfer 0x84d8 -/* ... */ -#define PM3PixelSize 0x80c0 - #define PM3PixelSize_GLOBAL_32BIT (0 << 0) - #define PM3PixelSize_GLOBAL_16BIT (1 << 0) - #define PM3PixelSize_GLOBAL_8BIT (2 << 0) - #define PM3PixelSize_RASTERIZER_32BIT (0 << 2) - #define PM3PixelSize_RASTERIZER_16BIT (1 << 2) - #define PM3PixelSize_RASTERIZER_8BIT (2 << 2) - #define PM3PixelSize_SCISSOR_AND_STIPPLE_32BIT (0 << 4) - #define PM3PixelSize_SCISSOR_AND_STIPPLE_16BIT (1 << 4) - #define PM3PixelSize_SCISSOR_AND_STIPPLE_8BIT (2 << 4) - #define PM3PixelSize_TEXTURE_32BIT (0 << 6) - #define PM3PixelSize_TEXTURE_16BIT (1 << 6) - #define PM3PixelSize_TEXTURE_8BIT (2 << 6) - #define PM3PixelSize_LUT_32BIT (0 << 8) - #define PM3PixelSize_LUT_16BIT (1 << 8) - #define PM3PixelSize_LUT_8BIT (2 << 8) - #define PM3PixelSize_FRAMEBUFFER_32BIT (0 << 10) - #define PM3PixelSize_FRAMEBUFFER_16BIT (1 << 10) - #define PM3PixelSize_FRAMEBUFFER_8BIT (2 << 10) - #define PM3PixelSize_LOGICAL_OP_32BIT (0 << 12) - #define PM3PixelSize_LOGICAL_OP_16BIT (1 << 12) - #define PM3PixelSize_LOGICAL_OP_8BIT (2 << 12) - #define PM3PixelSize_LOCALBUFFER_32BIT (0 << 14) - #define PM3PixelSize_LOCALBUFFER_16BIT (1 << 14) - #define PM3PixelSize_LOCALBUFFER_8BIT (2 << 14) - #define PM3PixelSize_SETUP_32BIT (0 << 16) - #define PM3PixelSize_SETUP_16BIT (1 << 16) - #define PM3PixelSize_SETUP_8BIT (2 << 16) - #define PM3PixelSize_GLOBAL (0 << 31) - #define PM3PixelSize_INDIVIDUAL (1 << 31) -/* ... */ -#define PM3Render 0x8038 - #define PM3Render_AreaStipple_Disable (0 << 0) - #define PM3Render_AreaStipple_Enable (1 << 0) - #define PM3Render_LineStipple_Disable (0 << 1) - #define PM3Render_LineStipple_Enable (1 << 1) - #define PM3Render_ResetLine_Disable (0 << 2) - #define PM3Render_ResetLine_Enable (1 << 2) - #define PM3Render_FastFill_Disable (0 << 3) - #define PM3Render_FastFill_Enable (1 << 3) - #define PM3Render_Primitive_Line (0 << 6) - #define PM3Render_Primitive_Trapezoid (1 << 6) - #define PM3Render_Primitive_Point (2 << 6) - #define PM3Render_Antialias_Disable (0 << 8) - #define PM3Render_Antialias_Enable (1 << 8) - #define PM3Render_Antialias_SubPixelRes_4x4 (0 << 9) - #define PM3Render_Antialias_SubPixelRes_8x8 (1 << 9) - #define PM3Render_UsePointTable_Disable (0 << 10) - #define PM3Render_UsePointTable_Enable (1 << 10) - #define PM3Render_SyncOnbitMask_Disable (0 << 11) - #define PM3Render_SyncOnBitMask_Enable (1 << 11) - #define PM3Render_SyncOnHostData_Disable (0 << 12) - #define PM3Render_SyncOnHostData_Enable (1 << 12) - #define PM3Render_Texture_Disable (0 << 13) - #define PM3Render_Texture_Enable (1 << 13) - #define PM3Render_Fog_Disable (0 << 14) - #define PM3Render_Fog_Enable (1 << 14) - #define PM3Render_Coverage_Disable (0 << 15) - #define PM3Render_Coverage_Enable (1 << 15) - #define PM3Render_SubPixelCorrection_Disable (0 << 16) - #define PM3Render_SubPixelCorrection_Enable (1 << 16) - #define PM3Render_SpanOperation_Disable (0 << 18) - #define PM3Render_SpanOperation_Enable (1 << 18) - #define PM3Render_FBSourceRead_Disable (0 << 27) - #define PM3Render_FBSourceRead_Enable (1 << 27) -#define PM3RasterizerMode 0x80a0 -#define PM3RasterizerModeAnd 0xaba0 -#define PM3RasterizerModeOr 0xaba8 -#define PM3RectangleHeight 0x94e0 -#define PM3RepeatLine 0x9328 -#define PM3ResetPickResult 0x8c20 -#define PM3RLEMask 0x8c48 -#define PM3RouterMode 0x8840 -#define PM3RStart 0x8780 -#define PM3S1Start 0x8400 -#define PM3aveLineStippleCounters 0x81c0 -#define PM3ScissorMaxXY 0x8190 -#define PM3ScissorMinXY 0x8188 -#define PM3ScissorMode 0x8180 -#define PM3ScissorModeAnd 0xabb0 -#define PM3ScissorModeOr 0xabb8 -#define PM3ScreenSize 0x8198 -#define PM3Security 0x8908 -#define PM3SetLogicalTexturePage 0xb360 -#define PM3SizeOfFramebuffer 0xb0a8 -#define PM3SStart 0x8388 -#define PM3StartXDom 0x8000 -#define PM3StartXSub 0x8010 -#define PM3StartY 0x8020 -/* ... */ -#define PM3SpanColorMask 0x8168 -/* ... */ -#define PM3TextureApplicationMode 0x8680 -#define PM3TextureApplicationModeAnd 0xac50 -#define PM3TextureApplicationModeOr 0xac58 -#define PM3TextureBaseAddr 0x8500 -#define PM3TextureCacheControl 0x8490 -#define PM3TextureChromaLower0 0x84f0 -#define PM3TextureChromaLower1 0x8608 -#define PM3TextureChromaUpper0 0x84e8 -#define PM3TextureChromaUpper1 0x8600 -#define PM3TextureCompositeAlphaMode0 0xb310 -#define PM3TextureCompositeAlphaMode0And 0xb390 -#define PM3TextureCompositeAlphaMode0Or 0xb398 -#define PM3TextureCompositeAlphaMode1 0xb320 -#define PM3TextureCompositeAlphaMode1And 0xb3b0 -#define PM3TextureCompositeAlphaMode1Or 0xb3b8 -#define PM3TextureCompositeColorMode0 0xb308 -#define PM3TextureCompositeColorMode0And 0xb380 -#define PM3TextureCompositeColorMode0Or 0xb388 -#define PM3TextureCompositeColorMode1 0xb318 -#define PM3TextureCompositeColorMode1And 0xb3a0 -#define PM3TextureCompositeColorMode1Or 0xb3a8 -#define PM3TextureCompositeFactor0 0xb328 -#define PM3TextureCompositeFactor1 0xb330 -#define PM3TextureCompositeMode 0xb300 -#define PM3TextureCoordMode 0x8380 -#define PM3TextureCoordModeAnd 0xac20 -#define PM3TextureCoordModeOr 0xac28 -#define PM3TextureData 0x88e8 -/* -#define PM3TextureDownloadControl 0x0108 -*/ -#define PM3TextureDownloadOffset 0x88f0 -#define PM3TextureEnvColor 0x8688 -#define PM3TextureFilterMode 0x84e0 -#define PM3TextureFilterModeAnd 0xad50 -#define PM3TextureFilterModeOr 0xad58 -#define PM3TextureIndexMode0 0xb338 -#define PM3TextureIndexMode0And 0xb3c0 -#define PM3TextureIndexMode0Or 0xb3c8 -#define PM3TextureIndexMode1 0xb340 -#define PM3TextureIndexMode1And 0xb3d0 -#define PM3TextureIndexMode1Or 0xb3d8 -/* ... */ -#define PM3TextureMapSize 0xb428 -#define PM3TextureMapWidth0 0x8580 -#define PM3TextureMapWidth1 0x8588 - #define PM3TextureMapWidth_Width(w) (((w) & 0xfff) << 0) - #define PM3TextureMapWidth_BorderLayout (1 << 12) - #define PM3TextureMapWidth_Layout_Linear (0 << 13) - #define PM3TextureMapWidth_Layout_Patch64 (1 << 13) - #define PM3TextureMapWidth_Layout_Patch32_2 (2 << 13) - #define PM3TextureMapWidth_Layout_Patch2 (3 << 13) - #define PM3TextureMapWidth_HostTexture (1 << 15) -#define PM3TextureReadMode0 0xb400 -#define PM3TextureReadMode0And 0xac30 -#define PM3TextureReadMode0Or 0xac38 -#define PM3TextureReadMode1 0xb408 -#define PM3TextureReadMode1And 0xad40 -#define PM3TextureReadMode1Or 0xad48 -/* ... */ -#define PM3WaitForCompletion 0x80b8 -#define PM3Window 0x8980 - #define PM3Window_ForceLBUpdate (1 << 3) - #define PM3Window_LBUpdateSource (1 << 4) - #define PM3Window_FrameCount(c) (((c) & 0xff) << 9) - #define PM3Window_StencilFCP (1 << 17) - #define PM3Window_DepthFCP (1 << 18) - #define PM3Window_OverrideWriteFiltering (1 << 19) -#define PM3WindowAnd 0xab80 -#define PM3WindowOr 0xab88 -#define PM3WindowOrigin 0x81c8 -#define PM3XBias 0x9480 -#define PM3YBias 0x9488 -#define PM3YLimits 0x80a8 -#define PM3UVMode 0x8f00 -#define PM3ZFogBias 0x86b8 -#define PM3ZStart 0xadd8 -#define PM3ZStartL 0x89b8 -#define PM3ZStartU 0x89b0 - - -/********************************************** -* GLINT Permedia3 2D setup Unit * -***********************************************/ -#define PM3Config2D 0xb618 - #define PM3Config2D_OpaqueSpan (1 << 0) - #define PM3Config2D_MultiRXBlit (1 << 1) - #define PM3Config2D_UserScissorEnable (1 << 2) - #define PM3Config2D_FBDestReadEnable (1 << 3) - #define PM3Config2D_AlphaBlendEnable (1 << 4) - #define PM3Config2D_DitherEnable (1 << 5) - #define PM3Config2D_ForegroundROPEnable (1 << 6) - #define PM3Config2D_ForegroundROP(rop) (((rop) & 0xf) << 7) - #define PM3Config2D_BackgroundROPEnable (1 << 11) - #define PM3Config2D_BackgroundROP(rop) (((rop) & 0xf) << 12) - #define PM3Config2D_UseConstantSource (1 << 16) - #define PM3Config2D_FBWriteEnable (1 << 17) - #define PM3Config2D_Blocking (1 << 18) - #define PM3Config2D_ExternalSourceData (1 << 19) - #define PM3Config2D_LUTModeEnable (1 << 20) -#define PM3DownloadGlyphwidth 0xb658 - #define PM3DownloadGlyphwidth_GlyphWidth(gw) ((gw) & 0xffff) -#define PM3DownloadTarget 0xb650 - #define PM3DownloadTarget_TagName(tag) ((tag) & 0x1fff) -#define PM3GlyphData 0xb660 -#define PM3GlyphPosition 0xb608 - #define PM3GlyphPosition_XOffset(x) ((x) & 0xffff) - #define PM3GlyphPosition_YOffset(y) (((y) & 0xffff) << 16) -#define PM3Packed4Pixels 0xb668 -#define PM3Packed8Pixels 0xb630 -#define PM3Packed16Pixels 0xb638 -#define PM3RectanglePosition 0xb600 - #define PM3RectanglePosition_XOffset(x) ((x) & 0xffff) - #define PM3RectanglePosition_YOffset(y) (((y) & 0xffff) << 16) -#define PM3Render2D 0xb640 - #define PM3Render2D_Width(w) ((w) & 0x0fff) - #define PM3Render2D_Operation_Normal (0 << 12) - #define PM3Render2D_Operation_SyncOnHostData (1 << 12) - #define PM3Render2D_Operation_SyncOnBitMask (2 << 12) - #define PM3Render2D_Operation_PatchOrderRendering (3 << 12) - #define PM3Render2D_FBSourceReadEnable (1 << 14) - #define PM3Render2D_SpanOperation (1 << 15) - #define PM3Render2D_Height(h) (((h) & 0x0fff) << 16) - #define PM3Render2D_XPositive (1 << 28) - #define PM3Render2D_YPositive (1 << 29) - #define PM3Render2D_AreaStippleEnable (1 << 30) - #define PM3Render2D_TextureEnable (1 << 31) -#define PM3Render2DGlyph 0xb648 - #define PM3Render2DGlyph_Width(w) ((w) & 0x7f) - #define PM3Render2DGlyph_Height(h) (((h) & 0x7f) << 7) - #define PM3Render2DGlyph_XOffset(x) (((x) & 0x1ff) << 14) - #define PM3Render2DGlyph_YOffset(y) (((y) & 0x1ff) << 23) -#define PM3RenderPatchOffset 0xb610 - #define PM3RenderPatchOffset_XOffset(x) ((x) & 0xffff) - #define PM3RenderPatchOffset_YOffset(y) (((y) & 0xffff) << 16) -#define PM3RLCount 0xb678 - #define PM3RLCount_Count(c) ((c) & 0x0fff) -#define PM3RLData 0xb670 - -/********************************************** -* GLINT Permedia3 Alias Register * -***********************************************/ -#define PM3FillBackgroundColor 0x8330 -#define PM3FillConfig2D0 0x8338 -#define PM3FillConfig2D1 0x8360 - #define PM3FillConfig2D_OpaqueSpan (1 << 0) - #define PM3FillConfig2D_MultiRXBlit (1 << 1) - #define PM3FillConfig2D_UserScissorEnable (1 << 2) - #define PM3FillConfig2D_FBDestReadEnable (1 << 3) - #define PM3FillConfig2D_AlphaBlendEnable (1 << 4) - #define PM3FillConfig2D_DitherEnable (1 << 5) - #define PM3FillConfig2D_ForegroundROPEnable (1 << 6) - #define PM3FillConfig2D_ForegroundROP(rop) (((rop) & 0xf) << 7) - #define PM3FillConfig2D_BackgroundROPEnable (1 << 11) - #define PM3FillConfig2D_BackgroundROP(rop) (((rop) & 0xf) << 12) - #define PM3FillConfig2D_UseConstantSource (1 << 16) - #define PM3FillConfig2D_FBWriteEnable (1 << 17) - #define PM3FillConfig2D_Blocking (1 << 18) - #define PM3FillConfig2D_ExternalSourceData (1 << 19) - #define PM3FillConfig2D_LUTModeEnable (1 << 20) -#define PM3FillFBDestReadBufferAddr 0x8310 -#define PM3FillFBSourceReadBufferAddr 0x8308 -#define PM3FillFBSourceReadBufferOffset 0x8340 - #define PM3FillFBSourceReadBufferOffset_XOffset(x) ((x) & 0xffff) - #define PM3FillFBSourceReadBufferOffset_YOffset(y) \ - (((y) & 0xffff) << 16) -#define PM3FillFBWriteBufferAddr 0x8300 -#define PM3FillForegroundColor0 0x8328 -#define PM3FillForegroundColor1 0x8358 -#define PM3FillGlyphPosition 0x8368 - #define PM3FillGlyphPosition_XOffset(x) ((x) & 0xffff) - #define PM3FillGlyphPosition_YOffset(y) (((y) & 0xffff) << 16) -#define PM3FillRectanglePosition 0x8348 - #define PM3FillRectanglePosition_XOffset(x) ((x) & 0xffff) - #define PM3FillRectanglePosition_YOffset(y) (((y) & 0xffff) << 16) - -/* a few more useful registers & regs value... */ -#define PM3Sync 0x8c40 - #define PM3Sync_Tag 0x188 -#define PM3FilterMode 0x8c00 - #define PM3FilterModeSync 0x400 -#define PM3OutputFifo 0x2000 -#define PM3StatisticMode 0x8c08 -#define PM3AreaStippleMode 0x81a0 -#define AreaStipplePattern_indexed(i) (0x8200 + ((i) * 0x8)) - -#define PM3DepthMode 0x89a0 -#define PM3StencilMode 0x8988 -#define PM3StencilData 0x8990 -#define PM3TextureReadMode 0x8670 -#define PM3FogMode 0x8690 -#define PM3ChromaTestMode 0x8f18 -#define PM3YUVMode 0x8f00 -#define PM3BitMaskPattern 0x8068 - -/* ***************************** */ -/* ***** pm3fb IOCTL const ***** */ -/* ***************************** */ -#define PM3FBIO_RESETCHIP 0x504D33FF /* 'PM3\377' */ - -/* ***************************************** */ -/* ***** pm3fb useful define and macro ***** */ -/* ***************************************** */ - -/* fifo size in chip */ -#define PM3_FIFO_SIZE 120 -#define PM3_REGS_SIZE 0x10000 -#define PM3_MAX_PIXCLOCK 300000 - -#endif /* PM3FB_H */ diff --git a/ANDROID_3.4.5/include/video/pmag-ba-fb.h b/ANDROID_3.4.5/include/video/pmag-ba-fb.h deleted file mode 100644 index fceb6c0f..00000000 --- a/ANDROID_3.4.5/include/video/pmag-ba-fb.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * linux/include/video/pmag-ba-fb.h - * - * TURBOchannel PMAG-BA Color Frame Buffer (CFB) card support, - * Copyright (C) 1999, 2000, 2001 by - * Michael Engel <engel@unix-ag.org>, - * Karsten Merker <merker@linuxtag.org> - * Copyright (c) 2005 Maciej W. Rozycki - * - * This file is subject to the terms and conditions of the GNU General - * Public License. See the file COPYING in the main directory of this - * archive for more details. - */ - -/* IOmem resource offsets. */ -#define PMAG_BA_FBMEM 0x000000 /* frame buffer */ -#define PMAG_BA_BT459 0x200000 /* Bt459 RAMDAC */ -#define PMAG_BA_IRQ 0x300000 /* IRQ acknowledge */ -#define PMAG_BA_ROM 0x380000 /* REX option ROM */ -#define PMAG_BA_BT438 0x380000 /* Bt438 clock chip reset */ -#define PMAG_BA_SIZE 0x400000 /* address space size */ - -/* Bt459 register offsets, byte-wide registers. */ -#define BT459_ADDR_LO 0x0 /* address low */ -#define BT459_ADDR_HI 0x4 /* address high */ -#define BT459_DATA 0x8 /* data window register */ -#define BT459_CMAP 0xc /* color map window register */ diff --git a/ANDROID_3.4.5/include/video/pmagb-b-fb.h b/ANDROID_3.4.5/include/video/pmagb-b-fb.h deleted file mode 100644 index 7539b908..00000000 --- a/ANDROID_3.4.5/include/video/pmagb-b-fb.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * linux/include/video/pmagb-b-fb.h - * - * TURBOchannel PMAGB-B Smart Frame Buffer (SFB) card support, - * Copyright (C) 1999, 2000, 2001 by - * Michael Engel <engel@unix-ag.org> and - * Karsten Merker <merker@linuxtag.org> - * Copyright (c) 2005 Maciej W. Rozycki - * - * This file is subject to the terms and conditions of the GNU General - * Public License. See the file COPYING in the main directory of this - * archive for more details. - */ - -/* IOmem resource offsets. */ -#define PMAGB_B_ROM 0x000000 /* REX option ROM */ -#define PMAGB_B_SFB 0x100000 /* SFB ASIC */ -#define PMAGB_B_GP0 0x140000 /* general purpose output 0 */ -#define PMAGB_B_GP1 0x180000 /* general purpose output 1 */ -#define PMAGB_B_BT459 0x1c0000 /* Bt459 RAMDAC */ -#define PMAGB_B_FBMEM 0x200000 /* frame buffer */ -#define PMAGB_B_SIZE 0x400000 /* address space size */ - -/* IOmem register offsets. */ -#define SFB_REG_VID_HOR 0x64 /* video horizontal setup */ -#define SFB_REG_VID_VER 0x68 /* video vertical setup */ -#define SFB_REG_VID_BASE 0x6c /* video base address */ -#define SFB_REG_TCCLK_COUNT 0x78 /* TURBOchannel clock count */ -#define SFB_REG_VIDCLK_COUNT 0x7c /* video clock count */ - -/* Video horizontal setup register constants. All bits are r/w. */ -#define SFB_VID_HOR_BP_SHIFT 0x15 /* back porch */ -#define SFB_VID_HOR_BP_MASK 0x7f -#define SFB_VID_HOR_SYN_SHIFT 0x0e /* sync pulse */ -#define SFB_VID_HOR_SYN_MASK 0x7f -#define SFB_VID_HOR_FP_SHIFT 0x09 /* front porch */ -#define SFB_VID_HOR_FP_MASK 0x1f -#define SFB_VID_HOR_PIX_SHIFT 0x00 /* active video */ -#define SFB_VID_HOR_PIX_MASK 0x1ff - -/* Video vertical setup register constants. All bits are r/w. */ -#define SFB_VID_VER_BP_SHIFT 0x16 /* back porch */ -#define SFB_VID_VER_BP_MASK 0x3f -#define SFB_VID_VER_SYN_SHIFT 0x10 /* sync pulse */ -#define SFB_VID_VER_SYN_MASK 0x3f -#define SFB_VID_VER_FP_SHIFT 0x0b /* front porch */ -#define SFB_VID_VER_FP_MASK 0x1f -#define SFB_VID_VER_SL_SHIFT 0x00 /* active scan lines */ -#define SFB_VID_VER_SL_MASK 0x7ff - -/* Video base address register constants. All bits are r/w. */ -#define SFB_VID_BASE_MASK 0x1ff /* video base row address */ - -/* Bt459 register offsets, byte-wide registers. */ -#define BT459_ADDR_LO 0x0 /* address low */ -#define BT459_ADDR_HI 0x4 /* address high */ -#define BT459_DATA 0x8 /* data window register */ -#define BT459_CMAP 0xc /* color map window register */ diff --git a/ANDROID_3.4.5/include/video/pxa168fb.h b/ANDROID_3.4.5/include/video/pxa168fb.h deleted file mode 100644 index 8c2f385a..00000000 --- a/ANDROID_3.4.5/include/video/pxa168fb.h +++ /dev/null @@ -1,125 +0,0 @@ -/* - * linux/arch/arm/mach-mmp/include/mach/pxa168fb.h - * - * Copyright (C) 2009 Marvell International Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_MACH_PXA168FB_H -#define __ASM_MACH_PXA168FB_H - -#include <linux/fb.h> -#include <linux/interrupt.h> - -/* Dumb interface */ -#define PIN_MODE_DUMB_24 0 -#define PIN_MODE_DUMB_18_SPI 1 -#define PIN_MODE_DUMB_18_GPIO 2 -#define PIN_MODE_DUMB_16_SPI 3 -#define PIN_MODE_DUMB_16_GPIO 4 -#define PIN_MODE_DUMB_12_SPI_GPIO 5 -#define PIN_MODE_SMART_18_SPI 6 -#define PIN_MODE_SMART_16_SPI 7 -#define PIN_MODE_SMART_8_SPI_GPIO 8 - -/* Dumb interface pin allocation */ -#define DUMB_MODE_RGB565 0 -#define DUMB_MODE_RGB565_UPPER 1 -#define DUMB_MODE_RGB666 2 -#define DUMB_MODE_RGB666_UPPER 3 -#define DUMB_MODE_RGB444 4 -#define DUMB_MODE_RGB444_UPPER 5 -#define DUMB_MODE_RGB888 6 - -/* default fb buffer size WVGA-32bits */ -#define DEFAULT_FB_SIZE (800 * 480 * 4) - -/* - * Buffer pixel format - * bit0 is for rb swap. - * bit12 is for Y UorV swap - */ -#define PIX_FMT_RGB565 0 -#define PIX_FMT_BGR565 1 -#define PIX_FMT_RGB1555 2 -#define PIX_FMT_BGR1555 3 -#define PIX_FMT_RGB888PACK 4 -#define PIX_FMT_BGR888PACK 5 -#define PIX_FMT_RGB888UNPACK 6 -#define PIX_FMT_BGR888UNPACK 7 -#define PIX_FMT_RGBA888 8 -#define PIX_FMT_BGRA888 9 -#define PIX_FMT_YUV422PACK 10 -#define PIX_FMT_YVU422PACK 11 -#define PIX_FMT_YUV422PLANAR 12 -#define PIX_FMT_YVU422PLANAR 13 -#define PIX_FMT_YUV420PLANAR 14 -#define PIX_FMT_YVU420PLANAR 15 -#define PIX_FMT_PSEUDOCOLOR 20 -#define PIX_FMT_UYVY422PACK (0x1000|PIX_FMT_YUV422PACK) - -/* - * PXA LCD controller private state. - */ -struct pxa168fb_info { - struct device *dev; - struct clk *clk; - struct fb_info *info; - - void __iomem *reg_base; - dma_addr_t fb_start_dma; - u32 pseudo_palette[16]; - - int pix_fmt; - unsigned is_blanked:1; - unsigned panel_rbswap:1; - unsigned active:1; -}; - -/* - * PXA fb machine information - */ -struct pxa168fb_mach_info { - char id[16]; - - int num_modes; - struct fb_videomode *modes; - - /* - * Pix_fmt - */ - unsigned pix_fmt; - - /* - * I/O pin allocation. - */ - unsigned io_pin_allocation_mode:4; - - /* - * Dumb panel -- assignment of R/G/B component info to the 24 - * available external data lanes. - */ - unsigned dumb_mode:4; - unsigned panel_rgb_reverse_lanes:1; - - /* - * Dumb panel -- GPIO output data. - */ - unsigned gpio_output_mask:8; - unsigned gpio_output_data:8; - - /* - * Dumb panel -- configurable output signal polarity. - */ - unsigned invert_composite_blank:1; - unsigned invert_pix_val_ena:1; - unsigned invert_pixclock:1; - unsigned panel_rbswap:1; - unsigned active:1; - unsigned enable_lcd:1; -}; - -#endif /* __ASM_MACH_PXA168FB_H */ diff --git a/ANDROID_3.4.5/include/video/radeon.h b/ANDROID_3.4.5/include/video/radeon.h deleted file mode 100644 index 56b188ab..00000000 --- a/ANDROID_3.4.5/include/video/radeon.h +++ /dev/null @@ -1,1993 +0,0 @@ -#ifndef _RADEON_H -#define _RADEON_H - - -#define RADEON_REGSIZE 0x4000 - - -#define MM_INDEX 0x0000 -#define MM_DATA 0x0004 -#define BUS_CNTL 0x0030 -#define HI_STAT 0x004C -#define BUS_CNTL1 0x0034 -#define I2C_CNTL_1 0x0094 -#define CNFG_CNTL 0x00E0 -#define CNFG_MEMSIZE 0x00F8 -#define CNFG_APER_0_BASE 0x0100 -#define CNFG_APER_1_BASE 0x0104 -#define CNFG_APER_SIZE 0x0108 -#define CNFG_REG_1_BASE 0x010C -#define CNFG_REG_APER_SIZE 0x0110 -#define PAD_AGPINPUT_DELAY 0x0164 -#define PAD_CTLR_STRENGTH 0x0168 -#define PAD_CTLR_UPDATE 0x016C -#define PAD_CTLR_MISC 0x0aa0 -#define AGP_CNTL 0x0174 -#define BM_STATUS 0x0160 -#define CAP0_TRIG_CNTL 0x0950 -#define CAP1_TRIG_CNTL 0x09c0 -#define VIPH_CONTROL 0x0C40 -#define VENDOR_ID 0x0F00 -#define DEVICE_ID 0x0F02 -#define COMMAND 0x0F04 -#define STATUS 0x0F06 -#define REVISION_ID 0x0F08 -#define REGPROG_INF 0x0F09 -#define SUB_CLASS 0x0F0A -#define BASE_CODE 0x0F0B -#define CACHE_LINE 0x0F0C -#define LATENCY 0x0F0D -#define HEADER 0x0F0E -#define BIST 0x0F0F -#define REG_MEM_BASE 0x0F10 -#define REG_IO_BASE 0x0F14 -#define REG_REG_BASE 0x0F18 -#define ADAPTER_ID 0x0F2C -#define BIOS_ROM 0x0F30 -#define CAPABILITIES_PTR 0x0F34 -#define INTERRUPT_LINE 0x0F3C -#define INTERRUPT_PIN 0x0F3D -#define MIN_GRANT 0x0F3E -#define MAX_LATENCY 0x0F3F -#define ADAPTER_ID_W 0x0F4C -#define PMI_CAP_ID 0x0F50 -#define PMI_NXT_CAP_PTR 0x0F51 -#define PMI_PMC_REG 0x0F52 -#define PM_STATUS 0x0F54 -#define PMI_DATA 0x0F57 -#define AGP_CAP_ID 0x0F58 -#define AGP_STATUS 0x0F5C -#define AGP_COMMAND 0x0F60 -#define AIC_CTRL 0x01D0 -#define AIC_STAT 0x01D4 -#define AIC_PT_BASE 0x01D8 -#define AIC_LO_ADDR 0x01DC -#define AIC_HI_ADDR 0x01E0 -#define AIC_TLB_ADDR 0x01E4 -#define AIC_TLB_DATA 0x01E8 -#define DAC_CNTL 0x0058 -#define DAC_CNTL2 0x007c -#define CRTC_GEN_CNTL 0x0050 -#define MEM_CNTL 0x0140 -#define MC_CNTL 0x0140 -#define EXT_MEM_CNTL 0x0144 -#define MC_TIMING_CNTL 0x0144 -#define MC_AGP_LOCATION 0x014C -#define MEM_IO_CNTL_A0 0x0178 -#define MEM_REFRESH_CNTL 0x0178 -#define MEM_INIT_LATENCY_TIMER 0x0154 -#define MC_INIT_GFX_LAT_TIMER 0x0154 -#define MEM_SDRAM_MODE_REG 0x0158 -#define AGP_BASE 0x0170 -#define MEM_IO_CNTL_A1 0x017C -#define MC_READ_CNTL_AB 0x017C -#define MEM_IO_CNTL_B0 0x0180 -#define MC_INIT_MISC_LAT_TIMER 0x0180 -#define MEM_IO_CNTL_B1 0x0184 -#define MC_IOPAD_CNTL 0x0184 -#define MC_DEBUG 0x0188 -#define MC_STATUS 0x0150 -#define MEM_IO_OE_CNTL 0x018C -#define MC_CHIP_IO_OE_CNTL_AB 0x018C -#define MC_FB_LOCATION 0x0148 -#define HOST_PATH_CNTL 0x0130 -#define MEM_VGA_WP_SEL 0x0038 -#define MEM_VGA_RP_SEL 0x003C -#define HDP_DEBUG 0x0138 -#define SW_SEMAPHORE 0x013C -#define CRTC2_GEN_CNTL 0x03f8 -#define CRTC2_DISPLAY_BASE_ADDR 0x033c -#define SURFACE_CNTL 0x0B00 -#define SURFACE0_LOWER_BOUND 0x0B04 -#define SURFACE1_LOWER_BOUND 0x0B14 -#define SURFACE2_LOWER_BOUND 0x0B24 -#define SURFACE3_LOWER_BOUND 0x0B34 -#define SURFACE4_LOWER_BOUND 0x0B44 -#define SURFACE5_LOWER_BOUND 0x0B54 -#define SURFACE6_LOWER_BOUND 0x0B64 -#define SURFACE7_LOWER_BOUND 0x0B74 -#define SURFACE0_UPPER_BOUND 0x0B08 -#define SURFACE1_UPPER_BOUND 0x0B18 -#define SURFACE2_UPPER_BOUND 0x0B28 -#define SURFACE3_UPPER_BOUND 0x0B38 -#define SURFACE4_UPPER_BOUND 0x0B48 -#define SURFACE5_UPPER_BOUND 0x0B58 -#define SURFACE6_UPPER_BOUND 0x0B68 -#define SURFACE7_UPPER_BOUND 0x0B78 -#define SURFACE0_INFO 0x0B0C -#define SURFACE1_INFO 0x0B1C -#define SURFACE2_INFO 0x0B2C -#define SURFACE3_INFO 0x0B3C -#define SURFACE4_INFO 0x0B4C -#define SURFACE5_INFO 0x0B5C -#define SURFACE6_INFO 0x0B6C -#define SURFACE7_INFO 0x0B7C -#define SURFACE_ACCESS_FLAGS 0x0BF8 -#define SURFACE_ACCESS_CLR 0x0BFC -#define GEN_INT_CNTL 0x0040 -#define GEN_INT_STATUS 0x0044 -#define CRTC_EXT_CNTL 0x0054 -#define RB3D_CNTL 0x1C3C -#define WAIT_UNTIL 0x1720 -#define ISYNC_CNTL 0x1724 -#define RBBM_GUICNTL 0x172C -#define RBBM_STATUS 0x0E40 -#define RBBM_STATUS_alt_1 0x1740 -#define RBBM_CNTL 0x00EC -#define RBBM_CNTL_alt_1 0x0E44 -#define RBBM_SOFT_RESET 0x00F0 -#define RBBM_SOFT_RESET_alt_1 0x0E48 -#define NQWAIT_UNTIL 0x0E50 -#define RBBM_DEBUG 0x0E6C -#define RBBM_CMDFIFO_ADDR 0x0E70 -#define RBBM_CMDFIFO_DATAL 0x0E74 -#define RBBM_CMDFIFO_DATAH 0x0E78 -#define RBBM_CMDFIFO_STAT 0x0E7C -#define CRTC_STATUS 0x005C -#define GPIO_VGA_DDC 0x0060 -#define GPIO_DVI_DDC 0x0064 -#define GPIO_MONID 0x0068 -#define GPIO_CRT2_DDC 0x006c -#define PALETTE_INDEX 0x00B0 -#define PALETTE_DATA 0x00B4 -#define PALETTE_30_DATA 0x00B8 -#define CRTC_H_TOTAL_DISP 0x0200 -#define CRTC_H_SYNC_STRT_WID 0x0204 -#define CRTC_V_TOTAL_DISP 0x0208 -#define CRTC_V_SYNC_STRT_WID 0x020C -#define CRTC_VLINE_CRNT_VLINE 0x0210 -#define CRTC_CRNT_FRAME 0x0214 -#define CRTC_GUI_TRIG_VLINE 0x0218 -#define CRTC_DEBUG 0x021C -#define CRTC_OFFSET_RIGHT 0x0220 -#define CRTC_OFFSET 0x0224 -#define CRTC_OFFSET_CNTL 0x0228 -#define CRTC_PITCH 0x022C -#define OVR_CLR 0x0230 -#define OVR_WID_LEFT_RIGHT 0x0234 -#define OVR_WID_TOP_BOTTOM 0x0238 -#define DISPLAY_BASE_ADDR 0x023C -#define SNAPSHOT_VH_COUNTS 0x0240 -#define SNAPSHOT_F_COUNT 0x0244 -#define N_VIF_COUNT 0x0248 -#define SNAPSHOT_VIF_COUNT 0x024C -#define FP_CRTC_H_TOTAL_DISP 0x0250 -#define FP_CRTC_V_TOTAL_DISP 0x0254 -#define CRT_CRTC_H_SYNC_STRT_WID 0x0258 -#define CRT_CRTC_V_SYNC_STRT_WID 0x025C -#define CUR_OFFSET 0x0260 -#define CUR_HORZ_VERT_POSN 0x0264 -#define CUR_HORZ_VERT_OFF 0x0268 -#define CUR_CLR0 0x026C -#define CUR_CLR1 0x0270 -#define FP_HORZ_VERT_ACTIVE 0x0278 -#define CRTC_MORE_CNTL 0x027C -#define CRTC_H_CUTOFF_ACTIVE_EN (1<<4) -#define CRTC_V_CUTOFF_ACTIVE_EN (1<<5) -#define DAC_EXT_CNTL 0x0280 -#define FP_GEN_CNTL 0x0284 -#define FP_HORZ_STRETCH 0x028C -#define FP_VERT_STRETCH 0x0290 -#define FP_H_SYNC_STRT_WID 0x02C4 -#define FP_V_SYNC_STRT_WID 0x02C8 -#define AUX_WINDOW_HORZ_CNTL 0x02D8 -#define AUX_WINDOW_VERT_CNTL 0x02DC -//#define DDA_CONFIG 0x02e0 -//#define DDA_ON_OFF 0x02e4 -#define DVI_I2C_CNTL_1 0x02e4 -#define GRPH_BUFFER_CNTL 0x02F0 -#define GRPH2_BUFFER_CNTL 0x03F0 -#define VGA_BUFFER_CNTL 0x02F4 -#define OV0_Y_X_START 0x0400 -#define OV0_Y_X_END 0x0404 -#define OV0_PIPELINE_CNTL 0x0408 -#define OV0_REG_LOAD_CNTL 0x0410 -#define OV0_SCALE_CNTL 0x0420 -#define OV0_V_INC 0x0424 -#define OV0_P1_V_ACCUM_INIT 0x0428 -#define OV0_P23_V_ACCUM_INIT 0x042C -#define OV0_P1_BLANK_LINES_AT_TOP 0x0430 -#define OV0_P23_BLANK_LINES_AT_TOP 0x0434 -#define OV0_BASE_ADDR 0x043C -#define OV0_VID_BUF0_BASE_ADRS 0x0440 -#define OV0_VID_BUF1_BASE_ADRS 0x0444 -#define OV0_VID_BUF2_BASE_ADRS 0x0448 -#define OV0_VID_BUF3_BASE_ADRS 0x044C -#define OV0_VID_BUF4_BASE_ADRS 0x0450 -#define OV0_VID_BUF5_BASE_ADRS 0x0454 -#define OV0_VID_BUF_PITCH0_VALUE 0x0460 -#define OV0_VID_BUF_PITCH1_VALUE 0x0464 -#define OV0_AUTO_FLIP_CNTRL 0x0470 -#define OV0_DEINTERLACE_PATTERN 0x0474 -#define OV0_SUBMIT_HISTORY 0x0478 -#define OV0_H_INC 0x0480 -#define OV0_STEP_BY 0x0484 -#define OV0_P1_H_ACCUM_INIT 0x0488 -#define OV0_P23_H_ACCUM_INIT 0x048C -#define OV0_P1_X_START_END 0x0494 -#define OV0_P2_X_START_END 0x0498 -#define OV0_P3_X_START_END 0x049C -#define OV0_FILTER_CNTL 0x04A0 -#define OV0_FOUR_TAP_COEF_0 0x04B0 -#define OV0_FOUR_TAP_COEF_1 0x04B4 -#define OV0_FOUR_TAP_COEF_2 0x04B8 -#define OV0_FOUR_TAP_COEF_3 0x04BC -#define OV0_FOUR_TAP_COEF_4 0x04C0 -#define OV0_FLAG_CNTRL 0x04DC -#define OV0_SLICE_CNTL 0x04E0 -#define OV0_VID_KEY_CLR_LOW 0x04E4 -#define OV0_VID_KEY_CLR_HIGH 0x04E8 -#define OV0_GRPH_KEY_CLR_LOW 0x04EC -#define OV0_GRPH_KEY_CLR_HIGH 0x04F0 -#define OV0_KEY_CNTL 0x04F4 -#define OV0_TEST 0x04F8 -#define SUBPIC_CNTL 0x0540 -#define SUBPIC_DEFCOLCON 0x0544 -#define SUBPIC_Y_X_START 0x054C -#define SUBPIC_Y_X_END 0x0550 -#define SUBPIC_V_INC 0x0554 -#define SUBPIC_H_INC 0x0558 -#define SUBPIC_BUF0_OFFSET 0x055C -#define SUBPIC_BUF1_OFFSET 0x0560 -#define SUBPIC_LC0_OFFSET 0x0564 -#define SUBPIC_LC1_OFFSET 0x0568 -#define SUBPIC_PITCH 0x056C -#define SUBPIC_BTN_HLI_COLCON 0x0570 -#define SUBPIC_BTN_HLI_Y_X_START 0x0574 -#define SUBPIC_BTN_HLI_Y_X_END 0x0578 -#define SUBPIC_PALETTE_INDEX 0x057C -#define SUBPIC_PALETTE_DATA 0x0580 -#define SUBPIC_H_ACCUM_INIT 0x0584 -#define SUBPIC_V_ACCUM_INIT 0x0588 -#define DISP_MISC_CNTL 0x0D00 -#define DAC_MACRO_CNTL 0x0D04 -#define DISP_PWR_MAN 0x0D08 -#define DISP_TEST_DEBUG_CNTL 0x0D10 -#define DISP_HW_DEBUG 0x0D14 -#define DAC_CRC_SIG1 0x0D18 -#define DAC_CRC_SIG2 0x0D1C -#define OV0_LIN_TRANS_A 0x0D20 -#define OV0_LIN_TRANS_B 0x0D24 -#define OV0_LIN_TRANS_C 0x0D28 -#define OV0_LIN_TRANS_D 0x0D2C -#define OV0_LIN_TRANS_E 0x0D30 -#define OV0_LIN_TRANS_F 0x0D34 -#define OV0_GAMMA_0_F 0x0D40 -#define OV0_GAMMA_10_1F 0x0D44 -#define OV0_GAMMA_20_3F 0x0D48 -#define OV0_GAMMA_40_7F 0x0D4C -#define OV0_GAMMA_380_3BF 0x0D50 -#define OV0_GAMMA_3C0_3FF 0x0D54 -#define DISP_MERGE_CNTL 0x0D60 -#define DISP_OUTPUT_CNTL 0x0D64 -#define DISP_LIN_TRANS_GRPH_A 0x0D80 -#define DISP_LIN_TRANS_GRPH_B 0x0D84 -#define DISP_LIN_TRANS_GRPH_C 0x0D88 -#define DISP_LIN_TRANS_GRPH_D 0x0D8C -#define DISP_LIN_TRANS_GRPH_E 0x0D90 -#define DISP_LIN_TRANS_GRPH_F 0x0D94 -#define DISP_LIN_TRANS_VID_A 0x0D98 -#define DISP_LIN_TRANS_VID_B 0x0D9C -#define DISP_LIN_TRANS_VID_C 0x0DA0 -#define DISP_LIN_TRANS_VID_D 0x0DA4 -#define DISP_LIN_TRANS_VID_E 0x0DA8 -#define DISP_LIN_TRANS_VID_F 0x0DAC -#define RMX_HORZ_FILTER_0TAP_COEF 0x0DB0 -#define RMX_HORZ_FILTER_1TAP_COEF 0x0DB4 -#define RMX_HORZ_FILTER_2TAP_COEF 0x0DB8 -#define RMX_HORZ_PHASE 0x0DBC -#define DAC_EMBEDDED_SYNC_CNTL 0x0DC0 -#define DAC_BROAD_PULSE 0x0DC4 -#define DAC_SKEW_CLKS 0x0DC8 -#define DAC_INCR 0x0DCC -#define DAC_NEG_SYNC_LEVEL 0x0DD0 -#define DAC_POS_SYNC_LEVEL 0x0DD4 -#define DAC_BLANK_LEVEL 0x0DD8 -#define CLOCK_CNTL_INDEX 0x0008 -#define CLOCK_CNTL_DATA 0x000C -#define CP_RB_CNTL 0x0704 -#define CP_RB_BASE 0x0700 -#define CP_RB_RPTR_ADDR 0x070C -#define CP_RB_RPTR 0x0710 -#define CP_RB_WPTR 0x0714 -#define CP_RB_WPTR_DELAY 0x0718 -#define CP_IB_BASE 0x0738 -#define CP_IB_BUFSZ 0x073C -#define SCRATCH_REG0 0x15E0 -#define GUI_SCRATCH_REG0 0x15E0 -#define SCRATCH_REG1 0x15E4 -#define GUI_SCRATCH_REG1 0x15E4 -#define SCRATCH_REG2 0x15E8 -#define GUI_SCRATCH_REG2 0x15E8 -#define SCRATCH_REG3 0x15EC -#define GUI_SCRATCH_REG3 0x15EC -#define SCRATCH_REG4 0x15F0 -#define GUI_SCRATCH_REG4 0x15F0 -#define SCRATCH_REG5 0x15F4 -#define GUI_SCRATCH_REG5 0x15F4 -#define SCRATCH_UMSK 0x0770 -#define SCRATCH_ADDR 0x0774 -#define DP_BRUSH_FRGD_CLR 0x147C -#define DP_BRUSH_BKGD_CLR 0x1478 -#define DST_LINE_START 0x1600 -#define DST_LINE_END 0x1604 -#define SRC_OFFSET 0x15AC -#define SRC_PITCH 0x15B0 -#define SRC_TILE 0x1704 -#define SRC_PITCH_OFFSET 0x1428 -#define SRC_X 0x1414 -#define SRC_Y 0x1418 -#define SRC_X_Y 0x1590 -#define SRC_Y_X 0x1434 -#define DST_Y_X 0x1438 -#define DST_WIDTH_HEIGHT 0x1598 -#define DST_HEIGHT_WIDTH 0x143c -#define DST_OFFSET 0x1404 -#define SRC_CLUT_ADDRESS 0x1780 -#define SRC_CLUT_DATA 0x1784 -#define SRC_CLUT_DATA_RD 0x1788 -#define HOST_DATA0 0x17C0 -#define HOST_DATA1 0x17C4 -#define HOST_DATA2 0x17C8 -#define HOST_DATA3 0x17CC -#define HOST_DATA4 0x17D0 -#define HOST_DATA5 0x17D4 -#define HOST_DATA6 0x17D8 -#define HOST_DATA7 0x17DC -#define HOST_DATA_LAST 0x17E0 -#define DP_SRC_ENDIAN 0x15D4 -#define DP_SRC_FRGD_CLR 0x15D8 -#define DP_SRC_BKGD_CLR 0x15DC -#define SC_LEFT 0x1640 -#define SC_RIGHT 0x1644 -#define SC_TOP 0x1648 -#define SC_BOTTOM 0x164C -#define SRC_SC_RIGHT 0x1654 -#define SRC_SC_BOTTOM 0x165C -#define DP_CNTL 0x16C0 -#define DP_CNTL_XDIR_YDIR_YMAJOR 0x16D0 -#define DP_DATATYPE 0x16C4 -#define DP_MIX 0x16C8 -#define DP_WRITE_MSK 0x16CC -#define DP_XOP 0x17F8 -#define CLR_CMP_CLR_SRC 0x15C4 -#define CLR_CMP_CLR_DST 0x15C8 -#define CLR_CMP_CNTL 0x15C0 -#define CLR_CMP_MSK 0x15CC -#define DSTCACHE_MODE 0x1710 -#define DSTCACHE_CTLSTAT 0x1714 -#define DEFAULT_PITCH_OFFSET 0x16E0 -#define DEFAULT_SC_BOTTOM_RIGHT 0x16E8 -#define DEFAULT_SC_TOP_LEFT 0x16EC -#define SRC_PITCH_OFFSET 0x1428 -#define DST_PITCH_OFFSET 0x142C -#define DP_GUI_MASTER_CNTL 0x146C -#define SC_TOP_LEFT 0x16EC -#define SC_BOTTOM_RIGHT 0x16F0 -#define SRC_SC_BOTTOM_RIGHT 0x16F4 -#define RB2D_DSTCACHE_MODE 0x3428 -#define RB2D_DSTCACHE_CTLSTAT_broken 0x342C /* do not use */ -#define LVDS_GEN_CNTL 0x02d0 -#define LVDS_PLL_CNTL 0x02d4 -#define FP2_GEN_CNTL 0x0288 -#define TMDS_CNTL 0x0294 -#define TMDS_CRC 0x02a0 -#define TMDS_TRANSMITTER_CNTL 0x02a4 -#define MPP_TB_CONFIG 0x01c0 -#define PAMAC0_DLY_CNTL 0x0a94 -#define PAMAC1_DLY_CNTL 0x0a98 -#define PAMAC2_DLY_CNTL 0x0a9c -#define FW_CNTL 0x0118 -#define FCP_CNTL 0x0910 -#define VGA_DDA_ON_OFF 0x02ec -#define TV_MASTER_CNTL 0x0800 - -//#define BASE_CODE 0x0f0b -#define BIOS_0_SCRATCH 0x0010 -#define BIOS_1_SCRATCH 0x0014 -#define BIOS_2_SCRATCH 0x0018 -#define BIOS_3_SCRATCH 0x001c -#define BIOS_4_SCRATCH 0x0020 -#define BIOS_5_SCRATCH 0x0024 -#define BIOS_6_SCRATCH 0x0028 -#define BIOS_7_SCRATCH 0x002c - -#define HDP_SOFT_RESET (1 << 26) - -#define TV_DAC_CNTL 0x088c -#define GPIOPAD_MASK 0x0198 -#define GPIOPAD_A 0x019c -#define GPIOPAD_EN 0x01a0 -#define GPIOPAD_Y 0x01a4 -#define ZV_LCDPAD_MASK 0x01a8 -#define ZV_LCDPAD_A 0x01ac -#define ZV_LCDPAD_EN 0x01b0 -#define ZV_LCDPAD_Y 0x01b4 - -/* PLL Registers */ -#define CLK_PIN_CNTL 0x0001 -#define PPLL_CNTL 0x0002 -#define PPLL_REF_DIV 0x0003 -#define PPLL_DIV_0 0x0004 -#define PPLL_DIV_1 0x0005 -#define PPLL_DIV_2 0x0006 -#define PPLL_DIV_3 0x0007 -#define VCLK_ECP_CNTL 0x0008 -#define HTOTAL_CNTL 0x0009 -#define M_SPLL_REF_FB_DIV 0x000a -#define AGP_PLL_CNTL 0x000b -#define SPLL_CNTL 0x000c -#define SCLK_CNTL 0x000d -#define MPLL_CNTL 0x000e -#define MDLL_CKO 0x000f -#define MDLL_RDCKA 0x0010 -#define MCLK_CNTL 0x0012 -#define AGP_PLL_CNTL 0x000b -#define PLL_TEST_CNTL 0x0013 -#define CLK_PWRMGT_CNTL 0x0014 -#define PLL_PWRMGT_CNTL 0x0015 -#define MCLK_MISC 0x001f -#define P2PLL_CNTL 0x002a -#define P2PLL_REF_DIV 0x002b -#define PIXCLKS_CNTL 0x002d -#define SCLK_MORE_CNTL 0x0035 - -/* MCLK_CNTL bit constants */ -#define FORCEON_MCLKA (1 << 16) -#define FORCEON_MCLKB (1 << 17) -#define FORCEON_YCLKA (1 << 18) -#define FORCEON_YCLKB (1 << 19) -#define FORCEON_MC (1 << 20) -#define FORCEON_AIC (1 << 21) - -/* SCLK_CNTL bit constants */ -#define DYN_STOP_LAT_MASK 0x00007ff8 -#define CP_MAX_DYN_STOP_LAT 0x0008 -#define SCLK_FORCEON_MASK 0xffff8000 - -/* SCLK_MORE_CNTL bit constants */ -#define SCLK_MORE_FORCEON 0x0700 - -/* BUS_CNTL bit constants */ -#define BUS_DBL_RESYNC 0x00000001 -#define BUS_MSTR_RESET 0x00000002 -#define BUS_FLUSH_BUF 0x00000004 -#define BUS_STOP_REQ_DIS 0x00000008 -#define BUS_ROTATION_DIS 0x00000010 -#define BUS_MASTER_DIS 0x00000040 -#define BUS_ROM_WRT_EN 0x00000080 -#define BUS_DIS_ROM 0x00001000 -#define BUS_PCI_READ_RETRY_EN 0x00002000 -#define BUS_AGP_AD_STEPPING_EN 0x00004000 -#define BUS_PCI_WRT_RETRY_EN 0x00008000 -#define BUS_MSTR_RD_MULT 0x00100000 -#define BUS_MSTR_RD_LINE 0x00200000 -#define BUS_SUSPEND 0x00400000 -#define LAT_16X 0x00800000 -#define BUS_RD_DISCARD_EN 0x01000000 -#define BUS_RD_ABORT_EN 0x02000000 -#define BUS_MSTR_WS 0x04000000 -#define BUS_PARKING_DIS 0x08000000 -#define BUS_MSTR_DISCONNECT_EN 0x10000000 -#define BUS_WRT_BURST 0x20000000 -#define BUS_READ_BURST 0x40000000 -#define BUS_RDY_READ_DLY 0x80000000 - -/* PIXCLKS_CNTL */ -#define PIX2CLK_SRC_SEL_MASK 0x03 -#define PIX2CLK_SRC_SEL_CPUCLK 0x00 -#define PIX2CLK_SRC_SEL_PSCANCLK 0x01 -#define PIX2CLK_SRC_SEL_BYTECLK 0x02 -#define PIX2CLK_SRC_SEL_P2PLLCLK 0x03 -#define PIX2CLK_ALWAYS_ONb (1<<6) -#define PIX2CLK_DAC_ALWAYS_ONb (1<<7) -#define PIXCLK_TV_SRC_SEL (1 << 8) -#define PIXCLK_LVDS_ALWAYS_ONb (1 << 14) -#define PIXCLK_TMDS_ALWAYS_ONb (1 << 15) - - -/* CLOCK_CNTL_INDEX bit constants */ -#define PLL_WR_EN 0x00000080 - -/* CNFG_CNTL bit constants */ -#define CFG_VGA_RAM_EN 0x00000100 -#define CFG_ATI_REV_ID_MASK (0xf << 16) -#define CFG_ATI_REV_A11 (0 << 16) -#define CFG_ATI_REV_A12 (1 << 16) -#define CFG_ATI_REV_A13 (2 << 16) - -/* CRTC_EXT_CNTL bit constants */ -#define VGA_ATI_LINEAR 0x00000008 -#define VGA_128KAP_PAGING 0x00000010 -#define XCRT_CNT_EN (1 << 6) -#define CRTC_HSYNC_DIS (1 << 8) -#define CRTC_VSYNC_DIS (1 << 9) -#define CRTC_DISPLAY_DIS (1 << 10) -#define CRTC_CRT_ON (1 << 15) - - -/* DSTCACHE_CTLSTAT bit constants */ -#define RB2D_DC_FLUSH_2D (1 << 0) -#define RB2D_DC_FREE_2D (1 << 2) -#define RB2D_DC_FLUSH_ALL (RB2D_DC_FLUSH_2D | RB2D_DC_FREE_2D) -#define RB2D_DC_BUSY (1 << 31) - -/* DSTCACHE_MODE bits constants */ -#define RB2D_DC_AUTOFLUSH_ENABLE (1 << 8) -#define RB2D_DC_DC_DISABLE_IGNORE_PE (1 << 17) - -/* CRTC_GEN_CNTL bit constants */ -#define CRTC_DBL_SCAN_EN 0x00000001 -#define CRTC_CUR_EN 0x00010000 -#define CRTC_INTERLACE_EN (1 << 1) -#define CRTC_BYPASS_LUT_EN (1 << 14) -#define CRTC_EXT_DISP_EN (1 << 24) -#define CRTC_EN (1 << 25) -#define CRTC_DISP_REQ_EN_B (1 << 26) - -/* CRTC_STATUS bit constants */ -#define CRTC_VBLANK 0x00000001 - -/* CRTC2_GEN_CNTL bit constants */ -#define CRT2_ON (1 << 7) -#define CRTC2_DISPLAY_DIS (1 << 23) -#define CRTC2_EN (1 << 25) -#define CRTC2_DISP_REQ_EN_B (1 << 26) - -/* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */ -#define CUR_LOCK 0x80000000 - -/* GPIO bit constants */ -#define GPIO_A_0 (1 << 0) -#define GPIO_A_1 (1 << 1) -#define GPIO_Y_0 (1 << 8) -#define GPIO_Y_1 (1 << 9) -#define GPIO_EN_0 (1 << 16) -#define GPIO_EN_1 (1 << 17) -#define GPIO_MASK_0 (1 << 24) -#define GPIO_MASK_1 (1 << 25) -#define VGA_DDC_DATA_OUTPUT GPIO_A_0 -#define VGA_DDC_CLK_OUTPUT GPIO_A_1 -#define VGA_DDC_DATA_INPUT GPIO_Y_0 -#define VGA_DDC_CLK_INPUT GPIO_Y_1 -#define VGA_DDC_DATA_OUT_EN GPIO_EN_0 -#define VGA_DDC_CLK_OUT_EN GPIO_EN_1 - - -/* FP bit constants */ -#define FP_CRTC_H_TOTAL_MASK 0x000003ff -#define FP_CRTC_H_DISP_MASK 0x01ff0000 -#define FP_CRTC_V_TOTAL_MASK 0x00000fff -#define FP_CRTC_V_DISP_MASK 0x0fff0000 -#define FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8 -#define FP_H_SYNC_WID_MASK 0x003f0000 -#define FP_V_SYNC_STRT_MASK 0x00000fff -#define FP_V_SYNC_WID_MASK 0x001f0000 -#define FP_CRTC_H_TOTAL_SHIFT 0x00000000 -#define FP_CRTC_H_DISP_SHIFT 0x00000010 -#define FP_CRTC_V_TOTAL_SHIFT 0x00000000 -#define FP_CRTC_V_DISP_SHIFT 0x00000010 -#define FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003 -#define FP_H_SYNC_WID_SHIFT 0x00000010 -#define FP_V_SYNC_STRT_SHIFT 0x00000000 -#define FP_V_SYNC_WID_SHIFT 0x00000010 - -/* FP_GEN_CNTL bit constants */ -#define FP_FPON (1 << 0) -#define FP_TMDS_EN (1 << 2) -#define FP_PANEL_FORMAT (1 << 3) -#define FP_EN_TMDS (1 << 7) -#define FP_DETECT_SENSE (1 << 8) -#define R200_FP_SOURCE_SEL_MASK (3 << 10) -#define R200_FP_SOURCE_SEL_CRTC1 (0 << 10) -#define R200_FP_SOURCE_SEL_CRTC2 (1 << 10) -#define R200_FP_SOURCE_SEL_RMX (2 << 10) -#define R200_FP_SOURCE_SEL_TRANS (3 << 10) -#define FP_SEL_CRTC1 (0 << 13) -#define FP_SEL_CRTC2 (1 << 13) -#define FP_USE_VGA_HSYNC (1 << 14) -#define FP_CRTC_DONT_SHADOW_HPAR (1 << 15) -#define FP_CRTC_DONT_SHADOW_VPAR (1 << 16) -#define FP_CRTC_DONT_SHADOW_HEND (1 << 17) -#define FP_CRTC_USE_SHADOW_VEND (1 << 18) -#define FP_RMX_HVSYNC_CONTROL_EN (1 << 20) -#define FP_DFP_SYNC_SEL (1 << 21) -#define FP_CRTC_LOCK_8DOT (1 << 22) -#define FP_CRT_SYNC_SEL (1 << 23) -#define FP_USE_SHADOW_EN (1 << 24) -#define FP_CRT_SYNC_ALT (1 << 26) - -/* FP2_GEN_CNTL bit constants */ -#define FP2_BLANK_EN (1 << 1) -#define FP2_ON (1 << 2) -#define FP2_PANEL_FORMAT (1 << 3) -#define FP2_SOURCE_SEL_MASK (3 << 10) -#define FP2_SOURCE_SEL_CRTC2 (1 << 10) -#define FP2_SRC_SEL_MASK (3 << 13) -#define FP2_SRC_SEL_CRTC2 (1 << 13) -#define FP2_FP_POL (1 << 16) -#define FP2_LP_POL (1 << 17) -#define FP2_SCK_POL (1 << 18) -#define FP2_LCD_CNTL_MASK (7 << 19) -#define FP2_PAD_FLOP_EN (1 << 22) -#define FP2_CRC_EN (1 << 23) -#define FP2_CRC_READ_EN (1 << 24) -#define FP2_DV0_EN (1 << 25) -#define FP2_DV0_RATE_SEL_SDR (1 << 26) - - -/* LVDS_GEN_CNTL bit constants */ -#define LVDS_ON (1 << 0) -#define LVDS_DISPLAY_DIS (1 << 1) -#define LVDS_PANEL_TYPE (1 << 2) -#define LVDS_PANEL_FORMAT (1 << 3) -#define LVDS_EN (1 << 7) -#define LVDS_BL_MOD_LEVEL_MASK 0x0000ff00 -#define LVDS_BL_MOD_LEVEL_SHIFT 8 -#define LVDS_BL_MOD_EN (1 << 16) -#define LVDS_DIGON (1 << 18) -#define LVDS_BLON (1 << 19) -#define LVDS_SEL_CRTC2 (1 << 23) -#define LVDS_STATE_MASK \ - (LVDS_ON | LVDS_DISPLAY_DIS | LVDS_BL_MOD_LEVEL_MASK | LVDS_BLON) - -/* LVDS_PLL_CNTL bit constatns */ -#define HSYNC_DELAY_SHIFT 0x1c -#define HSYNC_DELAY_MASK (0xf << 0x1c) - -/* TMDS_TRANSMITTER_CNTL bit constants */ -#define TMDS_PLL_EN (1 << 0) -#define TMDS_PLLRST (1 << 1) -#define TMDS_RAN_PAT_RST (1 << 7) -#define TMDS_ICHCSEL (1 << 28) - -/* FP_HORZ_STRETCH bit constants */ -#define HORZ_STRETCH_RATIO_MASK 0xffff -#define HORZ_STRETCH_RATIO_MAX 4096 -#define HORZ_PANEL_SIZE (0x1ff << 16) -#define HORZ_PANEL_SHIFT 16 -#define HORZ_STRETCH_PIXREP (0 << 25) -#define HORZ_STRETCH_BLEND (1 << 26) -#define HORZ_STRETCH_ENABLE (1 << 25) -#define HORZ_AUTO_RATIO (1 << 27) -#define HORZ_FP_LOOP_STRETCH (0x7 << 28) -#define HORZ_AUTO_RATIO_INC (1 << 31) - - -/* FP_VERT_STRETCH bit constants */ -#define VERT_STRETCH_RATIO_MASK 0xfff -#define VERT_STRETCH_RATIO_MAX 4096 -#define VERT_PANEL_SIZE (0xfff << 12) -#define VERT_PANEL_SHIFT 12 -#define VERT_STRETCH_LINREP (0 << 26) -#define VERT_STRETCH_BLEND (1 << 26) -#define VERT_STRETCH_ENABLE (1 << 25) -#define VERT_AUTO_RATIO_EN (1 << 27) -#define VERT_FP_LOOP_STRETCH (0x7 << 28) -#define VERT_STRETCH_RESERVED 0xf1000000 - -/* DAC_CNTL bit constants */ -#define DAC_8BIT_EN 0x00000100 -#define DAC_4BPP_PIX_ORDER 0x00000200 -#define DAC_CRC_EN 0x00080000 -#define DAC_MASK_ALL (0xff << 24) -#define DAC_PDWN (1 << 15) -#define DAC_EXPAND_MODE (1 << 14) -#define DAC_VGA_ADR_EN (1 << 13) -#define DAC_RANGE_CNTL (3 << 0) -#define DAC_RANGE_CNTL_MASK 0x03 -#define DAC_BLANKING (1 << 2) -#define DAC_CMP_EN (1 << 3) -#define DAC_CMP_OUTPUT (1 << 7) - -/* DAC_CNTL2 bit constants */ -#define DAC2_EXPAND_MODE (1 << 14) -#define DAC2_CMP_EN (1 << 7) -#define DAC2_PALETTE_ACCESS_CNTL (1 << 5) - -/* DAC_EXT_CNTL bit constants */ -#define DAC_FORCE_BLANK_OFF_EN (1 << 4) -#define DAC_FORCE_DATA_EN (1 << 5) -#define DAC_FORCE_DATA_SEL_MASK (3 << 6) -#define DAC_FORCE_DATA_MASK 0x0003ff00 -#define DAC_FORCE_DATA_SHIFT 8 - -/* GEN_RESET_CNTL bit constants */ -#define SOFT_RESET_GUI 0x00000001 -#define SOFT_RESET_VCLK 0x00000100 -#define SOFT_RESET_PCLK 0x00000200 -#define SOFT_RESET_ECP 0x00000400 -#define SOFT_RESET_DISPENG_XCLK 0x00000800 - -/* MEM_CNTL bit constants */ -#define MEM_CTLR_STATUS_IDLE 0x00000000 -#define MEM_CTLR_STATUS_BUSY 0x00100000 -#define MEM_SEQNCR_STATUS_IDLE 0x00000000 -#define MEM_SEQNCR_STATUS_BUSY 0x00200000 -#define MEM_ARBITER_STATUS_IDLE 0x00000000 -#define MEM_ARBITER_STATUS_BUSY 0x00400000 -#define MEM_REQ_UNLOCK 0x00000000 -#define MEM_REQ_LOCK 0x00800000 -#define MEM_NUM_CHANNELS_MASK 0x00000001 -#define MEM_USE_B_CH_ONLY 0x00000002 -#define RV100_MEM_HALF_MODE 0x00000008 -#define R300_MEM_NUM_CHANNELS_MASK 0x00000003 -#define R300_MEM_USE_CD_CH_ONLY 0x00000004 - - -/* RBBM_SOFT_RESET bit constants */ -#define SOFT_RESET_CP (1 << 0) -#define SOFT_RESET_HI (1 << 1) -#define SOFT_RESET_SE (1 << 2) -#define SOFT_RESET_RE (1 << 3) -#define SOFT_RESET_PP (1 << 4) -#define SOFT_RESET_E2 (1 << 5) -#define SOFT_RESET_RB (1 << 6) -#define SOFT_RESET_HDP (1 << 7) - -/* WAIT_UNTIL bit constants */ -#define WAIT_DMA_GUI_IDLE (1 << 9) -#define WAIT_2D_IDLECLEAN (1 << 16) - -/* SURFACE_CNTL bit consants */ -#define SURF_TRANSLATION_DIS (1 << 8) -#define NONSURF_AP0_SWP_16BPP (1 << 20) -#define NONSURF_AP0_SWP_32BPP (1 << 21) -#define NONSURF_AP1_SWP_16BPP (1 << 22) -#define NONSURF_AP1_SWP_32BPP (1 << 23) - -/* DEFAULT_SC_BOTTOM_RIGHT bit constants */ -#define DEFAULT_SC_RIGHT_MAX (0x1fff << 0) -#define DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) - -/* MM_INDEX bit constants */ -#define MM_APER 0x80000000 - -/* CLR_CMP_CNTL bit constants */ -#define COMPARE_SRC_FALSE 0x00000000 -#define COMPARE_SRC_TRUE 0x00000001 -#define COMPARE_SRC_NOT_EQUAL 0x00000004 -#define COMPARE_SRC_EQUAL 0x00000005 -#define COMPARE_SRC_EQUAL_FLIP 0x00000007 -#define COMPARE_DST_FALSE 0x00000000 -#define COMPARE_DST_TRUE 0x00000100 -#define COMPARE_DST_NOT_EQUAL 0x00000400 -#define COMPARE_DST_EQUAL 0x00000500 -#define COMPARE_DESTINATION 0x00000000 -#define COMPARE_SOURCE 0x01000000 -#define COMPARE_SRC_AND_DST 0x02000000 - - -/* DP_CNTL bit constants */ -#define DST_X_RIGHT_TO_LEFT 0x00000000 -#define DST_X_LEFT_TO_RIGHT 0x00000001 -#define DST_Y_BOTTOM_TO_TOP 0x00000000 -#define DST_Y_TOP_TO_BOTTOM 0x00000002 -#define DST_X_MAJOR 0x00000000 -#define DST_Y_MAJOR 0x00000004 -#define DST_X_TILE 0x00000008 -#define DST_Y_TILE 0x00000010 -#define DST_LAST_PEL 0x00000020 -#define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000 -#define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040 -#define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000 -#define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080 -#define DST_BRES_SIGN 0x00000100 -#define DST_HOST_BIG_ENDIAN_EN 0x00000200 -#define DST_POLYLINE_NONLAST 0x00008000 -#define DST_RASTER_STALL 0x00010000 -#define DST_POLY_EDGE 0x00040000 - - -/* DP_CNTL_YDIR_XDIR_YMAJOR bit constants (short version of DP_CNTL) */ -#define DST_X_MAJOR_S 0x00000000 -#define DST_Y_MAJOR_S 0x00000001 -#define DST_Y_BOTTOM_TO_TOP_S 0x00000000 -#define DST_Y_TOP_TO_BOTTOM_S 0x00008000 -#define DST_X_RIGHT_TO_LEFT_S 0x00000000 -#define DST_X_LEFT_TO_RIGHT_S 0x80000000 - - -/* DP_DATATYPE bit constants */ -#define DST_8BPP 0x00000002 -#define DST_15BPP 0x00000003 -#define DST_16BPP 0x00000004 -#define DST_24BPP 0x00000005 -#define DST_32BPP 0x00000006 -#define DST_8BPP_RGB332 0x00000007 -#define DST_8BPP_Y8 0x00000008 -#define DST_8BPP_RGB8 0x00000009 -#define DST_16BPP_VYUY422 0x0000000b -#define DST_16BPP_YVYU422 0x0000000c -#define DST_32BPP_AYUV444 0x0000000e -#define DST_16BPP_ARGB4444 0x0000000f -#define BRUSH_SOLIDCOLOR 0x00000d00 -#define SRC_MONO 0x00000000 -#define SRC_MONO_LBKGD 0x00010000 -#define SRC_DSTCOLOR 0x00030000 -#define BYTE_ORDER_MSB_TO_LSB 0x00000000 -#define BYTE_ORDER_LSB_TO_MSB 0x40000000 -#define DP_CONVERSION_TEMP 0x80000000 -#define HOST_BIG_ENDIAN_EN (1 << 29) - - -/* DP_GUI_MASTER_CNTL bit constants */ -#define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000 -#define GMC_SRC_PITCH_OFFSET_LEAVE 0x00000001 -#define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000 -#define GMC_DST_PITCH_OFFSET_LEAVE 0x00000002 -#define GMC_SRC_CLIP_DEFAULT 0x00000000 -#define GMC_SRC_CLIP_LEAVE 0x00000004 -#define GMC_DST_CLIP_DEFAULT 0x00000000 -#define GMC_DST_CLIP_LEAVE 0x00000008 -#define GMC_BRUSH_8x8MONO 0x00000000 -#define GMC_BRUSH_8x8MONO_LBKGD 0x00000010 -#define GMC_BRUSH_8x1MONO 0x00000020 -#define GMC_BRUSH_8x1MONO_LBKGD 0x00000030 -#define GMC_BRUSH_1x8MONO 0x00000040 -#define GMC_BRUSH_1x8MONO_LBKGD 0x00000050 -#define GMC_BRUSH_32x1MONO 0x00000060 -#define GMC_BRUSH_32x1MONO_LBKGD 0x00000070 -#define GMC_BRUSH_32x32MONO 0x00000080 -#define GMC_BRUSH_32x32MONO_LBKGD 0x00000090 -#define GMC_BRUSH_8x8COLOR 0x000000a0 -#define GMC_BRUSH_8x1COLOR 0x000000b0 -#define GMC_BRUSH_1x8COLOR 0x000000c0 -#define GMC_BRUSH_SOLID_COLOR 0x000000d0 -#define GMC_DST_8BPP 0x00000200 -#define GMC_DST_15BPP 0x00000300 -#define GMC_DST_16BPP 0x00000400 -#define GMC_DST_24BPP 0x00000500 -#define GMC_DST_32BPP 0x00000600 -#define GMC_DST_8BPP_RGB332 0x00000700 -#define GMC_DST_8BPP_Y8 0x00000800 -#define GMC_DST_8BPP_RGB8 0x00000900 -#define GMC_DST_16BPP_VYUY422 0x00000b00 -#define GMC_DST_16BPP_YVYU422 0x00000c00 -#define GMC_DST_32BPP_AYUV444 0x00000e00 -#define GMC_DST_16BPP_ARGB4444 0x00000f00 -#define GMC_SRC_MONO 0x00000000 -#define GMC_SRC_MONO_LBKGD 0x00001000 -#define GMC_SRC_DSTCOLOR 0x00003000 -#define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000 -#define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000 -#define GMC_DP_CONVERSION_TEMP_9300 0x00008000 -#define GMC_DP_CONVERSION_TEMP_6500 0x00000000 -#define GMC_DP_SRC_RECT 0x02000000 -#define GMC_DP_SRC_HOST 0x03000000 -#define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000 -#define GMC_3D_FCN_EN_CLR 0x00000000 -#define GMC_3D_FCN_EN_SET 0x08000000 -#define GMC_DST_CLR_CMP_FCN_LEAVE 0x00000000 -#define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000 -#define GMC_AUX_CLIP_LEAVE 0x00000000 -#define GMC_AUX_CLIP_CLEAR 0x20000000 -#define GMC_WRITE_MASK_LEAVE 0x00000000 -#define GMC_WRITE_MASK_SET 0x40000000 -#define GMC_CLR_CMP_CNTL_DIS (1 << 28) -#define GMC_SRC_DATATYPE_COLOR (3 << 12) -#define ROP3_S 0x00cc0000 -#define ROP3_SRCCOPY 0x00cc0000 -#define ROP3_P 0x00f00000 -#define ROP3_PATCOPY 0x00f00000 -#define DP_SRC_SOURCE_MASK (7 << 24) -#define GMC_BRUSH_NONE (15 << 4) -#define DP_SRC_SOURCE_MEMORY (2 << 24) -#define GMC_BRUSH_SOLIDCOLOR 0x000000d0 - -/* DP_MIX bit constants */ -#define DP_SRC_RECT 0x00000200 -#define DP_SRC_HOST 0x00000300 -#define DP_SRC_HOST_BYTEALIGN 0x00000400 - -/* MPLL_CNTL bit constants */ -#define MPLL_RESET 0x00000001 - -/* MDLL_CKO bit constants */ -#define MCKOA_SLEEP 0x00000001 -#define MCKOA_RESET 0x00000002 -#define MCKOA_REF_SKEW_MASK 0x00000700 -#define MCKOA_FB_SKEW_MASK 0x00007000 - -/* MDLL_RDCKA bit constants */ -#define MRDCKA0_SLEEP 0x00000001 -#define MRDCKA0_RESET 0x00000002 -#define MRDCKA1_SLEEP 0x00010000 -#define MRDCKA1_RESET 0x00020000 - -/* VCLK_ECP_CNTL constants */ -#define VCLK_SRC_SEL_MASK 0x03 -#define VCLK_SRC_SEL_CPUCLK 0x00 -#define VCLK_SRC_SEL_PSCANCLK 0x01 -#define VCLK_SRC_SEL_BYTECLK 0x02 -#define VCLK_SRC_SEL_PPLLCLK 0x03 -#define PIXCLK_ALWAYS_ONb 0x00000040 -#define PIXCLK_DAC_ALWAYS_ONb 0x00000080 - -/* BUS_CNTL1 constants */ -#define BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK 0x0c000000 -#define BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT 26 -#define BUS_CNTL1_AGPCLK_VALID 0x80000000 - -/* PLL_PWRMGT_CNTL constants */ -#define PLL_PWRMGT_CNTL_SPLL_TURNOFF 0x00000002 -#define PLL_PWRMGT_CNTL_PPLL_TURNOFF 0x00000004 -#define PLL_PWRMGT_CNTL_P2PLL_TURNOFF 0x00000008 -#define PLL_PWRMGT_CNTL_TVPLL_TURNOFF 0x00000010 -#define PLL_PWRMGT_CNTL_MOBILE_SU 0x00010000 -#define PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK 0x00020000 -#define PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK 0x00040000 - -/* TV_DAC_CNTL constants */ -#define TV_DAC_CNTL_BGSLEEP 0x00000040 -#define TV_DAC_CNTL_DETECT 0x00000010 -#define TV_DAC_CNTL_BGADJ_MASK 0x000f0000 -#define TV_DAC_CNTL_DACADJ_MASK 0x00f00000 -#define TV_DAC_CNTL_BGADJ__SHIFT 16 -#define TV_DAC_CNTL_DACADJ__SHIFT 20 -#define TV_DAC_CNTL_RDACPD 0x01000000 -#define TV_DAC_CNTL_GDACPD 0x02000000 -#define TV_DAC_CNTL_BDACPD 0x04000000 - -/* DISP_MISC_CNTL constants */ -#define DISP_MISC_CNTL_SOFT_RESET_GRPH_PP (1 << 0) -#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_PP (1 << 1) -#define DISP_MISC_CNTL_SOFT_RESET_OV0_PP (1 << 2) -#define DISP_MISC_CNTL_SOFT_RESET_GRPH_SCLK (1 << 4) -#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_SCLK (1 << 5) -#define DISP_MISC_CNTL_SOFT_RESET_OV0_SCLK (1 << 6) -#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_PP (1 << 12) -#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_SCLK (1 << 15) -#define DISP_MISC_CNTL_SOFT_RESET_LVDS (1 << 16) -#define DISP_MISC_CNTL_SOFT_RESET_TMDS (1 << 17) -#define DISP_MISC_CNTL_SOFT_RESET_DIG_TMDS (1 << 18) -#define DISP_MISC_CNTL_SOFT_RESET_TV (1 << 19) - -/* DISP_PWR_MAN constants */ -#define DISP_PWR_MAN_DISP_PWR_MAN_D3_CRTC_EN (1 << 0) -#define DISP_PWR_MAN_DISP2_PWR_MAN_D3_CRTC2_EN (1 << 4) -#define DISP_PWR_MAN_DISP_D3_RST (1 << 16) -#define DISP_PWR_MAN_DISP_D3_REG_RST (1 << 17) -#define DISP_PWR_MAN_DISP_D3_GRPH_RST (1 << 18) -#define DISP_PWR_MAN_DISP_D3_SUBPIC_RST (1 << 19) -#define DISP_PWR_MAN_DISP_D3_OV0_RST (1 << 20) -#define DISP_PWR_MAN_DISP_D1D2_GRPH_RST (1 << 21) -#define DISP_PWR_MAN_DISP_D1D2_SUBPIC_RST (1 << 22) -#define DISP_PWR_MAN_DISP_D1D2_OV0_RST (1 << 23) -#define DISP_PWR_MAN_DIG_TMDS_ENABLE_RST (1 << 24) -#define DISP_PWR_MAN_TV_ENABLE_RST (1 << 25) -#define DISP_PWR_MAN_AUTO_PWRUP_EN (1 << 26) - -/* masks */ - -#define CNFG_MEMSIZE_MASK 0x1f000000 -#define MEM_CFG_TYPE 0x40000000 -#define DST_OFFSET_MASK 0x003fffff -#define DST_PITCH_MASK 0x3fc00000 -#define DEFAULT_TILE_MASK 0xc0000000 -#define PPLL_DIV_SEL_MASK 0x00000300 -#define PPLL_RESET 0x00000001 -#define PPLL_SLEEP 0x00000002 -#define PPLL_ATOMIC_UPDATE_EN 0x00010000 -#define PPLL_REF_DIV_MASK 0x000003ff -#define PPLL_FB3_DIV_MASK 0x000007ff -#define PPLL_POST3_DIV_MASK 0x00070000 -#define PPLL_ATOMIC_UPDATE_R 0x00008000 -#define PPLL_ATOMIC_UPDATE_W 0x00008000 -#define PPLL_VGA_ATOMIC_UPDATE_EN 0x00020000 -#define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18) -#define R300_PPLL_REF_DIV_ACC_SHIFT 18 - -#define GUI_ACTIVE 0x80000000 - - -#define MC_IND_INDEX 0x01F8 -#define MC_IND_DATA 0x01FC - -/* PAD_CTLR_STRENGTH */ -#define PAD_MANUAL_OVERRIDE 0x80000000 - -// pllCLK_PIN_CNTL -#define CLK_PIN_CNTL__OSC_EN_MASK 0x00000001L -#define CLK_PIN_CNTL__OSC_EN 0x00000001L -#define CLK_PIN_CNTL__XTL_LOW_GAIN_MASK 0x00000004L -#define CLK_PIN_CNTL__XTL_LOW_GAIN 0x00000004L -#define CLK_PIN_CNTL__DONT_USE_XTALIN_MASK 0x00000010L -#define CLK_PIN_CNTL__DONT_USE_XTALIN 0x00000010L -#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE_MASK 0x00000020L -#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE 0x00000020L -#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN_MASK 0x00000800L -#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN 0x00000800L -#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN_MASK 0x00001000L -#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN 0x00001000L -#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND_MASK 0x00002000L -#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND 0x00002000L -#define CLK_PIN_CNTL__CG_SPARE_MASK 0x00004000L -#define CLK_PIN_CNTL__CG_SPARE 0x00004000L -#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL_MASK 0x00008000L -#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL 0x00008000L -#define CLK_PIN_CNTL__CP_CLK_RUNNING_MASK 0x00010000L -#define CLK_PIN_CNTL__CP_CLK_RUNNING 0x00010000L -#define CLK_PIN_CNTL__CG_SPARE_RD_MASK 0x00060000L -#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb_MASK 0x00080000L -#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb 0x00080000L -#define CLK_PIN_CNTL__PWRSEQ_DELAY_MASK 0xff000000L - -// pllCLK_PWRMGT_CNTL -#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF__SHIFT 0x00000000 -#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF__SHIFT 0x00000001 -#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF__SHIFT 0x00000002 -#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF__SHIFT 0x00000003 -#define CLK_PWRMGT_CNTL__MCLK_TURNOFF__SHIFT 0x00000004 -#define CLK_PWRMGT_CNTL__SCLK_TURNOFF__SHIFT 0x00000005 -#define CLK_PWRMGT_CNTL__PCLK_TURNOFF__SHIFT 0x00000006 -#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF__SHIFT 0x00000007 -#define CLK_PWRMGT_CNTL__MC_CH_MODE__SHIFT 0x00000008 -#define CLK_PWRMGT_CNTL__TEST_MODE__SHIFT 0x00000009 -#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN__SHIFT 0x0000000a -#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE__SHIFT 0x0000000c -#define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT__SHIFT 0x0000000d -#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT__SHIFT 0x0000000f -#define CLK_PWRMGT_CNTL__MC_BUSY__SHIFT 0x00000010 -#define CLK_PWRMGT_CNTL__MC_INT_CNTL__SHIFT 0x00000011 -#define CLK_PWRMGT_CNTL__MC_SWITCH__SHIFT 0x00000012 -#define CLK_PWRMGT_CNTL__DLL_READY__SHIFT 0x00000013 -#define CLK_PWRMGT_CNTL__DISP_PM__SHIFT 0x00000014 -#define CLK_PWRMGT_CNTL__DYN_STOP_MODE__SHIFT 0x00000015 -#define CLK_PWRMGT_CNTL__CG_NO1_DEBUG__SHIFT 0x00000018 -#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF__SHIFT 0x0000001e -#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF__SHIFT 0x0000001f - -// pllP2PLL_CNTL -#define P2PLL_CNTL__P2PLL_RESET_MASK 0x00000001L -#define P2PLL_CNTL__P2PLL_RESET 0x00000001L -#define P2PLL_CNTL__P2PLL_SLEEP_MASK 0x00000002L -#define P2PLL_CNTL__P2PLL_SLEEP 0x00000002L -#define P2PLL_CNTL__P2PLL_TST_EN_MASK 0x00000004L -#define P2PLL_CNTL__P2PLL_TST_EN 0x00000004L -#define P2PLL_CNTL__P2PLL_REFCLK_SEL_MASK 0x00000010L -#define P2PLL_CNTL__P2PLL_REFCLK_SEL 0x00000010L -#define P2PLL_CNTL__P2PLL_FBCLK_SEL_MASK 0x00000020L -#define P2PLL_CNTL__P2PLL_FBCLK_SEL 0x00000020L -#define P2PLL_CNTL__P2PLL_TCPOFF_MASK 0x00000040L -#define P2PLL_CNTL__P2PLL_TCPOFF 0x00000040L -#define P2PLL_CNTL__P2PLL_TVCOMAX_MASK 0x00000080L -#define P2PLL_CNTL__P2PLL_TVCOMAX 0x00000080L -#define P2PLL_CNTL__P2PLL_PCP_MASK 0x00000700L -#define P2PLL_CNTL__P2PLL_PVG_MASK 0x00003800L -#define P2PLL_CNTL__P2PLL_PDC_MASK 0x0000c000L -#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN_MASK 0x00010000L -#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN 0x00010000L -#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC_MASK 0x00040000L -#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC 0x00040000L -#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET_MASK 0x00080000L -#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET 0x00080000L - -// pllPIXCLKS_CNTL -#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT 0x00000000 -#define PIXCLKS_CNTL__PIX2CLK_INVERT__SHIFT 0x00000004 -#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT__SHIFT 0x00000005 -#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb__SHIFT 0x00000006 -#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb__SHIFT 0x00000007 -#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL__SHIFT 0x00000008 -#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb__SHIFT 0x0000000b -#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb__SHIFT 0x0000000c -#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb__SHIFT 0x0000000d -#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb__SHIFT 0x0000000e -#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb__SHIFT 0x0000000f - - -// pllPIXCLKS_CNTL -#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK 0x00000003L -#define PIXCLKS_CNTL__PIX2CLK_INVERT 0x00000010L -#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT 0x00000020L -#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb 0x00000040L -#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb 0x00000080L -#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL 0x00000100L -#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb 0x00000800L -#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb 0x00001000L -#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb 0x00002000L -#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb 0x00004000L -#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb 0x00008000L -#define PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9) -#define PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb (1 << 10) -#define PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13) -#define PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16) -#define PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17) -#define PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb (1 << 18) -#define PIXCLKS_CNTL__R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19) -#define PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23) - - -// pllP2PLL_DIV_0 -#define P2PLL_DIV_0__P2PLL_FB_DIV_MASK 0x000007ffL -#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W_MASK 0x00008000L -#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W 0x00008000L -#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R_MASK 0x00008000L -#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R 0x00008000L -#define P2PLL_DIV_0__P2PLL_POST_DIV_MASK 0x00070000L - -// pllSCLK_CNTL -#define SCLK_CNTL__SCLK_SRC_SEL_MASK 0x00000007L -#define SCLK_CNTL__CP_MAX_DYN_STOP_LAT 0x00000008L -#define SCLK_CNTL__HDP_MAX_DYN_STOP_LAT 0x00000010L -#define SCLK_CNTL__TV_MAX_DYN_STOP_LAT 0x00000020L -#define SCLK_CNTL__E2_MAX_DYN_STOP_LAT 0x00000040L -#define SCLK_CNTL__SE_MAX_DYN_STOP_LAT 0x00000080L -#define SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT 0x00000100L -#define SCLK_CNTL__VIP_MAX_DYN_STOP_LAT 0x00000200L -#define SCLK_CNTL__RE_MAX_DYN_STOP_LAT 0x00000400L -#define SCLK_CNTL__PB_MAX_DYN_STOP_LAT 0x00000800L -#define SCLK_CNTL__TAM_MAX_DYN_STOP_LAT 0x00001000L -#define SCLK_CNTL__TDM_MAX_DYN_STOP_LAT 0x00002000L -#define SCLK_CNTL__RB_MAX_DYN_STOP_LAT 0x00004000L -#define SCLK_CNTL__DYN_STOP_LAT_MASK 0x00007ff8 -#define SCLK_CNTL__FORCE_DISP2 0x00008000L -#define SCLK_CNTL__FORCE_CP 0x00010000L -#define SCLK_CNTL__FORCE_HDP 0x00020000L -#define SCLK_CNTL__FORCE_DISP1 0x00040000L -#define SCLK_CNTL__FORCE_TOP 0x00080000L -#define SCLK_CNTL__FORCE_E2 0x00100000L -#define SCLK_CNTL__FORCE_SE 0x00200000L -#define SCLK_CNTL__FORCE_IDCT 0x00400000L -#define SCLK_CNTL__FORCE_VIP 0x00800000L -#define SCLK_CNTL__FORCE_RE 0x01000000L -#define SCLK_CNTL__FORCE_PB 0x02000000L -#define SCLK_CNTL__FORCE_TAM 0x04000000L -#define SCLK_CNTL__FORCE_TDM 0x08000000L -#define SCLK_CNTL__FORCE_RB 0x10000000L -#define SCLK_CNTL__FORCE_TV_SCLK 0x20000000L -#define SCLK_CNTL__FORCE_SUBPIC 0x40000000L -#define SCLK_CNTL__FORCE_OV0 0x80000000L -#define SCLK_CNTL__R300_FORCE_VAP (1<<21) -#define SCLK_CNTL__R300_FORCE_SR (1<<25) -#define SCLK_CNTL__R300_FORCE_PX (1<<26) -#define SCLK_CNTL__R300_FORCE_TX (1<<27) -#define SCLK_CNTL__R300_FORCE_US (1<<28) -#define SCLK_CNTL__R300_FORCE_SU (1<<30) -#define SCLK_CNTL__FORCEON_MASK 0xffff8000L - -// pllSCLK_CNTL2 -#define SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT (1<<10) -#define SCLK_CNTL2__R300_GA_MAX_DYN_STOP_LAT (1<<11) -#define SCLK_CNTL2__R300_CBA_MAX_DYN_STOP_LAT (1<<12) -#define SCLK_CNTL2__R300_FORCE_TCL (1<<13) -#define SCLK_CNTL2__R300_FORCE_CBA (1<<14) -#define SCLK_CNTL2__R300_FORCE_GA (1<<15) - -// SCLK_MORE_CNTL -#define SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT 0x00000001L -#define SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT 0x00000002L -#define SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT 0x00000004L -#define SCLK_MORE_CNTL__FORCE_DISPREGS 0x00000100L -#define SCLK_MORE_CNTL__FORCE_MC_GUI 0x00000200L -#define SCLK_MORE_CNTL__FORCE_MC_HOST 0x00000400L -#define SCLK_MORE_CNTL__STOP_SCLK_EN 0x00001000L -#define SCLK_MORE_CNTL__STOP_SCLK_A 0x00002000L -#define SCLK_MORE_CNTL__STOP_SCLK_B 0x00004000L -#define SCLK_MORE_CNTL__STOP_SCLK_C 0x00008000L -#define SCLK_MORE_CNTL__HALF_SPEED_SCLK 0x00010000L -#define SCLK_MORE_CNTL__IO_CG_VOLTAGE_DROP 0x00020000L -#define SCLK_MORE_CNTL__TVFB_SOFT_RESET 0x00040000L -#define SCLK_MORE_CNTL__VOLTAGE_DROP_SYNC 0x00080000L -#define SCLK_MORE_CNTL__IDLE_DELAY_HALF_SCLK 0x00400000L -#define SCLK_MORE_CNTL__AGP_BUSY_HALF_SCLK 0x00800000L -#define SCLK_MORE_CNTL__CG_SPARE_RD_C_MASK 0xff000000L -#define SCLK_MORE_CNTL__FORCEON 0x00000700L - -// MCLK_CNTL -#define MCLK_CNTL__MCLKA_SRC_SEL_MASK 0x00000007L -#define MCLK_CNTL__YCLKA_SRC_SEL_MASK 0x00000070L -#define MCLK_CNTL__MCLKB_SRC_SEL_MASK 0x00000700L -#define MCLK_CNTL__YCLKB_SRC_SEL_MASK 0x00007000L -#define MCLK_CNTL__FORCE_MCLKA_MASK 0x00010000L -#define MCLK_CNTL__FORCE_MCLKA 0x00010000L -#define MCLK_CNTL__FORCE_MCLKB_MASK 0x00020000L -#define MCLK_CNTL__FORCE_MCLKB 0x00020000L -#define MCLK_CNTL__FORCE_YCLKA_MASK 0x00040000L -#define MCLK_CNTL__FORCE_YCLKA 0x00040000L -#define MCLK_CNTL__FORCE_YCLKB_MASK 0x00080000L -#define MCLK_CNTL__FORCE_YCLKB 0x00080000L -#define MCLK_CNTL__FORCE_MC_MASK 0x00100000L -#define MCLK_CNTL__FORCE_MC 0x00100000L -#define MCLK_CNTL__FORCE_AIC_MASK 0x00200000L -#define MCLK_CNTL__FORCE_AIC 0x00200000L -#define MCLK_CNTL__MRDCKA0_SOUTSEL_MASK 0x03000000L -#define MCLK_CNTL__MRDCKA1_SOUTSEL_MASK 0x0c000000L -#define MCLK_CNTL__MRDCKB0_SOUTSEL_MASK 0x30000000L -#define MCLK_CNTL__MRDCKB1_SOUTSEL_MASK 0xc0000000L -#define MCLK_CNTL__R300_DISABLE_MC_MCLKA (1 << 21) -#define MCLK_CNTL__R300_DISABLE_MC_MCLKB (1 << 21) - -// MCLK_MISC -#define MCLK_MISC__SCLK_SOURCED_FROM_MPLL_SEL_MASK 0x00000003L -#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL_MASK 0x00000004L -#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL 0x00000004L -#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL_MASK 0x00000008L -#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL 0x00000008L -#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN_MASK 0x00000010L -#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN 0x00000010L -#define MCLK_MISC__DLL_READY_LAT_MASK 0x00000100L -#define MCLK_MISC__DLL_READY_LAT 0x00000100L -#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT_MASK 0x00001000L -#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT 0x00001000L -#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT_MASK 0x00002000L -#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT 0x00002000L -#define MCLK_MISC__MC_MCLK_DYN_ENABLE_MASK 0x00004000L -#define MCLK_MISC__MC_MCLK_DYN_ENABLE 0x00004000L -#define MCLK_MISC__IO_MCLK_DYN_ENABLE_MASK 0x00008000L -#define MCLK_MISC__IO_MCLK_DYN_ENABLE 0x00008000L -#define MCLK_MISC__CGM_CLK_TO_OUTPIN_MASK 0x00010000L -#define MCLK_MISC__CGM_CLK_TO_OUTPIN 0x00010000L -#define MCLK_MISC__CLK_OR_COUNT_SEL_MASK 0x00020000L -#define MCLK_MISC__CLK_OR_COUNT_SEL 0x00020000L -#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND_MASK 0x00040000L -#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND 0x00040000L -#define MCLK_MISC__CGM_SPARE_RD_MASK 0x00300000L -#define MCLK_MISC__CGM_SPARE_A_RD_MASK 0x00c00000L -#define MCLK_MISC__TCLK_TO_YCLKB_EN_MASK 0x01000000L -#define MCLK_MISC__TCLK_TO_YCLKB_EN 0x01000000L -#define MCLK_MISC__CGM_SPARE_A_MASK 0x0e000000L - -// VCLK_ECP_CNTL -#define VCLK_ECP_CNTL__VCLK_SRC_SEL_MASK 0x00000003L -#define VCLK_ECP_CNTL__VCLK_INVERT 0x00000010L -#define VCLK_ECP_CNTL__PIXCLK_SRC_INVERT 0x00000020L -#define VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb 0x00000040L -#define VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb 0x00000080L -#define VCLK_ECP_CNTL__ECP_DIV_MASK 0x00000300L -#define VCLK_ECP_CNTL__ECP_FORCE_ON 0x00040000L -#define VCLK_ECP_CNTL__SUBCLK_FORCE_ON 0x00080000L -#define VCLK_ECP_CNTL__R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23) - -// PLL_PWRMGT_CNTL -#define PLL_PWRMGT_CNTL__MPLL_TURNOFF_MASK 0x00000001L -#define PLL_PWRMGT_CNTL__MPLL_TURNOFF 0x00000001L -#define PLL_PWRMGT_CNTL__SPLL_TURNOFF_MASK 0x00000002L -#define PLL_PWRMGT_CNTL__SPLL_TURNOFF 0x00000002L -#define PLL_PWRMGT_CNTL__PPLL_TURNOFF_MASK 0x00000004L -#define PLL_PWRMGT_CNTL__PPLL_TURNOFF 0x00000004L -#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF_MASK 0x00000008L -#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF 0x00000008L -#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF_MASK 0x00000010L -#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF 0x00000010L -#define PLL_PWRMGT_CNTL__AGPCLK_DYN_STOP_LAT_MASK 0x000001e0L -#define PLL_PWRMGT_CNTL__APM_POWER_STATE_MASK 0x00000600L -#define PLL_PWRMGT_CNTL__APM_PWRSTATE_RD_MASK 0x00001800L -#define PLL_PWRMGT_CNTL__PM_MODE_SEL_MASK 0x00002000L -#define PLL_PWRMGT_CNTL__PM_MODE_SEL 0x00002000L -#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND_MASK 0x00004000L -#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND 0x00004000L -#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND_MASK 0x00008000L -#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND 0x00008000L -#define PLL_PWRMGT_CNTL__MOBILE_SU_MASK 0x00010000L -#define PLL_PWRMGT_CNTL__MOBILE_SU 0x00010000L -#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK_MASK 0x00020000L -#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK 0x00020000L -#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK_MASK 0x00040000L -#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK 0x00040000L -#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE_MASK 0x00080000L -#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE 0x00080000L -#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE_MASK 0x00100000L -#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE 0x00100000L -#define PLL_PWRMGT_CNTL__TCL_CLOCK_CTIVE_RD_MASK 0x00200000L -#define PLL_PWRMGT_CNTL__TCL_CLOCK_ACTIVE_RD 0x00200000L -#define PLL_PWRMGT_CNTL__CG_NO2_DEBUG_MASK 0xff000000L - -// CLK_PWRMGT_CNTL -#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF_MASK 0x00000001L -#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF 0x00000001L -#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF_MASK 0x00000002L -#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF 0x00000002L -#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF_MASK 0x00000004L -#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF 0x00000004L -#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF_MASK 0x00000008L -#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF 0x00000008L -#define CLK_PWRMGT_CNTL__MCLK_TURNOFF_MASK 0x00000010L -#define CLK_PWRMGT_CNTL__MCLK_TURNOFF 0x00000010L -#define CLK_PWRMGT_CNTL__SCLK_TURNOFF_MASK 0x00000020L -#define CLK_PWRMGT_CNTL__SCLK_TURNOFF 0x00000020L -#define CLK_PWRMGT_CNTL__PCLK_TURNOFF_MASK 0x00000040L -#define CLK_PWRMGT_CNTL__PCLK_TURNOFF 0x00000040L -#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF_MASK 0x00000080L -#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF 0x00000080L -#define CLK_PWRMGT_CNTL__MC_CH_MODE_MASK 0x00000100L -#define CLK_PWRMGT_CNTL__MC_CH_MODE 0x00000100L -#define CLK_PWRMGT_CNTL__TEST_MODE_MASK 0x00000200L -#define CLK_PWRMGT_CNTL__TEST_MODE 0x00000200L -#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN_MASK 0x00000400L -#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN 0x00000400L -#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE_MASK 0x00001000L -#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE 0x00001000L -#define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK 0x00006000L -#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT_MASK 0x00008000L -#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT 0x00008000L -#define CLK_PWRMGT_CNTL__MC_BUSY_MASK 0x00010000L -#define CLK_PWRMGT_CNTL__MC_BUSY 0x00010000L -#define CLK_PWRMGT_CNTL__MC_INT_CNTL_MASK 0x00020000L -#define CLK_PWRMGT_CNTL__MC_INT_CNTL 0x00020000L -#define CLK_PWRMGT_CNTL__MC_SWITCH_MASK 0x00040000L -#define CLK_PWRMGT_CNTL__MC_SWITCH 0x00040000L -#define CLK_PWRMGT_CNTL__DLL_READY_MASK 0x00080000L -#define CLK_PWRMGT_CNTL__DLL_READY 0x00080000L -#define CLK_PWRMGT_CNTL__DISP_PM_MASK 0x00100000L -#define CLK_PWRMGT_CNTL__DISP_PM 0x00100000L -#define CLK_PWRMGT_CNTL__DYN_STOP_MODE_MASK 0x00e00000L -#define CLK_PWRMGT_CNTL__CG_NO1_DEBUG_MASK 0x3f000000L -#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF_MASK 0x40000000L -#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF 0x40000000L -#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF_MASK 0x80000000L -#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF 0x80000000L - -// BUS_CNTL1 -#define BUS_CNTL1__PMI_IO_DISABLE_MASK 0x00000001L -#define BUS_CNTL1__PMI_IO_DISABLE 0x00000001L -#define BUS_CNTL1__PMI_MEM_DISABLE_MASK 0x00000002L -#define BUS_CNTL1__PMI_MEM_DISABLE 0x00000002L -#define BUS_CNTL1__PMI_BM_DISABLE_MASK 0x00000004L -#define BUS_CNTL1__PMI_BM_DISABLE 0x00000004L -#define BUS_CNTL1__PMI_INT_DISABLE_MASK 0x00000008L -#define BUS_CNTL1__PMI_INT_DISABLE 0x00000008L -#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE_MASK 0x00000020L -#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE 0x00000020L -#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS_MASK 0x00000100L -#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS 0x00000100L -#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS_MASK 0x00000200L -#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS 0x00000200L -#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS_MASK 0x00000400L -#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS 0x00000400L -#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS_MASK 0x00000800L -#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS 0x00000800L -#define BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK 0x0c000000L -#define BUS_CNTL1__SEND_SBA_LATENCY_MASK 0x70000000L -#define BUS_CNTL1__AGPCLK_VALID_MASK 0x80000000L -#define BUS_CNTL1__AGPCLK_VALID 0x80000000L - -// BUS_CNTL1 -#define BUS_CNTL1__PMI_IO_DISABLE__SHIFT 0x00000000 -#define BUS_CNTL1__PMI_MEM_DISABLE__SHIFT 0x00000001 -#define BUS_CNTL1__PMI_BM_DISABLE__SHIFT 0x00000002 -#define BUS_CNTL1__PMI_INT_DISABLE__SHIFT 0x00000003 -#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE__SHIFT 0x00000005 -#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS__SHIFT 0x00000008 -#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS__SHIFT 0x00000009 -#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS__SHIFT 0x0000000a -#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS__SHIFT 0x0000000b -#define BUS_CNTL1__MOBILE_PLATFORM_SEL__SHIFT 0x0000001a -#define BUS_CNTL1__SEND_SBA_LATENCY__SHIFT 0x0000001c -#define BUS_CNTL1__AGPCLK_VALID__SHIFT 0x0000001f - -// CRTC_OFFSET_CNTL -#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_MASK 0x0000000fL -#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_RIGHT_MASK 0x000000f0L -#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT_MASK 0x00004000L -#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT 0x00004000L -#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_MASK 0x00008000L -#define CRTC_OFFSET_CNTL__CRTC_TILE_EN 0x00008000L -#define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL_MASK 0x00010000L -#define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL 0x00010000L -#define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN_MASK 0x00020000L -#define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN 0x00020000L -#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_EN_MASK 0x000c0000L -#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN_MASK 0x00100000L -#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN 0x00100000L -#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_MASK 0x00200000L -#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC 0x00200000L -#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN_MASK 0x10000000L -#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN 0x10000000L -#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN_MASK 0x20000000L -#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN 0x20000000L -#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_MASK 0x40000000L -#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET 0x40000000L -#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK_MASK 0x80000000L -#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK 0x80000000L - -// CRTC_GEN_CNTL -#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN_MASK 0x00000001L -#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN 0x00000001L -#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN_MASK 0x00000002L -#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN 0x00000002L -#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN_MASK 0x00000010L -#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN 0x00000010L -#define CRTC_GEN_CNTL__CRTC_PIX_WIDTH_MASK 0x00000f00L -#define CRTC_GEN_CNTL__CRTC_ICON_EN_MASK 0x00008000L -#define CRTC_GEN_CNTL__CRTC_ICON_EN 0x00008000L -#define CRTC_GEN_CNTL__CRTC_CUR_EN_MASK 0x00010000L -#define CRTC_GEN_CNTL__CRTC_CUR_EN 0x00010000L -#define CRTC_GEN_CNTL__CRTC_VSTAT_MODE_MASK 0x00060000L -#define CRTC_GEN_CNTL__CRTC_CUR_MODE_MASK 0x00700000L -#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN_MASK 0x01000000L -#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN 0x01000000L -#define CRTC_GEN_CNTL__CRTC_EN_MASK 0x02000000L -#define CRTC_GEN_CNTL__CRTC_EN 0x02000000L -#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B_MASK 0x04000000L -#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B 0x04000000L - -// CRTC2_GEN_CNTL -#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN_MASK 0x00000001L -#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN 0x00000001L -#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN_MASK 0x00000002L -#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN 0x00000002L -#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE_MASK 0x00000010L -#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE 0x00000010L -#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE_MASK 0x00000020L -#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE 0x00000020L -#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE_MASK 0x00000040L -#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE 0x00000040L -#define CRTC2_GEN_CNTL__CRT2_ON_MASK 0x00000080L -#define CRTC2_GEN_CNTL__CRT2_ON 0x00000080L -#define CRTC2_GEN_CNTL__CRTC2_PIX_WIDTH_MASK 0x00000f00L -#define CRTC2_GEN_CNTL__CRTC2_ICON_EN_MASK 0x00008000L -#define CRTC2_GEN_CNTL__CRTC2_ICON_EN 0x00008000L -#define CRTC2_GEN_CNTL__CRTC2_CUR_EN_MASK 0x00010000L -#define CRTC2_GEN_CNTL__CRTC2_CUR_EN 0x00010000L -#define CRTC2_GEN_CNTL__CRTC2_CUR_MODE_MASK 0x00700000L -#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS_MASK 0x00800000L -#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS 0x00800000L -#define CRTC2_GEN_CNTL__CRTC2_EN_MASK 0x02000000L -#define CRTC2_GEN_CNTL__CRTC2_EN 0x02000000L -#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B_MASK 0x04000000L -#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B 0x04000000L -#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN_MASK 0x08000000L -#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN 0x08000000L -#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS_MASK 0x10000000L -#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS 0x10000000L -#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS_MASK 0x20000000L -#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS 0x20000000L - -// AGP_CNTL -#define AGP_CNTL__MAX_IDLE_CLK_MASK 0x000000ffL -#define AGP_CNTL__HOLD_RD_FIFO_MASK 0x00000100L -#define AGP_CNTL__HOLD_RD_FIFO 0x00000100L -#define AGP_CNTL__HOLD_RQ_FIFO_MASK 0x00000200L -#define AGP_CNTL__HOLD_RQ_FIFO 0x00000200L -#define AGP_CNTL__EN_2X_STBB_MASK 0x00000400L -#define AGP_CNTL__EN_2X_STBB 0x00000400L -#define AGP_CNTL__FORCE_FULL_SBA_MASK 0x00000800L -#define AGP_CNTL__FORCE_FULL_SBA 0x00000800L -#define AGP_CNTL__SBA_DIS_MASK 0x00001000L -#define AGP_CNTL__SBA_DIS 0x00001000L -#define AGP_CNTL__AGP_REV_ID_MASK 0x00002000L -#define AGP_CNTL__AGP_REV_ID 0x00002000L -#define AGP_CNTL__REG_CRIPPLE_AGP4X_MASK 0x00004000L -#define AGP_CNTL__REG_CRIPPLE_AGP4X 0x00004000L -#define AGP_CNTL__REG_CRIPPLE_AGP2X4X_MASK 0x00008000L -#define AGP_CNTL__REG_CRIPPLE_AGP2X4X 0x00008000L -#define AGP_CNTL__FORCE_INT_VREF_MASK 0x00010000L -#define AGP_CNTL__FORCE_INT_VREF 0x00010000L -#define AGP_CNTL__PENDING_SLOTS_VAL_MASK 0x00060000L -#define AGP_CNTL__PENDING_SLOTS_SEL_MASK 0x00080000L -#define AGP_CNTL__PENDING_SLOTS_SEL 0x00080000L -#define AGP_CNTL__EN_EXTENDED_AD_STB_2X_MASK 0x00100000L -#define AGP_CNTL__EN_EXTENDED_AD_STB_2X 0x00100000L -#define AGP_CNTL__DIS_QUEUED_GNT_FIX_MASK 0x00200000L -#define AGP_CNTL__DIS_QUEUED_GNT_FIX 0x00200000L -#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET_MASK 0x00400000L -#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET 0x00400000L -#define AGP_CNTL__EN_RBFCALM_MASK 0x00800000L -#define AGP_CNTL__EN_RBFCALM 0x00800000L -#define AGP_CNTL__FORCE_EXT_VREF_MASK 0x01000000L -#define AGP_CNTL__FORCE_EXT_VREF 0x01000000L -#define AGP_CNTL__DIS_RBF_MASK 0x02000000L -#define AGP_CNTL__DIS_RBF 0x02000000L -#define AGP_CNTL__DELAY_FIRST_SBA_EN_MASK 0x04000000L -#define AGP_CNTL__DELAY_FIRST_SBA_EN 0x04000000L -#define AGP_CNTL__DELAY_FIRST_SBA_VAL_MASK 0x38000000L -#define AGP_CNTL__AGP_MISC_MASK 0xc0000000L - -// AGP_CNTL -#define AGP_CNTL__MAX_IDLE_CLK__SHIFT 0x00000000 -#define AGP_CNTL__HOLD_RD_FIFO__SHIFT 0x00000008 -#define AGP_CNTL__HOLD_RQ_FIFO__SHIFT 0x00000009 -#define AGP_CNTL__EN_2X_STBB__SHIFT 0x0000000a -#define AGP_CNTL__FORCE_FULL_SBA__SHIFT 0x0000000b -#define AGP_CNTL__SBA_DIS__SHIFT 0x0000000c -#define AGP_CNTL__AGP_REV_ID__SHIFT 0x0000000d -#define AGP_CNTL__REG_CRIPPLE_AGP4X__SHIFT 0x0000000e -#define AGP_CNTL__REG_CRIPPLE_AGP2X4X__SHIFT 0x0000000f -#define AGP_CNTL__FORCE_INT_VREF__SHIFT 0x00000010 -#define AGP_CNTL__PENDING_SLOTS_VAL__SHIFT 0x00000011 -#define AGP_CNTL__PENDING_SLOTS_SEL__SHIFT 0x00000013 -#define AGP_CNTL__EN_EXTENDED_AD_STB_2X__SHIFT 0x00000014 -#define AGP_CNTL__DIS_QUEUED_GNT_FIX__SHIFT 0x00000015 -#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET__SHIFT 0x00000016 -#define AGP_CNTL__EN_RBFCALM__SHIFT 0x00000017 -#define AGP_CNTL__FORCE_EXT_VREF__SHIFT 0x00000018 -#define AGP_CNTL__DIS_RBF__SHIFT 0x00000019 -#define AGP_CNTL__DELAY_FIRST_SBA_EN__SHIFT 0x0000001a -#define AGP_CNTL__DELAY_FIRST_SBA_VAL__SHIFT 0x0000001b -#define AGP_CNTL__AGP_MISC__SHIFT 0x0000001e - -// DISP_MISC_CNTL -#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP_MASK 0x00000001L -#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP 0x00000001L -#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP_MASK 0x00000002L -#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP 0x00000002L -#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP_MASK 0x00000004L -#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP 0x00000004L -#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK_MASK 0x00000010L -#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK 0x00000010L -#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK_MASK 0x00000020L -#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK 0x00000020L -#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK_MASK 0x00000040L -#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK 0x00000040L -#define DISP_MISC_CNTL__SYNC_STRENGTH_MASK 0x00000300L -#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN_MASK 0x00000400L -#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN 0x00000400L -#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP_MASK 0x00001000L -#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP 0x00001000L -#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK_MASK 0x00008000L -#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK 0x00008000L -#define DISP_MISC_CNTL__SOFT_RESET_LVDS_MASK 0x00010000L -#define DISP_MISC_CNTL__SOFT_RESET_LVDS 0x00010000L -#define DISP_MISC_CNTL__SOFT_RESET_TMDS_MASK 0x00020000L -#define DISP_MISC_CNTL__SOFT_RESET_TMDS 0x00020000L -#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS_MASK 0x00040000L -#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS 0x00040000L -#define DISP_MISC_CNTL__SOFT_RESET_TV_MASK 0x00080000L -#define DISP_MISC_CNTL__SOFT_RESET_TV 0x00080000L -#define DISP_MISC_CNTL__PALETTE2_MEM_RD_MARGIN_MASK 0x00f00000L -#define DISP_MISC_CNTL__PALETTE_MEM_RD_MARGIN_MASK 0x0f000000L -#define DISP_MISC_CNTL__RMX_BUF_MEM_RD_MARGIN_MASK 0xf0000000L - -// DISP_PWR_MAN -#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK 0x00000001L -#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN 0x00000001L -#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK 0x00000010L -#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN 0x00000010L -#define DISP_PWR_MAN__DISP_PWR_MAN_DPMS_MASK 0x00000300L -#define DISP_PWR_MAN__DISP_D3_RST_MASK 0x00010000L -#define DISP_PWR_MAN__DISP_D3_RST 0x00010000L -#define DISP_PWR_MAN__DISP_D3_REG_RST_MASK 0x00020000L -#define DISP_PWR_MAN__DISP_D3_REG_RST 0x00020000L -#define DISP_PWR_MAN__DISP_D3_GRPH_RST_MASK 0x00040000L -#define DISP_PWR_MAN__DISP_D3_GRPH_RST 0x00040000L -#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST_MASK 0x00080000L -#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST 0x00080000L -#define DISP_PWR_MAN__DISP_D3_OV0_RST_MASK 0x00100000L -#define DISP_PWR_MAN__DISP_D3_OV0_RST 0x00100000L -#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST_MASK 0x00200000L -#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST 0x00200000L -#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST_MASK 0x00400000L -#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST 0x00400000L -#define DISP_PWR_MAN__DISP_D1D2_OV0_RST_MASK 0x00800000L -#define DISP_PWR_MAN__DISP_D1D2_OV0_RST 0x00800000L -#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST_MASK 0x01000000L -#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST 0x01000000L -#define DISP_PWR_MAN__TV_ENABLE_RST_MASK 0x02000000L -#define DISP_PWR_MAN__TV_ENABLE_RST 0x02000000L -#define DISP_PWR_MAN__AUTO_PWRUP_EN_MASK 0x04000000L -#define DISP_PWR_MAN__AUTO_PWRUP_EN 0x04000000L - -// MC_IND_INDEX -#define MC_IND_INDEX__MC_IND_ADDR_MASK 0x0000001fL -#define MC_IND_INDEX__MC_IND_WR_EN_MASK 0x00000100L -#define MC_IND_INDEX__MC_IND_WR_EN 0x00000100L - -// MC_IND_DATA -#define MC_IND_DATA__MC_IND_DATA_MASK 0xffffffffL - -// MC_CHP_IO_CNTL_A1 -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA__SHIFT 0x00000000 -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA__SHIFT 0x00000001 -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA__SHIFT 0x00000002 -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA__SHIFT 0x00000003 -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA__SHIFT 0x00000004 -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA__SHIFT 0x00000005 -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA__SHIFT 0x00000006 -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA__SHIFT 0x00000007 -#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA__SHIFT 0x00000008 -#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA__SHIFT 0x00000009 -#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA__SHIFT 0x0000000a -#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA__SHIFT 0x0000000c -#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA__SHIFT 0x0000000e -#define MC_CHP_IO_CNTL_A1__MEM_REC_AA__SHIFT 0x00000010 -#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA__SHIFT 0x00000012 -#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA__SHIFT 0x00000014 -#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA__SHIFT 0x00000016 -#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA__SHIFT 0x00000017 -#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT 0x00000018 -#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA__SHIFT 0x0000001a -#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA__SHIFT 0x0000001c -#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A__SHIFT 0x0000001e -#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A__SHIFT 0x0000001f - -// MC_CHP_IO_CNTL_B1 -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB__SHIFT 0x00000000 -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB__SHIFT 0x00000001 -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB__SHIFT 0x00000002 -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB__SHIFT 0x00000003 -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB__SHIFT 0x00000004 -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB__SHIFT 0x00000005 -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB__SHIFT 0x00000006 -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB__SHIFT 0x00000007 -#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB__SHIFT 0x00000008 -#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB__SHIFT 0x00000009 -#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB__SHIFT 0x0000000a -#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB__SHIFT 0x0000000c -#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB__SHIFT 0x0000000e -#define MC_CHP_IO_CNTL_B1__MEM_REC_AB__SHIFT 0x00000010 -#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB__SHIFT 0x00000012 -#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB__SHIFT 0x00000014 -#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB__SHIFT 0x00000016 -#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB__SHIFT 0x00000017 -#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT 0x00000018 -#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB__SHIFT 0x0000001a -#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB__SHIFT 0x0000001c -#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B__SHIFT 0x0000001e -#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B__SHIFT 0x0000001f - -// MC_CHP_IO_CNTL_A1 -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA_MASK 0x00000001L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA 0x00000001L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA_MASK 0x00000002L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA 0x00000002L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA_MASK 0x00000004L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA 0x00000004L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA_MASK 0x00000008L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA 0x00000008L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA_MASK 0x00000010L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA 0x00000010L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA_MASK 0x00000020L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA 0x00000020L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA_MASK 0x00000040L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA 0x00000040L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA_MASK 0x00000080L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA 0x00000080L -#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA_MASK 0x00000100L -#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA 0x00000100L -#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA_MASK 0x00000200L -#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA 0x00000200L -#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA_MASK 0x00000400L -#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA 0x00000400L -#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA_MASK 0x00003000L -#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA_MASK 0x0000c000L -#define MC_CHP_IO_CNTL_A1__MEM_REC_AA_MASK 0x00030000L -#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA_MASK 0x000c0000L -#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA_MASK 0x00300000L -#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA_MASK 0x00400000L -#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA 0x00400000L -#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA_MASK 0x00800000L -#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA 0x00800000L -#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK 0x03000000L -#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA_MASK 0x0c000000L -#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA_MASK 0x10000000L -#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA 0x10000000L -#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A_MASK 0x40000000L -#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A 0x40000000L -#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A_MASK 0x80000000L -#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A 0x80000000L - -// MC_CHP_IO_CNTL_B1 -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB_MASK 0x00000001L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB 0x00000001L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB_MASK 0x00000002L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB 0x00000002L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB_MASK 0x00000004L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB 0x00000004L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB_MASK 0x00000008L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB 0x00000008L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB_MASK 0x00000010L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB 0x00000010L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB_MASK 0x00000020L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB 0x00000020L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB_MASK 0x00000040L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB 0x00000040L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB_MASK 0x00000080L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB 0x00000080L -#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB_MASK 0x00000100L -#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB 0x00000100L -#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB_MASK 0x00000200L -#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB 0x00000200L -#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB_MASK 0x00000400L -#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB 0x00000400L -#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB_MASK 0x00003000L -#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB_MASK 0x0000c000L -#define MC_CHP_IO_CNTL_B1__MEM_REC_AB_MASK 0x00030000L -#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB_MASK 0x000c0000L -#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB_MASK 0x00300000L -#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB_MASK 0x00400000L -#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB 0x00400000L -#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB_MASK 0x00800000L -#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB 0x00800000L -#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK 0x03000000L -#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB_MASK 0x0c000000L -#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB_MASK 0x10000000L -#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB 0x10000000L -#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B_MASK 0x40000000L -#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B 0x40000000L -#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B_MASK 0x80000000L -#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B 0x80000000L - -// MEM_SDRAM_MODE_REG -#define MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK 0x00007fffL -#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY_MASK 0x000f0000L -#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY_MASK 0x00700000L -#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY_MASK 0x00800000L -#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY 0x00800000L -#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY_MASK 0x01000000L -#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY 0x01000000L -#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD_MASK 0x02000000L -#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD 0x02000000L -#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA_MASK 0x04000000L -#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA 0x04000000L -#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR_MASK 0x08000000L -#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR 0x08000000L -#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE_MASK 0x10000000L -#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE 0x10000000L -#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL_MASK 0x20000000L -#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL 0x20000000L -#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE_MASK 0x40000000L -#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE 0x40000000L -#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET_MASK 0x80000000L -#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET 0x80000000L - -// MEM_SDRAM_MODE_REG -#define MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT 0x00000000 -#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY__SHIFT 0x00000010 -#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY__SHIFT 0x00000014 -#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY__SHIFT 0x00000017 -#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY__SHIFT 0x00000018 -#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD__SHIFT 0x00000019 -#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA__SHIFT 0x0000001a -#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR__SHIFT 0x0000001b -#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE__SHIFT 0x0000001c -#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL__SHIFT 0x0000001d -#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE__SHIFT 0x0000001e -#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET__SHIFT 0x0000001f - -// MEM_REFRESH_CNTL -#define MEM_REFRESH_CNTL__MEM_REFRESH_RATE_MASK 0x000000ffL -#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS_MASK 0x00000100L -#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS 0x00000100L -#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE_MASK 0x00000200L -#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE 0x00000200L -#define MEM_REFRESH_CNTL__MEM_TRFC_MASK 0x0000f000L -#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE_MASK 0x00010000L -#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE 0x00010000L -#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE_MASK 0x00020000L -#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE 0x00020000L -#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE_MASK 0x00040000L -#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE 0x00040000L -#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE_MASK 0x00080000L -#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE 0x00080000L -#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE_MASK 0x00100000L -#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE 0x00100000L -#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKA_MASK 0x00c00000L -#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE_MASK 0x01000000L -#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE 0x01000000L -#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE_MASK 0x02000000L -#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE 0x02000000L -#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE_MASK 0x04000000L -#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE 0x04000000L -#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE_MASK 0x08000000L -#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE 0x08000000L -#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE_MASK 0x10000000L -#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE 0x10000000L -#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKB_MASK 0xc0000000L - -// MC_STATUS -#define MC_STATUS__MEM_PWRUP_COMPL_A_MASK 0x00000001L -#define MC_STATUS__MEM_PWRUP_COMPL_A 0x00000001L -#define MC_STATUS__MEM_PWRUP_COMPL_B_MASK 0x00000002L -#define MC_STATUS__MEM_PWRUP_COMPL_B 0x00000002L -#define MC_STATUS__MC_IDLE_MASK 0x00000004L -#define MC_STATUS__MC_IDLE 0x00000004L -#define MC_STATUS__IMP_N_VALUE_R_BACK_MASK 0x00000078L -#define MC_STATUS__IMP_P_VALUE_R_BACK_MASK 0x00000780L -#define MC_STATUS__TEST_OUT_R_BACK_MASK 0x00000800L -#define MC_STATUS__TEST_OUT_R_BACK 0x00000800L -#define MC_STATUS__DUMMY_OUT_R_BACK_MASK 0x00001000L -#define MC_STATUS__DUMMY_OUT_R_BACK 0x00001000L -#define MC_STATUS__IMP_N_VALUE_A_R_BACK_MASK 0x0001e000L -#define MC_STATUS__IMP_P_VALUE_A_R_BACK_MASK 0x001e0000L -#define MC_STATUS__IMP_N_VALUE_CK_R_BACK_MASK 0x01e00000L -#define MC_STATUS__IMP_P_VALUE_CK_R_BACK_MASK 0x1e000000L - -// MDLL_CKO -#define MDLL_CKO__MCKOA_SLEEP_MASK 0x00000001L -#define MDLL_CKO__MCKOA_SLEEP 0x00000001L -#define MDLL_CKO__MCKOA_RESET_MASK 0x00000002L -#define MDLL_CKO__MCKOA_RESET 0x00000002L -#define MDLL_CKO__MCKOA_RANGE_MASK 0x0000000cL -#define MDLL_CKO__ERSTA_SOUTSEL_MASK 0x00000030L -#define MDLL_CKO__MCKOA_FB_SEL_MASK 0x000000c0L -#define MDLL_CKO__MCKOA_REF_SKEW_MASK 0x00000700L -#define MDLL_CKO__MCKOA_FB_SKEW_MASK 0x00007000L -#define MDLL_CKO__MCKOA_BP_SEL_MASK 0x00008000L -#define MDLL_CKO__MCKOA_BP_SEL 0x00008000L -#define MDLL_CKO__MCKOB_SLEEP_MASK 0x00010000L -#define MDLL_CKO__MCKOB_SLEEP 0x00010000L -#define MDLL_CKO__MCKOB_RESET_MASK 0x00020000L -#define MDLL_CKO__MCKOB_RESET 0x00020000L -#define MDLL_CKO__MCKOB_RANGE_MASK 0x000c0000L -#define MDLL_CKO__ERSTB_SOUTSEL_MASK 0x00300000L -#define MDLL_CKO__MCKOB_FB_SEL_MASK 0x00c00000L -#define MDLL_CKO__MCKOB_REF_SKEW_MASK 0x07000000L -#define MDLL_CKO__MCKOB_FB_SKEW_MASK 0x70000000L -#define MDLL_CKO__MCKOB_BP_SEL_MASK 0x80000000L -#define MDLL_CKO__MCKOB_BP_SEL 0x80000000L - -// MDLL_RDCKA -#define MDLL_RDCKA__MRDCKA0_SLEEP_MASK 0x00000001L -#define MDLL_RDCKA__MRDCKA0_SLEEP 0x00000001L -#define MDLL_RDCKA__MRDCKA0_RESET_MASK 0x00000002L -#define MDLL_RDCKA__MRDCKA0_RESET 0x00000002L -#define MDLL_RDCKA__MRDCKA0_RANGE_MASK 0x0000000cL -#define MDLL_RDCKA__MRDCKA0_REF_SEL_MASK 0x00000030L -#define MDLL_RDCKA__MRDCKA0_FB_SEL_MASK 0x000000c0L -#define MDLL_RDCKA__MRDCKA0_REF_SKEW_MASK 0x00000700L -#define MDLL_RDCKA__MRDCKA0_SINSEL_MASK 0x00000800L -#define MDLL_RDCKA__MRDCKA0_SINSEL 0x00000800L -#define MDLL_RDCKA__MRDCKA0_FB_SKEW_MASK 0x00007000L -#define MDLL_RDCKA__MRDCKA0_BP_SEL_MASK 0x00008000L -#define MDLL_RDCKA__MRDCKA0_BP_SEL 0x00008000L -#define MDLL_RDCKA__MRDCKA1_SLEEP_MASK 0x00010000L -#define MDLL_RDCKA__MRDCKA1_SLEEP 0x00010000L -#define MDLL_RDCKA__MRDCKA1_RESET_MASK 0x00020000L -#define MDLL_RDCKA__MRDCKA1_RESET 0x00020000L -#define MDLL_RDCKA__MRDCKA1_RANGE_MASK 0x000c0000L -#define MDLL_RDCKA__MRDCKA1_REF_SEL_MASK 0x00300000L -#define MDLL_RDCKA__MRDCKA1_FB_SEL_MASK 0x00c00000L -#define MDLL_RDCKA__MRDCKA1_REF_SKEW_MASK 0x07000000L -#define MDLL_RDCKA__MRDCKA1_SINSEL_MASK 0x08000000L -#define MDLL_RDCKA__MRDCKA1_SINSEL 0x08000000L -#define MDLL_RDCKA__MRDCKA1_FB_SKEW_MASK 0x70000000L -#define MDLL_RDCKA__MRDCKA1_BP_SEL_MASK 0x80000000L -#define MDLL_RDCKA__MRDCKA1_BP_SEL 0x80000000L - -// MDLL_RDCKB -#define MDLL_RDCKB__MRDCKB0_SLEEP_MASK 0x00000001L -#define MDLL_RDCKB__MRDCKB0_SLEEP 0x00000001L -#define MDLL_RDCKB__MRDCKB0_RESET_MASK 0x00000002L -#define MDLL_RDCKB__MRDCKB0_RESET 0x00000002L -#define MDLL_RDCKB__MRDCKB0_RANGE_MASK 0x0000000cL -#define MDLL_RDCKB__MRDCKB0_REF_SEL_MASK 0x00000030L -#define MDLL_RDCKB__MRDCKB0_FB_SEL_MASK 0x000000c0L -#define MDLL_RDCKB__MRDCKB0_REF_SKEW_MASK 0x00000700L -#define MDLL_RDCKB__MRDCKB0_SINSEL_MASK 0x00000800L -#define MDLL_RDCKB__MRDCKB0_SINSEL 0x00000800L -#define MDLL_RDCKB__MRDCKB0_FB_SKEW_MASK 0x00007000L -#define MDLL_RDCKB__MRDCKB0_BP_SEL_MASK 0x00008000L -#define MDLL_RDCKB__MRDCKB0_BP_SEL 0x00008000L -#define MDLL_RDCKB__MRDCKB1_SLEEP_MASK 0x00010000L -#define MDLL_RDCKB__MRDCKB1_SLEEP 0x00010000L -#define MDLL_RDCKB__MRDCKB1_RESET_MASK 0x00020000L -#define MDLL_RDCKB__MRDCKB1_RESET 0x00020000L -#define MDLL_RDCKB__MRDCKB1_RANGE_MASK 0x000c0000L -#define MDLL_RDCKB__MRDCKB1_REF_SEL_MASK 0x00300000L -#define MDLL_RDCKB__MRDCKB1_FB_SEL_MASK 0x00c00000L -#define MDLL_RDCKB__MRDCKB1_REF_SKEW_MASK 0x07000000L -#define MDLL_RDCKB__MRDCKB1_SINSEL_MASK 0x08000000L -#define MDLL_RDCKB__MRDCKB1_SINSEL 0x08000000L -#define MDLL_RDCKB__MRDCKB1_FB_SKEW_MASK 0x70000000L -#define MDLL_RDCKB__MRDCKB1_BP_SEL_MASK 0x80000000L -#define MDLL_RDCKB__MRDCKB1_BP_SEL 0x80000000L - -#define MDLL_R300_RDCK__MRDCKA_SLEEP 0x00000001L -#define MDLL_R300_RDCK__MRDCKA_RESET 0x00000002L -#define MDLL_R300_RDCK__MRDCKB_SLEEP 0x00000004L -#define MDLL_R300_RDCK__MRDCKB_RESET 0x00000008L -#define MDLL_R300_RDCK__MRDCKC_SLEEP 0x00000010L -#define MDLL_R300_RDCK__MRDCKC_RESET 0x00000020L -#define MDLL_R300_RDCK__MRDCKD_SLEEP 0x00000040L -#define MDLL_R300_RDCK__MRDCKD_RESET 0x00000080L - -#define pllCLK_PIN_CNTL 0x0001 -#define pllPPLL_CNTL 0x0002 -#define pllPPLL_REF_DIV 0x0003 -#define pllPPLL_DIV_0 0x0004 -#define pllPPLL_DIV_1 0x0005 -#define pllPPLL_DIV_2 0x0006 -#define pllPPLL_DIV_3 0x0007 -#define pllVCLK_ECP_CNTL 0x0008 -#define pllHTOTAL_CNTL 0x0009 -#define pllM_SPLL_REF_FB_DIV 0x000A -#define pllAGP_PLL_CNTL 0x000B -#define pllSPLL_CNTL 0x000C -#define pllSCLK_CNTL 0x000D -#define pllMPLL_CNTL 0x000E -#define pllMDLL_CKO 0x000F -#define pllMDLL_RDCKA 0x0010 -#define pllMDLL_RDCKB 0x0011 -#define pllMCLK_CNTL 0x0012 -#define pllPLL_TEST_CNTL 0x0013 -#define pllCLK_PWRMGT_CNTL 0x0014 -#define pllPLL_PWRMGT_CNTL 0x0015 -#define pllCG_TEST_MACRO_RW_WRITE 0x0016 -#define pllCG_TEST_MACRO_RW_READ 0x0017 -#define pllCG_TEST_MACRO_RW_DATA 0x0018 -#define pllCG_TEST_MACRO_RW_CNTL 0x0019 -#define pllDISP_TEST_MACRO_RW_WRITE 0x001A -#define pllDISP_TEST_MACRO_RW_READ 0x001B -#define pllDISP_TEST_MACRO_RW_DATA 0x001C -#define pllDISP_TEST_MACRO_RW_CNTL 0x001D -#define pllSCLK_CNTL2 0x001E -#define pllMCLK_MISC 0x001F -#define pllTV_PLL_FINE_CNTL 0x0020 -#define pllTV_PLL_CNTL 0x0021 -#define pllTV_PLL_CNTL1 0x0022 -#define pllTV_DTO_INCREMENTS 0x0023 -#define pllSPLL_AUX_CNTL 0x0024 -#define pllMPLL_AUX_CNTL 0x0025 -#define pllP2PLL_CNTL 0x002A -#define pllP2PLL_REF_DIV 0x002B -#define pllP2PLL_DIV_0 0x002C -#define pllPIXCLKS_CNTL 0x002D -#define pllHTOTAL2_CNTL 0x002E -#define pllSSPLL_CNTL 0x0030 -#define pllSSPLL_REF_DIV 0x0031 -#define pllSSPLL_DIV_0 0x0032 -#define pllSS_INT_CNTL 0x0033 -#define pllSS_TST_CNTL 0x0034 -#define pllSCLK_MORE_CNTL 0x0035 - -#define ixMC_PERF_CNTL 0x0000 -#define ixMC_PERF_SEL 0x0001 -#define ixMC_PERF_REGION_0 0x0002 -#define ixMC_PERF_REGION_1 0x0003 -#define ixMC_PERF_COUNT_0 0x0004 -#define ixMC_PERF_COUNT_1 0x0005 -#define ixMC_PERF_COUNT_2 0x0006 -#define ixMC_PERF_COUNT_3 0x0007 -#define ixMC_PERF_COUNT_MEMCH_A 0x0008 -#define ixMC_PERF_COUNT_MEMCH_B 0x0009 -#define ixMC_IMP_CNTL 0x000A -#define ixMC_CHP_IO_CNTL_A0 0x000B -#define ixMC_CHP_IO_CNTL_A1 0x000C -#define ixMC_CHP_IO_CNTL_B0 0x000D -#define ixMC_CHP_IO_CNTL_B1 0x000E -#define ixMC_IMP_CNTL_0 0x000F -#define ixTC_MISMATCH_1 0x0010 -#define ixTC_MISMATCH_2 0x0011 -#define ixMC_BIST_CTRL 0x0012 -#define ixREG_COLLAR_WRITE 0x0013 -#define ixREG_COLLAR_READ 0x0014 -#define ixR300_MC_IMP_CNTL 0x0018 -#define ixR300_MC_CHP_IO_CNTL_A0 0x0019 -#define ixR300_MC_CHP_IO_CNTL_A1 0x001a -#define ixR300_MC_CHP_IO_CNTL_B0 0x001b -#define ixR300_MC_CHP_IO_CNTL_B1 0x001c -#define ixR300_MC_CHP_IO_CNTL_C0 0x001d -#define ixR300_MC_CHP_IO_CNTL_C1 0x001e -#define ixR300_MC_CHP_IO_CNTL_D0 0x001f -#define ixR300_MC_CHP_IO_CNTL_D1 0x0020 -#define ixR300_MC_IMP_CNTL_0 0x0021 -#define ixR300_MC_ELPIDA_CNTL 0x0022 -#define ixR300_MC_CHP_IO_OE_CNTL_CD 0x0023 -#define ixR300_MC_READ_CNTL_CD 0x0024 -#define ixR300_MC_MC_INIT_WR_LAT_TIMER 0x0025 -#define ixR300_MC_DEBUG_CNTL 0x0026 -#define ixR300_MC_BIST_CNTL_0 0x0028 -#define ixR300_MC_BIST_CNTL_1 0x0029 -#define ixR300_MC_BIST_CNTL_2 0x002a -#define ixR300_MC_BIST_CNTL_3 0x002b -#define ixR300_MC_BIST_CNTL_4 0x002c -#define ixR300_MC_BIST_CNTL_5 0x002d -#define ixR300_MC_IMP_STATUS 0x002e -#define ixR300_MC_DLL_CNTL 0x002f -#define NB_TOM 0x15C - - -#endif /* _RADEON_H */ - diff --git a/ANDROID_3.4.5/include/video/s1d13xxxfb.h b/ANDROID_3.4.5/include/video/s1d13xxxfb.h deleted file mode 100644 index 55f53449..00000000 --- a/ANDROID_3.4.5/include/video/s1d13xxxfb.h +++ /dev/null @@ -1,174 +0,0 @@ -/* include/video/s1d13xxxfb.h - * - * (c) 2004 Simtec Electronics - * (c) 2005 Thibaut VARENE <varenet@parisc-linux.org> - * - * Header file for Epson S1D13XXX driver code - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive for - * more details. - */ - -#ifndef S1D13XXXFB_H -#define S1D13XXXFB_H - -#define S1D_PALETTE_SIZE 256 -#define S1D_FBID "S1D13xxx" -#define S1D_DEVICENAME "s1d13xxxfb" - -/* S1DREG_REV_CODE register = prod_id (6 bits) + revision (2 bits) */ -#define S1D13505_PROD_ID 0x3 /* 000011 */ -#define S1D13506_PROD_ID 0x4 /* 000100 */ -#define S1D13806_PROD_ID 0x7 /* 000111 */ - -/* register definitions (tested on s1d13896) */ -#define S1DREG_REV_CODE 0x0000 /* Prod + Rev Code Register */ -#define S1DREG_MISC 0x0001 /* Miscellaneous Register */ -#define S1DREG_GPIO_CNF0 0x0004 /* General IO Pins Configuration Register 0 */ -#define S1DREG_GPIO_CNF1 0x0005 /* General IO Pins Configuration Register 1 */ -#define S1DREG_GPIO_CTL0 0x0008 /* General IO Pins Control Register 0 */ -#define S1DREG_GPIO_CTL1 0x0009 /* General IO Pins Control Register 1 */ -#define S1DREG_CNF_STATUS 0x000C /* Configuration Status Readback Register */ -#define S1DREG_CLK_CNF 0x0010 /* Memory Clock Configuration Register */ -#define S1DREG_LCD_CLK_CNF 0x0014 /* LCD Pixel Clock Configuration Register */ -#define S1DREG_CRT_CLK_CNF 0x0018 /* CRT/TV Pixel Clock Configuration Register */ -#define S1DREG_MPLUG_CLK_CNF 0x001C /* MediaPlug Clock Configuration Register */ -#define S1DREG_CPU2MEM_WST_SEL 0x001E /* CPU To Memory Wait State Select Register */ -#define S1DREG_MEM_CNF 0x0020 /* Memory Configuration Register */ -#define S1DREG_SDRAM_REF_RATE 0x0021 /* SDRAM Refresh Rate Register */ -#define S1DREG_SDRAM_TC0 0x002A /* SDRAM Timing Control Register 0 */ -#define S1DREG_SDRAM_TC1 0x002B /* SDRAM Timing Control Register 1 */ -#define S1DREG_PANEL_TYPE 0x0030 /* Panel Type Register */ -#define S1DREG_MOD_RATE 0x0031 /* MOD Rate Register */ -#define S1DREG_LCD_DISP_HWIDTH 0x0032 /* LCD Horizontal Display Width Register: ((val)+1)*8)=pix/line */ -#define S1DREG_LCD_NDISP_HPER 0x0034 /* LCD Horizontal Non-Display Period Register: ((val)+1)*8)=NDpix/line */ -#define S1DREG_TFT_FPLINE_START 0x0035 /* TFT FPLINE Start Position Register */ -#define S1DREG_TFT_FPLINE_PWIDTH 0x0036 /* TFT FPLINE Pulse Width Register. */ -#define S1DREG_LCD_DISP_VHEIGHT0 0x0038 /* LCD Vertical Display Height Register 0 */ -#define S1DREG_LCD_DISP_VHEIGHT1 0x0039 /* LCD Vertical Display Height Register 1 */ -#define S1DREG_LCD_NDISP_VPER 0x003A /* LCD Vertical Non-Display Period Register: (val)+1=NDlines */ -#define S1DREG_TFT_FPFRAME_START 0x003B /* TFT FPFRAME Start Position Register */ -#define S1DREG_TFT_FPFRAME_PWIDTH 0x003C /* TFT FPFRAME Pulse Width Register */ -#define S1DREG_LCD_DISP_MODE 0x0040 /* LCD Display Mode Register */ -#define S1DREG_LCD_MISC 0x0041 /* LCD Miscellaneous Register */ -#define S1DREG_LCD_DISP_START0 0x0042 /* LCD Display Start Address Register 0 */ -#define S1DREG_LCD_DISP_START1 0x0043 /* LCD Display Start Address Register 1 */ -#define S1DREG_LCD_DISP_START2 0x0044 /* LCD Display Start Address Register 2 */ -#define S1DREG_LCD_MEM_OFF0 0x0046 /* LCD Memory Address Offset Register 0 */ -#define S1DREG_LCD_MEM_OFF1 0x0047 /* LCD Memory Address Offset Register 1 */ -#define S1DREG_LCD_PIX_PAN 0x0048 /* LCD Pixel Panning Register */ -#define S1DREG_LCD_DISP_FIFO_HTC 0x004A /* LCD Display FIFO High Threshold Control Register */ -#define S1DREG_LCD_DISP_FIFO_LTC 0x004B /* LCD Display FIFO Low Threshold Control Register */ -#define S1DREG_CRT_DISP_HWIDTH 0x0050 /* CRT/TV Horizontal Display Width Register: ((val)+1)*8)=pix/line */ -#define S1DREG_CRT_NDISP_HPER 0x0052 /* CRT/TV Horizontal Non-Display Period Register */ -#define S1DREG_CRT_HRTC_START 0x0053 /* CRT/TV HRTC Start Position Register */ -#define S1DREG_CRT_HRTC_PWIDTH 0x0054 /* CRT/TV HRTC Pulse Width Register */ -#define S1DREG_CRT_DISP_VHEIGHT0 0x0056 /* CRT/TV Vertical Display Height Register 0 */ -#define S1DREG_CRT_DISP_VHEIGHT1 0x0057 /* CRT/TV Vertical Display Height Register 1 */ -#define S1DREG_CRT_NDISP_VPER 0x0058 /* CRT/TV Vertical Non-Display Period Register */ -#define S1DREG_CRT_VRTC_START 0x0059 /* CRT/TV VRTC Start Position Register */ -#define S1DREG_CRT_VRTC_PWIDTH 0x005A /* CRT/TV VRTC Pulse Width Register */ -#define S1DREG_TV_OUT_CTL 0x005B /* TV Output Control Register */ -#define S1DREG_CRT_DISP_MODE 0x0060 /* CRT/TV Display Mode Register */ -#define S1DREG_CRT_DISP_START0 0x0062 /* CRT/TV Display Start Address Register 0 */ -#define S1DREG_CRT_DISP_START1 0x0063 /* CRT/TV Display Start Address Register 1 */ -#define S1DREG_CRT_DISP_START2 0x0064 /* CRT/TV Display Start Address Register 2 */ -#define S1DREG_CRT_MEM_OFF0 0x0066 /* CRT/TV Memory Address Offset Register 0 */ -#define S1DREG_CRT_MEM_OFF1 0x0067 /* CRT/TV Memory Address Offset Register 1 */ -#define S1DREG_CRT_PIX_PAN 0x0068 /* CRT/TV Pixel Panning Register */ -#define S1DREG_CRT_DISP_FIFO_HTC 0x006A /* CRT/TV Display FIFO High Threshold Control Register */ -#define S1DREG_CRT_DISP_FIFO_LTC 0x006B /* CRT/TV Display FIFO Low Threshold Control Register */ -#define S1DREG_LCD_CUR_CTL 0x0070 /* LCD Ink/Cursor Control Register */ -#define S1DREG_LCD_CUR_START 0x0071 /* LCD Ink/Cursor Start Address Register */ -#define S1DREG_LCD_CUR_XPOS0 0x0072 /* LCD Cursor X Position Register 0 */ -#define S1DREG_LCD_CUR_XPOS1 0x0073 /* LCD Cursor X Position Register 1 */ -#define S1DREG_LCD_CUR_YPOS0 0x0074 /* LCD Cursor Y Position Register 0 */ -#define S1DREG_LCD_CUR_YPOS1 0x0075 /* LCD Cursor Y Position Register 1 */ -#define S1DREG_LCD_CUR_BCTL0 0x0076 /* LCD Ink/Cursor Blue Color 0 Register */ -#define S1DREG_LCD_CUR_GCTL0 0x0077 /* LCD Ink/Cursor Green Color 0 Register */ -#define S1DREG_LCD_CUR_RCTL0 0x0078 /* LCD Ink/Cursor Red Color 0 Register */ -#define S1DREG_LCD_CUR_BCTL1 0x007A /* LCD Ink/Cursor Blue Color 1 Register */ -#define S1DREG_LCD_CUR_GCTL1 0x007B /* LCD Ink/Cursor Green Color 1 Register */ -#define S1DREG_LCD_CUR_RCTL1 0x007C /* LCD Ink/Cursor Red Color 1 Register */ -#define S1DREG_LCD_CUR_FIFO_HTC 0x007E /* LCD Ink/Cursor FIFO High Threshold Register */ -#define S1DREG_CRT_CUR_CTL 0x0080 /* CRT/TV Ink/Cursor Control Register */ -#define S1DREG_CRT_CUR_START 0x0081 /* CRT/TV Ink/Cursor Start Address Register */ -#define S1DREG_CRT_CUR_XPOS0 0x0082 /* CRT/TV Cursor X Position Register 0 */ -#define S1DREG_CRT_CUR_XPOS1 0x0083 /* CRT/TV Cursor X Position Register 1 */ -#define S1DREG_CRT_CUR_YPOS0 0x0084 /* CRT/TV Cursor Y Position Register 0 */ -#define S1DREG_CRT_CUR_YPOS1 0x0085 /* CRT/TV Cursor Y Position Register 1 */ -#define S1DREG_CRT_CUR_BCTL0 0x0086 /* CRT/TV Ink/Cursor Blue Color 0 Register */ -#define S1DREG_CRT_CUR_GCTL0 0x0087 /* CRT/TV Ink/Cursor Green Color 0 Register */ -#define S1DREG_CRT_CUR_RCTL0 0x0088 /* CRT/TV Ink/Cursor Red Color 0 Register */ -#define S1DREG_CRT_CUR_BCTL1 0x008A /* CRT/TV Ink/Cursor Blue Color 1 Register */ -#define S1DREG_CRT_CUR_GCTL1 0x008B /* CRT/TV Ink/Cursor Green Color 1 Register */ -#define S1DREG_CRT_CUR_RCTL1 0x008C /* CRT/TV Ink/Cursor Red Color 1 Register */ -#define S1DREG_CRT_CUR_FIFO_HTC 0x008E /* CRT/TV Ink/Cursor FIFO High Threshold Register */ -#define S1DREG_BBLT_CTL0 0x0100 /* BitBLT Control Register 0 */ -#define S1DREG_BBLT_CTL1 0x0101 /* BitBLT Control Register 1 */ -#define S1DREG_BBLT_CC_EXP 0x0102 /* BitBLT Code/Color Expansion Register */ -#define S1DREG_BBLT_OP 0x0103 /* BitBLT Operation Register */ -#define S1DREG_BBLT_SRC_START0 0x0104 /* BitBLT Source Start Address Register 0 */ -#define S1DREG_BBLT_SRC_START1 0x0105 /* BitBLT Source Start Address Register 1 */ -#define S1DREG_BBLT_SRC_START2 0x0106 /* BitBLT Source Start Address Register 2 */ -#define S1DREG_BBLT_DST_START0 0x0108 /* BitBLT Destination Start Address Register 0 */ -#define S1DREG_BBLT_DST_START1 0x0109 /* BitBLT Destination Start Address Register 1 */ -#define S1DREG_BBLT_DST_START2 0x010A /* BitBLT Destination Start Address Register 2 */ -#define S1DREG_BBLT_MEM_OFF0 0x010C /* BitBLT Memory Address Offset Register 0 */ -#define S1DREG_BBLT_MEM_OFF1 0x010D /* BitBLT Memory Address Offset Register 1 */ -#define S1DREG_BBLT_WIDTH0 0x0110 /* BitBLT Width Register 0 */ -#define S1DREG_BBLT_WIDTH1 0x0111 /* BitBLT Width Register 1 */ -#define S1DREG_BBLT_HEIGHT0 0x0112 /* BitBLT Height Register 0 */ -#define S1DREG_BBLT_HEIGHT1 0x0113 /* BitBLT Height Register 1 */ -#define S1DREG_BBLT_BGC0 0x0114 /* BitBLT Background Color Register 0 */ -#define S1DREG_BBLT_BGC1 0x0115 /* BitBLT Background Color Register 1 */ -#define S1DREG_BBLT_FGC0 0x0118 /* BitBLT Foreground Color Register 0 */ -#define S1DREG_BBLT_FGC1 0x0119 /* BitBLT Foreground Color Register 1 */ -#define S1DREG_LKUP_MODE 0x01E0 /* Look-Up Table Mode Register */ -#define S1DREG_LKUP_ADDR 0x01E2 /* Look-Up Table Address Register */ -#define S1DREG_LKUP_DATA 0x01E4 /* Look-Up Table Data Register */ -#define S1DREG_PS_CNF 0x01F0 /* Power Save Configuration Register */ -#define S1DREG_PS_STATUS 0x01F1 /* Power Save Status Register */ -#define S1DREG_CPU2MEM_WDOGT 0x01F4 /* CPU-to-Memory Access Watchdog Timer Register */ -#define S1DREG_COM_DISP_MODE 0x01FC /* Common Display Mode Register */ - -#define S1DREG_DELAYOFF 0xFFFE -#define S1DREG_DELAYON 0xFFFF - -#define BBLT_SOLID_FILL 0x0c - - -/* Note: all above defines should go in separate header files - when implementing other S1D13xxx chip support. */ - -struct s1d13xxxfb_regval { - u16 addr; - u8 value; -}; - -struct s1d13xxxfb_par { - void __iomem *regs; - unsigned char display; - unsigned char prod_id; - unsigned char revision; - - unsigned int pseudo_palette[16]; -#ifdef CONFIG_PM - void *regs_save; /* pm saves all registers here */ - void *disp_save; /* pm saves entire screen here */ -#endif -}; - -struct s1d13xxxfb_pdata { - const struct s1d13xxxfb_regval *initregs; - const unsigned int initregssize; - void (*platform_init_video)(void); -#ifdef CONFIG_PM - int (*platform_suspend_video)(void); - int (*platform_resume_video)(void); -#endif -}; - -#endif - diff --git a/ANDROID_3.4.5/include/video/sa1100fb.h b/ANDROID_3.4.5/include/video/sa1100fb.h deleted file mode 100644 index 4ab40965..00000000 --- a/ANDROID_3.4.5/include/video/sa1100fb.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * StrongARM 1100 LCD Controller Frame Buffer Device - * - * Copyright (C) 1999 Eric A. Thomas - * Based on acornfb.c Copyright (C) Russell King. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ -#ifndef _VIDEO_SA1100FB_H -#define _VIDEO_SA1100FB_H - -#include <linux/fb.h> -#include <linux/types.h> - -#define RGB_4 0 -#define RGB_8 1 -#define RGB_16 2 -#define NR_RGB 3 - -/* These are the bitfields for each display depth that we support. */ -struct sa1100fb_rgb { - struct fb_bitfield red; - struct fb_bitfield green; - struct fb_bitfield blue; - struct fb_bitfield transp; -}; - -/* This structure describes the machine which we are running on. */ -struct sa1100fb_mach_info { - u_long pixclock; - - u_short xres; - u_short yres; - - u_char bpp; - u_char hsync_len; - u_char left_margin; - u_char right_margin; - - u_char vsync_len; - u_char upper_margin; - u_char lower_margin; - u_char sync; - - u_int cmap_greyscale:1, - cmap_inverse:1, - cmap_static:1, - unused:29; - - u_int lccr0; - u_int lccr3; - - /* Overrides for the default RGB maps */ - const struct sa1100fb_rgb *rgb[NR_RGB]; - - void (*backlight_power)(int); - void (*lcd_power)(int); - void (*set_visual)(u32); -}; - -#endif diff --git a/ANDROID_3.4.5/include/video/sgivw.h b/ANDROID_3.4.5/include/video/sgivw.h deleted file mode 100644 index f6aa5692..00000000 --- a/ANDROID_3.4.5/include/video/sgivw.h +++ /dev/null @@ -1,681 +0,0 @@ -/* - * linux/drivers/video/sgivw.h -- SGI DBE frame buffer device header - * - * Copyright (C) 1999 Silicon Graphics, Inc. - * Jeffrey Newquist, newquist@engr.sgi.som - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive for - * more details. - */ - -#ifndef __SGIVWFB_H__ -#define __SGIVWFB_H__ - -#define DBE_GETREG(reg, dest) ((dest) = DBE_REG_BASE->reg) -#define DBE_SETREG(reg, src) DBE_REG_BASE->reg = (src) -#define DBE_IGETREG(reg, idx, dest) ((dest) = DBE_REG_BASE->reg[idx]) -#define DBE_ISETREG(reg, idx, src) (DBE_REG_BASE->reg[idx] = (src)) - -#define MASK(msb, lsb) ( (((u32)1<<((msb)-(lsb)+1))-1) << (lsb) ) -#define GET(v, msb, lsb) ( ((u32)(v) & MASK(msb,lsb)) >> (lsb) ) -#define SET(v, f, msb, lsb) ( (v) = ((v)&~MASK(msb,lsb)) | (( (u32)(f)<<(lsb) ) & MASK(msb,lsb)) ) - -#define GET_DBE_FIELD(reg, field, v) GET((v), DBE_##reg##_##field##_MSB, DBE_##reg##_##field##_LSB) -#define SET_DBE_FIELD(reg, field, v, f) SET((v), (f), DBE_##reg##_##field##_MSB, DBE_##reg##_##field##_LSB) - -/* NOTE: All loads/stores must be 32 bits and uncached */ - -#define DBE_REG_PHYS 0xd0000000 -#define DBE_REG_SIZE 0x01000000 - -struct asregs { - volatile u32 ctrlstat; /* 0x000000 general control */ - volatile u32 dotclock; /* 0x000004 dot clock PLL control */ - volatile u32 i2c; /* 0x000008 crt I2C control */ - volatile u32 sysclk; /* 0x00000c system clock PLL control */ - volatile u32 i2cfp; /* 0x000010 flat panel I2C control */ - volatile u32 id; /* 0x000014 device id/chip revision */ - volatile u32 config; /* 0x000018 power on configuration */ - volatile u32 bist; /* 0x00001c internal bist status */ - - char _pad0[ 0x010000 - 0x000020 ]; - - volatile u32 vt_xy; /* 0x010000 current dot coords */ - volatile u32 vt_xymax; /* 0x010004 maximum dot coords */ - volatile u32 vt_vsync; /* 0x010008 vsync on/off */ - volatile u32 vt_hsync; /* 0x01000c hsync on/off */ - volatile u32 vt_vblank; /* 0x010010 vblank on/off */ - volatile u32 vt_hblank; /* 0x010014 hblank on/off */ - volatile u32 vt_flags; /* 0x010018 polarity of vt signals */ - volatile u32 vt_f2rf_lock; /* 0x01001c f2rf & framelck y coord */ - volatile u32 vt_intr01; /* 0x010020 intr 0,1 y coords */ - volatile u32 vt_intr23; /* 0x010024 intr 2,3 y coords */ - volatile u32 fp_hdrv; /* 0x010028 flat panel hdrv on/off */ - volatile u32 fp_vdrv; /* 0x01002c flat panel vdrv on/off */ - volatile u32 fp_de; /* 0x010030 flat panel de on/off */ - volatile u32 vt_hpixen; /* 0x010034 intrnl horiz pixel on/off*/ - volatile u32 vt_vpixen; /* 0x010038 intrnl vert pixel on/off */ - volatile u32 vt_hcmap; /* 0x01003c cmap write (horiz) */ - volatile u32 vt_vcmap; /* 0x010040 cmap write (vert) */ - volatile u32 did_start_xy; /* 0x010044 eol/f did/xy reset val */ - volatile u32 crs_start_xy; /* 0x010048 eol/f crs/xy reset val */ - volatile u32 vc_start_xy; /* 0x01004c eol/f vc/xy reset val */ - - char _pad1[ 0x020000 - 0x010050 ]; - - volatile u32 ovr_width_tile; /* 0x020000 overlay plane ctrl 0 */ - volatile u32 ovr_inhwctrl; /* 0x020004 overlay plane ctrl 1 */ - volatile u32 ovr_control; /* 0x020008 overlay plane ctrl 1 */ - - char _pad2[ 0x030000 - 0x02000C ]; - - volatile u32 frm_size_tile; /* 0x030000 normal plane ctrl 0 */ - volatile u32 frm_size_pixel; /* 0x030004 normal plane ctrl 1 */ - volatile u32 frm_inhwctrl; /* 0x030008 normal plane ctrl 2 */ - volatile u32 frm_control; /* 0x03000C normal plane ctrl 3 */ - - char _pad3[ 0x040000 - 0x030010 ]; - - volatile u32 did_inhwctrl; /* 0x040000 DID control */ - volatile u32 did_control; /* 0x040004 DID shadow */ - - char _pad4[ 0x048000 - 0x040008 ]; - - volatile u32 mode_regs[32]; /* 0x048000 - 0x04807c WID table */ - - char _pad5[ 0x050000 - 0x048080 ]; - - volatile u32 cmap[6144]; /* 0x050000 - 0x055ffc color map */ - - char _pad6[ 0x058000 - 0x056000 ]; - - volatile u32 cm_fifo; /* 0x058000 color map fifo status */ - - char _pad7[ 0x060000 - 0x058004 ]; - - volatile u32 gmap[256]; /* 0x060000 - 0x0603fc gamma map */ - - char _pad8[ 0x068000 - 0x060400 ]; - - volatile u32 gmap10[1024]; /* 0x068000 - 0x068ffc gamma map */ - - char _pad9[ 0x070000 - 0x069000 ]; - - volatile u32 crs_pos; /* 0x070000 cusror control 0 */ - volatile u32 crs_ctl; /* 0x070004 cusror control 1 */ - volatile u32 crs_cmap[3]; /* 0x070008 - 0x070010 crs cmap */ - - char _pad10[ 0x078000 - 0x070014 ]; - - volatile u32 crs_glyph[64]; /* 0x078000 - 0x0780fc crs glyph */ - - char _pad11[ 0x080000 - 0x078100 ]; - - volatile u32 vc_0; /* 0x080000 video capture crtl 0 */ - volatile u32 vc_1; /* 0x080004 video capture crtl 1 */ - volatile u32 vc_2; /* 0x080008 video capture crtl 2 */ - volatile u32 vc_3; /* 0x08000c video capture crtl 3 */ - volatile u32 vc_4; /* 0x080010 video capture crtl 3 */ - volatile u32 vc_5; /* 0x080014 video capture crtl 3 */ - volatile u32 vc_6; /* 0x080018 video capture crtl 3 */ - volatile u32 vc_7; /* 0x08001c video capture crtl 3 */ - volatile u32 vc_8; /* 0x08000c video capture crtl 3 */ -}; - -/* Bit mask information */ - -#define DBE_CTRLSTAT_CHIPID_MSB 3 -#define DBE_CTRLSTAT_CHIPID_LSB 0 -#define DBE_CTRLSTAT_SENSE_N_MSB 4 -#define DBE_CTRLSTAT_SENSE_N_LSB 4 -#define DBE_CTRLSTAT_PCLKSEL_MSB 29 -#define DBE_CTRLSTAT_PCLKSEL_LSB 28 - -#define DBE_DOTCLK_M_MSB 7 -#define DBE_DOTCLK_M_LSB 0 -#define DBE_DOTCLK_N_MSB 13 -#define DBE_DOTCLK_N_LSB 8 -#define DBE_DOTCLK_P_MSB 15 -#define DBE_DOTCLK_P_LSB 14 -#define DBE_DOTCLK_RUN_MSB 20 -#define DBE_DOTCLK_RUN_LSB 20 - -#define DBE_VT_XY_VT_FREEZE_MSB 31 -#define DBE_VT_XY_VT_FREEZE_LSB 31 - -#define DBE_FP_VDRV_FP_VDRV_ON_MSB 23 -#define DBE_FP_VDRV_FP_VDRV_ON_LSB 12 -#define DBE_FP_VDRV_FP_VDRV_OFF_MSB 11 -#define DBE_FP_VDRV_FP_VDRV_OFF_LSB 0 - -#define DBE_FP_HDRV_FP_HDRV_ON_MSB 23 -#define DBE_FP_HDRV_FP_HDRV_ON_LSB 12 -#define DBE_FP_HDRV_FP_HDRV_OFF_MSB 11 -#define DBE_FP_HDRV_FP_HDRV_OFF_LSB 0 - -#define DBE_FP_DE_FP_DE_ON_MSB 23 -#define DBE_FP_DE_FP_DE_ON_LSB 12 -#define DBE_FP_DE_FP_DE_OFF_MSB 11 -#define DBE_FP_DE_FP_DE_OFF_LSB 0 - -#define DBE_VT_VSYNC_VT_VSYNC_ON_MSB 23 -#define DBE_VT_VSYNC_VT_VSYNC_ON_LSB 12 -#define DBE_VT_VSYNC_VT_VSYNC_OFF_MSB 11 -#define DBE_VT_VSYNC_VT_VSYNC_OFF_LSB 0 - -#define DBE_VT_HSYNC_VT_HSYNC_ON_MSB 23 -#define DBE_VT_HSYNC_VT_HSYNC_ON_LSB 12 -#define DBE_VT_HSYNC_VT_HSYNC_OFF_MSB 11 -#define DBE_VT_HSYNC_VT_HSYNC_OFF_LSB 0 - -#define DBE_VT_VBLANK_VT_VBLANK_ON_MSB 23 -#define DBE_VT_VBLANK_VT_VBLANK_ON_LSB 12 -#define DBE_VT_VBLANK_VT_VBLANK_OFF_MSB 11 -#define DBE_VT_VBLANK_VT_VBLANK_OFF_LSB 0 - -#define DBE_VT_HBLANK_VT_HBLANK_ON_MSB 23 -#define DBE_VT_HBLANK_VT_HBLANK_ON_LSB 12 -#define DBE_VT_HBLANK_VT_HBLANK_OFF_MSB 11 -#define DBE_VT_HBLANK_VT_HBLANK_OFF_LSB 0 - -#define DBE_VT_FLAGS_VDRV_INVERT_MSB 0 -#define DBE_VT_FLAGS_VDRV_INVERT_LSB 0 -#define DBE_VT_FLAGS_HDRV_INVERT_MSB 2 -#define DBE_VT_FLAGS_HDRV_INVERT_LSB 2 - -#define DBE_VT_VCMAP_VT_VCMAP_ON_MSB 23 -#define DBE_VT_VCMAP_VT_VCMAP_ON_LSB 12 -#define DBE_VT_VCMAP_VT_VCMAP_OFF_MSB 11 -#define DBE_VT_VCMAP_VT_VCMAP_OFF_LSB 0 - -#define DBE_VT_HCMAP_VT_HCMAP_ON_MSB 23 -#define DBE_VT_HCMAP_VT_HCMAP_ON_LSB 12 -#define DBE_VT_HCMAP_VT_HCMAP_OFF_MSB 11 -#define DBE_VT_HCMAP_VT_HCMAP_OFF_LSB 0 - -#define DBE_VT_XYMAX_VT_MAXX_MSB 11 -#define DBE_VT_XYMAX_VT_MAXX_LSB 0 -#define DBE_VT_XYMAX_VT_MAXY_MSB 23 -#define DBE_VT_XYMAX_VT_MAXY_LSB 12 - -#define DBE_VT_HPIXEN_VT_HPIXEN_ON_MSB 23 -#define DBE_VT_HPIXEN_VT_HPIXEN_ON_LSB 12 -#define DBE_VT_HPIXEN_VT_HPIXEN_OFF_MSB 11 -#define DBE_VT_HPIXEN_VT_HPIXEN_OFF_LSB 0 - -#define DBE_VT_VPIXEN_VT_VPIXEN_ON_MSB 23 -#define DBE_VT_VPIXEN_VT_VPIXEN_ON_LSB 12 -#define DBE_VT_VPIXEN_VT_VPIXEN_OFF_MSB 11 -#define DBE_VT_VPIXEN_VT_VPIXEN_OFF_LSB 0 - -#define DBE_OVR_CONTROL_OVR_DMA_ENABLE_MSB 0 -#define DBE_OVR_CONTROL_OVR_DMA_ENABLE_LSB 0 - -#define DBE_OVR_INHWCTRL_OVR_DMA_ENABLE_MSB 0 -#define DBE_OVR_INHWCTRL_OVR_DMA_ENABLE_LSB 0 - -#define DBE_OVR_WIDTH_TILE_OVR_FIFO_RESET_MSB 13 -#define DBE_OVR_WIDTH_TILE_OVR_FIFO_RESET_LSB 13 - -#define DBE_FRM_CONTROL_FRM_DMA_ENABLE_MSB 0 -#define DBE_FRM_CONTROL_FRM_DMA_ENABLE_LSB 0 -#define DBE_FRM_CONTROL_FRM_TILE_PTR_MSB 31 -#define DBE_FRM_CONTROL_FRM_TILE_PTR_LSB 9 -#define DBE_FRM_CONTROL_FRM_LINEAR_MSB 1 -#define DBE_FRM_CONTROL_FRM_LINEAR_LSB 1 - -#define DBE_FRM_INHWCTRL_FRM_DMA_ENABLE_MSB 0 -#define DBE_FRM_INHWCTRL_FRM_DMA_ENABLE_LSB 0 - -#define DBE_FRM_SIZE_TILE_FRM_WIDTH_TILE_MSB 12 -#define DBE_FRM_SIZE_TILE_FRM_WIDTH_TILE_LSB 5 -#define DBE_FRM_SIZE_TILE_FRM_RHS_MSB 4 -#define DBE_FRM_SIZE_TILE_FRM_RHS_LSB 0 -#define DBE_FRM_SIZE_TILE_FRM_DEPTH_MSB 14 -#define DBE_FRM_SIZE_TILE_FRM_DEPTH_LSB 13 -#define DBE_FRM_SIZE_TILE_FRM_FIFO_RESET_MSB 15 -#define DBE_FRM_SIZE_TILE_FRM_FIFO_RESET_LSB 15 - -#define DBE_FRM_SIZE_PIXEL_FB_HEIGHT_PIX_MSB 31 -#define DBE_FRM_SIZE_PIXEL_FB_HEIGHT_PIX_LSB 16 - -#define DBE_DID_CONTROL_DID_DMA_ENABLE_MSB 0 -#define DBE_DID_CONTROL_DID_DMA_ENABLE_LSB 0 -#define DBE_DID_INHWCTRL_DID_DMA_ENABLE_MSB 0 -#define DBE_DID_INHWCTRL_DID_DMA_ENABLE_LSB 0 - -#define DBE_DID_START_XY_DID_STARTY_MSB 23 -#define DBE_DID_START_XY_DID_STARTY_LSB 12 -#define DBE_DID_START_XY_DID_STARTX_MSB 11 -#define DBE_DID_START_XY_DID_STARTX_LSB 0 - -#define DBE_CRS_START_XY_CRS_STARTY_MSB 23 -#define DBE_CRS_START_XY_CRS_STARTY_LSB 12 -#define DBE_CRS_START_XY_CRS_STARTX_MSB 11 -#define DBE_CRS_START_XY_CRS_STARTX_LSB 0 - -#define DBE_WID_TYP_MSB 4 -#define DBE_WID_TYP_LSB 2 -#define DBE_WID_BUF_MSB 1 -#define DBE_WID_BUF_LSB 0 - -#define DBE_VC_START_XY_VC_STARTY_MSB 23 -#define DBE_VC_START_XY_VC_STARTY_LSB 12 -#define DBE_VC_START_XY_VC_STARTX_MSB 11 -#define DBE_VC_START_XY_VC_STARTX_LSB 0 - -/* Constants */ - -#define DBE_FRM_DEPTH_8 0 -#define DBE_FRM_DEPTH_16 1 -#define DBE_FRM_DEPTH_32 2 - -#define DBE_CMODE_I8 0 -#define DBE_CMODE_I12 1 -#define DBE_CMODE_RG3B2 2 -#define DBE_CMODE_RGB4 3 -#define DBE_CMODE_ARGB5 4 -#define DBE_CMODE_RGB8 5 -#define DBE_CMODE_RGBA5 6 -#define DBE_CMODE_RGB10 7 - -#define DBE_BMODE_BOTH 3 - -#define DBE_CRS_MAGIC 54 - -#define DBE_CLOCK_REF_KHZ 27000 - -/* Config Register (DBE Only) Definitions */ - -#define DBE_CONFIG_VDAC_ENABLE 0x00000001 -#define DBE_CONFIG_VDAC_GSYNC 0x00000002 -#define DBE_CONFIG_VDAC_PBLANK 0x00000004 -#define DBE_CONFIG_FPENABLE 0x00000008 -#define DBE_CONFIG_LENDIAN 0x00000020 -#define DBE_CONFIG_TILEHIST 0x00000040 -#define DBE_CONFIG_EXT_ADDR 0x00000080 - -#define DBE_CONFIG_FBDEV ( DBE_CONFIG_VDAC_ENABLE | \ - DBE_CONFIG_VDAC_GSYNC | \ - DBE_CONFIG_VDAC_PBLANK | \ - DBE_CONFIG_LENDIAN | \ - DBE_CONFIG_EXT_ADDR ) - -/* - * Available Video Timings and Corresponding Indices - */ - -typedef enum { - DBE_VT_640_480_60, - - DBE_VT_800_600_60, - DBE_VT_800_600_75, - DBE_VT_800_600_120, - - DBE_VT_1024_768_50, - DBE_VT_1024_768_60, - DBE_VT_1024_768_75, - DBE_VT_1024_768_85, - DBE_VT_1024_768_120, - - DBE_VT_1280_1024_50, - DBE_VT_1280_1024_60, - DBE_VT_1280_1024_75, - DBE_VT_1280_1024_85, - - DBE_VT_1600_1024_53, - DBE_VT_1600_1024_60, - - DBE_VT_1600_1200_50, - DBE_VT_1600_1200_60, - DBE_VT_1600_1200_75, - - DBE_VT_1920_1080_50, - DBE_VT_1920_1080_60, - DBE_VT_1920_1080_72, - - DBE_VT_1920_1200_50, - DBE_VT_1920_1200_60, - DBE_VT_1920_1200_66, - - DBE_VT_UNKNOWN -} dbe_timing_t; - - - -/* - * Crime Video Timing Data Structure - */ - -struct dbe_timing_info -{ - dbe_timing_t type; - int flags; - short width; /* Monitor resolution */ - short height; - int fields_sec; /* fields/sec (Hz -3 dec. places */ - int cfreq; /* pixel clock frequency (MHz -3 dec. places) */ - short htotal; /* Horizontal total pixels */ - short hblank_start; /* Horizontal blank start */ - short hblank_end; /* Horizontal blank end */ - short hsync_start; /* Horizontal sync start */ - short hsync_end; /* Horizontal sync end */ - short vtotal; /* Vertical total lines */ - short vblank_start; /* Vertical blank start */ - short vblank_end; /* Vertical blank end */ - short vsync_start; /* Vertical sync start */ - short vsync_end; /* Vertical sync end */ - short pll_m; /* PLL M parameter */ - short pll_n; /* PLL P parameter */ - short pll_p; /* PLL N parameter */ -}; - -/* Defines for dbe_vof_info_t flags */ - -#define DBE_VOF_UNKNOWNMON 1 -#define DBE_VOF_STEREO 2 -#define DBE_VOF_DO_GENSYNC 4 /* enable incoming sync */ -#define DBE_VOF_SYNC_ON_GREEN 8 /* sync on green */ -#define DBE_VOF_FLATPANEL 0x1000 /* FLATPANEL Timing */ -#define DBE_VOF_MAGICKEY 0x2000 /* Backdoor key */ - -/* - * DBE Timing Tables - */ - -#ifdef INCLUDE_TIMING_TABLE_DATA -struct dbe_timing_info dbeVTimings[] = { - { - DBE_VT_640_480_60, - /* flags, width, height, fields_sec, cfreq */ - 0, 640, 480, 59940, 25175, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 800, 640, 800, 656, 752, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 525, 480, 525, 490, 492, - /* pll_m, pll_n, pll_p */ - 15, 2, 3 - }, - - { - DBE_VT_800_600_60, - /* flags, width, height, fields_sec, cfreq */ - 0, 800, 600, 60317, 40000, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 1056, 800, 1056, 840, 968, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 628, 600, 628, 601, 605, - /* pll_m, pll_n, pll_p */ - 3, 1, 1 - }, - - { - DBE_VT_800_600_75, - /* flags, width, height, fields_sec, cfreq */ - 0, 800, 600, 75000, 49500, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 1056, 800, 1056, 816, 896, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 625, 600, 625, 601, 604, - /* pll_m, pll_n, pll_p */ - 11, 3, 1 - }, - - { - DBE_VT_800_600_120, - /* flags, width, height, fields_sec, cfreq */ - DBE_VOF_STEREO, 800, 600, 119800, 82978, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 1040, 800, 1040, 856, 976, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 666, 600, 666, 637, 643, - /* pll_m, pll_n, pll_p */ - 31, 5, 1 - }, - - { - DBE_VT_1024_768_50, - /* flags, width, height, fields_sec, cfreq */ - 0, 1024, 768, 50000, 54163, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 1344, 1024, 1344, 1048, 1184, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 806, 768, 806, 771, 777, - /* pll_m, pll_n, pll_p */ - 4, 1, 1 - }, - - { - DBE_VT_1024_768_60, - /* flags, width, height, fields_sec, cfreq */ - 0, 1024, 768, 60004, 65000, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 1344, 1024, 1344, 1048, 1184, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 806, 768, 806, 771, 777, - /* pll_m, pll_n, pll_p */ - 12, 5, 0 - }, - - { - DBE_VT_1024_768_75, - /* flags, width, height, fields_sec, cfreq */ - 0, 1024, 768, 75029, 78750, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 1312, 1024, 1312, 1040, 1136, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 800, 768, 800, 769, 772, - /* pll_m, pll_n, pll_p */ - 29, 5, 1 - }, - - { - DBE_VT_1024_768_85, - /* flags, width, height, fields_sec, cfreq */ - 0, 1024, 768, 84997, 94500, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 1376, 1024, 1376, 1072, 1168, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 808, 768, 808, 769, 772, - /* pll_m, pll_n, pll_p */ - 7, 2, 0 - }, - - { - DBE_VT_1024_768_120, - /* flags, width, height, fields_sec, cfreq */ - DBE_VOF_STEREO, 1024, 768, 119800, 133195, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 1376, 1024, 1376, 1072, 1168, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 808, 768, 808, 769, 772, - /* pll_m, pll_n, pll_p */ - 5, 1, 0 - }, - - { - DBE_VT_1280_1024_50, - /* flags, width, height, fields_sec, cfreq */ - 0, 1280, 1024, 50000, 89460, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 1680, 1280, 1680, 1360, 1480, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 1065, 1024, 1065, 1027, 1030, - /* pll_m, pll_n, pll_p */ - 10, 3, 0 - }, - - { - DBE_VT_1280_1024_60, - /* flags, width, height, fields_sec, cfreq */ - 0, 1280, 1024, 60020, 108000, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 1688, 1280, 1688, 1328, 1440, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 1066, 1024, 1066, 1025, 1028, - /* pll_m, pll_n, pll_p */ - 4, 1, 0 - }, - - { - DBE_VT_1280_1024_75, - /* flags, width, height, fields_sec, cfreq */ - 0, 1280, 1024, 75025, 135000, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 1688, 1280, 1688, 1296, 1440, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 1066, 1024, 1066, 1025, 1028, - /* pll_m, pll_n, pll_p */ - 5, 1, 0 - }, - - { - DBE_VT_1280_1024_85, - /* flags, width, height, fields_sec, cfreq */ - 0, 1280, 1024, 85024, 157500, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 1728, 1280, 1728, 1344, 1504, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 1072, 1024, 1072, 1025, 1028, - /* pll_m, pll_n, pll_p */ - 29, 5, 0 - }, - - { - DBE_VT_1600_1024_53, - /* flags, width, height, fields_sec, cfreq */ - DBE_VOF_FLATPANEL | DBE_VOF_MAGICKEY, - 1600, 1024, 53000, 107447, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 1900, 1600, 1900, 1630, 1730, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 1067, 1024, 1067, 1027, 1030, - /* pll_m, pll_n, pll_p */ - 4, 1, 0 - }, - - { - DBE_VT_1600_1024_60, - /* flags, width, height, fields_sec, cfreq */ - DBE_VOF_FLATPANEL, 1600, 1024, 60000, 106913, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 1670, 1600, 1670, 1630, 1650, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 1067, 1024, 1067, 1027, 1030, - /* pll_m, pll_n, pll_p */ - 4, 1, 0 - }, - - { - DBE_VT_1600_1200_50, - /* flags, width, height, fields_sec, cfreq */ - 0, 1600, 1200, 50000, 130500, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 2088, 1600, 2088, 1644, 1764, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 1250, 1200, 1250, 1205, 1211, - /* pll_m, pll_n, pll_p */ - 24, 5, 0 - }, - - { - DBE_VT_1600_1200_60, - /* flags, width, height, fields_sec, cfreq */ - 0, 1600, 1200, 59940, 162000, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 2160, 1600, 2160, 1644, 1856, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 1250, 1200, 1250, 1201, 1204, - /* pll_m, pll_n, pll_p */ - 6, 1, 0 - }, - - { - DBE_VT_1600_1200_75, - /* flags, width, height, fields_sec, cfreq */ - 0, 1600, 1200, 75000, 202500, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 2160, 1600, 2160, 1644, 1856, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 1250, 1200, 1250, 1201, 1204, - /* pll_m, pll_n, pll_p */ - 15, 2, 0 - }, - - { - DBE_VT_1920_1080_50, - /* flags, width, height, fields_sec, cfreq */ - 0, 1920, 1080, 50000, 133200, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 2368, 1920, 2368, 1952, 2096, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 1125, 1080, 1125, 1083, 1086, - /* pll_m, pll_n, pll_p */ - 5, 1, 0 - }, - - { - DBE_VT_1920_1080_60, - /* flags, width, height, fields_sec, cfreq */ - 0, 1920, 1080, 59940, 159840, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 2368, 1920, 2368, 1952, 2096, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 1125, 1080, 1125, 1083, 1086, - /* pll_m, pll_n, pll_p */ - 6, 1, 0 - }, - - { - DBE_VT_1920_1080_72, - /* flags, width, height, fields_sec, cfreq */ - 0, 1920, 1080, 72000, 216023, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 2560, 1920, 2560, 1968, 2184, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 1172, 1080, 1172, 1083, 1086, - /* pll_m, pll_n, pll_p */ - 8, 1, 0 - }, - - { - DBE_VT_1920_1200_50, - /* flags, width, height, fields_sec, cfreq */ - 0, 1920, 1200, 50000, 161500, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 2584, 1920, 2584, 1984, 2240, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 1250, 1200, 1250, 1203, 1206, - /* pll_m, pll_n, pll_p */ - 6, 1, 0 - }, - - { - DBE_VT_1920_1200_60, - /* flags, width, height, fields_sec, cfreq */ - 0, 1920, 1200, 59940, 193800, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 2584, 1920, 2584, 1984, 2240, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 1250, 1200, 1250, 1203, 1206, - /* pll_m, pll_n, pll_p */ - 29, 4, 0 - }, - - { - DBE_VT_1920_1200_66, - /* flags, width, height, fields_sec, cfreq */ - 0, 1920, 1200, 66000, 213180, - /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */ - 2584, 1920, 2584, 1984, 2240, - /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */ - 1250, 1200, 1250, 1203, 1206, - /* pll_m, pll_n, pll_p */ - 8, 1, 0 - } -}; - -#endif // INCLUDE_TIMING_TABLE_DATA - -#endif // ! __SGIVWFB_H__ diff --git a/ANDROID_3.4.5/include/video/sh_mipi_dsi.h b/ANDROID_3.4.5/include/video/sh_mipi_dsi.h deleted file mode 100644 index 06c67fbc..00000000 --- a/ANDROID_3.4.5/include/video/sh_mipi_dsi.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Public SH-mobile MIPI DSI header - * - * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef VIDEO_SH_MIPI_DSI_H -#define VIDEO_SH_MIPI_DSI_H - -enum sh_mipi_dsi_data_fmt { - MIPI_RGB888, - MIPI_RGB565, - MIPI_RGB666_LP, - MIPI_RGB666, - MIPI_BGR888, - MIPI_BGR565, - MIPI_BGR666_LP, - MIPI_BGR666, - MIPI_YUYV, - MIPI_UYVY, - MIPI_YUV420_L, - MIPI_YUV420, -}; - -struct sh_mobile_lcdc_chan_cfg; - -#define SH_MIPI_DSI_HSABM (1 << 0) -#define SH_MIPI_DSI_HBPBM (1 << 1) -#define SH_MIPI_DSI_HFPBM (1 << 2) -#define SH_MIPI_DSI_BL2E (1 << 3) -#define SH_MIPI_DSI_VSEE (1 << 4) -#define SH_MIPI_DSI_HSEE (1 << 5) -#define SH_MIPI_DSI_HSAE (1 << 6) - -#define SH_MIPI_DSI_HSbyteCLK (1 << 24) -#define SH_MIPI_DSI_HS6divCLK (1 << 25) -#define SH_MIPI_DSI_HS4divCLK (1 << 26) - -#define SH_MIPI_DSI_SYNC_PULSES_MODE (SH_MIPI_DSI_VSEE | \ - SH_MIPI_DSI_HSEE | \ - SH_MIPI_DSI_HSAE) -#define SH_MIPI_DSI_SYNC_EVENTS_MODE (0) -#define SH_MIPI_DSI_SYNC_BURST_MODE (SH_MIPI_DSI_BL2E) - -struct sh_mipi_dsi_info { - enum sh_mipi_dsi_data_fmt data_format; - struct sh_mobile_lcdc_chan_cfg *lcd_chan; - int lane; - unsigned long flags; - u32 clksrc; - u32 phyctrl; /* for extra setting */ - unsigned int vsynw_offset; - int (*set_dot_clock)(struct platform_device *pdev, - void __iomem *base, - int enable); -}; - -#endif diff --git a/ANDROID_3.4.5/include/video/sh_mobile_hdmi.h b/ANDROID_3.4.5/include/video/sh_mobile_hdmi.h deleted file mode 100644 index 728f9de9..00000000 --- a/ANDROID_3.4.5/include/video/sh_mobile_hdmi.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * SH-Mobile High-Definition Multimedia Interface (HDMI) - * - * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef SH_MOBILE_HDMI_H -#define SH_MOBILE_HDMI_H - -struct sh_mobile_lcdc_chan_cfg; -struct device; -struct clk; - -/* - * flags format - * - * 0x0000000A - * - * A: Audio source select - */ - -/* Audio source select */ -#define HDMI_SND_SRC_MASK (0xF << 0) -#define HDMI_SND_SRC_I2S (0 << 0) /* default */ -#define HDMI_SND_SRC_SPDIF (1 << 0) -#define HDMI_SND_SRC_DSD (2 << 0) -#define HDMI_SND_SRC_HBR (3 << 0) - -struct sh_mobile_hdmi_info { - unsigned int flags; - long (*clk_optimize_parent)(unsigned long target, unsigned long *best_freq, - unsigned long *parent_freq); -}; - -#endif diff --git a/ANDROID_3.4.5/include/video/sh_mobile_lcdc.h b/ANDROID_3.4.5/include/video/sh_mobile_lcdc.h deleted file mode 100644 index 7571b27a..00000000 --- a/ANDROID_3.4.5/include/video/sh_mobile_lcdc.h +++ /dev/null @@ -1,192 +0,0 @@ -#ifndef __ASM_SH_MOBILE_LCDC_H__ -#define __ASM_SH_MOBILE_LCDC_H__ - -#include <linux/fb.h> -#include <video/sh_mobile_meram.h> - -/* Register definitions */ -#define _LDDCKR 0x410 -#define LDDCKR_ICKSEL_BUS (0 << 16) -#define LDDCKR_ICKSEL_MIPI (1 << 16) -#define LDDCKR_ICKSEL_HDMI (2 << 16) -#define LDDCKR_ICKSEL_EXT (3 << 16) -#define LDDCKR_ICKSEL_MASK (7 << 16) -#define LDDCKR_MOSEL (1 << 6) -#define _LDDCKSTPR 0x414 -#define _LDINTR 0x468 -#define LDINTR_FE (1 << 10) -#define LDINTR_VSE (1 << 9) -#define LDINTR_VEE (1 << 8) -#define LDINTR_FS (1 << 2) -#define LDINTR_VSS (1 << 1) -#define LDINTR_VES (1 << 0) -#define LDINTR_STATUS_MASK (0xff << 0) -#define _LDSR 0x46c -#define LDSR_MSS (1 << 10) -#define LDSR_MRS (1 << 8) -#define LDSR_AS (1 << 1) -#define _LDCNT1R 0x470 -#define LDCNT1R_DE (1 << 0) -#define _LDCNT2R 0x474 -#define LDCNT2R_BR (1 << 8) -#define LDCNT2R_MD (1 << 3) -#define LDCNT2R_SE (1 << 2) -#define LDCNT2R_ME (1 << 1) -#define LDCNT2R_DO (1 << 0) -#define _LDRCNTR 0x478 -#define LDRCNTR_SRS (1 << 17) -#define LDRCNTR_SRC (1 << 16) -#define LDRCNTR_MRS (1 << 1) -#define LDRCNTR_MRC (1 << 0) -#define _LDDDSR 0x47c -#define LDDDSR_LS (1 << 2) -#define LDDDSR_WS (1 << 1) -#define LDDDSR_BS (1 << 0) - -#define LDMT1R_VPOL (1 << 28) -#define LDMT1R_HPOL (1 << 27) -#define LDMT1R_DWPOL (1 << 26) -#define LDMT1R_DIPOL (1 << 25) -#define LDMT1R_DAPOL (1 << 24) -#define LDMT1R_HSCNT (1 << 17) -#define LDMT1R_DWCNT (1 << 16) -#define LDMT1R_IFM (1 << 12) -#define LDMT1R_MIFTYP_RGB8 (0x0 << 0) -#define LDMT1R_MIFTYP_RGB9 (0x4 << 0) -#define LDMT1R_MIFTYP_RGB12A (0x5 << 0) -#define LDMT1R_MIFTYP_RGB12B (0x6 << 0) -#define LDMT1R_MIFTYP_RGB16 (0x7 << 0) -#define LDMT1R_MIFTYP_RGB18 (0xa << 0) -#define LDMT1R_MIFTYP_RGB24 (0xb << 0) -#define LDMT1R_MIFTYP_YCBCR (0xf << 0) -#define LDMT1R_MIFTYP_SYS8A (0x0 << 0) -#define LDMT1R_MIFTYP_SYS8B (0x1 << 0) -#define LDMT1R_MIFTYP_SYS8C (0x2 << 0) -#define LDMT1R_MIFTYP_SYS8D (0x3 << 0) -#define LDMT1R_MIFTYP_SYS9 (0x4 << 0) -#define LDMT1R_MIFTYP_SYS12 (0x5 << 0) -#define LDMT1R_MIFTYP_SYS16A (0x7 << 0) -#define LDMT1R_MIFTYP_SYS16B (0x8 << 0) -#define LDMT1R_MIFTYP_SYS16C (0x9 << 0) -#define LDMT1R_MIFTYP_SYS18 (0xa << 0) -#define LDMT1R_MIFTYP_SYS24 (0xb << 0) -#define LDMT1R_MIFTYP_MASK (0xf << 0) - -#define LDDFR_CF1 (1 << 18) -#define LDDFR_CF0 (1 << 17) -#define LDDFR_CC (1 << 16) -#define LDDFR_YF_420 (0 << 8) -#define LDDFR_YF_422 (1 << 8) -#define LDDFR_YF_444 (2 << 8) -#define LDDFR_YF_MASK (3 << 8) -#define LDDFR_PKF_ARGB32 (0x00 << 0) -#define LDDFR_PKF_RGB16 (0x03 << 0) -#define LDDFR_PKF_RGB24 (0x0b << 0) -#define LDDFR_PKF_MASK (0x1f << 0) - -#define LDSM1R_OS (1 << 0) - -#define LDSM2R_OSTRG (1 << 0) - -#define LDPMR_LPS (3 << 0) - -#define _LDDWD0R 0x800 -#define LDDWDxR_WDACT (1 << 28) -#define LDDWDxR_RSW (1 << 24) -#define _LDDRDR 0x840 -#define LDDRDR_RSR (1 << 24) -#define LDDRDR_DRD_MASK (0x3ffff << 0) -#define _LDDWAR 0x900 -#define LDDWAR_WA (1 << 0) -#define _LDDRAR 0x904 -#define LDDRAR_RA (1 << 0) - -enum { - RGB8 = LDMT1R_MIFTYP_RGB8, /* 24bpp, 8:8:8 */ - RGB9 = LDMT1R_MIFTYP_RGB9, /* 18bpp, 9:9 */ - RGB12A = LDMT1R_MIFTYP_RGB12A, /* 24bpp, 12:12 */ - RGB12B = LDMT1R_MIFTYP_RGB12B, /* 12bpp */ - RGB16 = LDMT1R_MIFTYP_RGB16, /* 16bpp */ - RGB18 = LDMT1R_MIFTYP_RGB18, /* 18bpp */ - RGB24 = LDMT1R_MIFTYP_RGB24, /* 24bpp */ - YUV422 = LDMT1R_MIFTYP_YCBCR, /* 16bpp */ - SYS8A = LDMT1R_IFM | LDMT1R_MIFTYP_SYS8A, /* 24bpp, 8:8:8 */ - SYS8B = LDMT1R_IFM | LDMT1R_MIFTYP_SYS8B, /* 18bpp, 8:8:2 */ - SYS8C = LDMT1R_IFM | LDMT1R_MIFTYP_SYS8C, /* 18bpp, 2:8:8 */ - SYS8D = LDMT1R_IFM | LDMT1R_MIFTYP_SYS8D, /* 16bpp, 8:8 */ - SYS9 = LDMT1R_IFM | LDMT1R_MIFTYP_SYS9, /* 18bpp, 9:9 */ - SYS12 = LDMT1R_IFM | LDMT1R_MIFTYP_SYS12, /* 24bpp, 12:12 */ - SYS16A = LDMT1R_IFM | LDMT1R_MIFTYP_SYS16A, /* 16bpp */ - SYS16B = LDMT1R_IFM | LDMT1R_MIFTYP_SYS16B, /* 18bpp, 16:2 */ - SYS16C = LDMT1R_IFM | LDMT1R_MIFTYP_SYS16C, /* 18bpp, 2:16 */ - SYS18 = LDMT1R_IFM | LDMT1R_MIFTYP_SYS18, /* 18bpp */ - SYS24 = LDMT1R_IFM | LDMT1R_MIFTYP_SYS24, /* 24bpp */ -}; - -enum { LCDC_CHAN_DISABLED = 0, - LCDC_CHAN_MAINLCD, - LCDC_CHAN_SUBLCD }; - -enum { LCDC_CLK_BUS, LCDC_CLK_PERIPHERAL, LCDC_CLK_EXTERNAL }; - -#define LCDC_FLAGS_DWPOL (1 << 0) /* Rising edge dot clock data latch */ -#define LCDC_FLAGS_DIPOL (1 << 1) /* Active low display enable polarity */ -#define LCDC_FLAGS_DAPOL (1 << 2) /* Active low display data polarity */ -#define LCDC_FLAGS_HSCNT (1 << 3) /* Disable HSYNC during VBLANK */ -#define LCDC_FLAGS_DWCNT (1 << 4) /* Disable dotclock during blanking */ - -struct sh_mobile_lcdc_sys_bus_cfg { - unsigned long ldmt2r; - unsigned long ldmt3r; - unsigned long deferred_io_msec; -}; - -struct sh_mobile_lcdc_sys_bus_ops { - void (*write_index)(void *handle, unsigned long data); - void (*write_data)(void *handle, unsigned long data); - unsigned long (*read_data)(void *handle); -}; - -struct sh_mobile_lcdc_panel_cfg { - unsigned long width; /* Panel width in mm */ - unsigned long height; /* Panel height in mm */ - int (*setup_sys)(void *sys_ops_handle, - struct sh_mobile_lcdc_sys_bus_ops *sys_ops); - void (*start_transfer)(void *sys_ops_handle, - struct sh_mobile_lcdc_sys_bus_ops *sys_ops); - void (*display_on)(void); - void (*display_off)(void); -}; - -/* backlight info */ -struct sh_mobile_lcdc_bl_info { - const char *name; - int max_brightness; - int (*set_brightness)(int brightness); - int (*get_brightness)(void); -}; - -struct sh_mobile_lcdc_chan_cfg { - int chan; - int fourcc; - int colorspace; - int interface_type; /* selects RGBn or SYSn I/F, see above */ - int clock_divider; - unsigned long flags; /* LCDC_FLAGS_... */ - const struct fb_videomode *lcd_modes; - int num_modes; - struct sh_mobile_lcdc_panel_cfg panel_cfg; - struct sh_mobile_lcdc_bl_info bl_info; - struct sh_mobile_lcdc_sys_bus_cfg sys_bus_cfg; /* only for SYSn I/F */ - const struct sh_mobile_meram_cfg *meram_cfg; - - struct platform_device *tx_dev; /* HDMI/DSI transmitter device */ -}; - -struct sh_mobile_lcdc_info { - int clock_source; - struct sh_mobile_lcdc_chan_cfg ch[2]; - struct sh_mobile_meram_info *meram_dev; -}; - -#endif /* __ASM_SH_MOBILE_LCDC_H__ */ diff --git a/ANDROID_3.4.5/include/video/sh_mobile_meram.h b/ANDROID_3.4.5/include/video/sh_mobile_meram.h deleted file mode 100644 index 29b2fd3b..00000000 --- a/ANDROID_3.4.5/include/video/sh_mobile_meram.h +++ /dev/null @@ -1,63 +0,0 @@ -#ifndef __VIDEO_SH_MOBILE_MERAM_H__ -#define __VIDEO_SH_MOBILE_MERAM_H__ - -/* For sh_mobile_meram_info.addr_mode */ -enum { - SH_MOBILE_MERAM_MODE0 = 0, - SH_MOBILE_MERAM_MODE1 -}; - -enum { - SH_MOBILE_MERAM_PF_NV = 0, - SH_MOBILE_MERAM_PF_RGB, - SH_MOBILE_MERAM_PF_NV24 -}; - - -struct sh_mobile_meram_priv; -struct sh_mobile_meram_ops; - -/* - * struct sh_mobile_meram_info - MERAM platform data - * @reserved_icbs: Bitmask of reserved ICBs (for instance used through UIO) - */ -struct sh_mobile_meram_info { - int addr_mode; - u32 reserved_icbs; - struct sh_mobile_meram_ops *ops; - struct sh_mobile_meram_priv *priv; - struct platform_device *pdev; -}; - -/* icb config */ -struct sh_mobile_meram_icb_cfg { - unsigned int meram_size; /* MERAM Buffer Size to use */ -}; - -struct sh_mobile_meram_cfg { - struct sh_mobile_meram_icb_cfg icb[2]; -}; - -struct module; -struct sh_mobile_meram_ops { - struct module *module; - /* register usage of meram */ - void *(*meram_register)(struct sh_mobile_meram_info *meram_dev, - const struct sh_mobile_meram_cfg *cfg, - unsigned int xres, unsigned int yres, - unsigned int pixelformat, - unsigned int *pitch); - - /* unregister usage of meram */ - void (*meram_unregister)(struct sh_mobile_meram_info *meram_dev, - void *data); - - /* update meram settings */ - void (*meram_update)(struct sh_mobile_meram_info *meram_dev, void *data, - unsigned long base_addr_y, - unsigned long base_addr_c, - unsigned long *icb_addr_y, - unsigned long *icb_addr_c); -}; - -#endif /* __VIDEO_SH_MOBILE_MERAM_H__ */ diff --git a/ANDROID_3.4.5/include/video/sisfb.h b/ANDROID_3.4.5/include/video/sisfb.h deleted file mode 100644 index 6dc5df9e..00000000 --- a/ANDROID_3.4.5/include/video/sisfb.h +++ /dev/null @@ -1,224 +0,0 @@ -/* - * sisfb.h - definitions for the SiS framebuffer driver - * - * Copyright (C) 2001-2005 by Thomas Winischhofer, Vienna, Austria. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the named License, - * or any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA - */ - -#ifndef _LINUX_SISFB_H_ -#define _LINUX_SISFB_H_ - -#include <linux/types.h> -#include <asm/ioctl.h> - -/**********************************************/ -/* PUBLIC */ -/**********************************************/ - -/* vbflags, public (others in sis.h) */ -#define CRT2_DEFAULT 0x00000001 -#define CRT2_LCD 0x00000002 -#define CRT2_TV 0x00000004 -#define CRT2_VGA 0x00000008 -#define TV_NTSC 0x00000010 -#define TV_PAL 0x00000020 -#define TV_HIVISION 0x00000040 -#define TV_YPBPR 0x00000080 -#define TV_AVIDEO 0x00000100 -#define TV_SVIDEO 0x00000200 -#define TV_SCART 0x00000400 -#define TV_PALM 0x00001000 -#define TV_PALN 0x00002000 -#define TV_NTSCJ 0x00001000 -#define TV_CHSCART 0x00008000 -#define TV_CHYPBPR525I 0x00010000 -#define CRT1_VGA 0x00000000 -#define CRT1_LCDA 0x00020000 -#define VGA2_CONNECTED 0x00040000 -#define VB_DISPTYPE_CRT1 0x00080000 /* CRT1 connected and used */ -#define VB_SINGLE_MODE 0x20000000 /* CRT1 or CRT2; determined by DISPTYPE_CRTx */ -#define VB_MIRROR_MODE 0x40000000 /* CRT1 + CRT2 identical (mirror mode) */ -#define VB_DUALVIEW_MODE 0x80000000 /* CRT1 + CRT2 independent (dual head mode) */ - -/* Aliases: */ -#define CRT2_ENABLE (CRT2_LCD | CRT2_TV | CRT2_VGA) -#define TV_STANDARD (TV_NTSC | TV_PAL | TV_PALM | TV_PALN | TV_NTSCJ) -#define TV_INTERFACE (TV_AVIDEO|TV_SVIDEO|TV_SCART|TV_HIVISION|TV_YPBPR|TV_CHSCART|TV_CHYPBPR525I) - -/* Only if TV_YPBPR is set: */ -#define TV_YPBPR525I TV_NTSC -#define TV_YPBPR525P TV_PAL -#define TV_YPBPR750P TV_PALM -#define TV_YPBPR1080I TV_PALN -#define TV_YPBPRALL (TV_YPBPR525I | TV_YPBPR525P | TV_YPBPR750P | TV_YPBPR1080I) - -#define VB_DISPTYPE_DISP2 CRT2_ENABLE -#define VB_DISPTYPE_CRT2 CRT2_ENABLE -#define VB_DISPTYPE_DISP1 VB_DISPTYPE_CRT1 -#define VB_DISPMODE_SINGLE VB_SINGLE_MODE -#define VB_DISPMODE_MIRROR VB_MIRROR_MODE -#define VB_DISPMODE_DUAL VB_DUALVIEW_MODE -#define VB_DISPLAY_MODE (SINGLE_MODE | MIRROR_MODE | DUALVIEW_MODE) - -/* Structure argument for SISFB_GET_INFO ioctl */ -struct sisfb_info { - __u32 sisfb_id; /* for identifying sisfb */ -#ifndef SISFB_ID -#define SISFB_ID 0x53495346 /* Identify myself with 'SISF' */ -#endif - __u32 chip_id; /* PCI-ID of detected chip */ - __u32 memory; /* total video memory in KB */ - __u32 heapstart; /* heap start offset in KB */ - __u8 fbvidmode; /* current sisfb mode */ - - __u8 sisfb_version; - __u8 sisfb_revision; - __u8 sisfb_patchlevel; - - __u8 sisfb_caps; /* sisfb capabilities */ - - __u32 sisfb_tqlen; /* turbo queue length (in KB) */ - - __u32 sisfb_pcibus; /* The card's PCI ID */ - __u32 sisfb_pcislot; - __u32 sisfb_pcifunc; - - __u8 sisfb_lcdpdc; /* PanelDelayCompensation */ - - __u8 sisfb_lcda; /* Detected status of LCDA for low res/text modes */ - - __u32 sisfb_vbflags; - __u32 sisfb_currentvbflags; - - __u32 sisfb_scalelcd; - __u32 sisfb_specialtiming; - - __u8 sisfb_haveemi; - __u8 sisfb_emi30,sisfb_emi31,sisfb_emi32,sisfb_emi33; - __u8 sisfb_haveemilcd; - - __u8 sisfb_lcdpdca; /* PanelDelayCompensation for LCD-via-CRT1 */ - - __u16 sisfb_tvxpos, sisfb_tvypos; /* Warning: Values + 32 ! */ - - __u32 sisfb_heapsize; /* heap size (in KB) */ - __u32 sisfb_videooffset; /* Offset of viewport in video memory (in bytes) */ - - __u32 sisfb_curfstn; /* currently running FSTN/DSTN mode */ - __u32 sisfb_curdstn; - - __u16 sisfb_pci_vendor; /* PCI vendor (SiS or XGI) */ - - __u32 sisfb_vbflags2; /* ivideo->vbflags2 */ - - __u8 sisfb_can_post; /* sisfb can POST this card */ - __u8 sisfb_card_posted; /* card is POSTED */ - __u8 sisfb_was_boot_device; /* This card was the boot video device (ie is primary) */ - - __u8 reserved[183]; /* for future use */ -}; - -#define SISFB_CMD_GETVBFLAGS 0x55AA0001 /* no arg; result[1] = vbflags */ -#define SISFB_CMD_SWITCHCRT1 0x55AA0010 /* arg[0]: 99 = query, 0 = off, 1 = on */ -/* more to come */ - -#define SISFB_CMD_ERR_OK 0x80000000 /* command succeeded */ -#define SISFB_CMD_ERR_LOCKED 0x80000001 /* sisfb is locked */ -#define SISFB_CMD_ERR_EARLY 0x80000002 /* request before sisfb took over gfx system */ -#define SISFB_CMD_ERR_NOVB 0x80000003 /* No video bridge */ -#define SISFB_CMD_ERR_NOCRT2 0x80000004 /* can't change CRT1 status, CRT2 disabled */ -/* more to come */ -#define SISFB_CMD_ERR_UNKNOWN 0x8000ffff /* Unknown command */ -#define SISFB_CMD_ERR_OTHER 0x80010000 /* Other error */ - -/* Argument for SISFB_CMD ioctl */ -struct sisfb_cmd { - __u32 sisfb_cmd; - __u32 sisfb_arg[16]; - __u32 sisfb_result[4]; -}; - -/* Additional IOCTLs for communication sisfb <> X driver */ -/* If changing this, vgatypes.h must also be changed (for X driver) */ - -/* ioctl for identifying and giving some info (esp. memory heap start) */ -#define SISFB_GET_INFO_SIZE _IOR(0xF3,0x00,__u32) -#define SISFB_GET_INFO _IOR(0xF3,0x01,struct sisfb_info) - -/* ioctrl to get current vertical retrace status */ -#define SISFB_GET_VBRSTATUS _IOR(0xF3,0x02,__u32) - -/* ioctl to enable/disable panning auto-maximize (like nomax parameter) */ -#define SISFB_GET_AUTOMAXIMIZE _IOR(0xF3,0x03,__u32) -#define SISFB_SET_AUTOMAXIMIZE _IOW(0xF3,0x03,__u32) - -/* ioctls to relocate TV output (x=D[31:16], y=D[15:0], + 32)*/ -#define SISFB_GET_TVPOSOFFSET _IOR(0xF3,0x04,__u32) -#define SISFB_SET_TVPOSOFFSET _IOW(0xF3,0x04,__u32) - -/* ioctl for internal sisfb commands (sisfbctrl) */ -#define SISFB_COMMAND _IOWR(0xF3,0x05,struct sisfb_cmd) - -/* ioctl for locking sisfb (no register access during lock) */ -/* As of now, only used to avoid register access during - * the ioctls listed above. - */ -#define SISFB_SET_LOCK _IOW(0xF3,0x06,__u32) - -/* ioctls 0xF3 up to 0x3F reserved for sisfb */ - -/****************************************************************/ -/* The following are deprecated and should not be used anymore: */ -/****************************************************************/ -/* ioctl for identifying and giving some info (esp. memory heap start) */ -#define SISFB_GET_INFO_OLD _IOR('n',0xF8,__u32) -/* ioctrl to get current vertical retrace status */ -#define SISFB_GET_VBRSTATUS_OLD _IOR('n',0xF9,__u32) -/* ioctl to enable/disable panning auto-maximize (like nomax parameter) */ -#define SISFB_GET_AUTOMAXIMIZE_OLD _IOR('n',0xFA,__u32) -#define SISFB_SET_AUTOMAXIMIZE_OLD _IOW('n',0xFA,__u32) -/****************************************************************/ -/* End of deprecated ioctl numbers */ -/****************************************************************/ - -/* For fb memory manager (FBIO_ALLOC, FBIO_FREE) */ -struct sis_memreq { - __u32 offset; - __u32 size; -}; - -/**********************************************/ -/* PRIVATE */ -/* (for IN-KERNEL usage only) */ -/**********************************************/ - -#ifdef __KERNEL__ - -#include <linux/pci.h> - -#define UNKNOWN_VGA 0 -#define SIS_300_VGA 1 -#define SIS_315_VGA 2 - -#define SISFB_HAVE_MALLOC_NEW -extern void sis_malloc(struct sis_memreq *req); -extern void sis_malloc_new(struct pci_dev *pdev, struct sis_memreq *req); - -extern void sis_free(u32 base); -extern void sis_free_new(struct pci_dev *pdev, u32 base); -#endif - -#endif diff --git a/ANDROID_3.4.5/include/video/sstfb.h b/ANDROID_3.4.5/include/video/sstfb.h deleted file mode 100644 index c449eace..00000000 --- a/ANDROID_3.4.5/include/video/sstfb.h +++ /dev/null @@ -1,355 +0,0 @@ -/* - * linux/drivers/video/sstfb.h -- voodoo graphics frame buffer - * - * Copyright (c) 2000,2001 Ghozlane Toumi <gtoumi@messel.emse.fr> - * - * Created 28 Aug 2001 by Ghozlane Toumi - */ - - -#ifndef _SSTFB_H_ -#define _SSTFB_H_ - -/* - * - * Debug Stuff - * - */ - -#ifdef SST_DEBUG -# define dprintk(X...) printk("sstfb: " X) -# define SST_DEBUG_REG 1 -# define SST_DEBUG_FUNC 1 -# define SST_DEBUG_VAR 1 -#else -# define dprintk(X...) -# define SST_DEBUG_REG 0 -# define SST_DEBUG_FUNC 0 -# define SST_DEBUG_VAR 0 -#endif - -#if (SST_DEBUG_REG > 0) -# define r_dprintk(X...) dprintk(X) -#else -# define r_dprintk(X...) -#endif -#if (SST_DEBUG_REG > 1) -# define r_ddprintk(X...) dprintk(" " X) -#else -# define r_ddprintk(X...) -#endif - -#if (SST_DEBUG_FUNC > 0) -# define f_dprintk(X...) dprintk(X) -#else -# define f_dprintk(X...) -#endif -#if (SST_DEBUG_FUNC > 1) -# define f_ddprintk(X...) dprintk(" " X) -#else -# define f_ddprintk(X...) -#endif -#if (SST_DEBUG_FUNC > 2) -# define f_dddprintk(X...) dprintk(" " X) -#else -# define f_dddprintk(X...) -#endif - -#if (SST_DEBUG_VAR > 0) -# define v_dprintk(X...) dprintk(X) -# define print_var(V, X...) \ - { \ - dprintk(X); \ - printk(" :\n"); \ - sst_dbg_print_var(V); \ - } -#else -# define v_dprintk(X...) -# define print_var(X,Y...) -#endif - -#define POW2(x) (1ul<<(x)) - -/* - * - * Const - * - */ - -/* pci stuff */ -#define PCI_INIT_ENABLE 0x40 -# define PCI_EN_INIT_WR BIT(0) -# define PCI_EN_FIFO_WR BIT(1) -# define PCI_REMAP_DAC BIT(2) -#define PCI_VCLK_ENABLE 0xc0 /* enable video */ -#define PCI_VCLK_DISABLE 0xe0 - -/* register offsets from memBaseAddr */ -#define STATUS 0x0000 -# define STATUS_FBI_BUSY BIT(7) -#define FBZMODE 0x0110 -# define EN_CLIPPING BIT(0) /* enable clipping */ -# define EN_RGB_WRITE BIT(9) /* enable writes to rgb area */ -# define EN_ALPHA_WRITE BIT(10) -# define ENGINE_INVERT_Y BIT(17) /* invert Y origin (pipe) */ -#define LFBMODE 0x0114 -# define LFB_565 0 /* bits 3:0 .16 bits RGB */ -# define LFB_888 4 /* 24 bits RGB */ -# define LFB_8888 5 /* 32 bits ARGB */ -# define WR_BUFF_FRONT 0 /* write buf select (front) */ -# define WR_BUFF_BACK (1 << 4) /* back */ -# define RD_BUFF_FRONT 0 /* read buff select (front) */ -# define RD_BUFF_BACK (1 << 6) /* back */ -# define EN_PXL_PIPELINE BIT(8) /* pixel pipeline (clip..)*/ -# define LFB_WORD_SWIZZLE_WR BIT(11) /* enable write-wordswap (big-endian) */ -# define LFB_BYTE_SWIZZLE_WR BIT(12) /* enable write-byteswap (big-endian) */ -# define LFB_INVERT_Y BIT(13) /* invert Y origin (LFB) */ -# define LFB_WORD_SWIZZLE_RD BIT(15) /* enable read-wordswap (big-endian) */ -# define LFB_BYTE_SWIZZLE_RD BIT(16) /* enable read-byteswap (big-endian) */ -#define CLIP_LEFT_RIGHT 0x0118 -#define CLIP_LOWY_HIGHY 0x011c -#define NOPCMD 0x0120 -#define FASTFILLCMD 0x0124 -#define SWAPBUFFCMD 0x0128 -#define FBIINIT4 0x0200 /* misc controls */ -# define FAST_PCI_READS 0 /* 1 waitstate */ -# define SLOW_PCI_READS BIT(0) /* 2 ws */ -# define LFB_READ_AHEAD BIT(1) -#define BACKPORCH 0x0208 -#define VIDEODIMENSIONS 0x020c -#define FBIINIT0 0x0210 /* misc+fifo controls */ -# define DIS_VGA_PASSTHROUGH BIT(0) -# define FBI_RESET BIT(1) -# define FIFO_RESET BIT(2) -#define FBIINIT1 0x0214 /* PCI + video controls */ -# define VIDEO_MASK 0x8080010f /* masks video related bits V1+V2*/ -# define FAST_PCI_WRITES 0 /* 0 ws */ -# define SLOW_PCI_WRITES BIT(1) /* 1 ws */ -# define EN_LFB_READ BIT(3) -# define TILES_IN_X_SHIFT 4 -# define VIDEO_RESET BIT(8) -# define EN_BLANKING BIT(12) -# define EN_DATA_OE BIT(13) -# define EN_BLANK_OE BIT(14) -# define EN_HVSYNC_OE BIT(15) -# define EN_DCLK_OE BIT(16) -# define SEL_INPUT_VCLK_2X 0 /* bit 17 */ -# define SEL_INPUT_VCLK_SLAVE BIT(17) -# define SEL_SOURCE_VCLK_SLAVE 0 /* bits 21:20 */ -# define SEL_SOURCE_VCLK_2X_DIV2 (0x01 << 20) -# define SEL_SOURCE_VCLK_2X_SEL (0x02 << 20) -# define EN_24BPP BIT(22) -# define TILES_IN_X_MSB_SHIFT 24 /* v2 */ -# define VCLK_2X_SEL_DEL_SHIFT 27 /* vclk out delay 0,4,6,8ns */ -# define VCLK_DEL_SHIFT 29 /* vclk in delay */ -#define FBIINIT2 0x0218 /* Dram controls */ -# define EN_FAST_RAS_READ BIT(5) -# define EN_DRAM_OE BIT(6) -# define EN_FAST_RD_AHEAD_WR BIT(7) -# define VIDEO_OFFSET_SHIFT 11 /* unit: #rows tile 64x16/2 */ -# define SWAP_DACVSYNC 0 -# define SWAP_DACDATA0 (1 << 9) -# define SWAP_FIFO_STALL (2 << 9) -# define EN_RD_AHEAD_FIFO BIT(21) -# define EN_DRAM_REFRESH BIT(22) -# define DRAM_REFRESH_16 (0x30 << 23) /* dram 16 ms */ -#define DAC_READ FBIINIT2 /* in remap mode */ -#define FBIINIT3 0x021c /* fbi controls */ -# define DISABLE_TEXTURE BIT(6) -# define Y_SWAP_ORIGIN_SHIFT 22 /* Y swap subtraction value */ -#define HSYNC 0x0220 -#define VSYNC 0x0224 -#define DAC_DATA 0x022c -# define DAC_READ_CMD BIT(11) /* set read dacreg mode */ -#define FBIINIT5 0x0244 /* v2 specific */ -# define FBIINIT5_MASK 0xfa40ffff /* mask video bits*/ -# define HDOUBLESCAN BIT(20) -# define VDOUBLESCAN BIT(21) -# define HSYNC_HIGH BIT(23) -# define VSYNC_HIGH BIT(24) -# define INTERLACE BIT(26) -#define FBIINIT6 0x0248 /* v2 specific */ -# define TILES_IN_X_LSB_SHIFT 30 /* v2 */ -#define FBIINIT7 0x024c /* v2 specific */ - -#define BLTSRCBASEADDR 0x02c0 /* BitBLT Source base address */ -#define BLTDSTBASEADDR 0x02c4 /* BitBLT Destination base address */ -#define BLTXYSTRIDES 0x02c8 /* BitBLT Source and Destination strides */ -#define BLTSRCCHROMARANGE 0x02cc /* BitBLT Source Chroma key range */ -#define BLTDSTCHROMARANGE 0x02d0 /* BitBLT Destination Chroma key range */ -#define BLTCLIPX 0x02d4 /* BitBLT Min/Max X clip values */ -#define BLTCLIPY 0x02d8 /* BitBLT Min/Max Y clip values */ -#define BLTSRCXY 0x02e0 /* BitBLT Source starting XY coordinates */ -#define BLTDSTXY 0x02e4 /* BitBLT Destination starting XY coordinates */ -#define BLTSIZE 0x02e8 /* BitBLT width and height */ -#define BLTROP 0x02ec /* BitBLT Raster operations */ -# define BLTROP_COPY 0x0cccc -# define BLTROP_INVERT 0x05555 -# define BLTROP_XOR 0x06666 -#define BLTCOLOR 0x02f0 /* BitBLT and foreground background colors */ -#define BLTCOMMAND 0x02f8 /* BitBLT command mode (v2 specific) */ -# define BLT_SCR2SCR_BITBLT 0 /* Screen-to-Screen BitBLT */ -# define BLT_CPU2SCR_BITBLT 1 /* CPU-to-screen BitBLT */ -# define BLT_RECFILL_BITBLT 2 /* BitBLT Rectangle Fill */ -# define BLT_16BPP_FMT 2 /* 16 BPP (5-6-5 RGB) */ -#define BLTDATA 0x02fc /* BitBLT data for CPU-to-Screen BitBLTs */ -# define LAUNCH_BITBLT BIT(31) /* Launch BitBLT in BltCommand, bltDstXY or bltSize */ - -/* Dac Registers */ -#define DACREG_WMA 0x0 /* pixel write mode address */ -#define DACREG_LUT 0x01 /* color value */ -#define DACREG_RMR 0x02 /* pixel mask */ -#define DACREG_RMA 0x03 /* pixel read mode address */ -/*Dac registers in indexed mode (TI, ATT dacs) */ -#define DACREG_ADDR_I DACREG_WMA -#define DACREG_DATA_I DACREG_RMR -#define DACREG_RMR_I 0x00 -#define DACREG_CR0_I 0x01 -# define DACREG_CR0_EN_INDEXED BIT(0) /* enable indexec mode */ -# define DACREG_CR0_8BIT BIT(1) /* set dac to 8 bits/read */ -# define DACREG_CR0_PWDOWN BIT(3) /* powerdown dac */ -# define DACREG_CR0_16BPP 0x30 /* mode 3 */ -# define DACREG_CR0_24BPP 0x50 /* mode 5 */ -#define DACREG_CR1_I 0x05 -#define DACREG_CC_I 0x06 -# define DACREG_CC_CLKA BIT(7) /* clk A controlled by regs */ -# define DACREG_CC_CLKA_C (2<<4) /* clk A uses reg C */ -# define DACREG_CC_CLKB BIT(3) /* clk B controlled by regs */ -# define DACREG_CC_CLKB_D 3 /* clkB uses reg D */ -#define DACREG_AC0_I 0x48 /* clock A reg C */ -#define DACREG_AC1_I 0x49 -#define DACREG_BD0_I 0x6c /* clock B reg D */ -#define DACREG_BD1_I 0x6d - -/* identification constants */ -#define DACREG_MIR_TI 0x97 -#define DACREG_DIR_TI 0x09 -#define DACREG_MIR_ATT 0x84 -#define DACREG_DIR_ATT 0x09 -/* ics dac specific registers */ -#define DACREG_ICS_PLLWMA 0x04 /* PLL write mode address */ -#define DACREG_ICS_PLLDATA 0x05 /* PLL data /parameter */ -#define DACREG_ICS_CMD 0x06 /* command */ -# define DACREG_ICS_CMD_16BPP 0x50 /* ics color mode 6 (16bpp bypass)*/ -# define DACREG_ICS_CMD_24BPP 0x70 /* ics color mode 7 (24bpp bypass)*/ -# define DACREG_ICS_CMD_PWDOWN BIT(0) /* powerdown dac */ -#define DACREG_ICS_PLLRMA 0x07 /* PLL read mode address */ -/* - * pll parameter register: - * indexed : write addr to PLLWMA, write data in PLLDATA. - * for reads use PLLRMA . - * 8 freq registers (0-7) for video clock (CLK0) - * 2 freq registers (a-b) for graphic clock (CLK1) - */ -#define DACREG_ICS_PLL_CLK0_1_INI 0x55 /* initial pll M value for freq f1 */ -#define DACREG_ICS_PLL_CLK0_7_INI 0x71 /* f7 */ -#define DACREG_ICS_PLL_CLK1_B_INI 0x79 /* fb */ -#define DACREG_ICS_PLL_CTRL 0x0e -# define DACREG_ICS_CLK0 BIT(5) -# define DACREG_ICS_CLK0_0 0 -# define DACREG_ICS_CLK1_A 0 /* bit4 */ - -/* sst default init registers */ -#define FBIINIT0_DEFAULT DIS_VGA_PASSTHROUGH - -#define FBIINIT1_DEFAULT \ - ( \ - FAST_PCI_WRITES \ -/* SLOW_PCI_WRITES*/ \ - | VIDEO_RESET \ - | 10 << TILES_IN_X_SHIFT\ - | SEL_SOURCE_VCLK_2X_SEL\ - | EN_LFB_READ \ - ) - -#define FBIINIT2_DEFAULT \ - ( \ - SWAP_DACVSYNC \ - | EN_DRAM_OE \ - | DRAM_REFRESH_16 \ - | EN_DRAM_REFRESH \ - | EN_FAST_RAS_READ \ - | EN_RD_AHEAD_FIFO \ - | EN_FAST_RD_AHEAD_WR \ - ) - -#define FBIINIT3_DEFAULT \ - ( DISABLE_TEXTURE ) - -#define FBIINIT4_DEFAULT \ - ( \ - FAST_PCI_READS \ -/* SLOW_PCI_READS*/ \ - | LFB_READ_AHEAD \ - ) -/* Careful with this one : writing back the data just read will trash the DAC - reading some fields give logic value on pins, but setting this field will - set the source signal driving the pin. conclusion : just use the default - as a base before writing back . -*/ -#define FBIINIT6_DEFAULT (0x0) - -/* - * - * Misc Const - * - */ - -/* ioctl to enable/disable VGA passthrough */ -#define SSTFB_SET_VGAPASS _IOW('F', 0xdd, __u32) -#define SSTFB_GET_VGAPASS _IOR('F', 0xdd, __u32) - - -/* used to know witch clock to set */ -enum { - VID_CLOCK=0, - GFX_CLOCK=1, -}; - -/* freq max */ -#define DAC_FREF 14318 /* DAC reference freq (Khz) */ -#define VCO_MAX 260000 - -/* - * driver structs - */ - -struct pll_timing { - unsigned int m; - unsigned int n; - unsigned int p; -}; - -struct dac_switch { - const char *name; - int (*detect) (struct fb_info *info); - int (*set_pll) (struct fb_info *info, const struct pll_timing *t, const int clock); - void (*set_vidmod) (struct fb_info *info, const int bpp); -}; - -struct sst_spec { - char * name; - int default_gfx_clock; /* 50000 for voodoo1, 75000 for voodoo2 */ - int max_gfxclk; /* ! in Mhz ie 60 for voodoo 1 */ -}; - -struct sstfb_par { - u32 palette[16]; - unsigned int yDim; - unsigned int hSyncOn; /* hsync_len */ - unsigned int hSyncOff; /* left_margin + xres + right_margin */ - unsigned int hBackPorch;/* left_margin */ - unsigned int vSyncOn; - unsigned int vSyncOff; - unsigned int vBackPorch; - struct pll_timing pll; - unsigned int tiles_in_X;/* num of tiles in X res */ - u8 __iomem *mmio_vbase; - struct dac_switch dac_sw; /* dac specific functions */ - struct pci_dev *dev; - int type; - u8 revision; - u8 vgapass; /* VGA pass through: 1=enabled, 0=disabled */ -}; - -#endif /* _SSTFB_H_ */ diff --git a/ANDROID_3.4.5/include/video/tdfx.h b/ANDROID_3.4.5/include/video/tdfx.h deleted file mode 100644 index befbaf0a..00000000 --- a/ANDROID_3.4.5/include/video/tdfx.h +++ /dev/null @@ -1,208 +0,0 @@ -#ifndef _TDFX_H -#define _TDFX_H - -#include <linux/i2c.h> -#include <linux/i2c-algo-bit.h> - -/* membase0 register offsets */ -#define STATUS 0x00 -#define PCIINIT0 0x04 -#define SIPMONITOR 0x08 -#define LFBMEMORYCONFIG 0x0c -#define MISCINIT0 0x10 -#define MISCINIT1 0x14 -#define DRAMINIT0 0x18 -#define DRAMINIT1 0x1c -#define AGPINIT 0x20 -#define TMUGBEINIT 0x24 -#define VGAINIT0 0x28 -#define VGAINIT1 0x2c -#define DRAMCOMMAND 0x30 -#define DRAMDATA 0x34 -/* reserved 0x38 */ -/* reserved 0x3c */ -#define PLLCTRL0 0x40 -#define PLLCTRL1 0x44 -#define PLLCTRL2 0x48 -#define DACMODE 0x4c -#define DACADDR 0x50 -#define DACDATA 0x54 -#define RGBMAXDELTA 0x58 -#define VIDPROCCFG 0x5c -#define HWCURPATADDR 0x60 -#define HWCURLOC 0x64 -#define HWCURC0 0x68 -#define HWCURC1 0x6c -#define VIDINFORMAT 0x70 -#define VIDINSTATUS 0x74 -#define VIDSERPARPORT 0x78 -#define VIDINXDELTA 0x7c -#define VIDININITERR 0x80 -#define VIDINYDELTA 0x84 -#define VIDPIXBUFTHOLD 0x88 -#define VIDCHRMIN 0x8c -#define VIDCHRMAX 0x90 -#define VIDCURLIN 0x94 -#define VIDSCREENSIZE 0x98 -#define VIDOVRSTARTCRD 0x9c -#define VIDOVRENDCRD 0xa0 -#define VIDOVRDUDX 0xa4 -#define VIDOVRDUDXOFF 0xa8 -#define VIDOVRDVDY 0xac -/* ... */ -#define VIDOVRDVDYOFF 0xe0 -#define VIDDESKSTART 0xe4 -#define VIDDESKSTRIDE 0xe8 -#define VIDINADDR0 0xec -#define VIDINADDR1 0xf0 -#define VIDINADDR2 0xf4 -#define VIDINSTRIDE 0xf8 -#define VIDCUROVRSTART 0xfc - -#define INTCTRL (0x00100000 + 0x04) -#define CLIP0MIN (0x00100000 + 0x08) -#define CLIP0MAX (0x00100000 + 0x0c) -#define DSTBASE (0x00100000 + 0x10) -#define DSTFORMAT (0x00100000 + 0x14) -#define SRCBASE (0x00100000 + 0x34) -#define COMMANDEXTRA_2D (0x00100000 + 0x38) -#define CLIP1MIN (0x00100000 + 0x4c) -#define CLIP1MAX (0x00100000 + 0x50) -#define SRCFORMAT (0x00100000 + 0x54) -#define SRCSIZE (0x00100000 + 0x58) -#define SRCXY (0x00100000 + 0x5c) -#define COLORBACK (0x00100000 + 0x60) -#define COLORFORE (0x00100000 + 0x64) -#define DSTSIZE (0x00100000 + 0x68) -#define DSTXY (0x00100000 + 0x6c) -#define COMMAND_2D (0x00100000 + 0x70) -#define LAUNCH_2D (0x00100000 + 0x80) - -#define COMMAND_3D (0x00200000 + 0x120) - -/* register bitfields (not all, only as needed) */ - -/* COMMAND_2D reg. values */ -#define TDFX_ROP_COPY 0xcc /* src */ -#define TDFX_ROP_INVERT 0x55 /* NOT dst */ -#define TDFX_ROP_XOR 0x66 /* src XOR dst */ - -#define AUTOINC_DSTX BIT(10) -#define AUTOINC_DSTY BIT(11) -#define COMMAND_2D_FILLRECT 0x05 -#define COMMAND_2D_S2S_BITBLT 0x01 /* screen to screen */ -#define COMMAND_2D_H2S_BITBLT 0x03 /* host to screen */ - -#define COMMAND_3D_NOP 0x00 -#define STATUS_RETRACE BIT(6) -#define STATUS_BUSY BIT(9) -#define MISCINIT1_CLUT_INV BIT(0) -#define MISCINIT1_2DBLOCK_DIS BIT(15) -#define DRAMINIT0_SGRAM_NUM BIT(26) -#define DRAMINIT0_SGRAM_TYPE BIT(27) -#define DRAMINIT0_SGRAM_TYPE_MASK (BIT(27) | BIT(28) | BIT(29)) -#define DRAMINIT0_SGRAM_TYPE_SHIFT 27 -#define DRAMINIT1_MEM_SDRAM BIT(30) -#define VGAINIT0_VGA_DISABLE BIT(0) -#define VGAINIT0_EXT_TIMING BIT(1) -#define VGAINIT0_8BIT_DAC BIT(2) -#define VGAINIT0_EXT_ENABLE BIT(6) -#define VGAINIT0_WAKEUP_3C3 BIT(8) -#define VGAINIT0_LEGACY_DISABLE BIT(9) -#define VGAINIT0_ALT_READBACK BIT(10) -#define VGAINIT0_FAST_BLINK BIT(11) -#define VGAINIT0_EXTSHIFTOUT BIT(12) -#define VGAINIT0_DECODE_3C6 BIT(13) -#define VGAINIT0_SGRAM_HBLANK_DISABLE BIT(22) -#define VGAINIT1_MASK 0x1fffff -#define VIDCFG_VIDPROC_ENABLE BIT(0) -#define VIDCFG_CURS_X11 BIT(1) -#define VIDCFG_INTERLACE BIT(3) -#define VIDCFG_HALF_MODE BIT(4) -#define VIDCFG_DESK_ENABLE BIT(7) -#define VIDCFG_CLUT_BYPASS BIT(10) -#define VIDCFG_2X BIT(26) -#define VIDCFG_HWCURSOR_ENABLE BIT(27) -#define VIDCFG_PIXFMT_SHIFT 18 -#define DACMODE_2X BIT(0) - -/* I2C bit locations in the VIDSERPARPORT register */ -#define DDC_ENAB 0x00040000 -#define DDC_SCL_OUT 0x00080000 -#define DDC_SDA_OUT 0x00100000 -#define DDC_SCL_IN 0x00200000 -#define DDC_SDA_IN 0x00400000 -#define I2C_ENAB 0x00800000 -#define I2C_SCL_OUT 0x01000000 -#define I2C_SDA_OUT 0x02000000 -#define I2C_SCL_IN 0x04000000 -#define I2C_SDA_IN 0x08000000 - -/* VGA rubbish, need to change this for multihead support */ -#define MISC_W 0x3c2 -#define MISC_R 0x3cc -#define SEQ_I 0x3c4 -#define SEQ_D 0x3c5 -#define CRT_I 0x3d4 -#define CRT_D 0x3d5 -#define ATT_IW 0x3c0 -#define IS1_R 0x3da -#define GRA_I 0x3ce -#define GRA_D 0x3cf - -#ifdef __KERNEL__ - -struct banshee_reg { - /* VGA rubbish */ - unsigned char att[21]; - unsigned char crt[25]; - unsigned char gra[9]; - unsigned char misc[1]; - unsigned char seq[5]; - - /* Banshee extensions */ - unsigned char ext[2]; - unsigned long vidcfg; - unsigned long vidpll; - unsigned long mempll; - unsigned long gfxpll; - unsigned long dacmode; - unsigned long vgainit0; - unsigned long vgainit1; - unsigned long screensize; - unsigned long stride; - unsigned long cursloc; - unsigned long curspataddr; - unsigned long cursc0; - unsigned long cursc1; - unsigned long startaddr; - unsigned long clip0min; - unsigned long clip0max; - unsigned long clip1min; - unsigned long clip1max; - unsigned long miscinit0; -}; - -struct tdfx_par; - -struct tdfxfb_i2c_chan { - struct tdfx_par *par; - struct i2c_adapter adapter; - struct i2c_algo_bit_data algo; -}; - -struct tdfx_par { - u32 max_pixclock; - u32 palette[16]; - void __iomem *regbase_virt; - unsigned long iobase; - int mtrr_handle; -#ifdef CONFIG_FB_3DFX_I2C - struct tdfxfb_i2c_chan chan[2]; -#endif -}; - -#endif /* __KERNEL__ */ - -#endif /* _TDFX_H */ - diff --git a/ANDROID_3.4.5/include/video/tgafb.h b/ANDROID_3.4.5/include/video/tgafb.h deleted file mode 100644 index 7bc5e2c1..00000000 --- a/ANDROID_3.4.5/include/video/tgafb.h +++ /dev/null @@ -1,280 +0,0 @@ -/* - * linux/drivers/video/tgafb.h -- DEC 21030 TGA frame buffer device - * - * Copyright (C) 1999,2000 Martin Lucina, Tom Zerucha - * - * $Id: tgafb.h,v 1.4.2.3 2000/04/04 06:44:56 mato Exp $ - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive for - * more details. - */ - -#ifndef TGAFB_H -#define TGAFB_H - -/* - * TGA hardware description (minimal) - */ - -#define TGA_TYPE_8PLANE 0 -#define TGA_TYPE_24PLANE 1 -#define TGA_TYPE_24PLUSZ 3 - -/* - * Offsets within Memory Space - */ - -#define TGA_ROM_OFFSET 0x0000000 -#define TGA_REGS_OFFSET 0x0100000 -#define TGA_8PLANE_FB_OFFSET 0x0200000 -#define TGA_24PLANE_FB_OFFSET 0x0804000 -#define TGA_24PLUSZ_FB_OFFSET 0x1004000 - -#define TGA_FOREGROUND_REG 0x0020 -#define TGA_BACKGROUND_REG 0x0024 -#define TGA_PLANEMASK_REG 0x0028 -#define TGA_PIXELMASK_ONESHOT_REG 0x002c -#define TGA_MODE_REG 0x0030 -#define TGA_RASTEROP_REG 0x0034 -#define TGA_PIXELSHIFT_REG 0x0038 -#define TGA_DEEP_REG 0x0050 -#define TGA_START_REG 0x0054 -#define TGA_PIXELMASK_REG 0x005c -#define TGA_CURSOR_BASE_REG 0x0060 -#define TGA_HORIZ_REG 0x0064 -#define TGA_VERT_REG 0x0068 -#define TGA_BASE_ADDR_REG 0x006c -#define TGA_VALID_REG 0x0070 -#define TGA_CURSOR_XY_REG 0x0074 -#define TGA_INTR_STAT_REG 0x007c -#define TGA_DATA_REG 0x0080 -#define TGA_RAMDAC_SETUP_REG 0x00c0 -#define TGA_BLOCK_COLOR0_REG 0x0140 -#define TGA_BLOCK_COLOR1_REG 0x0144 -#define TGA_BLOCK_COLOR2_REG 0x0148 -#define TGA_BLOCK_COLOR3_REG 0x014c -#define TGA_BLOCK_COLOR4_REG 0x0150 -#define TGA_BLOCK_COLOR5_REG 0x0154 -#define TGA_BLOCK_COLOR6_REG 0x0158 -#define TGA_BLOCK_COLOR7_REG 0x015c -#define TGA_COPY64_SRC 0x0160 -#define TGA_COPY64_DST 0x0164 -#define TGA_CLOCK_REG 0x01e8 -#define TGA_RAMDAC_REG 0x01f0 -#define TGA_CMD_STAT_REG 0x01f8 - - -/* - * Useful defines for managing the registers - */ - -#define TGA_HORIZ_ODD 0x80000000 -#define TGA_HORIZ_POLARITY 0x40000000 -#define TGA_HORIZ_ACT_MSB 0x30000000 -#define TGA_HORIZ_BP 0x0fe00000 -#define TGA_HORIZ_SYNC 0x001fc000 -#define TGA_HORIZ_FP 0x00007c00 -#define TGA_HORIZ_ACT_LSB 0x000001ff - -#define TGA_VERT_SE 0x80000000 -#define TGA_VERT_POLARITY 0x40000000 -#define TGA_VERT_RESERVED 0x30000000 -#define TGA_VERT_BP 0x0fc00000 -#define TGA_VERT_SYNC 0x003f0000 -#define TGA_VERT_FP 0x0000f800 -#define TGA_VERT_ACTIVE 0x000007ff - -#define TGA_VALID_VIDEO 0x01 -#define TGA_VALID_BLANK 0x02 -#define TGA_VALID_CURSOR 0x04 - -#define TGA_MODE_SBM_8BPP 0x000 -#define TGA_MODE_SBM_24BPP 0x300 - -#define TGA_MODE_SIMPLE 0x00 -#define TGA_MODE_SIMPLEZ 0x10 -#define TGA_MODE_OPAQUE_STIPPLE 0x01 -#define TGA_MODE_OPAQUE_FILL 0x21 -#define TGA_MODE_TRANSPARENT_STIPPLE 0x03 -#define TGA_MODE_TRANSPARENT_FILL 0x23 -#define TGA_MODE_BLOCK_STIPPLE 0x0d -#define TGA_MODE_BLOCK_FILL 0x2d -#define TGA_MODE_COPY 0x07 -#define TGA_MODE_DMA_READ_COPY_ND 0x17 -#define TGA_MODE_DMA_READ_COPY_D 0x37 -#define TGA_MODE_DMA_WRITE_COPY 0x1f - - -/* - * Useful defines for managing the ICS1562 PLL clock - */ - -#define TGA_PLL_BASE_FREQ 14318 /* .18 */ -#define TGA_PLL_MAX_FREQ 230000 - - -/* - * Useful defines for managing the BT485 on the 8-plane TGA - */ - -#define BT485_READ_BIT 0x01 -#define BT485_WRITE_BIT 0x00 - -#define BT485_ADDR_PAL_WRITE 0x00 -#define BT485_DATA_PAL 0x02 -#define BT485_PIXEL_MASK 0x04 -#define BT485_ADDR_PAL_READ 0x06 -#define BT485_ADDR_CUR_WRITE 0x08 -#define BT485_DATA_CUR 0x0a -#define BT485_CMD_0 0x0c -#define BT485_ADDR_CUR_READ 0x0e -#define BT485_CMD_1 0x10 -#define BT485_CMD_2 0x12 -#define BT485_STATUS 0x14 -#define BT485_CMD_3 0x14 -#define BT485_CUR_RAM 0x16 -#define BT485_CUR_LOW_X 0x18 -#define BT485_CUR_HIGH_X 0x1a -#define BT485_CUR_LOW_Y 0x1c -#define BT485_CUR_HIGH_Y 0x1e - - -/* - * Useful defines for managing the BT463 on the 24-plane TGAs/SFB+s - */ - -#define BT463_ADDR_LO 0x0 -#define BT463_ADDR_HI 0x1 -#define BT463_REG_ACC 0x2 -#define BT463_PALETTE 0x3 - -#define BT463_CUR_CLR_0 0x0100 -#define BT463_CUR_CLR_1 0x0101 - -#define BT463_CMD_REG_0 0x0201 -#define BT463_CMD_REG_1 0x0202 -#define BT463_CMD_REG_2 0x0203 - -#define BT463_READ_MASK_0 0x0205 -#define BT463_READ_MASK_1 0x0206 -#define BT463_READ_MASK_2 0x0207 -#define BT463_READ_MASK_3 0x0208 - -#define BT463_BLINK_MASK_0 0x0209 -#define BT463_BLINK_MASK_1 0x020a -#define BT463_BLINK_MASK_2 0x020b -#define BT463_BLINK_MASK_3 0x020c - -#define BT463_WINDOW_TYPE_BASE 0x0300 - -/* - * Useful defines for managing the BT459 on the 8-plane SFB+s - */ - -#define BT459_ADDR_LO 0x0 -#define BT459_ADDR_HI 0x1 -#define BT459_REG_ACC 0x2 -#define BT459_PALETTE 0x3 - -#define BT459_CUR_CLR_1 0x0181 -#define BT459_CUR_CLR_2 0x0182 -#define BT459_CUR_CLR_3 0x0183 - -#define BT459_CMD_REG_0 0x0201 -#define BT459_CMD_REG_1 0x0202 -#define BT459_CMD_REG_2 0x0203 - -#define BT459_READ_MASK 0x0204 - -#define BT459_BLINK_MASK 0x0206 - -#define BT459_CUR_CMD_REG 0x0300 - -/* - * The framebuffer driver private data. - */ - -struct tga_par { - /* PCI/TC device. */ - struct device *dev; - - /* Device dependent information. */ - void __iomem *tga_mem_base; - void __iomem *tga_fb_base; - void __iomem *tga_regs_base; - u8 tga_type; /* TGA_TYPE_XXX */ - u8 tga_chip_rev; /* dc21030 revision */ - - /* Remember blank mode. */ - u8 vesa_blanked; - - /* Define the video mode. */ - u32 xres, yres; /* resolution in pixels */ - u32 htimings; /* horizontal timing register */ - u32 vtimings; /* vertical timing register */ - u32 pll_freq; /* pixclock in mhz */ - u32 bits_per_pixel; /* bits per pixel */ - u32 sync_on_green; /* set if sync is on green */ - u32 palette[16]; -}; - - -/* - * Macros for reading/writing TGA and RAMDAC registers - */ - -static inline void -TGA_WRITE_REG(struct tga_par *par, u32 v, u32 r) -{ - writel(v, par->tga_regs_base +r); -} - -static inline u32 -TGA_READ_REG(struct tga_par *par, u32 r) -{ - return readl(par->tga_regs_base +r); -} - -static inline void -BT485_WRITE(struct tga_par *par, u8 v, u8 r) -{ - TGA_WRITE_REG(par, r, TGA_RAMDAC_SETUP_REG); - TGA_WRITE_REG(par, v | (r << 8), TGA_RAMDAC_REG); -} - -static inline void -BT463_LOAD_ADDR(struct tga_par *par, u16 a) -{ - TGA_WRITE_REG(par, BT463_ADDR_LO<<2, TGA_RAMDAC_SETUP_REG); - TGA_WRITE_REG(par, (BT463_ADDR_LO<<10) | (a & 0xff), TGA_RAMDAC_REG); - TGA_WRITE_REG(par, BT463_ADDR_HI<<2, TGA_RAMDAC_SETUP_REG); - TGA_WRITE_REG(par, (BT463_ADDR_HI<<10) | (a >> 8), TGA_RAMDAC_REG); -} - -static inline void -BT463_WRITE(struct tga_par *par, u32 m, u16 a, u8 v) -{ - BT463_LOAD_ADDR(par, a); - TGA_WRITE_REG(par, m << 2, TGA_RAMDAC_SETUP_REG); - TGA_WRITE_REG(par, m << 10 | v, TGA_RAMDAC_REG); -} - -static inline void -BT459_LOAD_ADDR(struct tga_par *par, u16 a) -{ - TGA_WRITE_REG(par, BT459_ADDR_LO << 2, TGA_RAMDAC_SETUP_REG); - TGA_WRITE_REG(par, a & 0xff, TGA_RAMDAC_REG); - TGA_WRITE_REG(par, BT459_ADDR_HI << 2, TGA_RAMDAC_SETUP_REG); - TGA_WRITE_REG(par, a >> 8, TGA_RAMDAC_REG); -} - -static inline void -BT459_WRITE(struct tga_par *par, u32 m, u16 a, u8 v) -{ - BT459_LOAD_ADDR(par, a); - TGA_WRITE_REG(par, m << 2, TGA_RAMDAC_SETUP_REG); - TGA_WRITE_REG(par, v, TGA_RAMDAC_REG); -} - -#endif /* TGAFB_H */ diff --git a/ANDROID_3.4.5/include/video/trident.h b/ANDROID_3.4.5/include/video/trident.h deleted file mode 100644 index b6ce19d1..00000000 --- a/ANDROID_3.4.5/include/video/trident.h +++ /dev/null @@ -1,146 +0,0 @@ - -#ifndef TRIDENTFB_DEBUG -#define TRIDENTFB_DEBUG 0 -#endif - -#if TRIDENTFB_DEBUG -#define debug(f, a...) printk("%s:" f, __func__ , ## a); -#else -#define debug(f, a...) -#endif - -#define output(f, a...) pr_info("tridentfb: " f, ## a) - -#define Kb (1024) -#define Mb (Kb*Kb) - -/* PCI IDS of supported cards temporarily here */ - -#define CYBER9320 0x9320 -#define CYBER9388 0x9388 -#define CYBER9382 0x9382 /* the real PCI id for this is 9660 */ -#define CYBER9385 0x9385 /* ditto */ -#define CYBER9397 0x9397 -#define CYBER9397DVD 0x939A -#define CYBER9520 0x9520 -#define CYBER9525DVD 0x9525 -#define TGUI9440 0x9440 -#define TGUI9660 0x9660 -#define PROVIDIA9685 0x9685 -#define IMAGE975 0x9750 -#define IMAGE985 0x9850 -#define BLADE3D 0x9880 -#define CYBERBLADEE4 0x9540 -#define CYBERBLADEi7 0x8400 -#define CYBERBLADEi7D 0x8420 -#define CYBERBLADEi1 0x8500 -#define CYBERBLADEi1D 0x8520 -#define CYBERBLADEAi1 0x8600 -#define CYBERBLADEAi1D 0x8620 -#define CYBERBLADEXPAi1 0x8820 -#define CYBERBLADEXPm8 0x9910 -#define CYBERBLADEXPm16 0x9930 - -/* these defines are for 'lcd' variable */ -#define LCD_STRETCH 0 -#define LCD_CENTER 1 -#define LCD_BIOS 2 - -/* General Registers */ -#define SPR 0x1F /* Software Programming Register (videoram) */ - -/* 3C4 */ -#define RevisionID 0x09 -#define OldOrNew 0x0B -#define ConfPort1 0x0C -#define ConfPort2 0x0C -#define NewMode2 0x0D -#define NewMode1 0x0E -#define Protection 0x11 -#define MCLKLow 0x16 -#define MCLKHigh 0x17 -#define ClockLow 0x18 -#define ClockHigh 0x19 -#define SSetup 0x20 -#define SKey 0x37 -#define SPKey 0x57 - -/* 3x4 */ -#define CRTCModuleTest 0x1E -#define FIFOControl 0x20 -#define LinearAddReg 0x21 -#define DRAMTiming 0x23 -#define New32 0x23 -#define RAMDACTiming 0x25 -#define CRTHiOrd 0x27 -#define AddColReg 0x29 -#define InterfaceSel 0x2A -#define HorizOverflow 0x2B -#define GETest 0x2D -#define Performance 0x2F -#define GraphEngReg 0x36 -#define I2C 0x37 -#define PixelBusReg 0x38 -#define PCIReg 0x39 -#define DRAMControl 0x3A -#define MiscContReg 0x3C -#define CursorXLow 0x40 -#define CursorXHigh 0x41 -#define CursorYLow 0x42 -#define CursorYHigh 0x43 -#define CursorLocLow 0x44 -#define CursorLocHigh 0x45 -#define CursorXOffset 0x46 -#define CursorYOffset 0x47 -#define CursorFG1 0x48 -#define CursorFG2 0x49 -#define CursorFG3 0x4A -#define CursorFG4 0x4B -#define CursorBG1 0x4C -#define CursorBG2 0x4D -#define CursorBG3 0x4E -#define CursorBG4 0x4F -#define CursorControl 0x50 -#define PCIRetry 0x55 -#define PreEndControl 0x56 -#define PreEndFetch 0x57 -#define PCIMaster 0x60 -#define Enhancement0 0x62 -#define NewEDO 0x64 -#define TVinterface 0xC0 -#define TVMode 0xC1 -#define ClockControl 0xCF - - -/* 3CE */ -#define MiscExtFunc 0x0F -#define PowerStatus 0x23 -#define MiscIntContReg 0x2F -#define CyberControl 0x30 -#define CyberEnhance 0x31 -#define FPConfig 0x33 -#define VertStretch 0x52 -#define HorStretch 0x53 -#define BiosMode 0x5c -#define BiosReg 0x5d - -/* Graphics Engine */ -#define STATUS 0x2120 -#define OLDCMD 0x2124 -#define DRAWFL 0x2128 -#define OLDCLR 0x212C -#define OLDDST 0x2138 -#define OLDSRC 0x213C -#define OLDDIM 0x2140 -#define CMD 0x2144 -#define ROP 0x2148 -#define COLOR 0x2160 -#define BGCOLOR 0x2164 -#define SRC1 0x2100 -#define SRC2 0x2104 -#define DST1 0x2108 -#define DST2 0x210C - -#define ROP_S 0xCC -#define ROP_P 0xF0 -#define ROP_X 0x66 diff --git a/ANDROID_3.4.5/include/video/udlfb.h b/ANDROID_3.4.5/include/video/udlfb.h deleted file mode 100644 index f9466fa5..00000000 --- a/ANDROID_3.4.5/include/video/udlfb.h +++ /dev/null @@ -1,97 +0,0 @@ -#ifndef UDLFB_H -#define UDLFB_H - -/* - * TODO: Propose standard fb.h ioctl for reporting damage, - * using _IOWR() and one of the existing area structs from fb.h - * Consider these ioctls deprecated, but they're still used by the - * DisplayLink X server as yet - need both to be modified in tandem - * when new ioctl(s) are ready. - */ -#define DLFB_IOCTL_RETURN_EDID 0xAD -#define DLFB_IOCTL_REPORT_DAMAGE 0xAA -struct dloarea { - int x, y; - int w, h; - int x2, y2; -}; - -struct urb_node { - struct list_head entry; - struct dlfb_data *dev; - struct delayed_work release_urb_work; - struct urb *urb; -}; - -struct urb_list { - struct list_head list; - spinlock_t lock; - struct semaphore limit_sem; - int available; - int count; - size_t size; -}; - -struct dlfb_data { - struct usb_device *udev; - struct device *gdev; /* &udev->dev */ - struct fb_info *info; - struct urb_list urbs; - struct kref kref; - char *backing_buffer; - int fb_count; - bool virtualized; /* true when physical usb device not present */ - struct delayed_work init_framebuffer_work; - struct delayed_work free_framebuffer_work; - atomic_t usb_active; /* 0 = update virtual buffer, but no usb traffic */ - atomic_t lost_pixels; /* 1 = a render op failed. Need screen refresh */ - char *edid; /* null until we read edid from hw or get from sysfs */ - size_t edid_size; - int sku_pixel_limit; - int base16; - int base8; - u32 pseudo_palette[256]; - int blank_mode; /*one of FB_BLANK_ */ - /* blit-only rendering path metrics, exposed through sysfs */ - atomic_t bytes_rendered; /* raw pixel-bytes driver asked to render */ - atomic_t bytes_identical; /* saved effort with backbuffer comparison */ - atomic_t bytes_sent; /* to usb, after compression including overhead */ - atomic_t cpu_kcycles_used; /* transpired during pixel processing */ -}; - -#define NR_USB_REQUEST_I2C_SUB_IO 0x02 -#define NR_USB_REQUEST_CHANNEL 0x12 - -/* -BULK_SIZE as per usb-skeleton. Can we get full page and avoid overhead? */ -#define BULK_SIZE 512 -#define MAX_TRANSFER (PAGE_SIZE*16 - BULK_SIZE) -#define WRITES_IN_FLIGHT (4) - -#define MAX_VENDOR_DESCRIPTOR_SIZE 256 - -#define GET_URB_TIMEOUT HZ -#define FREE_URB_TIMEOUT (HZ*2) - -#define BPP 2 -#define MAX_CMD_PIXELS 255 - -#define RLX_HEADER_BYTES 7 -#define MIN_RLX_PIX_BYTES 4 -#define MIN_RLX_CMD_BYTES (RLX_HEADER_BYTES + MIN_RLX_PIX_BYTES) - -#define RLE_HEADER_BYTES 6 -#define MIN_RLE_PIX_BYTES 3 -#define MIN_RLE_CMD_BYTES (RLE_HEADER_BYTES + MIN_RLE_PIX_BYTES) - -#define RAW_HEADER_BYTES 6 -#define MIN_RAW_PIX_BYTES 2 -#define MIN_RAW_CMD_BYTES (RAW_HEADER_BYTES + MIN_RAW_PIX_BYTES) - -#define DL_DEFIO_WRITE_DELAY 5 /* fb_deferred_io.delay in jiffies */ -#define DL_DEFIO_WRITE_DISABLE (HZ*60) /* "disable" with long delay */ - -/* remove these once align.h patch is taken into kernel */ -#define DL_ALIGN_UP(x, a) ALIGN(x, a) -#define DL_ALIGN_DOWN(x, a) ALIGN(x-(a-1), a) - -#endif diff --git a/ANDROID_3.4.5/include/video/uvesafb.h b/ANDROID_3.4.5/include/video/uvesafb.h deleted file mode 100644 index 0993a220..00000000 --- a/ANDROID_3.4.5/include/video/uvesafb.h +++ /dev/null @@ -1,195 +0,0 @@ -#ifndef _UVESAFB_H -#define _UVESAFB_H - -#include <linux/types.h> - -struct v86_regs { - __u32 ebx; - __u32 ecx; - __u32 edx; - __u32 esi; - __u32 edi; - __u32 ebp; - __u32 eax; - __u32 eip; - __u32 eflags; - __u32 esp; - __u16 cs; - __u16 ss; - __u16 es; - __u16 ds; - __u16 fs; - __u16 gs; -}; - -/* Task flags */ -#define TF_VBEIB 0x01 -#define TF_BUF_ESDI 0x02 -#define TF_BUF_ESBX 0x04 -#define TF_BUF_RET 0x08 -#define TF_EXIT 0x10 - -struct uvesafb_task { - __u8 flags; - int buf_len; - struct v86_regs regs; -}; - -/* Constants for the capabilities field - * in vbe_ib */ -#define VBE_CAP_CAN_SWITCH_DAC 0x01 -#define VBE_CAP_VGACOMPAT 0x02 - -/* The VBE Info Block */ -struct vbe_ib { - char vbe_signature[4]; - __u16 vbe_version; - __u32 oem_string_ptr; - __u32 capabilities; - __u32 mode_list_ptr; - __u16 total_memory; - __u16 oem_software_rev; - __u32 oem_vendor_name_ptr; - __u32 oem_product_name_ptr; - __u32 oem_product_rev_ptr; - __u8 reserved[222]; - char oem_data[256]; - char misc_data[512]; -} __attribute__ ((packed)); - -#ifdef __KERNEL__ - -/* VBE CRTC Info Block */ -struct vbe_crtc_ib { - u16 horiz_total; - u16 horiz_start; - u16 horiz_end; - u16 vert_total; - u16 vert_start; - u16 vert_end; - u8 flags; - u32 pixel_clock; - u16 refresh_rate; - u8 reserved[40]; -} __attribute__ ((packed)); - -#define VBE_MODE_VGACOMPAT 0x20 -#define VBE_MODE_COLOR 0x08 -#define VBE_MODE_SUPPORTEDHW 0x01 -#define VBE_MODE_GRAPHICS 0x10 -#define VBE_MODE_LFB 0x80 - -#define VBE_MODE_MASK (VBE_MODE_COLOR | VBE_MODE_SUPPORTEDHW | \ - VBE_MODE_GRAPHICS | VBE_MODE_LFB) - -/* VBE Mode Info Block */ -struct vbe_mode_ib { - /* for all VBE revisions */ - u16 mode_attr; - u8 winA_attr; - u8 winB_attr; - u16 win_granularity; - u16 win_size; - u16 winA_seg; - u16 winB_seg; - u32 win_func_ptr; - u16 bytes_per_scan_line; - - /* for VBE 1.2+ */ - u16 x_res; - u16 y_res; - u8 x_char_size; - u8 y_char_size; - u8 planes; - u8 bits_per_pixel; - u8 banks; - u8 memory_model; - u8 bank_size; - u8 image_pages; - u8 reserved1; - - /* Direct color fields for direct/6 and YUV/7 memory models. */ - /* Offsets are bit positions of lsb in the mask. */ - u8 red_len; - u8 red_off; - u8 green_len; - u8 green_off; - u8 blue_len; - u8 blue_off; - u8 rsvd_len; - u8 rsvd_off; - u8 direct_color_info; /* direct color mode attributes */ - - /* for VBE 2.0+ */ - u32 phys_base_ptr; - u8 reserved2[6]; - - /* for VBE 3.0+ */ - u16 lin_bytes_per_scan_line; - u8 bnk_image_pages; - u8 lin_image_pages; - u8 lin_red_len; - u8 lin_red_off; - u8 lin_green_len; - u8 lin_green_off; - u8 lin_blue_len; - u8 lin_blue_off; - u8 lin_rsvd_len; - u8 lin_rsvd_off; - u32 max_pixel_clock; - u16 mode_id; - u8 depth; -} __attribute__ ((packed)); - -#define UVESAFB_DEFAULT_MODE "640x480-16" - -/* How long to wait for a reply from userspace [ms] */ -#define UVESAFB_TIMEOUT 5000 - -/* Max number of concurrent tasks */ -#define UVESAFB_TASKS_MAX 16 - -#define dac_reg (0x3c8) -#define dac_val (0x3c9) - -struct uvesafb_pal_entry { - u_char blue, green, red, pad; -} __attribute__ ((packed)); - -struct uvesafb_ktask { - struct uvesafb_task t; - void *buf; - struct completion *done; - u32 ack; -}; - -static int uvesafb_exec(struct uvesafb_ktask *tsk); - -#define UVESAFB_EXACT_RES 1 -#define UVESAFB_EXACT_DEPTH 2 - -struct uvesafb_par { - struct vbe_ib vbe_ib; /* VBE Info Block */ - struct vbe_mode_ib *vbe_modes; /* list of supported VBE modes */ - int vbe_modes_cnt; - - u8 nocrtc; - u8 ypan; /* 0 - nothing, 1 - ypan, 2 - ywrap */ - u8 pmi_setpal; /* PMI for palette changes */ - u16 *pmi_base; /* protected mode interface location */ - void *pmi_start; - void *pmi_pal; - u8 *vbe_state_orig; /* - * original hardware state, before the - * driver was loaded - */ - u8 *vbe_state_saved; /* state saved by fb_save_state */ - int vbe_state_size; - atomic_t ref_count; - - int mode_idx; - struct vbe_crtc_ib crtc; -}; - -#endif /* __KERNEL__ */ -#endif /* _UVESAFB_H */ diff --git a/ANDROID_3.4.5/include/video/vga.h b/ANDROID_3.4.5/include/video/vga.h deleted file mode 100644 index 2b8691f7..00000000 --- a/ANDROID_3.4.5/include/video/vga.h +++ /dev/null @@ -1,481 +0,0 @@ -/* - * linux/include/video/vga.h -- standard VGA chipset interaction - * - * Copyright 1999 Jeff Garzik <jgarzik@pobox.com> - * - * Copyright history from vga16fb.c: - * Copyright 1999 Ben Pfaff and Petr Vandrovec - * Based on VGA info at http://www.osdever.net/FreeVGA/home.htm - * Based on VESA framebuffer (c) 1998 Gerd Knorr - * - * This file is subject to the terms and conditions of the GNU General - * Public License. See the file COPYING in the main directory of this - * archive for more details. - * - */ - -#ifndef __linux_video_vga_h__ -#define __linux_video_vga_h__ - -#include <linux/types.h> -#include <asm/io.h> -#ifndef CONFIG_AMIGA -#include <asm/vga.h> -#else -/* - * FIXME - * Ugh, we don't have PCI space, so map readb() and friends to use Zorro space - * for MMIO accesses. This should make cirrusfb work again on Amiga - */ -#undef inb_p -#undef inw_p -#undef outb_p -#undef outw -#undef readb -#undef writeb -#undef writew -#define inb_p(port) 0 -#define inw_p(port) 0 -#define outb_p(port, val) do { } while (0) -#define outw(port, val) do { } while (0) -#define readb z_readb -#define writeb z_writeb -#define writew z_writew -#endif -#include <asm/byteorder.h> - - -/* Some of the code below is taken from SVGAlib. The original, - unmodified copyright notice for that code is below. */ -/* VGAlib version 1.2 - (c) 1993 Tommy Frandsen */ -/* */ -/* This library is free software; you can redistribute it and/or */ -/* modify it without any restrictions. This library is distributed */ -/* in the hope that it will be useful, but without any warranty. */ - -/* Multi-chipset support Copyright 1993 Harm Hanemaayer */ -/* partially copyrighted (C) 1993 by Hartmut Schirmer */ - -/* VGA data register ports */ -#define VGA_CRT_DC 0x3D5 /* CRT Controller Data Register - color emulation */ -#define VGA_CRT_DM 0x3B5 /* CRT Controller Data Register - mono emulation */ -#define VGA_ATT_R 0x3C1 /* Attribute Controller Data Read Register */ -#define VGA_ATT_W 0x3C0 /* Attribute Controller Data Write Register */ -#define VGA_GFX_D 0x3CF /* Graphics Controller Data Register */ -#define VGA_SEQ_D 0x3C5 /* Sequencer Data Register */ -#define VGA_MIS_R 0x3CC /* Misc Output Read Register */ -#define VGA_MIS_W 0x3C2 /* Misc Output Write Register */ -#define VGA_FTC_R 0x3CA /* Feature Control Read Register */ -#define VGA_IS1_RC 0x3DA /* Input Status Register 1 - color emulation */ -#define VGA_IS1_RM 0x3BA /* Input Status Register 1 - mono emulation */ -#define VGA_PEL_D 0x3C9 /* PEL Data Register */ -#define VGA_PEL_MSK 0x3C6 /* PEL mask register */ - -/* EGA-specific registers */ -#define EGA_GFX_E0 0x3CC /* Graphics enable processor 0 */ -#define EGA_GFX_E1 0x3CA /* Graphics enable processor 1 */ - -/* VGA index register ports */ -#define VGA_CRT_IC 0x3D4 /* CRT Controller Index - color emulation */ -#define VGA_CRT_IM 0x3B4 /* CRT Controller Index - mono emulation */ -#define VGA_ATT_IW 0x3C0 /* Attribute Controller Index & Data Write Register */ -#define VGA_GFX_I 0x3CE /* Graphics Controller Index */ -#define VGA_SEQ_I 0x3C4 /* Sequencer Index */ -#define VGA_PEL_IW 0x3C8 /* PEL Write Index */ -#define VGA_PEL_IR 0x3C7 /* PEL Read Index */ - -/* standard VGA indexes max counts */ -#define VGA_CRT_C 0x19 /* Number of CRT Controller Registers */ -#define VGA_ATT_C 0x15 /* Number of Attribute Controller Registers */ -#define VGA_GFX_C 0x09 /* Number of Graphics Controller Registers */ -#define VGA_SEQ_C 0x05 /* Number of Sequencer Registers */ -#define VGA_MIS_C 0x01 /* Number of Misc Output Register */ - -/* VGA misc register bit masks */ -#define VGA_MIS_COLOR 0x01 -#define VGA_MIS_ENB_MEM_ACCESS 0x02 -#define VGA_MIS_DCLK_28322_720 0x04 -#define VGA_MIS_ENB_PLL_LOAD (0x04 | 0x08) -#define VGA_MIS_SEL_HIGH_PAGE 0x20 - -/* VGA CRT controller register indices */ -#define VGA_CRTC_H_TOTAL 0 -#define VGA_CRTC_H_DISP 1 -#define VGA_CRTC_H_BLANK_START 2 -#define VGA_CRTC_H_BLANK_END 3 -#define VGA_CRTC_H_SYNC_START 4 -#define VGA_CRTC_H_SYNC_END 5 -#define VGA_CRTC_V_TOTAL 6 -#define VGA_CRTC_OVERFLOW 7 -#define VGA_CRTC_PRESET_ROW 8 -#define VGA_CRTC_MAX_SCAN 9 -#define VGA_CRTC_CURSOR_START 0x0A -#define VGA_CRTC_CURSOR_END 0x0B -#define VGA_CRTC_START_HI 0x0C -#define VGA_CRTC_START_LO 0x0D -#define VGA_CRTC_CURSOR_HI 0x0E -#define VGA_CRTC_CURSOR_LO 0x0F -#define VGA_CRTC_V_SYNC_START 0x10 -#define VGA_CRTC_V_SYNC_END 0x11 -#define VGA_CRTC_V_DISP_END 0x12 -#define VGA_CRTC_OFFSET 0x13 -#define VGA_CRTC_UNDERLINE 0x14 -#define VGA_CRTC_V_BLANK_START 0x15 -#define VGA_CRTC_V_BLANK_END 0x16 -#define VGA_CRTC_MODE 0x17 -#define VGA_CRTC_LINE_COMPARE 0x18 -#define VGA_CRTC_REGS VGA_CRT_C - -/* VGA CRT controller bit masks */ -#define VGA_CR11_LOCK_CR0_CR7 0x80 /* lock writes to CR0 - CR7 */ -#define VGA_CR17_H_V_SIGNALS_ENABLED 0x80 - -/* VGA attribute controller register indices */ -#define VGA_ATC_PALETTE0 0x00 -#define VGA_ATC_PALETTE1 0x01 -#define VGA_ATC_PALETTE2 0x02 -#define VGA_ATC_PALETTE3 0x03 -#define VGA_ATC_PALETTE4 0x04 -#define VGA_ATC_PALETTE5 0x05 -#define VGA_ATC_PALETTE6 0x06 -#define VGA_ATC_PALETTE7 0x07 -#define VGA_ATC_PALETTE8 0x08 -#define VGA_ATC_PALETTE9 0x09 -#define VGA_ATC_PALETTEA 0x0A -#define VGA_ATC_PALETTEB 0x0B -#define VGA_ATC_PALETTEC 0x0C -#define VGA_ATC_PALETTED 0x0D -#define VGA_ATC_PALETTEE 0x0E -#define VGA_ATC_PALETTEF 0x0F -#define VGA_ATC_MODE 0x10 -#define VGA_ATC_OVERSCAN 0x11 -#define VGA_ATC_PLANE_ENABLE 0x12 -#define VGA_ATC_PEL 0x13 -#define VGA_ATC_COLOR_PAGE 0x14 - -#define VGA_AR_ENABLE_DISPLAY 0x20 - -/* VGA sequencer register indices */ -#define VGA_SEQ_RESET 0x00 -#define VGA_SEQ_CLOCK_MODE 0x01 -#define VGA_SEQ_PLANE_WRITE 0x02 -#define VGA_SEQ_CHARACTER_MAP 0x03 -#define VGA_SEQ_MEMORY_MODE 0x04 - -/* VGA sequencer register bit masks */ -#define VGA_SR01_CHAR_CLK_8DOTS 0x01 /* bit 0: character clocks 8 dots wide are generated */ -#define VGA_SR01_SCREEN_OFF 0x20 /* bit 5: Screen is off */ -#define VGA_SR02_ALL_PLANES 0x0F /* bits 3-0: enable access to all planes */ -#define VGA_SR04_EXT_MEM 0x02 /* bit 1: allows complete mem access to 256K */ -#define VGA_SR04_SEQ_MODE 0x04 /* bit 2: directs system to use a sequential addressing mode */ -#define VGA_SR04_CHN_4M 0x08 /* bit 3: selects modulo 4 addressing for CPU access to display memory */ - -/* VGA graphics controller register indices */ -#define VGA_GFX_SR_VALUE 0x00 -#define VGA_GFX_SR_ENABLE 0x01 -#define VGA_GFX_COMPARE_VALUE 0x02 -#define VGA_GFX_DATA_ROTATE 0x03 -#define VGA_GFX_PLANE_READ 0x04 -#define VGA_GFX_MODE 0x05 -#define VGA_GFX_MISC 0x06 -#define VGA_GFX_COMPARE_MASK 0x07 -#define VGA_GFX_BIT_MASK 0x08 - -/* VGA graphics controller bit masks */ -#define VGA_GR06_GRAPHICS_MODE 0x01 - -/* macro for composing an 8-bit VGA register index and value - * into a single 16-bit quantity */ -#define VGA_OUT16VAL(v, r) (((v) << 8) | (r)) - -/* decide whether we should enable the faster 16-bit VGA register writes */ -#ifdef __LITTLE_ENDIAN -#define VGA_OUTW_WRITE -#endif - -/* VGA State Save and Restore */ -#define VGA_SAVE_FONT0 1 /* save/restore plane 2 fonts */ -#define VGA_SAVE_FONT1 2 /* save/restore plane 3 fonts */ -#define VGA_SAVE_TEXT 4 /* save/restore plane 0/1 fonts */ -#define VGA_SAVE_FONTS 7 /* save/restore all fonts */ -#define VGA_SAVE_MODE 8 /* save/restore video mode */ -#define VGA_SAVE_CMAP 16 /* save/restore color map/DAC */ - -struct vgastate { - void __iomem *vgabase; /* mmio base, if supported */ - unsigned long membase; /* VGA window base, 0 for default - 0xA000 */ - __u32 memsize; /* VGA window size, 0 for default 64K */ - __u32 flags; /* what state[s] to save (see VGA_SAVE_*) */ - __u32 depth; /* current fb depth, not important */ - __u32 num_attr; /* number of att registers, 0 for default */ - __u32 num_crtc; /* number of crt registers, 0 for default */ - __u32 num_gfx; /* number of gfx registers, 0 for default */ - __u32 num_seq; /* number of seq registers, 0 for default */ - void *vidstate; -}; - -extern int save_vga(struct vgastate *state); -extern int restore_vga(struct vgastate *state); - -/* - * generic VGA port read/write - */ - -static inline unsigned char vga_io_r (unsigned short port) -{ - return inb_p(port); -} - -static inline void vga_io_w (unsigned short port, unsigned char val) -{ - outb_p(val, port); -} - -static inline void vga_io_w_fast (unsigned short port, unsigned char reg, - unsigned char val) -{ - outw(VGA_OUT16VAL (val, reg), port); -} - -static inline unsigned char vga_mm_r (void __iomem *regbase, unsigned short port) -{ - return readb (regbase + port); -} - -static inline void vga_mm_w (void __iomem *regbase, unsigned short port, unsigned char val) -{ - writeb (val, regbase + port); -} - -static inline void vga_mm_w_fast (void __iomem *regbase, unsigned short port, - unsigned char reg, unsigned char val) -{ - writew (VGA_OUT16VAL (val, reg), regbase + port); -} - -static inline unsigned char vga_r (void __iomem *regbase, unsigned short port) -{ - if (regbase) - return vga_mm_r (regbase, port); - else - return vga_io_r (port); -} - -static inline void vga_w (void __iomem *regbase, unsigned short port, unsigned char val) -{ - if (regbase) - vga_mm_w (regbase, port, val); - else - vga_io_w (port, val); -} - - -static inline void vga_w_fast (void __iomem *regbase, unsigned short port, - unsigned char reg, unsigned char val) -{ - if (regbase) - vga_mm_w_fast (regbase, port, reg, val); - else - vga_io_w_fast (port, reg, val); -} - - -/* - * VGA CRTC register read/write - */ - -static inline unsigned char vga_rcrt (void __iomem *regbase, unsigned char reg) -{ - vga_w (regbase, VGA_CRT_IC, reg); - return vga_r (regbase, VGA_CRT_DC); -} - -static inline void vga_wcrt (void __iomem *regbase, unsigned char reg, unsigned char val) -{ -#ifdef VGA_OUTW_WRITE - vga_w_fast (regbase, VGA_CRT_IC, reg, val); -#else - vga_w (regbase, VGA_CRT_IC, reg); - vga_w (regbase, VGA_CRT_DC, val); -#endif /* VGA_OUTW_WRITE */ -} - -static inline unsigned char vga_io_rcrt (unsigned char reg) -{ - vga_io_w (VGA_CRT_IC, reg); - return vga_io_r (VGA_CRT_DC); -} - -static inline void vga_io_wcrt (unsigned char reg, unsigned char val) -{ -#ifdef VGA_OUTW_WRITE - vga_io_w_fast (VGA_CRT_IC, reg, val); -#else - vga_io_w (VGA_CRT_IC, reg); - vga_io_w (VGA_CRT_DC, val); -#endif /* VGA_OUTW_WRITE */ -} - -static inline unsigned char vga_mm_rcrt (void __iomem *regbase, unsigned char reg) -{ - vga_mm_w (regbase, VGA_CRT_IC, reg); - return vga_mm_r (regbase, VGA_CRT_DC); -} - -static inline void vga_mm_wcrt (void __iomem *regbase, unsigned char reg, unsigned char val) -{ -#ifdef VGA_OUTW_WRITE - vga_mm_w_fast (regbase, VGA_CRT_IC, reg, val); -#else - vga_mm_w (regbase, VGA_CRT_IC, reg); - vga_mm_w (regbase, VGA_CRT_DC, val); -#endif /* VGA_OUTW_WRITE */ -} - - -/* - * VGA sequencer register read/write - */ - -static inline unsigned char vga_rseq (void __iomem *regbase, unsigned char reg) -{ - vga_w (regbase, VGA_SEQ_I, reg); - return vga_r (regbase, VGA_SEQ_D); -} - -static inline void vga_wseq (void __iomem *regbase, unsigned char reg, unsigned char val) -{ -#ifdef VGA_OUTW_WRITE - vga_w_fast (regbase, VGA_SEQ_I, reg, val); -#else - vga_w (regbase, VGA_SEQ_I, reg); - vga_w (regbase, VGA_SEQ_D, val); -#endif /* VGA_OUTW_WRITE */ -} - -static inline unsigned char vga_io_rseq (unsigned char reg) -{ - vga_io_w (VGA_SEQ_I, reg); - return vga_io_r (VGA_SEQ_D); -} - -static inline void vga_io_wseq (unsigned char reg, unsigned char val) -{ -#ifdef VGA_OUTW_WRITE - vga_io_w_fast (VGA_SEQ_I, reg, val); -#else - vga_io_w (VGA_SEQ_I, reg); - vga_io_w (VGA_SEQ_D, val); -#endif /* VGA_OUTW_WRITE */ -} - -static inline unsigned char vga_mm_rseq (void __iomem *regbase, unsigned char reg) -{ - vga_mm_w (regbase, VGA_SEQ_I, reg); - return vga_mm_r (regbase, VGA_SEQ_D); -} - -static inline void vga_mm_wseq (void __iomem *regbase, unsigned char reg, unsigned char val) -{ -#ifdef VGA_OUTW_WRITE - vga_mm_w_fast (regbase, VGA_SEQ_I, reg, val); -#else - vga_mm_w (regbase, VGA_SEQ_I, reg); - vga_mm_w (regbase, VGA_SEQ_D, val); -#endif /* VGA_OUTW_WRITE */ -} - -/* - * VGA graphics controller register read/write - */ - -static inline unsigned char vga_rgfx (void __iomem *regbase, unsigned char reg) -{ - vga_w (regbase, VGA_GFX_I, reg); - return vga_r (regbase, VGA_GFX_D); -} - -static inline void vga_wgfx (void __iomem *regbase, unsigned char reg, unsigned char val) -{ -#ifdef VGA_OUTW_WRITE - vga_w_fast (regbase, VGA_GFX_I, reg, val); -#else - vga_w (regbase, VGA_GFX_I, reg); - vga_w (regbase, VGA_GFX_D, val); -#endif /* VGA_OUTW_WRITE */ -} - -static inline unsigned char vga_io_rgfx (unsigned char reg) -{ - vga_io_w (VGA_GFX_I, reg); - return vga_io_r (VGA_GFX_D); -} - -static inline void vga_io_wgfx (unsigned char reg, unsigned char val) -{ -#ifdef VGA_OUTW_WRITE - vga_io_w_fast (VGA_GFX_I, reg, val); -#else - vga_io_w (VGA_GFX_I, reg); - vga_io_w (VGA_GFX_D, val); -#endif /* VGA_OUTW_WRITE */ -} - -static inline unsigned char vga_mm_rgfx (void __iomem *regbase, unsigned char reg) -{ - vga_mm_w (regbase, VGA_GFX_I, reg); - return vga_mm_r (regbase, VGA_GFX_D); -} - -static inline void vga_mm_wgfx (void __iomem *regbase, unsigned char reg, unsigned char val) -{ -#ifdef VGA_OUTW_WRITE - vga_mm_w_fast (regbase, VGA_GFX_I, reg, val); -#else - vga_mm_w (regbase, VGA_GFX_I, reg); - vga_mm_w (regbase, VGA_GFX_D, val); -#endif /* VGA_OUTW_WRITE */ -} - - -/* - * VGA attribute controller register read/write - */ - -static inline unsigned char vga_rattr (void __iomem *regbase, unsigned char reg) -{ - vga_w (regbase, VGA_ATT_IW, reg); - return vga_r (regbase, VGA_ATT_R); -} - -static inline void vga_wattr (void __iomem *regbase, unsigned char reg, unsigned char val) -{ - vga_w (regbase, VGA_ATT_IW, reg); - vga_w (regbase, VGA_ATT_W, val); -} - -static inline unsigned char vga_io_rattr (unsigned char reg) -{ - vga_io_w (VGA_ATT_IW, reg); - return vga_io_r (VGA_ATT_R); -} - -static inline void vga_io_wattr (unsigned char reg, unsigned char val) -{ - vga_io_w (VGA_ATT_IW, reg); - vga_io_w (VGA_ATT_W, val); -} - -static inline unsigned char vga_mm_rattr (void __iomem *regbase, unsigned char reg) -{ - vga_mm_w (regbase, VGA_ATT_IW, reg); - return vga_mm_r (regbase, VGA_ATT_R); -} - -static inline void vga_mm_wattr (void __iomem *regbase, unsigned char reg, unsigned char val) -{ - vga_mm_w (regbase, VGA_ATT_IW, reg); - vga_mm_w (regbase, VGA_ATT_W, val); -} - -#endif /* __linux_video_vga_h__ */ diff --git a/ANDROID_3.4.5/include/video/w100fb.h b/ANDROID_3.4.5/include/video/w100fb.h deleted file mode 100644 index 677d4032..00000000 --- a/ANDROID_3.4.5/include/video/w100fb.h +++ /dev/null @@ -1,150 +0,0 @@ -/* - * Support for the w100 frame buffer. - * - * Copyright (c) 2004-2005 Richard Purdie - * Copyright (c) 2005 Ian Molton - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#define W100_GPIO_PORT_A 0 -#define W100_GPIO_PORT_B 1 - -#define CLK_SRC_XTAL 0 -#define CLK_SRC_PLL 1 - -struct w100fb_par; - -unsigned long w100fb_gpio_read(int port); -void w100fb_gpio_write(int port, unsigned long value); -unsigned long w100fb_get_hsynclen(struct device *dev); - -/* LCD Specific Routines and Config */ -struct w100_tg_info { - void (*change)(struct w100fb_par*); - void (*suspend)(struct w100fb_par*); - void (*resume)(struct w100fb_par*); -}; - -/* General Platform Specific w100 Register Values */ -struct w100_gen_regs { - unsigned long lcd_format; - unsigned long lcdd_cntl1; - unsigned long lcdd_cntl2; - unsigned long genlcd_cntl1; - unsigned long genlcd_cntl2; - unsigned long genlcd_cntl3; -}; - -struct w100_gpio_regs { - unsigned long init_data1; - unsigned long init_data2; - unsigned long gpio_dir1; - unsigned long gpio_oe1; - unsigned long gpio_dir2; - unsigned long gpio_oe2; -}; - -/* Optional External Memory Configuration */ -struct w100_mem_info { - unsigned long ext_cntl; - unsigned long sdram_mode_reg; - unsigned long ext_timing_cntl; - unsigned long io_cntl; - unsigned int size; -}; - -struct w100_bm_mem_info { - unsigned long ext_mem_bw; - unsigned long offset; - unsigned long ext_timing_ctl; - unsigned long ext_cntl; - unsigned long mode_reg; - unsigned long io_cntl; - unsigned long config; -}; - -/* LCD Mode definition */ -struct w100_mode { - unsigned int xres; - unsigned int yres; - unsigned short left_margin; - unsigned short right_margin; - unsigned short upper_margin; - unsigned short lower_margin; - unsigned long crtc_ss; - unsigned long crtc_ls; - unsigned long crtc_gs; - unsigned long crtc_vpos_gs; - unsigned long crtc_rev; - unsigned long crtc_dclk; - unsigned long crtc_gclk; - unsigned long crtc_goe; - unsigned long crtc_ps1_active; - char pll_freq; - char fast_pll_freq; - int sysclk_src; - int sysclk_divider; - int pixclk_src; - int pixclk_divider; - int pixclk_divider_rotated; -}; - -struct w100_pll_info { - uint16_t freq; /* desired Fout for PLL (Mhz) */ - uint8_t M; /* input divider */ - uint8_t N_int; /* VCO multiplier */ - uint8_t N_fac; /* VCO multiplier fractional part */ - uint8_t tfgoal; - uint8_t lock_time; -}; - -/* Initial Video mode orientation flags */ -#define INIT_MODE_ROTATED 0x1 -#define INIT_MODE_FLIPPED 0x2 - -/* - * This structure describes the machine which we are running on. - * It is set by machine specific code and used in the probe routine - * of drivers/video/w100fb.c - */ -struct w100fb_mach_info { - /* General Platform Specific Registers */ - struct w100_gen_regs *regs; - /* Table of modes the LCD is capable of */ - struct w100_mode *modelist; - unsigned int num_modes; - /* Hooks for any platform specific tg/lcd code (optional) */ - struct w100_tg_info *tg; - /* External memory definition (if present) */ - struct w100_mem_info *mem; - /* Additional External memory definition (if present) */ - struct w100_bm_mem_info *bm_mem; - /* GPIO definitions (optional) */ - struct w100_gpio_regs *gpio; - /* Initial Mode flags */ - unsigned int init_mode; - /* Xtal Frequency */ - unsigned int xtal_freq; - /* Enable Xtal input doubler (1 == enable) */ - unsigned int xtal_dbl; -}; - -/* General frame buffer data structure */ -struct w100fb_par { - unsigned int chip_id; - unsigned int xres; - unsigned int yres; - unsigned int extmem_active; - unsigned int flip; - unsigned int blanked; - unsigned int fastpll_mode; - unsigned long hsync_len; - struct w100_mode *mode; - struct w100_pll_info *pll_table; - struct w100fb_mach_info *mach; - uint32_t *saved_intmem; - uint32_t *saved_extmem; -}; |