Moved, renamed, and deleted files

The original directory structure was scattered and unorganized.
Changes are basically to make it look like kernel structure.

8 files changed, 0 insertions, 2472 deletions

diff --git a/ANDROID_3.4.5/include/linux/ssb/ssb.h b/ANDROID_3.4.5/include/linux/ssb/ssb.h
deleted file mode 100644
index d2768318..00000000
--- a/ANDROID_3.4.5/include/linux/ssb/ssb.h
+++ /dev/null
@@ -1,625 +0,0 @@
-#ifndef LINUX_SSB_H_
-#define LINUX_SSB_H_
-
-#include <linux/device.h>
-#include <linux/list.h>
-#include <linux/types.h>
-#include <linux/spinlock.h>
-#include <linux/pci.h>
-#include <linux/mod_devicetable.h>
-#include <linux/dma-mapping.h>
-
-#include <linux/ssb/ssb_regs.h>
-
-
-struct pcmcia_device;
-struct ssb_bus;
-struct ssb_driver;
-
-struct ssb_sprom_core_pwr_info {
-	u8 itssi_2g, itssi_5g;
-	u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh;
-	u16 pa_2g[4], pa_5gl[4], pa_5g[4], pa_5gh[4];
-};
-
-struct ssb_sprom {
-	u8 revision;
-	u8 il0mac[6];		/* MAC address for 802.11b/g */
-	u8 et0mac[6];		/* MAC address for Ethernet */
-	u8 et1mac[6];		/* MAC address for 802.11a */
-	u8 et0phyaddr;		/* MII address for enet0 */
-	u8 et1phyaddr;		/* MII address for enet1 */
-	u8 et0mdcport;		/* MDIO for enet0 */
-	u8 et1mdcport;		/* MDIO for enet1 */
-	u16 board_rev;		/* Board revision number from SPROM. */
-	u16 board_num;		/* Board number from SPROM. */
-	u16 board_type;		/* Board type from SPROM. */
-	u8 country_code;	/* Country Code */
-	char alpha2[2];		/* Country Code as two chars like EU or US */
-	u8 leddc_on_time;	/* LED Powersave Duty Cycle On Count */
-	u8 leddc_off_time;	/* LED Powersave Duty Cycle Off Count */
-	u8 ant_available_a;	/* 2GHz antenna available bits (up to 4) */
-	u8 ant_available_bg;	/* 5GHz antenna available bits (up to 4) */
-	u16 pa0b0;
-	u16 pa0b1;
-	u16 pa0b2;
-	u16 pa1b0;
-	u16 pa1b1;
-	u16 pa1b2;
-	u16 pa1lob0;
-	u16 pa1lob1;
-	u16 pa1lob2;
-	u16 pa1hib0;
-	u16 pa1hib1;
-	u16 pa1hib2;
-	u8 gpio0;		/* GPIO pin 0 */
-	u8 gpio1;		/* GPIO pin 1 */
-	u8 gpio2;		/* GPIO pin 2 */
-	u8 gpio3;		/* GPIO pin 3 */
-	u8 maxpwr_bg;		/* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
-	u8 maxpwr_al;		/* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
-	u8 maxpwr_a;		/* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
-	u8 maxpwr_ah;		/* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
-	u8 itssi_a;		/* Idle TSSI Target for A-PHY */
-	u8 itssi_bg;		/* Idle TSSI Target for B/G-PHY */
-	u8 tri2g;		/* 2.4GHz TX isolation */
-	u8 tri5gl;		/* 5.2GHz TX isolation */
-	u8 tri5g;		/* 5.3GHz TX isolation */
-	u8 tri5gh;		/* 5.8GHz TX isolation */
-	u8 txpid2g[4];		/* 2GHz TX power index */
-	u8 txpid5gl[4];		/* 4.9 - 5.1GHz TX power index */
-	u8 txpid5g[4];		/* 5.1 - 5.5GHz TX power index */
-	u8 txpid5gh[4];		/* 5.5 - ...GHz TX power index */
-	s8 rxpo2g;		/* 2GHz RX power offset */
-	s8 rxpo5g;		/* 5GHz RX power offset */
-	u8 rssisav2g;		/* 2GHz RSSI params */
-	u8 rssismc2g;
-	u8 rssismf2g;
-	u8 bxa2g;		/* 2GHz BX arch */
-	u8 rssisav5g;		/* 5GHz RSSI params */
-	u8 rssismc5g;
-	u8 rssismf5g;
-	u8 bxa5g;		/* 5GHz BX arch */
-	u16 cck2gpo;		/* CCK power offset */
-	u32 ofdm2gpo;		/* 2.4GHz OFDM power offset */
-	u32 ofdm5glpo;		/* 5.2GHz OFDM power offset */
-	u32 ofdm5gpo;		/* 5.3GHz OFDM power offset */
-	u32 ofdm5ghpo;		/* 5.8GHz OFDM power offset */
-	u16 boardflags_lo;	/* Board flags (bits 0-15) */
-	u16 boardflags_hi;	/* Board flags (bits 16-31) */
-	u16 boardflags2_lo;	/* Board flags (bits 32-47) */
-	u16 boardflags2_hi;	/* Board flags (bits 48-63) */
-	/* TODO store board flags in a single u64 */
-
-	struct ssb_sprom_core_pwr_info core_pwr_info[4];
-
-	/* Antenna gain values for up to 4 antennas
-	 * on each band. Values in dBm/4 (Q5.2). Negative gain means the
-	 * loss in the connectors is bigger than the gain. */
-	struct {
-		s8 a0, a1, a2, a3;
-	} antenna_gain;
-
-	struct {
-		struct {
-			u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
-		} ghz2;
-		struct {
-			u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
-		} ghz5;
-	} fem;
-
-	u16 mcs2gpo[8];
-	u16 mcs5gpo[8];
-	u16 mcs5glpo[8];
-	u16 mcs5ghpo[8];
-	u8 opo;
-
-	u8 rxgainerr2ga[3];
-	u8 rxgainerr5gla[3];
-	u8 rxgainerr5gma[3];
-	u8 rxgainerr5gha[3];
-	u8 rxgainerr5gua[3];
-
-	u8 noiselvl2ga[3];
-	u8 noiselvl5gla[3];
-	u8 noiselvl5gma[3];
-	u8 noiselvl5gha[3];
-	u8 noiselvl5gua[3];
-
-	u8 regrev;
-	u8 txchain;
-	u8 rxchain;
-	u8 antswitch;
-	u16 cddpo;
-	u16 stbcpo;
-	u16 bw40po;
-	u16 bwduppo;
-
-	u8 tempthresh;
-	u8 tempoffset;
-	u16 rawtempsense;
-	u8 measpower;
-	u8 tempsense_slope;
-	u8 tempcorrx;
-	u8 tempsense_option;
-	u8 freqoffset_corr;
-	u8 iqcal_swp_dis;
-	u8 hw_iqcal_en;
-	u8 elna2g;
-	u8 elna5g;
-	u8 phycal_tempdelta;
-	u8 temps_period;
-	u8 temps_hysteresis;
-	u8 measpower1;
-	u8 measpower2;
-	u8 pcieingress_war;
-
-	/* power per rate from sromrev 9 */
-	u16 cckbw202gpo;
-	u16 cckbw20ul2gpo;
-	u32 legofdmbw202gpo;
-	u32 legofdmbw20ul2gpo;
-	u32 legofdmbw205glpo;
-	u32 legofdmbw20ul5glpo;
-	u32 legofdmbw205gmpo;
-	u32 legofdmbw20ul5gmpo;
-	u32 legofdmbw205ghpo;
-	u32 legofdmbw20ul5ghpo;
-	u32 mcsbw202gpo;
-	u32 mcsbw20ul2gpo;
-	u32 mcsbw402gpo;
-	u32 mcsbw205glpo;
-	u32 mcsbw20ul5glpo;
-	u32 mcsbw405glpo;
-	u32 mcsbw205gmpo;
-	u32 mcsbw20ul5gmpo;
-	u32 mcsbw405gmpo;
-	u32 mcsbw205ghpo;
-	u32 mcsbw20ul5ghpo;
-	u32 mcsbw405ghpo;
-	u16 mcs32po;
-	u16 legofdm40duppo;
-	u8 sar2g;
-	u8 sar5g;
-};
-
-/* Information about the PCB the circuitry is soldered on. */
-struct ssb_boardinfo {
-	u16 vendor;
-	u16 type;
-	u8  rev;
-};
-
-
-struct ssb_device;
-/* Lowlevel read/write operations on the device MMIO.
- * Internal, don't use that outside of ssb. */
-struct ssb_bus_ops {
-	u8 (*read8)(struct ssb_device *dev, u16 offset);
-	u16 (*read16)(struct ssb_device *dev, u16 offset);
-	u32 (*read32)(struct ssb_device *dev, u16 offset);
-	void (*write8)(struct ssb_device *dev, u16 offset, u8 value);
-	void (*write16)(struct ssb_device *dev, u16 offset, u16 value);
-	void (*write32)(struct ssb_device *dev, u16 offset, u32 value);
-#ifdef CONFIG_SSB_BLOCKIO
-	void (*block_read)(struct ssb_device *dev, void *buffer,
-			   size_t count, u16 offset, u8 reg_width);
-	void (*block_write)(struct ssb_device *dev, const void *buffer,
-			    size_t count, u16 offset, u8 reg_width);
-#endif
-};
-
-
-/* Core-ID values. */
-#define SSB_DEV_CHIPCOMMON	0x800
-#define SSB_DEV_ILINE20		0x801
-#define SSB_DEV_SDRAM		0x803
-#define SSB_DEV_PCI		0x804
-#define SSB_DEV_MIPS		0x805
-#define SSB_DEV_ETHERNET	0x806
-#define SSB_DEV_V90		0x807
-#define SSB_DEV_USB11_HOSTDEV	0x808
-#define SSB_DEV_ADSL		0x809
-#define SSB_DEV_ILINE100	0x80A
-#define SSB_DEV_IPSEC		0x80B
-#define SSB_DEV_PCMCIA		0x80D
-#define SSB_DEV_INTERNAL_MEM	0x80E
-#define SSB_DEV_MEMC_SDRAM	0x80F
-#define SSB_DEV_EXTIF		0x811
-#define SSB_DEV_80211		0x812
-#define SSB_DEV_MIPS_3302	0x816
-#define SSB_DEV_USB11_HOST	0x817
-#define SSB_DEV_USB11_DEV	0x818
-#define SSB_DEV_USB20_HOST	0x819
-#define SSB_DEV_USB20_DEV	0x81A
-#define SSB_DEV_SDIO_HOST	0x81B
-#define SSB_DEV_ROBOSWITCH	0x81C
-#define SSB_DEV_PARA_ATA	0x81D
-#define SSB_DEV_SATA_XORDMA	0x81E
-#define SSB_DEV_ETHERNET_GBIT	0x81F
-#define SSB_DEV_PCIE		0x820
-#define SSB_DEV_MIMO_PHY	0x821
-#define SSB_DEV_SRAM_CTRLR	0x822
-#define SSB_DEV_MINI_MACPHY	0x823
-#define SSB_DEV_ARM_1176	0x824
-#define SSB_DEV_ARM_7TDMI	0x825
-
-/* Vendor-ID values */
-#define SSB_VENDOR_BROADCOM	0x4243
-
-/* Some kernel subsystems poke with dev->drvdata, so we must use the
- * following ugly workaround to get from struct device to struct ssb_device */
-struct __ssb_dev_wrapper {
-	struct device dev;
-	struct ssb_device *sdev;
-};
-
-struct ssb_device {
-	/* Having a copy of the ops pointer in each dev struct
-	 * is an optimization. */
-	const struct ssb_bus_ops *ops;
-
-	struct device *dev, *dma_dev;
-
-	struct ssb_bus *bus;
-	struct ssb_device_id id;
-
-	u8 core_index;
-	unsigned int irq;
-
-	/* Internal-only stuff follows. */
-	void *drvdata;		/* Per-device data */
-	void *devtypedata;	/* Per-devicetype (eg 802.11) data */
-};
-
-/* Go from struct device to struct ssb_device. */
-static inline
-struct ssb_device * dev_to_ssb_dev(struct device *dev)
-{
-	struct __ssb_dev_wrapper *wrap;
-	wrap = container_of(dev, struct __ssb_dev_wrapper, dev);
-	return wrap->sdev;
-}
-
-/* Device specific user data */
-static inline
-void ssb_set_drvdata(struct ssb_device *dev, void *data)
-{
-	dev->drvdata = data;
-}
-static inline
-void * ssb_get_drvdata(struct ssb_device *dev)
-{
-	return dev->drvdata;
-}
-
-/* Devicetype specific user data. This is per device-type (not per device) */
-void ssb_set_devtypedata(struct ssb_device *dev, void *data);
-static inline
-void * ssb_get_devtypedata(struct ssb_device *dev)
-{
-	return dev->devtypedata;
-}
-
-
-struct ssb_driver {
-	const char *name;
-	const struct ssb_device_id *id_table;
-
-	int (*probe)(struct ssb_device *dev, const struct ssb_device_id *id);
-	void (*remove)(struct ssb_device *dev);
-	int (*suspend)(struct ssb_device *dev, pm_message_t state);
-	int (*resume)(struct ssb_device *dev);
-	void (*shutdown)(struct ssb_device *dev);
-
-	struct device_driver drv;
-};
-#define drv_to_ssb_drv(_drv) container_of(_drv, struct ssb_driver, drv)
-
-extern int __ssb_driver_register(struct ssb_driver *drv, struct module *owner);
-#define ssb_driver_register(drv) \
-	__ssb_driver_register(drv, THIS_MODULE)
-
-extern void ssb_driver_unregister(struct ssb_driver *drv);
-
-
-
-
-enum ssb_bustype {
-	SSB_BUSTYPE_SSB,	/* This SSB bus is the system bus */
-	SSB_BUSTYPE_PCI,	/* SSB is connected to PCI bus */
-	SSB_BUSTYPE_PCMCIA,	/* SSB is connected to PCMCIA bus */
-	SSB_BUSTYPE_SDIO,	/* SSB is connected to SDIO bus */
-};
-
-/* board_vendor */
-#define SSB_BOARDVENDOR_BCM	0x14E4	/* Broadcom */
-#define SSB_BOARDVENDOR_DELL	0x1028	/* Dell */
-#define SSB_BOARDVENDOR_HP	0x0E11	/* HP */
-/* board_type */
-#define SSB_BOARD_BCM94306MP	0x0418
-#define SSB_BOARD_BCM4309G	0x0421
-#define SSB_BOARD_BCM4306CB	0x0417
-#define SSB_BOARD_BCM4309MP	0x040C
-#define SSB_BOARD_MP4318	0x044A
-#define SSB_BOARD_BU4306	0x0416
-#define SSB_BOARD_BU4309	0x040A
-/* chip_package */
-#define SSB_CHIPPACK_BCM4712S	1	/* Small 200pin 4712 */
-#define SSB_CHIPPACK_BCM4712M	2	/* Medium 225pin 4712 */
-#define SSB_CHIPPACK_BCM4712L	0	/* Large 340pin 4712 */
-
-#include <linux/ssb/ssb_driver_chipcommon.h>
-#include <linux/ssb/ssb_driver_mips.h>
-#include <linux/ssb/ssb_driver_extif.h>
-#include <linux/ssb/ssb_driver_pci.h>
-
-struct ssb_bus {
-	/* The MMIO area. */
-	void __iomem *mmio;
-
-	const struct ssb_bus_ops *ops;
-
-	/* The core currently mapped into the MMIO window.
-	 * Not valid on all host-buses. So don't use outside of SSB. */
-	struct ssb_device *mapped_device;
-	union {
-		/* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */
-		u8 mapped_pcmcia_seg;
-		/* Current SSB base address window for SDIO. */
-		u32 sdio_sbaddr;
-	};
-	/* Lock for core and segment switching.
-	 * On PCMCIA-host busses this is used to protect the whole MMIO access. */
-	spinlock_t bar_lock;
-
-	/* The host-bus this backplane is running on. */
-	enum ssb_bustype bustype;
-	/* Pointers to the host-bus. Check bustype before using any of these pointers. */
-	union {
-		/* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */
-		struct pci_dev *host_pci;
-		/* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
-		struct pcmcia_device *host_pcmcia;
-		/* Pointer to the SDIO device (only if bustype == SSB_BUSTYPE_SDIO). */
-		struct sdio_func *host_sdio;
-	};
-
-	/* See enum ssb_quirks */
-	unsigned int quirks;
-
-#ifdef CONFIG_SSB_SPROM
-	/* Mutex to protect the SPROM writing. */
-	struct mutex sprom_mutex;
-#endif
-
-	/* ID information about the Chip. */
-	u16 chip_id;
-	u8 chip_rev;
-	u16 sprom_offset;
-	u16 sprom_size;		/* number of words in sprom */
-	u8 chip_package;
-
-	/* List of devices (cores) on the backplane. */
-	struct ssb_device devices[SSB_MAX_NR_CORES];
-	u8 nr_devices;
-
-	/* Software ID number for this bus. */
-	unsigned int busnumber;
-
-	/* The ChipCommon device (if available). */
-	struct ssb_chipcommon chipco;
-	/* The PCI-core device (if available). */
-	struct ssb_pcicore pcicore;
-	/* The MIPS-core device (if available). */
-	struct ssb_mipscore mipscore;
-	/* The EXTif-core device (if available). */
-	struct ssb_extif extif;
-
-	/* The following structure elements are not available in early
-	 * SSB initialization. Though, they are available for regular
-	 * registered drivers at any stage. So be careful when
-	 * using them in the ssb core code. */
-
-	/* ID information about the PCB. */
-	struct ssb_boardinfo boardinfo;
-	/* Contents of the SPROM. */
-	struct ssb_sprom sprom;
-	/* If the board has a cardbus slot, this is set to true. */
-	bool has_cardbus_slot;
-
-#ifdef CONFIG_SSB_EMBEDDED
-	/* Lock for GPIO register access. */
-	spinlock_t gpio_lock;
-#endif /* EMBEDDED */
-
-	/* Internal-only stuff follows. Do not touch. */
-	struct list_head list;
-#ifdef CONFIG_SSB_DEBUG
-	/* Is the bus already powered up? */
-	bool powered_up;
-	int power_warn_count;
-#endif /* DEBUG */
-};
-
-enum ssb_quirks {
-	/* SDIO connected card requires performing a read after writing a 32-bit value */
-	SSB_QUIRK_SDIO_READ_AFTER_WRITE32	= (1 << 0),
-};
-
-/* The initialization-invariants. */
-struct ssb_init_invariants {
-	/* Versioning information about the PCB. */
-	struct ssb_boardinfo boardinfo;
-	/* The SPROM information. That's either stored in an
-	 * EEPROM or NVRAM on the board. */
-	struct ssb_sprom sprom;
-	/* If the board has a cardbus slot, this is set to true. */
-	bool has_cardbus_slot;
-};
-/* Type of function to fetch the invariants. */
-typedef int (*ssb_invariants_func_t)(struct ssb_bus *bus,
-				     struct ssb_init_invariants *iv);
-
-/* Register a SSB system bus. get_invariants() is called after the
- * basic system devices are initialized.
- * The invariants are usually fetched from some NVRAM.
- * Put the invariants into the struct pointed to by iv. */
-extern int ssb_bus_ssbbus_register(struct ssb_bus *bus,
-				   unsigned long baseaddr,
-				   ssb_invariants_func_t get_invariants);
-#ifdef CONFIG_SSB_PCIHOST
-extern int ssb_bus_pcibus_register(struct ssb_bus *bus,
-				   struct pci_dev *host_pci);
-#endif /* CONFIG_SSB_PCIHOST */
-#ifdef CONFIG_SSB_PCMCIAHOST
-extern int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
-				      struct pcmcia_device *pcmcia_dev,
-				      unsigned long baseaddr);
-#endif /* CONFIG_SSB_PCMCIAHOST */
-#ifdef CONFIG_SSB_SDIOHOST
-extern int ssb_bus_sdiobus_register(struct ssb_bus *bus,
-				    struct sdio_func *sdio_func,
-				    unsigned int quirks);
-#endif /* CONFIG_SSB_SDIOHOST */
-
-
-extern void ssb_bus_unregister(struct ssb_bus *bus);
-
-/* Does the device have an SPROM? */
-extern bool ssb_is_sprom_available(struct ssb_bus *bus);
-
-/* Set a fallback SPROM.
- * See kdoc at the function definition for complete documentation. */
-extern int ssb_arch_register_fallback_sprom(
-		int (*sprom_callback)(struct ssb_bus *bus,
-		struct ssb_sprom *out));
-
-/* Suspend a SSB bus.
- * Call this from the parent bus suspend routine. */
-extern int ssb_bus_suspend(struct ssb_bus *bus);
-/* Resume a SSB bus.
- * Call this from the parent bus resume routine. */
-extern int ssb_bus_resume(struct ssb_bus *bus);
-
-extern u32 ssb_clockspeed(struct ssb_bus *bus);
-
-/* Is the device enabled in hardware? */
-int ssb_device_is_enabled(struct ssb_device *dev);
-/* Enable a device and pass device-specific SSB_TMSLOW flags.
- * If no device-specific flags are available, use 0. */
-void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags);
-/* Disable a device in hardware and pass SSB_TMSLOW flags (if any). */
-void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags);
-
-
-/* Device MMIO register read/write functions. */
-static inline u8 ssb_read8(struct ssb_device *dev, u16 offset)
-{
-	return dev->ops->read8(dev, offset);
-}
-static inline u16 ssb_read16(struct ssb_device *dev, u16 offset)
-{
-	return dev->ops->read16(dev, offset);
-}
-static inline u32 ssb_read32(struct ssb_device *dev, u16 offset)
-{
-	return dev->ops->read32(dev, offset);
-}
-static inline void ssb_write8(struct ssb_device *dev, u16 offset, u8 value)
-{
-	dev->ops->write8(dev, offset, value);
-}
-static inline void ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
-{
-	dev->ops->write16(dev, offset, value);
-}
-static inline void ssb_write32(struct ssb_device *dev, u16 offset, u32 value)
-{
-	dev->ops->write32(dev, offset, value);
-}
-#ifdef CONFIG_SSB_BLOCKIO
-static inline void ssb_block_read(struct ssb_device *dev, void *buffer,
-				  size_t count, u16 offset, u8 reg_width)
-{
-	dev->ops->block_read(dev, buffer, count, offset, reg_width);
-}
-
-static inline void ssb_block_write(struct ssb_device *dev, const void *buffer,
-				   size_t count, u16 offset, u8 reg_width)
-{
-	dev->ops->block_write(dev, buffer, count, offset, reg_width);
-}
-#endif /* CONFIG_SSB_BLOCKIO */
-
-
-/* The SSB DMA API. Use this API for any DMA operation on the device.
- * This API basically is a wrapper that calls the correct DMA API for
- * the host device type the SSB device is attached to. */
-
-/* Translation (routing) bits that need to be ORed to DMA
- * addresses before they are given to a device. */
-extern u32 ssb_dma_translation(struct ssb_device *dev);
-#define SSB_DMA_TRANSLATION_MASK	0xC0000000
-#define SSB_DMA_TRANSLATION_SHIFT	30
-
-static inline void __cold __ssb_dma_not_implemented(struct ssb_device *dev)
-{
-#ifdef CONFIG_SSB_DEBUG
-	printk(KERN_ERR "SSB: BUG! Calling DMA API for "
-	       "unsupported bustype %d\n", dev->bus->bustype);
-#endif /* DEBUG */
-}
-
-#ifdef CONFIG_SSB_PCIHOST
-/* PCI-host wrapper driver */
-extern int ssb_pcihost_register(struct pci_driver *driver);
-static inline void ssb_pcihost_unregister(struct pci_driver *driver)
-{
-	pci_unregister_driver(driver);
-}
-
-static inline
-void ssb_pcihost_set_power_state(struct ssb_device *sdev, pci_power_t state)
-{
-	if (sdev->bus->bustype == SSB_BUSTYPE_PCI)
-		pci_set_power_state(sdev->bus->host_pci, state);
-}
-#else
-static inline void ssb_pcihost_unregister(struct pci_driver *driver)
-{
-}
-
-static inline
-void ssb_pcihost_set_power_state(struct ssb_device *sdev, pci_power_t state)
-{
-}
-#endif /* CONFIG_SSB_PCIHOST */
-
-
-/* If a driver is shutdown or suspended, call this to signal
- * that the bus may be completely powered down. SSB will decide,
- * if it's really time to power down the bus, based on if there
- * are other devices that want to run. */
-extern int ssb_bus_may_powerdown(struct ssb_bus *bus);
-/* Before initializing and enabling a device, call this to power-up the bus.
- * If you want to allow use of dynamic-power-control, pass the flag.
- * Otherwise static always-on powercontrol will be used. */
-extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl);
-
-extern void ssb_commit_settings(struct ssb_bus *bus);
-
-/* Various helper functions */
-extern u32 ssb_admatch_base(u32 adm);
-extern u32 ssb_admatch_size(u32 adm);
-
-/* PCI device mapping and fixup routines.
- * Called from the architecture pcibios init code.
- * These are only available on SSB_EMBEDDED configurations. */
-#ifdef CONFIG_SSB_EMBEDDED
-int ssb_pcibios_plat_dev_init(struct pci_dev *dev);
-int ssb_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
-#endif /* CONFIG_SSB_EMBEDDED */
-
-#endif /* LINUX_SSB_H_ */
diff --git a/ANDROID_3.4.5/include/linux/ssb/ssb_driver_chipcommon.h b/ANDROID_3.4.5/include/linux/ssb/ssb_driver_chipcommon.h
deleted file mode 100644
index 1a6b0045..00000000
--- a/ANDROID_3.4.5/include/linux/ssb/ssb_driver_chipcommon.h
+++ /dev/null
@@ -1,665 +0,0 @@
-#ifndef LINUX_SSB_CHIPCO_H_
-#define LINUX_SSB_CHIPCO_H_
-
-/* SonicsSiliconBackplane CHIPCOMMON core hardware definitions
- *
- * The chipcommon core provides chip identification, SB control,
- * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
- * gpio interface, extbus, and support for serial and parallel flashes.
- *
- * Copyright 2005, Broadcom Corporation
- * Copyright 2006, Michael Buesch <m@bues.ch>
- *
- * Licensed under the GPL version 2. See COPYING for details.
- */
-
-/** ChipCommon core registers. **/
-
-#define SSB_CHIPCO_CHIPID		0x0000
-#define  SSB_CHIPCO_IDMASK		0x0000FFFF
-#define  SSB_CHIPCO_REVMASK		0x000F0000
-#define  SSB_CHIPCO_REVSHIFT		16
-#define  SSB_CHIPCO_PACKMASK		0x00F00000
-#define  SSB_CHIPCO_PACKSHIFT		20
-#define  SSB_CHIPCO_NRCORESMASK		0x0F000000
-#define  SSB_CHIPCO_NRCORESSHIFT	24
-#define SSB_CHIPCO_CAP	 		0x0004		/* Capabilities */
-#define  SSB_CHIPCO_CAP_NRUART		0x00000003	/* # of UARTs */
-#define  SSB_CHIPCO_CAP_MIPSEB		0x00000004	/* MIPS in BigEndian Mode */
-#define  SSB_CHIPCO_CAP_UARTCLK		0x00000018	/* UART clock select */
-#define   SSB_CHIPCO_CAP_UARTCLK_INT	0x00000008	/* UARTs are driven by internal divided clock */
-#define  SSB_CHIPCO_CAP_UARTGPIO	0x00000020	/* UARTs on GPIO 15-12 */
-#define  SSB_CHIPCO_CAP_EXTBUS		0x000000C0	/* External buses present */
-#define  SSB_CHIPCO_CAP_FLASHT		0x00000700	/* Flash Type */
-#define   SSB_CHIPCO_FLASHT_NONE	0x00000000	/* No flash */
-#define   SSB_CHIPCO_FLASHT_STSER	0x00000100	/* ST serial flash */
-#define   SSB_CHIPCO_FLASHT_ATSER	0x00000200	/* Atmel serial flash */
-#define	  SSB_CHIPCO_FLASHT_PARA	0x00000700	/* Parallel flash */
-#define  SSB_CHIPCO_CAP_PLLT		0x00038000	/* PLL Type */
-#define   SSB_PLLTYPE_NONE		0x00000000
-#define   SSB_PLLTYPE_1			0x00010000	/* 48Mhz base, 3 dividers */
-#define   SSB_PLLTYPE_2			0x00020000	/* 48Mhz, 4 dividers */
-#define   SSB_PLLTYPE_3			0x00030000	/* 25Mhz, 2 dividers */
-#define   SSB_PLLTYPE_4			0x00008000	/* 48Mhz, 4 dividers */
-#define   SSB_PLLTYPE_5			0x00018000	/* 25Mhz, 4 dividers */
-#define   SSB_PLLTYPE_6			0x00028000	/* 100/200 or 120/240 only */
-#define   SSB_PLLTYPE_7			0x00038000	/* 25Mhz, 4 dividers */
-#define  SSB_CHIPCO_CAP_PCTL		0x00040000	/* Power Control */
-#define  SSB_CHIPCO_CAP_OTPS		0x00380000	/* OTP size */
-#define  SSB_CHIPCO_CAP_OTPS_SHIFT	19
-#define  SSB_CHIPCO_CAP_OTPS_BASE	5
-#define  SSB_CHIPCO_CAP_JTAGM		0x00400000	/* JTAG master present */
-#define  SSB_CHIPCO_CAP_BROM		0x00800000	/* Internal boot ROM active */
-#define  SSB_CHIPCO_CAP_64BIT		0x08000000	/* 64-bit Backplane */
-#define  SSB_CHIPCO_CAP_PMU		0x10000000	/* PMU available (rev >= 20) */
-#define  SSB_CHIPCO_CAP_ECI		0x20000000	/* ECI available (rev >= 20) */
-#define  SSB_CHIPCO_CAP_SPROM		0x40000000	/* SPROM present */
-#define SSB_CHIPCO_CORECTL		0x0008
-#define  SSB_CHIPCO_CORECTL_UARTCLK0	0x00000001	/* Drive UART with internal clock */
-#define	 SSB_CHIPCO_CORECTL_SE		0x00000002	/* sync clk out enable (corerev >= 3) */
-#define  SSB_CHIPCO_CORECTL_UARTCLKEN	0x00000008	/* UART clock enable (rev >= 21) */
-#define SSB_CHIPCO_BIST			0x000C
-#define SSB_CHIPCO_OTPS			0x0010		/* OTP status */
-#define	 SSB_CHIPCO_OTPS_PROGFAIL	0x80000000
-#define	 SSB_CHIPCO_OTPS_PROTECT	0x00000007
-#define	 SSB_CHIPCO_OTPS_HW_PROTECT	0x00000001
-#define	 SSB_CHIPCO_OTPS_SW_PROTECT	0x00000002
-#define	 SSB_CHIPCO_OTPS_CID_PROTECT	0x00000004
-#define SSB_CHIPCO_OTPC			0x0014		/* OTP control */
-#define	 SSB_CHIPCO_OTPC_RECWAIT	0xFF000000
-#define	 SSB_CHIPCO_OTPC_PROGWAIT	0x00FFFF00
-#define	 SSB_CHIPCO_OTPC_PRW_SHIFT	8
-#define	 SSB_CHIPCO_OTPC_MAXFAIL	0x00000038
-#define	 SSB_CHIPCO_OTPC_VSEL		0x00000006
-#define	 SSB_CHIPCO_OTPC_SELVL		0x00000001
-#define SSB_CHIPCO_OTPP			0x0018		/* OTP prog */
-#define	 SSB_CHIPCO_OTPP_COL		0x000000FF
-#define	 SSB_CHIPCO_OTPP_ROW		0x0000FF00
-#define	 SSB_CHIPCO_OTPP_ROW_SHIFT	8
-#define	 SSB_CHIPCO_OTPP_READERR	0x10000000
-#define	 SSB_CHIPCO_OTPP_VALUE		0x20000000
-#define	 SSB_CHIPCO_OTPP_READ		0x40000000
-#define	 SSB_CHIPCO_OTPP_START		0x80000000
-#define	 SSB_CHIPCO_OTPP_BUSY		0x80000000
-#define SSB_CHIPCO_IRQSTAT		0x0020
-#define SSB_CHIPCO_IRQMASK		0x0024
-#define	 SSB_CHIPCO_IRQ_GPIO		0x00000001	/* gpio intr */
-#define	 SSB_CHIPCO_IRQ_EXT		0x00000002	/* ro: ext intr pin (corerev >= 3) */
-#define	 SSB_CHIPCO_IRQ_WDRESET		0x80000000	/* watchdog reset occurred */
-#define SSB_CHIPCO_CHIPCTL		0x0028		/* Rev >= 11 only */
-#define SSB_CHIPCO_CHIPSTAT		0x002C		/* Rev >= 11 only */
-#define SSB_CHIPCO_JCMD			0x0030		/* Rev >= 10 only */
-#define  SSB_CHIPCO_JCMD_START		0x80000000
-#define  SSB_CHIPCO_JCMD_BUSY		0x80000000
-#define  SSB_CHIPCO_JCMD_PAUSE		0x40000000
-#define  SSB_CHIPCO_JCMD0_ACC_MASK	0x0000F000
-#define  SSB_CHIPCO_JCMD0_ACC_IRDR	0x00000000
-#define  SSB_CHIPCO_JCMD0_ACC_DR	0x00001000
-#define  SSB_CHIPCO_JCMD0_ACC_IR	0x00002000
-#define  SSB_CHIPCO_JCMD0_ACC_RESET	0x00003000
-#define  SSB_CHIPCO_JCMD0_ACC_IRPDR	0x00004000
-#define  SSB_CHIPCO_JCMD0_ACC_PDR	0x00005000
-#define  SSB_CHIPCO_JCMD0_IRW_MASK	0x00000F00
-#define  SSB_CHIPCO_JCMD_ACC_MASK	0x000F0000	/* Changes for corerev 11 */
-#define  SSB_CHIPCO_JCMD_ACC_IRDR	0x00000000
-#define  SSB_CHIPCO_JCMD_ACC_DR		0x00010000
-#define  SSB_CHIPCO_JCMD_ACC_IR		0x00020000
-#define  SSB_CHIPCO_JCMD_ACC_RESET	0x00030000
-#define  SSB_CHIPCO_JCMD_ACC_IRPDR	0x00040000
-#define  SSB_CHIPCO_JCMD_ACC_PDR	0x00050000
-#define  SSB_CHIPCO_JCMD_IRW_MASK	0x00001F00
-#define  SSB_CHIPCO_JCMD_IRW_SHIFT	8
-#define  SSB_CHIPCO_JCMD_DRW_MASK	0x0000003F
-#define SSB_CHIPCO_JIR			0x0034		/* Rev >= 10 only */
-#define SSB_CHIPCO_JDR			0x0038		/* Rev >= 10 only */
-#define SSB_CHIPCO_JCTL			0x003C		/* Rev >= 10 only */
-#define  SSB_CHIPCO_JCTL_FORCE_CLK	4		/* Force clock */
-#define  SSB_CHIPCO_JCTL_EXT_EN		2		/* Enable external targets */
-#define  SSB_CHIPCO_JCTL_EN		1		/* Enable Jtag master */
-#define SSB_CHIPCO_FLASHCTL		0x0040
-#define  SSB_CHIPCO_FLASHCTL_START	0x80000000
-#define  SSB_CHIPCO_FLASHCTL_BUSY	SSB_CHIPCO_FLASHCTL_START
-#define SSB_CHIPCO_FLASHADDR		0x0044
-#define SSB_CHIPCO_FLASHDATA		0x0048
-#define SSB_CHIPCO_BCAST_ADDR		0x0050
-#define SSB_CHIPCO_BCAST_DATA		0x0054
-#define SSB_CHIPCO_GPIOPULLUP		0x0058		/* Rev >= 20 only */
-#define SSB_CHIPCO_GPIOPULLDOWN		0x005C		/* Rev >= 20 only */
-#define SSB_CHIPCO_GPIOIN		0x0060
-#define SSB_CHIPCO_GPIOOUT		0x0064
-#define SSB_CHIPCO_GPIOOUTEN		0x0068
-#define SSB_CHIPCO_GPIOCTL		0x006C
-#define SSB_CHIPCO_GPIOPOL		0x0070
-#define SSB_CHIPCO_GPIOIRQ		0x0074
-#define SSB_CHIPCO_WATCHDOG		0x0080
-#define SSB_CHIPCO_GPIOTIMER		0x0088		/* LED powersave (corerev >= 16) */
-#define  SSB_CHIPCO_GPIOTIMER_OFFTIME	0x0000FFFF
-#define  SSB_CHIPCO_GPIOTIMER_OFFTIME_SHIFT	0
-#define  SSB_CHIPCO_GPIOTIMER_ONTIME	0xFFFF0000
-#define  SSB_CHIPCO_GPIOTIMER_ONTIME_SHIFT	16
-#define SSB_CHIPCO_GPIOTOUTM		0x008C		/* LED powersave (corerev >= 16) */
-#define SSB_CHIPCO_CLOCK_N		0x0090
-#define SSB_CHIPCO_CLOCK_SB		0x0094
-#define SSB_CHIPCO_CLOCK_PCI		0x0098
-#define SSB_CHIPCO_CLOCK_M2		0x009C
-#define SSB_CHIPCO_CLOCK_MIPS		0x00A0
-#define SSB_CHIPCO_CLKDIV		0x00A4		/* Rev >= 3 only */
-#define	 SSB_CHIPCO_CLKDIV_SFLASH	0x0F000000
-#define	 SSB_CHIPCO_CLKDIV_SFLASH_SHIFT	24
-#define	 SSB_CHIPCO_CLKDIV_OTP		0x000F0000
-#define	 SSB_CHIPCO_CLKDIV_OTP_SHIFT	16
-#define	 SSB_CHIPCO_CLKDIV_JTAG		0x00000F00
-#define	 SSB_CHIPCO_CLKDIV_JTAG_SHIFT	8
-#define	 SSB_CHIPCO_CLKDIV_UART		0x000000FF
-#define SSB_CHIPCO_PLLONDELAY		0x00B0		/* Rev >= 4 only */
-#define SSB_CHIPCO_FREFSELDELAY		0x00B4		/* Rev >= 4 only */
-#define SSB_CHIPCO_SLOWCLKCTL		0x00B8		/* 6 <= Rev <= 9 only */
-#define  SSB_CHIPCO_SLOWCLKCTL_SRC	0x00000007	/* slow clock source mask */
-#define	  SSB_CHIPCO_SLOWCLKCTL_SRC_LPO		0x00000000	/* source of slow clock is LPO */
-#define   SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL	0x00000001	/* source of slow clock is crystal */
-#define	  SSB_CHIPCO_SLOECLKCTL_SRC_PCI		0x00000002	/* source of slow clock is PCI */
-#define  SSB_CHIPCO_SLOWCLKCTL_LPOFREQ	0x00000200	/* LPOFreqSel, 1: 160Khz, 0: 32KHz */
-#define  SSB_CHIPCO_SLOWCLKCTL_LPOPD	0x00000400	/* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
-#define  SSB_CHIPCO_SLOWCLKCTL_FSLOW	0x00000800	/* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
-#define  SSB_CHIPCO_SLOWCLKCTL_IPLL	0x00001000	/* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */
-#define  SSB_CHIPCO_SLOWCLKCTL_ENXTAL	0x00002000	/* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */
-#define  SSB_CHIPCO_SLOWCLKCTL_XTALPU	0x00004000	/* XtalPU (RO), 1/0: crystal running/disabled */
-#define  SSB_CHIPCO_SLOWCLKCTL_CLKDIV	0xFFFF0000	/* ClockDivider (SlowClk = 1/(4+divisor)) */
-#define  SSB_CHIPCO_SLOWCLKCTL_CLKDIV_SHIFT	16
-#define SSB_CHIPCO_SYSCLKCTL		0x00C0		/* Rev >= 3 only */
-#define	 SSB_CHIPCO_SYSCLKCTL_IDLPEN	0x00000001	/* ILPen: Enable Idle Low Power */
-#define	 SSB_CHIPCO_SYSCLKCTL_ALPEN	0x00000002	/* ALPen: Enable Active Low Power */
-#define	 SSB_CHIPCO_SYSCLKCTL_PLLEN	0x00000004	/* ForcePLLOn */
-#define	 SSB_CHIPCO_SYSCLKCTL_FORCEALP	0x00000008	/* Force ALP (or HT if ALPen is not set */
-#define	 SSB_CHIPCO_SYSCLKCTL_FORCEHT	0x00000010	/* Force HT */
-#define  SSB_CHIPCO_SYSCLKCTL_CLKDIV	0xFFFF0000	/* ClkDiv  (ILP = 1/(4+divisor)) */
-#define  SSB_CHIPCO_SYSCLKCTL_CLKDIV_SHIFT	16
-#define SSB_CHIPCO_CLKSTSTR		0x00C4		/* Rev >= 3 only */
-#define SSB_CHIPCO_PCMCIA_CFG		0x0100
-#define SSB_CHIPCO_PCMCIA_MEMWAIT	0x0104
-#define SSB_CHIPCO_PCMCIA_ATTRWAIT	0x0108
-#define SSB_CHIPCO_PCMCIA_IOWAIT	0x010C
-#define SSB_CHIPCO_IDE_CFG		0x0110
-#define SSB_CHIPCO_IDE_MEMWAIT		0x0114
-#define SSB_CHIPCO_IDE_ATTRWAIT		0x0118
-#define SSB_CHIPCO_IDE_IOWAIT		0x011C
-#define SSB_CHIPCO_PROG_CFG		0x0120
-#define SSB_CHIPCO_PROG_WAITCNT		0x0124
-#define SSB_CHIPCO_FLASH_CFG		0x0128
-#define SSB_CHIPCO_FLASH_WAITCNT	0x012C
-#define SSB_CHIPCO_CLKCTLST		0x01E0 /* Clock control and status (rev >= 20) */
-#define  SSB_CHIPCO_CLKCTLST_FORCEALP	0x00000001 /* Force ALP request */
-#define  SSB_CHIPCO_CLKCTLST_FORCEHT	0x00000002 /* Force HT request */
-#define  SSB_CHIPCO_CLKCTLST_FORCEILP	0x00000004 /* Force ILP request */
-#define  SSB_CHIPCO_CLKCTLST_HAVEALPREQ	0x00000008 /* ALP available request */
-#define  SSB_CHIPCO_CLKCTLST_HAVEHTREQ	0x00000010 /* HT available request */
-#define  SSB_CHIPCO_CLKCTLST_HWCROFF	0x00000020 /* Force HW clock request off */
-#define  SSB_CHIPCO_CLKCTLST_HAVEALP	0x00010000 /* ALP available */
-#define  SSB_CHIPCO_CLKCTLST_HAVEHT	0x00020000 /* HT available */
-#define  SSB_CHIPCO_CLKCTLST_4328A0_HAVEHT	0x00010000 /* 4328a0 has reversed bits */
-#define  SSB_CHIPCO_CLKCTLST_4328A0_HAVEALP	0x00020000 /* 4328a0 has reversed bits */
-#define SSB_CHIPCO_HW_WORKAROUND	0x01E4 /* Hardware workaround (rev >= 20) */
-#define SSB_CHIPCO_UART0_DATA		0x0300
-#define SSB_CHIPCO_UART0_IMR		0x0304
-#define SSB_CHIPCO_UART0_FCR		0x0308
-#define SSB_CHIPCO_UART0_LCR		0x030C
-#define SSB_CHIPCO_UART0_MCR		0x0310
-#define SSB_CHIPCO_UART0_LSR		0x0314
-#define SSB_CHIPCO_UART0_MSR		0x0318
-#define SSB_CHIPCO_UART0_SCRATCH	0x031C
-#define SSB_CHIPCO_UART1_DATA		0x0400
-#define SSB_CHIPCO_UART1_IMR		0x0404
-#define SSB_CHIPCO_UART1_FCR		0x0408
-#define SSB_CHIPCO_UART1_LCR		0x040C
-#define SSB_CHIPCO_UART1_MCR		0x0410
-#define SSB_CHIPCO_UART1_LSR		0x0414
-#define SSB_CHIPCO_UART1_MSR		0x0418
-#define SSB_CHIPCO_UART1_SCRATCH	0x041C
-/* PMU registers (rev >= 20) */
-#define SSB_CHIPCO_PMU_CTL			0x0600 /* PMU control */
-#define  SSB_CHIPCO_PMU_CTL_ILP_DIV		0xFFFF0000 /* ILP div mask */
-#define  SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT	16
-#define  SSB_CHIPCO_PMU_CTL_NOILPONW		0x00000200 /* No ILP on wait */
-#define  SSB_CHIPCO_PMU_CTL_HTREQEN		0x00000100 /* HT req enable */
-#define  SSB_CHIPCO_PMU_CTL_ALPREQEN		0x00000080 /* ALP req enable */
-#define  SSB_CHIPCO_PMU_CTL_XTALFREQ		0x0000007C /* Crystal freq */
-#define  SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT	2
-#define  SSB_CHIPCO_PMU_CTL_ILPDIVEN		0x00000002 /* ILP div enable */
-#define  SSB_CHIPCO_PMU_CTL_LPOSEL		0x00000001 /* LPO sel */
-#define SSB_CHIPCO_PMU_CAP			0x0604 /* PMU capabilities */
-#define  SSB_CHIPCO_PMU_CAP_REVISION		0x000000FF /* Revision mask */
-#define SSB_CHIPCO_PMU_STAT			0x0608 /* PMU status */
-#define  SSB_CHIPCO_PMU_STAT_INTPEND		0x00000040 /* Interrupt pending */
-#define  SSB_CHIPCO_PMU_STAT_SBCLKST		0x00000030 /* Backplane clock status? */
-#define  SSB_CHIPCO_PMU_STAT_HAVEALP		0x00000008 /* ALP available */
-#define  SSB_CHIPCO_PMU_STAT_HAVEHT		0x00000004 /* HT available */
-#define  SSB_CHIPCO_PMU_STAT_RESINIT		0x00000003 /* Res init */
-#define SSB_CHIPCO_PMU_RES_STAT			0x060C /* PMU res status */
-#define SSB_CHIPCO_PMU_RES_PEND			0x0610 /* PMU res pending */
-#define SSB_CHIPCO_PMU_TIMER			0x0614 /* PMU timer */
-#define SSB_CHIPCO_PMU_MINRES_MSK		0x0618 /* PMU min res mask */
-#define SSB_CHIPCO_PMU_MAXRES_MSK		0x061C /* PMU max res mask */
-#define SSB_CHIPCO_PMU_RES_TABSEL		0x0620 /* PMU res table sel */
-#define SSB_CHIPCO_PMU_RES_DEPMSK		0x0624 /* PMU res dep mask */
-#define SSB_CHIPCO_PMU_RES_UPDNTM		0x0628 /* PMU res updown timer */
-#define SSB_CHIPCO_PMU_RES_TIMER		0x062C /* PMU res timer */
-#define SSB_CHIPCO_PMU_CLKSTRETCH		0x0630 /* PMU clockstretch */
-#define SSB_CHIPCO_PMU_WATCHDOG			0x0634 /* PMU watchdog */
-#define SSB_CHIPCO_PMU_RES_REQTS		0x0640 /* PMU res req timer sel */
-#define SSB_CHIPCO_PMU_RES_REQT			0x0644 /* PMU res req timer */
-#define SSB_CHIPCO_PMU_RES_REQM			0x0648 /* PMU res req mask */
-#define SSB_CHIPCO_CHIPCTL_ADDR			0x0650
-#define SSB_CHIPCO_CHIPCTL_DATA			0x0654
-#define SSB_CHIPCO_REGCTL_ADDR			0x0658
-#define SSB_CHIPCO_REGCTL_DATA			0x065C
-#define SSB_CHIPCO_PLLCTL_ADDR			0x0660
-#define SSB_CHIPCO_PLLCTL_DATA			0x0664
-
-
-
-/** PMU PLL registers */
-
-/* PMU rev 0 PLL registers */
-#define SSB_PMU0_PLLCTL0			0
-#define  SSB_PMU0_PLLCTL0_PDIV_MSK		0x00000001
-#define  SSB_PMU0_PLLCTL0_PDIV_FREQ		25000 /* kHz */
-#define SSB_PMU0_PLLCTL1			1
-#define  SSB_PMU0_PLLCTL1_WILD_IMSK		0xF0000000 /* Wild int mask (low nibble) */
-#define  SSB_PMU0_PLLCTL1_WILD_IMSK_SHIFT	28
-#define  SSB_PMU0_PLLCTL1_WILD_FMSK		0x0FFFFF00 /* Wild frac mask */
-#define  SSB_PMU0_PLLCTL1_WILD_FMSK_SHIFT	8
-#define  SSB_PMU0_PLLCTL1_STOPMOD		0x00000040 /* Stop mod */
-#define SSB_PMU0_PLLCTL2			2
-#define  SSB_PMU0_PLLCTL2_WILD_IMSKHI		0x0000000F /* Wild int mask (high nibble) */
-#define  SSB_PMU0_PLLCTL2_WILD_IMSKHI_SHIFT	0
-
-/* PMU rev 1 PLL registers */
-#define SSB_PMU1_PLLCTL0			0
-#define  SSB_PMU1_PLLCTL0_P1DIV			0x00F00000 /* P1 div */
-#define  SSB_PMU1_PLLCTL0_P1DIV_SHIFT		20
-#define  SSB_PMU1_PLLCTL0_P2DIV			0x0F000000 /* P2 div */
-#define  SSB_PMU1_PLLCTL0_P2DIV_SHIFT		24
-#define SSB_PMU1_PLLCTL1			1
-#define  SSB_PMU1_PLLCTL1_M1DIV			0x000000FF /* M1 div */
-#define  SSB_PMU1_PLLCTL1_M1DIV_SHIFT		0
-#define  SSB_PMU1_PLLCTL1_M2DIV			0x0000FF00 /* M2 div */
-#define  SSB_PMU1_PLLCTL1_M2DIV_SHIFT		8
-#define  SSB_PMU1_PLLCTL1_M3DIV			0x00FF0000 /* M3 div */
-#define  SSB_PMU1_PLLCTL1_M3DIV_SHIFT		16
-#define  SSB_PMU1_PLLCTL1_M4DIV			0xFF000000 /* M4 div */
-#define  SSB_PMU1_PLLCTL1_M4DIV_SHIFT		24
-#define SSB_PMU1_PLLCTL2			2
-#define  SSB_PMU1_PLLCTL2_M5DIV			0x000000FF /* M5 div */
-#define  SSB_PMU1_PLLCTL2_M5DIV_SHIFT		0
-#define  SSB_PMU1_PLLCTL2_M6DIV			0x0000FF00 /* M6 div */
-#define  SSB_PMU1_PLLCTL2_M6DIV_SHIFT		8
-#define  SSB_PMU1_PLLCTL2_NDIVMODE		0x000E0000 /* NDIV mode */
-#define  SSB_PMU1_PLLCTL2_NDIVMODE_SHIFT	17
-#define  SSB_PMU1_PLLCTL2_NDIVINT		0x1FF00000 /* NDIV int */
-#define  SSB_PMU1_PLLCTL2_NDIVINT_SHIFT		20
-#define SSB_PMU1_PLLCTL3			3
-#define  SSB_PMU1_PLLCTL3_NDIVFRAC		0x00FFFFFF /* NDIV frac */
-#define  SSB_PMU1_PLLCTL3_NDIVFRAC_SHIFT	0
-#define SSB_PMU1_PLLCTL4			4
-#define SSB_PMU1_PLLCTL5			5
-#define  SSB_PMU1_PLLCTL5_CLKDRV		0xFFFFFF00 /* clk drv */
-#define  SSB_PMU1_PLLCTL5_CLKDRV_SHIFT		8
-
-/* BCM4312 PLL resource numbers. */
-#define SSB_PMURES_4312_SWITCHER_BURST		0
-#define SSB_PMURES_4312_SWITCHER_PWM    	1
-#define SSB_PMURES_4312_PA_REF_LDO		2
-#define SSB_PMURES_4312_CORE_LDO_BURST		3
-#define SSB_PMURES_4312_CORE_LDO_PWM		4
-#define SSB_PMURES_4312_RADIO_LDO		5
-#define SSB_PMURES_4312_ILP_REQUEST		6
-#define SSB_PMURES_4312_BG_FILTBYP		7
-#define SSB_PMURES_4312_TX_FILTBYP		8
-#define SSB_PMURES_4312_RX_FILTBYP		9
-#define SSB_PMURES_4312_XTAL_PU			10
-#define SSB_PMURES_4312_ALP_AVAIL		11
-#define SSB_PMURES_4312_BB_PLL_FILTBYP		12
-#define SSB_PMURES_4312_RF_PLL_FILTBYP		13
-#define SSB_PMURES_4312_HT_AVAIL		14
-
-/* BCM4325 PLL resource numbers. */
-#define SSB_PMURES_4325_BUCK_BOOST_BURST	0
-#define SSB_PMURES_4325_CBUCK_BURST		1
-#define SSB_PMURES_4325_CBUCK_PWM		2
-#define SSB_PMURES_4325_CLDO_CBUCK_BURST	3
-#define SSB_PMURES_4325_CLDO_CBUCK_PWM		4
-#define SSB_PMURES_4325_BUCK_BOOST_PWM		5
-#define SSB_PMURES_4325_ILP_REQUEST		6
-#define SSB_PMURES_4325_ABUCK_BURST		7
-#define SSB_PMURES_4325_ABUCK_PWM		8
-#define SSB_PMURES_4325_LNLDO1_PU		9
-#define SSB_PMURES_4325_LNLDO2_PU		10
-#define SSB_PMURES_4325_LNLDO3_PU		11
-#define SSB_PMURES_4325_LNLDO4_PU		12
-#define SSB_PMURES_4325_XTAL_PU			13
-#define SSB_PMURES_4325_ALP_AVAIL		14
-#define SSB_PMURES_4325_RX_PWRSW_PU		15
-#define SSB_PMURES_4325_TX_PWRSW_PU		16
-#define SSB_PMURES_4325_RFPLL_PWRSW_PU		17
-#define SSB_PMURES_4325_LOGEN_PWRSW_PU		18
-#define SSB_PMURES_4325_AFE_PWRSW_PU		19
-#define SSB_PMURES_4325_BBPLL_PWRSW_PU		20
-#define SSB_PMURES_4325_HT_AVAIL		21
-
-/* BCM4328 PLL resource numbers. */
-#define SSB_PMURES_4328_EXT_SWITCHER_PWM	0
-#define SSB_PMURES_4328_BB_SWITCHER_PWM		1
-#define SSB_PMURES_4328_BB_SWITCHER_BURST	2
-#define SSB_PMURES_4328_BB_EXT_SWITCHER_BURST	3
-#define SSB_PMURES_4328_ILP_REQUEST		4
-#define SSB_PMURES_4328_RADIO_SWITCHER_PWM	5
-#define SSB_PMURES_4328_RADIO_SWITCHER_BURST	6
-#define SSB_PMURES_4328_ROM_SWITCH		7
-#define SSB_PMURES_4328_PA_REF_LDO		8
-#define SSB_PMURES_4328_RADIO_LDO		9
-#define SSB_PMURES_4328_AFE_LDO			10
-#define SSB_PMURES_4328_PLL_LDO			11
-#define SSB_PMURES_4328_BG_FILTBYP		12
-#define SSB_PMURES_4328_TX_FILTBYP		13
-#define SSB_PMURES_4328_RX_FILTBYP		14
-#define SSB_PMURES_4328_XTAL_PU			15
-#define SSB_PMURES_4328_XTAL_EN			16
-#define SSB_PMURES_4328_BB_PLL_FILTBYP		17
-#define SSB_PMURES_4328_RF_PLL_FILTBYP		18
-#define SSB_PMURES_4328_BB_PLL_PU		19
-
-/* BCM5354 PLL resource numbers. */
-#define SSB_PMURES_5354_EXT_SWITCHER_PWM	0
-#define SSB_PMURES_5354_BB_SWITCHER_PWM		1
-#define SSB_PMURES_5354_BB_SWITCHER_BURST	2
-#define SSB_PMURES_5354_BB_EXT_SWITCHER_BURST	3
-#define SSB_PMURES_5354_ILP_REQUEST		4
-#define SSB_PMURES_5354_RADIO_SWITCHER_PWM	5
-#define SSB_PMURES_5354_RADIO_SWITCHER_BURST	6
-#define SSB_PMURES_5354_ROM_SWITCH		7
-#define SSB_PMURES_5354_PA_REF_LDO		8
-#define SSB_PMURES_5354_RADIO_LDO		9
-#define SSB_PMURES_5354_AFE_LDO			10
-#define SSB_PMURES_5354_PLL_LDO			11
-#define SSB_PMURES_5354_BG_FILTBYP		12
-#define SSB_PMURES_5354_TX_FILTBYP		13
-#define SSB_PMURES_5354_RX_FILTBYP		14
-#define SSB_PMURES_5354_XTAL_PU			15
-#define SSB_PMURES_5354_XTAL_EN			16
-#define SSB_PMURES_5354_BB_PLL_FILTBYP		17
-#define SSB_PMURES_5354_RF_PLL_FILTBYP		18
-#define SSB_PMURES_5354_BB_PLL_PU		19
-
-
-
-/** Chip specific Chip-Status register contents. */
-#define SSB_CHIPCO_CHST_4322_SPROM_EXISTS	0x00000040 /* SPROM present */
-#define SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL	0x00000003
-#define SSB_CHIPCO_CHST_4325_DEFCIS_SEL		0 /* OTP is powered up, use def. CIS, no SPROM */
-#define SSB_CHIPCO_CHST_4325_SPROM_SEL		1 /* OTP is powered up, SPROM is present */
-#define SSB_CHIPCO_CHST_4325_OTP_SEL		2 /* OTP is powered up, no SPROM */
-#define SSB_CHIPCO_CHST_4325_OTP_PWRDN		3 /* OTP is powered down, SPROM is present */
-#define SSB_CHIPCO_CHST_4325_SDIO_USB_MODE	0x00000004
-#define SSB_CHIPCO_CHST_4325_SDIO_USB_MODE_SHIFT  2
-#define SSB_CHIPCO_CHST_4325_RCAL_VALID		0x00000008
-#define SSB_CHIPCO_CHST_4325_RCAL_VALID_SHIFT	3
-#define SSB_CHIPCO_CHST_4325_RCAL_VALUE		0x000001F0
-#define SSB_CHIPCO_CHST_4325_RCAL_VALUE_SHIFT	4
-#define SSB_CHIPCO_CHST_4325_PMUTOP_2B 		0x00000200 /* 1 for 2b, 0 for to 2a */
-
-/** Macros to determine SPROM presence based on Chip-Status register. */
-#define SSB_CHIPCO_CHST_4312_SPROM_PRESENT(status) \
-	((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
-		SSB_CHIPCO_CHST_4325_OTP_SEL)
-#define SSB_CHIPCO_CHST_4322_SPROM_PRESENT(status) \
-	(status & SSB_CHIPCO_CHST_4322_SPROM_EXISTS)
-#define SSB_CHIPCO_CHST_4325_SPROM_PRESENT(status) \
-	(((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
-		SSB_CHIPCO_CHST_4325_DEFCIS_SEL) && \
-	 ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
-		SSB_CHIPCO_CHST_4325_OTP_SEL))
-
-
-
-/** Clockcontrol masks and values **/
-
-/* SSB_CHIPCO_CLOCK_N */
-#define	SSB_CHIPCO_CLK_N1		0x0000003F	/* n1 control */
-#define	SSB_CHIPCO_CLK_N2		0x00003F00	/* n2 control */
-#define	SSB_CHIPCO_CLK_N2_SHIFT		8
-#define	SSB_CHIPCO_CLK_PLLC		0x000F0000	/* pll control */
-#define	SSB_CHIPCO_CLK_PLLC_SHIFT	16
-
-/* SSB_CHIPCO_CLOCK_SB/PCI/UART */
-#define	SSB_CHIPCO_CLK_M1		0x0000003F	/* m1 control */
-#define	SSB_CHIPCO_CLK_M2		0x00003F00	/* m2 control */
-#define	SSB_CHIPCO_CLK_M2_SHIFT		8
-#define	SSB_CHIPCO_CLK_M3		0x003F0000	/* m3 control */
-#define	SSB_CHIPCO_CLK_M3_SHIFT		16
-#define	SSB_CHIPCO_CLK_MC		0x1F000000	/* mux control */
-#define	SSB_CHIPCO_CLK_MC_SHIFT		24
-
-/* N3M Clock control magic field values */
-#define	SSB_CHIPCO_CLK_F6_2		0x02		/* A factor of 2 in */
-#define	SSB_CHIPCO_CLK_F6_3		0x03		/* 6-bit fields like */
-#define	SSB_CHIPCO_CLK_F6_4		0x05		/* N1, M1 or M3 */
-#define	SSB_CHIPCO_CLK_F6_5		0x09
-#define	SSB_CHIPCO_CLK_F6_6		0x11
-#define	SSB_CHIPCO_CLK_F6_7		0x21
-
-#define	SSB_CHIPCO_CLK_F5_BIAS		5		/* 5-bit fields get this added */
-
-#define	SSB_CHIPCO_CLK_MC_BYPASS	0x08
-#define	SSB_CHIPCO_CLK_MC_M1		0x04
-#define	SSB_CHIPCO_CLK_MC_M1M2		0x02
-#define	SSB_CHIPCO_CLK_MC_M1M2M3	0x01
-#define	SSB_CHIPCO_CLK_MC_M1M3		0x11
-
-/* Type 2 Clock control magic field values */
-#define	SSB_CHIPCO_CLK_T2_BIAS		2		/* n1, n2, m1 & m3 bias */
-#define	SSB_CHIPCO_CLK_T2M2_BIAS	3		/* m2 bias */
-
-#define	SSB_CHIPCO_CLK_T2MC_M1BYP	1
-#define	SSB_CHIPCO_CLK_T2MC_M2BYP	2
-#define	SSB_CHIPCO_CLK_T2MC_M3BYP	4
-
-/* Type 6 Clock control magic field values */
-#define	SSB_CHIPCO_CLK_T6_MMASK		1		/* bits of interest in m */
-#define	SSB_CHIPCO_CLK_T6_M0		120000000	/* sb clock for m = 0 */
-#define	SSB_CHIPCO_CLK_T6_M1		100000000	/* sb clock for m = 1 */
-#define	SSB_CHIPCO_CLK_SB2MIPS_T6(sb)	(2 * (sb))
-
-/* Common clock base */
-#define	SSB_CHIPCO_CLK_BASE1		24000000	/* Half the clock freq */
-#define SSB_CHIPCO_CLK_BASE2		12500000	/* Alternate crystal on some PLL's */
-
-/* Clock control values for 200Mhz in 5350 */
-#define	SSB_CHIPCO_CLK_5350_N		0x0311
-#define	SSB_CHIPCO_CLK_5350_M		0x04020009
-
-
-/** Bits in the config registers **/
-
-#define	SSB_CHIPCO_CFG_EN		0x0001		/* Enable */
-#define	SSB_CHIPCO_CFG_EXTM		0x000E		/* Extif Mode */
-#define	 SSB_CHIPCO_CFG_EXTM_ASYNC	0x0002		/* Async/Parallel flash */
-#define	 SSB_CHIPCO_CFG_EXTM_SYNC	0x0004		/* Synchronous */
-#define	 SSB_CHIPCO_CFG_EXTM_PCMCIA	0x0008		/* PCMCIA */
-#define	 SSB_CHIPCO_CFG_EXTM_IDE	0x000A		/* IDE */
-#define	SSB_CHIPCO_CFG_DS16		0x0010		/* Data size, 0=8bit, 1=16bit */
-#define	SSB_CHIPCO_CFG_CLKDIV		0x0060		/* Sync: Clock divisor */
-#define	SSB_CHIPCO_CFG_CLKEN		0x0080		/* Sync: Clock enable */
-#define	SSB_CHIPCO_CFG_BSTRO		0x0100		/* Sync: Size/Bytestrobe */
-
-
-/** Flash-specific control/status values */
-
-/* flashcontrol opcodes for ST flashes */
-#define SSB_CHIPCO_FLASHCTL_ST_WREN	0x0006		/* Write Enable */
-#define SSB_CHIPCO_FLASHCTL_ST_WRDIS	0x0004		/* Write Disable */
-#define SSB_CHIPCO_FLASHCTL_ST_RDSR	0x0105		/* Read Status Register */
-#define SSB_CHIPCO_FLASHCTL_ST_WRSR	0x0101		/* Write Status Register */
-#define SSB_CHIPCO_FLASHCTL_ST_READ	0x0303		/* Read Data Bytes */
-#define SSB_CHIPCO_FLASHCTL_ST_PP	0x0302		/* Page Program */
-#define SSB_CHIPCO_FLASHCTL_ST_SE	0x02D8		/* Sector Erase */
-#define SSB_CHIPCO_FLASHCTL_ST_BE	0x00C7		/* Bulk Erase */
-#define SSB_CHIPCO_FLASHCTL_ST_DP	0x00B9		/* Deep Power-down */
-#define SSB_CHIPCO_FLASHCTL_ST_RSIG	0x03AB		/* Read Electronic Signature */
-
-/* Status register bits for ST flashes */
-#define SSB_CHIPCO_FLASHSTA_ST_WIP	0x01		/* Write In Progress */
-#define SSB_CHIPCO_FLASHSTA_ST_WEL	0x02		/* Write Enable Latch */
-#define SSB_CHIPCO_FLASHSTA_ST_BP	0x1C		/* Block Protect */
-#define SSB_CHIPCO_FLASHSTA_ST_BP_SHIFT	2
-#define SSB_CHIPCO_FLASHSTA_ST_SRWD	0x80		/* Status Register Write Disable */
-
-/* flashcontrol opcodes for Atmel flashes */
-#define SSB_CHIPCO_FLASHCTL_AT_READ		0x07E8
-#define SSB_CHIPCO_FLASHCTL_AT_PAGE_READ	0x07D2
-#define SSB_CHIPCO_FLASHCTL_AT_BUF1_READ	/* FIXME */
-#define SSB_CHIPCO_FLASHCTL_AT_BUF2_READ	/* FIXME */
-#define SSB_CHIPCO_FLASHCTL_AT_STATUS		0x01D7
-#define SSB_CHIPCO_FLASHCTL_AT_BUF1_WRITE	0x0384
-#define SSB_CHIPCO_FLASHCTL_AT_BUF2_WRITE	0x0387
-#define SSB_CHIPCO_FLASHCTL_AT_BUF1_ERASE_PRGM	0x0283	/* Erase program */
-#define SSB_CHIPCO_FLASHCTL_AT_BUF2_ERASE_PRGM	0x0286	/* Erase program */
-#define SSB_CHIPCO_FLASHCTL_AT_BUF1_PROGRAM	0x0288
-#define SSB_CHIPCO_FLASHCTL_AT_BUF2_PROGRAM	0x0289
-#define SSB_CHIPCO_FLASHCTL_AT_PAGE_ERASE	0x0281
-#define SSB_CHIPCO_FLASHCTL_AT_BLOCK_ERASE	0x0250
-#define SSB_CHIPCO_FLASHCTL_AT_BUF1_WRER_PRGM	0x0382	/* Write erase program */
-#define SSB_CHIPCO_FLASHCTL_AT_BUF2_WRER_PRGM	0x0385	/* Write erase program */
-#define SSB_CHIPCO_FLASHCTL_AT_BUF1_LOAD	0x0253
-#define SSB_CHIPCO_FLASHCTL_AT_BUF2_LOAD	0x0255
-#define SSB_CHIPCO_FLASHCTL_AT_BUF1_COMPARE	0x0260
-#define SSB_CHIPCO_FLASHCTL_AT_BUF2_COMPARE	0x0261
-#define SSB_CHIPCO_FLASHCTL_AT_BUF1_REPROGRAM	0x0258
-#define SSB_CHIPCO_FLASHCTL_AT_BUF2_REPROGRAM	0x0259
-
-/* Status register bits for Atmel flashes */
-#define SSB_CHIPCO_FLASHSTA_AT_READY	0x80
-#define SSB_CHIPCO_FLASHSTA_AT_MISMATCH	0x40
-#define SSB_CHIPCO_FLASHSTA_AT_ID	0x38
-#define SSB_CHIPCO_FLASHSTA_AT_ID_SHIFT	3
-
-
-/** OTP **/
-
-/* OTP regions */
-#define	SSB_CHIPCO_OTP_HW_REGION	SSB_CHIPCO_OTPS_HW_PROTECT
-#define	SSB_CHIPCO_OTP_SW_REGION	SSB_CHIPCO_OTPS_SW_PROTECT
-#define	SSB_CHIPCO_OTP_CID_REGION	SSB_CHIPCO_OTPS_CID_PROTECT
-
-/* OTP regions (Byte offsets from otp size) */
-#define	SSB_CHIPCO_OTP_SWLIM_OFF	(-8)
-#define	SSB_CHIPCO_OTP_CIDBASE_OFF	0
-#define	SSB_CHIPCO_OTP_CIDLIM_OFF	8
-
-/* Predefined OTP words (Word offset from otp size) */
-#define	SSB_CHIPCO_OTP_BOUNDARY_OFF	(-4)
-#define	SSB_CHIPCO_OTP_HWSIGN_OFF	(-3)
-#define	SSB_CHIPCO_OTP_SWSIGN_OFF	(-2)
-#define	SSB_CHIPCO_OTP_CIDSIGN_OFF	(-1)
-
-#define	SSB_CHIPCO_OTP_CID_OFF		0
-#define	SSB_CHIPCO_OTP_PKG_OFF		1
-#define	SSB_CHIPCO_OTP_FID_OFF		2
-#define	SSB_CHIPCO_OTP_RSV_OFF		3
-#define	SSB_CHIPCO_OTP_LIM_OFF		4
-
-#define	SSB_CHIPCO_OTP_SIGNATURE	0x578A
-#define	SSB_CHIPCO_OTP_MAGIC		0x4E56
-
-
-struct ssb_device;
-struct ssb_serial_port;
-
-/* Data for the PMU, if available.
- * Check availability with ((struct ssb_chipcommon)->capabilities & SSB_CHIPCO_CAP_PMU)
- */
-struct ssb_chipcommon_pmu {
-	u8 rev;			/* PMU revision */
-	u32 crystalfreq;	/* The active crystal frequency (in kHz) */
-};
-
-struct ssb_chipcommon {
-	struct ssb_device *dev;
-	u32 capabilities;
-	u32 status;
-	/* Fast Powerup Delay constant */
-	u16 fast_pwrup_delay;
-	struct ssb_chipcommon_pmu pmu;
-};
-
-static inline bool ssb_chipco_available(struct ssb_chipcommon *cc)
-{
-	return (cc->dev != NULL);
-}
-
-/* Register access */
-#define chipco_read32(cc, offset)	ssb_read32((cc)->dev, offset)
-#define chipco_write32(cc, offset, val)	ssb_write32((cc)->dev, offset, val)
-
-#define chipco_mask32(cc, offset, mask) \
-		chipco_write32(cc, offset, chipco_read32(cc, offset) & (mask))
-#define chipco_set32(cc, offset, set) \
-		chipco_write32(cc, offset, chipco_read32(cc, offset) | (set))
-#define chipco_maskset32(cc, offset, mask, set) \
-		chipco_write32(cc, offset, (chipco_read32(cc, offset) & (mask)) | (set))
-
-extern void ssb_chipcommon_init(struct ssb_chipcommon *cc);
-
-extern void ssb_chipco_suspend(struct ssb_chipcommon *cc);
-extern void ssb_chipco_resume(struct ssb_chipcommon *cc);
-
-extern void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
-                                    u32 *plltype, u32 *n, u32 *m);
-extern void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
-					u32 *plltype, u32 *n, u32 *m);
-extern void ssb_chipco_timing_init(struct ssb_chipcommon *cc,
-				   unsigned long ns_per_cycle);
-
-enum ssb_clkmode {
-	SSB_CLKMODE_SLOW,
-	SSB_CLKMODE_FAST,
-	SSB_CLKMODE_DYNAMIC,
-};
-
-extern void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
-				     enum ssb_clkmode mode);
-
-extern void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc,
-					  u32 ticks);
-
-void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value);
-
-u32 ssb_chipco_irq_status(struct ssb_chipcommon *cc, u32 mask);
-
-/* Chipcommon GPIO pin access. */
-u32 ssb_chipco_gpio_in(struct ssb_chipcommon *cc, u32 mask);
-u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value);
-u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value);
-u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value);
-u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value);
-u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value);
-
-#ifdef CONFIG_SSB_SERIAL
-extern int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
-				  struct ssb_serial_port *ports);
-#endif /* CONFIG_SSB_SERIAL */
-
-/* PMU support */
-extern void ssb_pmu_init(struct ssb_chipcommon *cc);
-
-enum ssb_pmu_ldo_volt_id {
-	LDO_PAREF = 0,
-	LDO_VOLT1,
-	LDO_VOLT2,
-	LDO_VOLT3,
-};
-
-void ssb_pmu_set_ldo_voltage(struct ssb_chipcommon *cc,
-			     enum ssb_pmu_ldo_volt_id id, u32 voltage);
-void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on);
-
-#endif /* LINUX_SSB_CHIPCO_H_ */
diff --git a/ANDROID_3.4.5/include/linux/ssb/ssb_driver_extif.h b/ANDROID_3.4.5/include/linux/ssb/ssb_driver_extif.h
deleted file mode 100644
index 91161f0a..00000000
--- a/ANDROID_3.4.5/include/linux/ssb/ssb_driver_extif.h
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
- * Hardware-specific External Interface I/O core definitions
- * for the BCM47xx family of SiliconBackplane-based chips.
- *
- * The External Interface core supports a total of three external chip selects
- * supporting external interfaces. One of the external chip selects is
- * used for Flash, one is used for PCMCIA, and the other may be
- * programmed to support either a synchronous interface or an
- * asynchronous interface. The asynchronous interface can be used to
- * support external devices such as UARTs and the BCM2019 Bluetooth
- * baseband processor.
- * The external interface core also contains 2 on-chip 16550 UARTs, clock
- * frequency control, a watchdog interrupt timer, and a GPIO interface.
- *
- * Copyright 2005, Broadcom Corporation
- * Copyright 2006, Michael Buesch
- *
- * Licensed under the GPL version 2. See COPYING for details.
- */
-#ifndef LINUX_SSB_EXTIFCORE_H_
-#define LINUX_SSB_EXTIFCORE_H_
-
-/* external interface address space */
-#define	SSB_EXTIF_PCMCIA_MEMBASE(x)	(x)
-#define	SSB_EXTIF_PCMCIA_IOBASE(x)	((x) + 0x100000)
-#define	SSB_EXTIF_PCMCIA_CFGBASE(x)	((x) + 0x200000)
-#define	SSB_EXTIF_CFGIF_BASE(x)		((x) + 0x800000)
-#define	SSB_EXTIF_FLASH_BASE(x)		((x) + 0xc00000)
-
-#define SSB_EXTIF_NR_GPIOOUT		5
-/* GPIO NOTE:
- * The multiple instances of output and output enable registers
- * are present to allow driver software for multiple cores to control
- * gpio outputs without needing to share a single register pair.
- * Use the following helper macro to get a register offset value.
- */
-#define SSB_EXTIF_GPIO_OUT(index)	({		\
-	BUILD_BUG_ON(index >= SSB_EXTIF_NR_GPIOOUT);	\
-	SSB_EXTIF_GPIO_OUT_BASE + ((index) * 8);	\
-					})
-#define SSB_EXTIF_GPIO_OUTEN(index)	({		\
-	BUILD_BUG_ON(index >= SSB_EXTIF_NR_GPIOOUT);	\
-	SSB_EXTIF_GPIO_OUTEN_BASE + ((index) * 8);	\
-					})
-
-/** EXTIF core registers **/
-
-#define SSB_EXTIF_CTL			0x0000
-#define  SSB_EXTIF_CTL_UARTEN		(1 << 0) /* UART enable */
-#define SSB_EXTIF_EXTSTAT		0x0004
-#define  SSB_EXTIF_EXTSTAT_EMODE	(1 << 0) /* Endian mode (ro) */
-#define  SSB_EXTIF_EXTSTAT_EIRQPIN	(1 << 1) /* External interrupt pin (ro) */
-#define  SSB_EXTIF_EXTSTAT_GPIOIRQPIN	(1 << 2) /* GPIO interrupt pin (ro) */
-#define SSB_EXTIF_PCMCIA_CFG		0x0010
-#define SSB_EXTIF_PCMCIA_MEMWAIT	0x0014
-#define SSB_EXTIF_PCMCIA_ATTRWAIT	0x0018
-#define SSB_EXTIF_PCMCIA_IOWAIT		0x001C
-#define SSB_EXTIF_PROG_CFG		0x0020
-#define SSB_EXTIF_PROG_WAITCNT		0x0024
-#define SSB_EXTIF_FLASH_CFG		0x0028
-#define SSB_EXTIF_FLASH_WAITCNT		0x002C
-#define SSB_EXTIF_WATCHDOG		0x0040
-#define SSB_EXTIF_CLOCK_N		0x0044
-#define SSB_EXTIF_CLOCK_SB		0x0048
-#define SSB_EXTIF_CLOCK_PCI		0x004C
-#define SSB_EXTIF_CLOCK_MII		0x0050
-#define SSB_EXTIF_GPIO_IN		0x0060
-#define SSB_EXTIF_GPIO_OUT_BASE		0x0064
-#define SSB_EXTIF_GPIO_OUTEN_BASE	0x0068
-#define SSB_EXTIF_EJTAG_OUTEN		0x0090
-#define SSB_EXTIF_GPIO_INTPOL		0x0094
-#define SSB_EXTIF_GPIO_INTMASK		0x0098
-#define SSB_EXTIF_UART_DATA		0x0300
-#define SSB_EXTIF_UART_TIMER		0x0310
-#define SSB_EXTIF_UART_FCR		0x0320
-#define SSB_EXTIF_UART_LCR		0x0330
-#define SSB_EXTIF_UART_MCR		0x0340
-#define SSB_EXTIF_UART_LSR		0x0350
-#define SSB_EXTIF_UART_MSR		0x0360
-#define SSB_EXTIF_UART_SCRATCH		0x0370
-
-
-
-
-/* pcmcia/prog/flash_config */
-#define	SSB_EXTCFG_EN			(1 << 0)	/* enable */
-#define	SSB_EXTCFG_MODE			0xE		/* mode */
-#define	SSB_EXTCFG_MODE_SHIFT		1
-#define	 SSB_EXTCFG_MODE_FLASH		0x0		/* flash/asynchronous mode */
-#define	 SSB_EXTCFG_MODE_SYNC		0x2		/* synchronous mode */
-#define	 SSB_EXTCFG_MODE_PCMCIA		0x4		/* pcmcia mode */
-#define	SSB_EXTCFG_DS16			(1 << 4)	/* destsize:  0=8bit, 1=16bit */
-#define	SSB_EXTCFG_BSWAP		(1 << 5)	/* byteswap */
-#define	SSB_EXTCFG_CLKDIV		0xC0		/* clock divider */
-#define	SSB_EXTCFG_CLKDIV_SHIFT		6
-#define	 SSB_EXTCFG_CLKDIV_2		0x0		/* backplane/2 */
-#define	 SSB_EXTCFG_CLKDIV_3		0x40		/* backplane/3 */
-#define	 SSB_EXTCFG_CLKDIV_4		0x80		/* backplane/4 */
-#define	SSB_EXTCFG_CLKEN		(1 << 8)	/* clock enable */
-#define	SSB_EXTCFG_STROBE		(1 << 9)	/* size/bytestrobe (synch only) */
-
-/* pcmcia_memwait */
-#define	SSB_PCMCIA_MEMW_0		0x0000003F	/* waitcount0 */
-#define	SSB_PCMCIA_MEMW_1		0x00001F00	/* waitcount1 */
-#define	SSB_PCMCIA_MEMW_1_SHIFT		8
-#define	SSB_PCMCIA_MEMW_2		0x001F0000	/* waitcount2 */
-#define	SSB_PCMCIA_MEMW_2_SHIFT		16
-#define	SSB_PCMCIA_MEMW_3		0x1F000000	/* waitcount3 */
-#define	SSB_PCMCIA_MEMW_3_SHIFT		24
-
-/* pcmcia_attrwait */
-#define	SSB_PCMCIA_ATTW_0		0x0000003F	/* waitcount0 */
-#define	SSB_PCMCIA_ATTW_1		0x00001F00	/* waitcount1 */
-#define	SSB_PCMCIA_ATTW_1_SHIFT		8
-#define	SSB_PCMCIA_ATTW_2		0x001F0000	/* waitcount2 */
-#define	SSB_PCMCIA_ATTW_2_SHIFT		16
-#define	SSB_PCMCIA_ATTW_3		0x1F000000	/* waitcount3 */
-#define	SSB_PCMCIA_ATTW_3_SHIFT		24
-
-/* pcmcia_iowait */
-#define	SSB_PCMCIA_IOW_0		0x0000003F	/* waitcount0 */
-#define	SSB_PCMCIA_IOW_1		0x00001F00	/* waitcount1 */
-#define	SSB_PCMCIA_IOW_1_SHIFT		8
-#define	SSB_PCMCIA_IOW_2		0x001F0000	/* waitcount2 */
-#define	SSB_PCMCIA_IOW_2_SHIFT		16
-#define	SSB_PCMCIA_IOW_3		0x1F000000	/* waitcount3 */
-#define	SSB_PCMCIA_IOW_3_SHIFT		24
-
-/* prog_waitcount */
-#define	SSB_PROG_WCNT_0			0x0000001F	/* waitcount0 */
-#define	SSB_PROG_WCNT_1			0x00001F00	/* waitcount1 */
-#define	SSB_PROG_WCNT_1_SHIFT		8
-#define	SSB_PROG_WCNT_2			0x001F0000	/* waitcount2 */
-#define	SSB_PROG_WCNT_2_SHIFT		16
-#define	SSB_PROG_WCNT_3			0x1F000000	/* waitcount3 */
-#define	SSB_PROG_WCNT_3_SHIFT		24
-
-#define SSB_PROG_W0			0x0000000C
-#define SSB_PROG_W1			0x00000A00
-#define SSB_PROG_W2			0x00020000
-#define SSB_PROG_W3			0x01000000
-
-/* flash_waitcount */
-#define	SSB_FLASH_WCNT_0		0x0000001F	/* waitcount0 */
-#define	SSB_FLASH_WCNT_1		0x00001F00	/* waitcount1 */
-#define	SSB_FLASH_WCNT_1_SHIFT		8
-#define	SSB_FLASH_WCNT_2		0x001F0000	/* waitcount2 */
-#define	SSB_FLASH_WCNT_2_SHIFT		16
-#define	SSB_FLASH_WCNT_3		0x1F000000	/* waitcount3 */
-#define	SSB_FLASH_WCNT_3_SHIFT		24
-
-/* watchdog */
-#define SSB_EXTIF_WATCHDOG_CLK		48000000	/* Hz */
-
-
-
-#ifdef CONFIG_SSB_DRIVER_EXTIF
-
-struct ssb_extif {
-	struct ssb_device *dev;
-};
-
-static inline bool ssb_extif_available(struct ssb_extif *extif)
-{
-	return (extif->dev != NULL);
-}
-
-extern void ssb_extif_get_clockcontrol(struct ssb_extif *extif,
-			               u32 *plltype, u32 *n, u32 *m);
-
-extern void ssb_extif_timing_init(struct ssb_extif *extif,
-				  unsigned long ns);
-
-extern void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
-					 u32 ticks);
-
-/* Extif GPIO pin access */
-u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask);
-u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask, u32 value);
-u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask, u32 value);
-u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask, u32 value);
-u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask, u32 value);
-
-#ifdef CONFIG_SSB_SERIAL
-extern int ssb_extif_serial_init(struct ssb_extif *extif,
-				 struct ssb_serial_port *ports);
-#endif /* CONFIG_SSB_SERIAL */
-
-
-#else /* CONFIG_SSB_DRIVER_EXTIF */
-/* extif disabled */
-
-struct ssb_extif {
-};
-
-static inline bool ssb_extif_available(struct ssb_extif *extif)
-{
-	return 0;
-}
-
-static inline
-void ssb_extif_get_clockcontrol(struct ssb_extif *extif,
-			        u32 *plltype, u32 *n, u32 *m)
-{
-}
-
-static inline
-void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
-				  u32 ticks)
-{
-}
-
-#endif /* CONFIG_SSB_DRIVER_EXTIF */
-#endif /* LINUX_SSB_EXTIFCORE_H_ */
diff --git a/ANDROID_3.4.5/include/linux/ssb/ssb_driver_gige.h b/ANDROID_3.4.5/include/linux/ssb/ssb_driver_gige.h
deleted file mode 100644
index 6b05dcd9..00000000
--- a/ANDROID_3.4.5/include/linux/ssb/ssb_driver_gige.h
+++ /dev/null
@@ -1,180 +0,0 @@
-#ifndef LINUX_SSB_DRIVER_GIGE_H_
-#define LINUX_SSB_DRIVER_GIGE_H_
-
-#include <linux/ssb/ssb.h>
-#include <linux/bug.h>
-#include <linux/pci.h>
-#include <linux/spinlock.h>
-
-
-#ifdef CONFIG_SSB_DRIVER_GIGE
-
-
-#define SSB_GIGE_PCIIO			0x0000 /* PCI I/O Registers (1024 bytes) */
-#define SSB_GIGE_RESERVED		0x0400 /* Reserved (1024 bytes) */
-#define SSB_GIGE_PCICFG			0x0800 /* PCI config space (256 bytes) */
-#define SSB_GIGE_SHIM_FLUSHSTAT		0x0C00 /* PCI to OCP: Flush status control (32bit) */
-#define SSB_GIGE_SHIM_FLUSHRDA		0x0C04 /* PCI to OCP: Flush read address (32bit) */
-#define SSB_GIGE_SHIM_FLUSHTO		0x0C08 /* PCI to OCP: Flush timeout counter (32bit) */
-#define SSB_GIGE_SHIM_BARRIER		0x0C0C /* PCI to OCP: Barrier register (32bit) */
-#define SSB_GIGE_SHIM_MAOCPSI		0x0C10 /* PCI to OCP: MaocpSI Control (32bit) */
-#define SSB_GIGE_SHIM_SIOCPMA		0x0C14 /* PCI to OCP: SiocpMa Control (32bit) */
-
-/* TM Status High flags */
-#define SSB_GIGE_TMSHIGH_RGMII		0x00010000 /* Have an RGMII PHY-bus */
-/* TM Status Low flags */
-#define SSB_GIGE_TMSLOW_TXBYPASS	0x00080000 /* TX bypass (no delay) */
-#define SSB_GIGE_TMSLOW_RXBYPASS	0x00100000 /* RX bypass (no delay) */
-#define SSB_GIGE_TMSLOW_DLLEN		0x01000000 /* Enable DLL controls */
-
-/* Boardflags (low) */
-#define SSB_GIGE_BFL_ROBOSWITCH		0x0010
-
-
-#define SSB_GIGE_MEM_RES_NAME		"SSB Broadcom 47xx GigE memory"
-#define SSB_GIGE_IO_RES_NAME		"SSB Broadcom 47xx GigE I/O"
-
-struct ssb_gige {
-	struct ssb_device *dev;
-
-	spinlock_t lock;
-
-	/* True, if the device has an RGMII bus.
-	 * False, if the device has a GMII bus. */
-	bool has_rgmii;
-
-	/* The PCI controller device. */
-	struct pci_controller pci_controller;
-	struct pci_ops pci_ops;
-	struct resource mem_resource;
-	struct resource io_resource;
-};
-
-/* Check whether a PCI device is a SSB Gigabit Ethernet core. */
-extern bool pdev_is_ssb_gige_core(struct pci_dev *pdev);
-
-/* Convert a pci_dev pointer to a ssb_gige pointer. */
-static inline struct ssb_gige * pdev_to_ssb_gige(struct pci_dev *pdev)
-{
-	if (!pdev_is_ssb_gige_core(pdev))
-		return NULL;
-	return container_of(pdev->bus->ops, struct ssb_gige, pci_ops);
-}
-
-/* Returns whether the PHY is connected by an RGMII bus. */
-static inline bool ssb_gige_is_rgmii(struct pci_dev *pdev)
-{
-	struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
-	return (dev ? dev->has_rgmii : 0);
-}
-
-/* Returns whether we have a Roboswitch. */
-static inline bool ssb_gige_have_roboswitch(struct pci_dev *pdev)
-{
-	struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
-	if (dev)
-		return !!(dev->dev->bus->sprom.boardflags_lo &
-			  SSB_GIGE_BFL_ROBOSWITCH);
-	return 0;
-}
-
-/* Returns whether we can only do one DMA at once. */
-static inline bool ssb_gige_one_dma_at_once(struct pci_dev *pdev)
-{
-	struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
-	if (dev)
-		return ((dev->dev->bus->chip_id == 0x4785) &&
-			(dev->dev->bus->chip_rev < 2));
-	return 0;
-}
-
-/* Returns whether we must flush posted writes. */
-static inline bool ssb_gige_must_flush_posted_writes(struct pci_dev *pdev)
-{
-	struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
-	if (dev)
-		return (dev->dev->bus->chip_id == 0x4785);
-	return 0;
-}
-
-#ifdef CONFIG_BCM47XX
-#include <asm/mach-bcm47xx/nvram.h>
-/* Get the device MAC address */
-static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
-{
-	char buf[20];
-	if (nvram_getenv("et0macaddr", buf, sizeof(buf)) < 0)
-		return;
-	nvram_parse_macaddr(buf, macaddr);
-}
-#else
-static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
-{
-}
-#endif
-
-extern int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
-					  struct pci_dev *pdev);
-extern int ssb_gige_map_irq(struct ssb_device *sdev,
-			    const struct pci_dev *pdev);
-
-/* The GigE driver is not a standalone module, because we don't have support
- * for unregistering the driver. So we could not unload the module anyway. */
-extern int ssb_gige_init(void);
-static inline void ssb_gige_exit(void)
-{
-	/* Currently we can not unregister the GigE driver,
-	 * because we can not unregister the PCI bridge. */
-	BUG();
-}
-
-
-#else /* CONFIG_SSB_DRIVER_GIGE */
-/* Gigabit Ethernet driver disabled */
-
-
-static inline int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
-						 struct pci_dev *pdev)
-{
-	return -ENOSYS;
-}
-static inline int ssb_gige_map_irq(struct ssb_device *sdev,
-				   const struct pci_dev *pdev)
-{
-	return -ENOSYS;
-}
-static inline int ssb_gige_init(void)
-{
-	return 0;
-}
-static inline void ssb_gige_exit(void)
-{
-}
-
-static inline bool pdev_is_ssb_gige_core(struct pci_dev *pdev)
-{
-	return 0;
-}
-static inline struct ssb_gige * pdev_to_ssb_gige(struct pci_dev *pdev)
-{
-	return NULL;
-}
-static inline bool ssb_gige_is_rgmii(struct pci_dev *pdev)
-{
-	return 0;
-}
-static inline bool ssb_gige_have_roboswitch(struct pci_dev *pdev)
-{
-	return 0;
-}
-static inline bool ssb_gige_one_dma_at_once(struct pci_dev *pdev)
-{
-	return 0;
-}
-static inline bool ssb_gige_must_flush_posted_writes(struct pci_dev *pdev)
-{
-	return 0;
-}
-
-#endif /* CONFIG_SSB_DRIVER_GIGE */
-#endif /* LINUX_SSB_DRIVER_GIGE_H_ */
diff --git a/ANDROID_3.4.5/include/linux/ssb/ssb_driver_mips.h b/ANDROID_3.4.5/include/linux/ssb/ssb_driver_mips.h
deleted file mode 100644
index 5f44e974..00000000
--- a/ANDROID_3.4.5/include/linux/ssb/ssb_driver_mips.h
+++ /dev/null
@@ -1,46 +0,0 @@
-#ifndef LINUX_SSB_MIPSCORE_H_
-#define LINUX_SSB_MIPSCORE_H_
-
-#ifdef CONFIG_SSB_DRIVER_MIPS
-
-struct ssb_device;
-
-struct ssb_serial_port {
-	void *regs;
-	unsigned long clockspeed;
-	unsigned int irq;
-	unsigned int baud_base;
-	unsigned int reg_shift;
-};
-
-
-struct ssb_mipscore {
-	struct ssb_device *dev;
-
-	int nr_serial_ports;
-	struct ssb_serial_port serial_ports[4];
-
-	u8 flash_buswidth;
-	u32 flash_window;
-	u32 flash_window_size;
-};
-
-extern void ssb_mipscore_init(struct ssb_mipscore *mcore);
-extern u32 ssb_cpu_clock(struct ssb_mipscore *mcore);
-
-extern unsigned int ssb_mips_irq(struct ssb_device *dev);
-
-
-#else /* CONFIG_SSB_DRIVER_MIPS */
-
-struct ssb_mipscore {
-};
-
-static inline
-void ssb_mipscore_init(struct ssb_mipscore *mcore)
-{
-}
-
-#endif /* CONFIG_SSB_DRIVER_MIPS */
-
-#endif /* LINUX_SSB_MIPSCORE_H_ */
diff --git a/ANDROID_3.4.5/include/linux/ssb/ssb_driver_pci.h b/ANDROID_3.4.5/include/linux/ssb/ssb_driver_pci.h
deleted file mode 100644
index 41e330e5..00000000
--- a/ANDROID_3.4.5/include/linux/ssb/ssb_driver_pci.h
+++ /dev/null
@@ -1,130 +0,0 @@
-#ifndef LINUX_SSB_PCICORE_H_
-#define LINUX_SSB_PCICORE_H_
-
-#include <linux/types.h>
-
-struct pci_dev;
-
-
-#ifdef CONFIG_SSB_DRIVER_PCICORE
-
-/* PCI core registers. */
-#define SSB_PCICORE_CTL			0x0000	/* PCI Control */
-#define  SSB_PCICORE_CTL_RST_OE		0x00000001 /* PCI_RESET Output Enable */
-#define  SSB_PCICORE_CTL_RST		0x00000002 /* PCI_RESET driven out to pin */
-#define  SSB_PCICORE_CTL_CLK_OE		0x00000004 /* Clock gate Output Enable */
-#define  SSB_PCICORE_CTL_CLK		0x00000008 /* Gate for clock driven out to pin */
-#define SSB_PCICORE_ARBCTL		0x0010	/* PCI Arbiter Control */
-#define  SSB_PCICORE_ARBCTL_INTERN	0x00000001 /* Use internal arbiter */
-#define  SSB_PCICORE_ARBCTL_EXTERN	0x00000002 /* Use external arbiter */
-#define  SSB_PCICORE_ARBCTL_PARKID	0x00000006 /* Mask, selects which agent is parked on an idle bus */
-#define   SSB_PCICORE_ARBCTL_PARKID_LAST	0x00000000 /* Last requestor */
-#define   SSB_PCICORE_ARBCTL_PARKID_4710	0x00000002 /* 4710 */
-#define   SSB_PCICORE_ARBCTL_PARKID_EXT0	0x00000004 /* External requestor 0 */
-#define   SSB_PCICORE_ARBCTL_PARKID_EXT1	0x00000006 /* External requestor 1 */
-#define SSB_PCICORE_ISTAT		0x0020	/* Interrupt status */
-#define  SSB_PCICORE_ISTAT_INTA		0x00000001 /* PCI INTA# */
-#define  SSB_PCICORE_ISTAT_INTB		0x00000002 /* PCI INTB# */
-#define  SSB_PCICORE_ISTAT_SERR		0x00000004 /* PCI SERR# (write to clear) */
-#define  SSB_PCICORE_ISTAT_PERR		0x00000008 /* PCI PERR# (write to clear) */
-#define  SSB_PCICORE_ISTAT_PME		0x00000010 /* PCI PME# */
-#define SSB_PCICORE_IMASK		0x0024	/* Interrupt mask */
-#define  SSB_PCICORE_IMASK_INTA		0x00000001 /* PCI INTA# */
-#define  SSB_PCICORE_IMASK_INTB		0x00000002 /* PCI INTB# */
-#define  SSB_PCICORE_IMASK_SERR		0x00000004 /* PCI SERR# */
-#define  SSB_PCICORE_IMASK_PERR		0x00000008 /* PCI PERR# */
-#define  SSB_PCICORE_IMASK_PME		0x00000010 /* PCI PME# */
-#define SSB_PCICORE_MBOX		0x0028	/* Backplane to PCI Mailbox */
-#define  SSB_PCICORE_MBOX_F0_0		0x00000100 /* PCI function 0, INT 0 */
-#define  SSB_PCICORE_MBOX_F0_1		0x00000200 /* PCI function 0, INT 1 */
-#define  SSB_PCICORE_MBOX_F1_0		0x00000400 /* PCI function 1, INT 0 */
-#define  SSB_PCICORE_MBOX_F1_1		0x00000800 /* PCI function 1, INT 1 */
-#define  SSB_PCICORE_MBOX_F2_0		0x00001000 /* PCI function 2, INT 0 */
-#define  SSB_PCICORE_MBOX_F2_1		0x00002000 /* PCI function 2, INT 1 */
-#define  SSB_PCICORE_MBOX_F3_0		0x00004000 /* PCI function 3, INT 0 */
-#define  SSB_PCICORE_MBOX_F3_1		0x00008000 /* PCI function 3, INT 1 */
-#define SSB_PCICORE_BCAST_ADDR		0x0050	/* Backplane Broadcast Address */
-#define  SSB_PCICORE_BCAST_ADDR_MASK	0x000000FF
-#define SSB_PCICORE_BCAST_DATA		0x0054	/* Backplane Broadcast Data */
-#define SSB_PCICORE_GPIO_IN		0x0060	/* rev >= 2 only */
-#define SSB_PCICORE_GPIO_OUT		0x0064	/* rev >= 2 only */
-#define SSB_PCICORE_GPIO_ENABLE		0x0068	/* rev >= 2 only */
-#define SSB_PCICORE_GPIO_CTL		0x006C	/* rev >= 2 only */
-#define SSB_PCICORE_SBTOPCI0		0x0100	/* Backplane to PCI translation 0 (sbtopci0) */
-#define  SSB_PCICORE_SBTOPCI0_MASK	0xFC000000
-#define SSB_PCICORE_SBTOPCI1		0x0104	/* Backplane to PCI translation 1 (sbtopci1) */
-#define  SSB_PCICORE_SBTOPCI1_MASK	0xFC000000
-#define SSB_PCICORE_SBTOPCI2		0x0108	/* Backplane to PCI translation 2 (sbtopci2) */
-#define  SSB_PCICORE_SBTOPCI2_MASK	0xC0000000
-#define SSB_PCICORE_PCICFG0		0x0400	/* PCI config space 0 (rev >= 8) */
-#define SSB_PCICORE_PCICFG1		0x0500	/* PCI config space 1 (rev >= 8) */
-#define SSB_PCICORE_PCICFG2		0x0600	/* PCI config space 2 (rev >= 8) */
-#define SSB_PCICORE_PCICFG3		0x0700	/* PCI config space 3 (rev >= 8) */
-#define SSB_PCICORE_SPROM(wordoffset)	(0x0800 + ((wordoffset) * 2)) /* SPROM shadow area (72 bytes) */
-
-/* SBtoPCIx */
-#define SSB_PCICORE_SBTOPCI_MEM		0x00000000
-#define SSB_PCICORE_SBTOPCI_IO		0x00000001
-#define SSB_PCICORE_SBTOPCI_CFG0	0x00000002
-#define SSB_PCICORE_SBTOPCI_CFG1	0x00000003
-#define SSB_PCICORE_SBTOPCI_PREF	0x00000004 /* Prefetch enable */
-#define SSB_PCICORE_SBTOPCI_BURST	0x00000008 /* Burst enable */
-#define SSB_PCICORE_SBTOPCI_MRM		0x00000020 /* Memory Read Multiple */
-#define SSB_PCICORE_SBTOPCI_RC		0x00000030 /* Read Command mask (rev >= 11) */
-#define  SSB_PCICORE_SBTOPCI_RC_READ	0x00000000 /* Memory read */
-#define  SSB_PCICORE_SBTOPCI_RC_READL	0x00000010 /* Memory read line */
-#define  SSB_PCICORE_SBTOPCI_RC_READM	0x00000020 /* Memory read multiple */
-
-
-/* PCIcore specific boardflags */
-#define SSB_PCICORE_BFL_NOPCI		0x00000400 /* Board leaves PCI floating */
-
-
-struct ssb_pcicore {
-	struct ssb_device *dev;
-	u8 setup_done:1;
-	u8 hostmode:1;
-	u8 cardbusmode:1;
-};
-
-extern void ssb_pcicore_init(struct ssb_pcicore *pc);
-
-/* Enable IRQ routing for a specific device */
-extern int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
-					  struct ssb_device *dev);
-
-int ssb_pcicore_plat_dev_init(struct pci_dev *d);
-int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
-
-
-#else /* CONFIG_SSB_DRIVER_PCICORE */
-
-
-struct ssb_pcicore {
-};
-
-static inline
-void ssb_pcicore_init(struct ssb_pcicore *pc)
-{
-}
-
-static inline
-int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
-				   struct ssb_device *dev)
-{
-	return 0;
-}
-
-static inline
-int ssb_pcicore_plat_dev_init(struct pci_dev *d)
-{
-	return -ENODEV;
-}
-static inline
-int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
-	return -ENODEV;
-}
-
-#endif /* CONFIG_SSB_DRIVER_PCICORE */
-#endif /* LINUX_SSB_PCICORE_H_ */
diff --git a/ANDROID_3.4.5/include/linux/ssb/ssb_embedded.h b/ANDROID_3.4.5/include/linux/ssb/ssb_embedded.h
deleted file mode 100644
index 8d8dedff..00000000
--- a/ANDROID_3.4.5/include/linux/ssb/ssb_embedded.h
+++ /dev/null
@@ -1,18 +0,0 @@
-#ifndef LINUX_SSB_EMBEDDED_H_
-#define LINUX_SSB_EMBEDDED_H_
-
-#include <linux/types.h>
-#include <linux/ssb/ssb.h>
-
-
-extern int ssb_watchdog_timer_set(struct ssb_bus *bus, u32 ticks);
-
-/* Generic GPIO API */
-u32 ssb_gpio_in(struct ssb_bus *bus, u32 mask);
-u32 ssb_gpio_out(struct ssb_bus *bus, u32 mask, u32 value);
-u32 ssb_gpio_outen(struct ssb_bus *bus, u32 mask, u32 value);
-u32 ssb_gpio_control(struct ssb_bus *bus, u32 mask, u32 value);
-u32 ssb_gpio_intmask(struct ssb_bus *bus, u32 mask, u32 value);
-u32 ssb_gpio_polarity(struct ssb_bus *bus, u32 mask, u32 value);
-
-#endif /* LINUX_SSB_EMBEDDED_H_ */
diff --git a/ANDROID_3.4.5/include/linux/ssb/ssb_regs.h b/ANDROID_3.4.5/include/linux/ssb/ssb_regs.h
deleted file mode 100644
index 40b1ef85..00000000
--- a/ANDROID_3.4.5/include/linux/ssb/ssb_regs.h
+++ /dev/null
@@ -1,594 +0,0 @@
-#ifndef LINUX_SSB_REGS_H_
-#define LINUX_SSB_REGS_H_
-
-
-/* SiliconBackplane Address Map.
- * All regions may not exist on all chips.
- */
-#define SSB_SDRAM_BASE		0x00000000U	/* Physical SDRAM */
-#define SSB_PCI_MEM		0x08000000U	/* Host Mode sb2pcitranslation0 (64 MB) */
-#define SSB_PCI_CFG		0x0c000000U	/* Host Mode sb2pcitranslation1 (64 MB) */
-#define	SSB_SDRAM_SWAPPED	0x10000000U	/* Byteswapped Physical SDRAM */
-#define SSB_ENUM_BASE    	0x18000000U	/* Enumeration space base */
-#define	SSB_ENUM_LIMIT		0x18010000U	/* Enumeration space limit */
-
-#define	SSB_FLASH2		0x1c000000U	/* Flash Region 2 (region 1 shadowed here) */
-#define	SSB_FLASH2_SZ		0x02000000U	/* Size of Flash Region 2 */
-
-#define	SSB_EXTIF_BASE		0x1f000000U	/* External Interface region base address */
-#define	SSB_FLASH1		0x1fc00000U	/* Flash Region 1 */
-#define	SSB_FLASH1_SZ		0x00400000U	/* Size of Flash Region 1 */
-
-#define SSB_PCI_DMA		0x40000000U	/* Client Mode sb2pcitranslation2 (1 GB) */
-#define SSB_PCI_DMA_SZ		0x40000000U	/* Client Mode sb2pcitranslation2 size in bytes */
-#define SSB_PCIE_DMA_L32	0x00000000U	/* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), low 32 bits */
-#define SSB_PCIE_DMA_H32	0x80000000U	/* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */
-#define	SSB_EUART		(SSB_EXTIF_BASE + 0x00800000)
-#define	SSB_LED			(SSB_EXTIF_BASE + 0x00900000)
-
-
-/* Enumeration space constants */
-#define SSB_CORE_SIZE		0x1000	/* Size of a core MMIO area */
-#define SSB_MAX_NR_CORES	((SSB_ENUM_LIMIT - SSB_ENUM_BASE) / SSB_CORE_SIZE)
-
-
-/* mips address */
-#define	SSB_EJTAG		0xff200000	/* MIPS EJTAG space (2M) */
-
-
-/* SSB PCI config space registers. */
-#define SSB_PMCSR		0x44
-#define  SSB_PE			0x100
-#define	SSB_BAR0_WIN		0x80	/* Backplane address space 0 */
-#define	SSB_BAR1_WIN		0x84	/* Backplane address space 1 */
-#define	SSB_SPROMCTL		0x88	/* SPROM control */
-#define  SSB_SPROMCTL_WE	0x10	/* SPROM write enable */
-#define	SSB_BAR1_CONTROL	0x8c	/* Address space 1 burst control */
-#define SSB_PCI_IRQS		0x90	/* PCI interrupts */
-#define SSB_PCI_IRQMASK		0x94	/* PCI IRQ control and mask (pcirev >= 6 only) */
-#define SSB_BACKPLANE_IRQS	0x98	/* Backplane Interrupts */
-#define SSB_GPIO_IN		0xB0	/* GPIO Input (pcirev >= 3 only) */
-#define SSB_GPIO_OUT		0xB4	/* GPIO Output (pcirev >= 3 only) */
-#define SSB_GPIO_OUT_ENABLE	0xB8	/* GPIO Output Enable/Disable (pcirev >= 3 only) */
-#define  SSB_GPIO_SCS		0x10	/* PCI config space bit 4 for 4306c0 slow clock source */
-#define  SSB_GPIO_HWRAD		0x20	/* PCI config space GPIO 13 for hw radio disable */
-#define  SSB_GPIO_XTAL		0x40	/* PCI config space GPIO 14 for Xtal powerup */
-#define  SSB_GPIO_PLL		0x80	/* PCI config space GPIO 15 for PLL powerdown */
-
-
-#define SSB_BAR0_MAX_RETRIES	50
-
-/* Silicon backplane configuration register definitions */
-#define SSB_IPSFLAG		0x0F08
-#define	 SSB_IPSFLAG_IRQ1	0x0000003F /* which sbflags get routed to mips interrupt 1 */
-#define	 SSB_IPSFLAG_IRQ1_SHIFT	0
-#define	 SSB_IPSFLAG_IRQ2	0x00003F00 /* which sbflags get routed to mips interrupt 2 */
-#define	 SSB_IPSFLAG_IRQ2_SHIFT	8
-#define	 SSB_IPSFLAG_IRQ3	0x003F0000 /* which sbflags get routed to mips interrupt 3 */
-#define	 SSB_IPSFLAG_IRQ3_SHIFT	16
-#define	 SSB_IPSFLAG_IRQ4	0x3F000000 /* which sbflags get routed to mips interrupt 4 */
-#define	 SSB_IPSFLAG_IRQ4_SHIFT	24
-#define SSB_TPSFLAG		0x0F18
-#define  SSB_TPSFLAG_BPFLAG	0x0000003F /* Backplane flag # */
-#define  SSB_TPSFLAG_ALWAYSIRQ	0x00000040 /* IRQ is always sent on the Backplane */
-#define SSB_TMERRLOGA		0x0F48
-#define SSB_TMERRLOG		0x0F50
-#define SSB_ADMATCH3		0x0F60
-#define SSB_ADMATCH2		0x0F68
-#define SSB_ADMATCH1		0x0F70
-#define SSB_IMSTATE		0x0F90     /* SB Initiator Agent State */
-#define  SSB_IMSTATE_PC		0x0000000f /* Pipe Count */
-#define  SSB_IMSTATE_AP_MASK	0x00000030 /* Arbitration Priority */
-#define  SSB_IMSTATE_AP_BOTH	0x00000000 /* Use both timeslices and token */
-#define  SSB_IMSTATE_AP_TS	0x00000010 /* Use timeslices only */
-#define  SSB_IMSTATE_AP_TK	0x00000020 /* Use token only */
-#define  SSB_IMSTATE_AP_RSV	0x00000030 /* Reserved */
-#define  SSB_IMSTATE_IBE	0x00020000 /* In Band Error */
-#define  SSB_IMSTATE_TO		0x00040000 /* Timeout */
-#define  SSB_IMSTATE_BUSY	0x01800000 /* Busy (Backplane rev >= 2.3 only) */
-#define  SSB_IMSTATE_REJECT	0x02000000 /* Reject (Backplane rev >= 2.3 only) */
-#define SSB_INTVEC		0x0F94     /* SB Interrupt Mask */
-#define  SSB_INTVEC_PCI		0x00000001 /* Enable interrupts for PCI */
-#define  SSB_INTVEC_ENET0	0x00000002 /* Enable interrupts for enet 0 */
-#define  SSB_INTVEC_ILINE20	0x00000004 /* Enable interrupts for iline20 */
-#define  SSB_INTVEC_CODEC	0x00000008 /* Enable interrupts for v90 codec */
-#define  SSB_INTVEC_USB		0x00000010 /* Enable interrupts for usb */
-#define  SSB_INTVEC_EXTIF	0x00000020 /* Enable interrupts for external i/f */
-#define  SSB_INTVEC_ENET1	0x00000040 /* Enable interrupts for enet 1 */
-#define SSB_TMSLOW		0x0F98     /* SB Target State Low */
-#define  SSB_TMSLOW_RESET	0x00000001 /* Reset */
-#define  SSB_TMSLOW_REJECT	0x00000002 /* Reject (Standard Backplane) */
-#define  SSB_TMSLOW_REJECT_23	0x00000004 /* Reject (Backplane rev 2.3) */
-#define  SSB_TMSLOW_CLOCK	0x00010000 /* Clock Enable */
-#define  SSB_TMSLOW_FGC		0x00020000 /* Force Gated Clocks On */
-#define  SSB_TMSLOW_PE		0x40000000 /* Power Management Enable */
-#define  SSB_TMSLOW_BE		0x80000000 /* BIST Enable */
-#define SSB_TMSHIGH		0x0F9C     /* SB Target State High */
-#define  SSB_TMSHIGH_SERR	0x00000001 /* S-error */
-#define  SSB_TMSHIGH_INT	0x00000002 /* Interrupt */
-#define  SSB_TMSHIGH_BUSY	0x00000004 /* Busy */
-#define  SSB_TMSHIGH_TO		0x00000020 /* Timeout. Backplane rev >= 2.3 only */
-#define  SSB_TMSHIGH_COREFL	0x1FFF0000 /* Core specific flags */
-#define  SSB_TMSHIGH_COREFL_SHIFT	16
-#define  SSB_TMSHIGH_DMA64	0x10000000 /* 64bit DMA supported */
-#define  SSB_TMSHIGH_GCR	0x20000000 /* Gated Clock Request */
-#define  SSB_TMSHIGH_BISTF	0x40000000 /* BIST Failed */
-#define  SSB_TMSHIGH_BISTD	0x80000000 /* BIST Done */
-#define SSB_BWA0		0x0FA0
-#define SSB_IMCFGLO		0x0FA8
-#define  SSB_IMCFGLO_SERTO	0x00000007 /* Service timeout */
-#define  SSB_IMCFGLO_REQTO	0x00000070 /* Request timeout */
-#define  SSB_IMCFGLO_REQTO_SHIFT	4
-#define  SSB_IMCFGLO_CONNID	0x00FF0000 /* Connection ID */
-#define  SSB_IMCFGLO_CONNID_SHIFT	16
-#define SSB_IMCFGHI		0x0FAC
-#define SSB_ADMATCH0		0x0FB0
-#define SSB_TMCFGLO		0x0FB8
-#define SSB_TMCFGHI		0x0FBC
-#define SSB_BCONFIG		0x0FC0
-#define SSB_BSTATE		0x0FC8
-#define SSB_ACTCFG		0x0FD8
-#define SSB_FLAGST		0x0FE8
-#define SSB_IDLOW		0x0FF8
-#define  SSB_IDLOW_CFGSP	0x00000003 /* Config Space */
-#define  SSB_IDLOW_ADDRNGE	0x00000038 /* Address Ranges supported */
-#define  SSB_IDLOW_ADDRNGE_SHIFT	3
-#define  SSB_IDLOW_SYNC		0x00000040
-#define  SSB_IDLOW_INITIATOR	0x00000080
-#define  SSB_IDLOW_MIBL		0x00000F00 /* Minimum Backplane latency */
-#define  SSB_IDLOW_MIBL_SHIFT	8
-#define  SSB_IDLOW_MABL		0x0000F000 /* Maximum Backplane latency */
-#define  SSB_IDLOW_MABL_SHIFT	12
-#define  SSB_IDLOW_TIF		0x00010000 /* This Initiator is first */
-#define  SSB_IDLOW_CCW		0x000C0000 /* Cycle counter width */
-#define  SSB_IDLOW_CCW_SHIFT	18
-#define  SSB_IDLOW_TPT		0x00F00000 /* Target ports */
-#define  SSB_IDLOW_TPT_SHIFT	20
-#define  SSB_IDLOW_INITP	0x0F000000 /* Initiator ports */
-#define  SSB_IDLOW_INITP_SHIFT	24
-#define  SSB_IDLOW_SSBREV	0xF0000000 /* Sonics Backplane Revision code */
-#define  SSB_IDLOW_SSBREV_22	0x00000000 /* <= 2.2 */
-#define  SSB_IDLOW_SSBREV_23	0x10000000 /* 2.3 */
-#define  SSB_IDLOW_SSBREV_24	0x40000000 /* ?? Found in BCM4328 */
-#define  SSB_IDLOW_SSBREV_25	0x50000000 /* ?? Not Found yet */
-#define  SSB_IDLOW_SSBREV_26	0x60000000 /* ?? Found in some BCM4311/2 */
-#define  SSB_IDLOW_SSBREV_27	0x70000000 /* ?? Found in some BCM4311/2 */
-#define SSB_IDHIGH		0x0FFC     /* SB Identification High */
-#define  SSB_IDHIGH_RCLO	0x0000000F /* Revision Code (low part) */
-#define  SSB_IDHIGH_CC		0x00008FF0 /* Core Code */
-#define  SSB_IDHIGH_CC_SHIFT	4
-#define  SSB_IDHIGH_RCHI	0x00007000 /* Revision Code (high part) */
-#define  SSB_IDHIGH_RCHI_SHIFT	8	   /* yes, shift 8 is right */
-#define  SSB_IDHIGH_VC		0xFFFF0000 /* Vendor Code */
-#define  SSB_IDHIGH_VC_SHIFT	16
-
-/* SPROM shadow area. If not otherwise noted, fields are
- * two bytes wide. Note that the SPROM can _only_ be read
- * in two-byte quantities.
- */
-#define SSB_SPROMSIZE_WORDS		64
-#define SSB_SPROMSIZE_BYTES		(SSB_SPROMSIZE_WORDS * sizeof(u16))
-#define SSB_SPROMSIZE_WORDS_R123	64
-#define SSB_SPROMSIZE_WORDS_R4		220
-#define SSB_SPROMSIZE_BYTES_R123	(SSB_SPROMSIZE_WORDS_R123 * sizeof(u16))
-#define SSB_SPROMSIZE_BYTES_R4		(SSB_SPROMSIZE_WORDS_R4 * sizeof(u16))
-#define SSB_SPROM_BASE1			0x1000
-#define SSB_SPROM_BASE31		0x0800
-#define SSB_SPROM_REVISION		0x007E
-#define  SSB_SPROM_REVISION_REV		0x00FF	/* SPROM Revision number */
-#define  SSB_SPROM_REVISION_CRC		0xFF00	/* SPROM CRC8 value */
-#define  SSB_SPROM_REVISION_CRC_SHIFT	8
-
-/* SPROM Revision 1 */
-#define SSB_SPROM1_SPID			0x0004	/* Subsystem Product ID for PCI */
-#define SSB_SPROM1_SVID			0x0006	/* Subsystem Vendor ID for PCI */
-#define SSB_SPROM1_PID			0x0008	/* Product ID for PCI */
-#define SSB_SPROM1_IL0MAC		0x0048	/* 6 bytes MAC address for 802.11b/g */
-#define SSB_SPROM1_ET0MAC		0x004E	/* 6 bytes MAC address for Ethernet */
-#define SSB_SPROM1_ET1MAC		0x0054	/* 6 bytes MAC address for 802.11a */
-#define SSB_SPROM1_ETHPHY		0x005A	/* Ethernet PHY settings */
-#define  SSB_SPROM1_ETHPHY_ET0A		0x001F	/* MII Address for enet0 */
-#define  SSB_SPROM1_ETHPHY_ET1A		0x03E0	/* MII Address for enet1 */
-#define  SSB_SPROM1_ETHPHY_ET1A_SHIFT	5
-#define  SSB_SPROM1_ETHPHY_ET0M		(1<<14)	/* MDIO for enet0 */
-#define  SSB_SPROM1_ETHPHY_ET1M		(1<<15)	/* MDIO for enet1 */
-#define SSB_SPROM1_BINF			0x005C	/* Board info */
-#define  SSB_SPROM1_BINF_BREV		0x00FF	/* Board Revision */
-#define  SSB_SPROM1_BINF_CCODE		0x0F00	/* Country Code */
-#define  SSB_SPROM1_BINF_CCODE_SHIFT	8
-#define  SSB_SPROM1_BINF_ANTBG		0x3000	/* Available B-PHY and G-PHY antennas */
-#define  SSB_SPROM1_BINF_ANTBG_SHIFT	12
-#define  SSB_SPROM1_BINF_ANTA		0xC000	/* Available A-PHY antennas */
-#define  SSB_SPROM1_BINF_ANTA_SHIFT	14
-#define SSB_SPROM1_PA0B0		0x005E
-#define SSB_SPROM1_PA0B1		0x0060
-#define SSB_SPROM1_PA0B2		0x0062
-#define SSB_SPROM1_GPIOA		0x0064	/* General Purpose IO pins 0 and 1 */
-#define  SSB_SPROM1_GPIOA_P0		0x00FF	/* Pin 0 */
-#define  SSB_SPROM1_GPIOA_P1		0xFF00	/* Pin 1 */
-#define  SSB_SPROM1_GPIOA_P1_SHIFT	8
-#define SSB_SPROM1_GPIOB		0x0066	/* General Purpuse IO pins 2 and 3 */
-#define  SSB_SPROM1_GPIOB_P2		0x00FF	/* Pin 2 */
-#define  SSB_SPROM1_GPIOB_P3		0xFF00	/* Pin 3 */
-#define  SSB_SPROM1_GPIOB_P3_SHIFT	8
-#define SSB_SPROM1_MAXPWR		0x0068	/* Power Amplifier Max Power */
-#define  SSB_SPROM1_MAXPWR_BG		0x00FF	/* B-PHY and G-PHY (in dBm Q5.2) */
-#define  SSB_SPROM1_MAXPWR_A		0xFF00	/* A-PHY (in dBm Q5.2) */
-#define  SSB_SPROM1_MAXPWR_A_SHIFT	8
-#define SSB_SPROM1_PA1B0		0x006A
-#define SSB_SPROM1_PA1B1		0x006C
-#define SSB_SPROM1_PA1B2		0x006E
-#define SSB_SPROM1_ITSSI		0x0070	/* Idle TSSI Target */
-#define  SSB_SPROM1_ITSSI_BG		0x00FF	/* B-PHY and G-PHY*/
-#define  SSB_SPROM1_ITSSI_A		0xFF00	/* A-PHY */
-#define  SSB_SPROM1_ITSSI_A_SHIFT	8
-#define SSB_SPROM1_BFLLO		0x0072	/* Boardflags (low 16 bits) */
-#define SSB_SPROM1_AGAIN		0x0074	/* Antenna Gain (in dBm Q5.2) */
-#define  SSB_SPROM1_AGAIN_BG		0x00FF	/* B-PHY and G-PHY */
-#define  SSB_SPROM1_AGAIN_BG_SHIFT	0
-#define  SSB_SPROM1_AGAIN_A		0xFF00	/* A-PHY */
-#define  SSB_SPROM1_AGAIN_A_SHIFT	8
-
-/* SPROM Revision 2 (inherits from rev 1) */
-#define SSB_SPROM2_BFLHI		0x0038	/* Boardflags (high 16 bits) */
-#define SSB_SPROM2_MAXP_A		0x003A	/* A-PHY Max Power */
-#define  SSB_SPROM2_MAXP_A_HI		0x00FF	/* Max Power High */
-#define  SSB_SPROM2_MAXP_A_LO		0xFF00	/* Max Power Low */
-#define  SSB_SPROM2_MAXP_A_LO_SHIFT	8
-#define SSB_SPROM2_PA1LOB0		0x003C	/* A-PHY PowerAmplifier Low Settings */
-#define SSB_SPROM2_PA1LOB1		0x003E	/* A-PHY PowerAmplifier Low Settings */
-#define SSB_SPROM2_PA1LOB2		0x0040	/* A-PHY PowerAmplifier Low Settings */
-#define SSB_SPROM2_PA1HIB0		0x0042	/* A-PHY PowerAmplifier High Settings */
-#define SSB_SPROM2_PA1HIB1		0x0044	/* A-PHY PowerAmplifier High Settings */
-#define SSB_SPROM2_PA1HIB2		0x0046	/* A-PHY PowerAmplifier High Settings */
-#define SSB_SPROM2_OPO			0x0078	/* OFDM Power Offset from CCK Level */
-#define  SSB_SPROM2_OPO_VALUE		0x00FF
-#define  SSB_SPROM2_OPO_UNUSED		0xFF00
-#define SSB_SPROM2_CCODE		0x007C	/* Two char Country Code */
-
-/* SPROM Revision 3 (inherits most data from rev 2) */
-#define SSB_SPROM3_OFDMAPO		0x002C	/* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
-#define SSB_SPROM3_OFDMALPO		0x0030	/* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
-#define SSB_SPROM3_OFDMAHPO		0x0034	/* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
-#define SSB_SPROM3_GPIOLDC		0x0042	/* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
-#define  SSB_SPROM3_GPIOLDC_OFF		0x0000FF00	/* Off Count */
-#define  SSB_SPROM3_GPIOLDC_OFF_SHIFT	8
-#define  SSB_SPROM3_GPIOLDC_ON		0x00FF0000	/* On Count */
-#define  SSB_SPROM3_GPIOLDC_ON_SHIFT	16
-#define SSB_SPROM3_IL0MAC		0x004A	/* 6 bytes MAC address for 802.11b/g */
-#define SSB_SPROM3_CCKPO		0x0078	/* CCK Power Offset */
-#define  SSB_SPROM3_CCKPO_1M		0x000F	/* 1M Rate PO */
-#define  SSB_SPROM3_CCKPO_2M		0x00F0	/* 2M Rate PO */
-#define  SSB_SPROM3_CCKPO_2M_SHIFT	4
-#define  SSB_SPROM3_CCKPO_55M		0x0F00	/* 5.5M Rate PO */
-#define  SSB_SPROM3_CCKPO_55M_SHIFT	8
-#define  SSB_SPROM3_CCKPO_11M		0xF000	/* 11M Rate PO */
-#define  SSB_SPROM3_CCKPO_11M_SHIFT	12
-#define  SSB_SPROM3_OFDMGPO		0x107A	/* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
-
-/* SPROM Revision 4 */
-#define SSB_SPROM4_BFLLO		0x0044	/* Boardflags (low 16 bits) */
-#define SSB_SPROM4_BFLHI		0x0046  /* Board Flags Hi */
-#define SSB_SPROM4_BFL2LO		0x0048	/* Board flags 2 (low 16 bits) */
-#define SSB_SPROM4_BFL2HI		0x004A	/* Board flags 2 Hi */
-#define SSB_SPROM4_IL0MAC		0x004C	/* 6 byte MAC address for a/b/g/n */
-#define SSB_SPROM4_CCODE		0x0052	/* Country Code (2 bytes) */
-#define SSB_SPROM4_GPIOA		0x0056	/* Gen. Purpose IO # 0 and 1 */
-#define  SSB_SPROM4_GPIOA_P0		0x00FF	/* Pin 0 */
-#define  SSB_SPROM4_GPIOA_P1		0xFF00	/* Pin 1 */
-#define  SSB_SPROM4_GPIOA_P1_SHIFT	8
-#define SSB_SPROM4_GPIOB		0x0058	/* Gen. Purpose IO # 2 and 3 */
-#define  SSB_SPROM4_GPIOB_P2		0x00FF	/* Pin 2 */
-#define  SSB_SPROM4_GPIOB_P3		0xFF00	/* Pin 3 */
-#define  SSB_SPROM4_GPIOB_P3_SHIFT	8
-#define SSB_SPROM4_ETHPHY		0x005A	/* Ethernet PHY settings ?? */
-#define  SSB_SPROM4_ETHPHY_ET0A		0x001F	/* MII Address for enet0 */
-#define  SSB_SPROM4_ETHPHY_ET1A		0x03E0	/* MII Address for enet1 */
-#define  SSB_SPROM4_ETHPHY_ET1A_SHIFT	5
-#define  SSB_SPROM4_ETHPHY_ET0M		(1<<14)	/* MDIO for enet0 */
-#define  SSB_SPROM4_ETHPHY_ET1M		(1<<15)	/* MDIO for enet1 */
-#define SSB_SPROM4_ANTAVAIL		0x005D  /* Antenna available bitfields */
-#define  SSB_SPROM4_ANTAVAIL_A		0x00FF	/* A-PHY bitfield */
-#define  SSB_SPROM4_ANTAVAIL_A_SHIFT	0
-#define  SSB_SPROM4_ANTAVAIL_BG		0xFF00	/* B-PHY and G-PHY bitfield */
-#define  SSB_SPROM4_ANTAVAIL_BG_SHIFT	8
-#define SSB_SPROM4_AGAIN01		0x005E	/* Antenna Gain (in dBm Q5.2) */
-#define  SSB_SPROM4_AGAIN0		0x00FF	/* Antenna 0 */
-#define  SSB_SPROM4_AGAIN0_SHIFT	0
-#define  SSB_SPROM4_AGAIN1		0xFF00	/* Antenna 1 */
-#define  SSB_SPROM4_AGAIN1_SHIFT	8
-#define SSB_SPROM4_AGAIN23		0x0060
-#define  SSB_SPROM4_AGAIN2		0x00FF	/* Antenna 2 */
-#define  SSB_SPROM4_AGAIN2_SHIFT	0
-#define  SSB_SPROM4_AGAIN3		0xFF00	/* Antenna 3 */
-#define  SSB_SPROM4_AGAIN3_SHIFT	8
-#define SSB_SPROM4_TXPID2G01		0x0062 	/* TX Power Index 2GHz */
-#define  SSB_SPROM4_TXPID2G0		0x00FF
-#define  SSB_SPROM4_TXPID2G0_SHIFT	0
-#define  SSB_SPROM4_TXPID2G1		0xFF00
-#define  SSB_SPROM4_TXPID2G1_SHIFT	8
-#define SSB_SPROM4_TXPID2G23		0x0064 	/* TX Power Index 2GHz */
-#define  SSB_SPROM4_TXPID2G2		0x00FF
-#define  SSB_SPROM4_TXPID2G2_SHIFT	0
-#define  SSB_SPROM4_TXPID2G3		0xFF00
-#define  SSB_SPROM4_TXPID2G3_SHIFT	8
-#define SSB_SPROM4_TXPID5G01		0x0066 	/* TX Power Index 5GHz middle subband */
-#define  SSB_SPROM4_TXPID5G0		0x00FF
-#define  SSB_SPROM4_TXPID5G0_SHIFT	0
-#define  SSB_SPROM4_TXPID5G1		0xFF00
-#define  SSB_SPROM4_TXPID5G1_SHIFT	8
-#define SSB_SPROM4_TXPID5G23		0x0068 	/* TX Power Index 5GHz middle subband */
-#define  SSB_SPROM4_TXPID5G2		0x00FF
-#define  SSB_SPROM4_TXPID5G2_SHIFT	0
-#define  SSB_SPROM4_TXPID5G3		0xFF00
-#define  SSB_SPROM4_TXPID5G3_SHIFT	8
-#define SSB_SPROM4_TXPID5GL01		0x006A 	/* TX Power Index 5GHz low subband */
-#define  SSB_SPROM4_TXPID5GL0		0x00FF
-#define  SSB_SPROM4_TXPID5GL0_SHIFT	0
-#define  SSB_SPROM4_TXPID5GL1		0xFF00
-#define  SSB_SPROM4_TXPID5GL1_SHIFT	8
-#define SSB_SPROM4_TXPID5GL23		0x006C 	/* TX Power Index 5GHz low subband */
-#define  SSB_SPROM4_TXPID5GL2		0x00FF
-#define  SSB_SPROM4_TXPID5GL2_SHIFT	0
-#define  SSB_SPROM4_TXPID5GL3		0xFF00
-#define  SSB_SPROM4_TXPID5GL3_SHIFT	8
-#define SSB_SPROM4_TXPID5GH01		0x006E 	/* TX Power Index 5GHz high subband */
-#define  SSB_SPROM4_TXPID5GH0		0x00FF
-#define  SSB_SPROM4_TXPID5GH0_SHIFT	0
-#define  SSB_SPROM4_TXPID5GH1		0xFF00
-#define  SSB_SPROM4_TXPID5GH1_SHIFT	8
-#define SSB_SPROM4_TXPID5GH23		0x0070 	/* TX Power Index 5GHz high subband */
-#define  SSB_SPROM4_TXPID5GH2		0x00FF
-#define  SSB_SPROM4_TXPID5GH2_SHIFT	0
-#define  SSB_SPROM4_TXPID5GH3		0xFF00
-#define  SSB_SPROM4_TXPID5GH3_SHIFT	8
-#define SSB_SPROM4_MAXP_BG		0x0080  /* Max Power BG in path 1 */
-#define  SSB_SPROM4_MAXP_BG_MASK	0x00FF  /* Mask for Max Power BG */
-#define  SSB_SPROM4_ITSSI_BG		0xFF00	/* Mask for path 1 itssi_bg */
-#define  SSB_SPROM4_ITSSI_BG_SHIFT	8
-#define SSB_SPROM4_MAXP_A		0x008A  /* Max Power A in path 1 */
-#define  SSB_SPROM4_MAXP_A_MASK		0x00FF  /* Mask for Max Power A */
-#define  SSB_SPROM4_ITSSI_A		0xFF00	/* Mask for path 1 itssi_a */
-#define  SSB_SPROM4_ITSSI_A_SHIFT	8
-#define SSB_SPROM4_PA0B0		0x0082	/* The paXbY locations are */
-#define SSB_SPROM4_PA0B1		0x0084	/*   only guesses */
-#define SSB_SPROM4_PA0B2		0x0086
-#define SSB_SPROM4_PA1B0		0x008E
-#define SSB_SPROM4_PA1B1		0x0090
-#define SSB_SPROM4_PA1B2		0x0092
-
-/* SPROM Revision 5 (inherits most data from rev 4) */
-#define SSB_SPROM5_CCODE		0x0044	/* Country Code (2 bytes) */
-#define SSB_SPROM5_BFLLO		0x004A	/* Boardflags (low 16 bits) */
-#define SSB_SPROM5_BFLHI		0x004C  /* Board Flags Hi */
-#define SSB_SPROM5_BFL2LO		0x004E	/* Board flags 2 (low 16 bits) */
-#define SSB_SPROM5_BFL2HI		0x0050	/* Board flags 2 Hi */
-#define SSB_SPROM5_IL0MAC		0x0052	/* 6 byte MAC address for a/b/g/n */
-#define SSB_SPROM5_GPIOA		0x0076	/* Gen. Purpose IO # 0 and 1 */
-#define  SSB_SPROM5_GPIOA_P0		0x00FF	/* Pin 0 */
-#define  SSB_SPROM5_GPIOA_P1		0xFF00	/* Pin 1 */
-#define  SSB_SPROM5_GPIOA_P1_SHIFT	8
-#define SSB_SPROM5_GPIOB		0x0078	/* Gen. Purpose IO # 2 and 3 */
-#define  SSB_SPROM5_GPIOB_P2		0x00FF	/* Pin 2 */
-#define  SSB_SPROM5_GPIOB_P3		0xFF00	/* Pin 3 */
-#define  SSB_SPROM5_GPIOB_P3_SHIFT	8
-
-/* SPROM Revision 8 */
-#define SSB_SPROM8_BOARDREV		0x0082	/* Board revision */
-#define SSB_SPROM8_BFLLO		0x0084	/* Board flags (bits 0-15) */
-#define SSB_SPROM8_BFLHI		0x0086	/* Board flags (bits 16-31) */
-#define SSB_SPROM8_BFL2LO		0x0088	/* Board flags (bits 32-47) */
-#define SSB_SPROM8_BFL2HI		0x008A	/* Board flags (bits 48-63) */
-#define SSB_SPROM8_IL0MAC		0x008C	/* 6 byte MAC address */
-#define SSB_SPROM8_CCODE		0x0092	/* 2 byte country code */
-#define SSB_SPROM8_GPIOA		0x0096	/*Gen. Purpose IO # 0 and 1 */
-#define  SSB_SPROM8_GPIOA_P0		0x00FF	/* Pin 0 */
-#define  SSB_SPROM8_GPIOA_P1		0xFF00	/* Pin 1 */
-#define  SSB_SPROM8_GPIOA_P1_SHIFT	8
-#define SSB_SPROM8_GPIOB		0x0098	/* Gen. Purpose IO # 2 and 3 */
-#define  SSB_SPROM8_GPIOB_P2		0x00FF	/* Pin 2 */
-#define  SSB_SPROM8_GPIOB_P3		0xFF00	/* Pin 3 */
-#define  SSB_SPROM8_GPIOB_P3_SHIFT	8
-#define SSB_SPROM8_ANTAVAIL		0x009C  /* Antenna available bitfields*/
-#define  SSB_SPROM8_ANTAVAIL_A		0xFF00	/* A-PHY bitfield */
-#define  SSB_SPROM8_ANTAVAIL_A_SHIFT	8
-#define  SSB_SPROM8_ANTAVAIL_BG		0x00FF	/* B-PHY and G-PHY bitfield */
-#define  SSB_SPROM8_ANTAVAIL_BG_SHIFT	0
-#define SSB_SPROM8_AGAIN01		0x009E	/* Antenna Gain (in dBm Q5.2) */
-#define  SSB_SPROM8_AGAIN0		0x00FF	/* Antenna 0 */
-#define  SSB_SPROM8_AGAIN0_SHIFT	0
-#define  SSB_SPROM8_AGAIN1		0xFF00	/* Antenna 1 */
-#define  SSB_SPROM8_AGAIN1_SHIFT	8
-#define SSB_SPROM8_AGAIN23		0x00A0
-#define  SSB_SPROM8_AGAIN2		0x00FF	/* Antenna 2 */
-#define  SSB_SPROM8_AGAIN2_SHIFT	0
-#define  SSB_SPROM8_AGAIN3		0xFF00	/* Antenna 3 */
-#define  SSB_SPROM8_AGAIN3_SHIFT	8
-#define SSB_SPROM8_RSSIPARM2G		0x00A4	/* RSSI params for 2GHz */
-#define  SSB_SPROM8_RSSISMF2G		0x000F
-#define  SSB_SPROM8_RSSISMC2G		0x00F0
-#define  SSB_SPROM8_RSSISMC2G_SHIFT	4
-#define  SSB_SPROM8_RSSISAV2G		0x0700
-#define  SSB_SPROM8_RSSISAV2G_SHIFT	8
-#define  SSB_SPROM8_BXA2G		0x1800
-#define  SSB_SPROM8_BXA2G_SHIFT		11
-#define SSB_SPROM8_RSSIPARM5G		0x00A6	/* RSSI params for 5GHz */
-#define  SSB_SPROM8_RSSISMF5G		0x000F
-#define  SSB_SPROM8_RSSISMC5G		0x00F0
-#define  SSB_SPROM8_RSSISMC5G_SHIFT	4
-#define  SSB_SPROM8_RSSISAV5G		0x0700
-#define  SSB_SPROM8_RSSISAV5G_SHIFT	8
-#define  SSB_SPROM8_BXA5G		0x1800
-#define  SSB_SPROM8_BXA5G_SHIFT		11
-#define SSB_SPROM8_TRI25G		0x00A8	/* TX isolation 2.4&5.3GHz */
-#define  SSB_SPROM8_TRI2G		0x00FF	/* TX isolation 2.4GHz */
-#define  SSB_SPROM8_TRI5G		0xFF00	/* TX isolation 5.3GHz */
-#define  SSB_SPROM8_TRI5G_SHIFT		8
-#define SSB_SPROM8_TRI5GHL		0x00AA	/* TX isolation 5.2/5.8GHz */
-#define  SSB_SPROM8_TRI5GL		0x00FF	/* TX isolation 5.2GHz */
-#define  SSB_SPROM8_TRI5GH		0xFF00	/* TX isolation 5.8GHz */
-#define  SSB_SPROM8_TRI5GH_SHIFT	8
-#define SSB_SPROM8_RXPO			0x00AC  /* RX power offsets */
-#define  SSB_SPROM8_RXPO2G		0x00FF	/* 2GHz RX power offset */
-#define  SSB_SPROM8_RXPO5G		0xFF00	/* 5GHz RX power offset */
-#define  SSB_SPROM8_RXPO5G_SHIFT	8
-#define SSB_SPROM8_FEM2G		0x00AE
-#define SSB_SPROM8_FEM5G		0x00B0
-#define  SSB_SROM8_FEM_TSSIPOS		0x0001
-#define  SSB_SROM8_FEM_TSSIPOS_SHIFT	0
-#define  SSB_SROM8_FEM_EXTPA_GAIN	0x0006
-#define  SSB_SROM8_FEM_EXTPA_GAIN_SHIFT	1
-#define  SSB_SROM8_FEM_PDET_RANGE	0x00F8
-#define  SSB_SROM8_FEM_PDET_RANGE_SHIFT	3
-#define  SSB_SROM8_FEM_TR_ISO		0x0700
-#define  SSB_SROM8_FEM_TR_ISO_SHIFT	8
-#define  SSB_SROM8_FEM_ANTSWLUT		0xF800
-#define  SSB_SROM8_FEM_ANTSWLUT_SHIFT	11
-#define SSB_SPROM8_THERMAL		0x00B2
-#define SSB_SPROM8_MPWR_RAWTS		0x00B4
-#define SSB_SPROM8_TS_SLP_OPT_CORRX	0x00B6
-#define SSB_SPROM8_FOC_HWIQ_IQSWP	0x00B8
-#define SSB_SPROM8_PHYCAL_TEMPDELTA	0x00BA
-
-/* There are 4 blocks with power info sharing the same layout */
-#define SSB_SROM8_PWR_INFO_CORE0	0x00C0
-#define SSB_SROM8_PWR_INFO_CORE1	0x00E0
-#define SSB_SROM8_PWR_INFO_CORE2	0x0100
-#define SSB_SROM8_PWR_INFO_CORE3	0x0120
-
-#define SSB_SROM8_2G_MAXP_ITSSI		0x00
-#define  SSB_SPROM8_2G_MAXP		0x00FF
-#define  SSB_SPROM8_2G_ITSSI		0xFF00
-#define  SSB_SPROM8_2G_ITSSI_SHIFT	8
-#define SSB_SROM8_2G_PA_0		0x02	/* 2GHz power amp settings */
-#define SSB_SROM8_2G_PA_1		0x04
-#define SSB_SROM8_2G_PA_2		0x06
-#define SSB_SROM8_5G_MAXP_ITSSI		0x08	/* 5GHz ITSSI and 5.3GHz Max Power */
-#define  SSB_SPROM8_5G_MAXP		0x00FF
-#define  SSB_SPROM8_5G_ITSSI		0xFF00
-#define  SSB_SPROM8_5G_ITSSI_SHIFT	8
-#define SSB_SPROM8_5GHL_MAXP		0x0A	/* 5.2GHz and 5.8GHz Max Power */
-#define  SSB_SPROM8_5GH_MAXP		0x00FF
-#define  SSB_SPROM8_5GL_MAXP		0xFF00
-#define  SSB_SPROM8_5GL_MAXP_SHIFT	8
-#define SSB_SROM8_5G_PA_0		0x0C	/* 5.3GHz power amp settings */
-#define SSB_SROM8_5G_PA_1		0x0E
-#define SSB_SROM8_5G_PA_2		0x10
-#define SSB_SROM8_5GL_PA_0		0x12	/* 5.2GHz power amp settings */
-#define SSB_SROM8_5GL_PA_1		0x14
-#define SSB_SROM8_5GL_PA_2		0x16
-#define SSB_SROM8_5GH_PA_0		0x18	/* 5.8GHz power amp settings */
-#define SSB_SROM8_5GH_PA_1		0x1A
-#define SSB_SROM8_5GH_PA_2		0x1C
-
-/* TODO: Make it deprecated */
-#define SSB_SPROM8_MAXP_BG		0x00C0  /* Max Power 2GHz in path 1 */
-#define  SSB_SPROM8_MAXP_BG_MASK	0x00FF  /* Mask for Max Power 2GHz */
-#define  SSB_SPROM8_ITSSI_BG		0xFF00	/* Mask for path 1 itssi_bg */
-#define  SSB_SPROM8_ITSSI_BG_SHIFT	8
-#define SSB_SPROM8_PA0B0		0x00C2	/* 2GHz power amp settings */
-#define SSB_SPROM8_PA0B1		0x00C4
-#define SSB_SPROM8_PA0B2		0x00C6
-#define SSB_SPROM8_MAXP_A		0x00C8  /* Max Power 5.3GHz */
-#define  SSB_SPROM8_MAXP_A_MASK		0x00FF  /* Mask for Max Power 5.3GHz */
-#define  SSB_SPROM8_ITSSI_A		0xFF00	/* Mask for path 1 itssi_a */
-#define  SSB_SPROM8_ITSSI_A_SHIFT	8
-#define SSB_SPROM8_MAXP_AHL		0x00CA  /* Max Power 5.2/5.8GHz */
-#define  SSB_SPROM8_MAXP_AH_MASK	0x00FF  /* Mask for Max Power 5.8GHz */
-#define  SSB_SPROM8_MAXP_AL_MASK	0xFF00  /* Mask for Max Power 5.2GHz */
-#define  SSB_SPROM8_MAXP_AL_SHIFT	8
-#define SSB_SPROM8_PA1B0		0x00CC	/* 5.3GHz power amp settings */
-#define SSB_SPROM8_PA1B1		0x00CE
-#define SSB_SPROM8_PA1B2		0x00D0
-#define SSB_SPROM8_PA1LOB0		0x00D2	/* 5.2GHz power amp settings */
-#define SSB_SPROM8_PA1LOB1		0x00D4
-#define SSB_SPROM8_PA1LOB2		0x00D6
-#define SSB_SPROM8_PA1HIB0		0x00D8	/* 5.8GHz power amp settings */
-#define SSB_SPROM8_PA1HIB1		0x00DA
-#define SSB_SPROM8_PA1HIB2		0x00DC
-
-#define SSB_SPROM8_CCK2GPO		0x0140	/* CCK power offset */
-#define SSB_SPROM8_OFDM2GPO		0x0142	/* 2.4GHz OFDM power offset */
-#define SSB_SPROM8_OFDM5GPO		0x0146	/* 5.3GHz OFDM power offset */
-#define SSB_SPROM8_OFDM5GLPO		0x014A	/* 5.2GHz OFDM power offset */
-#define SSB_SPROM8_OFDM5GHPO		0x014E	/* 5.8GHz OFDM power offset */
-
-/* Values for boardflags_lo read from SPROM */
-#define SSB_BFL_BTCOEXIST		0x0001	/* implements Bluetooth coexistance */
-#define SSB_BFL_PACTRL			0x0002	/* GPIO 9 controlling the PA */
-#define SSB_BFL_AIRLINEMODE		0x0004	/* implements GPIO 13 radio disable indication */
-#define SSB_BFL_RSSI			0x0008	/* software calculates nrssi slope. */
-#define SSB_BFL_ENETSPI			0x0010	/* has ephy roboswitch spi */
-#define SSB_BFL_XTAL_NOSLOW		0x0020	/* no slow clock available */
-#define SSB_BFL_CCKHIPWR		0x0040	/* can do high power CCK transmission */
-#define SSB_BFL_ENETADM			0x0080	/* has ADMtek switch */
-#define SSB_BFL_ENETVLAN		0x0100	/* can do vlan */
-#define SSB_BFL_AFTERBURNER		0x0200	/* supports Afterburner mode */
-#define SSB_BFL_NOPCI			0x0400	/* board leaves PCI floating */
-#define SSB_BFL_FEM			0x0800	/* supports the Front End Module */
-#define SSB_BFL_EXTLNA			0x1000	/* has an external LNA */
-#define SSB_BFL_HGPA			0x2000	/* had high gain PA */
-#define SSB_BFL_BTCMOD			0x4000	/* BFL_BTCOEXIST is given in alternate GPIOs */
-#define SSB_BFL_ALTIQ			0x8000	/* alternate I/Q settings */
-
-/* Values for boardflags_hi read from SPROM */
-#define SSB_BFH_NOPA			0x0001	/* has no PA */
-#define SSB_BFH_RSSIINV			0x0002	/* RSSI uses positive slope (not TSSI) */
-#define SSB_BFH_PAREF			0x0004	/* uses the PARef LDO */
-#define SSB_BFH_3TSWITCH		0x0008	/* uses a triple throw switch shared with bluetooth */
-#define SSB_BFH_PHASESHIFT		0x0010	/* can support phase shifter */
-#define SSB_BFH_BUCKBOOST		0x0020	/* has buck/booster */
-#define SSB_BFH_FEM_BT			0x0040	/* has FEM and switch to share antenna with bluetooth */
-
-/* Values for boardflags2_lo read from SPROM */
-#define SSB_BFL2_RXBB_INT_REG_DIS	0x0001	/* external RX BB regulator present */
-#define SSB_BFL2_APLL_WAR		0x0002	/* alternative A-band PLL settings implemented */
-#define SSB_BFL2_TXPWRCTRL_EN 		0x0004	/* permits enabling TX Power Control */
-#define SSB_BFL2_2X4_DIV		0x0008	/* 2x4 diversity switch */
-#define SSB_BFL2_5G_PWRGAIN		0x0010	/* supports 5G band power gain */
-#define SSB_BFL2_PCIEWAR_OVR		0x0020	/* overrides ASPM and Clkreq settings */
-#define SSB_BFL2_CAESERS_BRD		0x0040	/* is Caesers board (unused) */
-#define SSB_BFL2_BTC3WIRE		0x0080	/* used 3-wire bluetooth coexist */
-#define SSB_BFL2_SKWRKFEM_BRD		0x0100	/* 4321mcm93 uses Skyworks FEM */
-#define SSB_BFL2_SPUR_WAR		0x0200	/* has a workaround for clock-harmonic spurs */
-#define SSB_BFL2_GPLL_WAR		0x0400	/* altenative G-band PLL settings implemented */
-
-/* Values for SSB_SPROM1_BINF_CCODE */
-enum {
-	SSB_SPROM1CCODE_WORLD = 0,
-	SSB_SPROM1CCODE_THAILAND,
-	SSB_SPROM1CCODE_ISRAEL,
-	SSB_SPROM1CCODE_JORDAN,
-	SSB_SPROM1CCODE_CHINA,
-	SSB_SPROM1CCODE_JAPAN,
-	SSB_SPROM1CCODE_USA_CANADA_ANZ,
-	SSB_SPROM1CCODE_EUROPE,
-	SSB_SPROM1CCODE_USA_LOW,
-	SSB_SPROM1CCODE_JAPAN_HIGH,
-	SSB_SPROM1CCODE_ALL,
-	SSB_SPROM1CCODE_NONE,
-};
-
-/* Address-Match values and masks (SSB_ADMATCHxxx) */
-#define SSB_ADM_TYPE			0x00000003	/* Address type */
-#define  SSB_ADM_TYPE0			0
-#define  SSB_ADM_TYPE1			1
-#define  SSB_ADM_TYPE2			2
-#define SSB_ADM_AD64			0x00000004
-#define SSB_ADM_SZ0			0x000000F8	/* Type0 size */
-#define SSB_ADM_SZ0_SHIFT		3
-#define SSB_ADM_SZ1			0x000001F8	/* Type1 size */
-#define SSB_ADM_SZ1_SHIFT		3
-#define SSB_ADM_SZ2			0x000001F8	/* Type2 size */
-#define SSB_ADM_SZ2_SHIFT		3
-#define SSB_ADM_EN			0x00000400	/* Enable */
-#define SSB_ADM_NEG			0x00000800	/* Negative decode */
-#define SSB_ADM_BASE0			0xFFFFFF00	/* Type0 base address */
-#define SSB_ADM_BASE0_SHIFT		8
-#define SSB_ADM_BASE1			0xFFFFF000	/* Type1 base address for the core */
-#define SSB_ADM_BASE1_SHIFT		12
-#define SSB_ADM_BASE2			0xFFFF0000	/* Type2 base address for the core */
-#define SSB_ADM_BASE2_SHIFT		16
-
-
-#endif /* LINUX_SSB_REGS_H_ */