Moved, renamed, and deleted files

The original directory structure was scattered and unorganized.
Changes are basically to make it look like kernel structure.

6 files changed, 0 insertions, 1089 deletions

diff --git a/ANDROID_3.4.5/include/linux/bcma/bcma.h b/ANDROID_3.4.5/include/linux/bcma/bcma.h
deleted file mode 100644
index 5af9a075..00000000
--- a/ANDROID_3.4.5/include/linux/bcma/bcma.h
+++ /dev/null
@@ -1,307 +0,0 @@
-#ifndef LINUX_BCMA_H_
-#define LINUX_BCMA_H_
-
-#include <linux/pci.h>
-#include <linux/mod_devicetable.h>
-
-#include <linux/bcma/bcma_driver_chipcommon.h>
-#include <linux/bcma/bcma_driver_pci.h>
-#include <linux/bcma/bcma_driver_mips.h>
-#include <linux/ssb/ssb.h> /* SPROM sharing */
-
-#include "bcma_regs.h"
-
-struct bcma_device;
-struct bcma_bus;
-
-enum bcma_hosttype {
-	BCMA_HOSTTYPE_PCI,
-	BCMA_HOSTTYPE_SDIO,
-	BCMA_HOSTTYPE_SOC,
-};
-
-struct bcma_chipinfo {
-	u16 id;
-	u8 rev;
-	u8 pkg;
-};
-
-enum bcma_clkmode {
-	BCMA_CLKMODE_FAST,
-	BCMA_CLKMODE_DYNAMIC,
-};
-
-struct bcma_host_ops {
-	u8 (*read8)(struct bcma_device *core, u16 offset);
-	u16 (*read16)(struct bcma_device *core, u16 offset);
-	u32 (*read32)(struct bcma_device *core, u16 offset);
-	void (*write8)(struct bcma_device *core, u16 offset, u8 value);
-	void (*write16)(struct bcma_device *core, u16 offset, u16 value);
-	void (*write32)(struct bcma_device *core, u16 offset, u32 value);
-#ifdef CONFIG_BCMA_BLOCKIO
-	void (*block_read)(struct bcma_device *core, void *buffer,
-			   size_t count, u16 offset, u8 reg_width);
-	void (*block_write)(struct bcma_device *core, const void *buffer,
-			    size_t count, u16 offset, u8 reg_width);
-#endif
-	/* Agent ops */
-	u32 (*aread32)(struct bcma_device *core, u16 offset);
-	void (*awrite32)(struct bcma_device *core, u16 offset, u32 value);
-};
-
-/* Core manufacturers */
-#define BCMA_MANUF_ARM			0x43B
-#define BCMA_MANUF_MIPS			0x4A7
-#define BCMA_MANUF_BCM			0x4BF
-
-/* Core class values. */
-#define BCMA_CL_SIM			0x0
-#define BCMA_CL_EROM			0x1
-#define BCMA_CL_CORESIGHT		0x9
-#define BCMA_CL_VERIF			0xB
-#define BCMA_CL_OPTIMO			0xD
-#define BCMA_CL_GEN			0xE
-#define BCMA_CL_PRIMECELL		0xF
-
-/* Core-ID values. */
-#define BCMA_CORE_OOB_ROUTER		0x367	/* Out of band */
-#define BCMA_CORE_INVALID		0x700
-#define BCMA_CORE_CHIPCOMMON		0x800
-#define BCMA_CORE_ILINE20		0x801
-#define BCMA_CORE_SRAM			0x802
-#define BCMA_CORE_SDRAM			0x803
-#define BCMA_CORE_PCI			0x804
-#define BCMA_CORE_MIPS			0x805
-#define BCMA_CORE_ETHERNET		0x806
-#define BCMA_CORE_V90			0x807
-#define BCMA_CORE_USB11_HOSTDEV		0x808
-#define BCMA_CORE_ADSL			0x809
-#define BCMA_CORE_ILINE100		0x80A
-#define BCMA_CORE_IPSEC			0x80B
-#define BCMA_CORE_UTOPIA		0x80C
-#define BCMA_CORE_PCMCIA		0x80D
-#define BCMA_CORE_INTERNAL_MEM		0x80E
-#define BCMA_CORE_MEMC_SDRAM		0x80F
-#define BCMA_CORE_OFDM			0x810
-#define BCMA_CORE_EXTIF			0x811
-#define BCMA_CORE_80211			0x812
-#define BCMA_CORE_PHY_A			0x813
-#define BCMA_CORE_PHY_B			0x814
-#define BCMA_CORE_PHY_G			0x815
-#define BCMA_CORE_MIPS_3302		0x816
-#define BCMA_CORE_USB11_HOST		0x817
-#define BCMA_CORE_USB11_DEV		0x818
-#define BCMA_CORE_USB20_HOST		0x819
-#define BCMA_CORE_USB20_DEV		0x81A
-#define BCMA_CORE_SDIO_HOST		0x81B
-#define BCMA_CORE_ROBOSWITCH		0x81C
-#define BCMA_CORE_PARA_ATA		0x81D
-#define BCMA_CORE_SATA_XORDMA		0x81E
-#define BCMA_CORE_ETHERNET_GBIT		0x81F
-#define BCMA_CORE_PCIE			0x820
-#define BCMA_CORE_PHY_N			0x821
-#define BCMA_CORE_SRAM_CTL		0x822
-#define BCMA_CORE_MINI_MACPHY		0x823
-#define BCMA_CORE_ARM_1176		0x824
-#define BCMA_CORE_ARM_7TDMI		0x825
-#define BCMA_CORE_PHY_LP		0x826
-#define BCMA_CORE_PMU			0x827
-#define BCMA_CORE_PHY_SSN		0x828
-#define BCMA_CORE_SDIO_DEV		0x829
-#define BCMA_CORE_ARM_CM3		0x82A
-#define BCMA_CORE_PHY_HT		0x82B
-#define BCMA_CORE_MIPS_74K		0x82C
-#define BCMA_CORE_MAC_GBIT		0x82D
-#define BCMA_CORE_DDR12_MEM_CTL		0x82E
-#define BCMA_CORE_PCIE_RC		0x82F	/* PCIe Root Complex */
-#define BCMA_CORE_OCP_OCP_BRIDGE	0x830
-#define BCMA_CORE_SHARED_COMMON		0x831
-#define BCMA_CORE_OCP_AHB_BRIDGE	0x832
-#define BCMA_CORE_SPI_HOST		0x833
-#define BCMA_CORE_I2S			0x834
-#define BCMA_CORE_SDR_DDR1_MEM_CTL	0x835	/* SDR/DDR1 memory controller core */
-#define BCMA_CORE_SHIM			0x837	/* SHIM component in ubus/6362 */
-#define BCMA_CORE_DEFAULT		0xFFF
-
-#define BCMA_MAX_NR_CORES		16
-
-struct bcma_device {
-	struct bcma_bus *bus;
-	struct bcma_device_id id;
-
-	struct device dev;
-	struct device *dma_dev;
-
-	unsigned int irq;
-	bool dev_registered;
-
-	u8 core_index;
-	u8 core_unit;
-
-	u32 addr;
-	u32 wrap;
-
-	void __iomem *io_addr;
-	void __iomem *io_wrap;
-
-	void *drvdata;
-	struct list_head list;
-};
-
-static inline void *bcma_get_drvdata(struct bcma_device *core)
-{
-	return core->drvdata;
-}
-static inline void bcma_set_drvdata(struct bcma_device *core, void *drvdata)
-{
-	core->drvdata = drvdata;
-}
-
-struct bcma_driver {
-	const char *name;
-	const struct bcma_device_id *id_table;
-
-	int (*probe)(struct bcma_device *dev);
-	void (*remove)(struct bcma_device *dev);
-	int (*suspend)(struct bcma_device *dev);
-	int (*resume)(struct bcma_device *dev);
-	void (*shutdown)(struct bcma_device *dev);
-
-	struct device_driver drv;
-};
-extern
-int __bcma_driver_register(struct bcma_driver *drv, struct module *owner);
-#define bcma_driver_register(drv) \
-	__bcma_driver_register(drv, THIS_MODULE)
-
-extern void bcma_driver_unregister(struct bcma_driver *drv);
-
-/* Set a fallback SPROM.
- * See kdoc at the function definition for complete documentation. */
-extern int bcma_arch_register_fallback_sprom(
-		int (*sprom_callback)(struct bcma_bus *bus,
-		struct ssb_sprom *out));
-
-struct bcma_bus {
-	/* The MMIO area. */
-	void __iomem *mmio;
-
-	const struct bcma_host_ops *ops;
-
-	enum bcma_hosttype hosttype;
-	union {
-		/* Pointer to the PCI bus (only for BCMA_HOSTTYPE_PCI) */
-		struct pci_dev *host_pci;
-		/* Pointer to the SDIO device (only for BCMA_HOSTTYPE_SDIO) */
-		struct sdio_func *host_sdio;
-	};
-
-	struct bcma_chipinfo chipinfo;
-
-	struct bcma_device *mapped_core;
-	struct list_head cores;
-	u8 nr_cores;
-	u8 init_done:1;
-	u8 num;
-
-	struct bcma_drv_cc drv_cc;
-	struct bcma_drv_pci drv_pci;
-	struct bcma_drv_mips drv_mips;
-
-	/* We decided to share SPROM struct with SSB as long as we do not need
-	 * any hacks for BCMA. This simplifies drivers code. */
-	struct ssb_sprom sprom;
-};
-
-static inline u32 bcma_read8(struct bcma_device *core, u16 offset)
-{
-	return core->bus->ops->read8(core, offset);
-}
-static inline u32 bcma_read16(struct bcma_device *core, u16 offset)
-{
-	return core->bus->ops->read16(core, offset);
-}
-static inline u32 bcma_read32(struct bcma_device *core, u16 offset)
-{
-	return core->bus->ops->read32(core, offset);
-}
-static inline
-void bcma_write8(struct bcma_device *core, u16 offset, u32 value)
-{
-	core->bus->ops->write8(core, offset, value);
-}
-static inline
-void bcma_write16(struct bcma_device *core, u16 offset, u32 value)
-{
-	core->bus->ops->write16(core, offset, value);
-}
-static inline
-void bcma_write32(struct bcma_device *core, u16 offset, u32 value)
-{
-	core->bus->ops->write32(core, offset, value);
-}
-#ifdef CONFIG_BCMA_BLOCKIO
-static inline void bcma_block_read(struct bcma_device *core, void *buffer,
-				   size_t count, u16 offset, u8 reg_width)
-{
-	core->bus->ops->block_read(core, buffer, count, offset, reg_width);
-}
-static inline void bcma_block_write(struct bcma_device *core,
-				    const void *buffer, size_t count,
-				    u16 offset, u8 reg_width)
-{
-	core->bus->ops->block_write(core, buffer, count, offset, reg_width);
-}
-#endif
-static inline u32 bcma_aread32(struct bcma_device *core, u16 offset)
-{
-	return core->bus->ops->aread32(core, offset);
-}
-static inline
-void bcma_awrite32(struct bcma_device *core, u16 offset, u32 value)
-{
-	core->bus->ops->awrite32(core, offset, value);
-}
-
-static inline void bcma_mask32(struct bcma_device *cc, u16 offset, u32 mask)
-{
-	bcma_write32(cc, offset, bcma_read32(cc, offset) & mask);
-}
-static inline void bcma_set32(struct bcma_device *cc, u16 offset, u32 set)
-{
-	bcma_write32(cc, offset, bcma_read32(cc, offset) | set);
-}
-static inline void bcma_maskset32(struct bcma_device *cc,
-				  u16 offset, u32 mask, u32 set)
-{
-	bcma_write32(cc, offset, (bcma_read32(cc, offset) & mask) | set);
-}
-static inline void bcma_mask16(struct bcma_device *cc, u16 offset, u16 mask)
-{
-	bcma_write16(cc, offset, bcma_read16(cc, offset) & mask);
-}
-static inline void bcma_set16(struct bcma_device *cc, u16 offset, u16 set)
-{
-	bcma_write16(cc, offset, bcma_read16(cc, offset) | set);
-}
-static inline void bcma_maskset16(struct bcma_device *cc,
-				  u16 offset, u16 mask, u16 set)
-{
-	bcma_write16(cc, offset, (bcma_read16(cc, offset) & mask) | set);
-}
-
-extern struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid);
-extern bool bcma_core_is_enabled(struct bcma_device *core);
-extern void bcma_core_disable(struct bcma_device *core, u32 flags);
-extern int bcma_core_enable(struct bcma_device *core, u32 flags);
-extern void bcma_core_set_clockmode(struct bcma_device *core,
-				    enum bcma_clkmode clkmode);
-extern void bcma_core_pll_ctl(struct bcma_device *core, u32 req, u32 status,
-			      bool on);
-#define BCMA_DMA_TRANSLATION_MASK	0xC0000000
-#define  BCMA_DMA_TRANSLATION_NONE	0x00000000
-#define  BCMA_DMA_TRANSLATION_DMA32_CMT	0x40000000 /* Client Mode Translation for 32-bit DMA */
-#define  BCMA_DMA_TRANSLATION_DMA64_CMT	0x80000000 /* Client Mode Translation for 64-bit DMA */
-extern u32 bcma_core_dma_translation(struct bcma_device *core);
-
-#endif /* LINUX_BCMA_H_ */
diff --git a/ANDROID_3.4.5/include/linux/bcma/bcma_driver_chipcommon.h b/ANDROID_3.4.5/include/linux/bcma/bcma_driver_chipcommon.h
deleted file mode 100644
index 8bbfe31f..00000000
--- a/ANDROID_3.4.5/include/linux/bcma/bcma_driver_chipcommon.h
+++ /dev/null
@@ -1,415 +0,0 @@
-#ifndef LINUX_BCMA_DRIVER_CC_H_
-#define LINUX_BCMA_DRIVER_CC_H_
-
-/** ChipCommon core registers. **/
-#define BCMA_CC_ID			0x0000
-#define  BCMA_CC_ID_ID			0x0000FFFF
-#define  BCMA_CC_ID_ID_SHIFT		0
-#define  BCMA_CC_ID_REV			0x000F0000
-#define  BCMA_CC_ID_REV_SHIFT		16
-#define  BCMA_CC_ID_PKG			0x00F00000
-#define  BCMA_CC_ID_PKG_SHIFT		20
-#define  BCMA_CC_ID_NRCORES		0x0F000000
-#define  BCMA_CC_ID_NRCORES_SHIFT	24
-#define  BCMA_CC_ID_TYPE		0xF0000000
-#define  BCMA_CC_ID_TYPE_SHIFT		28
-#define BCMA_CC_CAP			0x0004		/* Capabilities */
-#define  BCMA_CC_CAP_NRUART		0x00000003	/* # of UARTs */
-#define  BCMA_CC_CAP_MIPSEB		0x00000004	/* MIPS in BigEndian Mode */
-#define  BCMA_CC_CAP_UARTCLK		0x00000018	/* UART clock select */
-#define   BCMA_CC_CAP_UARTCLK_INT	0x00000008	/* UARTs are driven by internal divided clock */
-#define  BCMA_CC_CAP_UARTGPIO		0x00000020	/* UARTs on GPIO 15-12 */
-#define  BCMA_CC_CAP_EXTBUS		0x000000C0	/* External buses present */
-#define  BCMA_CC_CAP_FLASHT		0x00000700	/* Flash Type */
-#define   BCMA_CC_FLASHT_NONE		0x00000000	/* No flash */
-#define   BCMA_CC_FLASHT_STSER		0x00000100	/* ST serial flash */
-#define   BCMA_CC_FLASHT_ATSER		0x00000200	/* Atmel serial flash */
-#define   BCMA_CC_FLASHT_NFLASH		0x00000200
-#define	  BCMA_CC_FLASHT_PARA		0x00000700	/* Parallel flash */
-#define  BCMA_CC_CAP_PLLT		0x00038000	/* PLL Type */
-#define   BCMA_PLLTYPE_NONE		0x00000000
-#define   BCMA_PLLTYPE_1		0x00010000	/* 48Mhz base, 3 dividers */
-#define   BCMA_PLLTYPE_2		0x00020000	/* 48Mhz, 4 dividers */
-#define   BCMA_PLLTYPE_3		0x00030000	/* 25Mhz, 2 dividers */
-#define   BCMA_PLLTYPE_4		0x00008000	/* 48Mhz, 4 dividers */
-#define   BCMA_PLLTYPE_5		0x00018000	/* 25Mhz, 4 dividers */
-#define   BCMA_PLLTYPE_6		0x00028000	/* 100/200 or 120/240 only */
-#define   BCMA_PLLTYPE_7		0x00038000	/* 25Mhz, 4 dividers */
-#define  BCMA_CC_CAP_PCTL		0x00040000	/* Power Control */
-#define  BCMA_CC_CAP_OTPS		0x00380000	/* OTP size */
-#define  BCMA_CC_CAP_OTPS_SHIFT		19
-#define  BCMA_CC_CAP_OTPS_BASE		5
-#define  BCMA_CC_CAP_JTAGM		0x00400000	/* JTAG master present */
-#define  BCMA_CC_CAP_BROM		0x00800000	/* Internal boot ROM active */
-#define  BCMA_CC_CAP_64BIT		0x08000000	/* 64-bit Backplane */
-#define  BCMA_CC_CAP_PMU		0x10000000	/* PMU available (rev >= 20) */
-#define  BCMA_CC_CAP_ECI		0x20000000	/* ECI available (rev >= 20) */
-#define  BCMA_CC_CAP_SPROM		0x40000000	/* SPROM present */
-#define BCMA_CC_CORECTL			0x0008
-#define  BCMA_CC_CORECTL_UARTCLK0	0x00000001	/* Drive UART with internal clock */
-#define	 BCMA_CC_CORECTL_SE		0x00000002	/* sync clk out enable (corerev >= 3) */
-#define  BCMA_CC_CORECTL_UARTCLKEN	0x00000008	/* UART clock enable (rev >= 21) */
-#define BCMA_CC_BIST			0x000C
-#define BCMA_CC_OTPS			0x0010		/* OTP status */
-#define	 BCMA_CC_OTPS_PROGFAIL		0x80000000
-#define	 BCMA_CC_OTPS_PROTECT		0x00000007
-#define	 BCMA_CC_OTPS_HW_PROTECT	0x00000001
-#define	 BCMA_CC_OTPS_SW_PROTECT	0x00000002
-#define	 BCMA_CC_OTPS_CID_PROTECT	0x00000004
-#define  BCMA_CC_OTPS_GU_PROG_IND	0x00000F00	/* General Use programmed indication */
-#define  BCMA_CC_OTPS_GU_PROG_IND_SHIFT	8
-#define  BCMA_CC_OTPS_GU_PROG_HW	0x00000100	/* HW region programmed */
-#define BCMA_CC_OTPC			0x0014		/* OTP control */
-#define	 BCMA_CC_OTPC_RECWAIT		0xFF000000
-#define	 BCMA_CC_OTPC_PROGWAIT		0x00FFFF00
-#define	 BCMA_CC_OTPC_PRW_SHIFT		8
-#define	 BCMA_CC_OTPC_MAXFAIL		0x00000038
-#define	 BCMA_CC_OTPC_VSEL		0x00000006
-#define	 BCMA_CC_OTPC_SELVL		0x00000001
-#define BCMA_CC_OTPP			0x0018		/* OTP prog */
-#define	 BCMA_CC_OTPP_COL		0x000000FF
-#define	 BCMA_CC_OTPP_ROW		0x0000FF00
-#define	 BCMA_CC_OTPP_ROW_SHIFT		8
-#define	 BCMA_CC_OTPP_READERR		0x10000000
-#define	 BCMA_CC_OTPP_VALUE		0x20000000
-#define	 BCMA_CC_OTPP_READ		0x40000000
-#define	 BCMA_CC_OTPP_START		0x80000000
-#define	 BCMA_CC_OTPP_BUSY		0x80000000
-#define BCMA_CC_OTPL			0x001C		/* OTP layout */
-#define  BCMA_CC_OTPL_GURGN_OFFSET	0x00000FFF	/* offset of general use region */
-#define BCMA_CC_IRQSTAT			0x0020
-#define BCMA_CC_IRQMASK			0x0024
-#define	 BCMA_CC_IRQ_GPIO		0x00000001	/* gpio intr */
-#define	 BCMA_CC_IRQ_EXT		0x00000002	/* ro: ext intr pin (corerev >= 3) */
-#define	 BCMA_CC_IRQ_WDRESET		0x80000000	/* watchdog reset occurred */
-#define BCMA_CC_CHIPCTL			0x0028		/* Rev >= 11 only */
-#define BCMA_CC_CHIPSTAT		0x002C		/* Rev >= 11 only */
-#define  BCMA_CC_CHIPST_4313_SPROM_PRESENT	1
-#define  BCMA_CC_CHIPST_4313_OTP_PRESENT	2
-#define  BCMA_CC_CHIPST_4331_SPROM_PRESENT	2
-#define  BCMA_CC_CHIPST_4331_OTP_PRESENT	4
-#define BCMA_CC_JCMD			0x0030		/* Rev >= 10 only */
-#define  BCMA_CC_JCMD_START		0x80000000
-#define  BCMA_CC_JCMD_BUSY		0x80000000
-#define  BCMA_CC_JCMD_PAUSE		0x40000000
-#define  BCMA_CC_JCMD0_ACC_MASK		0x0000F000
-#define  BCMA_CC_JCMD0_ACC_IRDR		0x00000000
-#define  BCMA_CC_JCMD0_ACC_DR		0x00001000
-#define  BCMA_CC_JCMD0_ACC_IR		0x00002000
-#define  BCMA_CC_JCMD0_ACC_RESET	0x00003000
-#define  BCMA_CC_JCMD0_ACC_IRPDR	0x00004000
-#define  BCMA_CC_JCMD0_ACC_PDR		0x00005000
-#define  BCMA_CC_JCMD0_IRW_MASK		0x00000F00
-#define  BCMA_CC_JCMD_ACC_MASK		0x000F0000	/* Changes for corerev 11 */
-#define  BCMA_CC_JCMD_ACC_IRDR		0x00000000
-#define  BCMA_CC_JCMD_ACC_DR		0x00010000
-#define  BCMA_CC_JCMD_ACC_IR		0x00020000
-#define  BCMA_CC_JCMD_ACC_RESET		0x00030000
-#define  BCMA_CC_JCMD_ACC_IRPDR		0x00040000
-#define  BCMA_CC_JCMD_ACC_PDR		0x00050000
-#define  BCMA_CC_JCMD_IRW_MASK		0x00001F00
-#define  BCMA_CC_JCMD_IRW_SHIFT		8
-#define  BCMA_CC_JCMD_DRW_MASK		0x0000003F
-#define BCMA_CC_JIR			0x0034		/* Rev >= 10 only */
-#define BCMA_CC_JDR			0x0038		/* Rev >= 10 only */
-#define BCMA_CC_JCTL			0x003C		/* Rev >= 10 only */
-#define  BCMA_CC_JCTL_FORCE_CLK		4		/* Force clock */
-#define  BCMA_CC_JCTL_EXT_EN		2		/* Enable external targets */
-#define  BCMA_CC_JCTL_EN		1		/* Enable Jtag master */
-#define BCMA_CC_FLASHCTL		0x0040
-#define  BCMA_CC_FLASHCTL_START		0x80000000
-#define  BCMA_CC_FLASHCTL_BUSY		BCMA_CC_FLASHCTL_START
-#define BCMA_CC_FLASHADDR		0x0044
-#define BCMA_CC_FLASHDATA		0x0048
-#define BCMA_CC_BCAST_ADDR		0x0050
-#define BCMA_CC_BCAST_DATA		0x0054
-#define BCMA_CC_GPIOPULLUP		0x0058		/* Rev >= 20 only */
-#define BCMA_CC_GPIOPULLDOWN		0x005C		/* Rev >= 20 only */
-#define BCMA_CC_GPIOIN			0x0060
-#define BCMA_CC_GPIOOUT			0x0064
-#define BCMA_CC_GPIOOUTEN		0x0068
-#define BCMA_CC_GPIOCTL			0x006C
-#define BCMA_CC_GPIOPOL			0x0070
-#define BCMA_CC_GPIOIRQ			0x0074
-#define BCMA_CC_WATCHDOG		0x0080
-#define BCMA_CC_GPIOTIMER		0x0088		/* LED powersave (corerev >= 16) */
-#define  BCMA_CC_GPIOTIMER_OFFTIME	0x0000FFFF
-#define  BCMA_CC_GPIOTIMER_OFFTIME_SHIFT	0
-#define  BCMA_CC_GPIOTIMER_ONTIME	0xFFFF0000
-#define  BCMA_CC_GPIOTIMER_ONTIME_SHIFT	16
-#define BCMA_CC_GPIOTOUTM		0x008C		/* LED powersave (corerev >= 16) */
-#define BCMA_CC_CLOCK_N			0x0090
-#define BCMA_CC_CLOCK_SB		0x0094
-#define BCMA_CC_CLOCK_PCI		0x0098
-#define BCMA_CC_CLOCK_M2		0x009C
-#define BCMA_CC_CLOCK_MIPS		0x00A0
-#define BCMA_CC_CLKDIV			0x00A4		/* Rev >= 3 only */
-#define	 BCMA_CC_CLKDIV_SFLASH		0x0F000000
-#define	 BCMA_CC_CLKDIV_SFLASH_SHIFT	24
-#define	 BCMA_CC_CLKDIV_OTP		0x000F0000
-#define	 BCMA_CC_CLKDIV_OTP_SHIFT	16
-#define	 BCMA_CC_CLKDIV_JTAG		0x00000F00
-#define	 BCMA_CC_CLKDIV_JTAG_SHIFT	8
-#define	 BCMA_CC_CLKDIV_UART		0x000000FF
-#define BCMA_CC_CAP_EXT			0x00AC		/* Capabilities */
-#define BCMA_CC_PLLONDELAY		0x00B0		/* Rev >= 4 only */
-#define BCMA_CC_FREFSELDELAY		0x00B4		/* Rev >= 4 only */
-#define BCMA_CC_SLOWCLKCTL		0x00B8		/* 6 <= Rev <= 9 only */
-#define  BCMA_CC_SLOWCLKCTL_SRC		0x00000007	/* slow clock source mask */
-#define	  BCMA_CC_SLOWCLKCTL_SRC_LPO	0x00000000	/* source of slow clock is LPO */
-#define   BCMA_CC_SLOWCLKCTL_SRC_XTAL	0x00000001	/* source of slow clock is crystal */
-#define	  BCMA_CC_SLOECLKCTL_SRC_PCI	0x00000002	/* source of slow clock is PCI */
-#define  BCMA_CC_SLOWCLKCTL_LPOFREQ	0x00000200	/* LPOFreqSel, 1: 160Khz, 0: 32KHz */
-#define  BCMA_CC_SLOWCLKCTL_LPOPD	0x00000400	/* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
-#define  BCMA_CC_SLOWCLKCTL_FSLOW	0x00000800	/* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
-#define  BCMA_CC_SLOWCLKCTL_IPLL	0x00001000	/* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */
-#define  BCMA_CC_SLOWCLKCTL_ENXTAL	0x00002000	/* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */
-#define  BCMA_CC_SLOWCLKCTL_XTALPU	0x00004000	/* XtalPU (RO), 1/0: crystal running/disabled */
-#define  BCMA_CC_SLOWCLKCTL_CLKDIV	0xFFFF0000	/* ClockDivider (SlowClk = 1/(4+divisor)) */
-#define  BCMA_CC_SLOWCLKCTL_CLKDIV_SHIFT	16
-#define BCMA_CC_SYSCLKCTL		0x00C0		/* Rev >= 3 only */
-#define	 BCMA_CC_SYSCLKCTL_IDLPEN	0x00000001	/* ILPen: Enable Idle Low Power */
-#define	 BCMA_CC_SYSCLKCTL_ALPEN	0x00000002	/* ALPen: Enable Active Low Power */
-#define	 BCMA_CC_SYSCLKCTL_PLLEN	0x00000004	/* ForcePLLOn */
-#define	 BCMA_CC_SYSCLKCTL_FORCEALP	0x00000008	/* Force ALP (or HT if ALPen is not set */
-#define	 BCMA_CC_SYSCLKCTL_FORCEHT	0x00000010	/* Force HT */
-#define  BCMA_CC_SYSCLKCTL_CLKDIV	0xFFFF0000	/* ClkDiv  (ILP = 1/(4+divisor)) */
-#define  BCMA_CC_SYSCLKCTL_CLKDIV_SHIFT	16
-#define BCMA_CC_CLKSTSTR		0x00C4		/* Rev >= 3 only */
-#define BCMA_CC_EROM			0x00FC
-#define BCMA_CC_PCMCIA_CFG		0x0100
-#define BCMA_CC_PCMCIA_MEMWAIT		0x0104
-#define BCMA_CC_PCMCIA_ATTRWAIT		0x0108
-#define BCMA_CC_PCMCIA_IOWAIT		0x010C
-#define BCMA_CC_IDE_CFG			0x0110
-#define BCMA_CC_IDE_MEMWAIT		0x0114
-#define BCMA_CC_IDE_ATTRWAIT		0x0118
-#define BCMA_CC_IDE_IOWAIT		0x011C
-#define BCMA_CC_PROG_CFG		0x0120
-#define BCMA_CC_PROG_WAITCNT		0x0124
-#define BCMA_CC_FLASH_CFG		0x0128
-#define  BCMA_CC_FLASH_CFG_DS		0x0010	/* Data size, 0=8bit, 1=16bit */
-#define BCMA_CC_FLASH_WAITCNT		0x012C
-#define BCMA_CC_SROM_CONTROL		0x0190
-#define  BCMA_CC_SROM_CONTROL_START	0x80000000
-#define  BCMA_CC_SROM_CONTROL_BUSY	0x80000000
-#define  BCMA_CC_SROM_CONTROL_OPCODE	0x60000000
-#define  BCMA_CC_SROM_CONTROL_OP_READ	0x00000000
-#define  BCMA_CC_SROM_CONTROL_OP_WRITE	0x20000000
-#define  BCMA_CC_SROM_CONTROL_OP_WRDIS	0x40000000
-#define  BCMA_CC_SROM_CONTROL_OP_WREN	0x60000000
-#define  BCMA_CC_SROM_CONTROL_OTPSEL	0x00000010
-#define  BCMA_CC_SROM_CONTROL_LOCK	0x00000008
-#define  BCMA_CC_SROM_CONTROL_SIZE_MASK	0x00000006
-#define  BCMA_CC_SROM_CONTROL_SIZE_1K	0x00000000
-#define  BCMA_CC_SROM_CONTROL_SIZE_4K	0x00000002
-#define  BCMA_CC_SROM_CONTROL_SIZE_16K	0x00000004
-#define  BCMA_CC_SROM_CONTROL_SIZE_SHIFT	1
-#define  BCMA_CC_SROM_CONTROL_PRESENT	0x00000001
-/* 0x1E0 is defined as shared BCMA_CLKCTLST */
-#define BCMA_CC_HW_WORKAROUND		0x01E4 /* Hardware workaround (rev >= 20) */
-#define BCMA_CC_UART0_DATA		0x0300
-#define BCMA_CC_UART0_IMR		0x0304
-#define BCMA_CC_UART0_FCR		0x0308
-#define BCMA_CC_UART0_LCR		0x030C
-#define BCMA_CC_UART0_MCR		0x0310
-#define BCMA_CC_UART0_LSR		0x0314
-#define BCMA_CC_UART0_MSR		0x0318
-#define BCMA_CC_UART0_SCRATCH		0x031C
-#define BCMA_CC_UART1_DATA		0x0400
-#define BCMA_CC_UART1_IMR		0x0404
-#define BCMA_CC_UART1_FCR		0x0408
-#define BCMA_CC_UART1_LCR		0x040C
-#define BCMA_CC_UART1_MCR		0x0410
-#define BCMA_CC_UART1_LSR		0x0414
-#define BCMA_CC_UART1_MSR		0x0418
-#define BCMA_CC_UART1_SCRATCH		0x041C
-/* PMU registers (rev >= 20) */
-#define BCMA_CC_PMU_CTL			0x0600 /* PMU control */
-#define  BCMA_CC_PMU_CTL_ILP_DIV	0xFFFF0000 /* ILP div mask */
-#define  BCMA_CC_PMU_CTL_ILP_DIV_SHIFT	16
-#define  BCMA_CC_PMU_CTL_PLL_UPD	0x00000400
-#define  BCMA_CC_PMU_CTL_NOILPONW	0x00000200 /* No ILP on wait */
-#define  BCMA_CC_PMU_CTL_HTREQEN	0x00000100 /* HT req enable */
-#define  BCMA_CC_PMU_CTL_ALPREQEN	0x00000080 /* ALP req enable */
-#define  BCMA_CC_PMU_CTL_XTALFREQ	0x0000007C /* Crystal freq */
-#define  BCMA_CC_PMU_CTL_XTALFREQ_SHIFT	2
-#define  BCMA_CC_PMU_CTL_ILPDIVEN	0x00000002 /* ILP div enable */
-#define  BCMA_CC_PMU_CTL_LPOSEL		0x00000001 /* LPO sel */
-#define BCMA_CC_PMU_CAP			0x0604 /* PMU capabilities */
-#define  BCMA_CC_PMU_CAP_REVISION	0x000000FF /* Revision mask */
-#define BCMA_CC_PMU_STAT		0x0608 /* PMU status */
-#define  BCMA_CC_PMU_STAT_INTPEND	0x00000040 /* Interrupt pending */
-#define  BCMA_CC_PMU_STAT_SBCLKST	0x00000030 /* Backplane clock status? */
-#define  BCMA_CC_PMU_STAT_HAVEALP	0x00000008 /* ALP available */
-#define  BCMA_CC_PMU_STAT_HAVEHT	0x00000004 /* HT available */
-#define  BCMA_CC_PMU_STAT_RESINIT	0x00000003 /* Res init */
-#define BCMA_CC_PMU_RES_STAT		0x060C /* PMU res status */
-#define BCMA_CC_PMU_RES_PEND		0x0610 /* PMU res pending */
-#define BCMA_CC_PMU_TIMER		0x0614 /* PMU timer */
-#define BCMA_CC_PMU_MINRES_MSK		0x0618 /* PMU min res mask */
-#define BCMA_CC_PMU_MAXRES_MSK		0x061C /* PMU max res mask */
-#define BCMA_CC_PMU_RES_TABSEL		0x0620 /* PMU res table sel */
-#define BCMA_CC_PMU_RES_DEPMSK		0x0624 /* PMU res dep mask */
-#define BCMA_CC_PMU_RES_UPDNTM		0x0628 /* PMU res updown timer */
-#define BCMA_CC_PMU_RES_TIMER		0x062C /* PMU res timer */
-#define BCMA_CC_PMU_CLKSTRETCH		0x0630 /* PMU clockstretch */
-#define BCMA_CC_PMU_WATCHDOG		0x0634 /* PMU watchdog */
-#define BCMA_CC_PMU_RES_REQTS		0x0640 /* PMU res req timer sel */
-#define BCMA_CC_PMU_RES_REQT		0x0644 /* PMU res req timer */
-#define BCMA_CC_PMU_RES_REQM		0x0648 /* PMU res req mask */
-#define BCMA_CC_CHIPCTL_ADDR		0x0650
-#define BCMA_CC_CHIPCTL_DATA		0x0654
-#define BCMA_CC_REGCTL_ADDR		0x0658
-#define BCMA_CC_REGCTL_DATA		0x065C
-#define BCMA_CC_PLLCTL_ADDR		0x0660
-#define BCMA_CC_PLLCTL_DATA		0x0664
-#define BCMA_CC_SPROM			0x0800 /* SPROM beginning */
-
-/* Divider allocation in 4716/47162/5356 */
-#define BCMA_CC_PMU5_MAINPLL_CPU	1
-#define BCMA_CC_PMU5_MAINPLL_MEM	2
-#define BCMA_CC_PMU5_MAINPLL_SSB	3
-
-/* PLL usage in 4716/47162 */
-#define BCMA_CC_PMU4716_MAINPLL_PLL0	12
-
-/* PLL usage in 5356/5357 */
-#define BCMA_CC_PMU5356_MAINPLL_PLL0	0
-#define BCMA_CC_PMU5357_MAINPLL_PLL0	0
-
-/* 4706 PMU */
-#define BCMA_CC_PMU4706_MAINPLL_PLL0	0
-
-/* ALP clock on pre-PMU chips */
-#define BCMA_CC_PMU_ALP_CLOCK		20000000
-/* HT clock for systems with PMU-enabled chipcommon */
-#define BCMA_CC_PMU_HT_CLOCK		80000000
-
-/* PMU rev 5 (& 6) */
-#define BCMA_CC_PPL_P1P2_OFF		0
-#define BCMA_CC_PPL_P1_MASK		0x0f000000
-#define BCMA_CC_PPL_P1_SHIFT		24
-#define BCMA_CC_PPL_P2_MASK		0x00f00000
-#define BCMA_CC_PPL_P2_SHIFT		20
-#define BCMA_CC_PPL_M14_OFF		1
-#define BCMA_CC_PPL_MDIV_MASK		0x000000ff
-#define BCMA_CC_PPL_MDIV_WIDTH		8
-#define BCMA_CC_PPL_NM5_OFF		2
-#define BCMA_CC_PPL_NDIV_MASK		0xfff00000
-#define BCMA_CC_PPL_NDIV_SHIFT		20
-#define BCMA_CC_PPL_FMAB_OFF		3
-#define BCMA_CC_PPL_MRAT_MASK		0xf0000000
-#define BCMA_CC_PPL_MRAT_SHIFT		28
-#define BCMA_CC_PPL_ABRAT_MASK		0x08000000
-#define BCMA_CC_PPL_ABRAT_SHIFT		27
-#define BCMA_CC_PPL_FDIV_MASK		0x07ffffff
-#define BCMA_CC_PPL_PLLCTL_OFF		4
-#define BCMA_CC_PPL_PCHI_OFF		5
-#define BCMA_CC_PPL_PCHI_MASK		0x0000003f
-
-/* BCM4331 ChipControl numbers. */
-#define BCMA_CHIPCTL_4331_BT_COEXIST		BIT(0)	/* 0 disable */
-#define BCMA_CHIPCTL_4331_SECI			BIT(1)	/* 0 SECI is disabled (JATG functional) */
-#define BCMA_CHIPCTL_4331_EXT_LNA		BIT(2)	/* 0 disable */
-#define BCMA_CHIPCTL_4331_SPROM_GPIO13_15	BIT(3)	/* sprom/gpio13-15 mux */
-#define BCMA_CHIPCTL_4331_EXTPA_EN		BIT(4)	/* 0 ext pa disable, 1 ext pa enabled */
-#define BCMA_CHIPCTL_4331_GPIOCLK_ON_SPROMCS	BIT(5)	/* set drive out GPIO_CLK on sprom_cs pin */
-#define BCMA_CHIPCTL_4331_PCIE_MDIO_ON_SPROMCS	BIT(6)	/* use sprom_cs pin as PCIE mdio interface */
-#define BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5	BIT(7)	/* aband extpa will be at gpio2/5 and sprom_dout */
-#define BCMA_CHIPCTL_4331_OVR_PIPEAUXCLKEN	BIT(8)	/* override core control on pipe_AuxClkEnable */
-#define BCMA_CHIPCTL_4331_OVR_PIPEAUXPWRDOWN	BIT(9)	/* override core control on pipe_AuxPowerDown */
-#define BCMA_CHIPCTL_4331_PCIE_AUXCLKEN		BIT(10)	/* pcie_auxclkenable */
-#define BCMA_CHIPCTL_4331_PCIE_PIPE_PLLDOWN	BIT(11)	/* pcie_pipe_pllpowerdown */
-#define BCMA_CHIPCTL_4331_BT_SHD0_ON_GPIO4	BIT(16)	/* enable bt_shd0 at gpio4 */
-#define BCMA_CHIPCTL_4331_BT_SHD1_ON_GPIO5	BIT(17)	/* enable bt_shd1 at gpio5 */
-
-/* Data for the PMU, if available.
- * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
- */
-struct bcma_chipcommon_pmu {
-	u8 rev;			/* PMU revision */
-	u32 crystalfreq;	/* The active crystal frequency (in kHz) */
-};
-
-#ifdef CONFIG_BCMA_DRIVER_MIPS
-struct bcma_pflash {
-	u8 buswidth;
-	u32 window;
-	u32 window_size;
-};
-
-struct bcma_serial_port {
-	void *regs;
-	unsigned long clockspeed;
-	unsigned int irq;
-	unsigned int baud_base;
-	unsigned int reg_shift;
-};
-#endif /* CONFIG_BCMA_DRIVER_MIPS */
-
-struct bcma_drv_cc {
-	struct bcma_device *core;
-	u32 status;
-	u32 capabilities;
-	u32 capabilities_ext;
-	u8 setup_done:1;
-	/* Fast Powerup Delay constant */
-	u16 fast_pwrup_delay;
-	struct bcma_chipcommon_pmu pmu;
-#ifdef CONFIG_BCMA_DRIVER_MIPS
-	struct bcma_pflash pflash;
-
-	int nr_serial_ports;
-	struct bcma_serial_port serial_ports[4];
-#endif /* CONFIG_BCMA_DRIVER_MIPS */
-};
-
-/* Register access */
-#define bcma_cc_read32(cc, offset) \
-	bcma_read32((cc)->core, offset)
-#define bcma_cc_write32(cc, offset, val) \
-	bcma_write32((cc)->core, offset, val)
-
-#define bcma_cc_mask32(cc, offset, mask) \
-	bcma_cc_write32(cc, offset, bcma_cc_read32(cc, offset) & (mask))
-#define bcma_cc_set32(cc, offset, set) \
-	bcma_cc_write32(cc, offset, bcma_cc_read32(cc, offset) | (set))
-#define bcma_cc_maskset32(cc, offset, mask, set) \
-	bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
-
-extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);
-
-extern void bcma_chipco_suspend(struct bcma_drv_cc *cc);
-extern void bcma_chipco_resume(struct bcma_drv_cc *cc);
-
-void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable);
-
-extern void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc,
-					  u32 ticks);
-
-void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
-
-u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask);
-
-/* Chipcommon GPIO pin access. */
-u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask);
-u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value);
-u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value);
-u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value);
-u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value);
-u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value);
-
-/* PMU support */
-extern void bcma_pmu_init(struct bcma_drv_cc *cc);
-
-extern void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset,
-				  u32 value);
-extern void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset,
-				    u32 mask, u32 set);
-extern void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
-					u32 offset, u32 mask, u32 set);
-extern void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc,
-				       u32 offset, u32 mask, u32 set);
-
-#endif /* LINUX_BCMA_DRIVER_CC_H_ */
diff --git a/ANDROID_3.4.5/include/linux/bcma/bcma_driver_mips.h b/ANDROID_3.4.5/include/linux/bcma/bcma_driver_mips.h
deleted file mode 100644
index c0043645..00000000
--- a/ANDROID_3.4.5/include/linux/bcma/bcma_driver_mips.h
+++ /dev/null
@@ -1,51 +0,0 @@
-#ifndef LINUX_BCMA_DRIVER_MIPS_H_
-#define LINUX_BCMA_DRIVER_MIPS_H_
-
-#define BCMA_MIPS_IPSFLAG		0x0F08
-/* which sbflags get routed to mips interrupt 1 */
-#define  BCMA_MIPS_IPSFLAG_IRQ1		0x0000003F
-#define  BCMA_MIPS_IPSFLAG_IRQ1_SHIFT	0
-/* which sbflags get routed to mips interrupt 2 */
-#define  BCMA_MIPS_IPSFLAG_IRQ2		0x00003F00
-#define  BCMA_MIPS_IPSFLAG_IRQ2_SHIFT	8
-/* which sbflags get routed to mips interrupt 3 */
-#define  BCMA_MIPS_IPSFLAG_IRQ3		0x003F0000
-#define  BCMA_MIPS_IPSFLAG_IRQ3_SHIFT	16
-/* which sbflags get routed to mips interrupt 4 */
-#define  BCMA_MIPS_IPSFLAG_IRQ4		0x3F000000
-#define  BCMA_MIPS_IPSFLAG_IRQ4_SHIFT	24
-
-/* MIPS 74K core registers */
-#define BCMA_MIPS_MIPS74K_CORECTL	0x0000
-#define BCMA_MIPS_MIPS74K_EXCEPTBASE	0x0004
-#define BCMA_MIPS_MIPS74K_BIST		0x000C
-#define BCMA_MIPS_MIPS74K_INTMASK_INT0	0x0014
-#define BCMA_MIPS_MIPS74K_INTMASK(int) \
-	((int) * 4 + BCMA_MIPS_MIPS74K_INTMASK_INT0)
-#define BCMA_MIPS_MIPS74K_NMIMASK	0x002C
-#define BCMA_MIPS_MIPS74K_GPIOSEL	0x0040
-#define BCMA_MIPS_MIPS74K_GPIOOUT	0x0044
-#define BCMA_MIPS_MIPS74K_GPIOEN	0x0048
-#define BCMA_MIPS_MIPS74K_CLKCTLST	0x01E0
-
-#define BCMA_MIPS_OOBSELOUTA30		0x100
-
-struct bcma_device;
-
-struct bcma_drv_mips {
-	struct bcma_device *core;
-	u8 setup_done:1;
-	unsigned int assigned_irqs;
-};
-
-#ifdef CONFIG_BCMA_DRIVER_MIPS
-extern void bcma_core_mips_init(struct bcma_drv_mips *mcore);
-#else
-static inline void bcma_core_mips_init(struct bcma_drv_mips *mcore) { }
-#endif
-
-extern u32 bcma_cpu_clock(struct bcma_drv_mips *mcore);
-
-extern unsigned int bcma_core_mips_irq(struct bcma_device *dev);
-
-#endif /* LINUX_BCMA_DRIVER_MIPS_H_ */
diff --git a/ANDROID_3.4.5/include/linux/bcma/bcma_driver_pci.h b/ANDROID_3.4.5/include/linux/bcma/bcma_driver_pci.h
deleted file mode 100644
index 46c71e27..00000000
--- a/ANDROID_3.4.5/include/linux/bcma/bcma_driver_pci.h
+++ /dev/null
@@ -1,214 +0,0 @@
-#ifndef LINUX_BCMA_DRIVER_PCI_H_
-#define LINUX_BCMA_DRIVER_PCI_H_
-
-#include <linux/types.h>
-
-struct pci_dev;
-
-/** PCI core registers. **/
-#define BCMA_CORE_PCI_CTL			0x0000	/* PCI Control */
-#define  BCMA_CORE_PCI_CTL_RST_OE		0x00000001 /* PCI_RESET Output Enable */
-#define  BCMA_CORE_PCI_CTL_RST			0x00000002 /* PCI_RESET driven out to pin */
-#define  BCMA_CORE_PCI_CTL_CLK_OE		0x00000004 /* Clock gate Output Enable */
-#define  BCMA_CORE_PCI_CTL_CLK			0x00000008 /* Gate for clock driven out to pin */
-#define BCMA_CORE_PCI_ARBCTL			0x0010	/* PCI Arbiter Control */
-#define  BCMA_CORE_PCI_ARBCTL_INTERN		0x00000001 /* Use internal arbiter */
-#define  BCMA_CORE_PCI_ARBCTL_EXTERN		0x00000002 /* Use external arbiter */
-#define  BCMA_CORE_PCI_ARBCTL_PARKID		0x00000006 /* Mask, selects which agent is parked on an idle bus */
-#define   BCMA_CORE_PCI_ARBCTL_PARKID_LAST	0x00000000 /* Last requestor */
-#define   BCMA_CORE_PCI_ARBCTL_PARKID_4710	0x00000002 /* 4710 */
-#define   BCMA_CORE_PCI_ARBCTL_PARKID_EXT0	0x00000004 /* External requestor 0 */
-#define   BCMA_CORE_PCI_ARBCTL_PARKID_EXT1	0x00000006 /* External requestor 1 */
-#define BCMA_CORE_PCI_ISTAT			0x0020	/* Interrupt status */
-#define  BCMA_CORE_PCI_ISTAT_INTA		0x00000001 /* PCI INTA# */
-#define  BCMA_CORE_PCI_ISTAT_INTB		0x00000002 /* PCI INTB# */
-#define  BCMA_CORE_PCI_ISTAT_SERR		0x00000004 /* PCI SERR# (write to clear) */
-#define  BCMA_CORE_PCI_ISTAT_PERR		0x00000008 /* PCI PERR# (write to clear) */
-#define  BCMA_CORE_PCI_ISTAT_PME		0x00000010 /* PCI PME# */
-#define BCMA_CORE_PCI_IMASK			0x0024	/* Interrupt mask */
-#define  BCMA_CORE_PCI_IMASK_INTA		0x00000001 /* PCI INTA# */
-#define  BCMA_CORE_PCI_IMASK_INTB		0x00000002 /* PCI INTB# */
-#define  BCMA_CORE_PCI_IMASK_SERR		0x00000004 /* PCI SERR# */
-#define  BCMA_CORE_PCI_IMASK_PERR		0x00000008 /* PCI PERR# */
-#define  BCMA_CORE_PCI_IMASK_PME		0x00000010 /* PCI PME# */
-#define BCMA_CORE_PCI_MBOX			0x0028	/* Backplane to PCI Mailbox */
-#define  BCMA_CORE_PCI_MBOX_F0_0		0x00000100 /* PCI function 0, INT 0 */
-#define  BCMA_CORE_PCI_MBOX_F0_1		0x00000200 /* PCI function 0, INT 1 */
-#define  BCMA_CORE_PCI_MBOX_F1_0		0x00000400 /* PCI function 1, INT 0 */
-#define  BCMA_CORE_PCI_MBOX_F1_1		0x00000800 /* PCI function 1, INT 1 */
-#define  BCMA_CORE_PCI_MBOX_F2_0		0x00001000 /* PCI function 2, INT 0 */
-#define  BCMA_CORE_PCI_MBOX_F2_1		0x00002000 /* PCI function 2, INT 1 */
-#define  BCMA_CORE_PCI_MBOX_F3_0		0x00004000 /* PCI function 3, INT 0 */
-#define  BCMA_CORE_PCI_MBOX_F3_1		0x00008000 /* PCI function 3, INT 1 */
-#define BCMA_CORE_PCI_BCAST_ADDR		0x0050	/* Backplane Broadcast Address */
-#define  BCMA_CORE_PCI_BCAST_ADDR_MASK		0x000000FF
-#define BCMA_CORE_PCI_BCAST_DATA		0x0054	/* Backplane Broadcast Data */
-#define BCMA_CORE_PCI_GPIO_IN			0x0060	/* rev >= 2 only */
-#define BCMA_CORE_PCI_GPIO_OUT			0x0064	/* rev >= 2 only */
-#define BCMA_CORE_PCI_GPIO_ENABLE		0x0068	/* rev >= 2 only */
-#define BCMA_CORE_PCI_GPIO_CTL			0x006C	/* rev >= 2 only */
-#define BCMA_CORE_PCI_SBTOPCI0			0x0100	/* Backplane to PCI translation 0 (sbtopci0) */
-#define  BCMA_CORE_PCI_SBTOPCI0_MASK		0xFC000000
-#define BCMA_CORE_PCI_SBTOPCI1			0x0104	/* Backplane to PCI translation 1 (sbtopci1) */
-#define  BCMA_CORE_PCI_SBTOPCI1_MASK		0xFC000000
-#define BCMA_CORE_PCI_SBTOPCI2			0x0108	/* Backplane to PCI translation 2 (sbtopci2) */
-#define  BCMA_CORE_PCI_SBTOPCI2_MASK		0xC0000000
-#define BCMA_CORE_PCI_CONFIG_ADDR		0x0120	/* pcie config space access */
-#define BCMA_CORE_PCI_CONFIG_DATA		0x0124	/* pcie config space access */
-#define BCMA_CORE_PCI_MDIO_CONTROL		0x0128	/* controls the mdio access */
-#define  BCMA_CORE_PCI_MDIOCTL_DIVISOR_MASK	0x7f	/* clock to be used on MDIO */
-#define  BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL	0x2
-#define  BCMA_CORE_PCI_MDIOCTL_PREAM_EN		0x80	/* Enable preamble sequnce */
-#define  BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE	0x100	/* Tranaction complete */
-#define BCMA_CORE_PCI_MDIO_DATA			0x012c	/* Data to the mdio access */
-#define  BCMA_CORE_PCI_MDIODATA_MASK		0x0000ffff /* data 2 bytes */
-#define  BCMA_CORE_PCI_MDIODATA_TA		0x00020000 /* Turnaround */
-#define  BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD	18	/* Regaddr shift (rev < 10) */
-#define  BCMA_CORE_PCI_MDIODATA_REGADDR_MASK_OLD	0x003c0000 /* Regaddr Mask (rev < 10) */
-#define  BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD	22	/* Physmedia devaddr shift (rev < 10) */
-#define  BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK_OLD	0x0fc00000 /* Physmedia devaddr Mask (rev < 10) */
-#define  BCMA_CORE_PCI_MDIODATA_REGADDR_SHF	18	/* Regaddr shift */
-#define  BCMA_CORE_PCI_MDIODATA_REGADDR_MASK	0x007c0000 /* Regaddr Mask */
-#define  BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF	23	/* Physmedia devaddr shift */
-#define  BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK	0x0f800000 /* Physmedia devaddr Mask */
-#define  BCMA_CORE_PCI_MDIODATA_WRITE		0x10000000 /* write Transaction */
-#define  BCMA_CORE_PCI_MDIODATA_READ		0x20000000 /* Read Transaction */
-#define  BCMA_CORE_PCI_MDIODATA_START		0x40000000 /* start of Transaction */
-#define  BCMA_CORE_PCI_MDIODATA_DEV_ADDR	0x0	/* dev address for serdes */
-#define  BCMA_CORE_PCI_MDIODATA_BLK_ADDR	0x1F	/* blk address for serdes */
-#define  BCMA_CORE_PCI_MDIODATA_DEV_PLL		0x1d	/* SERDES PLL Dev */
-#define  BCMA_CORE_PCI_MDIODATA_DEV_TX		0x1e	/* SERDES TX Dev */
-#define  BCMA_CORE_PCI_MDIODATA_DEV_RX		0x1f	/* SERDES RX Dev */
-#define BCMA_CORE_PCI_PCIEIND_ADDR		0x0130	/* indirect access to the internal register */
-#define BCMA_CORE_PCI_PCIEIND_DATA		0x0134	/* Data to/from the internal regsiter */
-#define BCMA_CORE_PCI_CLKREQENCTRL		0x0138	/*  >= rev 6, Clkreq rdma control */
-#define BCMA_CORE_PCI_PCICFG0			0x0400	/* PCI config space 0 (rev >= 8) */
-#define BCMA_CORE_PCI_PCICFG1			0x0500	/* PCI config space 1 (rev >= 8) */
-#define BCMA_CORE_PCI_PCICFG2			0x0600	/* PCI config space 2 (rev >= 8) */
-#define BCMA_CORE_PCI_PCICFG3			0x0700	/* PCI config space 3 (rev >= 8) */
-#define BCMA_CORE_PCI_SPROM(wordoffset)		(0x0800 + ((wordoffset) * 2)) /* SPROM shadow area (72 bytes) */
-
-/* SBtoPCIx */
-#define BCMA_CORE_PCI_SBTOPCI_MEM		0x00000000
-#define BCMA_CORE_PCI_SBTOPCI_IO		0x00000001
-#define BCMA_CORE_PCI_SBTOPCI_CFG0		0x00000002
-#define BCMA_CORE_PCI_SBTOPCI_CFG1		0x00000003
-#define BCMA_CORE_PCI_SBTOPCI_PREF		0x00000004 /* Prefetch enable */
-#define BCMA_CORE_PCI_SBTOPCI_BURST		0x00000008 /* Burst enable */
-#define BCMA_CORE_PCI_SBTOPCI_MRM		0x00000020 /* Memory Read Multiple */
-#define BCMA_CORE_PCI_SBTOPCI_RC		0x00000030 /* Read Command mask (rev >= 11) */
-#define  BCMA_CORE_PCI_SBTOPCI_RC_READ		0x00000000 /* Memory read */
-#define  BCMA_CORE_PCI_SBTOPCI_RC_READL		0x00000010 /* Memory read line */
-#define  BCMA_CORE_PCI_SBTOPCI_RC_READM		0x00000020 /* Memory read multiple */
-
-/* PCIE protocol PHY diagnostic registers */
-#define BCMA_CORE_PCI_PLP_MODEREG		0x200	/* Mode */
-#define BCMA_CORE_PCI_PLP_STATUSREG		0x204	/* Status */
-#define  BCMA_CORE_PCI_PLP_POLARITYINV_STAT	0x10	/* Status reg PCIE_PLP_STATUSREG */
-#define BCMA_CORE_PCI_PLP_LTSSMCTRLREG		0x208	/* LTSSM control */
-#define BCMA_CORE_PCI_PLP_LTLINKNUMREG		0x20c	/* Link Training Link number */
-#define BCMA_CORE_PCI_PLP_LTLANENUMREG		0x210	/* Link Training Lane number */
-#define BCMA_CORE_PCI_PLP_LTNFTSREG		0x214	/* Link Training N_FTS */
-#define BCMA_CORE_PCI_PLP_ATTNREG		0x218	/* Attention */
-#define BCMA_CORE_PCI_PLP_ATTNMASKREG		0x21C	/* Attention Mask */
-#define BCMA_CORE_PCI_PLP_RXERRCTR		0x220	/* Rx Error */
-#define BCMA_CORE_PCI_PLP_RXFRMERRCTR		0x224	/* Rx Framing Error */
-#define BCMA_CORE_PCI_PLP_RXERRTHRESHREG	0x228	/* Rx Error threshold */
-#define BCMA_CORE_PCI_PLP_TESTCTRLREG		0x22C	/* Test Control reg */
-#define BCMA_CORE_PCI_PLP_SERDESCTRLOVRDREG	0x230	/* SERDES Control Override */
-#define BCMA_CORE_PCI_PLP_TIMINGOVRDREG		0x234	/* Timing param override */
-#define BCMA_CORE_PCI_PLP_RXTXSMDIAGREG		0x238	/* RXTX State Machine Diag */
-#define BCMA_CORE_PCI_PLP_LTSSMDIAGREG		0x23C	/* LTSSM State Machine Diag */
-
-/* PCIE protocol DLLP diagnostic registers */
-#define BCMA_CORE_PCI_DLLP_LCREG		0x100	/* Link Control */
-#define BCMA_CORE_PCI_DLLP_LSREG		0x104	/* Link Status */
-#define BCMA_CORE_PCI_DLLP_LAREG		0x108	/* Link Attention */
-#define  BCMA_CORE_PCI_DLLP_LSREG_LINKUP	(1 << 16)
-#define BCMA_CORE_PCI_DLLP_LAMASKREG		0x10C	/* Link Attention Mask */
-#define BCMA_CORE_PCI_DLLP_NEXTTXSEQNUMREG	0x110	/* Next Tx Seq Num */
-#define BCMA_CORE_PCI_DLLP_ACKEDTXSEQNUMREG	0x114	/* Acked Tx Seq Num */
-#define BCMA_CORE_PCI_DLLP_PURGEDTXSEQNUMREG	0x118	/* Purged Tx Seq Num */
-#define BCMA_CORE_PCI_DLLP_RXSEQNUMREG		0x11C	/* Rx Sequence Number */
-#define BCMA_CORE_PCI_DLLP_LRREG		0x120	/* Link Replay */
-#define BCMA_CORE_PCI_DLLP_LACKTOREG		0x124	/* Link Ack Timeout */
-#define BCMA_CORE_PCI_DLLP_PMTHRESHREG		0x128	/* Power Management Threshold */
-#define BCMA_CORE_PCI_DLLP_RTRYWPREG		0x12C	/* Retry buffer write ptr */
-#define BCMA_CORE_PCI_DLLP_RTRYRPREG		0x130	/* Retry buffer Read ptr */
-#define BCMA_CORE_PCI_DLLP_RTRYPPREG		0x134	/* Retry buffer Purged ptr */
-#define BCMA_CORE_PCI_DLLP_RTRRWREG		0x138	/* Retry buffer Read/Write */
-#define BCMA_CORE_PCI_DLLP_ECTHRESHREG		0x13C	/* Error Count Threshold */
-#define BCMA_CORE_PCI_DLLP_TLPERRCTRREG		0x140	/* TLP Error Counter */
-#define BCMA_CORE_PCI_DLLP_ERRCTRREG		0x144	/* Error Counter */
-#define BCMA_CORE_PCI_DLLP_NAKRXCTRREG		0x148	/* NAK Received Counter */
-#define BCMA_CORE_PCI_DLLP_TESTREG		0x14C	/* Test */
-#define BCMA_CORE_PCI_DLLP_PKTBIST		0x150	/* Packet BIST */
-#define BCMA_CORE_PCI_DLLP_PCIE11		0x154	/* DLLP PCIE 1.1 reg */
-
-/* SERDES RX registers */
-#define BCMA_CORE_PCI_SERDES_RX_CTRL		1	/* Rx cntrl */
-#define  BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE	0x80	/* rxpolarity_force */
-#define  BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY	0x40	/* rxpolarity_value */
-#define BCMA_CORE_PCI_SERDES_RX_TIMER1		2	/* Rx Timer1 */
-#define BCMA_CORE_PCI_SERDES_RX_CDR		6	/* CDR */
-#define BCMA_CORE_PCI_SERDES_RX_CDRBW		7	/* CDR BW */
-
-/* SERDES PLL registers */
-#define BCMA_CORE_PCI_SERDES_PLL_CTRL		1	/* PLL control reg */
-#define BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN	0x4000	/* bit 14 is FREQDET on */
-
-/* PCIcore specific boardflags */
-#define BCMA_CORE_PCI_BFL_NOPCI			0x00000400 /* Board leaves PCI floating */
-
-/* PCIE Config space accessing MACROS */
-#define BCMA_CORE_PCI_CFG_BUS_SHIFT		24	/* Bus shift */
-#define BCMA_CORE_PCI_CFG_SLOT_SHIFT		19	/* Slot/Device shift */
-#define BCMA_CORE_PCI_CFG_FUN_SHIFT		16	/* Function shift */
-#define BCMA_CORE_PCI_CFG_OFF_SHIFT		0	/* Register shift */
-
-#define BCMA_CORE_PCI_CFG_BUS_MASK		0xff	/* Bus mask */
-#define BCMA_CORE_PCI_CFG_SLOT_MASK		0x1f	/* Slot/Device mask */
-#define BCMA_CORE_PCI_CFG_FUN_MASK		7	/* Function mask */
-#define BCMA_CORE_PCI_CFG_OFF_MASK		0xfff	/* Register mask */
-
-/* PCIE Root Capability Register bits (Host mode only) */
-#define BCMA_CORE_PCI_RC_CRS_VISIBILITY		0x0001
-
-struct bcma_drv_pci;
-
-#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
-struct bcma_drv_pci_host {
-	struct bcma_drv_pci *pdev;
-
-	u32 host_cfg_addr;
-	spinlock_t cfgspace_lock;
-
-	struct pci_controller pci_controller;
-	struct pci_ops pci_ops;
-	struct resource mem_resource;
-	struct resource io_resource;
-};
-#endif
-
-struct bcma_drv_pci {
-	struct bcma_device *core;
-	u8 setup_done:1;
-	u8 hostmode:1;
-
-#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
-	struct bcma_drv_pci_host *host_controller;
-#endif
-};
-
-/* Register access */
-#define pcicore_read32(pc, offset)		bcma_read32((pc)->core, offset)
-#define pcicore_write32(pc, offset, val)	bcma_write32((pc)->core, offset, val)
-
-extern void __devinit bcma_core_pci_init(struct bcma_drv_pci *pc);
-extern int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc,
-				 struct bcma_device *core, bool enable);
-
-extern int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev);
-extern int bcma_core_pci_plat_dev_init(struct pci_dev *dev);
-
-#endif /* LINUX_BCMA_DRIVER_PCI_H_ */
diff --git a/ANDROID_3.4.5/include/linux/bcma/bcma_regs.h b/ANDROID_3.4.5/include/linux/bcma/bcma_regs.h
deleted file mode 100644
index 5a71d571..00000000
--- a/ANDROID_3.4.5/include/linux/bcma/bcma_regs.h
+++ /dev/null
@@ -1,86 +0,0 @@
-#ifndef LINUX_BCMA_REGS_H_
-#define LINUX_BCMA_REGS_H_
-
-/* Some single registers are shared between many cores */
-/* BCMA_CLKCTLST: ChipCommon (rev >= 20), PCIe, 80211 */
-#define BCMA_CLKCTLST			0x01E0 /* Clock control and status */
-#define  BCMA_CLKCTLST_FORCEALP		0x00000001 /* Force ALP request */
-#define  BCMA_CLKCTLST_FORCEHT		0x00000002 /* Force HT request */
-#define  BCMA_CLKCTLST_FORCEILP		0x00000004 /* Force ILP request */
-#define  BCMA_CLKCTLST_HAVEALPREQ	0x00000008 /* ALP available request */
-#define  BCMA_CLKCTLST_HAVEHTREQ	0x00000010 /* HT available request */
-#define  BCMA_CLKCTLST_HWCROFF		0x00000020 /* Force HW clock request off */
-#define  BCMA_CLKCTLST_EXTRESREQ	0x00000700 /* Mask of external resource requests */
-#define  BCMA_CLKCTLST_HAVEALP		0x00010000 /* ALP available */
-#define  BCMA_CLKCTLST_HAVEHT		0x00020000 /* HT available */
-#define  BCMA_CLKCTLST_BP_ON_ALP	0x00040000 /* RO: running on ALP clock */
-#define  BCMA_CLKCTLST_BP_ON_HT		0x00080000 /* RO: running on HT clock */
-#define  BCMA_CLKCTLST_EXTRESST		0x07000000 /* Mask of external resource status */
-/* Is there any BCM4328 on BCMA bus? */
-#define  BCMA_CLKCTLST_4328A0_HAVEHT	0x00010000 /* 4328a0 has reversed bits */
-#define  BCMA_CLKCTLST_4328A0_HAVEALP	0x00020000 /* 4328a0 has reversed bits */
-
-/* Agent registers (common for every core) */
-#define BCMA_IOCTL			0x0408 /* IO control */
-#define  BCMA_IOCTL_CLK			0x0001
-#define  BCMA_IOCTL_FGC			0x0002
-#define  BCMA_IOCTL_CORE_BITS		0x3FFC
-#define  BCMA_IOCTL_PME_EN		0x4000
-#define  BCMA_IOCTL_BIST_EN		0x8000
-#define BCMA_IOST			0x0500 /* IO status */
-#define  BCMA_IOST_CORE_BITS		0x0FFF
-#define  BCMA_IOST_DMA64		0x1000
-#define  BCMA_IOST_GATED_CLK		0x2000
-#define  BCMA_IOST_BIST_ERROR		0x4000
-#define  BCMA_IOST_BIST_DONE		0x8000
-#define BCMA_RESET_CTL			0x0800
-#define  BCMA_RESET_CTL_RESET		0x0001
-
-/* BCMA PCI config space registers. */
-#define BCMA_PCI_PMCSR			0x44
-#define  BCMA_PCI_PE			0x100
-#define BCMA_PCI_BAR0_WIN		0x80	/* Backplane address space 0 */
-#define BCMA_PCI_BAR1_WIN		0x84	/* Backplane address space 1 */
-#define BCMA_PCI_SPROMCTL		0x88	/* SPROM control */
-#define  BCMA_PCI_SPROMCTL_WE		0x10	/* SPROM write enable */
-#define BCMA_PCI_BAR1_CONTROL		0x8c	/* Address space 1 burst control */
-#define BCMA_PCI_IRQS			0x90	/* PCI interrupts */
-#define BCMA_PCI_IRQMASK		0x94	/* PCI IRQ control and mask (pcirev >= 6 only) */
-#define BCMA_PCI_BACKPLANE_IRQS		0x98	/* Backplane Interrupts */
-#define BCMA_PCI_BAR0_WIN2		0xAC
-#define BCMA_PCI_GPIO_IN		0xB0	/* GPIO Input (pcirev >= 3 only) */
-#define BCMA_PCI_GPIO_OUT		0xB4	/* GPIO Output (pcirev >= 3 only) */
-#define BCMA_PCI_GPIO_OUT_ENABLE	0xB8	/* GPIO Output Enable/Disable (pcirev >= 3 only) */
-#define  BCMA_PCI_GPIO_SCS		0x10	/* PCI config space bit 4 for 4306c0 slow clock source */
-#define  BCMA_PCI_GPIO_HWRAD		0x20	/* PCI config space GPIO 13 for hw radio disable */
-#define  BCMA_PCI_GPIO_XTAL		0x40	/* PCI config space GPIO 14 for Xtal powerup */
-#define  BCMA_PCI_GPIO_PLL		0x80	/* PCI config space GPIO 15 for PLL powerdown */
-
-/* SiliconBackplane Address Map.
- * All regions may not exist on all chips.
- */
-#define BCMA_SOC_SDRAM_BASE		0x00000000U	/* Physical SDRAM */
-#define BCMA_SOC_PCI_MEM		0x08000000U	/* Host Mode sb2pcitranslation0 (64 MB) */
-#define BCMA_SOC_PCI_MEM_SZ		(64 * 1024 * 1024)
-#define BCMA_SOC_PCI_CFG		0x0c000000U	/* Host Mode sb2pcitranslation1 (64 MB) */
-#define BCMA_SOC_SDRAM_SWAPPED		0x10000000U	/* Byteswapped Physical SDRAM */
-#define BCMA_SOC_SDRAM_R2		0x80000000U	/* Region 2 for sdram (512 MB) */
-
-
-#define BCMA_SOC_PCI_DMA		0x40000000U	/* Client Mode sb2pcitranslation2 (1 GB) */
-#define BCMA_SOC_PCI_DMA2		0x80000000U	/* Client Mode sb2pcitranslation2 (1 GB) */
-#define BCMA_SOC_PCI_DMA_SZ		0x40000000U	/* Client Mode sb2pcitranslation2 size in bytes */
-#define BCMA_SOC_PCIE_DMA_L32		0x00000000U	/* PCIE Client Mode sb2pcitranslation2
-							 * (2 ZettaBytes), low 32 bits
-							 */
-#define BCMA_SOC_PCIE_DMA_H32		0x80000000U	/* PCIE Client Mode sb2pcitranslation2
-							 * (2 ZettaBytes), high 32 bits
-							 */
-
-#define BCMA_SOC_PCI1_MEM		0x40000000U	/* Host Mode sb2pcitranslation0 (64 MB) */
-#define BCMA_SOC_PCI1_CFG		0x44000000U	/* Host Mode sb2pcitranslation1 (64 MB) */
-#define BCMA_SOC_PCIE1_DMA_H32		0xc0000000U	/* PCIE Client Mode sb2pcitranslation2
-							 * (2 ZettaBytes), high 32 bits
-							 */
-
-#endif /* LINUX_BCMA_REGS_H_ */
diff --git a/ANDROID_3.4.5/include/linux/bcma/bcma_soc.h b/ANDROID_3.4.5/include/linux/bcma/bcma_soc.h
deleted file mode 100644
index 4203c559..00000000
--- a/ANDROID_3.4.5/include/linux/bcma/bcma_soc.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#ifndef LINUX_BCMA_SOC_H_
-#define LINUX_BCMA_SOC_H_
-
-#include <linux/bcma/bcma.h>
-
-struct bcma_soc {
-	struct bcma_bus bus;
-	struct bcma_device core_cc;
-	struct bcma_device core_mips;
-};
-
-int __init bcma_host_soc_register(struct bcma_soc *soc);
-
-int bcma_bus_register(struct bcma_bus *bus);
-
-#endif /* LINUX_BCMA_SOC_H_ */