Moved, renamed, and deleted files

The original directory structure was scattered and unorganized.
Changes are basically to make it look like kernel structure.

9 files changed, 0 insertions, 3654 deletions

diff --git a/ANDROID_3.4.5/arch/x86/kernel/cpu/mtrr/Makefile b/ANDROID_3.4.5/arch/x86/kernel/cpu/mtrr/Makefile
deleted file mode 100644
index ad9e5ed8..00000000
--- a/ANDROID_3.4.5/arch/x86/kernel/cpu/mtrr/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-obj-y		:= main.o if.o generic.o cleanup.o
-obj-$(CONFIG_X86_32) += amd.o cyrix.o centaur.o
-
diff --git a/ANDROID_3.4.5/arch/x86/kernel/cpu/mtrr/amd.c b/ANDROID_3.4.5/arch/x86/kernel/cpu/mtrr/amd.c
deleted file mode 100644
index 92ba9cd3..00000000
--- a/ANDROID_3.4.5/arch/x86/kernel/cpu/mtrr/amd.c
+++ /dev/null
@@ -1,124 +0,0 @@
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <asm/mtrr.h>
-#include <asm/msr.h>
-
-#include "mtrr.h"
-
-static void
-amd_get_mtrr(unsigned int reg, unsigned long *base,
-	     unsigned long *size, mtrr_type *type)
-{
-	unsigned long low, high;
-
-	rdmsr(MSR_K6_UWCCR, low, high);
-	/* Upper dword is region 1, lower is region 0 */
-	if (reg == 1)
-		low = high;
-	/* The base masks off on the right alignment */
-	*base = (low & 0xFFFE0000) >> PAGE_SHIFT;
-	*type = 0;
-	if (low & 1)
-		*type = MTRR_TYPE_UNCACHABLE;
-	if (low & 2)
-		*type = MTRR_TYPE_WRCOMB;
-	if (!(low & 3)) {
-		*size = 0;
-		return;
-	}
-	/*
-	 * This needs a little explaining. The size is stored as an
-	 * inverted mask of bits of 128K granularity 15 bits long offset
-	 * 2 bits.
-	 *
-	 * So to get a size we do invert the mask and add 1 to the lowest
-	 * mask bit (4 as its 2 bits in). This gives us a size we then shift
-	 * to turn into 128K blocks.
-	 *
-	 * eg              111 1111 1111 1100      is 512K
-	 *
-	 * invert          000 0000 0000 0011
-	 * +1              000 0000 0000 0100
-	 * *128K   ...
-	 */
-	low = (~low) & 0x1FFFC;
-	*size = (low + 4) << (15 - PAGE_SHIFT);
-}
-
-/**
- * amd_set_mtrr - Set variable MTRR register on the local CPU.
- *
- * @reg The register to set.
- * @base The base address of the region.
- * @size The size of the region. If this is 0 the region is disabled.
- * @type The type of the region.
- *
- * Returns nothing.
- */
-static void
-amd_set_mtrr(unsigned int reg, unsigned long base, unsigned long size, mtrr_type type)
-{
-	u32 regs[2];
-
-	/*
-	 * Low is MTRR0, High MTRR 1
-	 */
-	rdmsr(MSR_K6_UWCCR, regs[0], regs[1]);
-	/*
-	 * Blank to disable
-	 */
-	if (size == 0) {
-		regs[reg] = 0;
-	} else {
-		/*
-		 * Set the register to the base, the type (off by one) and an
-		 * inverted bitmask of the size The size is the only odd
-		 * bit. We are fed say 512K We invert this and we get 111 1111
-		 * 1111 1011 but if you subtract one and invert you get the
-		 * desired 111 1111 1111 1100 mask
-		 *
-		 *  But ~(x - 1) == ~x + 1 == -x. Two's complement rocks!
-		 */
-		regs[reg] = (-size >> (15 - PAGE_SHIFT) & 0x0001FFFC)
-		    | (base << PAGE_SHIFT) | (type + 1);
-	}
-
-	/*
-	 * The writeback rule is quite specific. See the manual. Its
-	 * disable local interrupts, write back the cache, set the mtrr
-	 */
-	wbinvd();
-	wrmsr(MSR_K6_UWCCR, regs[0], regs[1]);
-}
-
-static int
-amd_validate_add_page(unsigned long base, unsigned long size, unsigned int type)
-{
-	/*
-	 * Apply the K6 block alignment and size rules
-	 * In order
-	 * o Uncached or gathering only
-	 * o 128K or bigger block
-	 * o Power of 2 block
-	 * o base suitably aligned to the power
-	 */
-	if (type > MTRR_TYPE_WRCOMB || size < (1 << (17 - PAGE_SHIFT))
-	    || (size & ~(size - 1)) - size || (base & (size - 1)))
-		return -EINVAL;
-	return 0;
-}
-
-static const struct mtrr_ops amd_mtrr_ops = {
-	.vendor            = X86_VENDOR_AMD,
-	.set               = amd_set_mtrr,
-	.get               = amd_get_mtrr,
-	.get_free_region   = generic_get_free_region,
-	.validate_add_page = amd_validate_add_page,
-	.have_wrcomb       = positive_have_wrcomb,
-};
-
-int __init amd_init_mtrr(void)
-{
-	set_mtrr_ops(&amd_mtrr_ops);
-	return 0;
-}
diff --git a/ANDROID_3.4.5/arch/x86/kernel/cpu/mtrr/centaur.c b/ANDROID_3.4.5/arch/x86/kernel/cpu/mtrr/centaur.c
deleted file mode 100644
index 316fe3e6..00000000
--- a/ANDROID_3.4.5/arch/x86/kernel/cpu/mtrr/centaur.c
+++ /dev/null
@@ -1,126 +0,0 @@
-#include <linux/init.h>
-#include <linux/mm.h>
-
-#include <asm/mtrr.h>
-#include <asm/msr.h>
-
-#include "mtrr.h"
-
-static struct {
-	unsigned long high;
-	unsigned long low;
-} centaur_mcr[8];
-
-static u8 centaur_mcr_reserved;
-static u8 centaur_mcr_type;	/* 0 for winchip, 1 for winchip2 */
-
-/**
- * centaur_get_free_region - Get a free MTRR.
- *
- * @base: The starting (base) address of the region.
- * @size: The size (in bytes) of the region.
- *
- * Returns: the index of the region on success, else -1 on error.
- */
-static int
-centaur_get_free_region(unsigned long base, unsigned long size, int replace_reg)
-{
-	unsigned long lbase, lsize;
-	mtrr_type ltype;
-	int i, max;
-
-	max = num_var_ranges;
-	if (replace_reg >= 0 && replace_reg < max)
-		return replace_reg;
-
-	for (i = 0; i < max; ++i) {
-		if (centaur_mcr_reserved & (1 << i))
-			continue;
-		mtrr_if->get(i, &lbase, &lsize, &ltype);
-		if (lsize == 0)
-			return i;
-	}
-
-	return -ENOSPC;
-}
-
-/*
- * Report boot time MCR setups
- */
-void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi)
-{
-	centaur_mcr[mcr].low = lo;
-	centaur_mcr[mcr].high = hi;
-}
-
-static void
-centaur_get_mcr(unsigned int reg, unsigned long *base,
-		unsigned long *size, mtrr_type * type)
-{
-	*base = centaur_mcr[reg].high >> PAGE_SHIFT;
-	*size = -(centaur_mcr[reg].low & 0xfffff000) >> PAGE_SHIFT;
-	*type = MTRR_TYPE_WRCOMB;		/* write-combining  */
-
-	if (centaur_mcr_type == 1 && ((centaur_mcr[reg].low & 31) & 2))
-		*type = MTRR_TYPE_UNCACHABLE;
-	if (centaur_mcr_type == 1 && (centaur_mcr[reg].low & 31) == 25)
-		*type = MTRR_TYPE_WRBACK;
-	if (centaur_mcr_type == 0 && (centaur_mcr[reg].low & 31) == 31)
-		*type = MTRR_TYPE_WRBACK;
-}
-
-static void
-centaur_set_mcr(unsigned int reg, unsigned long base,
-		unsigned long size, mtrr_type type)
-{
-	unsigned long low, high;
-
-	if (size == 0) {
-		/* Disable */
-		high = low = 0;
-	} else {
-		high = base << PAGE_SHIFT;
-		if (centaur_mcr_type == 0) {
-			/* Only support write-combining... */
-			low = -size << PAGE_SHIFT | 0x1f;
-		} else {
-			if (type == MTRR_TYPE_UNCACHABLE)
-				low = -size << PAGE_SHIFT | 0x02; /* NC */
-			else
-				low = -size << PAGE_SHIFT | 0x09; /* WWO, WC */
-		}
-	}
-	centaur_mcr[reg].high = high;
-	centaur_mcr[reg].low = low;
-	wrmsr(MSR_IDT_MCR0 + reg, low, high);
-}
-
-static int
-centaur_validate_add_page(unsigned long base, unsigned long size, unsigned int type)
-{
-	/*
-	 * FIXME: Winchip2 supports uncached
-	 */
-	if (type != MTRR_TYPE_WRCOMB &&
-	    (centaur_mcr_type == 0 || type != MTRR_TYPE_UNCACHABLE)) {
-		pr_warning("mtrr: only write-combining%s supported\n",
-			   centaur_mcr_type ? " and uncacheable are" : " is");
-		return -EINVAL;
-	}
-	return 0;
-}
-
-static const struct mtrr_ops centaur_mtrr_ops = {
-	.vendor            = X86_VENDOR_CENTAUR,
-	.set               = centaur_set_mcr,
-	.get               = centaur_get_mcr,
-	.get_free_region   = centaur_get_free_region,
-	.validate_add_page = centaur_validate_add_page,
-	.have_wrcomb       = positive_have_wrcomb,
-};
-
-int __init centaur_init_mtrr(void)
-{
-	set_mtrr_ops(&centaur_mtrr_ops);
-	return 0;
-}
diff --git a/ANDROID_3.4.5/arch/x86/kernel/cpu/mtrr/cleanup.c b/ANDROID_3.4.5/arch/x86/kernel/cpu/mtrr/cleanup.c
deleted file mode 100644
index ac140c7b..00000000
--- a/ANDROID_3.4.5/arch/x86/kernel/cpu/mtrr/cleanup.c
+++ /dev/null
@@ -1,980 +0,0 @@
-/*
- * MTRR (Memory Type Range Register) cleanup
- *
- *  Copyright (C) 2009 Yinghai Lu
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Library General Public
- * License as published by the Free Software Foundation; either
- * version 2 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * Library General Public License for more details.
- *
- * You should have received a copy of the GNU Library General Public
- * License along with this library; if not, write to the Free
- * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/pci.h>
-#include <linux/smp.h>
-#include <linux/cpu.h>
-#include <linux/mutex.h>
-#include <linux/uaccess.h>
-#include <linux/kvm_para.h>
-#include <linux/range.h>
-
-#include <asm/processor.h>
-#include <asm/e820.h>
-#include <asm/mtrr.h>
-#include <asm/msr.h>
-
-#include "mtrr.h"
-
-struct var_mtrr_range_state {
-	unsigned long	base_pfn;
-	unsigned long	size_pfn;
-	mtrr_type	type;
-};
-
-struct var_mtrr_state {
-	unsigned long	range_startk;
-	unsigned long	range_sizek;
-	unsigned long	chunk_sizek;
-	unsigned long	gran_sizek;
-	unsigned int	reg;
-};
-
-/* Should be related to MTRR_VAR_RANGES nums */
-#define RANGE_NUM				256
-
-static struct range __initdata		range[RANGE_NUM];
-static int __initdata				nr_range;
-
-static struct var_mtrr_range_state __initdata	range_state[RANGE_NUM];
-
-static int __initdata debug_print;
-#define Dprintk(x...) do { if (debug_print) printk(KERN_DEBUG x); } while (0)
-
-#define BIOS_BUG_MSG KERN_WARNING \
-	"WARNING: BIOS bug: VAR MTRR %d contains strange UC entry under 1M, check with your system vendor!\n"
-
-static int __init
-x86_get_mtrr_mem_range(struct range *range, int nr_range,
-		       unsigned long extra_remove_base,
-		       unsigned long extra_remove_size)
-{
-	unsigned long base, size;
-	mtrr_type type;
-	int i;
-
-	for (i = 0; i < num_var_ranges; i++) {
-		type = range_state[i].type;
-		if (type != MTRR_TYPE_WRBACK)
-			continue;
-		base = range_state[i].base_pfn;
-		size = range_state[i].size_pfn;
-		nr_range = add_range_with_merge(range, RANGE_NUM, nr_range,
-						base, base + size);
-	}
-	if (debug_print) {
-		printk(KERN_DEBUG "After WB checking\n");
-		for (i = 0; i < nr_range; i++)
-			printk(KERN_DEBUG "MTRR MAP PFN: %016llx - %016llx\n",
-				 range[i].start, range[i].end);
-	}
-
-	/* Take out UC ranges: */
-	for (i = 0; i < num_var_ranges; i++) {
-		type = range_state[i].type;
-		if (type != MTRR_TYPE_UNCACHABLE &&
-		    type != MTRR_TYPE_WRPROT)
-			continue;
-		size = range_state[i].size_pfn;
-		if (!size)
-			continue;
-		base = range_state[i].base_pfn;
-		if (base < (1<<(20-PAGE_SHIFT)) && mtrr_state.have_fixed &&
-		    (mtrr_state.enabled & 1)) {
-			/* Var MTRR contains UC entry below 1M? Skip it: */
-			printk(BIOS_BUG_MSG, i);
-			if (base + size <= (1<<(20-PAGE_SHIFT)))
-				continue;
-			size -= (1<<(20-PAGE_SHIFT)) - base;
-			base = 1<<(20-PAGE_SHIFT);
-		}
-		subtract_range(range, RANGE_NUM, base, base + size);
-	}
-	if (extra_remove_size)
-		subtract_range(range, RANGE_NUM, extra_remove_base,
-				 extra_remove_base + extra_remove_size);
-
-	if  (debug_print) {
-		printk(KERN_DEBUG "After UC checking\n");
-		for (i = 0; i < RANGE_NUM; i++) {
-			if (!range[i].end)
-				continue;
-			printk(KERN_DEBUG "MTRR MAP PFN: %016llx - %016llx\n",
-				 range[i].start, range[i].end);
-		}
-	}
-
-	/* sort the ranges */
-	nr_range = clean_sort_range(range, RANGE_NUM);
-	if  (debug_print) {
-		printk(KERN_DEBUG "After sorting\n");
-		for (i = 0; i < nr_range; i++)
-			printk(KERN_DEBUG "MTRR MAP PFN: %016llx - %016llx\n",
-				 range[i].start, range[i].end);
-	}
-
-	return nr_range;
-}
-
-#ifdef CONFIG_MTRR_SANITIZER
-
-static unsigned long __init sum_ranges(struct range *range, int nr_range)
-{
-	unsigned long sum = 0;
-	int i;
-
-	for (i = 0; i < nr_range; i++)
-		sum += range[i].end - range[i].start;
-
-	return sum;
-}
-
-static int enable_mtrr_cleanup __initdata =
-	CONFIG_MTRR_SANITIZER_ENABLE_DEFAULT;
-
-static int __init disable_mtrr_cleanup_setup(char *str)
-{
-	enable_mtrr_cleanup = 0;
-	return 0;
-}
-early_param("disable_mtrr_cleanup", disable_mtrr_cleanup_setup);
-
-static int __init enable_mtrr_cleanup_setup(char *str)
-{
-	enable_mtrr_cleanup = 1;
-	return 0;
-}
-early_param("enable_mtrr_cleanup", enable_mtrr_cleanup_setup);
-
-static int __init mtrr_cleanup_debug_setup(char *str)
-{
-	debug_print = 1;
-	return 0;
-}
-early_param("mtrr_cleanup_debug", mtrr_cleanup_debug_setup);
-
-static void __init
-set_var_mtrr(unsigned int reg, unsigned long basek, unsigned long sizek,
-	     unsigned char type, unsigned int address_bits)
-{
-	u32 base_lo, base_hi, mask_lo, mask_hi;
-	u64 base, mask;
-
-	if (!sizek) {
-		fill_mtrr_var_range(reg, 0, 0, 0, 0);
-		return;
-	}
-
-	mask = (1ULL << address_bits) - 1;
-	mask &= ~((((u64)sizek) << 10) - 1);
-
-	base = ((u64)basek) << 10;
-
-	base |= type;
-	mask |= 0x800;
-
-	base_lo = base & ((1ULL<<32) - 1);
-	base_hi = base >> 32;
-
-	mask_lo = mask & ((1ULL<<32) - 1);
-	mask_hi = mask >> 32;
-
-	fill_mtrr_var_range(reg, base_lo, base_hi, mask_lo, mask_hi);
-}
-
-static void __init
-save_var_mtrr(unsigned int reg, unsigned long basek, unsigned long sizek,
-	      unsigned char type)
-{
-	range_state[reg].base_pfn = basek >> (PAGE_SHIFT - 10);
-	range_state[reg].size_pfn = sizek >> (PAGE_SHIFT - 10);
-	range_state[reg].type = type;
-}
-
-static void __init set_var_mtrr_all(unsigned int address_bits)
-{
-	unsigned long basek, sizek;
-	unsigned char type;
-	unsigned int reg;
-
-	for (reg = 0; reg < num_var_ranges; reg++) {
-		basek = range_state[reg].base_pfn << (PAGE_SHIFT - 10);
-		sizek = range_state[reg].size_pfn << (PAGE_SHIFT - 10);
-		type = range_state[reg].type;
-
-		set_var_mtrr(reg, basek, sizek, type, address_bits);
-	}
-}
-
-static unsigned long to_size_factor(unsigned long sizek, char *factorp)
-{
-	unsigned long base = sizek;
-	char factor;
-
-	if (base & ((1<<10) - 1)) {
-		/* Not MB-aligned: */
-		factor = 'K';
-	} else if (base & ((1<<20) - 1)) {
-		factor = 'M';
-		base >>= 10;
-	} else {
-		factor = 'G';
-		base >>= 20;
-	}
-
-	*factorp = factor;
-
-	return base;
-}
-
-static unsigned int __init
-range_to_mtrr(unsigned int reg, unsigned long range_startk,
-	      unsigned long range_sizek, unsigned char type)
-{
-	if (!range_sizek || (reg >= num_var_ranges))
-		return reg;
-
-	while (range_sizek) {
-		unsigned long max_align, align;
-		unsigned long sizek;
-
-		/* Compute the maximum size with which we can make a range: */
-		if (range_startk)
-			max_align = ffs(range_startk) - 1;
-		else
-			max_align = 32;
-
-		align = fls(range_sizek) - 1;
-		if (align > max_align)
-			align = max_align;
-
-		sizek = 1 << align;
-		if (debug_print) {
-			char start_factor = 'K', size_factor = 'K';
-			unsigned long start_base, size_base;
-
-			start_base = to_size_factor(range_startk, &start_factor);
-			size_base = to_size_factor(sizek, &size_factor);
-
-			Dprintk("Setting variable MTRR %d, "
-				"base: %ld%cB, range: %ld%cB, type %s\n",
-				reg, start_base, start_factor,
-				size_base, size_factor,
-				(type == MTRR_TYPE_UNCACHABLE) ? "UC" :
-				   ((type == MTRR_TYPE_WRBACK) ? "WB" : "Other")
-				);
-		}
-		save_var_mtrr(reg++, range_startk, sizek, type);
-		range_startk += sizek;
-		range_sizek -= sizek;
-		if (reg >= num_var_ranges)
-			break;
-	}
-	return reg;
-}
-
-static unsigned __init
-range_to_mtrr_with_hole(struct var_mtrr_state *state, unsigned long basek,
-			unsigned long sizek)
-{
-	unsigned long hole_basek, hole_sizek;
-	unsigned long second_basek, second_sizek;
-	unsigned long range0_basek, range0_sizek;
-	unsigned long range_basek, range_sizek;
-	unsigned long chunk_sizek;
-	unsigned long gran_sizek;
-
-	hole_basek = 0;
-	hole_sizek = 0;
-	second_basek = 0;
-	second_sizek = 0;
-	chunk_sizek = state->chunk_sizek;
-	gran_sizek = state->gran_sizek;
-
-	/* Align with gran size, prevent small block used up MTRRs: */
-	range_basek = ALIGN(state->range_startk, gran_sizek);
-	if ((range_basek > basek) && basek)
-		return second_sizek;
-
-	state->range_sizek -= (range_basek - state->range_startk);
-	range_sizek = ALIGN(state->range_sizek, gran_sizek);
-
-	while (range_sizek > state->range_sizek) {
-		range_sizek -= gran_sizek;
-		if (!range_sizek)
-			return 0;
-	}
-	state->range_sizek = range_sizek;
-
-	/* Try to append some small hole: */
-	range0_basek = state->range_startk;
-	range0_sizek = ALIGN(state->range_sizek, chunk_sizek);
-
-	/* No increase: */
-	if (range0_sizek == state->range_sizek) {
-		Dprintk("rangeX: %016lx - %016lx\n",
-			range0_basek<<10,
-			(range0_basek + state->range_sizek)<<10);
-		state->reg = range_to_mtrr(state->reg, range0_basek,
-				state->range_sizek, MTRR_TYPE_WRBACK);
-		return 0;
-	}
-
-	/* Only cut back when it is not the last: */
-	if (sizek) {
-		while (range0_basek + range0_sizek > (basek + sizek)) {
-			if (range0_sizek >= chunk_sizek)
-				range0_sizek -= chunk_sizek;
-			else
-				range0_sizek = 0;
-
-			if (!range0_sizek)
-				break;
-		}
-	}
-
-second_try:
-	range_basek = range0_basek + range0_sizek;
-
-	/* One hole in the middle: */
-	if (range_basek > basek && range_basek <= (basek + sizek))
-		second_sizek = range_basek - basek;
-
-	if (range0_sizek > state->range_sizek) {
-
-		/* One hole in middle or at the end: */
-		hole_sizek = range0_sizek - state->range_sizek - second_sizek;
-
-		/* Hole size should be less than half of range0 size: */
-		if (hole_sizek >= (range0_sizek >> 1) &&
-		    range0_sizek >= chunk_sizek) {
-			range0_sizek -= chunk_sizek;
-			second_sizek = 0;
-			hole_sizek = 0;
-
-			goto second_try;
-		}
-	}
-
-	if (range0_sizek) {
-		Dprintk("range0: %016lx - %016lx\n",
-			range0_basek<<10,
-			(range0_basek + range0_sizek)<<10);
-		state->reg = range_to_mtrr(state->reg, range0_basek,
-				range0_sizek, MTRR_TYPE_WRBACK);
-	}
-
-	if (range0_sizek < state->range_sizek) {
-		/* Need to handle left over range: */
-		range_sizek = state->range_sizek - range0_sizek;
-
-		Dprintk("range: %016lx - %016lx\n",
-			 range_basek<<10,
-			 (range_basek + range_sizek)<<10);
-
-		state->reg = range_to_mtrr(state->reg, range_basek,
-				 range_sizek, MTRR_TYPE_WRBACK);
-	}
-
-	if (hole_sizek) {
-		hole_basek = range_basek - hole_sizek - second_sizek;
-		Dprintk("hole: %016lx - %016lx\n",
-			 hole_basek<<10,
-			 (hole_basek + hole_sizek)<<10);
-		state->reg = range_to_mtrr(state->reg, hole_basek,
-				 hole_sizek, MTRR_TYPE_UNCACHABLE);
-	}
-
-	return second_sizek;
-}
-
-static void __init
-set_var_mtrr_range(struct var_mtrr_state *state, unsigned long base_pfn,
-		   unsigned long size_pfn)
-{
-	unsigned long basek, sizek;
-	unsigned long second_sizek = 0;
-
-	if (state->reg >= num_var_ranges)
-		return;
-
-	basek = base_pfn << (PAGE_SHIFT - 10);
-	sizek = size_pfn << (PAGE_SHIFT - 10);
-
-	/* See if I can merge with the last range: */
-	if ((basek <= 1024) ||
-	    (state->range_startk + state->range_sizek == basek)) {
-		unsigned long endk = basek + sizek;
-		state->range_sizek = endk - state->range_startk;
-		return;
-	}
-	/* Write the range mtrrs: */
-	if (state->range_sizek != 0)
-		second_sizek = range_to_mtrr_with_hole(state, basek, sizek);
-
-	/* Allocate an msr: */
-	state->range_startk = basek + second_sizek;
-	state->range_sizek  = sizek - second_sizek;
-}
-
-/* Mininum size of mtrr block that can take hole: */
-static u64 mtrr_chunk_size __initdata = (256ULL<<20);
-
-static int __init parse_mtrr_chunk_size_opt(char *p)
-{
-	if (!p)
-		return -EINVAL;
-	mtrr_chunk_size = memparse(p, &p);
-	return 0;
-}
-early_param("mtrr_chunk_size", parse_mtrr_chunk_size_opt);
-
-/* Granularity of mtrr of block: */
-static u64 mtrr_gran_size __initdata;
-
-static int __init parse_mtrr_gran_size_opt(char *p)
-{
-	if (!p)
-		return -EINVAL;
-	mtrr_gran_size = memparse(p, &p);
-	return 0;
-}
-early_param("mtrr_gran_size", parse_mtrr_gran_size_opt);
-
-static unsigned long nr_mtrr_spare_reg __initdata =
-				 CONFIG_MTRR_SANITIZER_SPARE_REG_NR_DEFAULT;
-
-static int __init parse_mtrr_spare_reg(char *arg)
-{
-	if (arg)
-		nr_mtrr_spare_reg = simple_strtoul(arg, NULL, 0);
-	return 0;
-}
-early_param("mtrr_spare_reg_nr", parse_mtrr_spare_reg);
-
-static int __init
-x86_setup_var_mtrrs(struct range *range, int nr_range,
-		    u64 chunk_size, u64 gran_size)
-{
-	struct var_mtrr_state var_state;
-	int num_reg;
-	int i;
-
-	var_state.range_startk	= 0;
-	var_state.range_sizek	= 0;
-	var_state.reg		= 0;
-	var_state.chunk_sizek	= chunk_size >> 10;
-	var_state.gran_sizek	= gran_size >> 10;
-
-	memset(range_state, 0, sizeof(range_state));
-
-	/* Write the range: */
-	for (i = 0; i < nr_range; i++) {
-		set_var_mtrr_range(&var_state, range[i].start,
-				   range[i].end - range[i].start);
-	}
-
-	/* Write the last range: */
-	if (var_state.range_sizek != 0)
-		range_to_mtrr_with_hole(&var_state, 0, 0);
-
-	num_reg = var_state.reg;
-	/* Clear out the extra MTRR's: */
-	while (var_state.reg < num_var_ranges) {
-		save_var_mtrr(var_state.reg, 0, 0, 0);
-		var_state.reg++;
-	}
-
-	return num_reg;
-}
-
-struct mtrr_cleanup_result {
-	unsigned long	gran_sizek;
-	unsigned long	chunk_sizek;
-	unsigned long	lose_cover_sizek;
-	unsigned int	num_reg;
-	int		bad;
-};
-
-/*
- * gran_size: 64K, 128K, 256K, 512K, 1M, 2M, ..., 2G
- * chunk size: gran_size, ..., 2G
- * so we need (1+16)*8
- */
-#define NUM_RESULT	136
-#define PSHIFT		(PAGE_SHIFT - 10)
-
-static struct mtrr_cleanup_result __initdata result[NUM_RESULT];
-static unsigned long __initdata min_loss_pfn[RANGE_NUM];
-
-static void __init print_out_mtrr_range_state(void)
-{
-	char start_factor = 'K', size_factor = 'K';
-	unsigned long start_base, size_base;
-	mtrr_type type;
-	int i;
-
-	for (i = 0; i < num_var_ranges; i++) {
-
-		size_base = range_state[i].size_pfn << (PAGE_SHIFT - 10);
-		if (!size_base)
-			continue;
-
-		size_base = to_size_factor(size_base, &size_factor),
-		start_base = range_state[i].base_pfn << (PAGE_SHIFT - 10);
-		start_base = to_size_factor(start_base, &start_factor),
-		type = range_state[i].type;
-
-		printk(KERN_DEBUG "reg %d, base: %ld%cB, range: %ld%cB, type %s\n",
-			i, start_base, start_factor,
-			size_base, size_factor,
-			(type == MTRR_TYPE_UNCACHABLE) ? "UC" :
-			    ((type == MTRR_TYPE_WRPROT) ? "WP" :
-			     ((type == MTRR_TYPE_WRBACK) ? "WB" : "Other"))
-			);
-	}
-}
-
-static int __init mtrr_need_cleanup(void)
-{
-	int i;
-	mtrr_type type;
-	unsigned long size;
-	/* Extra one for all 0: */
-	int num[MTRR_NUM_TYPES + 1];
-
-	/* Check entries number: */
-	memset(num, 0, sizeof(num));
-	for (i = 0; i < num_var_ranges; i++) {
-		type = range_state[i].type;
-		size = range_state[i].size_pfn;
-		if (type >= MTRR_NUM_TYPES)
-			continue;
-		if (!size)
-			type = MTRR_NUM_TYPES;
-		num[type]++;
-	}
-
-	/* Check if we got UC entries: */
-	if (!num[MTRR_TYPE_UNCACHABLE])
-		return 0;
-
-	/* Check if we only had WB and UC */
-	if (num[MTRR_TYPE_WRBACK] + num[MTRR_TYPE_UNCACHABLE] !=
-	    num_var_ranges - num[MTRR_NUM_TYPES])
-		return 0;
-
-	return 1;
-}
-
-static unsigned long __initdata range_sums;
-
-static void __init
-mtrr_calc_range_state(u64 chunk_size, u64 gran_size,
-		      unsigned long x_remove_base,
-		      unsigned long x_remove_size, int i)
-{
-	static struct range range_new[RANGE_NUM];
-	unsigned long range_sums_new;
-	static int nr_range_new;
-	int num_reg;
-
-	/* Convert ranges to var ranges state: */
-	num_reg = x86_setup_var_mtrrs(range, nr_range, chunk_size, gran_size);
-
-	/* We got new setting in range_state, check it: */
-	memset(range_new, 0, sizeof(range_new));
-	nr_range_new = x86_get_mtrr_mem_range(range_new, 0,
-				x_remove_base, x_remove_size);
-	range_sums_new = sum_ranges(range_new, nr_range_new);
-
-	result[i].chunk_sizek = chunk_size >> 10;
-	result[i].gran_sizek = gran_size >> 10;
-	result[i].num_reg = num_reg;
-
-	if (range_sums < range_sums_new) {
-		result[i].lose_cover_sizek = (range_sums_new - range_sums) << PSHIFT;
-		result[i].bad = 1;
-	} else {
-		result[i].lose_cover_sizek = (range_sums - range_sums_new) << PSHIFT;
-	}
-
-	/* Double check it: */
-	if (!result[i].bad && !result[i].lose_cover_sizek) {
-		if (nr_range_new != nr_range || memcmp(range, range_new, sizeof(range)))
-			result[i].bad = 1;
-	}
-
-	if (!result[i].bad && (range_sums - range_sums_new < min_loss_pfn[num_reg]))
-		min_loss_pfn[num_reg] = range_sums - range_sums_new;
-}
-
-static void __init mtrr_print_out_one_result(int i)
-{
-	unsigned long gran_base, chunk_base, lose_base;
-	char gran_factor, chunk_factor, lose_factor;
-
-	gran_base = to_size_factor(result[i].gran_sizek, &gran_factor);
-	chunk_base = to_size_factor(result[i].chunk_sizek, &chunk_factor);
-	lose_base = to_size_factor(result[i].lose_cover_sizek, &lose_factor);
-
-	pr_info("%sgran_size: %ld%c \tchunk_size: %ld%c \t",
-		result[i].bad ? "*BAD*" : " ",
-		gran_base, gran_factor, chunk_base, chunk_factor);
-	pr_cont("num_reg: %d  \tlose cover RAM: %s%ld%c\n",
-		result[i].num_reg, result[i].bad ? "-" : "",
-		lose_base, lose_factor);
-}
-
-static int __init mtrr_search_optimal_index(void)
-{
-	int num_reg_good;
-	int index_good;
-	int i;
-
-	if (nr_mtrr_spare_reg >= num_var_ranges)
-		nr_mtrr_spare_reg = num_var_ranges - 1;
-
-	num_reg_good = -1;
-	for (i = num_var_ranges - nr_mtrr_spare_reg; i > 0; i--) {
-		if (!min_loss_pfn[i])
-			num_reg_good = i;
-	}
-
-	index_good = -1;
-	if (num_reg_good != -1) {
-		for (i = 0; i < NUM_RESULT; i++) {
-			if (!result[i].bad &&
-			    result[i].num_reg == num_reg_good &&
-			    !result[i].lose_cover_sizek) {
-				index_good = i;
-				break;
-			}
-		}
-	}
-
-	return index_good;
-}
-
-int __init mtrr_cleanup(unsigned address_bits)
-{
-	unsigned long x_remove_base, x_remove_size;
-	unsigned long base, size, def, dummy;
-	u64 chunk_size, gran_size;
-	mtrr_type type;
-	int index_good;
-	int i;
-
-	if (!is_cpu(INTEL) || enable_mtrr_cleanup < 1)
-		return 0;
-
-	rdmsr(MSR_MTRRdefType, def, dummy);
-	def &= 0xff;
-	if (def != MTRR_TYPE_UNCACHABLE)
-		return 0;
-
-	/* Get it and store it aside: */
-	memset(range_state, 0, sizeof(range_state));
-	for (i = 0; i < num_var_ranges; i++) {
-		mtrr_if->get(i, &base, &size, &type);
-		range_state[i].base_pfn = base;
-		range_state[i].size_pfn = size;
-		range_state[i].type = type;
-	}
-
-	/* Check if we need handle it and can handle it: */
-	if (!mtrr_need_cleanup())
-		return 0;
-
-	/* Print original var MTRRs at first, for debugging: */
-	printk(KERN_DEBUG "original variable MTRRs\n");
-	print_out_mtrr_range_state();
-
-	memset(range, 0, sizeof(range));
-	x_remove_size = 0;
-	x_remove_base = 1 << (32 - PAGE_SHIFT);
-	if (mtrr_tom2)
-		x_remove_size = (mtrr_tom2 >> PAGE_SHIFT) - x_remove_base;
-
-	nr_range = x86_get_mtrr_mem_range(range, 0, x_remove_base, x_remove_size);
-	/*
-	 * [0, 1M) should always be covered by var mtrr with WB
-	 * and fixed mtrrs should take effect before var mtrr for it:
-	 */
-	nr_range = add_range_with_merge(range, RANGE_NUM, nr_range, 0,
-					1ULL<<(20 - PAGE_SHIFT));
-	/* Sort the ranges: */
-	sort_range(range, nr_range);
-
-	range_sums = sum_ranges(range, nr_range);
-	printk(KERN_INFO "total RAM covered: %ldM\n",
-	       range_sums >> (20 - PAGE_SHIFT));
-
-	if (mtrr_chunk_size && mtrr_gran_size) {
-		i = 0;
-		mtrr_calc_range_state(mtrr_chunk_size, mtrr_gran_size,
-				      x_remove_base, x_remove_size, i);
-
-		mtrr_print_out_one_result(i);
-
-		if (!result[i].bad) {
-			set_var_mtrr_all(address_bits);
-			printk(KERN_DEBUG "New variable MTRRs\n");
-			print_out_mtrr_range_state();
-			return 1;
-		}
-		printk(KERN_INFO "invalid mtrr_gran_size or mtrr_chunk_size, "
-		       "will find optimal one\n");
-	}
-
-	i = 0;
-	memset(min_loss_pfn, 0xff, sizeof(min_loss_pfn));
-	memset(result, 0, sizeof(result));
-	for (gran_size = (1ULL<<16); gran_size < (1ULL<<32); gran_size <<= 1) {
-
-		for (chunk_size = gran_size; chunk_size < (1ULL<<32);
-		     chunk_size <<= 1) {
-
-			if (i >= NUM_RESULT)
-				continue;
-
-			mtrr_calc_range_state(chunk_size, gran_size,
-				      x_remove_base, x_remove_size, i);
-			if (debug_print) {
-				mtrr_print_out_one_result(i);
-				printk(KERN_INFO "\n");
-			}
-
-			i++;
-		}
-	}
-
-	/* Try to find the optimal index: */
-	index_good = mtrr_search_optimal_index();
-
-	if (index_good != -1) {
-		printk(KERN_INFO "Found optimal setting for mtrr clean up\n");
-		i = index_good;
-		mtrr_print_out_one_result(i);
-
-		/* Convert ranges to var ranges state: */
-		chunk_size = result[i].chunk_sizek;
-		chunk_size <<= 10;
-		gran_size = result[i].gran_sizek;
-		gran_size <<= 10;
-		x86_setup_var_mtrrs(range, nr_range, chunk_size, gran_size);
-		set_var_mtrr_all(address_bits);
-		printk(KERN_DEBUG "New variable MTRRs\n");
-		print_out_mtrr_range_state();
-		return 1;
-	} else {
-		/* print out all */
-		for (i = 0; i < NUM_RESULT; i++)
-			mtrr_print_out_one_result(i);
-	}
-
-	printk(KERN_INFO "mtrr_cleanup: can not find optimal value\n");
-	printk(KERN_INFO "please specify mtrr_gran_size/mtrr_chunk_size\n");
-
-	return 0;
-}
-#else
-int __init mtrr_cleanup(unsigned address_bits)
-{
-	return 0;
-}
-#endif
-
-static int disable_mtrr_trim;
-
-static int __init disable_mtrr_trim_setup(char *str)
-{
-	disable_mtrr_trim = 1;
-	return 0;
-}
-early_param("disable_mtrr_trim", disable_mtrr_trim_setup);
-
-/*
- * Newer AMD K8s and later CPUs have a special magic MSR way to force WB
- * for memory >4GB. Check for that here.
- * Note this won't check if the MTRRs < 4GB where the magic bit doesn't
- * apply to are wrong, but so far we don't know of any such case in the wild.
- */
-#define Tom2Enabled		(1U << 21)
-#define Tom2ForceMemTypeWB	(1U << 22)
-
-int __init amd_special_default_mtrr(void)
-{
-	u32 l, h;
-
-	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
-		return 0;
-	if (boot_cpu_data.x86 < 0xf)
-		return 0;
-	/* In case some hypervisor doesn't pass SYSCFG through: */
-	if (rdmsr_safe(MSR_K8_SYSCFG, &l, &h) < 0)
-		return 0;
-	/*
-	 * Memory between 4GB and top of mem is forced WB by this magic bit.
-	 * Reserved before K8RevF, but should be zero there.
-	 */
-	if ((l & (Tom2Enabled | Tom2ForceMemTypeWB)) ==
-		 (Tom2Enabled | Tom2ForceMemTypeWB))
-		return 1;
-	return 0;
-}
-
-static u64 __init
-real_trim_memory(unsigned long start_pfn, unsigned long limit_pfn)
-{
-	u64 trim_start, trim_size;
-
-	trim_start = start_pfn;
-	trim_start <<= PAGE_SHIFT;
-
-	trim_size = limit_pfn;
-	trim_size <<= PAGE_SHIFT;
-	trim_size -= trim_start;
-
-	return e820_update_range(trim_start, trim_size, E820_RAM, E820_RESERVED);
-}
-
-/**
- * mtrr_trim_uncached_memory - trim RAM not covered by MTRRs
- * @end_pfn: ending page frame number
- *
- * Some buggy BIOSes don't setup the MTRRs properly for systems with certain
- * memory configurations.  This routine checks that the highest MTRR matches
- * the end of memory, to make sure the MTRRs having a write back type cover
- * all of the memory the kernel is intending to use.  If not, it'll trim any
- * memory off the end by adjusting end_pfn, removing it from the kernel's
- * allocation pools, warning the user with an obnoxious message.
- */
-int __init mtrr_trim_uncached_memory(unsigned long end_pfn)
-{
-	unsigned long i, base, size, highest_pfn = 0, def, dummy;
-	mtrr_type type;
-	u64 total_trim_size;
-	/* extra one for all 0 */
-	int num[MTRR_NUM_TYPES + 1];
-
-	/*
-	 * Make sure we only trim uncachable memory on machines that
-	 * support the Intel MTRR architecture:
-	 */
-	if (!is_cpu(INTEL) || disable_mtrr_trim)
-		return 0;
-
-	rdmsr(MSR_MTRRdefType, def, dummy);
-	def &= 0xff;
-	if (def != MTRR_TYPE_UNCACHABLE)
-		return 0;
-
-	/* Get it and store it aside: */
-	memset(range_state, 0, sizeof(range_state));
-	for (i = 0; i < num_var_ranges; i++) {
-		mtrr_if->get(i, &base, &size, &type);
-		range_state[i].base_pfn = base;
-		range_state[i].size_pfn = size;
-		range_state[i].type = type;
-	}
-
-	/* Find highest cached pfn: */
-	for (i = 0; i < num_var_ranges; i++) {
-		type = range_state[i].type;
-		if (type != MTRR_TYPE_WRBACK)
-			continue;
-		base = range_state[i].base_pfn;
-		size = range_state[i].size_pfn;
-		if (highest_pfn < base + size)
-			highest_pfn = base + size;
-	}
-
-	/* kvm/qemu doesn't have mtrr set right, don't trim them all: */
-	if (!highest_pfn) {
-		printk(KERN_INFO "CPU MTRRs all blank - virtualized system.\n");
-		return 0;
-	}
-
-	/* Check entries number: */
-	memset(num, 0, sizeof(num));
-	for (i = 0; i < num_var_ranges; i++) {
-		type = range_state[i].type;
-		if (type >= MTRR_NUM_TYPES)
-			continue;
-		size = range_state[i].size_pfn;
-		if (!size)
-			type = MTRR_NUM_TYPES;
-		num[type]++;
-	}
-
-	/* No entry for WB? */
-	if (!num[MTRR_TYPE_WRBACK])
-		return 0;
-
-	/* Check if we only had WB and UC: */
-	if (num[MTRR_TYPE_WRBACK] + num[MTRR_TYPE_UNCACHABLE] !=
-		num_var_ranges - num[MTRR_NUM_TYPES])
-		return 0;
-
-	memset(range, 0, sizeof(range));
-	nr_range = 0;
-	if (mtrr_tom2) {
-		range[nr_range].start = (1ULL<<(32 - PAGE_SHIFT));
-		range[nr_range].end = mtrr_tom2 >> PAGE_SHIFT;
-		if (highest_pfn < range[nr_range].end)
-			highest_pfn = range[nr_range].end;
-		nr_range++;
-	}
-	nr_range = x86_get_mtrr_mem_range(range, nr_range, 0, 0);
-
-	/* Check the head: */
-	total_trim_size = 0;
-	if (range[0].start)
-		total_trim_size += real_trim_memory(0, range[0].start);
-
-	/* Check the holes: */
-	for (i = 0; i < nr_range - 1; i++) {
-		if (range[i].end < range[i+1].start)
-			total_trim_size += real_trim_memory(range[i].end,
-							    range[i+1].start);
-	}
-
-	/* Check the top: */
-	i = nr_range - 1;
-	if (range[i].end < end_pfn)
-		total_trim_size += real_trim_memory(range[i].end,
-							 end_pfn);
-
-	if (total_trim_size) {
-		pr_warning("WARNING: BIOS bug: CPU MTRRs don't cover all of memory, losing %lluMB of RAM.\n", total_trim_size >> 20);
-
-		if (!changed_by_mtrr_cleanup)
-			WARN_ON(1);
-
-		pr_info("update e820 for mtrr\n");
-		update_e820();
-
-		return 1;
-	}
-
-	return 0;
-}
diff --git a/ANDROID_3.4.5/arch/x86/kernel/cpu/mtrr/cyrix.c b/ANDROID_3.4.5/arch/x86/kernel/cpu/mtrr/cyrix.c
deleted file mode 100644
index 68a3343e..00000000
--- a/ANDROID_3.4.5/arch/x86/kernel/cpu/mtrr/cyrix.c
+++ /dev/null
@@ -1,282 +0,0 @@
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/mm.h>
-
-#include <asm/processor-cyrix.h>
-#include <asm/processor-flags.h>
-#include <asm/mtrr.h>
-#include <asm/msr.h>
-
-#include "mtrr.h"
-
-static void
-cyrix_get_arr(unsigned int reg, unsigned long *base,
-	      unsigned long *size, mtrr_type * type)
-{
-	unsigned char arr, ccr3, rcr, shift;
-	unsigned long flags;
-
-	arr = CX86_ARR_BASE + (reg << 1) + reg;	/* avoid multiplication by 3 */
-
-	local_irq_save(flags);
-
-	ccr3 = getCx86(CX86_CCR3);
-	setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10);	/* enable MAPEN */
-	((unsigned char *)base)[3] = getCx86(arr);
-	((unsigned char *)base)[2] = getCx86(arr + 1);
-	((unsigned char *)base)[1] = getCx86(arr + 2);
-	rcr = getCx86(CX86_RCR_BASE + reg);
-	setCx86(CX86_CCR3, ccr3);			/* disable MAPEN */
-
-	local_irq_restore(flags);
-
-	shift = ((unsigned char *) base)[1] & 0x0f;
-	*base >>= PAGE_SHIFT;
-
-	/*
-	 * Power of two, at least 4K on ARR0-ARR6, 256K on ARR7
-	 * Note: shift==0xf means 4G, this is unsupported.
-	 */
-	if (shift)
-		*size = (reg < 7 ? 0x1UL : 0x40UL) << (shift - 1);
-	else
-		*size = 0;
-
-	/* Bit 0 is Cache Enable on ARR7, Cache Disable on ARR0-ARR6 */
-	if (reg < 7) {
-		switch (rcr) {
-		case 1:
-			*type = MTRR_TYPE_UNCACHABLE;
-			break;
-		case 8:
-			*type = MTRR_TYPE_WRBACK;
-			break;
-		case 9:
-			*type = MTRR_TYPE_WRCOMB;
-			break;
-		case 24:
-		default:
-			*type = MTRR_TYPE_WRTHROUGH;
-			break;
-		}
-	} else {
-		switch (rcr) {
-		case 0:
-			*type = MTRR_TYPE_UNCACHABLE;
-			break;
-		case 8:
-			*type = MTRR_TYPE_WRCOMB;
-			break;
-		case 9:
-			*type = MTRR_TYPE_WRBACK;
-			break;
-		case 25:
-		default:
-			*type = MTRR_TYPE_WRTHROUGH;
-			break;
-		}
-	}
-}
-
-/*
- * cyrix_get_free_region - get a free ARR.
- *
- * @base: the starting (base) address of the region.
- * @size: the size (in bytes) of the region.
- *
- * Returns: the index of the region on success, else -1 on error.
-*/
-static int
-cyrix_get_free_region(unsigned long base, unsigned long size, int replace_reg)
-{
-	unsigned long lbase, lsize;
-	mtrr_type ltype;
-	int i;
-
-	switch (replace_reg) {
-	case 7:
-		if (size < 0x40)
-			break;
-	case 6:
-	case 5:
-	case 4:
-		return replace_reg;
-	case 3:
-	case 2:
-	case 1:
-	case 0:
-		return replace_reg;
-	}
-	/* If we are to set up a region >32M then look at ARR7 immediately */
-	if (size > 0x2000) {
-		cyrix_get_arr(7, &lbase, &lsize, &ltype);
-		if (lsize == 0)
-			return 7;
-		/* Else try ARR0-ARR6 first  */
-	} else {
-		for (i = 0; i < 7; i++) {
-			cyrix_get_arr(i, &lbase, &lsize, &ltype);
-			if (lsize == 0)
-				return i;
-		}
-		/*
-		 * ARR0-ARR6 isn't free
-		 * try ARR7 but its size must be at least 256K
-		 */
-		cyrix_get_arr(i, &lbase, &lsize, &ltype);
-		if ((lsize == 0) && (size >= 0x40))
-			return i;
-	}
-	return -ENOSPC;
-}
-
-static u32 cr4, ccr3;
-
-static void prepare_set(void)
-{
-	u32 cr0;
-
-	/*  Save value of CR4 and clear Page Global Enable (bit 7)  */
-	if (cpu_has_pge) {
-		cr4 = read_cr4();
-		write_cr4(cr4 & ~X86_CR4_PGE);
-	}
-
-	/*
-	 * Disable and flush caches.
-	 * Note that wbinvd flushes the TLBs as a side-effect
-	 */
-	cr0 = read_cr0() | X86_CR0_CD;
-	wbinvd();
-	write_cr0(cr0);
-	wbinvd();
-
-	/* Cyrix ARRs - everything else was excluded at the top */
-	ccr3 = getCx86(CX86_CCR3);
-
-	/* Cyrix ARRs - everything else was excluded at the top */
-	setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10);
-}
-
-static void post_set(void)
-{
-	/* Flush caches and TLBs */
-	wbinvd();
-
-	/* Cyrix ARRs - everything else was excluded at the top */
-	setCx86(CX86_CCR3, ccr3);
-
-	/* Enable caches */
-	write_cr0(read_cr0() & 0xbfffffff);
-
-	/* Restore value of CR4 */
-	if (cpu_has_pge)
-		write_cr4(cr4);
-}
-
-static void cyrix_set_arr(unsigned int reg, unsigned long base,
-			  unsigned long size, mtrr_type type)
-{
-	unsigned char arr, arr_type, arr_size;
-
-	arr = CX86_ARR_BASE + (reg << 1) + reg;	/* avoid multiplication by 3 */
-
-	/* count down from 32M (ARR0-ARR6) or from 2G (ARR7) */
-	if (reg >= 7)
-		size >>= 6;
-
-	size &= 0x7fff;		/* make sure arr_size <= 14 */
-	for (arr_size = 0; size; arr_size++, size >>= 1)
-		;
-
-	if (reg < 7) {
-		switch (type) {
-		case MTRR_TYPE_UNCACHABLE:
-			arr_type = 1;
-			break;
-		case MTRR_TYPE_WRCOMB:
-			arr_type = 9;
-			break;
-		case MTRR_TYPE_WRTHROUGH:
-			arr_type = 24;
-			break;
-		default:
-			arr_type = 8;
-			break;
-		}
-	} else {
-		switch (type) {
-		case MTRR_TYPE_UNCACHABLE:
-			arr_type = 0;
-			break;
-		case MTRR_TYPE_WRCOMB:
-			arr_type = 8;
-			break;
-		case MTRR_TYPE_WRTHROUGH:
-			arr_type = 25;
-			break;
-		default:
-			arr_type = 9;
-			break;
-		}
-	}
-
-	prepare_set();
-
-	base <<= PAGE_SHIFT;
-	setCx86(arr + 0,  ((unsigned char *)&base)[3]);
-	setCx86(arr + 1,  ((unsigned char *)&base)[2]);
-	setCx86(arr + 2, (((unsigned char *)&base)[1]) | arr_size);
-	setCx86(CX86_RCR_BASE + reg, arr_type);
-
-	post_set();
-}
-
-typedef struct {
-	unsigned long	base;
-	unsigned long	size;
-	mtrr_type	type;
-} arr_state_t;
-
-static arr_state_t arr_state[8] = {
-	{0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL},
-	{0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}
-};
-
-static unsigned char ccr_state[7] = { 0, 0, 0, 0, 0, 0, 0 };
-
-static void cyrix_set_all(void)
-{
-	int i;
-
-	prepare_set();
-
-	/* the CCRs are not contiguous */
-	for (i = 0; i < 4; i++)
-		setCx86(CX86_CCR0 + i, ccr_state[i]);
-	for (; i < 7; i++)
-		setCx86(CX86_CCR4 + i, ccr_state[i]);
-
-	for (i = 0; i < 8; i++) {
-		cyrix_set_arr(i, arr_state[i].base,
-			      arr_state[i].size, arr_state[i].type);
-	}
-
-	post_set();
-}
-
-static const struct mtrr_ops cyrix_mtrr_ops = {
-	.vendor            = X86_VENDOR_CYRIX,
-	.set_all	   = cyrix_set_all,
-	.set               = cyrix_set_arr,
-	.get               = cyrix_get_arr,
-	.get_free_region   = cyrix_get_free_region,
-	.validate_add_page = generic_validate_add_page,
-	.have_wrcomb       = positive_have_wrcomb,
-};
-
-int __init cyrix_init_mtrr(void)
-{
-	set_mtrr_ops(&cyrix_mtrr_ops);
-	return 0;
-}
diff --git a/ANDROID_3.4.5/arch/x86/kernel/cpu/mtrr/generic.c b/ANDROID_3.4.5/arch/x86/kernel/cpu/mtrr/generic.c
deleted file mode 100644
index 75772ae6..00000000
--- a/ANDROID_3.4.5/arch/x86/kernel/cpu/mtrr/generic.c
+++ /dev/null
@@ -1,846 +0,0 @@
-/*
- * This only handles 32bit MTRR on 32bit hosts. This is strictly wrong
- * because MTRRs can span up to 40 bits (36bits on most modern x86)
- */
-#define DEBUG
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/mm.h>
-
-#include <asm/processor-flags.h>
-#include <asm/cpufeature.h>
-#include <asm/tlbflush.h>
-#include <asm/mtrr.h>
-#include <asm/msr.h>
-#include <asm/pat.h>
-
-#include "mtrr.h"
-
-struct fixed_range_block {
-	int base_msr;		/* start address of an MTRR block */
-	int ranges;		/* number of MTRRs in this block  */
-};
-
-static struct fixed_range_block fixed_range_blocks[] = {
-	{ MSR_MTRRfix64K_00000, 1 }, /* one   64k MTRR  */
-	{ MSR_MTRRfix16K_80000, 2 }, /* two   16k MTRRs */
-	{ MSR_MTRRfix4K_C0000,  8 }, /* eight  4k MTRRs */
-	{}
-};
-
-static unsigned long smp_changes_mask;
-static int mtrr_state_set;
-u64 mtrr_tom2;
-
-struct mtrr_state_type mtrr_state;
-EXPORT_SYMBOL_GPL(mtrr_state);
-
-/*
- * BIOS is expected to clear MtrrFixDramModEn bit, see for example
- * "BIOS and Kernel Developer's Guide for the AMD Athlon 64 and AMD
- * Opteron Processors" (26094 Rev. 3.30 February 2006), section
- * "13.2.1.2 SYSCFG Register": "The MtrrFixDramModEn bit should be set
- * to 1 during BIOS initalization of the fixed MTRRs, then cleared to
- * 0 for operation."
- */
-static inline void k8_check_syscfg_dram_mod_en(void)
-{
-	u32 lo, hi;
-
-	if (!((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
-	      (boot_cpu_data.x86 >= 0x0f)))
-		return;
-
-	rdmsr(MSR_K8_SYSCFG, lo, hi);
-	if (lo & K8_MTRRFIXRANGE_DRAM_MODIFY) {
-		printk(KERN_ERR FW_WARN "MTRR: CPU %u: SYSCFG[MtrrFixDramModEn]"
-		       " not cleared by BIOS, clearing this bit\n",
-		       smp_processor_id());
-		lo &= ~K8_MTRRFIXRANGE_DRAM_MODIFY;
-		mtrr_wrmsr(MSR_K8_SYSCFG, lo, hi);
-	}
-}
-
-/* Get the size of contiguous MTRR range */
-static u64 get_mtrr_size(u64 mask)
-{
-	u64 size;
-
-	mask >>= PAGE_SHIFT;
-	mask |= size_or_mask;
-	size = -mask;
-	size <<= PAGE_SHIFT;
-	return size;
-}
-
-/*
- * Check and return the effective type for MTRR-MTRR type overlap.
- * Returns 1 if the effective type is UNCACHEABLE, else returns 0
- */
-static int check_type_overlap(u8 *prev, u8 *curr)
-{
-	if (*prev == MTRR_TYPE_UNCACHABLE || *curr == MTRR_TYPE_UNCACHABLE) {
-		*prev = MTRR_TYPE_UNCACHABLE;
-		*curr = MTRR_TYPE_UNCACHABLE;
-		return 1;
-	}
-
-	if ((*prev == MTRR_TYPE_WRBACK && *curr == MTRR_TYPE_WRTHROUGH) ||
-	    (*prev == MTRR_TYPE_WRTHROUGH && *curr == MTRR_TYPE_WRBACK)) {
-		*prev = MTRR_TYPE_WRTHROUGH;
-		*curr = MTRR_TYPE_WRTHROUGH;
-	}
-
-	if (*prev != *curr) {
-		*prev = MTRR_TYPE_UNCACHABLE;
-		*curr = MTRR_TYPE_UNCACHABLE;
-		return 1;
-	}
-
-	return 0;
-}
-
-/*
- * Error/Semi-error returns:
- * 0xFF - when MTRR is not enabled
- * *repeat == 1 implies [start:end] spanned across MTRR range and type returned
- *		corresponds only to [start:*partial_end].
- *		Caller has to lookup again for [*partial_end:end].
- */
-static u8 __mtrr_type_lookup(u64 start, u64 end, u64 *partial_end, int *repeat)
-{
-	int i;
-	u64 base, mask;
-	u8 prev_match, curr_match;
-
-	*repeat = 0;
-	if (!mtrr_state_set)
-		return 0xFF;
-
-	if (!mtrr_state.enabled)
-		return 0xFF;
-
-	/* Make end inclusive end, instead of exclusive */
-	end--;
-
-	/* Look in fixed ranges. Just return the type as per start */
-	if (mtrr_state.have_fixed && (start < 0x100000)) {
-		int idx;
-
-		if (start < 0x80000) {
-			idx = 0;
-			idx += (start >> 16);
-			return mtrr_state.fixed_ranges[idx];
-		} else if (start < 0xC0000) {
-			idx = 1 * 8;
-			idx += ((start - 0x80000) >> 14);
-			return mtrr_state.fixed_ranges[idx];
-		} else if (start < 0x1000000) {
-			idx = 3 * 8;
-			idx += ((start - 0xC0000) >> 12);
-			return mtrr_state.fixed_ranges[idx];
-		}
-	}
-
-	/*
-	 * Look in variable ranges
-	 * Look of multiple ranges matching this address and pick type
-	 * as per MTRR precedence
-	 */
-	if (!(mtrr_state.enabled & 2))
-		return mtrr_state.def_type;
-
-	prev_match = 0xFF;
-	for (i = 0; i < num_var_ranges; ++i) {
-		unsigned short start_state, end_state;
-
-		if (!(mtrr_state.var_ranges[i].mask_lo & (1 << 11)))
-			continue;
-
-		base = (((u64)mtrr_state.var_ranges[i].base_hi) << 32) +
-		       (mtrr_state.var_ranges[i].base_lo & PAGE_MASK);
-		mask = (((u64)mtrr_state.var_ranges[i].mask_hi) << 32) +
-		       (mtrr_state.var_ranges[i].mask_lo & PAGE_MASK);
-
-		start_state = ((start & mask) == (base & mask));
-		end_state = ((end & mask) == (base & mask));
-
-		if (start_state != end_state) {
-			/*
-			 * We have start:end spanning across an MTRR.
-			 * We split the region into
-			 * either
-			 * (start:mtrr_end) (mtrr_end:end)
-			 * or
-			 * (start:mtrr_start) (mtrr_start:end)
-			 * depending on kind of overlap.
-			 * Return the type for first region and a pointer to
-			 * the start of second region so that caller will
-			 * lookup again on the second region.
-			 * Note: This way we handle multiple overlaps as well.
-			 */
-			if (start_state)
-				*partial_end = base + get_mtrr_size(mask);
-			else
-				*partial_end = base;
-
-			if (unlikely(*partial_end <= start)) {
-				WARN_ON(1);
-				*partial_end = start + PAGE_SIZE;
-			}
-
-			end = *partial_end - 1; /* end is inclusive */
-			*repeat = 1;
-		}
-
-		if ((start & mask) != (base & mask))
-			continue;
-
-		curr_match = mtrr_state.var_ranges[i].base_lo & 0xff;
-		if (prev_match == 0xFF) {
-			prev_match = curr_match;
-			continue;
-		}
-
-		if (check_type_overlap(&prev_match, &curr_match))
-			return curr_match;
-	}
-
-	if (mtrr_tom2) {
-		if (start >= (1ULL<<32) && (end < mtrr_tom2))
-			return MTRR_TYPE_WRBACK;
-	}
-
-	if (prev_match != 0xFF)
-		return prev_match;
-
-	return mtrr_state.def_type;
-}
-
-/*
- * Returns the effective MTRR type for the region
- * Error return:
- * 0xFF - when MTRR is not enabled
- */
-u8 mtrr_type_lookup(u64 start, u64 end)
-{
-	u8 type, prev_type;
-	int repeat;
-	u64 partial_end;
-
-	type = __mtrr_type_lookup(start, end, &partial_end, &repeat);
-
-	/*
-	 * Common path is with repeat = 0.
-	 * However, we can have cases where [start:end] spans across some
-	 * MTRR range. Do repeated lookups for that case here.
-	 */
-	while (repeat) {
-		prev_type = type;
-		start = partial_end;
-		type = __mtrr_type_lookup(start, end, &partial_end, &repeat);
-
-		if (check_type_overlap(&prev_type, &type))
-			return type;
-	}
-
-	return type;
-}
-
-/* Get the MSR pair relating to a var range */
-static void
-get_mtrr_var_range(unsigned int index, struct mtrr_var_range *vr)
-{
-	rdmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi);
-	rdmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi);
-}
-
-/* Fill the MSR pair relating to a var range */
-void fill_mtrr_var_range(unsigned int index,
-		u32 base_lo, u32 base_hi, u32 mask_lo, u32 mask_hi)
-{
-	struct mtrr_var_range *vr;
-
-	vr = mtrr_state.var_ranges;
-
-	vr[index].base_lo = base_lo;
-	vr[index].base_hi = base_hi;
-	vr[index].mask_lo = mask_lo;
-	vr[index].mask_hi = mask_hi;
-}
-
-static void get_fixed_ranges(mtrr_type *frs)
-{
-	unsigned int *p = (unsigned int *)frs;
-	int i;
-
-	k8_check_syscfg_dram_mod_en();
-
-	rdmsr(MSR_MTRRfix64K_00000, p[0], p[1]);
-
-	for (i = 0; i < 2; i++)
-		rdmsr(MSR_MTRRfix16K_80000 + i, p[2 + i * 2], p[3 + i * 2]);
-	for (i = 0; i < 8; i++)
-		rdmsr(MSR_MTRRfix4K_C0000 + i, p[6 + i * 2], p[7 + i * 2]);
-}
-
-void mtrr_save_fixed_ranges(void *info)
-{
-	if (cpu_has_mtrr)
-		get_fixed_ranges(mtrr_state.fixed_ranges);
-}
-
-static unsigned __initdata last_fixed_start;
-static unsigned __initdata last_fixed_end;
-static mtrr_type __initdata last_fixed_type;
-
-static void __init print_fixed_last(void)
-{
-	if (!last_fixed_end)
-		return;
-
-	pr_debug("  %05X-%05X %s\n", last_fixed_start,
-		 last_fixed_end - 1, mtrr_attrib_to_str(last_fixed_type));
-
-	last_fixed_end = 0;
-}
-
-static void __init update_fixed_last(unsigned base, unsigned end,
-				     mtrr_type type)
-{
-	last_fixed_start = base;
-	last_fixed_end = end;
-	last_fixed_type = type;
-}
-
-static void __init
-print_fixed(unsigned base, unsigned step, const mtrr_type *types)
-{
-	unsigned i;
-
-	for (i = 0; i < 8; ++i, ++types, base += step) {
-		if (last_fixed_end == 0) {
-			update_fixed_last(base, base + step, *types);
-			continue;
-		}
-		if (last_fixed_end == base && last_fixed_type == *types) {
-			last_fixed_end = base + step;
-			continue;
-		}
-		/* new segments: gap or different type */
-		print_fixed_last();
-		update_fixed_last(base, base + step, *types);
-	}
-}
-
-static void prepare_set(void);
-static void post_set(void);
-
-static void __init print_mtrr_state(void)
-{
-	unsigned int i;
-	int high_width;
-
-	pr_debug("MTRR default type: %s\n",
-		 mtrr_attrib_to_str(mtrr_state.def_type));
-	if (mtrr_state.have_fixed) {
-		pr_debug("MTRR fixed ranges %sabled:\n",
-			 mtrr_state.enabled & 1 ? "en" : "dis");
-		print_fixed(0x00000, 0x10000, mtrr_state.fixed_ranges + 0);
-		for (i = 0; i < 2; ++i)
-			print_fixed(0x80000 + i * 0x20000, 0x04000,
-				    mtrr_state.fixed_ranges + (i + 1) * 8);
-		for (i = 0; i < 8; ++i)
-			print_fixed(0xC0000 + i * 0x08000, 0x01000,
-				    mtrr_state.fixed_ranges + (i + 3) * 8);
-
-		/* tail */
-		print_fixed_last();
-	}
-	pr_debug("MTRR variable ranges %sabled:\n",
-		 mtrr_state.enabled & 2 ? "en" : "dis");
-	if (size_or_mask & 0xffffffffUL)
-		high_width = ffs(size_or_mask & 0xffffffffUL) - 1;
-	else
-		high_width = ffs(size_or_mask>>32) + 32 - 1;
-	high_width = (high_width - (32 - PAGE_SHIFT) + 3) / 4;
-
-	for (i = 0; i < num_var_ranges; ++i) {
-		if (mtrr_state.var_ranges[i].mask_lo & (1 << 11))
-			pr_debug("  %u base %0*X%05X000 mask %0*X%05X000 %s\n",
-				 i,
-				 high_width,
-				 mtrr_state.var_ranges[i].base_hi,
-				 mtrr_state.var_ranges[i].base_lo >> 12,
-				 high_width,
-				 mtrr_state.var_ranges[i].mask_hi,
-				 mtrr_state.var_ranges[i].mask_lo >> 12,
-				 mtrr_attrib_to_str(mtrr_state.var_ranges[i].base_lo & 0xff));
-		else
-			pr_debug("  %u disabled\n", i);
-	}
-	if (mtrr_tom2)
-		pr_debug("TOM2: %016llx aka %lldM\n", mtrr_tom2, mtrr_tom2>>20);
-}
-
-/* Grab all of the MTRR state for this CPU into *state */
-void __init get_mtrr_state(void)
-{
-	struct mtrr_var_range *vrs;
-	unsigned long flags;
-	unsigned lo, dummy;
-	unsigned int i;
-
-	vrs = mtrr_state.var_ranges;
-
-	rdmsr(MSR_MTRRcap, lo, dummy);
-	mtrr_state.have_fixed = (lo >> 8) & 1;
-
-	for (i = 0; i < num_var_ranges; i++)
-		get_mtrr_var_range(i, &vrs[i]);
-	if (mtrr_state.have_fixed)
-		get_fixed_ranges(mtrr_state.fixed_ranges);
-
-	rdmsr(MSR_MTRRdefType, lo, dummy);
-	mtrr_state.def_type = (lo & 0xff);
-	mtrr_state.enabled = (lo & 0xc00) >> 10;
-
-	if (amd_special_default_mtrr()) {
-		unsigned low, high;
-
-		/* TOP_MEM2 */
-		rdmsr(MSR_K8_TOP_MEM2, low, high);
-		mtrr_tom2 = high;
-		mtrr_tom2 <<= 32;
-		mtrr_tom2 |= low;
-		mtrr_tom2 &= 0xffffff800000ULL;
-	}
-
-	print_mtrr_state();
-
-	mtrr_state_set = 1;
-
-	/* PAT setup for BP. We need to go through sync steps here */
-	local_irq_save(flags);
-	prepare_set();
-
-	pat_init();
-
-	post_set();
-	local_irq_restore(flags);
-}
-
-/* Some BIOS's are messed up and don't set all MTRRs the same! */
-void __init mtrr_state_warn(void)
-{
-	unsigned long mask = smp_changes_mask;
-
-	if (!mask)
-		return;
-	if (mask & MTRR_CHANGE_MASK_FIXED)
-		pr_warning("mtrr: your CPUs had inconsistent fixed MTRR settings\n");
-	if (mask & MTRR_CHANGE_MASK_VARIABLE)
-		pr_warning("mtrr: your CPUs had inconsistent variable MTRR settings\n");
-	if (mask & MTRR_CHANGE_MASK_DEFTYPE)
-		pr_warning("mtrr: your CPUs had inconsistent MTRRdefType settings\n");
-
-	printk(KERN_INFO "mtrr: probably your BIOS does not setup all CPUs.\n");
-	printk(KERN_INFO "mtrr: corrected configuration.\n");
-}
-
-/*
- * Doesn't attempt to pass an error out to MTRR users
- * because it's quite complicated in some cases and probably not
- * worth it because the best error handling is to ignore it.
- */
-void mtrr_wrmsr(unsigned msr, unsigned a, unsigned b)
-{
-	if (wrmsr_safe(msr, a, b) < 0) {
-		printk(KERN_ERR
-			"MTRR: CPU %u: Writing MSR %x to %x:%x failed\n",
-			smp_processor_id(), msr, a, b);
-	}
-}
-
-/**
- * set_fixed_range - checks & updates a fixed-range MTRR if it
- *		     differs from the value it should have
- * @msr: MSR address of the MTTR which should be checked and updated
- * @changed: pointer which indicates whether the MTRR needed to be changed
- * @msrwords: pointer to the MSR values which the MSR should have
- */
-static void set_fixed_range(int msr, bool *changed, unsigned int *msrwords)
-{
-	unsigned lo, hi;
-
-	rdmsr(msr, lo, hi);
-
-	if (lo != msrwords[0] || hi != msrwords[1]) {
-		mtrr_wrmsr(msr, msrwords[0], msrwords[1]);
-		*changed = true;
-	}
-}
-
-/**
- * generic_get_free_region - Get a free MTRR.
- * @base: The starting (base) address of the region.
- * @size: The size (in bytes) of the region.
- * @replace_reg: mtrr index to be replaced; set to invalid value if none.
- *
- * Returns: The index of the region on success, else negative on error.
- */
-int
-generic_get_free_region(unsigned long base, unsigned long size, int replace_reg)
-{
-	unsigned long lbase, lsize;
-	mtrr_type ltype;
-	int i, max;
-
-	max = num_var_ranges;
-	if (replace_reg >= 0 && replace_reg < max)
-		return replace_reg;
-
-	for (i = 0; i < max; ++i) {
-		mtrr_if->get(i, &lbase, &lsize, &ltype);
-		if (lsize == 0)
-			return i;
-	}
-
-	return -ENOSPC;
-}
-
-static void generic_get_mtrr(unsigned int reg, unsigned long *base,
-			     unsigned long *size, mtrr_type *type)
-{
-	unsigned int mask_lo, mask_hi, base_lo, base_hi;
-	unsigned int tmp, hi;
-
-	/*
-	 * get_mtrr doesn't need to update mtrr_state, also it could be called
-	 * from any cpu, so try to print it out directly.
-	 */
-	get_cpu();
-
-	rdmsr(MTRRphysMask_MSR(reg), mask_lo, mask_hi);
-
-	if ((mask_lo & 0x800) == 0) {
-		/*  Invalid (i.e. free) range */
-		*base = 0;
-		*size = 0;
-		*type = 0;
-		goto out_put_cpu;
-	}
-
-	rdmsr(MTRRphysBase_MSR(reg), base_lo, base_hi);
-
-	/* Work out the shifted address mask: */
-	tmp = mask_hi << (32 - PAGE_SHIFT) | mask_lo >> PAGE_SHIFT;
-	mask_lo = size_or_mask | tmp;
-
-	/* Expand tmp with high bits to all 1s: */
-	hi = fls(tmp);
-	if (hi > 0) {
-		tmp |= ~((1<<(hi - 1)) - 1);
-
-		if (tmp != mask_lo) {
-			printk(KERN_WARNING "mtrr: your BIOS has configured an incorrect mask, fixing it.\n");
-			add_taint(TAINT_FIRMWARE_WORKAROUND);
-			mask_lo = tmp;
-		}
-	}
-
-	/*
-	 * This works correctly if size is a power of two, i.e. a
-	 * contiguous range:
-	 */
-	*size = -mask_lo;
-	*base = base_hi << (32 - PAGE_SHIFT) | base_lo >> PAGE_SHIFT;
-	*type = base_lo & 0xff;
-
-out_put_cpu:
-	put_cpu();
-}
-
-/**
- * set_fixed_ranges - checks & updates the fixed-range MTRRs if they
- *		      differ from the saved set
- * @frs: pointer to fixed-range MTRR values, saved by get_fixed_ranges()
- */
-static int set_fixed_ranges(mtrr_type *frs)
-{
-	unsigned long long *saved = (unsigned long long *)frs;
-	bool changed = false;
-	int block = -1, range;
-
-	k8_check_syscfg_dram_mod_en();
-
-	while (fixed_range_blocks[++block].ranges) {
-		for (range = 0; range < fixed_range_blocks[block].ranges; range++)
-			set_fixed_range(fixed_range_blocks[block].base_msr + range,
-					&changed, (unsigned int *)saved++);
-	}
-
-	return changed;
-}
-
-/*
- * Set the MSR pair relating to a var range.
- * Returns true if changes are made.
- */
-static bool set_mtrr_var_ranges(unsigned int index, struct mtrr_var_range *vr)
-{
-	unsigned int lo, hi;
-	bool changed = false;
-
-	rdmsr(MTRRphysBase_MSR(index), lo, hi);
-	if ((vr->base_lo & 0xfffff0ffUL) != (lo & 0xfffff0ffUL)
-	    || (vr->base_hi & (size_and_mask >> (32 - PAGE_SHIFT))) !=
-		(hi & (size_and_mask >> (32 - PAGE_SHIFT)))) {
-
-		mtrr_wrmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi);
-		changed = true;
-	}
-
-	rdmsr(MTRRphysMask_MSR(index), lo, hi);
-
-	if ((vr->mask_lo & 0xfffff800UL) != (lo & 0xfffff800UL)
-	    || (vr->mask_hi & (size_and_mask >> (32 - PAGE_SHIFT))) !=
-		(hi & (size_and_mask >> (32 - PAGE_SHIFT)))) {
-		mtrr_wrmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi);
-		changed = true;
-	}
-	return changed;
-}
-
-static u32 deftype_lo, deftype_hi;
-
-/**
- * set_mtrr_state - Set the MTRR state for this CPU.
- *
- * NOTE: The CPU must already be in a safe state for MTRR changes.
- * RETURNS: 0 if no changes made, else a mask indicating what was changed.
- */
-static unsigned long set_mtrr_state(void)
-{
-	unsigned long change_mask = 0;
-	unsigned int i;
-
-	for (i = 0; i < num_var_ranges; i++) {
-		if (set_mtrr_var_ranges(i, &mtrr_state.var_ranges[i]))
-			change_mask |= MTRR_CHANGE_MASK_VARIABLE;
-	}
-
-	if (mtrr_state.have_fixed && set_fixed_ranges(mtrr_state.fixed_ranges))
-		change_mask |= MTRR_CHANGE_MASK_FIXED;
-
-	/*
-	 * Set_mtrr_restore restores the old value of MTRRdefType,
-	 * so to set it we fiddle with the saved value:
-	 */
-	if ((deftype_lo & 0xff) != mtrr_state.def_type
-	    || ((deftype_lo & 0xc00) >> 10) != mtrr_state.enabled) {
-
-		deftype_lo = (deftype_lo & ~0xcff) | mtrr_state.def_type |
-			     (mtrr_state.enabled << 10);
-		change_mask |= MTRR_CHANGE_MASK_DEFTYPE;
-	}
-
-	return change_mask;
-}
-
-
-static unsigned long cr4;
-static DEFINE_RAW_SPINLOCK(set_atomicity_lock);
-
-/*
- * Since we are disabling the cache don't allow any interrupts,
- * they would run extremely slow and would only increase the pain.
- *
- * The caller must ensure that local interrupts are disabled and
- * are reenabled after post_set() has been called.
- */
-static void prepare_set(void) __acquires(set_atomicity_lock)
-{
-	unsigned long cr0;
-
-	/*
-	 * Note that this is not ideal
-	 * since the cache is only flushed/disabled for this CPU while the
-	 * MTRRs are changed, but changing this requires more invasive
-	 * changes to the way the kernel boots
-	 */
-
-	raw_spin_lock(&set_atomicity_lock);
-
-	/* Enter the no-fill (CD=1, NW=0) cache mode and flush caches. */
-	cr0 = read_cr0() | X86_CR0_CD;
-	write_cr0(cr0);
-	wbinvd();
-
-	/* Save value of CR4 and clear Page Global Enable (bit 7) */
-	if (cpu_has_pge) {
-		cr4 = read_cr4();
-		write_cr4(cr4 & ~X86_CR4_PGE);
-	}
-
-	/* Flush all TLBs via a mov %cr3, %reg; mov %reg, %cr3 */
-	__flush_tlb();
-
-	/* Save MTRR state */
-	rdmsr(MSR_MTRRdefType, deftype_lo, deftype_hi);
-
-	/* Disable MTRRs, and set the default type to uncached */
-	mtrr_wrmsr(MSR_MTRRdefType, deftype_lo & ~0xcff, deftype_hi);
-	wbinvd();
-}
-
-static void post_set(void) __releases(set_atomicity_lock)
-{
-	/* Flush TLBs (no need to flush caches - they are disabled) */
-	__flush_tlb();
-
-	/* Intel (P6) standard MTRRs */
-	mtrr_wrmsr(MSR_MTRRdefType, deftype_lo, deftype_hi);
-
-	/* Enable caches */
-	write_cr0(read_cr0() & 0xbfffffff);
-
-	/* Restore value of CR4 */
-	if (cpu_has_pge)
-		write_cr4(cr4);
-	raw_spin_unlock(&set_atomicity_lock);
-}
-
-static void generic_set_all(void)
-{
-	unsigned long mask, count;
-	unsigned long flags;
-
-	local_irq_save(flags);
-	prepare_set();
-
-	/* Actually set the state */
-	mask = set_mtrr_state();
-
-	/* also set PAT */
-	pat_init();
-
-	post_set();
-	local_irq_restore(flags);
-
-	/* Use the atomic bitops to update the global mask */
-	for (count = 0; count < sizeof mask * 8; ++count) {
-		if (mask & 0x01)
-			set_bit(count, &smp_changes_mask);
-		mask >>= 1;
-	}
-
-}
-
-/**
- * generic_set_mtrr - set variable MTRR register on the local CPU.
- *
- * @reg: The register to set.
- * @base: The base address of the region.
- * @size: The size of the region. If this is 0 the region is disabled.
- * @type: The type of the region.
- *
- * Returns nothing.
- */
-static void generic_set_mtrr(unsigned int reg, unsigned long base,
-			     unsigned long size, mtrr_type type)
-{
-	unsigned long flags;
-	struct mtrr_var_range *vr;
-
-	vr = &mtrr_state.var_ranges[reg];
-
-	local_irq_save(flags);
-	prepare_set();
-
-	if (size == 0) {
-		/*
-		 * The invalid bit is kept in the mask, so we simply
-		 * clear the relevant mask register to disable a range.
-		 */
-		mtrr_wrmsr(MTRRphysMask_MSR(reg), 0, 0);
-		memset(vr, 0, sizeof(struct mtrr_var_range));
-	} else {
-		vr->base_lo = base << PAGE_SHIFT | type;
-		vr->base_hi = (base & size_and_mask) >> (32 - PAGE_SHIFT);
-		vr->mask_lo = -size << PAGE_SHIFT | 0x800;
-		vr->mask_hi = (-size & size_and_mask) >> (32 - PAGE_SHIFT);
-
-		mtrr_wrmsr(MTRRphysBase_MSR(reg), vr->base_lo, vr->base_hi);
-		mtrr_wrmsr(MTRRphysMask_MSR(reg), vr->mask_lo, vr->mask_hi);
-	}
-
-	post_set();
-	local_irq_restore(flags);
-}
-
-int generic_validate_add_page(unsigned long base, unsigned long size,
-			      unsigned int type)
-{
-	unsigned long lbase, last;
-
-	/*
-	 * For Intel PPro stepping <= 7
-	 * must be 4 MiB aligned and not touch 0x70000000 -> 0x7003FFFF
-	 */
-	if (is_cpu(INTEL) && boot_cpu_data.x86 == 6 &&
-	    boot_cpu_data.x86_model == 1 &&
-	    boot_cpu_data.x86_mask <= 7) {
-		if (base & ((1 << (22 - PAGE_SHIFT)) - 1)) {
-			pr_warning("mtrr: base(0x%lx000) is not 4 MiB aligned\n", base);
-			return -EINVAL;
-		}
-		if (!(base + size < 0x70000 || base > 0x7003F) &&
-		    (type == MTRR_TYPE_WRCOMB
-		     || type == MTRR_TYPE_WRBACK)) {
-			pr_warning("mtrr: writable mtrr between 0x70000000 and 0x7003FFFF may hang the CPU.\n");
-			return -EINVAL;
-		}
-	}
-
-	/*
-	 * Check upper bits of base and last are equal and lower bits are 0
-	 * for base and 1 for last
-	 */
-	last = base + size - 1;
-	for (lbase = base; !(lbase & 1) && (last & 1);
-	     lbase = lbase >> 1, last = last >> 1)
-		;
-	if (lbase != last) {
-		pr_warning("mtrr: base(0x%lx000) is not aligned on a size(0x%lx000) boundary\n", base, size);
-		return -EINVAL;
-	}
-	return 0;
-}
-
-static int generic_have_wrcomb(void)
-{
-	unsigned long config, dummy;
-	rdmsr(MSR_MTRRcap, config, dummy);
-	return config & (1 << 10);
-}
-
-int positive_have_wrcomb(void)
-{
-	return 1;
-}
-
-/*
- * Generic structure...
- */
-const struct mtrr_ops generic_mtrr_ops = {
-	.use_intel_if		= 1,
-	.set_all		= generic_set_all,
-	.get			= generic_get_mtrr,
-	.get_free_region	= generic_get_free_region,
-	.set			= generic_set_mtrr,
-	.validate_add_page	= generic_validate_add_page,
-	.have_wrcomb		= generic_have_wrcomb,
-};
diff --git a/ANDROID_3.4.5/arch/x86/kernel/cpu/mtrr/if.c b/ANDROID_3.4.5/arch/x86/kernel/cpu/mtrr/if.c
deleted file mode 100644
index a041e094..00000000
--- a/ANDROID_3.4.5/arch/x86/kernel/cpu/mtrr/if.c
+++ /dev/null
@@ -1,451 +0,0 @@
-#include <linux/capability.h>
-#include <linux/seq_file.h>
-#include <linux/uaccess.h>
-#include <linux/proc_fs.h>
-#include <linux/module.h>
-#include <linux/ctype.h>
-#include <linux/string.h>
-#include <linux/slab.h>
-#include <linux/init.h>
-
-#define LINE_SIZE 80
-
-#include <asm/mtrr.h>
-
-#include "mtrr.h"
-
-#define FILE_FCOUNT(f) (((struct seq_file *)((f)->private_data))->private)
-
-static const char *const mtrr_strings[MTRR_NUM_TYPES] =
-{
-	"uncachable",		/* 0 */
-	"write-combining",	/* 1 */
-	"?",			/* 2 */
-	"?",			/* 3 */
-	"write-through",	/* 4 */
-	"write-protect",	/* 5 */
-	"write-back",		/* 6 */
-};
-
-const char *mtrr_attrib_to_str(int x)
-{
-	return (x <= 6) ? mtrr_strings[x] : "?";
-}
-
-#ifdef CONFIG_PROC_FS
-
-static int
-mtrr_file_add(unsigned long base, unsigned long size,
-	      unsigned int type, bool increment, struct file *file, int page)
-{
-	unsigned int *fcount = FILE_FCOUNT(file);
-	int reg, max;
-
-	max = num_var_ranges;
-	if (fcount == NULL) {
-		fcount = kzalloc(max * sizeof *fcount, GFP_KERNEL);
-		if (!fcount)
-			return -ENOMEM;
-		FILE_FCOUNT(file) = fcount;
-	}
-	if (!page) {
-		if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1)))
-			return -EINVAL;
-		base >>= PAGE_SHIFT;
-		size >>= PAGE_SHIFT;
-	}
-	reg = mtrr_add_page(base, size, type, true);
-	if (reg >= 0)
-		++fcount[reg];
-	return reg;
-}
-
-static int
-mtrr_file_del(unsigned long base, unsigned long size,
-	      struct file *file, int page)
-{
-	unsigned int *fcount = FILE_FCOUNT(file);
-	int reg;
-
-	if (!page) {
-		if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1)))
-			return -EINVAL;
-		base >>= PAGE_SHIFT;
-		size >>= PAGE_SHIFT;
-	}
-	reg = mtrr_del_page(-1, base, size);
-	if (reg < 0)
-		return reg;
-	if (fcount == NULL)
-		return reg;
-	if (fcount[reg] < 1)
-		return -EINVAL;
-	--fcount[reg];
-	return reg;
-}
-
-/*
- * seq_file can seek but we ignore it.
- *
- * Format of control line:
- *    "base=%Lx size=%Lx type=%s" or "disable=%d"
- */
-static ssize_t
-mtrr_write(struct file *file, const char __user *buf, size_t len, loff_t * ppos)
-{
-	int i, err;
-	unsigned long reg;
-	unsigned long long base, size;
-	char *ptr;
-	char line[LINE_SIZE];
-	int length;
-	size_t linelen;
-
-	if (!capable(CAP_SYS_ADMIN))
-		return -EPERM;
-
-	memset(line, 0, LINE_SIZE);
-
-	length = len;
-	length--;
-
-	if (length > LINE_SIZE - 1)
-		length = LINE_SIZE - 1;
-
-	if (length < 0)
-		return -EINVAL;
-
-	if (copy_from_user(line, buf, length))
-		return -EFAULT;
-
-	linelen = strlen(line);
-	ptr = line + linelen - 1;
-	if (linelen && *ptr == '\n')
-		*ptr = '\0';
-
-	if (!strncmp(line, "disable=", 8)) {
-		reg = simple_strtoul(line + 8, &ptr, 0);
-		err = mtrr_del_page(reg, 0, 0);
-		if (err < 0)
-			return err;
-		return len;
-	}
-
-	if (strncmp(line, "base=", 5))
-		return -EINVAL;
-
-	base = simple_strtoull(line + 5, &ptr, 0);
-	ptr = skip_spaces(ptr);
-
-	if (strncmp(ptr, "size=", 5))
-		return -EINVAL;
-
-	size = simple_strtoull(ptr + 5, &ptr, 0);
-	if ((base & 0xfff) || (size & 0xfff))
-		return -EINVAL;
-	ptr = skip_spaces(ptr);
-
-	if (strncmp(ptr, "type=", 5))
-		return -EINVAL;
-	ptr = skip_spaces(ptr + 5);
-
-	for (i = 0; i < MTRR_NUM_TYPES; ++i) {
-		if (strcmp(ptr, mtrr_strings[i]))
-			continue;
-		base >>= PAGE_SHIFT;
-		size >>= PAGE_SHIFT;
-		err = mtrr_add_page((unsigned long)base, (unsigned long)size, i, true);
-		if (err < 0)
-			return err;
-		return len;
-	}
-	return -EINVAL;
-}
-
-static long
-mtrr_ioctl(struct file *file, unsigned int cmd, unsigned long __arg)
-{
-	int err = 0;
-	mtrr_type type;
-	unsigned long base;
-	unsigned long size;
-	struct mtrr_sentry sentry;
-	struct mtrr_gentry gentry;
-	void __user *arg = (void __user *) __arg;
-
-	switch (cmd) {
-	case MTRRIOC_ADD_ENTRY:
-	case MTRRIOC_SET_ENTRY:
-	case MTRRIOC_DEL_ENTRY:
-	case MTRRIOC_KILL_ENTRY:
-	case MTRRIOC_ADD_PAGE_ENTRY:
-	case MTRRIOC_SET_PAGE_ENTRY:
-	case MTRRIOC_DEL_PAGE_ENTRY:
-	case MTRRIOC_KILL_PAGE_ENTRY:
-		if (copy_from_user(&sentry, arg, sizeof sentry))
-			return -EFAULT;
-		break;
-	case MTRRIOC_GET_ENTRY:
-	case MTRRIOC_GET_PAGE_ENTRY:
-		if (copy_from_user(&gentry, arg, sizeof gentry))
-			return -EFAULT;
-		break;
-#ifdef CONFIG_COMPAT
-	case MTRRIOC32_ADD_ENTRY:
-	case MTRRIOC32_SET_ENTRY:
-	case MTRRIOC32_DEL_ENTRY:
-	case MTRRIOC32_KILL_ENTRY:
-	case MTRRIOC32_ADD_PAGE_ENTRY:
-	case MTRRIOC32_SET_PAGE_ENTRY:
-	case MTRRIOC32_DEL_PAGE_ENTRY:
-	case MTRRIOC32_KILL_PAGE_ENTRY: {
-		struct mtrr_sentry32 __user *s32;
-
-		s32 = (struct mtrr_sentry32 __user *)__arg;
-		err = get_user(sentry.base, &s32->base);
-		err |= get_user(sentry.size, &s32->size);
-		err |= get_user(sentry.type, &s32->type);
-		if (err)
-			return err;
-		break;
-	}
-	case MTRRIOC32_GET_ENTRY:
-	case MTRRIOC32_GET_PAGE_ENTRY: {
-		struct mtrr_gentry32 __user *g32;
-
-		g32 = (struct mtrr_gentry32 __user *)__arg;
-		err = get_user(gentry.regnum, &g32->regnum);
-		err |= get_user(gentry.base, &g32->base);
-		err |= get_user(gentry.size, &g32->size);
-		err |= get_user(gentry.type, &g32->type);
-		if (err)
-			return err;
-		break;
-	}
-#endif
-	}
-
-	switch (cmd) {
-	default:
-		return -ENOTTY;
-	case MTRRIOC_ADD_ENTRY:
-#ifdef CONFIG_COMPAT
-	case MTRRIOC32_ADD_ENTRY:
-#endif
-		if (!capable(CAP_SYS_ADMIN))
-			return -EPERM;
-		err =
-		    mtrr_file_add(sentry.base, sentry.size, sentry.type, true,
-				  file, 0);
-		break;
-	case MTRRIOC_SET_ENTRY:
-#ifdef CONFIG_COMPAT
-	case MTRRIOC32_SET_ENTRY:
-#endif
-		if (!capable(CAP_SYS_ADMIN))
-			return -EPERM;
-		err = mtrr_add(sentry.base, sentry.size, sentry.type, false);
-		break;
-	case MTRRIOC_DEL_ENTRY:
-#ifdef CONFIG_COMPAT
-	case MTRRIOC32_DEL_ENTRY:
-#endif
-		if (!capable(CAP_SYS_ADMIN))
-			return -EPERM;
-		err = mtrr_file_del(sentry.base, sentry.size, file, 0);
-		break;
-	case MTRRIOC_KILL_ENTRY:
-#ifdef CONFIG_COMPAT
-	case MTRRIOC32_KILL_ENTRY:
-#endif
-		if (!capable(CAP_SYS_ADMIN))
-			return -EPERM;
-		err = mtrr_del(-1, sentry.base, sentry.size);
-		break;
-	case MTRRIOC_GET_ENTRY:
-#ifdef CONFIG_COMPAT
-	case MTRRIOC32_GET_ENTRY:
-#endif
-		if (gentry.regnum >= num_var_ranges)
-			return -EINVAL;
-		mtrr_if->get(gentry.regnum, &base, &size, &type);
-
-		/* Hide entries that go above 4GB */
-		if (base + size - 1 >= (1UL << (8 * sizeof(gentry.size) - PAGE_SHIFT))
-		    || size >= (1UL << (8 * sizeof(gentry.size) - PAGE_SHIFT)))
-			gentry.base = gentry.size = gentry.type = 0;
-		else {
-			gentry.base = base << PAGE_SHIFT;
-			gentry.size = size << PAGE_SHIFT;
-			gentry.type = type;
-		}
-
-		break;
-	case MTRRIOC_ADD_PAGE_ENTRY:
-#ifdef CONFIG_COMPAT
-	case MTRRIOC32_ADD_PAGE_ENTRY:
-#endif
-		if (!capable(CAP_SYS_ADMIN))
-			return -EPERM;
-		err =
-		    mtrr_file_add(sentry.base, sentry.size, sentry.type, true,
-				  file, 1);
-		break;
-	case MTRRIOC_SET_PAGE_ENTRY:
-#ifdef CONFIG_COMPAT
-	case MTRRIOC32_SET_PAGE_ENTRY:
-#endif
-		if (!capable(CAP_SYS_ADMIN))
-			return -EPERM;
-		err =
-		    mtrr_add_page(sentry.base, sentry.size, sentry.type, false);
-		break;
-	case MTRRIOC_DEL_PAGE_ENTRY:
-#ifdef CONFIG_COMPAT
-	case MTRRIOC32_DEL_PAGE_ENTRY:
-#endif
-		if (!capable(CAP_SYS_ADMIN))
-			return -EPERM;
-		err = mtrr_file_del(sentry.base, sentry.size, file, 1);
-		break;
-	case MTRRIOC_KILL_PAGE_ENTRY:
-#ifdef CONFIG_COMPAT
-	case MTRRIOC32_KILL_PAGE_ENTRY:
-#endif
-		if (!capable(CAP_SYS_ADMIN))
-			return -EPERM;
-		err = mtrr_del_page(-1, sentry.base, sentry.size);
-		break;
-	case MTRRIOC_GET_PAGE_ENTRY:
-#ifdef CONFIG_COMPAT
-	case MTRRIOC32_GET_PAGE_ENTRY:
-#endif
-		if (gentry.regnum >= num_var_ranges)
-			return -EINVAL;
-		mtrr_if->get(gentry.regnum, &base, &size, &type);
-		/* Hide entries that would overflow */
-		if (size != (__typeof__(gentry.size))size)
-			gentry.base = gentry.size = gentry.type = 0;
-		else {
-			gentry.base = base;
-			gentry.size = size;
-			gentry.type = type;
-		}
-		break;
-	}
-
-	if (err)
-		return err;
-
-	switch (cmd) {
-	case MTRRIOC_GET_ENTRY:
-	case MTRRIOC_GET_PAGE_ENTRY:
-		if (copy_to_user(arg, &gentry, sizeof gentry))
-			err = -EFAULT;
-		break;
-#ifdef CONFIG_COMPAT
-	case MTRRIOC32_GET_ENTRY:
-	case MTRRIOC32_GET_PAGE_ENTRY: {
-		struct mtrr_gentry32 __user *g32;
-
-		g32 = (struct mtrr_gentry32 __user *)__arg;
-		err = put_user(gentry.base, &g32->base);
-		err |= put_user(gentry.size, &g32->size);
-		err |= put_user(gentry.regnum, &g32->regnum);
-		err |= put_user(gentry.type, &g32->type);
-		break;
-	}
-#endif
-	}
-	return err;
-}
-
-static int mtrr_close(struct inode *ino, struct file *file)
-{
-	unsigned int *fcount = FILE_FCOUNT(file);
-	int i, max;
-
-	if (fcount != NULL) {
-		max = num_var_ranges;
-		for (i = 0; i < max; ++i) {
-			while (fcount[i] > 0) {
-				mtrr_del(i, 0, 0);
-				--fcount[i];
-			}
-		}
-		kfree(fcount);
-		FILE_FCOUNT(file) = NULL;
-	}
-	return single_release(ino, file);
-}
-
-static int mtrr_seq_show(struct seq_file *seq, void *offset);
-
-static int mtrr_open(struct inode *inode, struct file *file)
-{
-	if (!mtrr_if)
-		return -EIO;
-	if (!mtrr_if->get)
-		return -ENXIO;
-	return single_open(file, mtrr_seq_show, NULL);
-}
-
-static const struct file_operations mtrr_fops = {
-	.owner			= THIS_MODULE,
-	.open			= mtrr_open,
-	.read			= seq_read,
-	.llseek			= seq_lseek,
-	.write			= mtrr_write,
-	.unlocked_ioctl		= mtrr_ioctl,
-	.compat_ioctl		= mtrr_ioctl,
-	.release		= mtrr_close,
-};
-
-static int mtrr_seq_show(struct seq_file *seq, void *offset)
-{
-	char factor;
-	int i, max, len;
-	mtrr_type type;
-	unsigned long base, size;
-
-	len = 0;
-	max = num_var_ranges;
-	for (i = 0; i < max; i++) {
-		mtrr_if->get(i, &base, &size, &type);
-		if (size == 0) {
-			mtrr_usage_table[i] = 0;
-			continue;
-		}
-		if (size < (0x100000 >> PAGE_SHIFT)) {
-			/* less than 1MB */
-			factor = 'K';
-			size <<= PAGE_SHIFT - 10;
-		} else {
-			factor = 'M';
-			size >>= 20 - PAGE_SHIFT;
-		}
-		/* Base can be > 32bit */
-		len += seq_printf(seq, "reg%02i: base=0x%06lx000 "
-			"(%5luMB), size=%5lu%cB, count=%d: %s\n",
-			i, base, base >> (20 - PAGE_SHIFT), size,
-			factor, mtrr_usage_table[i],
-			mtrr_attrib_to_str(type));
-	}
-	return 0;
-}
-
-static int __init mtrr_if_init(void)
-{
-	struct cpuinfo_x86 *c = &boot_cpu_data;
-
-	if ((!cpu_has(c, X86_FEATURE_MTRR)) &&
-	    (!cpu_has(c, X86_FEATURE_K6_MTRR)) &&
-	    (!cpu_has(c, X86_FEATURE_CYRIX_ARR)) &&
-	    (!cpu_has(c, X86_FEATURE_CENTAUR_MCR)))
-		return -ENODEV;
-
-	proc_create("mtrr", S_IWUSR | S_IRUGO, NULL, &mtrr_fops);
-	return 0;
-}
-arch_initcall(mtrr_if_init);
-#endif			/*  CONFIG_PROC_FS  */
diff --git a/ANDROID_3.4.5/arch/x86/kernel/cpu/mtrr/main.c b/ANDROID_3.4.5/arch/x86/kernel/cpu/mtrr/main.c
deleted file mode 100644
index 6b96110b..00000000
--- a/ANDROID_3.4.5/arch/x86/kernel/cpu/mtrr/main.c
+++ /dev/null
@@ -1,764 +0,0 @@
-/*  Generic MTRR (Memory Type Range Register) driver.
-
-    Copyright (C) 1997-2000  Richard Gooch
-    Copyright (c) 2002	     Patrick Mochel
-
-    This library is free software; you can redistribute it and/or
-    modify it under the terms of the GNU Library General Public
-    License as published by the Free Software Foundation; either
-    version 2 of the License, or (at your option) any later version.
-
-    This library is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-    Library General Public License for more details.
-
-    You should have received a copy of the GNU Library General Public
-    License along with this library; if not, write to the Free
-    Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-
-    Richard Gooch may be reached by email at  rgooch@atnf.csiro.au
-    The postal address is:
-      Richard Gooch, c/o ATNF, P. O. Box 76, Epping, N.S.W., 2121, Australia.
-
-    Source: "Pentium Pro Family Developer's Manual, Volume 3:
-    Operating System Writer's Guide" (Intel document number 242692),
-    section 11.11.7
-
-    This was cleaned and made readable by Patrick Mochel <mochel@osdl.org>
-    on 6-7 March 2002.
-    Source: Intel Architecture Software Developers Manual, Volume 3:
-    System Programming Guide; Section 9.11. (1997 edition - PPro).
-*/
-
-#define DEBUG
-
-#include <linux/types.h> /* FIXME: kvm_para.h needs this */
-
-#include <linux/stop_machine.h>
-#include <linux/kvm_para.h>
-#include <linux/uaccess.h>
-#include <linux/module.h>
-#include <linux/mutex.h>
-#include <linux/init.h>
-#include <linux/sort.h>
-#include <linux/cpu.h>
-#include <linux/pci.h>
-#include <linux/smp.h>
-#include <linux/syscore_ops.h>
-
-#include <asm/processor.h>
-#include <asm/e820.h>
-#include <asm/mtrr.h>
-#include <asm/msr.h>
-
-#include "mtrr.h"
-
-u32 num_var_ranges;
-
-unsigned int mtrr_usage_table[MTRR_MAX_VAR_RANGES];
-static DEFINE_MUTEX(mtrr_mutex);
-
-u64 size_or_mask, size_and_mask;
-static bool mtrr_aps_delayed_init;
-
-static const struct mtrr_ops *mtrr_ops[X86_VENDOR_NUM];
-
-const struct mtrr_ops *mtrr_if;
-
-static void set_mtrr(unsigned int reg, unsigned long base,
-		     unsigned long size, mtrr_type type);
-
-void set_mtrr_ops(const struct mtrr_ops *ops)
-{
-	if (ops->vendor && ops->vendor < X86_VENDOR_NUM)
-		mtrr_ops[ops->vendor] = ops;
-}
-
-/*  Returns non-zero if we have the write-combining memory type  */
-static int have_wrcomb(void)
-{
-	struct pci_dev *dev;
-
-	dev = pci_get_class(PCI_CLASS_BRIDGE_HOST << 8, NULL);
-	if (dev != NULL) {
-		/*
-		 * ServerWorks LE chipsets < rev 6 have problems with
-		 * write-combining. Don't allow it and leave room for other
-		 * chipsets to be tagged
-		 */
-		if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
-		    dev->device == PCI_DEVICE_ID_SERVERWORKS_LE &&
-		    dev->revision <= 5) {
-			pr_info("mtrr: Serverworks LE rev < 6 detected. Write-combining disabled.\n");
-			pci_dev_put(dev);
-			return 0;
-		}
-		/*
-		 * Intel 450NX errata # 23. Non ascending cacheline evictions to
-		 * write combining memory may resulting in data corruption
-		 */
-		if (dev->vendor == PCI_VENDOR_ID_INTEL &&
-		    dev->device == PCI_DEVICE_ID_INTEL_82451NX) {
-			pr_info("mtrr: Intel 450NX MMC detected. Write-combining disabled.\n");
-			pci_dev_put(dev);
-			return 0;
-		}
-		pci_dev_put(dev);
-	}
-	return mtrr_if->have_wrcomb ? mtrr_if->have_wrcomb() : 0;
-}
-
-/*  This function returns the number of variable MTRRs  */
-static void __init set_num_var_ranges(void)
-{
-	unsigned long config = 0, dummy;
-
-	if (use_intel())
-		rdmsr(MSR_MTRRcap, config, dummy);
-	else if (is_cpu(AMD))
-		config = 2;
-	else if (is_cpu(CYRIX) || is_cpu(CENTAUR))
-		config = 8;
-
-	num_var_ranges = config & 0xff;
-}
-
-static void __init init_table(void)
-{
-	int i, max;
-
-	max = num_var_ranges;
-	for (i = 0; i < max; i++)
-		mtrr_usage_table[i] = 1;
-}
-
-struct set_mtrr_data {
-	unsigned long	smp_base;
-	unsigned long	smp_size;
-	unsigned int	smp_reg;
-	mtrr_type	smp_type;
-};
-
-/**
- * mtrr_rendezvous_handler - Work done in the synchronization handler. Executed
- * by all the CPUs.
- * @info: pointer to mtrr configuration data
- *
- * Returns nothing.
- */
-static int mtrr_rendezvous_handler(void *info)
-{
-	struct set_mtrr_data *data = info;
-
-	/*
-	 * We use this same function to initialize the mtrrs during boot,
-	 * resume, runtime cpu online and on an explicit request to set a
-	 * specific MTRR.
-	 *
-	 * During boot or suspend, the state of the boot cpu's mtrrs has been
-	 * saved, and we want to replicate that across all the cpus that come
-	 * online (either at the end of boot or resume or during a runtime cpu
-	 * online). If we're doing that, @reg is set to something special and on
-	 * all the cpu's we do mtrr_if->set_all() (On the logical cpu that
-	 * started the boot/resume sequence, this might be a duplicate
-	 * set_all()).
-	 */
-	if (data->smp_reg != ~0U) {
-		mtrr_if->set(data->smp_reg, data->smp_base,
-			     data->smp_size, data->smp_type);
-	} else if (mtrr_aps_delayed_init || !cpu_online(smp_processor_id())) {
-		mtrr_if->set_all();
-	}
-	return 0;
-}
-
-static inline int types_compatible(mtrr_type type1, mtrr_type type2)
-{
-	return type1 == MTRR_TYPE_UNCACHABLE ||
-	       type2 == MTRR_TYPE_UNCACHABLE ||
-	       (type1 == MTRR_TYPE_WRTHROUGH && type2 == MTRR_TYPE_WRBACK) ||
-	       (type1 == MTRR_TYPE_WRBACK && type2 == MTRR_TYPE_WRTHROUGH);
-}
-
-/**
- * set_mtrr - update mtrrs on all processors
- * @reg:	mtrr in question
- * @base:	mtrr base
- * @size:	mtrr size
- * @type:	mtrr type
- *
- * This is kinda tricky, but fortunately, Intel spelled it out for us cleanly:
- *
- * 1. Queue work to do the following on all processors:
- * 2. Disable Interrupts
- * 3. Wait for all procs to do so
- * 4. Enter no-fill cache mode
- * 5. Flush caches
- * 6. Clear PGE bit
- * 7. Flush all TLBs
- * 8. Disable all range registers
- * 9. Update the MTRRs
- * 10. Enable all range registers
- * 11. Flush all TLBs and caches again
- * 12. Enter normal cache mode and reenable caching
- * 13. Set PGE
- * 14. Wait for buddies to catch up
- * 15. Enable interrupts.
- *
- * What does that mean for us? Well, stop_machine() will ensure that
- * the rendezvous handler is started on each CPU. And in lockstep they
- * do the state transition of disabling interrupts, updating MTRR's
- * (the CPU vendors may each do it differently, so we call mtrr_if->set()
- * callback and let them take care of it.) and enabling interrupts.
- *
- * Note that the mechanism is the same for UP systems, too; all the SMP stuff
- * becomes nops.
- */
-static void
-set_mtrr(unsigned int reg, unsigned long base, unsigned long size, mtrr_type type)
-{
-	struct set_mtrr_data data = { .smp_reg = reg,
-				      .smp_base = base,
-				      .smp_size = size,
-				      .smp_type = type
-				    };
-
-	stop_machine(mtrr_rendezvous_handler, &data, cpu_online_mask);
-}
-
-static void set_mtrr_from_inactive_cpu(unsigned int reg, unsigned long base,
-				      unsigned long size, mtrr_type type)
-{
-	struct set_mtrr_data data = { .smp_reg = reg,
-				      .smp_base = base,
-				      .smp_size = size,
-				      .smp_type = type
-				    };
-
-	stop_machine_from_inactive_cpu(mtrr_rendezvous_handler, &data,
-				       cpu_callout_mask);
-}
-
-/**
- * mtrr_add_page - Add a memory type region
- * @base: Physical base address of region in pages (in units of 4 kB!)
- * @size: Physical size of region in pages (4 kB)
- * @type: Type of MTRR desired
- * @increment: If this is true do usage counting on the region
- *
- * Memory type region registers control the caching on newer Intel and
- * non Intel processors. This function allows drivers to request an
- * MTRR is added. The details and hardware specifics of each processor's
- * implementation are hidden from the caller, but nevertheless the
- * caller should expect to need to provide a power of two size on an
- * equivalent power of two boundary.
- *
- * If the region cannot be added either because all regions are in use
- * or the CPU cannot support it a negative value is returned. On success
- * the register number for this entry is returned, but should be treated
- * as a cookie only.
- *
- * On a multiprocessor machine the changes are made to all processors.
- * This is required on x86 by the Intel processors.
- *
- * The available types are
- *
- * %MTRR_TYPE_UNCACHABLE - No caching
- *
- * %MTRR_TYPE_WRBACK - Write data back in bursts whenever
- *
- * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts
- *
- * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes
- *
- * BUGS: Needs a quiet flag for the cases where drivers do not mind
- * failures and do not wish system log messages to be sent.
- */
-int mtrr_add_page(unsigned long base, unsigned long size,
-		  unsigned int type, bool increment)
-{
-	unsigned long lbase, lsize;
-	int i, replace, error;
-	mtrr_type ltype;
-
-	if (!mtrr_if)
-		return -ENXIO;
-
-	error = mtrr_if->validate_add_page(base, size, type);
-	if (error)
-		return error;
-
-	if (type >= MTRR_NUM_TYPES) {
-		pr_warning("mtrr: type: %u invalid\n", type);
-		return -EINVAL;
-	}
-
-	/* If the type is WC, check that this processor supports it */
-	if ((type == MTRR_TYPE_WRCOMB) && !have_wrcomb()) {
-		pr_warning("mtrr: your processor doesn't support write-combining\n");
-		return -ENOSYS;
-	}
-
-	if (!size) {
-		pr_warning("mtrr: zero sized request\n");
-		return -EINVAL;
-	}
-
-	if (base & size_or_mask || size & size_or_mask) {
-		pr_warning("mtrr: base or size exceeds the MTRR width\n");
-		return -EINVAL;
-	}
-
-	error = -EINVAL;
-	replace = -1;
-
-	/* No CPU hotplug when we change MTRR entries */
-	get_online_cpus();
-
-	/* Search for existing MTRR  */
-	mutex_lock(&mtrr_mutex);
-	for (i = 0; i < num_var_ranges; ++i) {
-		mtrr_if->get(i, &lbase, &lsize, &ltype);
-		if (!lsize || base > lbase + lsize - 1 ||
-		    base + size - 1 < lbase)
-			continue;
-		/*
-		 * At this point we know there is some kind of
-		 * overlap/enclosure
-		 */
-		if (base < lbase || base + size - 1 > lbase + lsize - 1) {
-			if (base <= lbase &&
-			    base + size - 1 >= lbase + lsize - 1) {
-				/*  New region encloses an existing region  */
-				if (type == ltype) {
-					replace = replace == -1 ? i : -2;
-					continue;
-				} else if (types_compatible(type, ltype))
-					continue;
-			}
-			pr_warning("mtrr: 0x%lx000,0x%lx000 overlaps existing"
-				" 0x%lx000,0x%lx000\n", base, size, lbase,
-				lsize);
-			goto out;
-		}
-		/* New region is enclosed by an existing region */
-		if (ltype != type) {
-			if (types_compatible(type, ltype))
-				continue;
-			pr_warning("mtrr: type mismatch for %lx000,%lx000 old: %s new: %s\n",
-				base, size, mtrr_attrib_to_str(ltype),
-				mtrr_attrib_to_str(type));
-			goto out;
-		}
-		if (increment)
-			++mtrr_usage_table[i];
-		error = i;
-		goto out;
-	}
-	/* Search for an empty MTRR */
-	i = mtrr_if->get_free_region(base, size, replace);
-	if (i >= 0) {
-		set_mtrr(i, base, size, type);
-		if (likely(replace < 0)) {
-			mtrr_usage_table[i] = 1;
-		} else {
-			mtrr_usage_table[i] = mtrr_usage_table[replace];
-			if (increment)
-				mtrr_usage_table[i]++;
-			if (unlikely(replace != i)) {
-				set_mtrr(replace, 0, 0, 0);
-				mtrr_usage_table[replace] = 0;
-			}
-		}
-	} else {
-		pr_info("mtrr: no more MTRRs available\n");
-	}
-	error = i;
- out:
-	mutex_unlock(&mtrr_mutex);
-	put_online_cpus();
-	return error;
-}
-
-static int mtrr_check(unsigned long base, unsigned long size)
-{
-	if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1))) {
-		pr_warning("mtrr: size and base must be multiples of 4 kiB\n");
-		pr_debug("mtrr: size: 0x%lx  base: 0x%lx\n", size, base);
-		dump_stack();
-		return -1;
-	}
-	return 0;
-}
-
-/**
- * mtrr_add - Add a memory type region
- * @base: Physical base address of region
- * @size: Physical size of region
- * @type: Type of MTRR desired
- * @increment: If this is true do usage counting on the region
- *
- * Memory type region registers control the caching on newer Intel and
- * non Intel processors. This function allows drivers to request an
- * MTRR is added. The details and hardware specifics of each processor's
- * implementation are hidden from the caller, but nevertheless the
- * caller should expect to need to provide a power of two size on an
- * equivalent power of two boundary.
- *
- * If the region cannot be added either because all regions are in use
- * or the CPU cannot support it a negative value is returned. On success
- * the register number for this entry is returned, but should be treated
- * as a cookie only.
- *
- * On a multiprocessor machine the changes are made to all processors.
- * This is required on x86 by the Intel processors.
- *
- * The available types are
- *
- * %MTRR_TYPE_UNCACHABLE - No caching
- *
- * %MTRR_TYPE_WRBACK - Write data back in bursts whenever
- *
- * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts
- *
- * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes
- *
- * BUGS: Needs a quiet flag for the cases where drivers do not mind
- * failures and do not wish system log messages to be sent.
- */
-int mtrr_add(unsigned long base, unsigned long size, unsigned int type,
-	     bool increment)
-{
-	if (mtrr_check(base, size))
-		return -EINVAL;
-	return mtrr_add_page(base >> PAGE_SHIFT, size >> PAGE_SHIFT, type,
-			     increment);
-}
-EXPORT_SYMBOL(mtrr_add);
-
-/**
- * mtrr_del_page - delete a memory type region
- * @reg: Register returned by mtrr_add
- * @base: Physical base address
- * @size: Size of region
- *
- * If register is supplied then base and size are ignored. This is
- * how drivers should call it.
- *
- * Releases an MTRR region. If the usage count drops to zero the
- * register is freed and the region returns to default state.
- * On success the register is returned, on failure a negative error
- * code.
- */
-int mtrr_del_page(int reg, unsigned long base, unsigned long size)
-{
-	int i, max;
-	mtrr_type ltype;
-	unsigned long lbase, lsize;
-	int error = -EINVAL;
-
-	if (!mtrr_if)
-		return -ENXIO;
-
-	max = num_var_ranges;
-	/* No CPU hotplug when we change MTRR entries */
-	get_online_cpus();
-	mutex_lock(&mtrr_mutex);
-	if (reg < 0) {
-		/*  Search for existing MTRR  */
-		for (i = 0; i < max; ++i) {
-			mtrr_if->get(i, &lbase, &lsize, &ltype);
-			if (lbase == base && lsize == size) {
-				reg = i;
-				break;
-			}
-		}
-		if (reg < 0) {
-			pr_debug("mtrr: no MTRR for %lx000,%lx000 found\n",
-				 base, size);
-			goto out;
-		}
-	}
-	if (reg >= max) {
-		pr_warning("mtrr: register: %d too big\n", reg);
-		goto out;
-	}
-	mtrr_if->get(reg, &lbase, &lsize, &ltype);
-	if (lsize < 1) {
-		pr_warning("mtrr: MTRR %d not used\n", reg);
-		goto out;
-	}
-	if (mtrr_usage_table[reg] < 1) {
-		pr_warning("mtrr: reg: %d has count=0\n", reg);
-		goto out;
-	}
-	if (--mtrr_usage_table[reg] < 1)
-		set_mtrr(reg, 0, 0, 0);
-	error = reg;
- out:
-	mutex_unlock(&mtrr_mutex);
-	put_online_cpus();
-	return error;
-}
-
-/**
- * mtrr_del - delete a memory type region
- * @reg: Register returned by mtrr_add
- * @base: Physical base address
- * @size: Size of region
- *
- * If register is supplied then base and size are ignored. This is
- * how drivers should call it.
- *
- * Releases an MTRR region. If the usage count drops to zero the
- * register is freed and the region returns to default state.
- * On success the register is returned, on failure a negative error
- * code.
- */
-int mtrr_del(int reg, unsigned long base, unsigned long size)
-{
-	if (mtrr_check(base, size))
-		return -EINVAL;
-	return mtrr_del_page(reg, base >> PAGE_SHIFT, size >> PAGE_SHIFT);
-}
-EXPORT_SYMBOL(mtrr_del);
-
-/*
- * HACK ALERT!
- * These should be called implicitly, but we can't yet until all the initcall
- * stuff is done...
- */
-static void __init init_ifs(void)
-{
-#ifndef CONFIG_X86_64
-	amd_init_mtrr();
-	cyrix_init_mtrr();
-	centaur_init_mtrr();
-#endif
-}
-
-/* The suspend/resume methods are only for CPU without MTRR. CPU using generic
- * MTRR driver doesn't require this
- */
-struct mtrr_value {
-	mtrr_type	ltype;
-	unsigned long	lbase;
-	unsigned long	lsize;
-};
-
-static struct mtrr_value mtrr_value[MTRR_MAX_VAR_RANGES];
-
-static int mtrr_save(void)
-{
-	int i;
-
-	for (i = 0; i < num_var_ranges; i++) {
-		mtrr_if->get(i, &mtrr_value[i].lbase,
-				&mtrr_value[i].lsize,
-				&mtrr_value[i].ltype);
-	}
-	return 0;
-}
-
-static void mtrr_restore(void)
-{
-	int i;
-
-	for (i = 0; i < num_var_ranges; i++) {
-		if (mtrr_value[i].lsize) {
-			set_mtrr(i, mtrr_value[i].lbase,
-				    mtrr_value[i].lsize,
-				    mtrr_value[i].ltype);
-		}
-	}
-}
-
-
-
-static struct syscore_ops mtrr_syscore_ops = {
-	.suspend	= mtrr_save,
-	.resume		= mtrr_restore,
-};
-
-int __initdata changed_by_mtrr_cleanup;
-
-/**
- * mtrr_bp_init - initialize mtrrs on the boot CPU
- *
- * This needs to be called early; before any of the other CPUs are
- * initialized (i.e. before smp_init()).
- *
- */
-void __init mtrr_bp_init(void)
-{
-	u32 phys_addr;
-
-	init_ifs();
-
-	phys_addr = 32;
-
-	if (cpu_has_mtrr) {
-		mtrr_if = &generic_mtrr_ops;
-		size_or_mask = 0xff000000;			/* 36 bits */
-		size_and_mask = 0x00f00000;
-		phys_addr = 36;
-
-		/*
-		 * This is an AMD specific MSR, but we assume(hope?) that
-		 * Intel will implement it to when they extend the address
-		 * bus of the Xeon.
-		 */
-		if (cpuid_eax(0x80000000) >= 0x80000008) {
-			phys_addr = cpuid_eax(0x80000008) & 0xff;
-			/* CPUID workaround for Intel 0F33/0F34 CPU */
-			if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
-			    boot_cpu_data.x86 == 0xF &&
-			    boot_cpu_data.x86_model == 0x3 &&
-			    (boot_cpu_data.x86_mask == 0x3 ||
-			     boot_cpu_data.x86_mask == 0x4))
-				phys_addr = 36;
-
-			size_or_mask = ~((1ULL << (phys_addr - PAGE_SHIFT)) - 1);
-			size_and_mask = ~size_or_mask & 0xfffff00000ULL;
-		} else if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR &&
-			   boot_cpu_data.x86 == 6) {
-			/*
-			 * VIA C* family have Intel style MTRRs,
-			 * but don't support PAE
-			 */
-			size_or_mask = 0xfff00000;		/* 32 bits */
-			size_and_mask = 0;
-			phys_addr = 32;
-		}
-	} else {
-		switch (boot_cpu_data.x86_vendor) {
-		case X86_VENDOR_AMD:
-			if (cpu_has_k6_mtrr) {
-				/* Pre-Athlon (K6) AMD CPU MTRRs */
-				mtrr_if = mtrr_ops[X86_VENDOR_AMD];
-				size_or_mask = 0xfff00000;	/* 32 bits */
-				size_and_mask = 0;
-			}
-			break;
-		case X86_VENDOR_CENTAUR:
-			if (cpu_has_centaur_mcr) {
-				mtrr_if = mtrr_ops[X86_VENDOR_CENTAUR];
-				size_or_mask = 0xfff00000;	/* 32 bits */
-				size_and_mask = 0;
-			}
-			break;
-		case X86_VENDOR_CYRIX:
-			if (cpu_has_cyrix_arr) {
-				mtrr_if = mtrr_ops[X86_VENDOR_CYRIX];
-				size_or_mask = 0xfff00000;	/* 32 bits */
-				size_and_mask = 0;
-			}
-			break;
-		default:
-			break;
-		}
-	}
-
-	if (mtrr_if) {
-		set_num_var_ranges();
-		init_table();
-		if (use_intel()) {
-			get_mtrr_state();
-
-			if (mtrr_cleanup(phys_addr)) {
-				changed_by_mtrr_cleanup = 1;
-				mtrr_if->set_all();
-			}
-		}
-	}
-}
-
-void mtrr_ap_init(void)
-{
-	if (!use_intel() || mtrr_aps_delayed_init)
-		return;
-	/*
-	 * Ideally we should hold mtrr_mutex here to avoid mtrr entries
-	 * changed, but this routine will be called in cpu boot time,
-	 * holding the lock breaks it.
-	 *
-	 * This routine is called in two cases:
-	 *
-	 *   1. very earily time of software resume, when there absolutely
-	 *      isn't mtrr entry changes;
-	 *
-	 *   2. cpu hotadd time. We let mtrr_add/del_page hold cpuhotplug
-	 *      lock to prevent mtrr entry changes
-	 */
-	set_mtrr_from_inactive_cpu(~0U, 0, 0, 0);
-}
-
-/**
- * Save current fixed-range MTRR state of the BSP
- */
-void mtrr_save_state(void)
-{
-	smp_call_function_single(0, mtrr_save_fixed_ranges, NULL, 1);
-}
-
-void set_mtrr_aps_delayed_init(void)
-{
-	if (!use_intel())
-		return;
-
-	mtrr_aps_delayed_init = true;
-}
-
-/*
- * Delayed MTRR initialization for all AP's
- */
-void mtrr_aps_init(void)
-{
-	if (!use_intel())
-		return;
-
-	/*
-	 * Check if someone has requested the delay of AP MTRR initialization,
-	 * by doing set_mtrr_aps_delayed_init(), prior to this point. If not,
-	 * then we are done.
-	 */
-	if (!mtrr_aps_delayed_init)
-		return;
-
-	set_mtrr(~0U, 0, 0, 0);
-	mtrr_aps_delayed_init = false;
-}
-
-void mtrr_bp_restore(void)
-{
-	if (!use_intel())
-		return;
-
-	mtrr_if->set_all();
-}
-
-static int __init mtrr_init_finialize(void)
-{
-	if (!mtrr_if)
-		return 0;
-
-	if (use_intel()) {
-		if (!changed_by_mtrr_cleanup)
-			mtrr_state_warn();
-		return 0;
-	}
-
-	/*
-	 * The CPU has no MTRR and seems to not support SMP. They have
-	 * specific drivers, we use a tricky method to support
-	 * suspend/resume for them.
-	 *
-	 * TBD: is there any system with such CPU which supports
-	 * suspend/resume? If no, we should remove the code.
-	 */
-	register_syscore_ops(&mtrr_syscore_ops);
-
-	return 0;
-}
-subsys_initcall(mtrr_init_finialize);
diff --git a/ANDROID_3.4.5/arch/x86/kernel/cpu/mtrr/mtrr.h b/ANDROID_3.4.5/arch/x86/kernel/cpu/mtrr/mtrr.h
deleted file mode 100644
index df5e41f3..00000000
--- a/ANDROID_3.4.5/arch/x86/kernel/cpu/mtrr/mtrr.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * local MTRR defines.
- */
-
-#include <linux/types.h>
-#include <linux/stddef.h>
-
-#define MTRR_CHANGE_MASK_FIXED     0x01
-#define MTRR_CHANGE_MASK_VARIABLE  0x02
-#define MTRR_CHANGE_MASK_DEFTYPE   0x04
-
-extern unsigned int mtrr_usage_table[MTRR_MAX_VAR_RANGES];
-
-struct mtrr_ops {
-	u32	vendor;
-	u32	use_intel_if;
-	void	(*set)(unsigned int reg, unsigned long base,
-		       unsigned long size, mtrr_type type);
-	void	(*set_all)(void);
-
-	void	(*get)(unsigned int reg, unsigned long *base,
-		       unsigned long *size, mtrr_type *type);
-	int	(*get_free_region)(unsigned long base, unsigned long size,
-				   int replace_reg);
-	int	(*validate_add_page)(unsigned long base, unsigned long size,
-				     unsigned int type);
-	int	(*have_wrcomb)(void);
-};
-
-extern int generic_get_free_region(unsigned long base, unsigned long size,
-				   int replace_reg);
-extern int generic_validate_add_page(unsigned long base, unsigned long size,
-				     unsigned int type);
-
-extern const struct mtrr_ops generic_mtrr_ops;
-
-extern int positive_have_wrcomb(void);
-
-/* library functions for processor-specific routines */
-struct set_mtrr_context {
-	unsigned long	flags;
-	unsigned long	cr4val;
-	u32		deftype_lo;
-	u32		deftype_hi;
-	u32		ccr3;
-};
-
-void set_mtrr_done(struct set_mtrr_context *ctxt);
-void set_mtrr_cache_disable(struct set_mtrr_context *ctxt);
-void set_mtrr_prepare_save(struct set_mtrr_context *ctxt);
-
-void fill_mtrr_var_range(unsigned int index,
-		u32 base_lo, u32 base_hi, u32 mask_lo, u32 mask_hi);
-void get_mtrr_state(void);
-
-extern void set_mtrr_ops(const struct mtrr_ops *ops);
-
-extern u64 size_or_mask, size_and_mask;
-extern const struct mtrr_ops *mtrr_if;
-
-#define is_cpu(vnd)	(mtrr_if && mtrr_if->vendor == X86_VENDOR_##vnd)
-#define use_intel()	(mtrr_if && mtrr_if->use_intel_if == 1)
-
-extern unsigned int num_var_ranges;
-extern u64 mtrr_tom2;
-extern struct mtrr_state_type mtrr_state;
-
-void mtrr_state_warn(void);
-const char *mtrr_attrib_to_str(int x);
-void mtrr_wrmsr(unsigned, unsigned, unsigned);
-
-/* CPU specific mtrr init functions */
-int amd_init_mtrr(void);
-int cyrix_init_mtrr(void);
-int centaur_init_mtrr(void);
-
-extern int changed_by_mtrr_cleanup;
-extern int mtrr_cleanup(unsigned address_bits);