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| author | Kevin | 2014-11-15 09:58:27 +0800 |
|---|---|---|
| committer | Kevin | 2014-11-15 09:58:27 +0800 |
| commit | 392e8802486cb573b916e746010e141a75f507e6 (patch) | |
| tree | 50029aca02c81f087b90336e670b44e510782330 /ANDROID_3.4.5/arch/sparc/include/asm/dcu.h | |
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init android origin source code
Diffstat (limited to 'ANDROID_3.4.5/arch/sparc/include/asm/dcu.h')
| -rw-r--r-- | ANDROID_3.4.5/arch/sparc/include/asm/dcu.h | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/ANDROID_3.4.5/arch/sparc/include/asm/dcu.h b/ANDROID_3.4.5/arch/sparc/include/asm/dcu.h new file mode 100644 index 00000000..0f704e10 --- /dev/null +++ b/ANDROID_3.4.5/arch/sparc/include/asm/dcu.h @@ -0,0 +1,27 @@ +#ifndef _SPARC64_DCU_H +#define _SPARC64_DCU_H + +#include <linux/const.h> + +/* UltraSparc-III Data Cache Unit Control Register */ +#define DCU_CP _AC(0x0002000000000000,UL) /* Phys Cache Enable w/o mmu */ +#define DCU_CV _AC(0x0001000000000000,UL) /* Virt Cache Enable w/o mmu */ +#define DCU_ME _AC(0x0000800000000000,UL) /* NC-store Merging Enable */ +#define DCU_RE _AC(0x0000400000000000,UL) /* RAW bypass Enable */ +#define DCU_PE _AC(0x0000200000000000,UL) /* PCache Enable */ +#define DCU_HPE _AC(0x0000100000000000,UL) /* HW prefetch Enable */ +#define DCU_SPE _AC(0x0000080000000000,UL) /* SW prefetch Enable */ +#define DCU_SL _AC(0x0000040000000000,UL) /* Secondary ld-steering Enab*/ +#define DCU_WE _AC(0x0000020000000000,UL) /* WCache enable */ +#define DCU_PM _AC(0x000001fe00000000,UL) /* PA Watchpoint Byte Mask */ +#define DCU_VM _AC(0x00000001fe000000,UL) /* VA Watchpoint Byte Mask */ +#define DCU_PR _AC(0x0000000001000000,UL) /* PA Watchpoint Read Enable */ +#define DCU_PW _AC(0x0000000000800000,UL) /* PA Watchpoint Write Enable*/ +#define DCU_VR _AC(0x0000000000400000,UL) /* VA Watchpoint Read Enable */ +#define DCU_VW _AC(0x0000000000200000,UL) /* VA Watchpoint Write Enable*/ +#define DCU_DM _AC(0x0000000000000008,UL) /* DMMU Enable */ +#define DCU_IM _AC(0x0000000000000004,UL) /* IMMU Enable */ +#define DCU_DC _AC(0x0000000000000002,UL) /* Data Cache Enable */ +#define DCU_IC _AC(0x0000000000000001,UL) /* Instruction Cache Enable */ + +#endif /* _SPARC64_DCU_H */ |