Moved, renamed, and deleted files

The original directory structure was scattered and unorganized.
Changes are basically to make it look like kernel structure.

299 files changed, 0 insertions, 46791 deletions

diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/8xx_immap.h b/ANDROID_3.4.5/arch/powerpc/include/asm/8xx_immap.h
deleted file mode 100644
index bdf0563b..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/8xx_immap.h
+++ /dev/null
@@ -1,564 +0,0 @@
-/*
- * MPC8xx Internal Memory Map
- * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
- *
- * The I/O on the MPC860 is comprised of blocks of special registers
- * and the dual port ram for the Communication Processor Module.
- * Within this space are functional units such as the SIU, memory
- * controller, system timers, and other control functions.  It is
- * a combination that I found difficult to separate into logical
- * functional files.....but anyone else is welcome to try.  -- Dan
- */
-#ifdef __KERNEL__
-#ifndef __IMMAP_8XX__
-#define __IMMAP_8XX__
-
-/* System configuration registers.
-*/
-typedef	struct sys_conf {
-	uint	sc_siumcr;
-	uint	sc_sypcr;
-	uint	sc_swt;
-	char	res1[2];
-	ushort	sc_swsr;
-	uint	sc_sipend;
-	uint	sc_simask;
-	uint	sc_siel;
-	uint	sc_sivec;
-	uint	sc_tesr;
-	char	res2[0xc];
-	uint	sc_sdcr;
-	char	res3[0x4c];
-} sysconf8xx_t;
-
-/* PCMCIA configuration registers.
-*/
-typedef struct pcmcia_conf {
-	uint	pcmc_pbr0;
-	uint	pcmc_por0;
-	uint	pcmc_pbr1;
-	uint	pcmc_por1;
-	uint	pcmc_pbr2;
-	uint	pcmc_por2;
-	uint	pcmc_pbr3;
-	uint	pcmc_por3;
-	uint	pcmc_pbr4;
-	uint	pcmc_por4;
-	uint	pcmc_pbr5;
-	uint	pcmc_por5;
-	uint	pcmc_pbr6;
-	uint	pcmc_por6;
-	uint	pcmc_pbr7;
-	uint	pcmc_por7;
-	char	res1[0x20];
-	uint	pcmc_pgcra;
-	uint	pcmc_pgcrb;
-	uint	pcmc_pscr;
-	char	res2[4];
-	uint	pcmc_pipr;
-	char	res3[4];
-	uint	pcmc_per;
-	char	res4[4];
-} pcmconf8xx_t;
-
-/* Memory controller registers.
-*/
-typedef struct	mem_ctlr {
-	uint	memc_br0;
-	uint	memc_or0;
-	uint	memc_br1;
-	uint	memc_or1;
-	uint	memc_br2;
-	uint	memc_or2;
-	uint	memc_br3;
-	uint	memc_or3;
-	uint	memc_br4;
-	uint	memc_or4;
-	uint	memc_br5;
-	uint	memc_or5;
-	uint	memc_br6;
-	uint	memc_or6;
-	uint	memc_br7;
-	uint	memc_or7;
-	char	res1[0x24];
-	uint	memc_mar;
-	uint	memc_mcr;
-	char	res2[4];
-	uint	memc_mamr;
-	uint	memc_mbmr;
-	ushort	memc_mstat;
-	ushort	memc_mptpr;
-	uint	memc_mdr;
-	char	res3[0x80];
-} memctl8xx_t;
-
-/*-----------------------------------------------------------------------
- * BR - Memory Controller: Base Register					16-9
- */
-#define BR_BA_MSK	0xffff8000	/* Base Address Mask			*/
-#define BR_AT_MSK	0x00007000	/* Address Type Mask			*/
-#define BR_PS_MSK	0x00000c00	/* Port Size Mask			*/
-#define BR_PS_32	0x00000000	/* 32 bit port size			*/
-#define BR_PS_16	0x00000800	/* 16 bit port size			*/
-#define BR_PS_8		0x00000400	/*  8 bit port size			*/
-#define BR_PARE		0x00000200	/* Parity Enable			*/
-#define BR_WP		0x00000100	/* Write Protect			*/
-#define BR_MS_MSK	0x000000c0	/* Machine Select Mask			*/
-#define BR_MS_GPCM	0x00000000	/* G.P.C.M. Machine Select		*/
-#define BR_MS_UPMA	0x00000080	/* U.P.M.A Machine Select		*/
-#define BR_MS_UPMB	0x000000c0	/* U.P.M.B Machine Select		*/
-#define BR_V		0x00000001	/* Bank Valid				*/
-
-/*-----------------------------------------------------------------------
- * OR - Memory Controller: Option Register				16-11
- */
-#define OR_AM_MSK	0xffff8000	/* Address Mask Mask			*/
-#define OR_ATM_MSK	0x00007000	/* Address Type Mask Mask		*/
-#define OR_CSNT_SAM	0x00000800	/* Chip Select Negation Time/ Start	*/
-					/* Address Multiplex			*/
-#define OR_ACS_MSK	0x00000600	/* Address to Chip Select Setup mask	*/
-#define OR_ACS_DIV1	0x00000000	/* CS is output at the same time	*/
-#define OR_ACS_DIV4	0x00000400	/* CS is output 1/4 a clock later	*/
-#define OR_ACS_DIV2	0x00000600	/* CS is output 1/2 a clock later	*/
-#define OR_G5LA		0x00000400	/* Output #GPL5 on #GPL_A5		*/
-#define OR_G5LS		0x00000200	/* Drive #GPL high on falling edge of...*/
-#define OR_BI		0x00000100	/* Burst inhibit			*/
-#define OR_SCY_MSK	0x000000f0	/* Cycle Length in Clocks		*/
-#define OR_SCY_0_CLK	0x00000000	/* 0 clock cycles wait states		*/
-#define OR_SCY_1_CLK	0x00000010	/* 1 clock cycles wait states		*/
-#define OR_SCY_2_CLK	0x00000020	/* 2 clock cycles wait states		*/
-#define OR_SCY_3_CLK	0x00000030	/* 3 clock cycles wait states		*/
-#define OR_SCY_4_CLK	0x00000040	/* 4 clock cycles wait states		*/
-#define OR_SCY_5_CLK	0x00000050	/* 5 clock cycles wait states		*/
-#define OR_SCY_6_CLK	0x00000060	/* 6 clock cycles wait states		*/
-#define OR_SCY_7_CLK	0x00000070	/* 7 clock cycles wait states		*/
-#define OR_SCY_8_CLK	0x00000080	/* 8 clock cycles wait states		*/
-#define OR_SCY_9_CLK	0x00000090	/* 9 clock cycles wait states		*/
-#define OR_SCY_10_CLK	0x000000a0	/* 10 clock cycles wait states		*/
-#define OR_SCY_11_CLK	0x000000b0	/* 11 clock cycles wait states		*/
-#define OR_SCY_12_CLK	0x000000c0	/* 12 clock cycles wait states		*/
-#define OR_SCY_13_CLK	0x000000d0	/* 13 clock cycles wait states		*/
-#define OR_SCY_14_CLK	0x000000e0	/* 14 clock cycles wait states		*/
-#define OR_SCY_15_CLK	0x000000f0	/* 15 clock cycles wait states		*/
-#define OR_SETA		0x00000008	/* External Transfer Acknowledge	*/
-#define OR_TRLX		0x00000004	/* Timing Relaxed			*/
-#define OR_EHTR		0x00000002	/* Extended Hold Time on Read		*/
-
-/* System Integration Timers.
-*/
-typedef struct	sys_int_timers {
-	ushort	sit_tbscr;
-	char	res0[0x02];
-	uint	sit_tbreff0;
-	uint	sit_tbreff1;
-	char	res1[0x14];
-	ushort	sit_rtcsc;
-	char	res2[0x02];
-	uint	sit_rtc;
-	uint	sit_rtsec;
-	uint	sit_rtcal;
-	char	res3[0x10];
-	ushort	sit_piscr;
-	char	res4[2];
-	uint	sit_pitc;
-	uint	sit_pitr;
-	char	res5[0x34];
-} sit8xx_t;
-
-#define TBSCR_TBIRQ_MASK	((ushort)0xff00)
-#define TBSCR_REFA		((ushort)0x0080)
-#define TBSCR_REFB		((ushort)0x0040)
-#define TBSCR_REFAE		((ushort)0x0008)
-#define TBSCR_REFBE		((ushort)0x0004)
-#define TBSCR_TBF		((ushort)0x0002)
-#define TBSCR_TBE		((ushort)0x0001)
-
-#define RTCSC_RTCIRQ_MASK	((ushort)0xff00)
-#define RTCSC_SEC		((ushort)0x0080)
-#define RTCSC_ALR		((ushort)0x0040)
-#define RTCSC_38K		((ushort)0x0010)
-#define RTCSC_SIE		((ushort)0x0008)
-#define RTCSC_ALE		((ushort)0x0004)
-#define RTCSC_RTF		((ushort)0x0002)
-#define RTCSC_RTE		((ushort)0x0001)
-
-#define PISCR_PIRQ_MASK		((ushort)0xff00)
-#define PISCR_PS		((ushort)0x0080)
-#define PISCR_PIE		((ushort)0x0004)
-#define PISCR_PTF		((ushort)0x0002)
-#define PISCR_PTE		((ushort)0x0001)
-
-/* Clocks and Reset.
-*/
-typedef struct clk_and_reset {
-	uint	car_sccr;
-	uint	car_plprcr;
-	uint	car_rsr;
-	char	res[0x74];        /* Reserved area                  */
-} car8xx_t;
-
-/* System Integration Timers keys.
-*/
-typedef struct sitk {
-	uint	sitk_tbscrk;
-	uint	sitk_tbreff0k;
-	uint	sitk_tbreff1k;
-	uint	sitk_tbk;
-	char	res1[0x10];
-	uint	sitk_rtcsck;
-	uint	sitk_rtck;
-	uint	sitk_rtseck;
-	uint	sitk_rtcalk;
-	char	res2[0x10];
-	uint	sitk_piscrk;
-	uint	sitk_pitck;
-	char	res3[0x38];
-} sitk8xx_t;
-
-/* Clocks and reset keys.
-*/
-typedef struct cark {
-	uint	cark_sccrk;
-	uint	cark_plprcrk;
-	uint	cark_rsrk;
-	char	res[0x474];
-} cark8xx_t;
-
-/* The key to unlock registers maintained by keep-alive power.
-*/
-#define KAPWR_KEY	((unsigned int)0x55ccaa33)
-
-/* Video interface.  MPC823 Only.
-*/
-typedef struct vid823 {
-	ushort	vid_vccr;
-	ushort	res1;
-	u_char	vid_vsr;
-	u_char	res2;
-	u_char	vid_vcmr;
-	u_char	res3;
-	uint	vid_vbcb;
-	uint	res4;
-	uint	vid_vfcr0;
-	uint	vid_vfaa0;
-	uint	vid_vfba0;
-	uint	vid_vfcr1;
-	uint	vid_vfaa1;
-	uint	vid_vfba1;
-	u_char	res5[0x18];
-} vid823_t;
-
-/* LCD interface.  823 Only.
-*/
-typedef struct lcd {
-	uint	lcd_lccr;
-	uint	lcd_lchcr;
-	uint	lcd_lcvcr;
-	char	res1[4];
-	uint	lcd_lcfaa;
-	uint	lcd_lcfba;
-	char	lcd_lcsr;
-	char	res2[0x7];
-} lcd823_t;
-
-/* I2C
-*/
-typedef struct i2c {
-	u_char	i2c_i2mod;
-	char	res1[3];
-	u_char	i2c_i2add;
-	char	res2[3];
-	u_char	i2c_i2brg;
-	char	res3[3];
-	u_char	i2c_i2com;
-	char	res4[3];
-	u_char	i2c_i2cer;
-	char	res5[3];
-	u_char	i2c_i2cmr;
-	char	res6[0x8b];
-} i2c8xx_t;
-
-/* DMA control/status registers.
-*/
-typedef struct sdma_csr {
-	char	res1[4];
-	uint	sdma_sdar;
-	u_char	sdma_sdsr;
-	char	res3[3];
-	u_char	sdma_sdmr;
-	char	res4[3];
-	u_char	sdma_idsr1;
-	char	res5[3];
-	u_char	sdma_idmr1;
-	char	res6[3];
-	u_char	sdma_idsr2;
-	char	res7[3];
-	u_char	sdma_idmr2;
-	char	res8[0x13];
-} sdma8xx_t;
-
-/* Communication Processor Module Interrupt Controller.
-*/
-typedef struct cpm_ic {
-	ushort	cpic_civr;
-	char	res[0xe];
-	uint	cpic_cicr;
-	uint	cpic_cipr;
-	uint	cpic_cimr;
-	uint	cpic_cisr;
-} cpic8xx_t;
-
-/* Input/Output Port control/status registers.
-*/
-typedef struct io_port {
-	ushort	iop_padir;
-	ushort	iop_papar;
-	ushort	iop_paodr;
-	ushort	iop_padat;
-	char	res1[8];
-	ushort	iop_pcdir;
-	ushort	iop_pcpar;
-	ushort	iop_pcso;
-	ushort	iop_pcdat;
-	ushort	iop_pcint;
-	char	res2[6];
-	ushort	iop_pddir;
-	ushort	iop_pdpar;
-	char	res3[2];
-	ushort	iop_pddat;
-	uint	utmode;
-	char	res4[4];
-} iop8xx_t;
-
-/* Communication Processor Module Timers
-*/
-typedef struct cpm_timers {
-	ushort	cpmt_tgcr;
-	char	res1[0xe];
-	ushort	cpmt_tmr1;
-	ushort	cpmt_tmr2;
-	ushort	cpmt_trr1;
-	ushort	cpmt_trr2;
-	ushort	cpmt_tcr1;
-	ushort	cpmt_tcr2;
-	ushort	cpmt_tcn1;
-	ushort	cpmt_tcn2;
-	ushort	cpmt_tmr3;
-	ushort	cpmt_tmr4;
-	ushort	cpmt_trr3;
-	ushort	cpmt_trr4;
-	ushort	cpmt_tcr3;
-	ushort	cpmt_tcr4;
-	ushort	cpmt_tcn3;
-	ushort	cpmt_tcn4;
-	ushort	cpmt_ter1;
-	ushort	cpmt_ter2;
-	ushort	cpmt_ter3;
-	ushort	cpmt_ter4;
-	char	res2[8];
-} cpmtimer8xx_t;
-
-/* Finally, the Communication Processor stuff.....
-*/
-typedef struct scc {		/* Serial communication channels */
-	uint	scc_gsmrl;
-	uint	scc_gsmrh;
-	ushort	scc_psmr;
-	char	res1[2];
-	ushort	scc_todr;
-	ushort	scc_dsr;
-	ushort	scc_scce;
-	char	res2[2];
-	ushort	scc_sccm;
-	char	res3;
-	u_char	scc_sccs;
-	char	res4[8];
-} scc_t;
-
-typedef struct smc {		/* Serial management channels */
-	char	res1[2];
-	ushort	smc_smcmr;
-	char	res2[2];
-	u_char	smc_smce;
-	char	res3[3];
-	u_char	smc_smcm;
-	char	res4[5];
-} smc_t;
-
-/* MPC860T Fast Ethernet Controller.  It isn't part of the CPM, but
- * it fits within the address space.
- */
-
-typedef struct fec {
-	uint	fec_addr_low;		/* lower 32 bits of station address	*/
-	ushort	fec_addr_high;		/* upper 16 bits of station address	*/
-	ushort	res1;			/* reserved				*/
-	uint	fec_grp_hash_table_high;	/* upper 32-bits of hash table		*/
-	uint	fec_grp_hash_table_low;	/* lower 32-bits of hash table		*/
-	uint	fec_r_des_start;	/* beginning of Rx descriptor ring	*/
-	uint	fec_x_des_start;	/* beginning of Tx descriptor ring	*/
-	uint	fec_r_buff_size;	/* Rx buffer size			*/
-	uint	res2[9];		/* reserved				*/
-	uint	fec_ecntrl;		/* ethernet control register		*/
-	uint	fec_ievent;		/* interrupt event register		*/
-	uint	fec_imask;		/* interrupt mask register		*/
-	uint	fec_ivec;		/* interrupt level and vector status	*/
-	uint	fec_r_des_active;	/* Rx ring updated flag			*/
-	uint	fec_x_des_active;	/* Tx ring updated flag			*/
-	uint	res3[10];		/* reserved				*/
-	uint	fec_mii_data;		/* MII data register			*/
-	uint	fec_mii_speed;		/* MII speed control register		*/
-	uint	res4[17];		/* reserved				*/
-	uint	fec_r_bound;		/* end of RAM (read-only)		*/
-	uint	fec_r_fstart;		/* Rx FIFO start address		*/
-	uint	res5[6];		/* reserved				*/
-	uint	fec_x_fstart;		/* Tx FIFO start address		*/
-	uint	res6[17];		/* reserved				*/
-	uint	fec_fun_code;		/* fec SDMA function code		*/
-	uint	res7[3];		/* reserved				*/
-	uint	fec_r_cntrl;		/* Rx control register			*/
-	uint	fec_r_hash;		/* Rx hash register			*/
-	uint	res8[14];		/* reserved				*/
-	uint	fec_x_cntrl;		/* Tx control register			*/
-	uint	res9[0x1e];		/* reserved				*/
-} fec_t;
-
-/* The FEC and LCD color map share the same address space....
- * I guess we will never see an 823T :-).
- */
-union fec_lcd {
-	fec_t	fl_un_fec;
-	u_char	fl_un_cmap[0x200];
-};
-
-typedef struct comm_proc {
-	/* General control and status registers.
-	*/
-	ushort	cp_cpcr;
-	u_char	res1[2];
-	ushort	cp_rccr;
-	u_char	res2;
-	u_char	cp_rmds;
-	u_char	res3[4];
-	ushort	cp_cpmcr1;
-	ushort	cp_cpmcr2;
-	ushort	cp_cpmcr3;
-	ushort	cp_cpmcr4;
-	u_char	res4[2];
-	ushort	cp_rter;
-	u_char	res5[2];
-	ushort	cp_rtmr;
-	u_char	res6[0x14];
-
-	/* Baud rate generators.
-	*/
-	uint	cp_brgc1;
-	uint	cp_brgc2;
-	uint	cp_brgc3;
-	uint	cp_brgc4;
-
-	/* Serial Communication Channels.
-	*/
-	scc_t	cp_scc[4];
-
-	/* Serial Management Channels.
-	*/
-	smc_t	cp_smc[2];
-
-	/* Serial Peripheral Interface.
-	*/
-	ushort	cp_spmode;
-	u_char	res7[4];
-	u_char	cp_spie;
-	u_char	res8[3];
-	u_char	cp_spim;
-	u_char	res9[2];
-	u_char	cp_spcom;
-	u_char	res10[2];
-
-	/* Parallel Interface Port.
-	*/
-	u_char	res11[2];
-	ushort	cp_pipc;
-	u_char	res12[2];
-	ushort	cp_ptpr;
-	uint	cp_pbdir;
-	uint	cp_pbpar;
-	u_char	res13[2];
-	ushort	cp_pbodr;
-	uint	cp_pbdat;
-
-	/* Port E - MPC87x/88x only.
-	 */
-	uint	cp_pedir;
-	uint	cp_pepar;
-	uint	cp_peso;
-	uint	cp_peodr;
-	uint	cp_pedat;
-
-	/* Communications Processor Timing Register -
-	   Contains RMII Timing for the FECs on MPC87x/88x only.
-	*/
-	uint	cp_cptr;
-
-	/* Serial Interface and Time Slot Assignment.
-	*/
-	uint	cp_simode;
-	u_char	cp_sigmr;
-	u_char	res15;
-	u_char	cp_sistr;
-	u_char	cp_sicmr;
-	u_char	res16[4];
-	uint	cp_sicr;
-	uint	cp_sirp;
-	u_char	res17[0xc];
-
-	/* 256 bytes of MPC823 video controller RAM array.
-	*/
-	u_char	cp_vcram[0x100];
-	u_char	cp_siram[0x200];
-
-	/* The fast ethernet controller is not really part of the CPM,
-	 * but it resides in the address space.
-	 * The LCD color map is also here.
-	 */
-	union	fec_lcd	fl_un;
-#define cp_fec		fl_un.fl_un_fec
-#define lcd_cmap	fl_un.fl_un_cmap
-	char	res18[0xE00];
-
-	/* The DUET family has a second FEC here */
-	fec_t	cp_fec2;
-#define cp_fec1	cp_fec	/* consistency macro */
-
-	/* Dual Ported RAM follows.
-	 * There are many different formats for this memory area
-	 * depending upon the devices used and options chosen.
-	 * Some processors don't have all of it populated.
-	 */
-	u_char	cp_dpmem[0x1C00];	/* BD / Data / ucode */
-	u_char	cp_dparam[0x400];	/* Parameter RAM */
-} cpm8xx_t;
-
-/* Internal memory map.
-*/
-typedef struct immap {
-	sysconf8xx_t	im_siu_conf;	/* SIU Configuration */
-	pcmconf8xx_t	im_pcmcia;	/* PCMCIA Configuration */
-	memctl8xx_t	im_memctl;	/* Memory Controller */
-	sit8xx_t	im_sit;		/* System integration timers */
-	car8xx_t	im_clkrst;	/* Clocks and reset */
-	sitk8xx_t	im_sitk;	/* Sys int timer keys */
-	cark8xx_t	im_clkrstk;	/* Clocks and reset keys */
-	vid823_t	im_vid;		/* Video (823 only) */
-	lcd823_t	im_lcd;		/* LCD (823 only) */
-	i2c8xx_t	im_i2c;		/* I2C control/status */
-	sdma8xx_t	im_sdma;	/* SDMA control/status */
-	cpic8xx_t	im_cpic;	/* CPM Interrupt Controller */
-	iop8xx_t	im_ioport;	/* IO Port control/status */
-	cpmtimer8xx_t	im_cpmtimer;	/* CPM timers */
-	cpm8xx_t	im_cpm;		/* Communication processor */
-} immap_t;
-
-#endif /* __IMMAP_8XX__ */
-#endif /* __KERNEL__ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/Kbuild b/ANDROID_3.4.5/arch/powerpc/include/asm/Kbuild
deleted file mode 100644
index 7e313f1e..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/Kbuild
+++ /dev/null
@@ -1,38 +0,0 @@
-include include/asm-generic/Kbuild.asm
-
-header-y += auxvec.h
-header-y += bootx.h
-header-y += byteorder.h
-header-y += cputable.h
-header-y += elf.h
-header-y += errno.h
-header-y += fcntl.h
-header-y += ioctl.h
-header-y += ioctls.h
-header-y += ipcbuf.h
-header-y += linkage.h
-header-y += msgbuf.h
-header-y += nvram.h
-header-y += param.h
-header-y += poll.h
-header-y += posix_types.h
-header-y += ps3fb.h
-header-y += resource.h
-header-y += seccomp.h
-header-y += sembuf.h
-header-y += shmbuf.h
-header-y += sigcontext.h
-header-y += siginfo.h
-header-y += signal.h
-header-y += socket.h
-header-y += sockios.h
-header-y += spu_info.h
-header-y += stat.h
-header-y += statfs.h
-header-y += termbits.h
-header-y += termios.h
-header-y += types.h
-header-y += ucontext.h
-header-y += unistd.h
-
-generic-y += rwsem.h
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/abs_addr.h b/ANDROID_3.4.5/arch/powerpc/include/asm/abs_addr.h
deleted file mode 100644
index 9d92ba04..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/abs_addr.h
+++ /dev/null
@@ -1,56 +0,0 @@
-#ifndef _ASM_POWERPC_ABS_ADDR_H
-#define _ASM_POWERPC_ABS_ADDR_H
-#ifdef __KERNEL__
-
-
-/*
- * c 2001 PPC 64 Team, IBM Corp
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/memblock.h>
-
-#include <asm/types.h>
-#include <asm/page.h>
-#include <asm/prom.h>
-
-struct mschunks_map {
-        unsigned long num_chunks;
-        unsigned long chunk_size;
-        unsigned long chunk_shift;
-        unsigned long chunk_mask;
-        u32 *mapping;
-};
-
-extern struct mschunks_map mschunks_map;
-
-/* Chunks are 256 KB */
-#define MSCHUNKS_CHUNK_SHIFT	(18)
-#define MSCHUNKS_CHUNK_SIZE	(1UL << MSCHUNKS_CHUNK_SHIFT)
-#define MSCHUNKS_OFFSET_MASK	(MSCHUNKS_CHUNK_SIZE - 1)
-
-static inline unsigned long chunk_to_addr(unsigned long chunk)
-{
-	return chunk << MSCHUNKS_CHUNK_SHIFT;
-}
-
-static inline unsigned long addr_to_chunk(unsigned long addr)
-{
-	return addr >> MSCHUNKS_CHUNK_SHIFT;
-}
-
-static inline unsigned long phys_to_abs(unsigned long pa)
-{
-	return pa;
-}
-
-/* Convenience macros */
-#define virt_to_abs(va) phys_to_abs(__pa(va))
-#define abs_to_virt(aa) __va(aa)
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_ABS_ADDR_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/agp.h b/ANDROID_3.4.5/arch/powerpc/include/asm/agp.h
deleted file mode 100644
index 416e12c2..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/agp.h
+++ /dev/null
@@ -1,18 +0,0 @@
-#ifndef _ASM_POWERPC_AGP_H
-#define _ASM_POWERPC_AGP_H
-#ifdef __KERNEL__
-
-#include <asm/io.h>
-
-#define map_page_into_agp(page)
-#define unmap_page_from_agp(page)
-#define flush_agp_cache() mb()
-
-/* GATT allocation. Returns/accepts GATT kernel virtual address. */
-#define alloc_gatt_pages(order)		\
-	((char *)__get_free_pages(GFP_KERNEL, (order)))
-#define free_gatt_pages(table, order)	\
-	free_pages((unsigned long)(table), (order))
-
-#endif /* __KERNEL__ */
-#endif	/* _ASM_POWERPC_AGP_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/asm-compat.h b/ANDROID_3.4.5/arch/powerpc/include/asm/asm-compat.h
deleted file mode 100644
index decad950..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/asm-compat.h
+++ /dev/null
@@ -1,76 +0,0 @@
-#ifndef _ASM_POWERPC_ASM_COMPAT_H
-#define _ASM_POWERPC_ASM_COMPAT_H
-
-#include <asm/types.h>
-#include <asm/ppc-opcode.h>
-
-#ifdef __ASSEMBLY__
-#  define stringify_in_c(...)	__VA_ARGS__
-#  define ASM_CONST(x)		x
-#else
-/* This version of stringify will deal with commas... */
-#  define __stringify_in_c(...)	#__VA_ARGS__
-#  define stringify_in_c(...)	__stringify_in_c(__VA_ARGS__) " "
-#  define __ASM_CONST(x)	x##UL
-#  define ASM_CONST(x)		__ASM_CONST(x)
-#endif
-
-
-#ifdef __powerpc64__
-
-/* operations for longs and pointers */
-#define PPC_LL		stringify_in_c(ld)
-#define PPC_STL		stringify_in_c(std)
-#define PPC_STLU	stringify_in_c(stdu)
-#define PPC_LCMPI	stringify_in_c(cmpdi)
-#define PPC_LONG	stringify_in_c(.llong)
-#define PPC_LONG_ALIGN	stringify_in_c(.balign 8)
-#define PPC_TLNEI	stringify_in_c(tdnei)
-#define PPC_LLARX(t, a, b, eh)	PPC_LDARX(t, a, b, eh)
-#define PPC_STLCX	stringify_in_c(stdcx.)
-#define PPC_CNTLZL	stringify_in_c(cntlzd)
-#define PPC_LR_STKOFF	16
-#define PPC_MIN_STKFRM	112
-
-/* Move to CR, single-entry optimized version. Only available
- * on POWER4 and later.
- */
-#ifdef CONFIG_POWER4_ONLY
-#define PPC_MTOCRF	stringify_in_c(mtocrf)
-#else
-#define PPC_MTOCRF	stringify_in_c(mtcrf)
-#endif
-
-#else /* 32-bit */
-
-/* operations for longs and pointers */
-#define PPC_LL		stringify_in_c(lwz)
-#define PPC_STL		stringify_in_c(stw)
-#define PPC_STLU	stringify_in_c(stwu)
-#define PPC_LCMPI	stringify_in_c(cmpwi)
-#define PPC_LONG	stringify_in_c(.long)
-#define PPC_LONG_ALIGN	stringify_in_c(.balign 4)
-#define PPC_TLNEI	stringify_in_c(twnei)
-#define PPC_LLARX(t, a, b, eh)	PPC_LWARX(t, a, b, eh)
-#define PPC_STLCX	stringify_in_c(stwcx.)
-#define PPC_CNTLZL	stringify_in_c(cntlzw)
-#define PPC_MTOCRF	stringify_in_c(mtcrf)
-#define PPC_LR_STKOFF	4
-#define PPC_MIN_STKFRM	16
-
-#endif
-
-#ifdef __KERNEL__
-#ifdef CONFIG_IBM405_ERR77
-/* Erratum #77 on the 405 means we need a sync or dcbt before every
- * stwcx.  The old ATOMIC_SYNC_FIX covered some but not all of this.
- */
-#define PPC405_ERR77(ra,rb)	stringify_in_c(dcbt	ra, rb;)
-#define	PPC405_ERR77_SYNC	stringify_in_c(sync;)
-#else
-#define PPC405_ERR77(ra,rb)
-#define PPC405_ERR77_SYNC
-#endif
-#endif
-
-#endif /* _ASM_POWERPC_ASM_COMPAT_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/asm-offsets.h b/ANDROID_3.4.5/arch/powerpc/include/asm/asm-offsets.h
deleted file mode 100644
index d370ee36..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/asm-offsets.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <generated/asm-offsets.h>
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/async_tx.h b/ANDROID_3.4.5/arch/powerpc/include/asm/async_tx.h
deleted file mode 100644
index 8b2dc55d..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/async_tx.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright (C) 2008-2009 DENX Software Engineering.
- *
- * Author: Yuri Tikhonov <yur@emcraft.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 59
- * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
- *
- * The full GNU General Public License is included in this distribution in the
- * file called COPYING.
- */
-#ifndef _ASM_POWERPC_ASYNC_TX_H_
-#define _ASM_POWERPC_ASYNC_TX_H_
-
-#if defined(CONFIG_440SPe) || defined(CONFIG_440SP)
-extern struct dma_chan *
-ppc440spe_async_tx_find_best_channel(enum dma_transaction_type cap,
-	struct page **dst_lst, int dst_cnt, struct page **src_lst,
-	int src_cnt, size_t src_sz);
-
-#define async_tx_find_channel(dep, cap, dst_lst, dst_cnt, src_lst, \
-			      src_cnt, src_sz) \
-	ppc440spe_async_tx_find_best_channel(cap, dst_lst, dst_cnt, src_lst, \
-					     src_cnt, src_sz)
-#else
-
-#define async_tx_find_channel(dep, type, dst, dst_count, src, src_count, len) \
-	__async_tx_find_channel(dep, type)
-
-struct dma_chan *
-__async_tx_find_channel(struct async_submit_ctl *submit,
-			enum dma_transaction_type tx_type);
-
-#endif
-
-#endif
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/atomic.h b/ANDROID_3.4.5/arch/powerpc/include/asm/atomic.h
deleted file mode 100644
index da29032a..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/atomic.h
+++ /dev/null
@@ -1,528 +0,0 @@
-#ifndef _ASM_POWERPC_ATOMIC_H_
-#define _ASM_POWERPC_ATOMIC_H_
-
-/*
- * PowerPC atomic operations
- */
-
-#ifdef __KERNEL__
-#include <linux/types.h>
-#include <asm/cmpxchg.h>
-
-#define ATOMIC_INIT(i)		{ (i) }
-
-static __inline__ int atomic_read(const atomic_t *v)
-{
-	int t;
-
-	__asm__ __volatile__("lwz%U1%X1 %0,%1" : "=r"(t) : "m"(v->counter));
-
-	return t;
-}
-
-static __inline__ void atomic_set(atomic_t *v, int i)
-{
-	__asm__ __volatile__("stw%U0%X0 %1,%0" : "=m"(v->counter) : "r"(i));
-}
-
-static __inline__ void atomic_add(int a, atomic_t *v)
-{
-	int t;
-
-	__asm__ __volatile__(
-"1:	lwarx	%0,0,%3		# atomic_add\n\
-	add	%0,%2,%0\n"
-	PPC405_ERR77(0,%3)
-"	stwcx.	%0,0,%3 \n\
-	bne-	1b"
-	: "=&r" (t), "+m" (v->counter)
-	: "r" (a), "r" (&v->counter)
-	: "cc");
-}
-
-static __inline__ int atomic_add_return(int a, atomic_t *v)
-{
-	int t;
-
-	__asm__ __volatile__(
-	PPC_ATOMIC_ENTRY_BARRIER
-"1:	lwarx	%0,0,%2		# atomic_add_return\n\
-	add	%0,%1,%0\n"
-	PPC405_ERR77(0,%2)
-"	stwcx.	%0,0,%2 \n\
-	bne-	1b"
-	PPC_ATOMIC_EXIT_BARRIER
-	: "=&r" (t)
-	: "r" (a), "r" (&v->counter)
-	: "cc", "memory");
-
-	return t;
-}
-
-#define atomic_add_negative(a, v)	(atomic_add_return((a), (v)) < 0)
-
-static __inline__ void atomic_sub(int a, atomic_t *v)
-{
-	int t;
-
-	__asm__ __volatile__(
-"1:	lwarx	%0,0,%3		# atomic_sub\n\
-	subf	%0,%2,%0\n"
-	PPC405_ERR77(0,%3)
-"	stwcx.	%0,0,%3 \n\
-	bne-	1b"
-	: "=&r" (t), "+m" (v->counter)
-	: "r" (a), "r" (&v->counter)
-	: "cc");
-}
-
-static __inline__ int atomic_sub_return(int a, atomic_t *v)
-{
-	int t;
-
-	__asm__ __volatile__(
-	PPC_ATOMIC_ENTRY_BARRIER
-"1:	lwarx	%0,0,%2		# atomic_sub_return\n\
-	subf	%0,%1,%0\n"
-	PPC405_ERR77(0,%2)
-"	stwcx.	%0,0,%2 \n\
-	bne-	1b"
-	PPC_ATOMIC_EXIT_BARRIER
-	: "=&r" (t)
-	: "r" (a), "r" (&v->counter)
-	: "cc", "memory");
-
-	return t;
-}
-
-static __inline__ void atomic_inc(atomic_t *v)
-{
-	int t;
-
-	__asm__ __volatile__(
-"1:	lwarx	%0,0,%2		# atomic_inc\n\
-	addic	%0,%0,1\n"
-	PPC405_ERR77(0,%2)
-"	stwcx.	%0,0,%2 \n\
-	bne-	1b"
-	: "=&r" (t), "+m" (v->counter)
-	: "r" (&v->counter)
-	: "cc", "xer");
-}
-
-static __inline__ int atomic_inc_return(atomic_t *v)
-{
-	int t;
-
-	__asm__ __volatile__(
-	PPC_ATOMIC_ENTRY_BARRIER
-"1:	lwarx	%0,0,%1		# atomic_inc_return\n\
-	addic	%0,%0,1\n"
-	PPC405_ERR77(0,%1)
-"	stwcx.	%0,0,%1 \n\
-	bne-	1b"
-	PPC_ATOMIC_EXIT_BARRIER
-	: "=&r" (t)
-	: "r" (&v->counter)
-	: "cc", "xer", "memory");
-
-	return t;
-}
-
-/*
- * atomic_inc_and_test - increment and test
- * @v: pointer of type atomic_t
- *
- * Atomically increments @v by 1
- * and returns true if the result is zero, or false for all
- * other cases.
- */
-#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
-
-static __inline__ void atomic_dec(atomic_t *v)
-{
-	int t;
-
-	__asm__ __volatile__(
-"1:	lwarx	%0,0,%2		# atomic_dec\n\
-	addic	%0,%0,-1\n"
-	PPC405_ERR77(0,%2)\
-"	stwcx.	%0,0,%2\n\
-	bne-	1b"
-	: "=&r" (t), "+m" (v->counter)
-	: "r" (&v->counter)
-	: "cc", "xer");
-}
-
-static __inline__ int atomic_dec_return(atomic_t *v)
-{
-	int t;
-
-	__asm__ __volatile__(
-	PPC_ATOMIC_ENTRY_BARRIER
-"1:	lwarx	%0,0,%1		# atomic_dec_return\n\
-	addic	%0,%0,-1\n"
-	PPC405_ERR77(0,%1)
-"	stwcx.	%0,0,%1\n\
-	bne-	1b"
-	PPC_ATOMIC_EXIT_BARRIER
-	: "=&r" (t)
-	: "r" (&v->counter)
-	: "cc", "xer", "memory");
-
-	return t;
-}
-
-#define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
-#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
-
-/**
- * __atomic_add_unless - add unless the number is a given value
- * @v: pointer of type atomic_t
- * @a: the amount to add to v...
- * @u: ...unless v is equal to u.
- *
- * Atomically adds @a to @v, so long as it was not @u.
- * Returns the old value of @v.
- */
-static __inline__ int __atomic_add_unless(atomic_t *v, int a, int u)
-{
-	int t;
-
-	__asm__ __volatile__ (
-	PPC_ATOMIC_ENTRY_BARRIER
-"1:	lwarx	%0,0,%1		# __atomic_add_unless\n\
-	cmpw	0,%0,%3 \n\
-	beq-	2f \n\
-	add	%0,%2,%0 \n"
-	PPC405_ERR77(0,%2)
-"	stwcx.	%0,0,%1 \n\
-	bne-	1b \n"
-	PPC_ATOMIC_EXIT_BARRIER
-"	subf	%0,%2,%0 \n\
-2:"
-	: "=&r" (t)
-	: "r" (&v->counter), "r" (a), "r" (u)
-	: "cc", "memory");
-
-	return t;
-}
-
-/**
- * atomic_inc_not_zero - increment unless the number is zero
- * @v: pointer of type atomic_t
- *
- * Atomically increments @v by 1, so long as @v is non-zero.
- * Returns non-zero if @v was non-zero, and zero otherwise.
- */
-static __inline__ int atomic_inc_not_zero(atomic_t *v)
-{
-	int t1, t2;
-
-	__asm__ __volatile__ (
-	PPC_ATOMIC_ENTRY_BARRIER
-"1:	lwarx	%0,0,%2		# atomic_inc_not_zero\n\
-	cmpwi	0,%0,0\n\
-	beq-	2f\n\
-	addic	%1,%0,1\n"
-	PPC405_ERR77(0,%2)
-"	stwcx.	%1,0,%2\n\
-	bne-	1b\n"
-	PPC_ATOMIC_EXIT_BARRIER
-	"\n\
-2:"
-	: "=&r" (t1), "=&r" (t2)
-	: "r" (&v->counter)
-	: "cc", "xer", "memory");
-
-	return t1;
-}
-#define atomic_inc_not_zero(v) atomic_inc_not_zero((v))
-
-#define atomic_sub_and_test(a, v)	(atomic_sub_return((a), (v)) == 0)
-#define atomic_dec_and_test(v)		(atomic_dec_return((v)) == 0)
-
-/*
- * Atomically test *v and decrement if it is greater than 0.
- * The function returns the old value of *v minus 1, even if
- * the atomic variable, v, was not decremented.
- */
-static __inline__ int atomic_dec_if_positive(atomic_t *v)
-{
-	int t;
-
-	__asm__ __volatile__(
-	PPC_ATOMIC_ENTRY_BARRIER
-"1:	lwarx	%0,0,%1		# atomic_dec_if_positive\n\
-	cmpwi	%0,1\n\
-	addi	%0,%0,-1\n\
-	blt-	2f\n"
-	PPC405_ERR77(0,%1)
-"	stwcx.	%0,0,%1\n\
-	bne-	1b"
-	PPC_ATOMIC_EXIT_BARRIER
-	"\n\
-2:"	: "=&b" (t)
-	: "r" (&v->counter)
-	: "cc", "memory");
-
-	return t;
-}
-
-#define smp_mb__before_atomic_dec()     smp_mb()
-#define smp_mb__after_atomic_dec()      smp_mb()
-#define smp_mb__before_atomic_inc()     smp_mb()
-#define smp_mb__after_atomic_inc()      smp_mb()
-
-#ifdef __powerpc64__
-
-#define ATOMIC64_INIT(i)	{ (i) }
-
-static __inline__ long atomic64_read(const atomic64_t *v)
-{
-	long t;
-
-	__asm__ __volatile__("ld%U1%X1 %0,%1" : "=r"(t) : "m"(v->counter));
-
-	return t;
-}
-
-static __inline__ void atomic64_set(atomic64_t *v, long i)
-{
-	__asm__ __volatile__("std%U0%X0 %1,%0" : "=m"(v->counter) : "r"(i));
-}
-
-static __inline__ void atomic64_add(long a, atomic64_t *v)
-{
-	long t;
-
-	__asm__ __volatile__(
-"1:	ldarx	%0,0,%3		# atomic64_add\n\
-	add	%0,%2,%0\n\
-	stdcx.	%0,0,%3 \n\
-	bne-	1b"
-	: "=&r" (t), "+m" (v->counter)
-	: "r" (a), "r" (&v->counter)
-	: "cc");
-}
-
-static __inline__ long atomic64_add_return(long a, atomic64_t *v)
-{
-	long t;
-
-	__asm__ __volatile__(
-	PPC_ATOMIC_ENTRY_BARRIER
-"1:	ldarx	%0,0,%2		# atomic64_add_return\n\
-	add	%0,%1,%0\n\
-	stdcx.	%0,0,%2 \n\
-	bne-	1b"
-	PPC_ATOMIC_EXIT_BARRIER
-	: "=&r" (t)
-	: "r" (a), "r" (&v->counter)
-	: "cc", "memory");
-
-	return t;
-}
-
-#define atomic64_add_negative(a, v)	(atomic64_add_return((a), (v)) < 0)
-
-static __inline__ void atomic64_sub(long a, atomic64_t *v)
-{
-	long t;
-
-	__asm__ __volatile__(
-"1:	ldarx	%0,0,%3		# atomic64_sub\n\
-	subf	%0,%2,%0\n\
-	stdcx.	%0,0,%3 \n\
-	bne-	1b"
-	: "=&r" (t), "+m" (v->counter)
-	: "r" (a), "r" (&v->counter)
-	: "cc");
-}
-
-static __inline__ long atomic64_sub_return(long a, atomic64_t *v)
-{
-	long t;
-
-	__asm__ __volatile__(
-	PPC_ATOMIC_ENTRY_BARRIER
-"1:	ldarx	%0,0,%2		# atomic64_sub_return\n\
-	subf	%0,%1,%0\n\
-	stdcx.	%0,0,%2 \n\
-	bne-	1b"
-	PPC_ATOMIC_EXIT_BARRIER
-	: "=&r" (t)
-	: "r" (a), "r" (&v->counter)
-	: "cc", "memory");
-
-	return t;
-}
-
-static __inline__ void atomic64_inc(atomic64_t *v)
-{
-	long t;
-
-	__asm__ __volatile__(
-"1:	ldarx	%0,0,%2		# atomic64_inc\n\
-	addic	%0,%0,1\n\
-	stdcx.	%0,0,%2 \n\
-	bne-	1b"
-	: "=&r" (t), "+m" (v->counter)
-	: "r" (&v->counter)
-	: "cc", "xer");
-}
-
-static __inline__ long atomic64_inc_return(atomic64_t *v)
-{
-	long t;
-
-	__asm__ __volatile__(
-	PPC_ATOMIC_ENTRY_BARRIER
-"1:	ldarx	%0,0,%1		# atomic64_inc_return\n\
-	addic	%0,%0,1\n\
-	stdcx.	%0,0,%1 \n\
-	bne-	1b"
-	PPC_ATOMIC_EXIT_BARRIER
-	: "=&r" (t)
-	: "r" (&v->counter)
-	: "cc", "xer", "memory");
-
-	return t;
-}
-
-/*
- * atomic64_inc_and_test - increment and test
- * @v: pointer of type atomic64_t
- *
- * Atomically increments @v by 1
- * and returns true if the result is zero, or false for all
- * other cases.
- */
-#define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
-
-static __inline__ void atomic64_dec(atomic64_t *v)
-{
-	long t;
-
-	__asm__ __volatile__(
-"1:	ldarx	%0,0,%2		# atomic64_dec\n\
-	addic	%0,%0,-1\n\
-	stdcx.	%0,0,%2\n\
-	bne-	1b"
-	: "=&r" (t), "+m" (v->counter)
-	: "r" (&v->counter)
-	: "cc", "xer");
-}
-
-static __inline__ long atomic64_dec_return(atomic64_t *v)
-{
-	long t;
-
-	__asm__ __volatile__(
-	PPC_ATOMIC_ENTRY_BARRIER
-"1:	ldarx	%0,0,%1		# atomic64_dec_return\n\
-	addic	%0,%0,-1\n\
-	stdcx.	%0,0,%1\n\
-	bne-	1b"
-	PPC_ATOMIC_EXIT_BARRIER
-	: "=&r" (t)
-	: "r" (&v->counter)
-	: "cc", "xer", "memory");
-
-	return t;
-}
-
-#define atomic64_sub_and_test(a, v)	(atomic64_sub_return((a), (v)) == 0)
-#define atomic64_dec_and_test(v)	(atomic64_dec_return((v)) == 0)
-
-/*
- * Atomically test *v and decrement if it is greater than 0.
- * The function returns the old value of *v minus 1.
- */
-static __inline__ long atomic64_dec_if_positive(atomic64_t *v)
-{
-	long t;
-
-	__asm__ __volatile__(
-	PPC_ATOMIC_ENTRY_BARRIER
-"1:	ldarx	%0,0,%1		# atomic64_dec_if_positive\n\
-	addic.	%0,%0,-1\n\
-	blt-	2f\n\
-	stdcx.	%0,0,%1\n\
-	bne-	1b"
-	PPC_ATOMIC_EXIT_BARRIER
-	"\n\
-2:"	: "=&r" (t)
-	: "r" (&v->counter)
-	: "cc", "xer", "memory");
-
-	return t;
-}
-
-#define atomic64_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
-#define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
-
-/**
- * atomic64_add_unless - add unless the number is a given value
- * @v: pointer of type atomic64_t
- * @a: the amount to add to v...
- * @u: ...unless v is equal to u.
- *
- * Atomically adds @a to @v, so long as it was not @u.
- * Returns the old value of @v.
- */
-static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
-{
-	long t;
-
-	__asm__ __volatile__ (
-	PPC_ATOMIC_ENTRY_BARRIER
-"1:	ldarx	%0,0,%1		# __atomic_add_unless\n\
-	cmpd	0,%0,%3 \n\
-	beq-	2f \n\
-	add	%0,%2,%0 \n"
-"	stdcx.	%0,0,%1 \n\
-	bne-	1b \n"
-	PPC_ATOMIC_EXIT_BARRIER
-"	subf	%0,%2,%0 \n\
-2:"
-	: "=&r" (t)
-	: "r" (&v->counter), "r" (a), "r" (u)
-	: "cc", "memory");
-
-	return t != u;
-}
-
-/**
- * atomic_inc64_not_zero - increment unless the number is zero
- * @v: pointer of type atomic64_t
- *
- * Atomically increments @v by 1, so long as @v is non-zero.
- * Returns non-zero if @v was non-zero, and zero otherwise.
- */
-static __inline__ long atomic64_inc_not_zero(atomic64_t *v)
-{
-	long t1, t2;
-
-	__asm__ __volatile__ (
-	PPC_ATOMIC_ENTRY_BARRIER
-"1:	ldarx	%0,0,%2		# atomic64_inc_not_zero\n\
-	cmpdi	0,%0,0\n\
-	beq-	2f\n\
-	addic	%1,%0,1\n\
-	stdcx.	%1,0,%2\n\
-	bne-	1b\n"
-	PPC_ATOMIC_EXIT_BARRIER
-	"\n\
-2:"
-	: "=&r" (t1), "=&r" (t2)
-	: "r" (&v->counter)
-	: "cc", "xer", "memory");
-
-	return t1;
-}
-
-#endif /* __powerpc64__ */
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_ATOMIC_H_ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/auxvec.h b/ANDROID_3.4.5/arch/powerpc/include/asm/auxvec.h
deleted file mode 100644
index ce17d2c9..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/auxvec.h
+++ /dev/null
@@ -1,21 +0,0 @@
-#ifndef _ASM_POWERPC_AUXVEC_H
-#define _ASM_POWERPC_AUXVEC_H
-
-/*
- * We need to put in some extra aux table entries to tell glibc what
- * the cache block size is, so it can use the dcbz instruction safely.
- */
-#define AT_DCACHEBSIZE		19
-#define AT_ICACHEBSIZE		20
-#define AT_UCACHEBSIZE		21
-/* A special ignored type value for PPC, for glibc compatibility.  */
-#define AT_IGNOREPPC		22
-
-/* The vDSO location. We have to use the same value as x86 for glibc's
- * sake :-)
- */
-#define AT_SYSINFO_EHDR		33
-
-#define AT_VECTOR_SIZE_ARCH 6 /* entries in ARCH_DLINFO */
-
-#endif
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/backlight.h b/ANDROID_3.4.5/arch/powerpc/include/asm/backlight.h
deleted file mode 100644
index 8cf5c37c..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/backlight.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Routines for handling backlight control on PowerBooks
- *
- * For now, implementation resides in
- * arch/powerpc/platforms/powermac/backlight.c
- *
- */
-#ifndef __ASM_POWERPC_BACKLIGHT_H
-#define __ASM_POWERPC_BACKLIGHT_H
-#ifdef __KERNEL__
-
-#include <linux/fb.h>
-#include <linux/mutex.h>
-
-/* For locking instructions, see the implementation file */
-extern struct backlight_device *pmac_backlight;
-extern struct mutex pmac_backlight_mutex;
-
-extern int pmac_backlight_curve_lookup(struct fb_info *info, int value);
-
-extern int pmac_has_backlight_type(const char *type);
-
-extern void pmac_backlight_key(int direction);
-static inline void pmac_backlight_key_up(void)
-{
-	pmac_backlight_key(0);
-}
-static inline void pmac_backlight_key_down(void)
-{
-	pmac_backlight_key(1);
-}
-
-extern void pmac_backlight_set_legacy_brightness_pmu(int brightness);
-extern int pmac_backlight_set_legacy_brightness(int brightness);
-extern int pmac_backlight_get_legacy_brightness(void);
-
-extern void pmac_backlight_enable(void);
-extern void pmac_backlight_disable(void);
-
-#endif /* __KERNEL__ */
-#endif
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/barrier.h b/ANDROID_3.4.5/arch/powerpc/include/asm/barrier.h
deleted file mode 100644
index ae782254..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/barrier.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
- */
-#ifndef _ASM_POWERPC_BARRIER_H
-#define _ASM_POWERPC_BARRIER_H
-
-/*
- * Memory barrier.
- * The sync instruction guarantees that all memory accesses initiated
- * by this processor have been performed (with respect to all other
- * mechanisms that access memory).  The eieio instruction is a barrier
- * providing an ordering (separately) for (a) cacheable stores and (b)
- * loads and stores to non-cacheable memory (e.g. I/O devices).
- *
- * mb() prevents loads and stores being reordered across this point.
- * rmb() prevents loads being reordered across this point.
- * wmb() prevents stores being reordered across this point.
- * read_barrier_depends() prevents data-dependent loads being reordered
- *	across this point (nop on PPC).
- *
- * *mb() variants without smp_ prefix must order all types of memory
- * operations with one another. sync is the only instruction sufficient
- * to do this.
- *
- * For the smp_ barriers, ordering is for cacheable memory operations
- * only. We have to use the sync instruction for smp_mb(), since lwsync
- * doesn't order loads with respect to previous stores.  Lwsync can be
- * used for smp_rmb() and smp_wmb().
- *
- * However, on CPUs that don't support lwsync, lwsync actually maps to a
- * heavy-weight sync, so smp_wmb() can be a lighter-weight eieio.
- */
-#define mb()   __asm__ __volatile__ ("sync" : : : "memory")
-#define rmb()  __asm__ __volatile__ ("sync" : : : "memory")
-#define wmb()  __asm__ __volatile__ ("sync" : : : "memory")
-#define read_barrier_depends()  do { } while(0)
-
-#define set_mb(var, value)	do { var = value; mb(); } while (0)
-
-#ifdef CONFIG_SMP
-
-#ifdef __SUBARCH_HAS_LWSYNC
-#    define SMPWMB      LWSYNC
-#else
-#    define SMPWMB      eieio
-#endif
-
-#define smp_mb()	mb()
-#define smp_rmb()	__asm__ __volatile__ (stringify_in_c(LWSYNC) : : :"memory")
-#define smp_wmb()	__asm__ __volatile__ (stringify_in_c(SMPWMB) : : :"memory")
-#define smp_read_barrier_depends()	read_barrier_depends()
-#else
-#define smp_mb()	barrier()
-#define smp_rmb()	barrier()
-#define smp_wmb()	barrier()
-#define smp_read_barrier_depends()	do { } while(0)
-#endif /* CONFIG_SMP */
-
-/*
- * This is a barrier which prevents following instructions from being
- * started until the value of the argument x is known.  For example, if
- * x is a variable loaded from memory, this prevents following
- * instructions from being executed until the load has been performed.
- */
-#define data_barrier(x)	\
-	asm volatile("twi 0,%0,0; isync" : : "r" (x) : "memory");
-
-#endif /* _ASM_POWERPC_BARRIER_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/bitops.h b/ANDROID_3.4.5/arch/powerpc/include/asm/bitops.h
deleted file mode 100644
index efdc9261..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/bitops.h
+++ /dev/null
@@ -1,336 +0,0 @@
-/*
- * PowerPC atomic bit operations.
- *
- * Merged version by David Gibson <david@gibson.dropbear.id.au>.
- * Based on ppc64 versions by: Dave Engebretsen, Todd Inglett, Don
- * Reed, Pat McCarthy, Peter Bergner, Anton Blanchard.  They
- * originally took it from the ppc32 code.
- *
- * Within a word, bits are numbered LSB first.  Lot's of places make
- * this assumption by directly testing bits with (val & (1<<nr)).
- * This can cause confusion for large (> 1 word) bitmaps on a
- * big-endian system because, unlike little endian, the number of each
- * bit depends on the word size.
- *
- * The bitop functions are defined to work on unsigned longs, so for a
- * ppc64 system the bits end up numbered:
- *   |63..............0|127............64|191...........128|255...........196|
- * and on ppc32:
- *   |31.....0|63....31|95....64|127...96|159..128|191..160|223..192|255..224|
- *
- * There are a few little-endian macros used mostly for filesystem
- * bitmaps, these work on similar bit arrays layouts, but
- * byte-oriented:
- *   |7...0|15...8|23...16|31...24|39...32|47...40|55...48|63...56|
- *
- * The main difference is that bit 3-5 (64b) or 3-4 (32b) in the bit
- * number field needs to be reversed compared to the big-endian bit
- * fields. This can be achieved by XOR with 0x38 (64b) or 0x18 (32b).
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_POWERPC_BITOPS_H
-#define _ASM_POWERPC_BITOPS_H
-
-#ifdef __KERNEL__
-
-#ifndef _LINUX_BITOPS_H
-#error only <linux/bitops.h> can be included directly
-#endif
-
-#include <linux/compiler.h>
-#include <asm/asm-compat.h>
-#include <asm/synch.h>
-
-/*
- * clear_bit doesn't imply a memory barrier
- */
-#define smp_mb__before_clear_bit()	smp_mb()
-#define smp_mb__after_clear_bit()	smp_mb()
-
-#define BITOP_MASK(nr)		(1UL << ((nr) % BITS_PER_LONG))
-#define BITOP_WORD(nr)		((nr) / BITS_PER_LONG)
-#define BITOP_LE_SWIZZLE	((BITS_PER_LONG-1) & ~0x7)
-
-/* Macro for generating the ***_bits() functions */
-#define DEFINE_BITOP(fn, op, prefix, postfix)	\
-static __inline__ void fn(unsigned long mask,	\
-		volatile unsigned long *_p)	\
-{						\
-	unsigned long old;			\
-	unsigned long *p = (unsigned long *)_p;	\
-	__asm__ __volatile__ (			\
-	prefix					\
-"1:"	PPC_LLARX(%0,0,%3,0) "\n"		\
-	stringify_in_c(op) "%0,%0,%2\n"		\
-	PPC405_ERR77(0,%3)			\
-	PPC_STLCX "%0,0,%3\n"			\
-	"bne- 1b\n"				\
-	postfix					\
-	: "=&r" (old), "+m" (*p)		\
-	: "r" (mask), "r" (p)			\
-	: "cc", "memory");			\
-}
-
-DEFINE_BITOP(set_bits, or, "", "")
-DEFINE_BITOP(clear_bits, andc, "", "")
-DEFINE_BITOP(clear_bits_unlock, andc, PPC_RELEASE_BARRIER, "")
-DEFINE_BITOP(change_bits, xor, "", "")
-
-static __inline__ void set_bit(int nr, volatile unsigned long *addr)
-{
-	set_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr));
-}
-
-static __inline__ void clear_bit(int nr, volatile unsigned long *addr)
-{
-	clear_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr));
-}
-
-static __inline__ void clear_bit_unlock(int nr, volatile unsigned long *addr)
-{
-	clear_bits_unlock(BITOP_MASK(nr), addr + BITOP_WORD(nr));
-}
-
-static __inline__ void change_bit(int nr, volatile unsigned long *addr)
-{
-	change_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr));
-}
-
-/* Like DEFINE_BITOP(), with changes to the arguments to 'op' and the output
- * operands. */
-#define DEFINE_TESTOP(fn, op, prefix, postfix, eh)	\
-static __inline__ unsigned long fn(			\
-		unsigned long mask,			\
-		volatile unsigned long *_p)		\
-{							\
-	unsigned long old, t;				\
-	unsigned long *p = (unsigned long *)_p;		\
-	__asm__ __volatile__ (				\
-	prefix						\
-"1:"	PPC_LLARX(%0,0,%3,eh) "\n"			\
-	stringify_in_c(op) "%1,%0,%2\n"			\
-	PPC405_ERR77(0,%3)				\
-	PPC_STLCX "%1,0,%3\n"				\
-	"bne- 1b\n"					\
-	postfix						\
-	: "=&r" (old), "=&r" (t)			\
-	: "r" (mask), "r" (p)				\
-	: "cc", "memory");				\
-	return (old & mask);				\
-}
-
-DEFINE_TESTOP(test_and_set_bits, or, PPC_ATOMIC_ENTRY_BARRIER,
-	      PPC_ATOMIC_EXIT_BARRIER, 0)
-DEFINE_TESTOP(test_and_set_bits_lock, or, "",
-	      PPC_ACQUIRE_BARRIER, 1)
-DEFINE_TESTOP(test_and_clear_bits, andc, PPC_ATOMIC_ENTRY_BARRIER,
-	      PPC_ATOMIC_EXIT_BARRIER, 0)
-DEFINE_TESTOP(test_and_change_bits, xor, PPC_ATOMIC_ENTRY_BARRIER,
-	      PPC_ATOMIC_EXIT_BARRIER, 0)
-
-static __inline__ int test_and_set_bit(unsigned long nr,
-				       volatile unsigned long *addr)
-{
-	return test_and_set_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr)) != 0;
-}
-
-static __inline__ int test_and_set_bit_lock(unsigned long nr,
-				       volatile unsigned long *addr)
-{
-	return test_and_set_bits_lock(BITOP_MASK(nr),
-				addr + BITOP_WORD(nr)) != 0;
-}
-
-static __inline__ int test_and_clear_bit(unsigned long nr,
-					 volatile unsigned long *addr)
-{
-	return test_and_clear_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr)) != 0;
-}
-
-static __inline__ int test_and_change_bit(unsigned long nr,
-					  volatile unsigned long *addr)
-{
-	return test_and_change_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr)) != 0;
-}
-
-#include <asm-generic/bitops/non-atomic.h>
-
-static __inline__ void __clear_bit_unlock(int nr, volatile unsigned long *addr)
-{
-	__asm__ __volatile__(PPC_RELEASE_BARRIER "" ::: "memory");
-	__clear_bit(nr, addr);
-}
-
-/*
- * Return the zero-based bit position (LE, not IBM bit numbering) of
- * the most significant 1-bit in a double word.
- */
-static __inline__ __attribute__((const))
-int __ilog2(unsigned long x)
-{
-	int lz;
-
-	asm (PPC_CNTLZL "%0,%1" : "=r" (lz) : "r" (x));
-	return BITS_PER_LONG - 1 - lz;
-}
-
-static inline __attribute__((const))
-int __ilog2_u32(u32 n)
-{
-	int bit;
-	asm ("cntlzw %0,%1" : "=r" (bit) : "r" (n));
-	return 31 - bit;
-}
-
-#ifdef __powerpc64__
-static inline __attribute__((const))
-int __ilog2_u64(u64 n)
-{
-	int bit;
-	asm ("cntlzd %0,%1" : "=r" (bit) : "r" (n));
-	return 63 - bit;
-}
-#endif
-
-/*
- * Determines the bit position of the least significant 0 bit in the
- * specified double word. The returned bit position will be
- * zero-based, starting from the right side (63/31 - 0).
- */
-static __inline__ unsigned long ffz(unsigned long x)
-{
-	/* no zero exists anywhere in the 8 byte area. */
-	if ((x = ~x) == 0)
-		return BITS_PER_LONG;
-
-	/*
-	 * Calculate the bit position of the least significant '1' bit in x
-	 * (since x has been changed this will actually be the least significant
-	 * '0' bit in * the original x).  Note: (x & -x) gives us a mask that
-	 * is the least significant * (RIGHT-most) 1-bit of the value in x.
-	 */
-	return __ilog2(x & -x);
-}
-
-static __inline__ int __ffs(unsigned long x)
-{
-	return __ilog2(x & -x);
-}
-
-/*
- * ffs: find first bit set. This is defined the same way as
- * the libc and compiler builtin ffs routines, therefore
- * differs in spirit from the above ffz (man ffs).
- */
-static __inline__ int ffs(int x)
-{
-	unsigned long i = (unsigned long)x;
-	return __ilog2(i & -i) + 1;
-}
-
-/*
- * fls: find last (most-significant) bit set.
- * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
- */
-static __inline__ int fls(unsigned int x)
-{
-	int lz;
-
-	asm ("cntlzw %0,%1" : "=r" (lz) : "r" (x));
-	return 32 - lz;
-}
-
-static __inline__ unsigned long __fls(unsigned long x)
-{
-	return __ilog2(x);
-}
-
-/*
- * 64-bit can do this using one cntlzd (count leading zeroes doubleword)
- * instruction; for 32-bit we use the generic version, which does two
- * 32-bit fls calls.
- */
-#ifdef __powerpc64__
-static __inline__ int fls64(__u64 x)
-{
-	int lz;
-
-	asm ("cntlzd %0,%1" : "=r" (lz) : "r" (x));
-	return 64 - lz;
-}
-#else
-#include <asm-generic/bitops/fls64.h>
-#endif /* __powerpc64__ */
-
-#ifdef CONFIG_PPC64
-unsigned int __arch_hweight8(unsigned int w);
-unsigned int __arch_hweight16(unsigned int w);
-unsigned int __arch_hweight32(unsigned int w);
-unsigned long __arch_hweight64(__u64 w);
-#include <asm-generic/bitops/const_hweight.h>
-#else
-#include <asm-generic/bitops/hweight.h>
-#endif
-
-#include <asm-generic/bitops/find.h>
-
-/* Little-endian versions */
-
-static __inline__ int test_bit_le(unsigned long nr,
-				  __const__ void *addr)
-{
-	__const__ unsigned char	*tmp = (__const__ unsigned char *) addr;
-	return (tmp[nr >> 3] >> (nr & 7)) & 1;
-}
-
-static inline void __set_bit_le(int nr, void *addr)
-{
-	__set_bit(nr ^ BITOP_LE_SWIZZLE, addr);
-}
-
-static inline void __clear_bit_le(int nr, void *addr)
-{
-	__clear_bit(nr ^ BITOP_LE_SWIZZLE, addr);
-}
-
-static inline int test_and_set_bit_le(int nr, void *addr)
-{
-	return test_and_set_bit(nr ^ BITOP_LE_SWIZZLE, addr);
-}
-
-static inline int test_and_clear_bit_le(int nr, void *addr)
-{
-	return test_and_clear_bit(nr ^ BITOP_LE_SWIZZLE, addr);
-}
-
-static inline int __test_and_set_bit_le(int nr, void *addr)
-{
-	return __test_and_set_bit(nr ^ BITOP_LE_SWIZZLE, addr);
-}
-
-static inline int __test_and_clear_bit_le(int nr, void *addr)
-{
-	return __test_and_clear_bit(nr ^ BITOP_LE_SWIZZLE, addr);
-}
-
-#define find_first_zero_bit_le(addr, size) \
-	find_next_zero_bit_le((addr), (size), 0)
-unsigned long find_next_zero_bit_le(const void *addr,
-				    unsigned long size, unsigned long offset);
-
-unsigned long find_next_bit_le(const void *addr,
-				    unsigned long size, unsigned long offset);
-/* Bitmap functions for the ext2 filesystem */
-
-#include <asm-generic/bitops/ext2-atomic-setbit.h>
-
-#include <asm-generic/bitops/sched.h>
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_POWERPC_BITOPS_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/bitsperlong.h b/ANDROID_3.4.5/arch/powerpc/include/asm/bitsperlong.h
deleted file mode 100644
index 5f165903..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/bitsperlong.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef __ASM_POWERPC_BITSPERLONG_H
-#define __ASM_POWERPC_BITSPERLONG_H
-
-#if defined(__powerpc64__)
-# define __BITS_PER_LONG 64
-#else
-# define __BITS_PER_LONG 32
-#endif
-
-#include <asm-generic/bitsperlong.h>
-
-#endif /* __ASM_POWERPC_BITSPERLONG_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/bootx.h b/ANDROID_3.4.5/arch/powerpc/include/asm/bootx.h
deleted file mode 100644
index 60a3c9ef..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/bootx.h
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * This file describes the structure passed from the BootX application
- * (for MacOS) when it is used to boot Linux.
- *
- * Written by Benjamin Herrenschmidt.
- */
-
-
-#ifndef __ASM_BOOTX_H__
-#define __ASM_BOOTX_H__
-
-#include <linux/types.h>
-
-#ifdef macintosh
-#include <Types.h>
-#include "linux_type_defs.h"
-#endif
-
-#ifdef macintosh
-/* All this requires PowerPC alignment */
-#pragma options align=power
-#endif
-
-/* On kernel entry:
- *
- * r3 = 0x426f6f58    ('BooX')
- * r4 = pointer to boot_infos
- * r5 = NULL
- *
- * Data and instruction translation disabled, interrupts
- * disabled, kernel loaded at physical 0x00000000 on PCI
- * machines (will be different on NuBus).
- */
-
-#define BOOT_INFO_VERSION               5
-#define BOOT_INFO_COMPATIBLE_VERSION    1
-
-/* Bit in the architecture flag mask. More to be defined in
-   future versions. Note that either BOOT_ARCH_PCI or
-   BOOT_ARCH_NUBUS is set. The other BOOT_ARCH_NUBUS_xxx are
-   set additionally when BOOT_ARCH_NUBUS is set.
- */
-#define BOOT_ARCH_PCI                   0x00000001UL
-#define BOOT_ARCH_NUBUS                 0x00000002UL
-#define BOOT_ARCH_NUBUS_PDM             0x00000010UL
-#define BOOT_ARCH_NUBUS_PERFORMA        0x00000020UL
-#define BOOT_ARCH_NUBUS_POWERBOOK       0x00000040UL
-
-/*  Maximum number of ranges in phys memory map */
-#define MAX_MEM_MAP_SIZE				26
-
-/* This is the format of an element in the physical memory map. Note that
-   the map is optional and current BootX will only build it for pre-PCI
-   machines */
-typedef struct boot_info_map_entry
-{
-    __u32       physAddr;                /* Physical starting address */
-    __u32       size;                    /* Size in bytes */
-} boot_info_map_entry_t;
-
-
-/* Here are the boot informations that are passed to the bootstrap
- * Note that the kernel arguments and the device tree are appended
- * at the end of this structure. */
-typedef struct boot_infos
-{
-    /* Version of this structure */
-    __u32       version;
-    /* backward compatible down to version: */
-    __u32       compatible_version;
-
-    /* NEW (vers. 2) this holds the current _logical_ base addr of
-       the frame buffer (for use by early boot message) */
-    __u8*       logicalDisplayBase;
-
-    /* NEW (vers. 4) Apple's machine identification */
-    __u32       machineID;
-
-    /* NEW (vers. 4) Detected hw architecture */
-    __u32       architecture;
-
-    /* The device tree (internal addresses relative to the beginning of the tree,
-     * device tree offset relative to the beginning of this structure).
-     * On pre-PCI macintosh (BOOT_ARCH_PCI bit set to 0 in architecture), this
-     * field is 0.
-     */
-    __u32       deviceTreeOffset;        /* Device tree offset */
-    __u32       deviceTreeSize;          /* Size of the device tree */
-
-    /* Some infos about the current MacOS display */
-    __u32       dispDeviceRect[4];       /* left,top,right,bottom */
-    __u32       dispDeviceDepth;         /* (8, 16 or 32) */
-    __u8*       dispDeviceBase;          /* base address (physical) */
-    __u32       dispDeviceRowBytes;      /* rowbytes (in bytes) */
-    __u32       dispDeviceColorsOffset;  /* Colormap (8 bits only) or 0 (*) */
-    /* Optional offset in the registry to the current
-     * MacOS display. (Can be 0 when not detected) */
-     __u32      dispDeviceRegEntryOffset;
-
-    /* Optional pointer to boot ramdisk (offset from this structure) */
-    __u32       ramDisk;
-    __u32       ramDiskSize;             /* size of ramdisk image */
-
-    /* Kernel command line arguments (offset from this structure) */
-    __u32       kernelParamsOffset;
-
-    /* ALL BELOW NEW (vers. 4) */
-
-    /* This defines the physical memory. Valid with BOOT_ARCH_NUBUS flag
-       (non-PCI) only. On PCI, memory is contiguous and it's size is in the
-       device-tree. */
-    boot_info_map_entry_t
-    	        physMemoryMap[MAX_MEM_MAP_SIZE]; /* Where the phys memory is */
-    __u32       physMemoryMapSize;               /* How many entries in map */
-
-
-    /* The framebuffer size (optional, currently 0) */
-    __u32       frameBufferSize;         /* Represents a max size, can be 0. */
-
-    /* NEW (vers. 5) */
-
-    /* Total params size (args + colormap + device tree + ramdisk) */
-    __u32       totalParamsSize;
-
-} boot_infos_t;
-
-#ifdef __KERNEL__
-/* (*) The format of the colormap is 256 * 3 * 2 bytes. Each color index
- * is represented by 3 short words containing a 16 bits (unsigned) color
- * component. Later versions may contain the gamma table for direct-color
- * devices here.
- */
-#define BOOTX_COLORTABLE_SIZE    (256UL*3UL*2UL)
-
-/* BootX passes the device-tree using a format that comes from earlier
- * ppc32 kernels. This used to match what is in prom.h, but not anymore
- * so we now define it here
- */
-struct bootx_dt_prop {
-	u32	name;
-	int	length;
-	u32	value;
-	u32	next;
-};
-
-struct bootx_dt_node {
-	u32	unused0;
-	u32	unused1;
-	u32	phandle;	/* not really available */
-	u32	unused2;
-	u32	unused3;
-	u32	unused4;
-	u32	unused5;
-	u32	full_name;
-	u32	properties;
-	u32	parent;
-	u32	child;
-	u32	sibling;
-	u32	next;
-	u32	allnext;
-};
-
-extern void bootx_init(unsigned long r4, unsigned long phys);
-
-#endif /* __KERNEL__ */
-
-#ifdef macintosh
-#pragma options align=reset
-#endif
-
-#endif
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/btext.h b/ANDROID_3.4.5/arch/powerpc/include/asm/btext.h
deleted file mode 100644
index 906f46e3..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/btext.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Definitions for using the procedures in btext.c.
- *
- * Benjamin Herrenschmidt <benh@kernel.crashing.org>
- */
-#ifndef __PPC_BTEXT_H
-#define __PPC_BTEXT_H
-#ifdef __KERNEL__
-
-extern int btext_find_display(int allow_nonstdout);
-extern void btext_update_display(unsigned long phys, int width, int height,
-				 int depth, int pitch);
-extern void btext_setup_display(int width, int height, int depth, int pitch,
-				unsigned long address);
-extern void btext_prepare_BAT(void);
-extern void btext_unmap(void);
-
-extern void btext_drawchar(char c);
-extern void btext_drawstring(const char *str);
-extern void btext_drawhex(unsigned long v);
-extern void btext_drawtext(const char *c, unsigned int len);
-
-extern void btext_clearscreen(void);
-extern void btext_flushscreen(void);
-extern void btext_flushline(void);
-
-#endif /* __KERNEL__ */
-#endif /* __PPC_BTEXT_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/bug.h b/ANDROID_3.4.5/arch/powerpc/include/asm/bug.h
deleted file mode 100644
index 3eb53d74..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/bug.h
+++ /dev/null
@@ -1,141 +0,0 @@
-#ifndef _ASM_POWERPC_BUG_H
-#define _ASM_POWERPC_BUG_H
-#ifdef __KERNEL__
-
-#include <asm/asm-compat.h>
-
-/*
- * Define an illegal instr to trap on the bug.
- * We don't use 0 because that marks the end of a function
- * in the ELF ABI.  That's "Boo Boo" in case you wonder...
- */
-#define BUG_OPCODE .long 0x00b00b00  /* For asm */
-#define BUG_ILLEGAL_INSTR "0x00b00b00" /* For BUG macro */
-
-#ifdef CONFIG_BUG
-
-#ifdef __ASSEMBLY__
-#include <asm/asm-offsets.h>
-#ifdef CONFIG_DEBUG_BUGVERBOSE
-.macro EMIT_BUG_ENTRY addr,file,line,flags
-	 .section __bug_table,"a"
-5001:	 PPC_LONG \addr, 5002f
-	 .short \line, \flags
-	 .org 5001b+BUG_ENTRY_SIZE
-	 .previous
-	 .section .rodata,"a"
-5002:	 .asciz "\file"
-	 .previous
-.endm
-#else
-.macro EMIT_BUG_ENTRY addr,file,line,flags
-	 .section __bug_table,"a"
-5001:	 PPC_LONG \addr
-	 .short \flags
-	 .org 5001b+BUG_ENTRY_SIZE
-	 .previous
-.endm
-#endif /* verbose */
-
-#else /* !__ASSEMBLY__ */
-/* _EMIT_BUG_ENTRY expects args %0,%1,%2,%3 to be FILE, LINE, flags and
-   sizeof(struct bug_entry), respectively */
-#ifdef CONFIG_DEBUG_BUGVERBOSE
-#define _EMIT_BUG_ENTRY				\
-	".section __bug_table,\"a\"\n"		\
-	"2:\t" PPC_LONG "1b, %0\n"		\
-	"\t.short %1, %2\n"			\
-	".org 2b+%3\n"				\
-	".previous\n"
-#else
-#define _EMIT_BUG_ENTRY				\
-	".section __bug_table,\"a\"\n"		\
-	"2:\t" PPC_LONG "1b\n"			\
-	"\t.short %2\n"				\
-	".org 2b+%3\n"				\
-	".previous\n"
-#endif
-
-/*
- * BUG_ON() and WARN_ON() do their best to cooperate with compile-time
- * optimisations. However depending on the complexity of the condition
- * some compiler versions may not produce optimal results.
- */
-
-#define BUG() do {						\
-	__asm__ __volatile__(					\
-		"1:	twi 31,0,0\n"				\
-		_EMIT_BUG_ENTRY					\
-		: : "i" (__FILE__), "i" (__LINE__),		\
-		    "i" (0), "i"  (sizeof(struct bug_entry)));	\
-	unreachable();						\
-} while (0)
-
-#define BUG_ON(x) do {						\
-	if (__builtin_constant_p(x)) {				\
-		if (x)						\
-			BUG();					\
-	} else {						\
-		__asm__ __volatile__(				\
-		"1:	"PPC_TLNEI"	%4,0\n"			\
-		_EMIT_BUG_ENTRY					\
-		: : "i" (__FILE__), "i" (__LINE__), "i" (0),	\
-		  "i" (sizeof(struct bug_entry)),		\
-		  "r" ((__force long)(x)));			\
-	}							\
-} while (0)
-
-#define __WARN_TAINT(taint) do {				\
-	__asm__ __volatile__(					\
-		"1:	twi 31,0,0\n"				\
-		_EMIT_BUG_ENTRY					\
-		: : "i" (__FILE__), "i" (__LINE__),		\
-		  "i" (BUGFLAG_TAINT(taint)),			\
-		  "i" (sizeof(struct bug_entry)));		\
-} while (0)
-
-#define WARN_ON(x) ({						\
-	int __ret_warn_on = !!(x);				\
-	if (__builtin_constant_p(__ret_warn_on)) {		\
-		if (__ret_warn_on)				\
-			__WARN();				\
-	} else {						\
-		__asm__ __volatile__(				\
-		"1:	"PPC_TLNEI"	%4,0\n"			\
-		_EMIT_BUG_ENTRY					\
-		: : "i" (__FILE__), "i" (__LINE__),		\
-		  "i" (BUGFLAG_TAINT(TAINT_WARN)),		\
-		  "i" (sizeof(struct bug_entry)),		\
-		  "r" (__ret_warn_on));				\
-	}							\
-	unlikely(__ret_warn_on);				\
-})
-
-#define HAVE_ARCH_BUG
-#define HAVE_ARCH_BUG_ON
-#define HAVE_ARCH_WARN_ON
-#endif /* __ASSEMBLY __ */
-#else
-#ifdef __ASSEMBLY__
-.macro EMIT_BUG_ENTRY addr,file,line,flags
-.endm
-#else /* !__ASSEMBLY__ */
-#define _EMIT_BUG_ENTRY
-#endif
-#endif /* CONFIG_BUG */
-
-#include <asm-generic/bug.h>
-
-#ifndef __ASSEMBLY__
-
-struct pt_regs;
-extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long);
-extern void bad_page_fault(struct pt_regs *, unsigned long, int);
-extern void _exception(int, struct pt_regs *, int, unsigned long);
-extern void die(const char *, struct pt_regs *, long);
-extern void print_backtrace(unsigned long *);
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_BUG_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/bugs.h b/ANDROID_3.4.5/arch/powerpc/include/asm/bugs.h
deleted file mode 100644
index 42fdb73e..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/bugs.h
+++ /dev/null
@@ -1,18 +0,0 @@
-#ifndef _ASM_POWERPC_BUGS_H
-#define _ASM_POWERPC_BUGS_H
-
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-/*
- * This file is included by 'init/main.c' to check for
- * architecture-dependent bugs.
- */
-
-static inline void check_bugs(void) { }
-
-#endif	/* _ASM_POWERPC_BUGS_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/byteorder.h b/ANDROID_3.4.5/arch/powerpc/include/asm/byteorder.h
deleted file mode 100644
index aa6cc4fa..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/byteorder.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef _ASM_POWERPC_BYTEORDER_H
-#define _ASM_POWERPC_BYTEORDER_H
-
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#include <linux/byteorder/big_endian.h>
-
-#endif /* _ASM_POWERPC_BYTEORDER_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/cache.h b/ANDROID_3.4.5/arch/powerpc/include/asm/cache.h
deleted file mode 100644
index 9e495c9a..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/cache.h
+++ /dev/null
@@ -1,65 +0,0 @@
-#ifndef _ASM_POWERPC_CACHE_H
-#define _ASM_POWERPC_CACHE_H
-
-#ifdef __KERNEL__
-
-
-/* bytes per L1 cache line */
-#if defined(CONFIG_8xx) || defined(CONFIG_403GCX)
-#define L1_CACHE_SHIFT		4
-#define MAX_COPY_PREFETCH	1
-#elif defined(CONFIG_PPC_E500MC)
-#define L1_CACHE_SHIFT		6
-#define MAX_COPY_PREFETCH	4
-#elif defined(CONFIG_PPC32)
-#define MAX_COPY_PREFETCH	4
-#if defined(CONFIG_PPC_47x)
-#define L1_CACHE_SHIFT		7
-#else
-#define L1_CACHE_SHIFT		5
-#endif
-#else /* CONFIG_PPC64 */
-#define L1_CACHE_SHIFT		7
-#endif
-
-#define	L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)
-
-#define	SMP_CACHE_BYTES		L1_CACHE_BYTES
-
-#if defined(__powerpc64__) && !defined(__ASSEMBLY__)
-struct ppc64_caches {
-	u32	dsize;			/* L1 d-cache size */
-	u32	dline_size;		/* L1 d-cache line size	*/
-	u32	log_dline_size;
-	u32	dlines_per_page;
-	u32	isize;			/* L1 i-cache size */
-	u32	iline_size;		/* L1 i-cache line size	*/
-	u32	log_iline_size;
-	u32	ilines_per_page;
-};
-
-extern struct ppc64_caches ppc64_caches;
-#endif /* __powerpc64__ && ! __ASSEMBLY__ */
-
-#if !defined(__ASSEMBLY__)
-
-#define __read_mostly __attribute__((__section__(".data..read_mostly")))
-
-#ifdef CONFIG_6xx
-extern long _get_L2CR(void);
-extern long _get_L3CR(void);
-extern void _set_L2CR(unsigned long);
-extern void _set_L3CR(unsigned long);
-#else
-#define _get_L2CR()	0L
-#define _get_L3CR()	0L
-#define _set_L2CR(val)	do { } while(0)
-#define _set_L3CR(val)	do { } while(0)
-#endif
-
-extern void cacheable_memzero(void *p, unsigned int nb);
-extern void *cacheable_memcpy(void *, const void *, unsigned int);
-
-#endif /* !__ASSEMBLY__ */
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_CACHE_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/cacheflush.h b/ANDROID_3.4.5/arch/powerpc/include/asm/cacheflush.h
deleted file mode 100644
index ab9e4025..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/cacheflush.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- *  This program is free software; you can redistribute it and/or
- *  modify it under the terms of the GNU General Public License
- *  as published by the Free Software Foundation; either version
- *  2 of the License, or (at your option) any later version.
- */
-#ifndef _ASM_POWERPC_CACHEFLUSH_H
-#define _ASM_POWERPC_CACHEFLUSH_H
-
-#ifdef __KERNEL__
-
-#include <linux/mm.h>
-#include <asm/cputable.h>
-
-/*
- * No cache flushing is required when address mappings are changed,
- * because the caches on PowerPCs are physically addressed.
- */
-#define flush_cache_all()			do { } while (0)
-#define flush_cache_mm(mm)			do { } while (0)
-#define flush_cache_dup_mm(mm)			do { } while (0)
-#define flush_cache_range(vma, start, end)	do { } while (0)
-#define flush_cache_page(vma, vmaddr, pfn)	do { } while (0)
-#define flush_icache_page(vma, page)		do { } while (0)
-#define flush_cache_vmap(start, end)		do { } while (0)
-#define flush_cache_vunmap(start, end)		do { } while (0)
-
-#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
-extern void flush_dcache_page(struct page *page);
-#define flush_dcache_mmap_lock(mapping)		do { } while (0)
-#define flush_dcache_mmap_unlock(mapping)	do { } while (0)
-
-extern void __flush_icache_range(unsigned long, unsigned long);
-static inline void flush_icache_range(unsigned long start, unsigned long stop)
-{
-	if (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
-		__flush_icache_range(start, stop);
-}
-
-extern void flush_icache_user_range(struct vm_area_struct *vma,
-				    struct page *page, unsigned long addr,
-				    int len);
-extern void __flush_dcache_icache(void *page_va);
-extern void flush_dcache_icache_page(struct page *page);
-#if defined(CONFIG_PPC32) && !defined(CONFIG_BOOKE)
-extern void __flush_dcache_icache_phys(unsigned long physaddr);
-#endif /* CONFIG_PPC32 && !CONFIG_BOOKE */
-
-extern void flush_dcache_range(unsigned long start, unsigned long stop);
-#ifdef CONFIG_PPC32
-extern void clean_dcache_range(unsigned long start, unsigned long stop);
-extern void invalidate_dcache_range(unsigned long start, unsigned long stop);
-#endif /* CONFIG_PPC32 */
-#ifdef CONFIG_PPC64
-extern void flush_inval_dcache_range(unsigned long start, unsigned long stop);
-extern void flush_dcache_phys_range(unsigned long start, unsigned long stop);
-#endif
-
-#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
-	do { \
-		memcpy(dst, src, len); \
-		flush_icache_user_range(vma, page, vaddr, len); \
-	} while (0)
-#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
-	memcpy(dst, src, len)
-
-
-
-#ifdef CONFIG_DEBUG_PAGEALLOC
-/* internal debugging function */
-void kernel_map_pages(struct page *page, int numpages, int enable);
-#endif
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_POWERPC_CACHEFLUSH_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/cell-pmu.h b/ANDROID_3.4.5/arch/powerpc/include/asm/cell-pmu.h
deleted file mode 100644
index b4b7338a..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/cell-pmu.h
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * Cell Broadband Engine Performance Monitor
- *
- * (C) Copyright IBM Corporation 2006
- *
- * Author:
- *   David Erb (djerb@us.ibm.com)
- *   Kevin Corry (kevcorry@us.ibm.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ASM_CELL_PMU_H__
-#define __ASM_CELL_PMU_H__
-
-/* The Cell PMU has four hardware performance counters, which can be
- * configured as four 32-bit counters or eight 16-bit counters.
- */
-#define NR_PHYS_CTRS 4
-#define NR_CTRS      (NR_PHYS_CTRS * 2)
-
-/* Macros for the pm_control register. */
-#define CBE_PM_16BIT_CTR(ctr)              (1 << (24 - ((ctr) & (NR_PHYS_CTRS - 1))))
-#define CBE_PM_ENABLE_PERF_MON             0x80000000
-#define CBE_PM_STOP_AT_MAX                 0x40000000
-#define CBE_PM_TRACE_MODE_GET(pm_control)  (((pm_control) >> 28) & 0x3)
-#define CBE_PM_TRACE_MODE_SET(mode)        (((mode)  & 0x3) << 28)
-#define CBE_PM_TRACE_BUF_OVFLW(bit)        (((bit) & 0x1) << 17)
-#define CBE_PM_COUNT_MODE_SET(count)       (((count) & 0x3) << 18)
-#define CBE_PM_FREEZE_ALL_CTRS             0x00100000
-#define CBE_PM_ENABLE_EXT_TRACE            0x00008000
-#define CBE_PM_SPU_ADDR_TRACE_SET(msk)     (((msk) & 0x3) << 9)
-
-/* Macros for the trace_address register. */
-#define CBE_PM_TRACE_BUF_FULL              0x00000800
-#define CBE_PM_TRACE_BUF_EMPTY             0x00000400
-#define CBE_PM_TRACE_BUF_DATA_COUNT(ta)    ((ta) & 0x3ff)
-#define CBE_PM_TRACE_BUF_MAX_COUNT         0x400
-
-/* Macros for the pm07_control registers. */
-#define CBE_PM_CTR_INPUT_MUX(pm07_control) (((pm07_control) >> 26) & 0x3f)
-#define CBE_PM_CTR_INPUT_CONTROL           0x02000000
-#define CBE_PM_CTR_POLARITY                0x01000000
-#define CBE_PM_CTR_COUNT_CYCLES            0x00800000
-#define CBE_PM_CTR_ENABLE                  0x00400000
-#define PM07_CTR_INPUT_MUX(x)              (((x) & 0x3F) << 26)
-#define PM07_CTR_INPUT_CONTROL(x)          (((x) & 1) << 25)
-#define PM07_CTR_POLARITY(x)               (((x) & 1) << 24)
-#define PM07_CTR_COUNT_CYCLES(x)           (((x) & 1) << 23)
-#define PM07_CTR_ENABLE(x)                 (((x) & 1) << 22)
-
-/* Macros for the pm_status register. */
-#define CBE_PM_CTR_OVERFLOW_INTR(ctr)      (1 << (31 - ((ctr) & 7)))
-
-enum pm_reg_name {
-	group_control,
-	debug_bus_control,
-	trace_address,
-	ext_tr_timer,
-	pm_status,
-	pm_control,
-	pm_interval,
-	pm_start_stop,
-};
-
-/* Routines for reading/writing the PMU registers. */
-extern u32  cbe_read_phys_ctr(u32 cpu, u32 phys_ctr);
-extern void cbe_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val);
-extern u32  cbe_read_ctr(u32 cpu, u32 ctr);
-extern void cbe_write_ctr(u32 cpu, u32 ctr, u32 val);
-
-extern u32  cbe_read_pm07_control(u32 cpu, u32 ctr);
-extern void cbe_write_pm07_control(u32 cpu, u32 ctr, u32 val);
-extern u32  cbe_read_pm(u32 cpu, enum pm_reg_name reg);
-extern void cbe_write_pm(u32 cpu, enum pm_reg_name reg, u32 val);
-
-extern u32  cbe_get_ctr_size(u32 cpu, u32 phys_ctr);
-extern void cbe_set_ctr_size(u32 cpu, u32 phys_ctr, u32 ctr_size);
-
-extern void cbe_enable_pm(u32 cpu);
-extern void cbe_disable_pm(u32 cpu);
-
-extern void cbe_read_trace_buffer(u32 cpu, u64 *buf);
-
-extern void cbe_enable_pm_interrupts(u32 cpu, u32 thread, u32 mask);
-extern void cbe_disable_pm_interrupts(u32 cpu);
-extern u32  cbe_get_and_clear_pm_interrupts(u32 cpu);
-extern void cbe_sync_irq(int node);
-
-#define CBE_COUNT_SUPERVISOR_MODE       0
-#define CBE_COUNT_HYPERVISOR_MODE       1
-#define CBE_COUNT_PROBLEM_MODE          2
-#define CBE_COUNT_ALL_MODES             3
-
-#endif /* __ASM_CELL_PMU_H__ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/cell-regs.h b/ANDROID_3.4.5/arch/powerpc/include/asm/cell-regs.h
deleted file mode 100644
index fdf64fd2..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/cell-regs.h
+++ /dev/null
@@ -1,326 +0,0 @@
-/*
- * cbe_regs.h
- *
- * This file is intended to hold the various register definitions for CBE
- * on-chip system devices (memory controller, IO controller, etc...)
- *
- * (C) Copyright IBM Corporation 2001,2006
- *
- * Authors: Maximino Aguilar (maguilar@us.ibm.com)
- *          David J. Erb (djerb@us.ibm.com)
- *
- * (c) 2006 Benjamin Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
- */
-
-#ifndef CBE_REGS_H
-#define CBE_REGS_H
-
-#include <asm/cell-pmu.h>
-
-/*
- *
- * Some HID register definitions
- *
- */
-
-/* CBE specific HID0 bits */
-#define HID0_CBE_THERM_WAKEUP	0x0000020000000000ul
-#define HID0_CBE_SYSERR_WAKEUP	0x0000008000000000ul
-#define HID0_CBE_THERM_INT_EN	0x0000000400000000ul
-#define HID0_CBE_SYSERR_INT_EN	0x0000000200000000ul
-
-#define MAX_CBE		2
-
-/*
- *
- * Pervasive unit register definitions
- *
- */
-
-union spe_reg {
-	u64 val;
-	u8 spe[8];
-};
-
-union ppe_spe_reg {
-	u64 val;
-	struct {
-		u32 ppe;
-		u32 spe;
-	};
-};
-
-
-struct cbe_pmd_regs {
-	/* Debug Bus Control */
-	u64	pad_0x0000;					/* 0x0000 */
-
-	u64	group_control;					/* 0x0008 */
-
-	u8	pad_0x0010_0x00a8 [0x00a8 - 0x0010];		/* 0x0010 */
-
-	u64	debug_bus_control;				/* 0x00a8 */
-
-	u8	pad_0x00b0_0x0100 [0x0100 - 0x00b0];		/* 0x00b0 */
-
-	u64	trace_aux_data;					/* 0x0100 */
-	u64	trace_buffer_0_63;				/* 0x0108 */
-	u64	trace_buffer_64_127;				/* 0x0110 */
-	u64	trace_address;					/* 0x0118 */
-	u64	ext_tr_timer;					/* 0x0120 */
-
-	u8	pad_0x0128_0x0400 [0x0400 - 0x0128];		/* 0x0128 */
-
-	/* Performance Monitor */
-	u64	pm_status;					/* 0x0400 */
-	u64	pm_control;					/* 0x0408 */
-	u64	pm_interval;					/* 0x0410 */
-	u64	pm_ctr[4];					/* 0x0418 */
-	u64	pm_start_stop;					/* 0x0438 */
-	u64	pm07_control[8];				/* 0x0440 */
-
-	u8	pad_0x0480_0x0800 [0x0800 - 0x0480];		/* 0x0480 */
-
-	/* Thermal Sensor Registers */
-	union	spe_reg	ts_ctsr1;				/* 0x0800 */
-	u64	ts_ctsr2;					/* 0x0808 */
-	union	spe_reg	ts_mtsr1;				/* 0x0810 */
-	u64	ts_mtsr2;					/* 0x0818 */
-	union	spe_reg	ts_itr1;				/* 0x0820 */
-	u64	ts_itr2;					/* 0x0828 */
-	u64	ts_gitr;					/* 0x0830 */
-	u64	ts_isr;						/* 0x0838 */
-	u64	ts_imr;						/* 0x0840 */
-	union	spe_reg	tm_cr1;					/* 0x0848 */
-	u64	tm_cr2;						/* 0x0850 */
-	u64	tm_simr;					/* 0x0858 */
-	union	ppe_spe_reg tm_tpr;				/* 0x0860 */
-	union	spe_reg	tm_str1;				/* 0x0868 */
-	u64	tm_str2;					/* 0x0870 */
-	union	ppe_spe_reg tm_tsr;				/* 0x0878 */
-
-	/* Power Management */
-	u64	pmcr;						/* 0x0880 */
-#define CBE_PMD_PAUSE_ZERO_CONTROL	0x10000
-	u64	pmsr;						/* 0x0888 */
-
-	/* Time Base Register */
-	u64	tbr;						/* 0x0890 */
-
-	u8	pad_0x0898_0x0c00 [0x0c00 - 0x0898];		/* 0x0898 */
-
-	/* Fault Isolation Registers */
-	u64	checkstop_fir;					/* 0x0c00 */
-	u64	recoverable_fir;				/* 0x0c08 */
-	u64	spec_att_mchk_fir;				/* 0x0c10 */
-	u32	fir_mode_reg;					/* 0x0c18 */
-	u8	pad_0x0c1c_0x0c20 [4];				/* 0x0c1c */
-#define CBE_PMD_FIR_MODE_M8		0x00800
-	u64	fir_enable_mask;				/* 0x0c20 */
-
-	u8	pad_0x0c28_0x0ca8 [0x0ca8 - 0x0c28];		/* 0x0c28 */
-	u64	ras_esc_0;					/* 0x0ca8 */
-	u8	pad_0x0cb0_0x1000 [0x1000 - 0x0cb0];		/* 0x0cb0 */
-};
-
-extern struct cbe_pmd_regs __iomem *cbe_get_pmd_regs(struct device_node *np);
-extern struct cbe_pmd_regs __iomem *cbe_get_cpu_pmd_regs(int cpu);
-
-/*
- * PMU shadow registers
- *
- * Many of the registers in the performance monitoring unit are write-only,
- * so we need to save a copy of what we write to those registers.
- *
- * The actual data counters are read/write. However, writing to the counters
- * only takes effect if the PMU is enabled. Otherwise the value is stored in
- * a hardware latch until the next time the PMU is enabled. So we save a copy
- * of the counter values if we need to read them back while the PMU is
- * disabled. The counter_value_in_latch field is a bitmap indicating which
- * counters currently have a value waiting to be written.
- */
-
-struct cbe_pmd_shadow_regs {
-	u32 group_control;
-	u32 debug_bus_control;
-	u32 trace_address;
-	u32 ext_tr_timer;
-	u32 pm_status;
-	u32 pm_control;
-	u32 pm_interval;
-	u32 pm_start_stop;
-	u32 pm07_control[NR_CTRS];
-
-	u32 pm_ctr[NR_PHYS_CTRS];
-	u32 counter_value_in_latch;
-};
-
-extern struct cbe_pmd_shadow_regs *cbe_get_pmd_shadow_regs(struct device_node *np);
-extern struct cbe_pmd_shadow_regs *cbe_get_cpu_pmd_shadow_regs(int cpu);
-
-/*
- *
- * IIC unit register definitions
- *
- */
-
-struct cbe_iic_pending_bits {
-	u32 data;
-	u8 flags;
-	u8 class;
-	u8 source;
-	u8 prio;
-};
-
-#define CBE_IIC_IRQ_VALID	0x80
-#define CBE_IIC_IRQ_IPI		0x40
-
-struct cbe_iic_thread_regs {
-	struct cbe_iic_pending_bits pending;
-	struct cbe_iic_pending_bits pending_destr;
-	u64 generate;
-	u64 prio;
-};
-
-struct cbe_iic_regs {
-	u8	pad_0x0000_0x0400[0x0400 - 0x0000];		/* 0x0000 */
-
-	/* IIC interrupt registers */
-	struct	cbe_iic_thread_regs thread[2];			/* 0x0400 */
-
-	u64	iic_ir;						/* 0x0440 */
-#define CBE_IIC_IR_PRIO(x)      (((x) & 0xf) << 12)
-#define CBE_IIC_IR_DEST_NODE(x) (((x) & 0xf) << 4)
-#define CBE_IIC_IR_DEST_UNIT(x) ((x) & 0xf)
-#define CBE_IIC_IR_IOC_0        0x0
-#define CBE_IIC_IR_IOC_1S       0xb
-#define CBE_IIC_IR_PT_0         0xe
-#define CBE_IIC_IR_PT_1         0xf
-
-	u64	iic_is;						/* 0x0448 */
-#define CBE_IIC_IS_PMI		0x2
-
-	u8	pad_0x0450_0x0500[0x0500 - 0x0450];		/* 0x0450 */
-
-	/* IOC FIR */
-	u64	ioc_fir_reset;					/* 0x0500 */
-	u64	ioc_fir_set;					/* 0x0508 */
-	u64	ioc_checkstop_enable;				/* 0x0510 */
-	u64	ioc_fir_error_mask;				/* 0x0518 */
-	u64	ioc_syserr_enable;				/* 0x0520 */
-	u64	ioc_fir;					/* 0x0528 */
-
-	u8	pad_0x0530_0x1000[0x1000 - 0x0530];		/* 0x0530 */
-};
-
-extern struct cbe_iic_regs __iomem *cbe_get_iic_regs(struct device_node *np);
-extern struct cbe_iic_regs __iomem *cbe_get_cpu_iic_regs(int cpu);
-
-
-struct cbe_mic_tm_regs {
-	u8	pad_0x0000_0x0040[0x0040 - 0x0000];		/* 0x0000 */
-
-	u64	mic_ctl_cnfg2;					/* 0x0040 */
-#define CBE_MIC_ENABLE_AUX_TRC		0x8000000000000000LL
-#define CBE_MIC_DISABLE_PWR_SAV_2	0x0200000000000000LL
-#define CBE_MIC_DISABLE_AUX_TRC_WRAP	0x0100000000000000LL
-#define CBE_MIC_ENABLE_AUX_TRC_INT	0x0080000000000000LL
-
-	u64	pad_0x0048;					/* 0x0048 */
-
-	u64	mic_aux_trc_base;				/* 0x0050 */
-	u64	mic_aux_trc_max_addr;				/* 0x0058 */
-	u64	mic_aux_trc_cur_addr;				/* 0x0060 */
-	u64	mic_aux_trc_grf_addr;				/* 0x0068 */
-	u64	mic_aux_trc_grf_data;				/* 0x0070 */
-
-	u64	pad_0x0078;					/* 0x0078 */
-
-	u64	mic_ctl_cnfg_0;					/* 0x0080 */
-#define CBE_MIC_DISABLE_PWR_SAV_0	0x8000000000000000LL
-
-	u64	pad_0x0088;					/* 0x0088 */
-
-	u64	slow_fast_timer_0;				/* 0x0090 */
-	u64	slow_next_timer_0;				/* 0x0098 */
-
-	u8	pad_0x00a0_0x00f8[0x00f8 - 0x00a0];		/* 0x00a0 */
-	u64    	mic_df_ecc_address_0;				/* 0x00f8 */
-
-	u8	pad_0x0100_0x01b8[0x01b8 - 0x0100];		/* 0x0100 */
-	u64    	mic_df_ecc_address_1;				/* 0x01b8 */
-
-	u64	mic_ctl_cnfg_1;					/* 0x01c0 */
-#define CBE_MIC_DISABLE_PWR_SAV_1	0x8000000000000000LL
-
-	u64	pad_0x01c8;					/* 0x01c8 */
-
-	u64	slow_fast_timer_1;				/* 0x01d0 */
-	u64	slow_next_timer_1;				/* 0x01d8 */
-
-	u8	pad_0x01e0_0x0208[0x0208 - 0x01e0];		/* 0x01e0 */
-	u64	mic_exc;					/* 0x0208 */
-#define CBE_MIC_EXC_BLOCK_SCRUB		0x0800000000000000ULL
-#define CBE_MIC_EXC_FAST_SCRUB		0x0100000000000000ULL
-
-	u64	mic_mnt_cfg;					/* 0x0210 */
-#define CBE_MIC_MNT_CFG_CHAN_0_POP	0x0002000000000000ULL
-#define CBE_MIC_MNT_CFG_CHAN_1_POP	0x0004000000000000ULL
-
-	u64	mic_df_config;					/* 0x0218 */
-#define CBE_MIC_ECC_DISABLE_0		0x4000000000000000ULL
-#define CBE_MIC_ECC_REP_SINGLE_0	0x2000000000000000ULL
-#define CBE_MIC_ECC_DISABLE_1		0x0080000000000000ULL
-#define CBE_MIC_ECC_REP_SINGLE_1	0x0040000000000000ULL
-
-	u8	pad_0x0220_0x0230[0x0230 - 0x0220];		/* 0x0220 */
-	u64	mic_fir;					/* 0x0230 */
-#define CBE_MIC_FIR_ECC_SINGLE_0_ERR	0x0200000000000000ULL
-#define CBE_MIC_FIR_ECC_MULTI_0_ERR	0x0100000000000000ULL
-#define CBE_MIC_FIR_ECC_SINGLE_1_ERR	0x0080000000000000ULL
-#define CBE_MIC_FIR_ECC_MULTI_1_ERR	0x0040000000000000ULL
-#define CBE_MIC_FIR_ECC_ERR_MASK	0xffff000000000000ULL
-#define CBE_MIC_FIR_ECC_SINGLE_0_CTE	0x0000020000000000ULL
-#define CBE_MIC_FIR_ECC_MULTI_0_CTE	0x0000010000000000ULL
-#define CBE_MIC_FIR_ECC_SINGLE_1_CTE	0x0000008000000000ULL
-#define CBE_MIC_FIR_ECC_MULTI_1_CTE	0x0000004000000000ULL
-#define CBE_MIC_FIR_ECC_CTE_MASK	0x0000ffff00000000ULL
-#define CBE_MIC_FIR_ECC_SINGLE_0_RESET	0x0000000002000000ULL
-#define CBE_MIC_FIR_ECC_MULTI_0_RESET	0x0000000001000000ULL
-#define CBE_MIC_FIR_ECC_SINGLE_1_RESET	0x0000000000800000ULL
-#define CBE_MIC_FIR_ECC_MULTI_1_RESET	0x0000000000400000ULL
-#define CBE_MIC_FIR_ECC_RESET_MASK	0x00000000ffff0000ULL
-#define CBE_MIC_FIR_ECC_SINGLE_0_SET	0x0000000000000200ULL
-#define CBE_MIC_FIR_ECC_MULTI_0_SET	0x0000000000000100ULL
-#define CBE_MIC_FIR_ECC_SINGLE_1_SET	0x0000000000000080ULL
-#define CBE_MIC_FIR_ECC_MULTI_1_SET	0x0000000000000040ULL
-#define CBE_MIC_FIR_ECC_SET_MASK	0x000000000000ffffULL
-	u64	mic_fir_debug;					/* 0x0238 */
-
-	u8	pad_0x0240_0x1000[0x1000 - 0x0240];		/* 0x0240 */
-};
-
-extern struct cbe_mic_tm_regs __iomem *cbe_get_mic_tm_regs(struct device_node *np);
-extern struct cbe_mic_tm_regs __iomem *cbe_get_cpu_mic_tm_regs(int cpu);
-
-
-/* Cell page table entries */
-#define CBE_IOPTE_PP_W		0x8000000000000000ul /* protection: write */
-#define CBE_IOPTE_PP_R		0x4000000000000000ul /* protection: read */
-#define CBE_IOPTE_M		0x2000000000000000ul /* coherency required */
-#define CBE_IOPTE_SO_R		0x1000000000000000ul /* ordering: writes */
-#define CBE_IOPTE_SO_RW		0x1800000000000000ul /* ordering: r & w */
-#define CBE_IOPTE_RPN_Mask	0x07fffffffffff000ul /* RPN */
-#define CBE_IOPTE_H		0x0000000000000800ul /* cache hint */
-#define CBE_IOPTE_IOID_Mask	0x00000000000007fful /* ioid */
-
-/* some utility functions to deal with SMT */
-extern u32 cbe_get_hw_thread_id(int cpu);
-extern u32 cbe_cpu_to_node(int cpu);
-extern u32 cbe_node_to_cpu(int node);
-
-/* Init this module early */
-extern void cbe_regs_init(void);
-
-
-#endif /* CBE_REGS_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/checksum.h b/ANDROID_3.4.5/arch/powerpc/include/asm/checksum.h
deleted file mode 100644
index ce0c2849..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/checksum.h
+++ /dev/null
@@ -1,127 +0,0 @@
-#ifndef _ASM_POWERPC_CHECKSUM_H
-#define _ASM_POWERPC_CHECKSUM_H
-#ifdef __KERNEL__
-
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-/*
- * This is a version of ip_compute_csum() optimized for IP headers,
- * which always checksum on 4 octet boundaries.  ihl is the number
- * of 32-bit words and is always >= 5.
- */
-extern __sum16 ip_fast_csum(const void *iph, unsigned int ihl);
-
-/*
- * computes the checksum of the TCP/UDP pseudo-header
- * returns a 16-bit checksum, already complemented
- */
-extern __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr,
-					unsigned short len,
-					unsigned short proto,
-					__wsum sum);
-
-/*
- * computes the checksum of a memory block at buff, length len,
- * and adds in "sum" (32-bit)
- *
- * returns a 32-bit number suitable for feeding into itself
- * or csum_tcpudp_magic
- *
- * this function must be called with even lengths, except
- * for the last fragment, which may be odd
- *
- * it's best to have buff aligned on a 32-bit boundary
- */
-extern __wsum csum_partial(const void *buff, int len, __wsum sum);
-
-/*
- * Computes the checksum of a memory block at src, length len,
- * and adds in "sum" (32-bit), while copying the block to dst.
- * If an access exception occurs on src or dst, it stores -EFAULT
- * to *src_err or *dst_err respectively (if that pointer is not
- * NULL), and, for an error on src, zeroes the rest of dst.
- *
- * Like csum_partial, this must be called with even lengths,
- * except for the last fragment.
- */
-extern __wsum csum_partial_copy_generic(const void *src, void *dst,
-					      int len, __wsum sum,
-					      int *src_err, int *dst_err);
-
-#ifdef __powerpc64__
-#define _HAVE_ARCH_COPY_AND_CSUM_FROM_USER
-extern __wsum csum_and_copy_from_user(const void __user *src, void *dst,
-				      int len, __wsum sum, int *err_ptr);
-#define HAVE_CSUM_COPY_USER
-extern __wsum csum_and_copy_to_user(const void *src, void __user *dst,
-				    int len, __wsum sum, int *err_ptr);
-#else
-/*
- * the same as csum_partial, but copies from src to dst while it
- * checksums.
- */
-#define csum_partial_copy_from_user(src, dst, len, sum, errp)   \
-        csum_partial_copy_generic((__force const void *)(src), (dst), (len), (sum), (errp), NULL)
-#endif
-
-#define csum_partial_copy_nocheck(src, dst, len, sum)   \
-        csum_partial_copy_generic((src), (dst), (len), (sum), NULL, NULL)
-
-
-/*
- * turns a 32-bit partial checksum (e.g. from csum_partial) into a
- * 1's complement 16-bit checksum.
- */
-static inline __sum16 csum_fold(__wsum sum)
-{
-	unsigned int tmp;
-
-	/* swap the two 16-bit halves of sum */
-	__asm__("rlwinm %0,%1,16,0,31" : "=r" (tmp) : "r" (sum));
-	/* if there is a carry from adding the two 16-bit halves,
-	   it will carry from the lower half into the upper half,
-	   giving us the correct sum in the upper half. */
-	return (__force __sum16)(~((__force u32)sum + tmp) >> 16);
-}
-
-/*
- * this routine is used for miscellaneous IP-like checksums, mainly
- * in icmp.c
- */
-static inline __sum16 ip_compute_csum(const void *buff, int len)
-{
-	return csum_fold(csum_partial(buff, len, 0));
-}
-
-static inline __wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr,
-                                     unsigned short len,
-                                     unsigned short proto,
-                                     __wsum sum)
-{
-#ifdef __powerpc64__
-	unsigned long s = (__force u32)sum;
-
-	s += (__force u32)saddr;
-	s += (__force u32)daddr;
-	s += proto + len;
-	s += (s >> 32);
-	return (__force __wsum) s;
-#else
-    __asm__("\n\
-	addc %0,%0,%1 \n\
-	adde %0,%0,%2 \n\
-	adde %0,%0,%3 \n\
-	addze %0,%0 \n\
-	"
-	: "=r" (sum)
-	: "r" (daddr), "r"(saddr), "r"(proto + len), "0"(sum));
-	return sum;
-#endif
-}
-#endif /* __KERNEL__ */
-#endif
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/clk_interface.h b/ANDROID_3.4.5/arch/powerpc/include/asm/clk_interface.h
deleted file mode 100644
index ab1882c1..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/clk_interface.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef __ASM_POWERPC_CLK_INTERFACE_H
-#define __ASM_POWERPC_CLK_INTERFACE_H
-
-#include <linux/clk.h>
-
-struct clk_interface {
-	struct clk*	(*clk_get)	(struct device *dev, const char *id);
-	int		(*clk_enable)	(struct clk *clk);
-	void		(*clk_disable)	(struct clk *clk);
-	unsigned long	(*clk_get_rate)	(struct clk *clk);
-	void		(*clk_put)	(struct clk *clk);
-	long		(*clk_round_rate) (struct clk *clk, unsigned long rate);
-	int 		(*clk_set_rate)	(struct clk *clk, unsigned long rate);
-	int		(*clk_set_parent) (struct clk *clk, struct clk *parent);
-	struct clk*	(*clk_get_parent) (struct clk *clk);
-};
-
-extern struct clk_interface clk_functions;
-
-#endif /* __ASM_POWERPC_CLK_INTERFACE_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/cmpxchg.h b/ANDROID_3.4.5/arch/powerpc/include/asm/cmpxchg.h
deleted file mode 100644
index e245aab7..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/cmpxchg.h
+++ /dev/null
@@ -1,309 +0,0 @@
-#ifndef _ASM_POWERPC_CMPXCHG_H_
-#define _ASM_POWERPC_CMPXCHG_H_
-
-#ifdef __KERNEL__
-#include <linux/compiler.h>
-#include <asm/synch.h>
-#include <asm/asm-compat.h>
-
-/*
- * Atomic exchange
- *
- * Changes the memory location '*ptr' to be val and returns
- * the previous value stored there.
- */
-static __always_inline unsigned long
-__xchg_u32(volatile void *p, unsigned long val)
-{
-	unsigned long prev;
-
-	__asm__ __volatile__(
-	PPC_RELEASE_BARRIER
-"1:	lwarx	%0,0,%2 \n"
-	PPC405_ERR77(0,%2)
-"	stwcx.	%3,0,%2 \n\
-	bne-	1b"
-	PPC_ACQUIRE_BARRIER
-	: "=&r" (prev), "+m" (*(volatile unsigned int *)p)
-	: "r" (p), "r" (val)
-	: "cc", "memory");
-
-	return prev;
-}
-
-/*
- * Atomic exchange
- *
- * Changes the memory location '*ptr' to be val and returns
- * the previous value stored there.
- */
-static __always_inline unsigned long
-__xchg_u32_local(volatile void *p, unsigned long val)
-{
-	unsigned long prev;
-
-	__asm__ __volatile__(
-"1:	lwarx	%0,0,%2 \n"
-	PPC405_ERR77(0,%2)
-"	stwcx.	%3,0,%2 \n\
-	bne-	1b"
-	: "=&r" (prev), "+m" (*(volatile unsigned int *)p)
-	: "r" (p), "r" (val)
-	: "cc", "memory");
-
-	return prev;
-}
-
-#ifdef CONFIG_PPC64
-static __always_inline unsigned long
-__xchg_u64(volatile void *p, unsigned long val)
-{
-	unsigned long prev;
-
-	__asm__ __volatile__(
-	PPC_RELEASE_BARRIER
-"1:	ldarx	%0,0,%2 \n"
-	PPC405_ERR77(0,%2)
-"	stdcx.	%3,0,%2 \n\
-	bne-	1b"
-	PPC_ACQUIRE_BARRIER
-	: "=&r" (prev), "+m" (*(volatile unsigned long *)p)
-	: "r" (p), "r" (val)
-	: "cc", "memory");
-
-	return prev;
-}
-
-static __always_inline unsigned long
-__xchg_u64_local(volatile void *p, unsigned long val)
-{
-	unsigned long prev;
-
-	__asm__ __volatile__(
-"1:	ldarx	%0,0,%2 \n"
-	PPC405_ERR77(0,%2)
-"	stdcx.	%3,0,%2 \n\
-	bne-	1b"
-	: "=&r" (prev), "+m" (*(volatile unsigned long *)p)
-	: "r" (p), "r" (val)
-	: "cc", "memory");
-
-	return prev;
-}
-#endif
-
-/*
- * This function doesn't exist, so you'll get a linker error
- * if something tries to do an invalid xchg().
- */
-extern void __xchg_called_with_bad_pointer(void);
-
-static __always_inline unsigned long
-__xchg(volatile void *ptr, unsigned long x, unsigned int size)
-{
-	switch (size) {
-	case 4:
-		return __xchg_u32(ptr, x);
-#ifdef CONFIG_PPC64
-	case 8:
-		return __xchg_u64(ptr, x);
-#endif
-	}
-	__xchg_called_with_bad_pointer();
-	return x;
-}
-
-static __always_inline unsigned long
-__xchg_local(volatile void *ptr, unsigned long x, unsigned int size)
-{
-	switch (size) {
-	case 4:
-		return __xchg_u32_local(ptr, x);
-#ifdef CONFIG_PPC64
-	case 8:
-		return __xchg_u64_local(ptr, x);
-#endif
-	}
-	__xchg_called_with_bad_pointer();
-	return x;
-}
-#define xchg(ptr,x)							     \
-  ({									     \
-     __typeof__(*(ptr)) _x_ = (x);					     \
-     (__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \
-  })
-
-#define xchg_local(ptr,x)						     \
-  ({									     \
-     __typeof__(*(ptr)) _x_ = (x);					     \
-     (__typeof__(*(ptr))) __xchg_local((ptr),				     \
-     		(unsigned long)_x_, sizeof(*(ptr))); 			     \
-  })
-
-/*
- * Compare and exchange - if *p == old, set it to new,
- * and return the old value of *p.
- */
-#define __HAVE_ARCH_CMPXCHG	1
-
-static __always_inline unsigned long
-__cmpxchg_u32(volatile unsigned int *p, unsigned long old, unsigned long new)
-{
-	unsigned int prev;
-
-	__asm__ __volatile__ (
-	PPC_RELEASE_BARRIER
-"1:	lwarx	%0,0,%2		# __cmpxchg_u32\n\
-	cmpw	0,%0,%3\n\
-	bne-	2f\n"
-	PPC405_ERR77(0,%2)
-"	stwcx.	%4,0,%2\n\
-	bne-	1b"
-	PPC_ACQUIRE_BARRIER
-	"\n\
-2:"
-	: "=&r" (prev), "+m" (*p)
-	: "r" (p), "r" (old), "r" (new)
-	: "cc", "memory");
-
-	return prev;
-}
-
-static __always_inline unsigned long
-__cmpxchg_u32_local(volatile unsigned int *p, unsigned long old,
-			unsigned long new)
-{
-	unsigned int prev;
-
-	__asm__ __volatile__ (
-"1:	lwarx	%0,0,%2		# __cmpxchg_u32\n\
-	cmpw	0,%0,%3\n\
-	bne-	2f\n"
-	PPC405_ERR77(0,%2)
-"	stwcx.	%4,0,%2\n\
-	bne-	1b"
-	"\n\
-2:"
-	: "=&r" (prev), "+m" (*p)
-	: "r" (p), "r" (old), "r" (new)
-	: "cc", "memory");
-
-	return prev;
-}
-
-#ifdef CONFIG_PPC64
-static __always_inline unsigned long
-__cmpxchg_u64(volatile unsigned long *p, unsigned long old, unsigned long new)
-{
-	unsigned long prev;
-
-	__asm__ __volatile__ (
-	PPC_RELEASE_BARRIER
-"1:	ldarx	%0,0,%2		# __cmpxchg_u64\n\
-	cmpd	0,%0,%3\n\
-	bne-	2f\n\
-	stdcx.	%4,0,%2\n\
-	bne-	1b"
-	PPC_ACQUIRE_BARRIER
-	"\n\
-2:"
-	: "=&r" (prev), "+m" (*p)
-	: "r" (p), "r" (old), "r" (new)
-	: "cc", "memory");
-
-	return prev;
-}
-
-static __always_inline unsigned long
-__cmpxchg_u64_local(volatile unsigned long *p, unsigned long old,
-			unsigned long new)
-{
-	unsigned long prev;
-
-	__asm__ __volatile__ (
-"1:	ldarx	%0,0,%2		# __cmpxchg_u64\n\
-	cmpd	0,%0,%3\n\
-	bne-	2f\n\
-	stdcx.	%4,0,%2\n\
-	bne-	1b"
-	"\n\
-2:"
-	: "=&r" (prev), "+m" (*p)
-	: "r" (p), "r" (old), "r" (new)
-	: "cc", "memory");
-
-	return prev;
-}
-#endif
-
-/* This function doesn't exist, so you'll get a linker error
-   if something tries to do an invalid cmpxchg().  */
-extern void __cmpxchg_called_with_bad_pointer(void);
-
-static __always_inline unsigned long
-__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new,
-	  unsigned int size)
-{
-	switch (size) {
-	case 4:
-		return __cmpxchg_u32(ptr, old, new);
-#ifdef CONFIG_PPC64
-	case 8:
-		return __cmpxchg_u64(ptr, old, new);
-#endif
-	}
-	__cmpxchg_called_with_bad_pointer();
-	return old;
-}
-
-static __always_inline unsigned long
-__cmpxchg_local(volatile void *ptr, unsigned long old, unsigned long new,
-	  unsigned int size)
-{
-	switch (size) {
-	case 4:
-		return __cmpxchg_u32_local(ptr, old, new);
-#ifdef CONFIG_PPC64
-	case 8:
-		return __cmpxchg_u64_local(ptr, old, new);
-#endif
-	}
-	__cmpxchg_called_with_bad_pointer();
-	return old;
-}
-
-#define cmpxchg(ptr, o, n)						 \
-  ({									 \
-     __typeof__(*(ptr)) _o_ = (o);					 \
-     __typeof__(*(ptr)) _n_ = (n);					 \
-     (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,		 \
-				    (unsigned long)_n_, sizeof(*(ptr))); \
-  })
-
-
-#define cmpxchg_local(ptr, o, n)					 \
-  ({									 \
-     __typeof__(*(ptr)) _o_ = (o);					 \
-     __typeof__(*(ptr)) _n_ = (n);					 \
-     (__typeof__(*(ptr))) __cmpxchg_local((ptr), (unsigned long)_o_,	 \
-				    (unsigned long)_n_, sizeof(*(ptr))); \
-  })
-
-#ifdef CONFIG_PPC64
-#define cmpxchg64(ptr, o, n)						\
-  ({									\
-	BUILD_BUG_ON(sizeof(*(ptr)) != 8);				\
-	cmpxchg((ptr), (o), (n));					\
-  })
-#define cmpxchg64_local(ptr, o, n)					\
-  ({									\
-	BUILD_BUG_ON(sizeof(*(ptr)) != 8);				\
-	cmpxchg_local((ptr), (o), (n));					\
-  })
-#else
-#include <asm-generic/cmpxchg-local.h>
-#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
-#endif
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_CMPXCHG_H_ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/code-patching.h b/ANDROID_3.4.5/arch/powerpc/include/asm/code-patching.h
deleted file mode 100644
index 37c32aba..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/code-patching.h
+++ /dev/null
@@ -1,52 +0,0 @@
-#ifndef _ASM_POWERPC_CODE_PATCHING_H
-#define _ASM_POWERPC_CODE_PATCHING_H
-
-/*
- * Copyright 2008, Michael Ellerman, IBM Corporation.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <asm/types.h>
-#include <asm/ppc-opcode.h>
-
-/* Flags for create_branch:
- * "b"   == create_branch(addr, target, 0);
- * "ba"  == create_branch(addr, target, BRANCH_ABSOLUTE);
- * "bl"  == create_branch(addr, target, BRANCH_SET_LINK);
- * "bla" == create_branch(addr, target, BRANCH_ABSOLUTE | BRANCH_SET_LINK);
- */
-#define BRANCH_SET_LINK	0x1
-#define BRANCH_ABSOLUTE	0x2
-
-unsigned int create_branch(const unsigned int *addr,
-			   unsigned long target, int flags);
-unsigned int create_cond_branch(const unsigned int *addr,
-				unsigned long target, int flags);
-void patch_branch(unsigned int *addr, unsigned long target, int flags);
-void patch_instruction(unsigned int *addr, unsigned int instr);
-
-int instr_is_relative_branch(unsigned int instr);
-int instr_is_branch_to_addr(const unsigned int *instr, unsigned long addr);
-unsigned long branch_target(const unsigned int *instr);
-unsigned int translate_branch(const unsigned int *dest,
-			      const unsigned int *src);
-
-static inline unsigned long ppc_function_entry(void *func)
-{
-#ifdef CONFIG_PPC64
-	/*
-	 * On PPC64 the function pointer actually points to the function's
-	 * descriptor. The first entry in the descriptor is the address
-	 * of the function text.
-	 */
-	return ((func_descr_t *)func)->entry;
-#else
-	return (unsigned long)func;
-#endif
-}
-
-#endif /* _ASM_POWERPC_CODE_PATCHING_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/compat.h b/ANDROID_3.4.5/arch/powerpc/include/asm/compat.h
deleted file mode 100644
index 88e602f6..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/compat.h
+++ /dev/null
@@ -1,221 +0,0 @@
-#ifndef _ASM_POWERPC_COMPAT_H
-#define _ASM_POWERPC_COMPAT_H
-#ifdef __KERNEL__
-/*
- * Architecture specific compatibility types
- */
-#include <linux/types.h>
-#include <linux/sched.h>
-
-#define COMPAT_USER_HZ		100
-#define COMPAT_UTS_MACHINE	"ppc\0\0"
-
-typedef u32		compat_size_t;
-typedef s32		compat_ssize_t;
-typedef s32		compat_time_t;
-typedef s32		compat_clock_t;
-typedef s32		compat_pid_t;
-typedef u32		__compat_uid_t;
-typedef u32		__compat_gid_t;
-typedef u32		__compat_uid32_t;
-typedef u32		__compat_gid32_t;
-typedef u32		compat_mode_t;
-typedef u32		compat_ino_t;
-typedef u32		compat_dev_t;
-typedef s32		compat_off_t;
-typedef s64		compat_loff_t;
-typedef s16		compat_nlink_t;
-typedef u16		compat_ipc_pid_t;
-typedef s32		compat_daddr_t;
-typedef u32		compat_caddr_t;
-typedef __kernel_fsid_t	compat_fsid_t;
-typedef s32		compat_key_t;
-typedef s32		compat_timer_t;
-
-typedef s32		compat_int_t;
-typedef s32		compat_long_t;
-typedef s64		compat_s64;
-typedef u32		compat_uint_t;
-typedef u32		compat_ulong_t;
-typedef u64		compat_u64;
-
-struct compat_timespec {
-	compat_time_t	tv_sec;
-	s32		tv_nsec;
-};
-
-struct compat_timeval {
-	compat_time_t	tv_sec;
-	s32		tv_usec;
-};
-
-struct compat_stat {
-	compat_dev_t	st_dev;
-	compat_ino_t	st_ino;
-	compat_mode_t	st_mode;
-	compat_nlink_t	st_nlink;
-	__compat_uid32_t	st_uid;
-	__compat_gid32_t	st_gid;
-	compat_dev_t	st_rdev;
-	compat_off_t	st_size;
-	compat_off_t	st_blksize;
-	compat_off_t	st_blocks;
-	compat_time_t	st_atime;
-	u32		st_atime_nsec;
-	compat_time_t	st_mtime;
-	u32		st_mtime_nsec;
-	compat_time_t	st_ctime;
-	u32		st_ctime_nsec;
-	u32		__unused4[2];
-};
-
-struct compat_flock {
-	short		l_type;
-	short		l_whence;
-	compat_off_t	l_start;
-	compat_off_t	l_len;
-	compat_pid_t	l_pid;
-};
-
-#define F_GETLK64	12	/*  using 'struct flock64' */
-#define F_SETLK64	13
-#define F_SETLKW64	14
-
-struct compat_flock64 {
-	short		l_type;
-	short		l_whence;
-	compat_loff_t	l_start;
-	compat_loff_t	l_len;
-	compat_pid_t	l_pid;
-};
-
-struct compat_statfs {
-	int		f_type;
-	int		f_bsize;
-	int		f_blocks;
-	int		f_bfree;
-	int		f_bavail;
-	int		f_files;
-	int		f_ffree;
-	compat_fsid_t	f_fsid;
-	int		f_namelen;	/* SunOS ignores this field. */
-	int		f_frsize;
-	int		f_flags;
-	int		f_spare[4];
-};
-
-#define COMPAT_RLIM_OLD_INFINITY	0x7fffffff
-#define COMPAT_RLIM_INFINITY		0xffffffff
-
-typedef u32		compat_old_sigset_t;
-
-#define _COMPAT_NSIG		64
-#define _COMPAT_NSIG_BPW	32
-
-typedef u32		compat_sigset_word;
-
-#define COMPAT_OFF_T_MAX	0x7fffffff
-#define COMPAT_LOFF_T_MAX	0x7fffffffffffffffL
-
-/*
- * A pointer passed in from user mode. This should not
- * be used for syscall parameters, just declare them
- * as pointers because the syscall entry code will have
- * appropriately converted them already.
- */
-typedef	u32		compat_uptr_t;
-
-static inline void __user *compat_ptr(compat_uptr_t uptr)
-{
-	return (void __user *)(unsigned long)uptr;
-}
-
-static inline compat_uptr_t ptr_to_compat(void __user *uptr)
-{
-	return (u32)(unsigned long)uptr;
-}
-
-static inline void __user *arch_compat_alloc_user_space(long len)
-{
-	struct pt_regs *regs = current->thread.regs;
-	unsigned long usp = regs->gpr[1];
-
-	/*
-	 * We can't access below the stack pointer in the 32bit ABI and
-	 * can access 288 bytes in the 64bit ABI
-	 */
-	if (!is_32bit_task())
-		usp -= 288;
-
-	return (void __user *) (usp - len);
-}
-
-/*
- * ipc64_perm is actually 32/64bit clean but since the compat layer refers to
- * it we may as well define it.
- */
-struct compat_ipc64_perm {
-	compat_key_t key;
-	__compat_uid_t uid;
-	__compat_gid_t gid;
-	__compat_uid_t cuid;
-	__compat_gid_t cgid;
-	compat_mode_t mode;
-	unsigned int seq;
-	unsigned int __pad2;
-	unsigned long __unused1;	/* yes they really are 64bit pads */
-	unsigned long __unused2;
-};
-
-struct compat_semid64_ds {
-	struct compat_ipc64_perm sem_perm;
-	unsigned int __unused1;
-	compat_time_t sem_otime;
-	unsigned int __unused2;
-	compat_time_t sem_ctime;
-	compat_ulong_t sem_nsems;
-	compat_ulong_t __unused3;
-	compat_ulong_t __unused4;
-};
-
-struct compat_msqid64_ds {
-	struct compat_ipc64_perm msg_perm;
-	unsigned int __unused1;
-	compat_time_t msg_stime;
-	unsigned int __unused2;
-	compat_time_t msg_rtime;
-	unsigned int __unused3;
-	compat_time_t msg_ctime;
-	compat_ulong_t msg_cbytes;
-	compat_ulong_t msg_qnum;
-	compat_ulong_t msg_qbytes;
-	compat_pid_t msg_lspid;
-	compat_pid_t msg_lrpid;
-	compat_ulong_t __unused4;
-	compat_ulong_t __unused5;
-};
-
-struct compat_shmid64_ds {
-	struct compat_ipc64_perm shm_perm;
-	unsigned int __unused1;
-	compat_time_t shm_atime;
-	unsigned int __unused2;
-	compat_time_t shm_dtime;
-	unsigned int __unused3;
-	compat_time_t shm_ctime;
-	unsigned int __unused4;
-	compat_size_t shm_segsz;
-	compat_pid_t shm_cpid;
-	compat_pid_t shm_lpid;
-	compat_ulong_t shm_nattch;
-	compat_ulong_t __unused5;
-	compat_ulong_t __unused6;
-};
-
-static inline int is_compat_task(void)
-{
-	return is_32bit_task();
-}
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_COMPAT_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/cpm.h b/ANDROID_3.4.5/arch/powerpc/include/asm/cpm.h
deleted file mode 100644
index 4398a6cd..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/cpm.h
+++ /dev/null
@@ -1,212 +0,0 @@
-#ifndef __CPM_H
-#define __CPM_H
-
-#include <linux/compiler.h>
-#include <linux/types.h>
-#include <linux/errno.h>
-#include <linux/of.h>
-
-/*
- * SPI Parameter RAM common to QE and CPM.
- */
-struct spi_pram {
-	__be16	rbase;	/* Rx Buffer descriptor base address */
-	__be16	tbase;	/* Tx Buffer descriptor base address */
-	u8	rfcr;	/* Rx function code */
-	u8	tfcr;	/* Tx function code */
-	__be16	mrblr;	/* Max receive buffer length */
-	__be32	rstate;	/* Internal */
-	__be32	rdp;	/* Internal */
-	__be16	rbptr;	/* Internal */
-	__be16	rbc;	/* Internal */
-	__be32	rxtmp;	/* Internal */
-	__be32	tstate;	/* Internal */
-	__be32	tdp;	/* Internal */
-	__be16	tbptr;	/* Internal */
-	__be16	tbc;	/* Internal */
-	__be32	txtmp;	/* Internal */
-	__be32	res;	/* Tx temp. */
-	__be16  rpbase;	/* Relocation pointer (CPM1 only) */
-	__be16	res1;	/* Reserved */
-};
-
-/*
- * USB Controller pram common to QE and CPM.
- */
-struct usb_ctlr {
-	u8	usb_usmod;
-	u8	usb_usadr;
-	u8	usb_uscom;
-	u8	res1[1];
-	__be16	usb_usep[4];
-	u8	res2[4];
-	__be16	usb_usber;
-	u8	res3[2];
-	__be16	usb_usbmr;
-	u8	res4[1];
-	u8	usb_usbs;
-	/* Fields down below are QE-only */
-	__be16	usb_ussft;
-	u8	res5[2];
-	__be16	usb_usfrn;
-	u8	res6[0x22];
-} __attribute__ ((packed));
-
-/*
- * Function code bits, usually generic to devices.
- */
-#ifdef CONFIG_CPM1
-#define CPMFCR_GBL	((u_char)0x00)	/* Flag doesn't exist in CPM1 */
-#define CPMFCR_TC2	((u_char)0x00)	/* Flag doesn't exist in CPM1 */
-#define CPMFCR_DTB	((u_char)0x00)	/* Flag doesn't exist in CPM1 */
-#define CPMFCR_BDB	((u_char)0x00)	/* Flag doesn't exist in CPM1 */
-#else
-#define CPMFCR_GBL	((u_char)0x20)	/* Set memory snooping */
-#define CPMFCR_TC2	((u_char)0x04)	/* Transfer code 2 value */
-#define CPMFCR_DTB	((u_char)0x02)	/* Use local bus for data when set */
-#define CPMFCR_BDB	((u_char)0x01)	/* Use local bus for BD when set */
-#endif
-#define CPMFCR_EB	((u_char)0x10)	/* Set big endian byte order */
-
-/* Opcodes common to CPM1 and CPM2
-*/
-#define CPM_CR_INIT_TRX		((ushort)0x0000)
-#define CPM_CR_INIT_RX		((ushort)0x0001)
-#define CPM_CR_INIT_TX		((ushort)0x0002)
-#define CPM_CR_HUNT_MODE	((ushort)0x0003)
-#define CPM_CR_STOP_TX		((ushort)0x0004)
-#define CPM_CR_GRA_STOP_TX	((ushort)0x0005)
-#define CPM_CR_RESTART_TX	((ushort)0x0006)
-#define CPM_CR_CLOSE_RX_BD	((ushort)0x0007)
-#define CPM_CR_SET_GADDR	((ushort)0x0008)
-#define CPM_CR_SET_TIMER	((ushort)0x0008)
-#define CPM_CR_STOP_IDMA	((ushort)0x000b)
-
-/* Buffer descriptors used by many of the CPM protocols. */
-typedef struct cpm_buf_desc {
-	ushort	cbd_sc;		/* Status and Control */
-	ushort	cbd_datlen;	/* Data length in buffer */
-	uint	cbd_bufaddr;	/* Buffer address in host memory */
-} cbd_t;
-
-/* Buffer descriptor control/status used by serial
- */
-
-#define BD_SC_EMPTY	(0x8000)	/* Receive is empty */
-#define BD_SC_READY	(0x8000)	/* Transmit is ready */
-#define BD_SC_WRAP	(0x2000)	/* Last buffer descriptor */
-#define BD_SC_INTRPT	(0x1000)	/* Interrupt on change */
-#define BD_SC_LAST	(0x0800)	/* Last buffer in frame */
-#define BD_SC_TC	(0x0400)	/* Transmit CRC */
-#define BD_SC_CM	(0x0200)	/* Continuous mode */
-#define BD_SC_ID	(0x0100)	/* Rec'd too many idles */
-#define BD_SC_P		(0x0100)	/* xmt preamble */
-#define BD_SC_BR	(0x0020)	/* Break received */
-#define BD_SC_FR	(0x0010)	/* Framing error */
-#define BD_SC_PR	(0x0008)	/* Parity error */
-#define BD_SC_NAK	(0x0004)	/* NAK - did not respond */
-#define BD_SC_OV	(0x0002)	/* Overrun */
-#define BD_SC_UN	(0x0002)	/* Underrun */
-#define BD_SC_CD	(0x0001)	/* */
-#define BD_SC_CL	(0x0001)	/* Collision */
-
-/* Buffer descriptor control/status used by Ethernet receive.
- * Common to SCC and FCC.
- */
-#define BD_ENET_RX_EMPTY	(0x8000)
-#define BD_ENET_RX_WRAP		(0x2000)
-#define BD_ENET_RX_INTR		(0x1000)
-#define BD_ENET_RX_LAST		(0x0800)
-#define BD_ENET_RX_FIRST	(0x0400)
-#define BD_ENET_RX_MISS		(0x0100)
-#define BD_ENET_RX_BC		(0x0080)	/* FCC Only */
-#define BD_ENET_RX_MC		(0x0040)	/* FCC Only */
-#define BD_ENET_RX_LG		(0x0020)
-#define BD_ENET_RX_NO		(0x0010)
-#define BD_ENET_RX_SH		(0x0008)
-#define BD_ENET_RX_CR		(0x0004)
-#define BD_ENET_RX_OV		(0x0002)
-#define BD_ENET_RX_CL		(0x0001)
-#define BD_ENET_RX_STATS	(0x01ff)	/* All status bits */
-
-/* Buffer descriptor control/status used by Ethernet transmit.
- * Common to SCC and FCC.
- */
-#define BD_ENET_TX_READY	(0x8000)
-#define BD_ENET_TX_PAD		(0x4000)
-#define BD_ENET_TX_WRAP		(0x2000)
-#define BD_ENET_TX_INTR		(0x1000)
-#define BD_ENET_TX_LAST		(0x0800)
-#define BD_ENET_TX_TC		(0x0400)
-#define BD_ENET_TX_DEF		(0x0200)
-#define BD_ENET_TX_HB		(0x0100)
-#define BD_ENET_TX_LC		(0x0080)
-#define BD_ENET_TX_RL		(0x0040)
-#define BD_ENET_TX_RCMASK	(0x003c)
-#define BD_ENET_TX_UN		(0x0002)
-#define BD_ENET_TX_CSL		(0x0001)
-#define BD_ENET_TX_STATS	(0x03ff)	/* All status bits */
-
-/* Buffer descriptor control/status used by Transparent mode SCC.
- */
-#define BD_SCC_TX_LAST		(0x0800)
-
-/* Buffer descriptor control/status used by I2C.
- */
-#define BD_I2C_START		(0x0400)
-
-int cpm_muram_init(void);
-
-#if defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE)
-unsigned long cpm_muram_alloc(unsigned long size, unsigned long align);
-int cpm_muram_free(unsigned long offset);
-unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long size);
-void __iomem *cpm_muram_addr(unsigned long offset);
-unsigned long cpm_muram_offset(void __iomem *addr);
-dma_addr_t cpm_muram_dma(void __iomem *addr);
-#else
-static inline unsigned long cpm_muram_alloc(unsigned long size,
-					    unsigned long align)
-{
-	return -ENOSYS;
-}
-
-static inline int cpm_muram_free(unsigned long offset)
-{
-	return -ENOSYS;
-}
-
-static inline unsigned long cpm_muram_alloc_fixed(unsigned long offset,
-						  unsigned long size)
-{
-	return -ENOSYS;
-}
-
-static inline void __iomem *cpm_muram_addr(unsigned long offset)
-{
-	return NULL;
-}
-
-static inline unsigned long cpm_muram_offset(void __iomem *addr)
-{
-	return -ENOSYS;
-}
-
-static inline dma_addr_t cpm_muram_dma(void __iomem *addr)
-{
-	return 0;
-}
-#endif /* defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE) */
-
-#ifdef CONFIG_CPM
-int cpm_command(u32 command, u8 opcode);
-#else
-static inline int cpm_command(u32 command, u8 opcode)
-{
-	return -ENOSYS;
-}
-#endif /* CONFIG_CPM */
-
-int cpm2_gpiochip_add32(struct device_node *np);
-
-#endif
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/cpm1.h b/ANDROID_3.4.5/arch/powerpc/include/asm/cpm1.h
deleted file mode 100644
index 8ee4211c..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/cpm1.h
+++ /dev/null
@@ -1,606 +0,0 @@
-/*
- * MPC8xx Communication Processor Module.
- * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
- *
- * This file contains structures and information for the communication
- * processor channels.  Some CPM control and status is available
- * through the MPC8xx internal memory map.  See immap.h for details.
- * This file only contains what I need for the moment, not the total
- * CPM capabilities.  I (or someone else) will add definitions as they
- * are needed.  -- Dan
- *
- * On the MBX board, EPPC-Bug loads CPM microcode into the first 512
- * bytes of the DP RAM and relocates the I2C parameter area to the
- * IDMA1 space.  The remaining DP RAM is available for buffer descriptors
- * or other use.
- */
-#ifndef __CPM1__
-#define __CPM1__
-
-#include <linux/init.h>
-#include <asm/8xx_immap.h>
-#include <asm/ptrace.h>
-#include <asm/cpm.h>
-
-/* CPM Command register.
-*/
-#define CPM_CR_RST	((ushort)0x8000)
-#define CPM_CR_OPCODE	((ushort)0x0f00)
-#define CPM_CR_CHAN	((ushort)0x00f0)
-#define CPM_CR_FLG	((ushort)0x0001)
-
-/* Channel numbers.
-*/
-#define CPM_CR_CH_SCC1		((ushort)0x0000)
-#define CPM_CR_CH_I2C		((ushort)0x0001)	/* I2C and IDMA1 */
-#define CPM_CR_CH_SCC2		((ushort)0x0004)
-#define CPM_CR_CH_SPI		((ushort)0x0005)	/* SPI / IDMA2 / Timers */
-#define CPM_CR_CH_TIMER		CPM_CR_CH_SPI
-#define CPM_CR_CH_SCC3		((ushort)0x0008)
-#define CPM_CR_CH_SMC1		((ushort)0x0009)	/* SMC1 / DSP1 */
-#define CPM_CR_CH_SCC4		((ushort)0x000c)
-#define CPM_CR_CH_SMC2		((ushort)0x000d)	/* SMC2 / DSP2 */
-
-#define mk_cr_cmd(CH, CMD)	((CMD << 8) | (CH << 4))
-
-/* Export the base address of the communication processor registers
- * and dual port ram.
- */
-extern cpm8xx_t __iomem *cpmp; /* Pointer to comm processor */
-
-#define cpm_dpalloc cpm_muram_alloc
-#define cpm_dpfree cpm_muram_free
-#define cpm_dpram_addr cpm_muram_addr
-#define cpm_dpram_phys cpm_muram_dma
-
-extern void cpm_setbrg(uint brg, uint rate);
-
-extern void __init cpm_load_patch(cpm8xx_t *cp);
-
-extern void cpm_reset(void);
-
-/* Parameter RAM offsets.
-*/
-#define PROFF_SCC1	((uint)0x0000)
-#define PROFF_IIC	((uint)0x0080)
-#define PROFF_SCC2	((uint)0x0100)
-#define PROFF_SPI	((uint)0x0180)
-#define PROFF_SCC3	((uint)0x0200)
-#define PROFF_SMC1	((uint)0x0280)
-#define PROFF_SCC4	((uint)0x0300)
-#define PROFF_SMC2	((uint)0x0380)
-
-/* Define enough so I can at least use the serial port as a UART.
- * The MBX uses SMC1 as the host serial port.
- */
-typedef struct smc_uart {
-	ushort	smc_rbase;	/* Rx Buffer descriptor base address */
-	ushort	smc_tbase;	/* Tx Buffer descriptor base address */
-	u_char	smc_rfcr;	/* Rx function code */
-	u_char	smc_tfcr;	/* Tx function code */
-	ushort	smc_mrblr;	/* Max receive buffer length */
-	uint	smc_rstate;	/* Internal */
-	uint	smc_idp;	/* Internal */
-	ushort	smc_rbptr;	/* Internal */
-	ushort	smc_ibc;	/* Internal */
-	uint	smc_rxtmp;	/* Internal */
-	uint	smc_tstate;	/* Internal */
-	uint	smc_tdp;	/* Internal */
-	ushort	smc_tbptr;	/* Internal */
-	ushort	smc_tbc;	/* Internal */
-	uint	smc_txtmp;	/* Internal */
-	ushort	smc_maxidl;	/* Maximum idle characters */
-	ushort	smc_tmpidl;	/* Temporary idle counter */
-	ushort	smc_brklen;	/* Last received break length */
-	ushort	smc_brkec;	/* rcv'd break condition counter */
-	ushort	smc_brkcr;	/* xmt break count register */
-	ushort	smc_rmask;	/* Temporary bit mask */
-	char	res1[8];	/* Reserved */
-	ushort	smc_rpbase;	/* Relocation pointer */
-} smc_uart_t;
-
-/* Function code bits.
-*/
-#define SMC_EB	((u_char)0x10)	/* Set big endian byte order */
-
-/* SMC uart mode register.
-*/
-#define	SMCMR_REN	((ushort)0x0001)
-#define SMCMR_TEN	((ushort)0x0002)
-#define SMCMR_DM	((ushort)0x000c)
-#define SMCMR_SM_GCI	((ushort)0x0000)
-#define SMCMR_SM_UART	((ushort)0x0020)
-#define SMCMR_SM_TRANS	((ushort)0x0030)
-#define SMCMR_SM_MASK	((ushort)0x0030)
-#define SMCMR_PM_EVEN	((ushort)0x0100)	/* Even parity, else odd */
-#define SMCMR_REVD	SMCMR_PM_EVEN
-#define SMCMR_PEN	((ushort)0x0200)	/* Parity enable */
-#define SMCMR_BS	SMCMR_PEN
-#define SMCMR_SL	((ushort)0x0400)	/* Two stops, else one */
-#define SMCR_CLEN_MASK	((ushort)0x7800)	/* Character length */
-#define smcr_mk_clen(C)	(((C) << 11) & SMCR_CLEN_MASK)
-
-/* SMC2 as Centronics parallel printer.  It is half duplex, in that
- * it can only receive or transmit.  The parameter ram values for
- * each direction are either unique or properly overlap, so we can
- * include them in one structure.
- */
-typedef struct smc_centronics {
-	ushort	scent_rbase;
-	ushort	scent_tbase;
-	u_char	scent_cfcr;
-	u_char	scent_smask;
-	ushort	scent_mrblr;
-	uint	scent_rstate;
-	uint	scent_r_ptr;
-	ushort	scent_rbptr;
-	ushort	scent_r_cnt;
-	uint	scent_rtemp;
-	uint	scent_tstate;
-	uint	scent_t_ptr;
-	ushort	scent_tbptr;
-	ushort	scent_t_cnt;
-	uint	scent_ttemp;
-	ushort	scent_max_sl;
-	ushort	scent_sl_cnt;
-	ushort	scent_character1;
-	ushort	scent_character2;
-	ushort	scent_character3;
-	ushort	scent_character4;
-	ushort	scent_character5;
-	ushort	scent_character6;
-	ushort	scent_character7;
-	ushort	scent_character8;
-	ushort	scent_rccm;
-	ushort	scent_rccr;
-} smc_cent_t;
-
-/* Centronics Status Mask Register.
-*/
-#define SMC_CENT_F	((u_char)0x08)
-#define SMC_CENT_PE	((u_char)0x04)
-#define SMC_CENT_S	((u_char)0x02)
-
-/* SMC Event and Mask register.
-*/
-#define	SMCM_BRKE	((unsigned char)0x40)	/* When in UART Mode */
-#define	SMCM_BRK	((unsigned char)0x10)	/* When in UART Mode */
-#define	SMCM_TXE	((unsigned char)0x10)	/* When in Transparent Mode */
-#define	SMCM_BSY	((unsigned char)0x04)
-#define	SMCM_TX		((unsigned char)0x02)
-#define	SMCM_RX		((unsigned char)0x01)
-
-/* Baud rate generators.
-*/
-#define CPM_BRG_RST		((uint)0x00020000)
-#define CPM_BRG_EN		((uint)0x00010000)
-#define CPM_BRG_EXTC_INT	((uint)0x00000000)
-#define CPM_BRG_EXTC_CLK2	((uint)0x00004000)
-#define CPM_BRG_EXTC_CLK6	((uint)0x00008000)
-#define CPM_BRG_ATB		((uint)0x00002000)
-#define CPM_BRG_CD_MASK		((uint)0x00001ffe)
-#define CPM_BRG_DIV16		((uint)0x00000001)
-
-/* SI Clock Route Register
-*/
-#define SICR_RCLK_SCC1_BRG1	((uint)0x00000000)
-#define SICR_TCLK_SCC1_BRG1	((uint)0x00000000)
-#define SICR_RCLK_SCC2_BRG2	((uint)0x00000800)
-#define SICR_TCLK_SCC2_BRG2	((uint)0x00000100)
-#define SICR_RCLK_SCC3_BRG3	((uint)0x00100000)
-#define SICR_TCLK_SCC3_BRG3	((uint)0x00020000)
-#define SICR_RCLK_SCC4_BRG4	((uint)0x18000000)
-#define SICR_TCLK_SCC4_BRG4	((uint)0x03000000)
-
-/* SCCs.
-*/
-#define SCC_GSMRH_IRP		((uint)0x00040000)
-#define SCC_GSMRH_GDE		((uint)0x00010000)
-#define SCC_GSMRH_TCRC_CCITT	((uint)0x00008000)
-#define SCC_GSMRH_TCRC_BISYNC	((uint)0x00004000)
-#define SCC_GSMRH_TCRC_HDLC	((uint)0x00000000)
-#define SCC_GSMRH_REVD		((uint)0x00002000)
-#define SCC_GSMRH_TRX		((uint)0x00001000)
-#define SCC_GSMRH_TTX		((uint)0x00000800)
-#define SCC_GSMRH_CDP		((uint)0x00000400)
-#define SCC_GSMRH_CTSP		((uint)0x00000200)
-#define SCC_GSMRH_CDS		((uint)0x00000100)
-#define SCC_GSMRH_CTSS		((uint)0x00000080)
-#define SCC_GSMRH_TFL		((uint)0x00000040)
-#define SCC_GSMRH_RFW		((uint)0x00000020)
-#define SCC_GSMRH_TXSY		((uint)0x00000010)
-#define SCC_GSMRH_SYNL16	((uint)0x0000000c)
-#define SCC_GSMRH_SYNL8		((uint)0x00000008)
-#define SCC_GSMRH_SYNL4		((uint)0x00000004)
-#define SCC_GSMRH_RTSM		((uint)0x00000002)
-#define SCC_GSMRH_RSYN		((uint)0x00000001)
-
-#define SCC_GSMRL_SIR		((uint)0x80000000)	/* SCC2 only */
-#define SCC_GSMRL_EDGE_NONE	((uint)0x60000000)
-#define SCC_GSMRL_EDGE_NEG	((uint)0x40000000)
-#define SCC_GSMRL_EDGE_POS	((uint)0x20000000)
-#define SCC_GSMRL_EDGE_BOTH	((uint)0x00000000)
-#define SCC_GSMRL_TCI		((uint)0x10000000)
-#define SCC_GSMRL_TSNC_3	((uint)0x0c000000)
-#define SCC_GSMRL_TSNC_4	((uint)0x08000000)
-#define SCC_GSMRL_TSNC_14	((uint)0x04000000)
-#define SCC_GSMRL_TSNC_INF	((uint)0x00000000)
-#define SCC_GSMRL_RINV		((uint)0x02000000)
-#define SCC_GSMRL_TINV		((uint)0x01000000)
-#define SCC_GSMRL_TPL_128	((uint)0x00c00000)
-#define SCC_GSMRL_TPL_64	((uint)0x00a00000)
-#define SCC_GSMRL_TPL_48	((uint)0x00800000)
-#define SCC_GSMRL_TPL_32	((uint)0x00600000)
-#define SCC_GSMRL_TPL_16	((uint)0x00400000)
-#define SCC_GSMRL_TPL_8		((uint)0x00200000)
-#define SCC_GSMRL_TPL_NONE	((uint)0x00000000)
-#define SCC_GSMRL_TPP_ALL1	((uint)0x00180000)
-#define SCC_GSMRL_TPP_01	((uint)0x00100000)
-#define SCC_GSMRL_TPP_10	((uint)0x00080000)
-#define SCC_GSMRL_TPP_ZEROS	((uint)0x00000000)
-#define SCC_GSMRL_TEND		((uint)0x00040000)
-#define SCC_GSMRL_TDCR_32	((uint)0x00030000)
-#define SCC_GSMRL_TDCR_16	((uint)0x00020000)
-#define SCC_GSMRL_TDCR_8	((uint)0x00010000)
-#define SCC_GSMRL_TDCR_1	((uint)0x00000000)
-#define SCC_GSMRL_RDCR_32	((uint)0x0000c000)
-#define SCC_GSMRL_RDCR_16	((uint)0x00008000)
-#define SCC_GSMRL_RDCR_8	((uint)0x00004000)
-#define SCC_GSMRL_RDCR_1	((uint)0x00000000)
-#define SCC_GSMRL_RENC_DFMAN	((uint)0x00003000)
-#define SCC_GSMRL_RENC_MANCH	((uint)0x00002000)
-#define SCC_GSMRL_RENC_FM0	((uint)0x00001000)
-#define SCC_GSMRL_RENC_NRZI	((uint)0x00000800)
-#define SCC_GSMRL_RENC_NRZ	((uint)0x00000000)
-#define SCC_GSMRL_TENC_DFMAN	((uint)0x00000600)
-#define SCC_GSMRL_TENC_MANCH	((uint)0x00000400)
-#define SCC_GSMRL_TENC_FM0	((uint)0x00000200)
-#define SCC_GSMRL_TENC_NRZI	((uint)0x00000100)
-#define SCC_GSMRL_TENC_NRZ	((uint)0x00000000)
-#define SCC_GSMRL_DIAG_LE	((uint)0x000000c0)	/* Loop and echo */
-#define SCC_GSMRL_DIAG_ECHO	((uint)0x00000080)
-#define SCC_GSMRL_DIAG_LOOP	((uint)0x00000040)
-#define SCC_GSMRL_DIAG_NORM	((uint)0x00000000)
-#define SCC_GSMRL_ENR		((uint)0x00000020)
-#define SCC_GSMRL_ENT		((uint)0x00000010)
-#define SCC_GSMRL_MODE_ENET	((uint)0x0000000c)
-#define SCC_GSMRL_MODE_QMC	((uint)0x0000000a)
-#define SCC_GSMRL_MODE_DDCMP	((uint)0x00000009)
-#define SCC_GSMRL_MODE_BISYNC	((uint)0x00000008)
-#define SCC_GSMRL_MODE_V14	((uint)0x00000007)
-#define SCC_GSMRL_MODE_AHDLC	((uint)0x00000006)
-#define SCC_GSMRL_MODE_PROFIBUS	((uint)0x00000005)
-#define SCC_GSMRL_MODE_UART	((uint)0x00000004)
-#define SCC_GSMRL_MODE_SS7	((uint)0x00000003)
-#define SCC_GSMRL_MODE_ATALK	((uint)0x00000002)
-#define SCC_GSMRL_MODE_HDLC	((uint)0x00000000)
-
-#define SCC_TODR_TOD		((ushort)0x8000)
-
-/* SCC Event and Mask register.
-*/
-#define	SCCM_TXE	((unsigned char)0x10)
-#define	SCCM_BSY	((unsigned char)0x04)
-#define	SCCM_TX		((unsigned char)0x02)
-#define	SCCM_RX		((unsigned char)0x01)
-
-typedef struct scc_param {
-	ushort	scc_rbase;	/* Rx Buffer descriptor base address */
-	ushort	scc_tbase;	/* Tx Buffer descriptor base address */
-	u_char	scc_rfcr;	/* Rx function code */
-	u_char	scc_tfcr;	/* Tx function code */
-	ushort	scc_mrblr;	/* Max receive buffer length */
-	uint	scc_rstate;	/* Internal */
-	uint	scc_idp;	/* Internal */
-	ushort	scc_rbptr;	/* Internal */
-	ushort	scc_ibc;	/* Internal */
-	uint	scc_rxtmp;	/* Internal */
-	uint	scc_tstate;	/* Internal */
-	uint	scc_tdp;	/* Internal */
-	ushort	scc_tbptr;	/* Internal */
-	ushort	scc_tbc;	/* Internal */
-	uint	scc_txtmp;	/* Internal */
-	uint	scc_rcrc;	/* Internal */
-	uint	scc_tcrc;	/* Internal */
-} sccp_t;
-
-/* Function code bits.
-*/
-#define SCC_EB	((u_char)0x10)	/* Set big endian byte order */
-
-/* CPM Ethernet through SCCx.
- */
-typedef struct scc_enet {
-	sccp_t	sen_genscc;
-	uint	sen_cpres;	/* Preset CRC */
-	uint	sen_cmask;	/* Constant mask for CRC */
-	uint	sen_crcec;	/* CRC Error counter */
-	uint	sen_alec;	/* alignment error counter */
-	uint	sen_disfc;	/* discard frame counter */
-	ushort	sen_pads;	/* Tx short frame pad character */
-	ushort	sen_retlim;	/* Retry limit threshold */
-	ushort	sen_retcnt;	/* Retry limit counter */
-	ushort	sen_maxflr;	/* maximum frame length register */
-	ushort	sen_minflr;	/* minimum frame length register */
-	ushort	sen_maxd1;	/* maximum DMA1 length */
-	ushort	sen_maxd2;	/* maximum DMA2 length */
-	ushort	sen_maxd;	/* Rx max DMA */
-	ushort	sen_dmacnt;	/* Rx DMA counter */
-	ushort	sen_maxb;	/* Max BD byte count */
-	ushort	sen_gaddr1;	/* Group address filter */
-	ushort	sen_gaddr2;
-	ushort	sen_gaddr3;
-	ushort	sen_gaddr4;
-	uint	sen_tbuf0data0;	/* Save area 0 - current frame */
-	uint	sen_tbuf0data1;	/* Save area 1 - current frame */
-	uint	sen_tbuf0rba;	/* Internal */
-	uint	sen_tbuf0crc;	/* Internal */
-	ushort	sen_tbuf0bcnt;	/* Internal */
-	ushort	sen_paddrh;	/* physical address (MSB) */
-	ushort	sen_paddrm;
-	ushort	sen_paddrl;	/* physical address (LSB) */
-	ushort	sen_pper;	/* persistence */
-	ushort	sen_rfbdptr;	/* Rx first BD pointer */
-	ushort	sen_tfbdptr;	/* Tx first BD pointer */
-	ushort	sen_tlbdptr;	/* Tx last BD pointer */
-	uint	sen_tbuf1data0;	/* Save area 0 - current frame */
-	uint	sen_tbuf1data1;	/* Save area 1 - current frame */
-	uint	sen_tbuf1rba;	/* Internal */
-	uint	sen_tbuf1crc;	/* Internal */
-	ushort	sen_tbuf1bcnt;	/* Internal */
-	ushort	sen_txlen;	/* Tx Frame length counter */
-	ushort	sen_iaddr1;	/* Individual address filter */
-	ushort	sen_iaddr2;
-	ushort	sen_iaddr3;
-	ushort	sen_iaddr4;
-	ushort	sen_boffcnt;	/* Backoff counter */
-
-	/* NOTE: Some versions of the manual have the following items
-	 * incorrectly documented.  Below is the proper order.
-	 */
-	ushort	sen_taddrh;	/* temp address (MSB) */
-	ushort	sen_taddrm;
-	ushort	sen_taddrl;	/* temp address (LSB) */
-} scc_enet_t;
-
-/* SCC Event register as used by Ethernet.
-*/
-#define SCCE_ENET_GRA	((ushort)0x0080)	/* Graceful stop complete */
-#define SCCE_ENET_TXE	((ushort)0x0010)	/* Transmit Error */
-#define SCCE_ENET_RXF	((ushort)0x0008)	/* Full frame received */
-#define SCCE_ENET_BSY	((ushort)0x0004)	/* All incoming buffers full */
-#define SCCE_ENET_TXB	((ushort)0x0002)	/* A buffer was transmitted */
-#define SCCE_ENET_RXB	((ushort)0x0001)	/* A buffer was received */
-
-/* SCC Mode Register (PMSR) as used by Ethernet.
-*/
-#define SCC_PSMR_HBC	((ushort)0x8000)	/* Enable heartbeat */
-#define SCC_PSMR_FC	((ushort)0x4000)	/* Force collision */
-#define SCC_PSMR_RSH	((ushort)0x2000)	/* Receive short frames */
-#define SCC_PSMR_IAM	((ushort)0x1000)	/* Check individual hash */
-#define SCC_PSMR_ENCRC	((ushort)0x0800)	/* Ethernet CRC mode */
-#define SCC_PSMR_PRO	((ushort)0x0200)	/* Promiscuous mode */
-#define SCC_PSMR_BRO	((ushort)0x0100)	/* Catch broadcast pkts */
-#define SCC_PSMR_SBT	((ushort)0x0080)	/* Special backoff timer */
-#define SCC_PSMR_LPB	((ushort)0x0040)	/* Set Loopback mode */
-#define SCC_PSMR_SIP	((ushort)0x0020)	/* Sample Input Pins */
-#define SCC_PSMR_LCW	((ushort)0x0010)	/* Late collision window */
-#define SCC_PSMR_NIB22	((ushort)0x000a)	/* Start frame search */
-#define SCC_PSMR_FDE	((ushort)0x0001)	/* Full duplex enable */
-
-/* SCC as UART
-*/
-typedef struct scc_uart {
-	sccp_t	scc_genscc;
-	char	res1[8];	/* Reserved */
-	ushort	scc_maxidl;	/* Maximum idle chars */
-	ushort	scc_idlc;	/* temp idle counter */
-	ushort	scc_brkcr;	/* Break count register */
-	ushort	scc_parec;	/* receive parity error counter */
-	ushort	scc_frmec;	/* receive framing error counter */
-	ushort	scc_nosec;	/* receive noise counter */
-	ushort	scc_brkec;	/* receive break condition counter */
-	ushort	scc_brkln;	/* last received break length */
-	ushort	scc_uaddr1;	/* UART address character 1 */
-	ushort	scc_uaddr2;	/* UART address character 2 */
-	ushort	scc_rtemp;	/* Temp storage */
-	ushort	scc_toseq;	/* Transmit out of sequence char */
-	ushort	scc_char1;	/* control character 1 */
-	ushort	scc_char2;	/* control character 2 */
-	ushort	scc_char3;	/* control character 3 */
-	ushort	scc_char4;	/* control character 4 */
-	ushort	scc_char5;	/* control character 5 */
-	ushort	scc_char6;	/* control character 6 */
-	ushort	scc_char7;	/* control character 7 */
-	ushort	scc_char8;	/* control character 8 */
-	ushort	scc_rccm;	/* receive control character mask */
-	ushort	scc_rccr;	/* receive control character register */
-	ushort	scc_rlbc;	/* receive last break character */
-} scc_uart_t;
-
-/* SCC Event and Mask registers when it is used as a UART.
-*/
-#define UART_SCCM_GLR		((ushort)0x1000)
-#define UART_SCCM_GLT		((ushort)0x0800)
-#define UART_SCCM_AB		((ushort)0x0200)
-#define UART_SCCM_IDL		((ushort)0x0100)
-#define UART_SCCM_GRA		((ushort)0x0080)
-#define UART_SCCM_BRKE		((ushort)0x0040)
-#define UART_SCCM_BRKS		((ushort)0x0020)
-#define UART_SCCM_CCR		((ushort)0x0008)
-#define UART_SCCM_BSY		((ushort)0x0004)
-#define UART_SCCM_TX		((ushort)0x0002)
-#define UART_SCCM_RX		((ushort)0x0001)
-
-/* The SCC PMSR when used as a UART.
-*/
-#define SCU_PSMR_FLC		((ushort)0x8000)
-#define SCU_PSMR_SL		((ushort)0x4000)
-#define SCU_PSMR_CL		((ushort)0x3000)
-#define SCU_PSMR_UM		((ushort)0x0c00)
-#define SCU_PSMR_FRZ		((ushort)0x0200)
-#define SCU_PSMR_RZS		((ushort)0x0100)
-#define SCU_PSMR_SYN		((ushort)0x0080)
-#define SCU_PSMR_DRT		((ushort)0x0040)
-#define SCU_PSMR_PEN		((ushort)0x0010)
-#define SCU_PSMR_RPM		((ushort)0x000c)
-#define SCU_PSMR_REVP		((ushort)0x0008)
-#define SCU_PSMR_TPM		((ushort)0x0003)
-#define SCU_PSMR_TEVP		((ushort)0x0002)
-
-/* CPM Transparent mode SCC.
- */
-typedef struct scc_trans {
-	sccp_t	st_genscc;
-	uint	st_cpres;	/* Preset CRC */
-	uint	st_cmask;	/* Constant mask for CRC */
-} scc_trans_t;
-
-/* IIC parameter RAM.
-*/
-typedef struct iic {
-	ushort	iic_rbase;	/* Rx Buffer descriptor base address */
-	ushort	iic_tbase;	/* Tx Buffer descriptor base address */
-	u_char	iic_rfcr;	/* Rx function code */
-	u_char	iic_tfcr;	/* Tx function code */
-	ushort	iic_mrblr;	/* Max receive buffer length */
-	uint	iic_rstate;	/* Internal */
-	uint	iic_rdp;	/* Internal */
-	ushort	iic_rbptr;	/* Internal */
-	ushort	iic_rbc;	/* Internal */
-	uint	iic_rxtmp;	/* Internal */
-	uint	iic_tstate;	/* Internal */
-	uint	iic_tdp;	/* Internal */
-	ushort	iic_tbptr;	/* Internal */
-	ushort	iic_tbc;	/* Internal */
-	uint	iic_txtmp;	/* Internal */
-	char	res1[4];	/* Reserved */
-	ushort	iic_rpbase;	/* Relocation pointer */
-	char	res2[2];	/* Reserved */
-} iic_t;
-
-/*
- * RISC Controller Configuration Register definitons
- */
-#define RCCR_TIME	0x8000			/* RISC Timer Enable */
-#define RCCR_TIMEP(t)	(((t) & 0x3F)<<8)	/* RISC Timer Period */
-#define RCCR_TIME_MASK	0x00FF			/* not RISC Timer related bits */
-
-/* RISC Timer Parameter RAM offset */
-#define PROFF_RTMR	((uint)0x01B0)
-
-typedef struct risc_timer_pram {
-	unsigned short	tm_base;	/* RISC Timer Table Base Address */
-	unsigned short	tm_ptr;		/* RISC Timer Table Pointer (internal) */
-	unsigned short	r_tmr;		/* RISC Timer Mode Register */
-	unsigned short	r_tmv;		/* RISC Timer Valid Register */
-	unsigned long	tm_cmd;		/* RISC Timer Command Register */
-	unsigned long	tm_cnt;		/* RISC Timer Internal Count */
-} rt_pram_t;
-
-/* Bits in RISC Timer Command Register */
-#define TM_CMD_VALID	0x80000000	/* Valid - Enables the timer */
-#define TM_CMD_RESTART	0x40000000	/* Restart - for automatic restart */
-#define TM_CMD_PWM	0x20000000	/* Run in Pulse Width Modulation Mode */
-#define TM_CMD_NUM(n)	(((n)&0xF)<<16)	/* Timer Number */
-#define TM_CMD_PERIOD(p) ((p)&0xFFFF)	/* Timer Period */
-
-/* CPM interrupts.  There are nearly 32 interrupts generated by CPM
- * channels or devices.  All of these are presented to the PPC core
- * as a single interrupt.  The CPM interrupt handler dispatches its
- * own handlers, in a similar fashion to the PPC core handler.  We
- * use the table as defined in the manuals (i.e. no special high
- * priority and SCC1 == SCCa, etc...).
- */
-#define CPMVEC_NR		32
-#define	CPMVEC_PIO_PC15		((ushort)0x1f)
-#define	CPMVEC_SCC1		((ushort)0x1e)
-#define	CPMVEC_SCC2		((ushort)0x1d)
-#define	CPMVEC_SCC3		((ushort)0x1c)
-#define	CPMVEC_SCC4		((ushort)0x1b)
-#define	CPMVEC_PIO_PC14		((ushort)0x1a)
-#define	CPMVEC_TIMER1		((ushort)0x19)
-#define	CPMVEC_PIO_PC13		((ushort)0x18)
-#define	CPMVEC_PIO_PC12		((ushort)0x17)
-#define	CPMVEC_SDMA_CB_ERR	((ushort)0x16)
-#define CPMVEC_IDMA1		((ushort)0x15)
-#define CPMVEC_IDMA2		((ushort)0x14)
-#define CPMVEC_TIMER2		((ushort)0x12)
-#define CPMVEC_RISCTIMER	((ushort)0x11)
-#define CPMVEC_I2C		((ushort)0x10)
-#define	CPMVEC_PIO_PC11		((ushort)0x0f)
-#define	CPMVEC_PIO_PC10		((ushort)0x0e)
-#define CPMVEC_TIMER3		((ushort)0x0c)
-#define	CPMVEC_PIO_PC9		((ushort)0x0b)
-#define	CPMVEC_PIO_PC8		((ushort)0x0a)
-#define	CPMVEC_PIO_PC7		((ushort)0x09)
-#define CPMVEC_TIMER4		((ushort)0x07)
-#define	CPMVEC_PIO_PC6		((ushort)0x06)
-#define	CPMVEC_SPI		((ushort)0x05)
-#define	CPMVEC_SMC1		((ushort)0x04)
-#define	CPMVEC_SMC2		((ushort)0x03)
-#define	CPMVEC_PIO_PC5		((ushort)0x02)
-#define	CPMVEC_PIO_PC4		((ushort)0x01)
-#define	CPMVEC_ERROR		((ushort)0x00)
-
-/* CPM interrupt configuration vector.
-*/
-#define	CICR_SCD_SCC4		((uint)0x00c00000)	/* SCC4 @ SCCd */
-#define	CICR_SCC_SCC3		((uint)0x00200000)	/* SCC3 @ SCCc */
-#define	CICR_SCB_SCC2		((uint)0x00040000)	/* SCC2 @ SCCb */
-#define	CICR_SCA_SCC1		((uint)0x00000000)	/* SCC1 @ SCCa */
-#define CICR_IRL_MASK		((uint)0x0000e000)	/* Core interrupt */
-#define CICR_HP_MASK		((uint)0x00001f00)	/* Hi-pri int. */
-#define CICR_IEN		((uint)0x00000080)	/* Int. enable */
-#define CICR_SPS		((uint)0x00000001)	/* SCC Spread */
-
-#define CPM_PIN_INPUT     0
-#define CPM_PIN_OUTPUT    1
-#define CPM_PIN_PRIMARY   0
-#define CPM_PIN_SECONDARY 2
-#define CPM_PIN_GPIO      4
-#define CPM_PIN_OPENDRAIN 8
-
-enum cpm_port {
-	CPM_PORTA,
-	CPM_PORTB,
-	CPM_PORTC,
-	CPM_PORTD,
-	CPM_PORTE,
-};
-
-void cpm1_set_pin(enum cpm_port port, int pin, int flags);
-
-enum cpm_clk_dir {
-	CPM_CLK_RX,
-	CPM_CLK_TX,
-	CPM_CLK_RTX
-};
-
-enum cpm_clk_target {
-	CPM_CLK_SCC1,
-	CPM_CLK_SCC2,
-	CPM_CLK_SCC3,
-	CPM_CLK_SCC4,
-	CPM_CLK_SMC1,
-	CPM_CLK_SMC2,
-};
-
-enum cpm_clk {
-	CPM_BRG1,	/* Baud Rate Generator  1 */
-	CPM_BRG2,	/* Baud Rate Generator  2 */
-	CPM_BRG3,	/* Baud Rate Generator  3 */
-	CPM_BRG4,	/* Baud Rate Generator  4 */
-	CPM_CLK1,	/* Clock  1 */
-	CPM_CLK2,	/* Clock  2 */
-	CPM_CLK3,	/* Clock  3 */
-	CPM_CLK4,	/* Clock  4 */
-	CPM_CLK5,	/* Clock  5 */
-	CPM_CLK6,	/* Clock  6 */
-	CPM_CLK7,	/* Clock  7 */
-	CPM_CLK8,	/* Clock  8 */
-};
-
-int cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode);
-
-#endif /* __CPM1__ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/cpm2.h b/ANDROID_3.4.5/arch/powerpc/include/asm/cpm2.h
deleted file mode 100644
index f42e9baf..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/cpm2.h
+++ /dev/null
@@ -1,1149 +0,0 @@
-/*
- * Communication Processor Module v2.
- *
- * This file contains structures and information for the communication
- * processor channels found in the dual port RAM or parameter RAM.
- * All CPM control and status is available through the CPM2 internal
- * memory map.  See immap_cpm2.h for details.
- */
-#ifdef __KERNEL__
-#ifndef __CPM2__
-#define __CPM2__
-
-#include <asm/immap_cpm2.h>
-#include <asm/cpm.h>
-#include <sysdev/fsl_soc.h>
-
-/* CPM Command register.
-*/
-#define CPM_CR_RST	((uint)0x80000000)
-#define CPM_CR_PAGE	((uint)0x7c000000)
-#define CPM_CR_SBLOCK	((uint)0x03e00000)
-#define CPM_CR_FLG	((uint)0x00010000)
-#define CPM_CR_MCN	((uint)0x00003fc0)
-#define CPM_CR_OPCODE	((uint)0x0000000f)
-
-/* Device sub-block and page codes.
-*/
-#define CPM_CR_SCC1_SBLOCK	(0x04)
-#define CPM_CR_SCC2_SBLOCK	(0x05)
-#define CPM_CR_SCC3_SBLOCK	(0x06)
-#define CPM_CR_SCC4_SBLOCK	(0x07)
-#define CPM_CR_SMC1_SBLOCK	(0x08)
-#define CPM_CR_SMC2_SBLOCK	(0x09)
-#define CPM_CR_SPI_SBLOCK	(0x0a)
-#define CPM_CR_I2C_SBLOCK	(0x0b)
-#define CPM_CR_TIMER_SBLOCK	(0x0f)
-#define CPM_CR_RAND_SBLOCK	(0x0e)
-#define CPM_CR_FCC1_SBLOCK	(0x10)
-#define CPM_CR_FCC2_SBLOCK	(0x11)
-#define CPM_CR_FCC3_SBLOCK	(0x12)
-#define CPM_CR_IDMA1_SBLOCK	(0x14)
-#define CPM_CR_IDMA2_SBLOCK	(0x15)
-#define CPM_CR_IDMA3_SBLOCK	(0x16)
-#define CPM_CR_IDMA4_SBLOCK	(0x17)
-#define CPM_CR_MCC1_SBLOCK	(0x1c)
-
-#define CPM_CR_FCC_SBLOCK(x)	(x + 0x10)
-
-#define CPM_CR_SCC1_PAGE	(0x00)
-#define CPM_CR_SCC2_PAGE	(0x01)
-#define CPM_CR_SCC3_PAGE	(0x02)
-#define CPM_CR_SCC4_PAGE	(0x03)
-#define CPM_CR_SMC1_PAGE	(0x07)
-#define CPM_CR_SMC2_PAGE	(0x08)
-#define CPM_CR_SPI_PAGE		(0x09)
-#define CPM_CR_I2C_PAGE		(0x0a)
-#define CPM_CR_TIMER_PAGE	(0x0a)
-#define CPM_CR_RAND_PAGE	(0x0a)
-#define CPM_CR_FCC1_PAGE	(0x04)
-#define CPM_CR_FCC2_PAGE	(0x05)
-#define CPM_CR_FCC3_PAGE	(0x06)
-#define CPM_CR_IDMA1_PAGE	(0x07)
-#define CPM_CR_IDMA2_PAGE	(0x08)
-#define CPM_CR_IDMA3_PAGE	(0x09)
-#define CPM_CR_IDMA4_PAGE	(0x0a)
-#define CPM_CR_MCC1_PAGE	(0x07)
-#define CPM_CR_MCC2_PAGE	(0x08)
-
-#define CPM_CR_FCC_PAGE(x)	(x + 0x04)
-
-/* CPM2-specific opcodes (see cpm.h for common opcodes)
-*/
-#define CPM_CR_START_IDMA	((ushort)0x0009)
-
-#define mk_cr_cmd(PG, SBC, MCN, OP) \
-	((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
-
-/* The number of pages of host memory we allocate for CPM.  This is
- * done early in kernel initialization to get physically contiguous
- * pages.
- */
-#define NUM_CPM_HOST_PAGES	2
-
-/* Export the base address of the communication processor registers
- * and dual port ram.
- */
-extern cpm_cpm2_t __iomem *cpmp; /* Pointer to comm processor */
-
-#define cpm_dpalloc cpm_muram_alloc
-#define cpm_dpfree cpm_muram_free
-#define cpm_dpram_addr cpm_muram_addr
-
-extern void cpm2_reset(void);
-
-/* Baud rate generators.
-*/
-#define CPM_BRG_RST		((uint)0x00020000)
-#define CPM_BRG_EN		((uint)0x00010000)
-#define CPM_BRG_EXTC_INT	((uint)0x00000000)
-#define CPM_BRG_EXTC_CLK3_9	((uint)0x00004000)
-#define CPM_BRG_EXTC_CLK5_15	((uint)0x00008000)
-#define CPM_BRG_ATB		((uint)0x00002000)
-#define CPM_BRG_CD_MASK		((uint)0x00001ffe)
-#define CPM_BRG_DIV16		((uint)0x00000001)
-
-#define CPM2_BRG_INT_CLK	(get_brgfreq())
-#define CPM2_BRG_UART_CLK	(CPM2_BRG_INT_CLK/16)
-
-extern void __cpm2_setbrg(uint brg, uint rate, uint clk, int div16, int src);
-
-/* This function is used by UARTS, or anything else that uses a 16x
- * oversampled clock.
- */
-static inline void cpm_setbrg(uint brg, uint rate)
-{
-	__cpm2_setbrg(brg, rate, CPM2_BRG_UART_CLK, 0, CPM_BRG_EXTC_INT);
-}
-
-/* This function is used to set high speed synchronous baud rate
- * clocks.
- */
-static inline void cpm2_fastbrg(uint brg, uint rate, int div16)
-{
-	__cpm2_setbrg(brg, rate, CPM2_BRG_INT_CLK, div16, CPM_BRG_EXTC_INT);
-}
-
-/* Parameter RAM offsets from the base.
-*/
-#define PROFF_SCC1		((uint)0x8000)
-#define PROFF_SCC2		((uint)0x8100)
-#define PROFF_SCC3		((uint)0x8200)
-#define PROFF_SCC4		((uint)0x8300)
-#define PROFF_FCC1		((uint)0x8400)
-#define PROFF_FCC2		((uint)0x8500)
-#define PROFF_FCC3		((uint)0x8600)
-#define PROFF_MCC1		((uint)0x8700)
-#define PROFF_SMC1_BASE		((uint)0x87fc)
-#define PROFF_IDMA1_BASE	((uint)0x87fe)
-#define PROFF_MCC2		((uint)0x8800)
-#define PROFF_SMC2_BASE		((uint)0x88fc)
-#define PROFF_IDMA2_BASE	((uint)0x88fe)
-#define PROFF_SPI_BASE		((uint)0x89fc)
-#define PROFF_IDMA3_BASE	((uint)0x89fe)
-#define PROFF_TIMERS		((uint)0x8ae0)
-#define PROFF_REVNUM		((uint)0x8af0)
-#define PROFF_RAND		((uint)0x8af8)
-#define PROFF_I2C_BASE		((uint)0x8afc)
-#define PROFF_IDMA4_BASE	((uint)0x8afe)
-
-#define PROFF_SCC_SIZE		((uint)0x100)
-#define PROFF_FCC_SIZE		((uint)0x100)
-#define PROFF_SMC_SIZE		((uint)64)
-
-/* The SMCs are relocated to any of the first eight DPRAM pages.
- * We will fix these at the first locations of DPRAM, until we
- * get some microcode patches :-).
- * The parameter ram space for the SMCs is fifty-some bytes, and
- * they are required to start on a 64 byte boundary.
- */
-#define PROFF_SMC1	(0)
-#define PROFF_SMC2	(64)
-
-
-/* Define enough so I can at least use the serial port as a UART.
- */
-typedef struct smc_uart {
-	ushort	smc_rbase;	/* Rx Buffer descriptor base address */
-	ushort	smc_tbase;	/* Tx Buffer descriptor base address */
-	u_char	smc_rfcr;	/* Rx function code */
-	u_char	smc_tfcr;	/* Tx function code */
-	ushort	smc_mrblr;	/* Max receive buffer length */
-	uint	smc_rstate;	/* Internal */
-	uint	smc_idp;	/* Internal */
-	ushort	smc_rbptr;	/* Internal */
-	ushort	smc_ibc;	/* Internal */
-	uint	smc_rxtmp;	/* Internal */
-	uint	smc_tstate;	/* Internal */
-	uint	smc_tdp;	/* Internal */
-	ushort	smc_tbptr;	/* Internal */
-	ushort	smc_tbc;	/* Internal */
-	uint	smc_txtmp;	/* Internal */
-	ushort	smc_maxidl;	/* Maximum idle characters */
-	ushort	smc_tmpidl;	/* Temporary idle counter */
-	ushort	smc_brklen;	/* Last received break length */
-	ushort	smc_brkec;	/* rcv'd break condition counter */
-	ushort	smc_brkcr;	/* xmt break count register */
-	ushort	smc_rmask;	/* Temporary bit mask */
-	uint	smc_stmp;	/* SDMA Temp */
-} smc_uart_t;
-
-/* SMC uart mode register (Internal memory map).
-*/
-#define SMCMR_REN	((ushort)0x0001)
-#define SMCMR_TEN	((ushort)0x0002)
-#define SMCMR_DM	((ushort)0x000c)
-#define SMCMR_SM_GCI	((ushort)0x0000)
-#define SMCMR_SM_UART	((ushort)0x0020)
-#define SMCMR_SM_TRANS	((ushort)0x0030)
-#define SMCMR_SM_MASK	((ushort)0x0030)
-#define SMCMR_PM_EVEN	((ushort)0x0100)	/* Even parity, else odd */
-#define SMCMR_REVD	SMCMR_PM_EVEN
-#define SMCMR_PEN	((ushort)0x0200)	/* Parity enable */
-#define SMCMR_BS	SMCMR_PEN
-#define SMCMR_SL	((ushort)0x0400)	/* Two stops, else one */
-#define SMCR_CLEN_MASK	((ushort)0x7800)	/* Character length */
-#define smcr_mk_clen(C)	(((C) << 11) & SMCR_CLEN_MASK)
-
-/* SMC Event and Mask register.
-*/
-#define SMCM_BRKE       ((unsigned char)0x40)   /* When in UART Mode */
-#define SMCM_BRK        ((unsigned char)0x10)   /* When in UART Mode */
-#define SMCM_TXE	((unsigned char)0x10)
-#define SMCM_BSY	((unsigned char)0x04)
-#define SMCM_TX		((unsigned char)0x02)
-#define SMCM_RX		((unsigned char)0x01)
-
-/* SCCs.
-*/
-#define SCC_GSMRH_IRP		((uint)0x00040000)
-#define SCC_GSMRH_GDE		((uint)0x00010000)
-#define SCC_GSMRH_TCRC_CCITT	((uint)0x00008000)
-#define SCC_GSMRH_TCRC_BISYNC	((uint)0x00004000)
-#define SCC_GSMRH_TCRC_HDLC	((uint)0x00000000)
-#define SCC_GSMRH_REVD		((uint)0x00002000)
-#define SCC_GSMRH_TRX		((uint)0x00001000)
-#define SCC_GSMRH_TTX		((uint)0x00000800)
-#define SCC_GSMRH_CDP		((uint)0x00000400)
-#define SCC_GSMRH_CTSP		((uint)0x00000200)
-#define SCC_GSMRH_CDS		((uint)0x00000100)
-#define SCC_GSMRH_CTSS		((uint)0x00000080)
-#define SCC_GSMRH_TFL		((uint)0x00000040)
-#define SCC_GSMRH_RFW		((uint)0x00000020)
-#define SCC_GSMRH_TXSY		((uint)0x00000010)
-#define SCC_GSMRH_SYNL16	((uint)0x0000000c)
-#define SCC_GSMRH_SYNL8		((uint)0x00000008)
-#define SCC_GSMRH_SYNL4		((uint)0x00000004)
-#define SCC_GSMRH_RTSM		((uint)0x00000002)
-#define SCC_GSMRH_RSYN		((uint)0x00000001)
-
-#define SCC_GSMRL_SIR		((uint)0x80000000)	/* SCC2 only */
-#define SCC_GSMRL_EDGE_NONE	((uint)0x60000000)
-#define SCC_GSMRL_EDGE_NEG	((uint)0x40000000)
-#define SCC_GSMRL_EDGE_POS	((uint)0x20000000)
-#define SCC_GSMRL_EDGE_BOTH	((uint)0x00000000)
-#define SCC_GSMRL_TCI		((uint)0x10000000)
-#define SCC_GSMRL_TSNC_3	((uint)0x0c000000)
-#define SCC_GSMRL_TSNC_4	((uint)0x08000000)
-#define SCC_GSMRL_TSNC_14	((uint)0x04000000)
-#define SCC_GSMRL_TSNC_INF	((uint)0x00000000)
-#define SCC_GSMRL_RINV		((uint)0x02000000)
-#define SCC_GSMRL_TINV		((uint)0x01000000)
-#define SCC_GSMRL_TPL_128	((uint)0x00c00000)
-#define SCC_GSMRL_TPL_64	((uint)0x00a00000)
-#define SCC_GSMRL_TPL_48	((uint)0x00800000)
-#define SCC_GSMRL_TPL_32	((uint)0x00600000)
-#define SCC_GSMRL_TPL_16	((uint)0x00400000)
-#define SCC_GSMRL_TPL_8		((uint)0x00200000)
-#define SCC_GSMRL_TPL_NONE	((uint)0x00000000)
-#define SCC_GSMRL_TPP_ALL1	((uint)0x00180000)
-#define SCC_GSMRL_TPP_01	((uint)0x00100000)
-#define SCC_GSMRL_TPP_10	((uint)0x00080000)
-#define SCC_GSMRL_TPP_ZEROS	((uint)0x00000000)
-#define SCC_GSMRL_TEND		((uint)0x00040000)
-#define SCC_GSMRL_TDCR_32	((uint)0x00030000)
-#define SCC_GSMRL_TDCR_16	((uint)0x00020000)
-#define SCC_GSMRL_TDCR_8	((uint)0x00010000)
-#define SCC_GSMRL_TDCR_1	((uint)0x00000000)
-#define SCC_GSMRL_RDCR_32	((uint)0x0000c000)
-#define SCC_GSMRL_RDCR_16	((uint)0x00008000)
-#define SCC_GSMRL_RDCR_8	((uint)0x00004000)
-#define SCC_GSMRL_RDCR_1	((uint)0x00000000)
-#define SCC_GSMRL_RENC_DFMAN	((uint)0x00003000)
-#define SCC_GSMRL_RENC_MANCH	((uint)0x00002000)
-#define SCC_GSMRL_RENC_FM0	((uint)0x00001000)
-#define SCC_GSMRL_RENC_NRZI	((uint)0x00000800)
-#define SCC_GSMRL_RENC_NRZ	((uint)0x00000000)
-#define SCC_GSMRL_TENC_DFMAN	((uint)0x00000600)
-#define SCC_GSMRL_TENC_MANCH	((uint)0x00000400)
-#define SCC_GSMRL_TENC_FM0	((uint)0x00000200)
-#define SCC_GSMRL_TENC_NRZI	((uint)0x00000100)
-#define SCC_GSMRL_TENC_NRZ	((uint)0x00000000)
-#define SCC_GSMRL_DIAG_LE	((uint)0x000000c0)	/* Loop and echo */
-#define SCC_GSMRL_DIAG_ECHO	((uint)0x00000080)
-#define SCC_GSMRL_DIAG_LOOP	((uint)0x00000040)
-#define SCC_GSMRL_DIAG_NORM	((uint)0x00000000)
-#define SCC_GSMRL_ENR		((uint)0x00000020)
-#define SCC_GSMRL_ENT		((uint)0x00000010)
-#define SCC_GSMRL_MODE_ENET	((uint)0x0000000c)
-#define SCC_GSMRL_MODE_DDCMP	((uint)0x00000009)
-#define SCC_GSMRL_MODE_BISYNC	((uint)0x00000008)
-#define SCC_GSMRL_MODE_V14	((uint)0x00000007)
-#define SCC_GSMRL_MODE_AHDLC	((uint)0x00000006)
-#define SCC_GSMRL_MODE_PROFIBUS	((uint)0x00000005)
-#define SCC_GSMRL_MODE_UART	((uint)0x00000004)
-#define SCC_GSMRL_MODE_SS7	((uint)0x00000003)
-#define SCC_GSMRL_MODE_ATALK	((uint)0x00000002)
-#define SCC_GSMRL_MODE_HDLC	((uint)0x00000000)
-
-#define SCC_TODR_TOD		((ushort)0x8000)
-
-/* SCC Event and Mask register.
-*/
-#define SCCM_TXE	((unsigned char)0x10)
-#define SCCM_BSY	((unsigned char)0x04)
-#define SCCM_TX		((unsigned char)0x02)
-#define SCCM_RX		((unsigned char)0x01)
-
-typedef struct scc_param {
-	ushort	scc_rbase;	/* Rx Buffer descriptor base address */
-	ushort	scc_tbase;	/* Tx Buffer descriptor base address */
-	u_char	scc_rfcr;	/* Rx function code */
-	u_char	scc_tfcr;	/* Tx function code */
-	ushort	scc_mrblr;	/* Max receive buffer length */
-	uint	scc_rstate;	/* Internal */
-	uint	scc_idp;	/* Internal */
-	ushort	scc_rbptr;	/* Internal */
-	ushort	scc_ibc;	/* Internal */
-	uint	scc_rxtmp;	/* Internal */
-	uint	scc_tstate;	/* Internal */
-	uint	scc_tdp;	/* Internal */
-	ushort	scc_tbptr;	/* Internal */
-	ushort	scc_tbc;	/* Internal */
-	uint	scc_txtmp;	/* Internal */
-	uint	scc_rcrc;	/* Internal */
-	uint	scc_tcrc;	/* Internal */
-} sccp_t;
-
-/* Function code bits.
-*/
-#define SCC_EB	((u_char) 0x10)	/* Set big endian byte order */
-#define SCC_GBL	((u_char) 0x20) /* Snooping enabled */
-
-/* CPM Ethernet through SCC1.
- */
-typedef struct scc_enet {
-	sccp_t	sen_genscc;
-	uint	sen_cpres;	/* Preset CRC */
-	uint	sen_cmask;	/* Constant mask for CRC */
-	uint	sen_crcec;	/* CRC Error counter */
-	uint	sen_alec;	/* alignment error counter */
-	uint	sen_disfc;	/* discard frame counter */
-	ushort	sen_pads;	/* Tx short frame pad character */
-	ushort	sen_retlim;	/* Retry limit threshold */
-	ushort	sen_retcnt;	/* Retry limit counter */
-	ushort	sen_maxflr;	/* maximum frame length register */
-	ushort	sen_minflr;	/* minimum frame length register */
-	ushort	sen_maxd1;	/* maximum DMA1 length */
-	ushort	sen_maxd2;	/* maximum DMA2 length */
-	ushort	sen_maxd;	/* Rx max DMA */
-	ushort	sen_dmacnt;	/* Rx DMA counter */
-	ushort	sen_maxb;	/* Max BD byte count */
-	ushort	sen_gaddr1;	/* Group address filter */
-	ushort	sen_gaddr2;
-	ushort	sen_gaddr3;
-	ushort	sen_gaddr4;
-	uint	sen_tbuf0data0;	/* Save area 0 - current frame */
-	uint	sen_tbuf0data1;	/* Save area 1 - current frame */
-	uint	sen_tbuf0rba;	/* Internal */
-	uint	sen_tbuf0crc;	/* Internal */
-	ushort	sen_tbuf0bcnt;	/* Internal */
-	ushort	sen_paddrh;	/* physical address (MSB) */
-	ushort	sen_paddrm;
-	ushort	sen_paddrl;	/* physical address (LSB) */
-	ushort	sen_pper;	/* persistence */
-	ushort	sen_rfbdptr;	/* Rx first BD pointer */
-	ushort	sen_tfbdptr;	/* Tx first BD pointer */
-	ushort	sen_tlbdptr;	/* Tx last BD pointer */
-	uint	sen_tbuf1data0;	/* Save area 0 - current frame */
-	uint	sen_tbuf1data1;	/* Save area 1 - current frame */
-	uint	sen_tbuf1rba;	/* Internal */
-	uint	sen_tbuf1crc;	/* Internal */
-	ushort	sen_tbuf1bcnt;	/* Internal */
-	ushort	sen_txlen;	/* Tx Frame length counter */
-	ushort	sen_iaddr1;	/* Individual address filter */
-	ushort	sen_iaddr2;
-	ushort	sen_iaddr3;
-	ushort	sen_iaddr4;
-	ushort	sen_boffcnt;	/* Backoff counter */
-
-	/* NOTE: Some versions of the manual have the following items
-	 * incorrectly documented.  Below is the proper order.
-	 */
-	ushort	sen_taddrh;	/* temp address (MSB) */
-	ushort	sen_taddrm;
-	ushort	sen_taddrl;	/* temp address (LSB) */
-} scc_enet_t;
-
-
-/* SCC Event register as used by Ethernet.
-*/
-#define SCCE_ENET_GRA	((ushort)0x0080)	/* Graceful stop complete */
-#define SCCE_ENET_TXE	((ushort)0x0010)	/* Transmit Error */
-#define SCCE_ENET_RXF	((ushort)0x0008)	/* Full frame received */
-#define SCCE_ENET_BSY	((ushort)0x0004)	/* All incoming buffers full */
-#define SCCE_ENET_TXB	((ushort)0x0002)	/* A buffer was transmitted */
-#define SCCE_ENET_RXB	((ushort)0x0001)	/* A buffer was received */
-
-/* SCC Mode Register (PSMR) as used by Ethernet.
-*/
-#define SCC_PSMR_HBC	((ushort)0x8000)	/* Enable heartbeat */
-#define SCC_PSMR_FC	((ushort)0x4000)	/* Force collision */
-#define SCC_PSMR_RSH	((ushort)0x2000)	/* Receive short frames */
-#define SCC_PSMR_IAM	((ushort)0x1000)	/* Check individual hash */
-#define SCC_PSMR_ENCRC	((ushort)0x0800)	/* Ethernet CRC mode */
-#define SCC_PSMR_PRO	((ushort)0x0200)	/* Promiscuous mode */
-#define SCC_PSMR_BRO	((ushort)0x0100)	/* Catch broadcast pkts */
-#define SCC_PSMR_SBT	((ushort)0x0080)	/* Special backoff timer */
-#define SCC_PSMR_LPB	((ushort)0x0040)	/* Set Loopback mode */
-#define SCC_PSMR_SIP	((ushort)0x0020)	/* Sample Input Pins */
-#define SCC_PSMR_LCW	((ushort)0x0010)	/* Late collision window */
-#define SCC_PSMR_NIB22	((ushort)0x000a)	/* Start frame search */
-#define SCC_PSMR_FDE	((ushort)0x0001)	/* Full duplex enable */
-
-/* SCC as UART
-*/
-typedef struct scc_uart {
-	sccp_t	scc_genscc;
-	uint	scc_res1;	/* Reserved */
-	uint	scc_res2;	/* Reserved */
-	ushort	scc_maxidl;	/* Maximum idle chars */
-	ushort	scc_idlc;	/* temp idle counter */
-	ushort	scc_brkcr;	/* Break count register */
-	ushort	scc_parec;	/* receive parity error counter */
-	ushort	scc_frmec;	/* receive framing error counter */
-	ushort	scc_nosec;	/* receive noise counter */
-	ushort	scc_brkec;	/* receive break condition counter */
-	ushort	scc_brkln;	/* last received break length */
-	ushort	scc_uaddr1;	/* UART address character 1 */
-	ushort	scc_uaddr2;	/* UART address character 2 */
-	ushort	scc_rtemp;	/* Temp storage */
-	ushort	scc_toseq;	/* Transmit out of sequence char */
-	ushort	scc_char1;	/* control character 1 */
-	ushort	scc_char2;	/* control character 2 */
-	ushort	scc_char3;	/* control character 3 */
-	ushort	scc_char4;	/* control character 4 */
-	ushort	scc_char5;	/* control character 5 */
-	ushort	scc_char6;	/* control character 6 */
-	ushort	scc_char7;	/* control character 7 */
-	ushort	scc_char8;	/* control character 8 */
-	ushort	scc_rccm;	/* receive control character mask */
-	ushort	scc_rccr;	/* receive control character register */
-	ushort	scc_rlbc;	/* receive last break character */
-} scc_uart_t;
-
-/* SCC Event and Mask registers when it is used as a UART.
-*/
-#define UART_SCCM_GLR		((ushort)0x1000)
-#define UART_SCCM_GLT		((ushort)0x0800)
-#define UART_SCCM_AB		((ushort)0x0200)
-#define UART_SCCM_IDL		((ushort)0x0100)
-#define UART_SCCM_GRA		((ushort)0x0080)
-#define UART_SCCM_BRKE		((ushort)0x0040)
-#define UART_SCCM_BRKS		((ushort)0x0020)
-#define UART_SCCM_CCR		((ushort)0x0008)
-#define UART_SCCM_BSY		((ushort)0x0004)
-#define UART_SCCM_TX		((ushort)0x0002)
-#define UART_SCCM_RX		((ushort)0x0001)
-
-/* The SCC PSMR when used as a UART.
-*/
-#define SCU_PSMR_FLC		((ushort)0x8000)
-#define SCU_PSMR_SL		((ushort)0x4000)
-#define SCU_PSMR_CL		((ushort)0x3000)
-#define SCU_PSMR_UM		((ushort)0x0c00)
-#define SCU_PSMR_FRZ		((ushort)0x0200)
-#define SCU_PSMR_RZS		((ushort)0x0100)
-#define SCU_PSMR_SYN		((ushort)0x0080)
-#define SCU_PSMR_DRT		((ushort)0x0040)
-#define SCU_PSMR_PEN		((ushort)0x0010)
-#define SCU_PSMR_RPM		((ushort)0x000c)
-#define SCU_PSMR_REVP		((ushort)0x0008)
-#define SCU_PSMR_TPM		((ushort)0x0003)
-#define SCU_PSMR_TEVP		((ushort)0x0002)
-
-/* CPM Transparent mode SCC.
- */
-typedef struct scc_trans {
-	sccp_t	st_genscc;
-	uint	st_cpres;	/* Preset CRC */
-	uint	st_cmask;	/* Constant mask for CRC */
-} scc_trans_t;
-
-/* How about some FCCs.....
-*/
-#define FCC_GFMR_DIAG_NORM	((uint)0x00000000)
-#define FCC_GFMR_DIAG_LE	((uint)0x40000000)
-#define FCC_GFMR_DIAG_AE	((uint)0x80000000)
-#define FCC_GFMR_DIAG_ALE	((uint)0xc0000000)
-#define FCC_GFMR_TCI		((uint)0x20000000)
-#define FCC_GFMR_TRX		((uint)0x10000000)
-#define FCC_GFMR_TTX		((uint)0x08000000)
-#define FCC_GFMR_TTX		((uint)0x08000000)
-#define FCC_GFMR_CDP		((uint)0x04000000)
-#define FCC_GFMR_CTSP		((uint)0x02000000)
-#define FCC_GFMR_CDS		((uint)0x01000000)
-#define FCC_GFMR_CTSS		((uint)0x00800000)
-#define FCC_GFMR_SYNL_NONE	((uint)0x00000000)
-#define FCC_GFMR_SYNL_AUTO	((uint)0x00004000)
-#define FCC_GFMR_SYNL_8		((uint)0x00008000)
-#define FCC_GFMR_SYNL_16	((uint)0x0000c000)
-#define FCC_GFMR_RTSM		((uint)0x00002000)
-#define FCC_GFMR_RENC_NRZ	((uint)0x00000000)
-#define FCC_GFMR_RENC_NRZI	((uint)0x00000800)
-#define FCC_GFMR_REVD		((uint)0x00000400)
-#define FCC_GFMR_TENC_NRZ	((uint)0x00000000)
-#define FCC_GFMR_TENC_NRZI	((uint)0x00000100)
-#define FCC_GFMR_TCRC_16	((uint)0x00000000)
-#define FCC_GFMR_TCRC_32	((uint)0x00000080)
-#define FCC_GFMR_ENR		((uint)0x00000020)
-#define FCC_GFMR_ENT		((uint)0x00000010)
-#define FCC_GFMR_MODE_ENET	((uint)0x0000000c)
-#define FCC_GFMR_MODE_ATM	((uint)0x0000000a)
-#define FCC_GFMR_MODE_HDLC	((uint)0x00000000)
-
-/* Generic FCC parameter ram.
-*/
-typedef struct fcc_param {
-	ushort	fcc_riptr;	/* Rx Internal temp pointer */
-	ushort	fcc_tiptr;	/* Tx Internal temp pointer */
-	ushort	fcc_res1;
-	ushort	fcc_mrblr;	/* Max receive buffer length, mod 32 bytes */
-	uint	fcc_rstate;	/* Upper byte is Func code, must be set */
-	uint	fcc_rbase;	/* Receive BD base */
-	ushort	fcc_rbdstat;	/* RxBD status */
-	ushort	fcc_rbdlen;	/* RxBD down counter */
-	uint	fcc_rdptr;	/* RxBD internal data pointer */
-	uint	fcc_tstate;	/* Upper byte is Func code, must be set */
-	uint	fcc_tbase;	/* Transmit BD base */
-	ushort	fcc_tbdstat;	/* TxBD status */
-	ushort	fcc_tbdlen;	/* TxBD down counter */
-	uint	fcc_tdptr;	/* TxBD internal data pointer */
-	uint	fcc_rbptr;	/* Rx BD Internal buf pointer */
-	uint	fcc_tbptr;	/* Tx BD Internal buf pointer */
-	uint	fcc_rcrc;	/* Rx temp CRC */
-	uint	fcc_res2;
-	uint	fcc_tcrc;	/* Tx temp CRC */
-} fccp_t;
-
-
-/* Ethernet controller through FCC.
-*/
-typedef struct fcc_enet {
-	fccp_t	fen_genfcc;
-	uint	fen_statbuf;	/* Internal status buffer */
-	uint	fen_camptr;	/* CAM address */
-	uint	fen_cmask;	/* Constant mask for CRC */
-	uint	fen_cpres;	/* Preset CRC */
-	uint	fen_crcec;	/* CRC Error counter */
-	uint	fen_alec;	/* alignment error counter */
-	uint	fen_disfc;	/* discard frame counter */
-	ushort	fen_retlim;	/* Retry limit */
-	ushort	fen_retcnt;	/* Retry counter */
-	ushort	fen_pper;	/* Persistence */
-	ushort	fen_boffcnt;	/* backoff counter */
-	uint	fen_gaddrh;	/* Group address filter, high 32-bits */
-	uint	fen_gaddrl;	/* Group address filter, low 32-bits */
-	ushort	fen_tfcstat;	/* out of sequence TxBD */
-	ushort	fen_tfclen;
-	uint	fen_tfcptr;
-	ushort	fen_mflr;	/* Maximum frame length (1518) */
-	ushort	fen_paddrh;	/* MAC address */
-	ushort	fen_paddrm;
-	ushort	fen_paddrl;
-	ushort	fen_ibdcount;	/* Internal BD counter */
-	ushort	fen_ibdstart;	/* Internal BD start pointer */
-	ushort	fen_ibdend;	/* Internal BD end pointer */
-	ushort	fen_txlen;	/* Internal Tx frame length counter */
-	uint	fen_ibdbase[8]; /* Internal use */
-	uint	fen_iaddrh;	/* Individual address filter */
-	uint	fen_iaddrl;
-	ushort	fen_minflr;	/* Minimum frame length (64) */
-	ushort	fen_taddrh;	/* Filter transfer MAC address */
-	ushort	fen_taddrm;
-	ushort	fen_taddrl;
-	ushort	fen_padptr;	/* Pointer to pad byte buffer */
-	ushort	fen_cftype;	/* control frame type */
-	ushort	fen_cfrange;	/* control frame range */
-	ushort	fen_maxb;	/* maximum BD count */
-	ushort	fen_maxd1;	/* Max DMA1 length (1520) */
-	ushort	fen_maxd2;	/* Max DMA2 length (1520) */
-	ushort	fen_maxd;	/* internal max DMA count */
-	ushort	fen_dmacnt;	/* internal DMA counter */
-	uint	fen_octc;	/* Total octect counter */
-	uint	fen_colc;	/* Total collision counter */
-	uint	fen_broc;	/* Total broadcast packet counter */
-	uint	fen_mulc;	/* Total multicast packet count */
-	uint	fen_uspc;	/* Total packets < 64 bytes */
-	uint	fen_frgc;	/* Total packets < 64 bytes with errors */
-	uint	fen_ospc;	/* Total packets > 1518 */
-	uint	fen_jbrc;	/* Total packets > 1518 with errors */
-	uint	fen_p64c;	/* Total packets == 64 bytes */
-	uint	fen_p65c;	/* Total packets 64 < bytes <= 127 */
-	uint	fen_p128c;	/* Total packets 127 < bytes <= 255 */
-	uint	fen_p256c;	/* Total packets 256 < bytes <= 511 */
-	uint	fen_p512c;	/* Total packets 512 < bytes <= 1023 */
-	uint	fen_p1024c;	/* Total packets 1024 < bytes <= 1518 */
-	uint	fen_cambuf;	/* Internal CAM buffer poiner */
-	ushort	fen_rfthr;	/* Received frames threshold */
-	ushort	fen_rfcnt;	/* Received frames count */
-} fcc_enet_t;
-
-/* FCC Event/Mask register as used by Ethernet.
-*/
-#define FCC_ENET_GRA	((ushort)0x0080)	/* Graceful stop complete */
-#define FCC_ENET_RXC	((ushort)0x0040)	/* Control Frame Received */
-#define FCC_ENET_TXC	((ushort)0x0020)	/* Out of seq. Tx sent */
-#define FCC_ENET_TXE	((ushort)0x0010)	/* Transmit Error */
-#define FCC_ENET_RXF	((ushort)0x0008)	/* Full frame received */
-#define FCC_ENET_BSY	((ushort)0x0004)	/* Busy.  Rx Frame dropped */
-#define FCC_ENET_TXB	((ushort)0x0002)	/* A buffer was transmitted */
-#define FCC_ENET_RXB	((ushort)0x0001)	/* A buffer was received */
-
-/* FCC Mode Register (FPSMR) as used by Ethernet.
-*/
-#define FCC_PSMR_HBC	((uint)0x80000000)	/* Enable heartbeat */
-#define FCC_PSMR_FC	((uint)0x40000000)	/* Force Collision */
-#define FCC_PSMR_SBT	((uint)0x20000000)	/* Stop backoff timer */
-#define FCC_PSMR_LPB	((uint)0x10000000)	/* Local protect. 1 = FDX */
-#define FCC_PSMR_LCW	((uint)0x08000000)	/* Late collision select */
-#define FCC_PSMR_FDE	((uint)0x04000000)	/* Full Duplex Enable */
-#define FCC_PSMR_MON	((uint)0x02000000)	/* RMON Enable */
-#define FCC_PSMR_PRO	((uint)0x00400000)	/* Promiscuous Enable */
-#define FCC_PSMR_FCE	((uint)0x00200000)	/* Flow Control Enable */
-#define FCC_PSMR_RSH	((uint)0x00100000)	/* Receive Short Frames */
-#define FCC_PSMR_CAM	((uint)0x00000400)	/* CAM enable */
-#define FCC_PSMR_BRO	((uint)0x00000200)	/* Broadcast pkt discard */
-#define FCC_PSMR_ENCRC	((uint)0x00000080)	/* Use 32-bit CRC */
-
-/* IIC parameter RAM.
-*/
-typedef struct iic {
-	ushort	iic_rbase;	/* Rx Buffer descriptor base address */
-	ushort	iic_tbase;	/* Tx Buffer descriptor base address */
-	u_char	iic_rfcr;	/* Rx function code */
-	u_char	iic_tfcr;	/* Tx function code */
-	ushort	iic_mrblr;	/* Max receive buffer length */
-	uint	iic_rstate;	/* Internal */
-	uint	iic_rdp;	/* Internal */
-	ushort	iic_rbptr;	/* Internal */
-	ushort	iic_rbc;	/* Internal */
-	uint	iic_rxtmp;	/* Internal */
-	uint	iic_tstate;	/* Internal */
-	uint	iic_tdp;	/* Internal */
-	ushort	iic_tbptr;	/* Internal */
-	ushort	iic_tbc;	/* Internal */
-	uint	iic_txtmp;	/* Internal */
-} iic_t;
-
-/* IDMA parameter RAM
-*/
-typedef struct idma {
-	ushort ibase;		/* IDMA buffer descriptor table base address */
-	ushort dcm;		/* DMA channel mode */
-	ushort ibdptr;		/* IDMA current buffer descriptor pointer */
-	ushort dpr_buf;		/* IDMA transfer buffer base address */
-	ushort buf_inv;		/* internal buffer inventory */
-	ushort ss_max;		/* steady-state maximum transfer size */
-	ushort dpr_in_ptr;	/* write pointer inside the internal buffer */
-	ushort sts;		/* source transfer size */
-	ushort dpr_out_ptr;	/* read pointer inside the internal buffer */
-	ushort seob;		/* source end of burst */
-	ushort deob;		/* destination end of burst */
-	ushort dts;		/* destination transfer size */
-	ushort ret_add;		/* return address when working in ERM=1 mode */
-	ushort res0;		/* reserved */
-	uint   bd_cnt;		/* internal byte count */
-	uint   s_ptr;		/* source internal data pointer */
-	uint   d_ptr;		/* destination internal data pointer */
-	uint   istate;		/* internal state */
-	u_char res1[20];	/* pad to 64-byte length */
-} idma_t;
-
-/* DMA channel mode bit fields
-*/
-#define IDMA_DCM_FB		((ushort)0x8000) /* fly-by mode */
-#define IDMA_DCM_LP		((ushort)0x4000) /* low priority */
-#define IDMA_DCM_TC2		((ushort)0x0400) /* value driven on TC[2] */
-#define IDMA_DCM_DMA_WRAP_MASK	((ushort)0x01c0) /* mask for DMA wrap */
-#define IDMA_DCM_DMA_WRAP_64	((ushort)0x0000) /* 64-byte DMA xfer buffer */
-#define IDMA_DCM_DMA_WRAP_128	((ushort)0x0040) /* 128-byte DMA xfer buffer */
-#define IDMA_DCM_DMA_WRAP_256	((ushort)0x0080) /* 256-byte DMA xfer buffer */
-#define IDMA_DCM_DMA_WRAP_512	((ushort)0x00c0) /* 512-byte DMA xfer buffer */
-#define IDMA_DCM_DMA_WRAP_1024	((ushort)0x0100) /* 1024-byte DMA xfer buffer */
-#define IDMA_DCM_DMA_WRAP_2048	((ushort)0x0140) /* 2048-byte DMA xfer buffer */
-#define IDMA_DCM_SINC		((ushort)0x0020) /* source inc addr */
-#define IDMA_DCM_DINC		((ushort)0x0010) /* destination inc addr */
-#define IDMA_DCM_ERM		((ushort)0x0008) /* external request mode */
-#define IDMA_DCM_DT		((ushort)0x0004) /* DONE treatment */
-#define IDMA_DCM_SD_MASK	((ushort)0x0003) /* mask for SD bit field */
-#define IDMA_DCM_SD_MEM2MEM	((ushort)0x0000) /* memory-to-memory xfer */
-#define IDMA_DCM_SD_PER2MEM	((ushort)0x0002) /* peripheral-to-memory xfer */
-#define IDMA_DCM_SD_MEM2PER	((ushort)0x0001) /* memory-to-peripheral xfer */
-
-/* IDMA Buffer Descriptors
-*/
-typedef struct idma_bd {
-	uint flags;
-	uint len;	/* data length */
-	uint src;	/* source data buffer pointer */
-	uint dst;	/* destination data buffer pointer */
-} idma_bd_t;
-
-/* IDMA buffer descriptor flag bit fields
-*/
-#define IDMA_BD_V	((uint)0x80000000)	/* valid */
-#define IDMA_BD_W	((uint)0x20000000)	/* wrap */
-#define IDMA_BD_I	((uint)0x10000000)	/* interrupt */
-#define IDMA_BD_L	((uint)0x08000000)	/* last */
-#define IDMA_BD_CM	((uint)0x02000000)	/* continuous mode */
-#define IDMA_BD_SDN	((uint)0x00400000)	/* source done */
-#define IDMA_BD_DDN	((uint)0x00200000)	/* destination done */
-#define IDMA_BD_DGBL	((uint)0x00100000)	/* destination global */
-#define IDMA_BD_DBO_LE	((uint)0x00040000)	/* little-end dest byte order */
-#define IDMA_BD_DBO_BE	((uint)0x00080000)	/* big-end dest byte order */
-#define IDMA_BD_DDTB	((uint)0x00010000)	/* destination data bus */
-#define IDMA_BD_SGBL	((uint)0x00002000)	/* source global */
-#define IDMA_BD_SBO_LE	((uint)0x00000800)	/* little-end src byte order */
-#define IDMA_BD_SBO_BE	((uint)0x00001000)	/* big-end src byte order */
-#define IDMA_BD_SDTB	((uint)0x00000200)	/* source data bus */
-
-/* per-channel IDMA registers
-*/
-typedef struct im_idma {
-	u_char idsr;			/* IDMAn event status register */
-	u_char res0[3];
-	u_char idmr;			/* IDMAn event mask register */
-	u_char res1[3];
-} im_idma_t;
-
-/* IDMA event register bit fields
-*/
-#define IDMA_EVENT_SC	((unsigned char)0x08)	/* stop completed */
-#define IDMA_EVENT_OB	((unsigned char)0x04)	/* out of buffers */
-#define IDMA_EVENT_EDN	((unsigned char)0x02)	/* external DONE asserted */
-#define IDMA_EVENT_BC	((unsigned char)0x01)	/* buffer descriptor complete */
-
-/* RISC Controller Configuration Register (RCCR) bit fields
-*/
-#define RCCR_TIME	((uint)0x80000000) /* timer enable */
-#define RCCR_TIMEP_MASK	((uint)0x3f000000) /* mask for timer period bit field */
-#define RCCR_DR0M	((uint)0x00800000) /* IDMA0 request mode */
-#define RCCR_DR1M	((uint)0x00400000) /* IDMA1 request mode */
-#define RCCR_DR2M	((uint)0x00000080) /* IDMA2 request mode */
-#define RCCR_DR3M	((uint)0x00000040) /* IDMA3 request mode */
-#define RCCR_DR0QP_MASK	((uint)0x00300000) /* mask for IDMA0 req priority */
-#define RCCR_DR0QP_HIGH ((uint)0x00000000) /* IDMA0 has high req priority */
-#define RCCR_DR0QP_MED	((uint)0x00100000) /* IDMA0 has medium req priority */
-#define RCCR_DR0QP_LOW	((uint)0x00200000) /* IDMA0 has low req priority */
-#define RCCR_DR1QP_MASK	((uint)0x00030000) /* mask for IDMA1 req priority */
-#define RCCR_DR1QP_HIGH ((uint)0x00000000) /* IDMA1 has high req priority */
-#define RCCR_DR1QP_MED	((uint)0x00010000) /* IDMA1 has medium req priority */
-#define RCCR_DR1QP_LOW	((uint)0x00020000) /* IDMA1 has low req priority */
-#define RCCR_DR2QP_MASK	((uint)0x00000030) /* mask for IDMA2 req priority */
-#define RCCR_DR2QP_HIGH ((uint)0x00000000) /* IDMA2 has high req priority */
-#define RCCR_DR2QP_MED	((uint)0x00000010) /* IDMA2 has medium req priority */
-#define RCCR_DR2QP_LOW	((uint)0x00000020) /* IDMA2 has low req priority */
-#define RCCR_DR3QP_MASK	((uint)0x00000003) /* mask for IDMA3 req priority */
-#define RCCR_DR3QP_HIGH ((uint)0x00000000) /* IDMA3 has high req priority */
-#define RCCR_DR3QP_MED	((uint)0x00000001) /* IDMA3 has medium req priority */
-#define RCCR_DR3QP_LOW	((uint)0x00000002) /* IDMA3 has low req priority */
-#define RCCR_EIE	((uint)0x00080000) /* external interrupt enable */
-#define RCCR_SCD	((uint)0x00040000) /* scheduler configuration */
-#define RCCR_ERAM_MASK	((uint)0x0000e000) /* mask for enable RAM microcode */
-#define RCCR_ERAM_0KB	((uint)0x00000000) /* use 0KB of dpram for microcode */
-#define RCCR_ERAM_2KB	((uint)0x00002000) /* use 2KB of dpram for microcode */
-#define RCCR_ERAM_4KB	((uint)0x00004000) /* use 4KB of dpram for microcode */
-#define RCCR_ERAM_6KB	((uint)0x00006000) /* use 6KB of dpram for microcode */
-#define RCCR_ERAM_8KB	((uint)0x00008000) /* use 8KB of dpram for microcode */
-#define RCCR_ERAM_10KB	((uint)0x0000a000) /* use 10KB of dpram for microcode */
-#define RCCR_ERAM_12KB	((uint)0x0000c000) /* use 12KB of dpram for microcode */
-#define RCCR_EDM0	((uint)0x00000800) /* DREQ0 edge detect mode */
-#define RCCR_EDM1	((uint)0x00000400) /* DREQ1 edge detect mode */
-#define RCCR_EDM2	((uint)0x00000200) /* DREQ2 edge detect mode */
-#define RCCR_EDM3	((uint)0x00000100) /* DREQ3 edge detect mode */
-#define RCCR_DEM01	((uint)0x00000008) /* DONE0/DONE1 edge detect mode */
-#define RCCR_DEM23	((uint)0x00000004) /* DONE2/DONE3 edge detect mode */
-
-/*-----------------------------------------------------------------------
- * CMXFCR - CMX FCC Clock Route Register
- */
-#define CMXFCR_FC1         0x40000000   /* FCC1 connection              */
-#define CMXFCR_RF1CS_MSK   0x38000000   /* Receive FCC1 Clock Source Mask */
-#define CMXFCR_TF1CS_MSK   0x07000000   /* Transmit FCC1 Clock Source Mask */
-#define CMXFCR_FC2         0x00400000   /* FCC2 connection              */
-#define CMXFCR_RF2CS_MSK   0x00380000   /* Receive FCC2 Clock Source Mask */
-#define CMXFCR_TF2CS_MSK   0x00070000   /* Transmit FCC2 Clock Source Mask */
-#define CMXFCR_FC3         0x00004000   /* FCC3 connection              */
-#define CMXFCR_RF3CS_MSK   0x00003800   /* Receive FCC3 Clock Source Mask */
-#define CMXFCR_TF3CS_MSK   0x00000700   /* Transmit FCC3 Clock Source Mask */
-
-#define CMXFCR_RF1CS_BRG5  0x00000000   /* Receive FCC1 Clock Source is BRG5 */
-#define CMXFCR_RF1CS_BRG6  0x08000000   /* Receive FCC1 Clock Source is BRG6 */
-#define CMXFCR_RF1CS_BRG7  0x10000000   /* Receive FCC1 Clock Source is BRG7 */
-#define CMXFCR_RF1CS_BRG8  0x18000000   /* Receive FCC1 Clock Source is BRG8 */
-#define CMXFCR_RF1CS_CLK9  0x20000000   /* Receive FCC1 Clock Source is CLK9 */
-#define CMXFCR_RF1CS_CLK10 0x28000000   /* Receive FCC1 Clock Source is CLK10 */
-#define CMXFCR_RF1CS_CLK11 0x30000000   /* Receive FCC1 Clock Source is CLK11 */
-#define CMXFCR_RF1CS_CLK12 0x38000000   /* Receive FCC1 Clock Source is CLK12 */
-
-#define CMXFCR_TF1CS_BRG5  0x00000000   /* Transmit FCC1 Clock Source is BRG5 */
-#define CMXFCR_TF1CS_BRG6  0x01000000   /* Transmit FCC1 Clock Source is BRG6 */
-#define CMXFCR_TF1CS_BRG7  0x02000000   /* Transmit FCC1 Clock Source is BRG7 */
-#define CMXFCR_TF1CS_BRG8  0x03000000   /* Transmit FCC1 Clock Source is BRG8 */
-#define CMXFCR_TF1CS_CLK9  0x04000000   /* Transmit FCC1 Clock Source is CLK9 */
-#define CMXFCR_TF1CS_CLK10 0x05000000   /* Transmit FCC1 Clock Source is CLK10 */
-#define CMXFCR_TF1CS_CLK11 0x06000000   /* Transmit FCC1 Clock Source is CLK11 */
-#define CMXFCR_TF1CS_CLK12 0x07000000   /* Transmit FCC1 Clock Source is CLK12 */
-
-#define CMXFCR_RF2CS_BRG5  0x00000000   /* Receive FCC2 Clock Source is BRG5 */
-#define CMXFCR_RF2CS_BRG6  0x00080000   /* Receive FCC2 Clock Source is BRG6 */
-#define CMXFCR_RF2CS_BRG7  0x00100000   /* Receive FCC2 Clock Source is BRG7 */
-#define CMXFCR_RF2CS_BRG8  0x00180000   /* Receive FCC2 Clock Source is BRG8 */
-#define CMXFCR_RF2CS_CLK13 0x00200000   /* Receive FCC2 Clock Source is CLK13 */
-#define CMXFCR_RF2CS_CLK14 0x00280000   /* Receive FCC2 Clock Source is CLK14 */
-#define CMXFCR_RF2CS_CLK15 0x00300000   /* Receive FCC2 Clock Source is CLK15 */
-#define CMXFCR_RF2CS_CLK16 0x00380000   /* Receive FCC2 Clock Source is CLK16 */
-
-#define CMXFCR_TF2CS_BRG5  0x00000000   /* Transmit FCC2 Clock Source is BRG5 */
-#define CMXFCR_TF2CS_BRG6  0x00010000   /* Transmit FCC2 Clock Source is BRG6 */
-#define CMXFCR_TF2CS_BRG7  0x00020000   /* Transmit FCC2 Clock Source is BRG7 */
-#define CMXFCR_TF2CS_BRG8  0x00030000   /* Transmit FCC2 Clock Source is BRG8 */
-#define CMXFCR_TF2CS_CLK13 0x00040000   /* Transmit FCC2 Clock Source is CLK13 */
-#define CMXFCR_TF2CS_CLK14 0x00050000   /* Transmit FCC2 Clock Source is CLK14 */
-#define CMXFCR_TF2CS_CLK15 0x00060000   /* Transmit FCC2 Clock Source is CLK15 */
-#define CMXFCR_TF2CS_CLK16 0x00070000   /* Transmit FCC2 Clock Source is CLK16 */
-
-#define CMXFCR_RF3CS_BRG5  0x00000000   /* Receive FCC3 Clock Source is BRG5 */
-#define CMXFCR_RF3CS_BRG6  0x00000800   /* Receive FCC3 Clock Source is BRG6 */
-#define CMXFCR_RF3CS_BRG7  0x00001000   /* Receive FCC3 Clock Source is BRG7 */
-#define CMXFCR_RF3CS_BRG8  0x00001800   /* Receive FCC3 Clock Source is BRG8 */
-#define CMXFCR_RF3CS_CLK13 0x00002000   /* Receive FCC3 Clock Source is CLK13 */
-#define CMXFCR_RF3CS_CLK14 0x00002800   /* Receive FCC3 Clock Source is CLK14 */
-#define CMXFCR_RF3CS_CLK15 0x00003000   /* Receive FCC3 Clock Source is CLK15 */
-#define CMXFCR_RF3CS_CLK16 0x00003800   /* Receive FCC3 Clock Source is CLK16 */
-
-#define CMXFCR_TF3CS_BRG5  0x00000000   /* Transmit FCC3 Clock Source is BRG5 */
-#define CMXFCR_TF3CS_BRG6  0x00000100   /* Transmit FCC3 Clock Source is BRG6 */
-#define CMXFCR_TF3CS_BRG7  0x00000200   /* Transmit FCC3 Clock Source is BRG7 */
-#define CMXFCR_TF3CS_BRG8  0x00000300   /* Transmit FCC3 Clock Source is BRG8 */
-#define CMXFCR_TF3CS_CLK13 0x00000400   /* Transmit FCC3 Clock Source is CLK13 */
-#define CMXFCR_TF3CS_CLK14 0x00000500   /* Transmit FCC3 Clock Source is CLK14 */
-#define CMXFCR_TF3CS_CLK15 0x00000600   /* Transmit FCC3 Clock Source is CLK15 */
-#define CMXFCR_TF3CS_CLK16 0x00000700   /* Transmit FCC3 Clock Source is CLK16 */
-
-/*-----------------------------------------------------------------------
- * CMXSCR - CMX SCC Clock Route Register
- */
-#define CMXSCR_GR1         0x80000000   /* Grant Support of SCC1        */
-#define CMXSCR_SC1         0x40000000   /* SCC1 connection              */
-#define CMXSCR_RS1CS_MSK   0x38000000   /* Receive SCC1 Clock Source Mask */
-#define CMXSCR_TS1CS_MSK   0x07000000   /* Transmit SCC1 Clock Source Mask */
-#define CMXSCR_GR2         0x00800000   /* Grant Support of SCC2        */
-#define CMXSCR_SC2         0x00400000   /* SCC2 connection              */
-#define CMXSCR_RS2CS_MSK   0x00380000   /* Receive SCC2 Clock Source Mask */
-#define CMXSCR_TS2CS_MSK   0x00070000   /* Transmit SCC2 Clock Source Mask */
-#define CMXSCR_GR3         0x00008000   /* Grant Support of SCC3        */
-#define CMXSCR_SC3         0x00004000   /* SCC3 connection              */
-#define CMXSCR_RS3CS_MSK   0x00003800   /* Receive SCC3 Clock Source Mask */
-#define CMXSCR_TS3CS_MSK   0x00000700   /* Transmit SCC3 Clock Source Mask */
-#define CMXSCR_GR4         0x00000080   /* Grant Support of SCC4        */
-#define CMXSCR_SC4         0x00000040   /* SCC4 connection              */
-#define CMXSCR_RS4CS_MSK   0x00000038   /* Receive SCC4 Clock Source Mask */
-#define CMXSCR_TS4CS_MSK   0x00000007   /* Transmit SCC4 Clock Source Mask */
-
-#define CMXSCR_RS1CS_BRG1  0x00000000   /* SCC1 Rx Clock Source is BRG1 */
-#define CMXSCR_RS1CS_BRG2  0x08000000   /* SCC1 Rx Clock Source is BRG2 */
-#define CMXSCR_RS1CS_BRG3  0x10000000   /* SCC1 Rx Clock Source is BRG3 */
-#define CMXSCR_RS1CS_BRG4  0x18000000   /* SCC1 Rx Clock Source is BRG4 */
-#define CMXSCR_RS1CS_CLK11 0x20000000   /* SCC1 Rx Clock Source is CLK11 */
-#define CMXSCR_RS1CS_CLK12 0x28000000   /* SCC1 Rx Clock Source is CLK12 */
-#define CMXSCR_RS1CS_CLK3  0x30000000   /* SCC1 Rx Clock Source is CLK3 */
-#define CMXSCR_RS1CS_CLK4  0x38000000   /* SCC1 Rx Clock Source is CLK4 */
-
-#define CMXSCR_TS1CS_BRG1  0x00000000   /* SCC1 Tx Clock Source is BRG1 */
-#define CMXSCR_TS1CS_BRG2  0x01000000   /* SCC1 Tx Clock Source is BRG2 */
-#define CMXSCR_TS1CS_BRG3  0x02000000   /* SCC1 Tx Clock Source is BRG3 */
-#define CMXSCR_TS1CS_BRG4  0x03000000   /* SCC1 Tx Clock Source is BRG4 */
-#define CMXSCR_TS1CS_CLK11 0x04000000   /* SCC1 Tx Clock Source is CLK11 */
-#define CMXSCR_TS1CS_CLK12 0x05000000   /* SCC1 Tx Clock Source is CLK12 */
-#define CMXSCR_TS1CS_CLK3  0x06000000   /* SCC1 Tx Clock Source is CLK3 */
-#define CMXSCR_TS1CS_CLK4  0x07000000   /* SCC1 Tx Clock Source is CLK4 */
-
-#define CMXSCR_RS2CS_BRG1  0x00000000   /* SCC2 Rx Clock Source is BRG1 */
-#define CMXSCR_RS2CS_BRG2  0x00080000   /* SCC2 Rx Clock Source is BRG2 */
-#define CMXSCR_RS2CS_BRG3  0x00100000   /* SCC2 Rx Clock Source is BRG3 */
-#define CMXSCR_RS2CS_BRG4  0x00180000   /* SCC2 Rx Clock Source is BRG4 */
-#define CMXSCR_RS2CS_CLK11 0x00200000   /* SCC2 Rx Clock Source is CLK11 */
-#define CMXSCR_RS2CS_CLK12 0x00280000   /* SCC2 Rx Clock Source is CLK12 */
-#define CMXSCR_RS2CS_CLK3  0x00300000   /* SCC2 Rx Clock Source is CLK3 */
-#define CMXSCR_RS2CS_CLK4  0x00380000   /* SCC2 Rx Clock Source is CLK4 */
-
-#define CMXSCR_TS2CS_BRG1  0x00000000   /* SCC2 Tx Clock Source is BRG1 */
-#define CMXSCR_TS2CS_BRG2  0x00010000   /* SCC2 Tx Clock Source is BRG2 */
-#define CMXSCR_TS2CS_BRG3  0x00020000   /* SCC2 Tx Clock Source is BRG3 */
-#define CMXSCR_TS2CS_BRG4  0x00030000   /* SCC2 Tx Clock Source is BRG4 */
-#define CMXSCR_TS2CS_CLK11 0x00040000   /* SCC2 Tx Clock Source is CLK11 */
-#define CMXSCR_TS2CS_CLK12 0x00050000   /* SCC2 Tx Clock Source is CLK12 */
-#define CMXSCR_TS2CS_CLK3  0x00060000   /* SCC2 Tx Clock Source is CLK3 */
-#define CMXSCR_TS2CS_CLK4  0x00070000   /* SCC2 Tx Clock Source is CLK4 */
-
-#define CMXSCR_RS3CS_BRG1  0x00000000   /* SCC3 Rx Clock Source is BRG1 */
-#define CMXSCR_RS3CS_BRG2  0x00000800   /* SCC3 Rx Clock Source is BRG2 */
-#define CMXSCR_RS3CS_BRG3  0x00001000   /* SCC3 Rx Clock Source is BRG3 */
-#define CMXSCR_RS3CS_BRG4  0x00001800   /* SCC3 Rx Clock Source is BRG4 */
-#define CMXSCR_RS3CS_CLK5  0x00002000   /* SCC3 Rx Clock Source is CLK5 */
-#define CMXSCR_RS3CS_CLK6  0x00002800   /* SCC3 Rx Clock Source is CLK6 */
-#define CMXSCR_RS3CS_CLK7  0x00003000   /* SCC3 Rx Clock Source is CLK7 */
-#define CMXSCR_RS3CS_CLK8  0x00003800   /* SCC3 Rx Clock Source is CLK8 */
-
-#define CMXSCR_TS3CS_BRG1  0x00000000   /* SCC3 Tx Clock Source is BRG1 */
-#define CMXSCR_TS3CS_BRG2  0x00000100   /* SCC3 Tx Clock Source is BRG2 */
-#define CMXSCR_TS3CS_BRG3  0x00000200   /* SCC3 Tx Clock Source is BRG3 */
-#define CMXSCR_TS3CS_BRG4  0x00000300   /* SCC3 Tx Clock Source is BRG4 */
-#define CMXSCR_TS3CS_CLK5  0x00000400   /* SCC3 Tx Clock Source is CLK5 */
-#define CMXSCR_TS3CS_CLK6  0x00000500   /* SCC3 Tx Clock Source is CLK6 */
-#define CMXSCR_TS3CS_CLK7  0x00000600   /* SCC3 Tx Clock Source is CLK7 */
-#define CMXSCR_TS3CS_CLK8  0x00000700   /* SCC3 Tx Clock Source is CLK8 */
-
-#define CMXSCR_RS4CS_BRG1  0x00000000   /* SCC4 Rx Clock Source is BRG1 */
-#define CMXSCR_RS4CS_BRG2  0x00000008   /* SCC4 Rx Clock Source is BRG2 */
-#define CMXSCR_RS4CS_BRG3  0x00000010   /* SCC4 Rx Clock Source is BRG3 */
-#define CMXSCR_RS4CS_BRG4  0x00000018   /* SCC4 Rx Clock Source is BRG4 */
-#define CMXSCR_RS4CS_CLK5  0x00000020   /* SCC4 Rx Clock Source is CLK5 */
-#define CMXSCR_RS4CS_CLK6  0x00000028   /* SCC4 Rx Clock Source is CLK6 */
-#define CMXSCR_RS4CS_CLK7  0x00000030   /* SCC4 Rx Clock Source is CLK7 */
-#define CMXSCR_RS4CS_CLK8  0x00000038   /* SCC4 Rx Clock Source is CLK8 */
-
-#define CMXSCR_TS4CS_BRG1  0x00000000   /* SCC4 Tx Clock Source is BRG1 */
-#define CMXSCR_TS4CS_BRG2  0x00000001   /* SCC4 Tx Clock Source is BRG2 */
-#define CMXSCR_TS4CS_BRG3  0x00000002   /* SCC4 Tx Clock Source is BRG3 */
-#define CMXSCR_TS4CS_BRG4  0x00000003   /* SCC4 Tx Clock Source is BRG4 */
-#define CMXSCR_TS4CS_CLK5  0x00000004   /* SCC4 Tx Clock Source is CLK5 */
-#define CMXSCR_TS4CS_CLK6  0x00000005   /* SCC4 Tx Clock Source is CLK6 */
-#define CMXSCR_TS4CS_CLK7  0x00000006   /* SCC4 Tx Clock Source is CLK7 */
-#define CMXSCR_TS4CS_CLK8  0x00000007   /* SCC4 Tx Clock Source is CLK8 */
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration Register				 4-31
- */
-#define SIUMCR_BBD	0x80000000	/* Bus Busy Disable		*/
-#define SIUMCR_ESE	0x40000000	/* External Snoop Enable	*/
-#define SIUMCR_PBSE	0x20000000	/* Parity Byte Select Enable	*/
-#define SIUMCR_CDIS	0x10000000	/* Core Disable			*/
-#define SIUMCR_DPPC00	0x00000000	/* Data Parity Pins Configuration*/
-#define SIUMCR_DPPC01	0x04000000	/* - " -			*/
-#define SIUMCR_DPPC10	0x08000000	/* - " -			*/
-#define SIUMCR_DPPC11	0x0c000000	/* - " -			*/
-#define SIUMCR_L2CPC00	0x00000000	/* L2 Cache Pins Configuration	*/
-#define SIUMCR_L2CPC01	0x01000000	/* - " -			*/
-#define SIUMCR_L2CPC10	0x02000000	/* - " -			*/
-#define SIUMCR_L2CPC11	0x03000000	/* - " -			*/
-#define SIUMCR_LBPC00	0x00000000	/* Local Bus Pins Configuration	*/
-#define SIUMCR_LBPC01	0x00400000	/* - " -			*/
-#define SIUMCR_LBPC10	0x00800000	/* - " -			*/
-#define SIUMCR_LBPC11	0x00c00000	/* - " -			*/
-#define SIUMCR_APPC00	0x00000000	/* Address Parity Pins Configuration*/
-#define SIUMCR_APPC01	0x00100000	/* - " -			*/
-#define SIUMCR_APPC10	0x00200000	/* - " -			*/
-#define SIUMCR_APPC11	0x00300000	/* - " -			*/
-#define SIUMCR_CS10PC00	0x00000000	/* CS10 Pin Configuration	*/
-#define SIUMCR_CS10PC01	0x00040000	/* - " -			*/
-#define SIUMCR_CS10PC10	0x00080000	/* - " -			*/
-#define SIUMCR_CS10PC11	0x000c0000	/* - " -			*/
-#define SIUMCR_BCTLC00	0x00000000	/* Buffer Control Configuration	*/
-#define SIUMCR_BCTLC01	0x00010000	/* - " -			*/
-#define SIUMCR_BCTLC10	0x00020000	/* - " -			*/
-#define SIUMCR_BCTLC11	0x00030000	/* - " -			*/
-#define SIUMCR_MMR00	0x00000000	/* Mask Masters Requests	*/
-#define SIUMCR_MMR01	0x00004000	/* - " -			*/
-#define SIUMCR_MMR10	0x00008000	/* - " -			*/
-#define SIUMCR_MMR11	0x0000c000	/* - " -			*/
-#define SIUMCR_LPBSE	0x00002000	/* LocalBus Parity Byte Select Enable*/
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control Register					 9-8
-*/
-#define SCCR_PCI_MODE	0x00000100	/* PCI Mode	*/
-#define SCCR_PCI_MODCK	0x00000080	/* Value of PCI_MODCK pin	*/
-#define SCCR_PCIDF_MSK	0x00000078	/* PCI division factor	*/
-#define SCCR_PCIDF_SHIFT 3
-
-#ifndef CPM_IMMR_OFFSET
-#define CPM_IMMR_OFFSET	0x101a8
-#endif
-
-#define FCC_PSMR_RMII	((uint)0x00020000)	/* Use RMII interface */
-
-/* FCC iop & clock configuration. BSP code is responsible to define Fx_RXCLK & Fx_TXCLK
- * in order to use clock-computing stuff below for the FCC x
- */
-
-/* Automatically generates register configurations */
-#define PC_CLK(x)	((uint)(1<<(x-1)))	/* FCC CLK I/O ports */
-
-#define CMXFCR_RF1CS(x)	((uint)((x-5)<<27))	/* FCC1 Receive Clock Source */
-#define CMXFCR_TF1CS(x)	((uint)((x-5)<<24))	/* FCC1 Transmit Clock Source */
-#define CMXFCR_RF2CS(x)	((uint)((x-9)<<19))	/* FCC2 Receive Clock Source */
-#define CMXFCR_TF2CS(x) ((uint)((x-9)<<16))	/* FCC2 Transmit Clock Source */
-#define CMXFCR_RF3CS(x)	((uint)((x-9)<<11))	/* FCC3 Receive Clock Source */
-#define CMXFCR_TF3CS(x) ((uint)((x-9)<<8))	/* FCC3 Transmit Clock Source */
-
-#define PC_F1RXCLK	PC_CLK(F1_RXCLK)
-#define PC_F1TXCLK	PC_CLK(F1_TXCLK)
-#define CMX1_CLK_ROUTE	(CMXFCR_RF1CS(F1_RXCLK) | CMXFCR_TF1CS(F1_TXCLK))
-#define CMX1_CLK_MASK	((uint)0xff000000)
-
-#define PC_F2RXCLK	PC_CLK(F2_RXCLK)
-#define PC_F2TXCLK	PC_CLK(F2_TXCLK)
-#define CMX2_CLK_ROUTE	(CMXFCR_RF2CS(F2_RXCLK) | CMXFCR_TF2CS(F2_TXCLK))
-#define CMX2_CLK_MASK	((uint)0x00ff0000)
-
-#define PC_F3RXCLK	PC_CLK(F3_RXCLK)
-#define PC_F3TXCLK	PC_CLK(F3_TXCLK)
-#define CMX3_CLK_ROUTE	(CMXFCR_RF3CS(F3_RXCLK) | CMXFCR_TF3CS(F3_TXCLK))
-#define CMX3_CLK_MASK	((uint)0x0000ff00)
-
-#define CPMUX_CLK_MASK (CMX3_CLK_MASK | CMX2_CLK_MASK)
-#define CPMUX_CLK_ROUTE (CMX3_CLK_ROUTE | CMX2_CLK_ROUTE)
-
-#define CLK_TRX (PC_F3TXCLK | PC_F3RXCLK | PC_F2TXCLK | PC_F2RXCLK)
-
-/* I/O Pin assignment for FCC1.  I don't yet know the best way to do this,
- * but there is little variation among the choices.
- */
-#define PA1_COL		0x00000001U
-#define PA1_CRS		0x00000002U
-#define PA1_TXER	0x00000004U
-#define PA1_TXEN	0x00000008U
-#define PA1_RXDV	0x00000010U
-#define PA1_RXER	0x00000020U
-#define PA1_TXDAT	0x00003c00U
-#define PA1_RXDAT	0x0003c000U
-#define PA1_PSORA0	(PA1_RXDAT | PA1_TXDAT)
-#define PA1_PSORA1	(PA1_COL | PA1_CRS | PA1_TXER | PA1_TXEN | \
-		PA1_RXDV | PA1_RXER)
-#define PA1_DIRA0	(PA1_RXDAT | PA1_CRS | PA1_COL | PA1_RXER | PA1_RXDV)
-#define PA1_DIRA1	(PA1_TXDAT | PA1_TXEN | PA1_TXER)
-
-
-/* I/O Pin assignment for FCC2.  I don't yet know the best way to do this,
- * but there is little variation among the choices.
- */
-#define PB2_TXER	0x00000001U
-#define PB2_RXDV	0x00000002U
-#define PB2_TXEN	0x00000004U
-#define PB2_RXER	0x00000008U
-#define PB2_COL		0x00000010U
-#define PB2_CRS		0x00000020U
-#define PB2_TXDAT	0x000003c0U
-#define PB2_RXDAT	0x00003c00U
-#define PB2_PSORB0	(PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \
-		PB2_RXER | PB2_RXDV | PB2_TXER)
-#define PB2_PSORB1	(PB2_TXEN)
-#define PB2_DIRB0	(PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV)
-#define PB2_DIRB1	(PB2_TXDAT | PB2_TXEN | PB2_TXER)
-
-
-/* I/O Pin assignment for FCC3.  I don't yet know the best way to do this,
- * but there is little variation among the choices.
- */
-#define PB3_RXDV	0x00004000U
-#define PB3_RXER	0x00008000U
-#define PB3_TXER	0x00010000U
-#define PB3_TXEN	0x00020000U
-#define PB3_COL		0x00040000U
-#define PB3_CRS		0x00080000U
-#define PB3_TXDAT	0x0f000000U
-#define PC3_TXDAT	0x00000010U
-#define PB3_RXDAT	0x00f00000U
-#define PB3_PSORB0	(PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \
-		PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN)
-#define PB3_PSORB1	0
-#define PB3_DIRB0	(PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV)
-#define PB3_DIRB1	(PB3_TXDAT | PB3_TXEN | PB3_TXER)
-#define PC3_DIRC1	(PC3_TXDAT)
-
-/* Handy macro to specify mem for FCCs*/
-#define FCC_MEM_OFFSET(x) (CPM_FCC_SPECIAL_BASE + (x*128))
-#define FCC1_MEM_OFFSET FCC_MEM_OFFSET(0)
-#define FCC2_MEM_OFFSET FCC_MEM_OFFSET(1)
-#define FCC3_MEM_OFFSET FCC_MEM_OFFSET(2)
-
-/* Clocks and GRG's */
-
-enum cpm_clk_dir {
-	CPM_CLK_RX,
-	CPM_CLK_TX,
-	CPM_CLK_RTX
-};
-
-enum cpm_clk_target {
-	CPM_CLK_SCC1,
-	CPM_CLK_SCC2,
-	CPM_CLK_SCC3,
-	CPM_CLK_SCC4,
-	CPM_CLK_FCC1,
-	CPM_CLK_FCC2,
-	CPM_CLK_FCC3,
-	CPM_CLK_SMC1,
-	CPM_CLK_SMC2,
-};
-
-enum cpm_clk {
-	CPM_CLK_NONE = 0,
-	CPM_BRG1,	/* Baud Rate Generator  1 */
-	CPM_BRG2,	/* Baud Rate Generator  2 */
-	CPM_BRG3,	/* Baud Rate Generator  3 */
-	CPM_BRG4,	/* Baud Rate Generator  4 */
-	CPM_BRG5,	/* Baud Rate Generator  5 */
-	CPM_BRG6,	/* Baud Rate Generator  6 */
-	CPM_BRG7,	/* Baud Rate Generator  7 */
-	CPM_BRG8,	/* Baud Rate Generator  8 */
-	CPM_CLK1,	/* Clock  1 */
-	CPM_CLK2,	/* Clock  2 */
-	CPM_CLK3,	/* Clock  3 */
-	CPM_CLK4,	/* Clock  4 */
-	CPM_CLK5,	/* Clock  5 */
-	CPM_CLK6,	/* Clock  6 */
-	CPM_CLK7,	/* Clock  7 */
-	CPM_CLK8,	/* Clock  8 */
-	CPM_CLK9,	/* Clock  9 */
-	CPM_CLK10,	/* Clock 10 */
-	CPM_CLK11,	/* Clock 11 */
-	CPM_CLK12,	/* Clock 12 */
-	CPM_CLK13,	/* Clock 13 */
-	CPM_CLK14,	/* Clock 14 */
-	CPM_CLK15,	/* Clock 15 */
-	CPM_CLK16,	/* Clock 16 */
-	CPM_CLK17,	/* Clock 17 */
-	CPM_CLK18,	/* Clock 18 */
-	CPM_CLK19,	/* Clock 19 */
-	CPM_CLK20,	/* Clock 20 */
-	CPM_CLK_DUMMY
-};
-
-extern int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode);
-extern int cpm2_smc_clk_setup(enum cpm_clk_target target, int clock);
-
-#define CPM_PIN_INPUT     0
-#define CPM_PIN_OUTPUT    1
-#define CPM_PIN_PRIMARY   0
-#define CPM_PIN_SECONDARY 2
-#define CPM_PIN_GPIO      4
-#define CPM_PIN_OPENDRAIN 8
-
-void cpm2_set_pin(int port, int pin, int flags);
-
-#endif /* __CPM2__ */
-#endif /* __KERNEL__ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/cputable.h b/ANDROID_3.4.5/arch/powerpc/include/asm/cputable.h
deleted file mode 100644
index b9219e99..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/cputable.h
+++ /dev/null
@@ -1,556 +0,0 @@
-#ifndef __ASM_POWERPC_CPUTABLE_H
-#define __ASM_POWERPC_CPUTABLE_H
-
-#define PPC_FEATURE_32			0x80000000
-#define PPC_FEATURE_64			0x40000000
-#define PPC_FEATURE_601_INSTR		0x20000000
-#define PPC_FEATURE_HAS_ALTIVEC		0x10000000
-#define PPC_FEATURE_HAS_FPU		0x08000000
-#define PPC_FEATURE_HAS_MMU		0x04000000
-#define PPC_FEATURE_HAS_4xxMAC		0x02000000
-#define PPC_FEATURE_UNIFIED_CACHE	0x01000000
-#define PPC_FEATURE_HAS_SPE		0x00800000
-#define PPC_FEATURE_HAS_EFP_SINGLE	0x00400000
-#define PPC_FEATURE_HAS_EFP_DOUBLE	0x00200000
-#define PPC_FEATURE_NO_TB		0x00100000
-#define PPC_FEATURE_POWER4		0x00080000
-#define PPC_FEATURE_POWER5		0x00040000
-#define PPC_FEATURE_POWER5_PLUS		0x00020000
-#define PPC_FEATURE_CELL		0x00010000
-#define PPC_FEATURE_BOOKE		0x00008000
-#define PPC_FEATURE_SMT			0x00004000
-#define PPC_FEATURE_ICACHE_SNOOP	0x00002000
-#define PPC_FEATURE_ARCH_2_05		0x00001000
-#define PPC_FEATURE_PA6T		0x00000800
-#define PPC_FEATURE_HAS_DFP		0x00000400
-#define PPC_FEATURE_POWER6_EXT		0x00000200
-#define PPC_FEATURE_ARCH_2_06		0x00000100
-#define PPC_FEATURE_HAS_VSX		0x00000080
-
-#define PPC_FEATURE_PSERIES_PERFMON_COMPAT \
-					0x00000040
-
-#define PPC_FEATURE_TRUE_LE		0x00000002
-#define PPC_FEATURE_PPC_LE		0x00000001
-
-#ifdef __KERNEL__
-
-#include <asm/asm-compat.h>
-#include <asm/feature-fixups.h>
-
-#ifndef __ASSEMBLY__
-
-/* This structure can grow, it's real size is used by head.S code
- * via the mkdefs mechanism.
- */
-struct cpu_spec;
-
-typedef	void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
-typedef	void (*cpu_restore_t)(void);
-
-enum powerpc_oprofile_type {
-	PPC_OPROFILE_INVALID = 0,
-	PPC_OPROFILE_RS64 = 1,
-	PPC_OPROFILE_POWER4 = 2,
-	PPC_OPROFILE_G4 = 3,
-	PPC_OPROFILE_FSL_EMB = 4,
-	PPC_OPROFILE_CELL = 5,
-	PPC_OPROFILE_PA6T = 6,
-};
-
-enum powerpc_pmc_type {
-	PPC_PMC_DEFAULT = 0,
-	PPC_PMC_IBM = 1,
-	PPC_PMC_PA6T = 2,
-	PPC_PMC_G4 = 3,
-};
-
-struct pt_regs;
-
-extern int machine_check_generic(struct pt_regs *regs);
-extern int machine_check_4xx(struct pt_regs *regs);
-extern int machine_check_440A(struct pt_regs *regs);
-extern int machine_check_e500mc(struct pt_regs *regs);
-extern int machine_check_e500(struct pt_regs *regs);
-extern int machine_check_e200(struct pt_regs *regs);
-extern int machine_check_47x(struct pt_regs *regs);
-
-/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
-struct cpu_spec {
-	/* CPU is matched via (PVR & pvr_mask) == pvr_value */
-	unsigned int	pvr_mask;
-	unsigned int	pvr_value;
-
-	char		*cpu_name;
-	unsigned long	cpu_features;		/* Kernel features */
-	unsigned int	cpu_user_features;	/* Userland features */
-	unsigned int	mmu_features;		/* MMU features */
-
-	/* cache line sizes */
-	unsigned int	icache_bsize;
-	unsigned int	dcache_bsize;
-
-	/* number of performance monitor counters */
-	unsigned int	num_pmcs;
-	enum powerpc_pmc_type pmc_type;
-
-	/* this is called to initialize various CPU bits like L1 cache,
-	 * BHT, SPD, etc... from head.S before branching to identify_machine
-	 */
-	cpu_setup_t	cpu_setup;
-	/* Used to restore cpu setup on secondary processors and at resume */
-	cpu_restore_t	cpu_restore;
-
-	/* Used by oprofile userspace to select the right counters */
-	char		*oprofile_cpu_type;
-
-	/* Processor specific oprofile operations */
-	enum powerpc_oprofile_type oprofile_type;
-
-	/* Bit locations inside the mmcra change */
-	unsigned long	oprofile_mmcra_sihv;
-	unsigned long	oprofile_mmcra_sipr;
-
-	/* Bits to clear during an oprofile exception */
-	unsigned long	oprofile_mmcra_clear;
-
-	/* Name of processor class, for the ELF AT_PLATFORM entry */
-	char		*platform;
-
-	/* Processor specific machine check handling. Return negative
-	 * if the error is fatal, 1 if it was fully recovered and 0 to
-	 * pass up (not CPU originated) */
-	int		(*machine_check)(struct pt_regs *regs);
-};
-
-extern struct cpu_spec		*cur_cpu_spec;
-
-extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
-
-extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
-extern void do_feature_fixups(unsigned long value, void *fixup_start,
-			      void *fixup_end);
-
-extern const char *powerpc_base_platform;
-
-#endif /* __ASSEMBLY__ */
-
-/* CPU kernel features */
-
-/* Retain the 32b definitions all use bottom half of word */
-#define CPU_FTR_COHERENT_ICACHE		ASM_CONST(0x0000000000000001)
-#define CPU_FTR_L2CR			ASM_CONST(0x0000000000000002)
-#define CPU_FTR_SPEC7450		ASM_CONST(0x0000000000000004)
-#define CPU_FTR_ALTIVEC			ASM_CONST(0x0000000000000008)
-#define CPU_FTR_TAU			ASM_CONST(0x0000000000000010)
-#define CPU_FTR_CAN_DOZE		ASM_CONST(0x0000000000000020)
-#define CPU_FTR_USE_TB			ASM_CONST(0x0000000000000040)
-#define CPU_FTR_L2CSR			ASM_CONST(0x0000000000000080)
-#define CPU_FTR_601			ASM_CONST(0x0000000000000100)
-#define CPU_FTR_DBELL			ASM_CONST(0x0000000000000200)
-#define CPU_FTR_CAN_NAP			ASM_CONST(0x0000000000000400)
-#define CPU_FTR_L3CR			ASM_CONST(0x0000000000000800)
-#define CPU_FTR_L3_DISABLE_NAP		ASM_CONST(0x0000000000001000)
-#define CPU_FTR_NAP_DISABLE_L2_PR	ASM_CONST(0x0000000000002000)
-#define CPU_FTR_DUAL_PLL_750FX		ASM_CONST(0x0000000000004000)
-#define CPU_FTR_NO_DPM			ASM_CONST(0x0000000000008000)
-#define CPU_FTR_476_DD2			ASM_CONST(0x0000000000010000)
-#define CPU_FTR_NEED_COHERENT		ASM_CONST(0x0000000000020000)
-#define CPU_FTR_NO_BTIC			ASM_CONST(0x0000000000040000)
-#define CPU_FTR_DEBUG_LVL_EXC		ASM_CONST(0x0000000000080000)
-#define CPU_FTR_NODSISRALIGN		ASM_CONST(0x0000000000100000)
-#define CPU_FTR_PPC_LE			ASM_CONST(0x0000000000200000)
-#define CPU_FTR_REAL_LE			ASM_CONST(0x0000000000400000)
-#define CPU_FTR_FPU_UNAVAILABLE		ASM_CONST(0x0000000000800000)
-#define CPU_FTR_UNIFIED_ID_CACHE	ASM_CONST(0x0000000001000000)
-#define CPU_FTR_SPE			ASM_CONST(0x0000000002000000)
-#define CPU_FTR_NEED_PAIRED_STWCX	ASM_CONST(0x0000000004000000)
-#define CPU_FTR_LWSYNC			ASM_CONST(0x0000000008000000)
-#define CPU_FTR_NOEXECUTE		ASM_CONST(0x0000000010000000)
-#define CPU_FTR_INDEXED_DCR		ASM_CONST(0x0000000020000000)
-
-/*
- * Add the 64-bit processor unique features in the top half of the word;
- * on 32-bit, make the names available but defined to be 0.
- */
-#ifdef __powerpc64__
-#define LONG_ASM_CONST(x)		ASM_CONST(x)
-#else
-#define LONG_ASM_CONST(x)		0
-#endif
-
-#define CPU_FTR_HVMODE			LONG_ASM_CONST(0x0000000200000000)
-#define CPU_FTR_ARCH_201		LONG_ASM_CONST(0x0000000400000000)
-#define CPU_FTR_ARCH_206		LONG_ASM_CONST(0x0000000800000000)
-#define CPU_FTR_CFAR			LONG_ASM_CONST(0x0000001000000000)
-#define CPU_FTR_IABR			LONG_ASM_CONST(0x0000002000000000)
-#define CPU_FTR_MMCRA			LONG_ASM_CONST(0x0000004000000000)
-#define CPU_FTR_CTRL			LONG_ASM_CONST(0x0000008000000000)
-#define CPU_FTR_SMT			LONG_ASM_CONST(0x0000010000000000)
-#define CPU_FTR_PAUSE_ZERO		LONG_ASM_CONST(0x0000200000000000)
-#define CPU_FTR_PURR			LONG_ASM_CONST(0x0000400000000000)
-#define CPU_FTR_CELL_TB_BUG		LONG_ASM_CONST(0x0000800000000000)
-#define CPU_FTR_SPURR			LONG_ASM_CONST(0x0001000000000000)
-#define CPU_FTR_DSCR			LONG_ASM_CONST(0x0002000000000000)
-#define CPU_FTR_VSX			LONG_ASM_CONST(0x0010000000000000)
-#define CPU_FTR_SAO			LONG_ASM_CONST(0x0020000000000000)
-#define CPU_FTR_CP_USE_DCBTZ		LONG_ASM_CONST(0x0040000000000000)
-#define CPU_FTR_UNALIGNED_LD_STD	LONG_ASM_CONST(0x0080000000000000)
-#define CPU_FTR_ASYM_SMT		LONG_ASM_CONST(0x0100000000000000)
-#define CPU_FTR_STCX_CHECKS_ADDRESS	LONG_ASM_CONST(0x0200000000000000)
-#define CPU_FTR_POPCNTB			LONG_ASM_CONST(0x0400000000000000)
-#define CPU_FTR_POPCNTD			LONG_ASM_CONST(0x0800000000000000)
-#define CPU_FTR_ICSWX			LONG_ASM_CONST(0x1000000000000000)
-#define CPU_FTR_VMX_COPY		LONG_ASM_CONST(0x2000000000000000)
-
-#ifndef __ASSEMBLY__
-
-#define CPU_FTR_PPCAS_ARCH_V2	(CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
-
-#define MMU_FTR_PPCAS_ARCH_V2 	(MMU_FTR_SLB | MMU_FTR_TLBIEL | \
-				 MMU_FTR_16M_PAGE)
-
-/* We only set the altivec features if the kernel was compiled with altivec
- * support
- */
-#ifdef CONFIG_ALTIVEC
-#define CPU_FTR_ALTIVEC_COMP	CPU_FTR_ALTIVEC
-#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
-#else
-#define CPU_FTR_ALTIVEC_COMP	0
-#define PPC_FEATURE_HAS_ALTIVEC_COMP    0
-#endif
-
-/* We only set the VSX features if the kernel was compiled with VSX
- * support
- */
-#ifdef CONFIG_VSX
-#define CPU_FTR_VSX_COMP	CPU_FTR_VSX
-#define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
-#else
-#define CPU_FTR_VSX_COMP	0
-#define PPC_FEATURE_HAS_VSX_COMP    0
-#endif
-
-/* We only set the spe features if the kernel was compiled with spe
- * support
- */
-#ifdef CONFIG_SPE
-#define CPU_FTR_SPE_COMP	CPU_FTR_SPE
-#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
-#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
-#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
-#else
-#define CPU_FTR_SPE_COMP	0
-#define PPC_FEATURE_HAS_SPE_COMP    0
-#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
-#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
-#endif
-
-/* We need to mark all pages as being coherent if we're SMP or we have a
- * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
- * require it for PCI "streaming/prefetch" to work properly.
- * This is also required by 52xx family.
- */
-#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
-	|| defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \
-	|| defined(CONFIG_PPC_MPC52xx)
-#define CPU_FTR_COMMON                  CPU_FTR_NEED_COHERENT
-#else
-#define CPU_FTR_COMMON                  0
-#endif
-
-/* The powersave features NAP & DOZE seems to confuse BDI when
-   debugging. So if a BDI is used, disable theses
- */
-#ifndef CONFIG_BDI_SWITCH
-#define CPU_FTR_MAYBE_CAN_DOZE	CPU_FTR_CAN_DOZE
-#define CPU_FTR_MAYBE_CAN_NAP	CPU_FTR_CAN_NAP
-#else
-#define CPU_FTR_MAYBE_CAN_DOZE	0
-#define CPU_FTR_MAYBE_CAN_NAP	0
-#endif
-
-#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
-		     !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
-		     !defined(CONFIG_BOOKE))
-
-#define CPU_FTRS_PPC601	(CPU_FTR_COMMON | CPU_FTR_601 | \
-	CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
-#define CPU_FTRS_603	(CPU_FTR_COMMON | \
-	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
-	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
-#define CPU_FTRS_604	(CPU_FTR_COMMON | \
-	    CPU_FTR_USE_TB | CPU_FTR_PPC_LE)
-#define CPU_FTRS_740_NOTAU	(CPU_FTR_COMMON | \
-	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
-	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
-#define CPU_FTRS_740	(CPU_FTR_COMMON | \
-	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
-	    CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
-	    CPU_FTR_PPC_LE)
-#define CPU_FTRS_750	(CPU_FTR_COMMON | \
-	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
-	    CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
-	    CPU_FTR_PPC_LE)
-#define CPU_FTRS_750CL	(CPU_FTRS_750)
-#define CPU_FTRS_750FX1	(CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
-#define CPU_FTRS_750FX2	(CPU_FTRS_750 | CPU_FTR_NO_DPM)
-#define CPU_FTRS_750FX	(CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX)
-#define CPU_FTRS_750GX	(CPU_FTRS_750FX)
-#define CPU_FTRS_7400_NOTAU	(CPU_FTR_COMMON | \
-	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
-	    CPU_FTR_ALTIVEC_COMP | \
-	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
-#define CPU_FTRS_7400	(CPU_FTR_COMMON | \
-	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
-	    CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \
-	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
-#define CPU_FTRS_7450_20	(CPU_FTR_COMMON | \
-	    CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
-	    CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
-	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
-#define CPU_FTRS_7450_21	(CPU_FTR_COMMON | \
-	    CPU_FTR_USE_TB | \
-	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
-	    CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
-	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
-	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
-#define CPU_FTRS_7450_23	(CPU_FTR_COMMON | \
-	    CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
-	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
-	    CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
-	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
-#define CPU_FTRS_7455_1	(CPU_FTR_COMMON | \
-	    CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
-	    CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
-	    CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
-#define CPU_FTRS_7455_20	(CPU_FTR_COMMON | \
-	    CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
-	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
-	    CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
-	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
-	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
-#define CPU_FTRS_7455	(CPU_FTR_COMMON | \
-	    CPU_FTR_USE_TB | \
-	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
-	    CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
-	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
-#define CPU_FTRS_7447_10	(CPU_FTR_COMMON | \
-	    CPU_FTR_USE_TB | \
-	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
-	    CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
-	    CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
-	    CPU_FTR_NEED_PAIRED_STWCX)
-#define CPU_FTRS_7447	(CPU_FTR_COMMON | \
-	    CPU_FTR_USE_TB | \
-	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
-	    CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
-	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
-#define CPU_FTRS_7447A	(CPU_FTR_COMMON | \
-	    CPU_FTR_USE_TB | \
-	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
-	    CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
-	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
-#define CPU_FTRS_7448	(CPU_FTR_COMMON | \
-	    CPU_FTR_USE_TB | \
-	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
-	    CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
-	    CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
-#define CPU_FTRS_82XX	(CPU_FTR_COMMON | \
-	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
-#define CPU_FTRS_G2_LE	(CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
-	    CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP)
-#define CPU_FTRS_E300	(CPU_FTR_MAYBE_CAN_DOZE | \
-	    CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
-	    CPU_FTR_COMMON)
-#define CPU_FTRS_E300C2	(CPU_FTR_MAYBE_CAN_DOZE | \
-	    CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
-	    CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
-#define CPU_FTRS_CLASSIC32	(CPU_FTR_COMMON | CPU_FTR_USE_TB)
-#define CPU_FTRS_8XX	(CPU_FTR_USE_TB)
-#define CPU_FTRS_40X	(CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
-#define CPU_FTRS_44X	(CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
-#define CPU_FTRS_440x6	(CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \
-	    CPU_FTR_INDEXED_DCR)
-#define CPU_FTRS_47X	(CPU_FTRS_440x6)
-#define CPU_FTRS_E200	(CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
-	    CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
-	    CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE)
-#define CPU_FTRS_E500	(CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
-	    CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
-	    CPU_FTR_NOEXECUTE)
-#define CPU_FTRS_E500_2	(CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
-	    CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
-	    CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
-#define CPU_FTRS_E500MC	(CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
-	    CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
-	    CPU_FTR_DBELL)
-#define CPU_FTRS_E5500	(CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
-	    CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
-	    CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
-	    CPU_FTR_DEBUG_LVL_EXC)
-#define CPU_FTRS_E6500	(CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
-	    CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
-	    CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
-	    CPU_FTR_DEBUG_LVL_EXC)
-#define CPU_FTRS_GENERIC_32	(CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
-
-/* 64-bit CPUs */
-#define CPU_FTRS_POWER3	(CPU_FTR_USE_TB | \
-	    CPU_FTR_IABR | CPU_FTR_PPC_LE)
-#define CPU_FTRS_RS64	(CPU_FTR_USE_TB | \
-	    CPU_FTR_IABR | \
-	    CPU_FTR_MMCRA | CPU_FTR_CTRL)
-#define CPU_FTRS_POWER4	(CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
-	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
-	    CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ | \
-	    CPU_FTR_STCX_CHECKS_ADDRESS)
-#define CPU_FTRS_PPC970	(CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
-	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_201 | \
-	    CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
-	    CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \
-	    CPU_FTR_HVMODE)
-#define CPU_FTRS_POWER5	(CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
-	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
-	    CPU_FTR_MMCRA | CPU_FTR_SMT | \
-	    CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
-	    CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB)
-#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
-	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
-	    CPU_FTR_MMCRA | CPU_FTR_SMT | \
-	    CPU_FTR_COHERENT_ICACHE | \
-	    CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
-	    CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
-	    CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR)
-#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
-	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
-	    CPU_FTR_MMCRA | CPU_FTR_SMT | \
-	    CPU_FTR_COHERENT_ICACHE | \
-	    CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
-	    CPU_FTR_DSCR | CPU_FTR_SAO  | CPU_FTR_ASYM_SMT | \
-	    CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
-	    CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY)
-#define CPU_FTRS_CELL	(CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
-	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
-	    CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
-	    CPU_FTR_PAUSE_ZERO  | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
-	    CPU_FTR_UNALIGNED_LD_STD)
-#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
-	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
-	    CPU_FTR_PURR | CPU_FTR_REAL_LE)
-#define CPU_FTRS_COMPATIBLE	(CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
-
-#define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \
-		     CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | CPU_FTR_ICSWX)
-
-#ifdef __powerpc64__
-#ifdef CONFIG_PPC_BOOK3E
-#define CPU_FTRS_POSSIBLE	(CPU_FTRS_E6500 | CPU_FTRS_E5500 | CPU_FTRS_A2)
-#else
-#define CPU_FTRS_POSSIBLE	\
-	    (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 |	\
-	    CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 |	\
-	    CPU_FTRS_POWER7 | CPU_FTRS_CELL | CPU_FTRS_PA6T |		\
-	    CPU_FTR_VSX)
-#endif
-#else
-enum {
-	CPU_FTRS_POSSIBLE =
-#if CLASSIC_PPC
-	    CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
-	    CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
-	    CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
-	    CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
-	    CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
-	    CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
-	    CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
-	    CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
-	    CPU_FTRS_CLASSIC32 |
-#else
-	    CPU_FTRS_GENERIC_32 |
-#endif
-#ifdef CONFIG_8xx
-	    CPU_FTRS_8XX |
-#endif
-#ifdef CONFIG_40x
-	    CPU_FTRS_40X |
-#endif
-#ifdef CONFIG_44x
-	    CPU_FTRS_44X | CPU_FTRS_440x6 |
-#endif
-#ifdef CONFIG_PPC_47x
-	    CPU_FTRS_47X | CPU_FTR_476_DD2 |
-#endif
-#ifdef CONFIG_E200
-	    CPU_FTRS_E200 |
-#endif
-#ifdef CONFIG_E500
-	    CPU_FTRS_E500 | CPU_FTRS_E500_2 | CPU_FTRS_E500MC |
-	    CPU_FTRS_E5500 | CPU_FTRS_E6500 |
-#endif
-	    0,
-};
-#endif /* __powerpc64__ */
-
-#ifdef __powerpc64__
-#ifdef CONFIG_PPC_BOOK3E
-#define CPU_FTRS_ALWAYS		(CPU_FTRS_E6500 & CPU_FTRS_E5500 & CPU_FTRS_A2)
-#else
-#define CPU_FTRS_ALWAYS		\
-	    (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 &	\
-	    CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 &	\
-	    CPU_FTRS_POWER7 & CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
-#endif
-#else
-enum {
-	CPU_FTRS_ALWAYS =
-#if CLASSIC_PPC
-	    CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
-	    CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
-	    CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
-	    CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
-	    CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
-	    CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
-	    CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
-	    CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
-	    CPU_FTRS_CLASSIC32 &
-#else
-	    CPU_FTRS_GENERIC_32 &
-#endif
-#ifdef CONFIG_8xx
-	    CPU_FTRS_8XX &
-#endif
-#ifdef CONFIG_40x
-	    CPU_FTRS_40X &
-#endif
-#ifdef CONFIG_44x
-	    CPU_FTRS_44X & CPU_FTRS_440x6 &
-#endif
-#ifdef CONFIG_E200
-	    CPU_FTRS_E200 &
-#endif
-#ifdef CONFIG_E500
-	    CPU_FTRS_E500 & CPU_FTRS_E500_2 & CPU_FTRS_E500MC &
-	    CPU_FTRS_E5500 & CPU_FTRS_E6500 &
-#endif
-	    CPU_FTRS_POSSIBLE,
-};
-#endif /* __powerpc64__ */
-
-static inline int cpu_has_feature(unsigned long feature)
-{
-	return (CPU_FTRS_ALWAYS & feature) ||
-	       (CPU_FTRS_POSSIBLE
-		& cur_cpu_spec->cpu_features
-		& feature);
-}
-
-#ifdef CONFIG_HAVE_HW_BREAKPOINT
-#define HBP_NUM 1
-#endif /* CONFIG_HAVE_HW_BREAKPOINT */
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* __KERNEL__ */
-#endif /* __ASM_POWERPC_CPUTABLE_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/cputhreads.h b/ANDROID_3.4.5/arch/powerpc/include/asm/cputhreads.h
deleted file mode 100644
index ce516e5e..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/cputhreads.h
+++ /dev/null
@@ -1,90 +0,0 @@
-#ifndef _ASM_POWERPC_CPUTHREADS_H
-#define _ASM_POWERPC_CPUTHREADS_H
-
-#include <linux/cpumask.h>
-
-/*
- * Mapping of threads to cores
- *
- * Note: This implementation is limited to a power of 2 number of
- * threads per core and the same number for each core in the system
- * (though it would work if some processors had less threads as long
- * as the CPU numbers are still allocated, just not brought offline).
- *
- * However, the API allows for a different implementation in the future
- * if needed, as long as you only use the functions and not the variables
- * directly.
- */
-
-#ifdef CONFIG_SMP
-extern int threads_per_core;
-extern int threads_shift;
-extern cpumask_t threads_core_mask;
-#else
-#define threads_per_core	1
-#define threads_shift		0
-#define threads_core_mask	(CPU_MASK_CPU0)
-#endif
-
-/* cpu_thread_mask_to_cores - Return a cpumask of one per cores
- *                            hit by the argument
- *
- * @threads:	a cpumask of threads
- *
- * This function returns a cpumask which will have one "cpu" (or thread)
- * bit set for each core that has at least one thread set in the argument.
- *
- * This can typically be used for things like IPI for tlb invalidations
- * since those need to be done only once per core/TLB
- */
-static inline cpumask_t cpu_thread_mask_to_cores(const struct cpumask *threads)
-{
-	cpumask_t	tmp, res;
-	int		i;
-
-	cpumask_clear(&res);
-	for (i = 0; i < NR_CPUS; i += threads_per_core) {
-		cpumask_shift_left(&tmp, &threads_core_mask, i);
-		if (cpumask_intersects(threads, &tmp))
-			cpumask_set_cpu(i, &res);
-	}
-	return res;
-}
-
-static inline int cpu_nr_cores(void)
-{
-	return NR_CPUS >> threads_shift;
-}
-
-static inline cpumask_t cpu_online_cores_map(void)
-{
-	return cpu_thread_mask_to_cores(cpu_online_mask);
-}
-
-#ifdef CONFIG_SMP
-int cpu_core_index_of_thread(int cpu);
-int cpu_first_thread_of_core(int core);
-#else
-static inline int cpu_core_index_of_thread(int cpu) { return cpu; }
-static inline int cpu_first_thread_of_core(int core) { return core; }
-#endif
-
-static inline int cpu_thread_in_core(int cpu)
-{
-	return cpu & (threads_per_core - 1);
-}
-
-static inline int cpu_first_thread_sibling(int cpu)
-{
-	return cpu & ~(threads_per_core - 1);
-}
-
-static inline int cpu_last_thread_sibling(int cpu)
-{
-	return cpu | (threads_per_core - 1);
-}
-
-
-
-#endif /* _ASM_POWERPC_CPUTHREADS_H */
-
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/cputime.h b/ANDROID_3.4.5/arch/powerpc/include/asm/cputime.h
deleted file mode 100644
index 487d46ff..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/cputime.h
+++ /dev/null
@@ -1,233 +0,0 @@
-/*
- * Definitions for measuring cputime on powerpc machines.
- *
- * Copyright (C) 2006 Paul Mackerras, IBM Corp.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- *
- * If we have CONFIG_VIRT_CPU_ACCOUNTING, we measure cpu time in
- * the same units as the timebase.  Otherwise we measure cpu time
- * in jiffies using the generic definitions.
- */
-
-#ifndef __POWERPC_CPUTIME_H
-#define __POWERPC_CPUTIME_H
-
-#ifndef CONFIG_VIRT_CPU_ACCOUNTING
-#include <asm-generic/cputime.h>
-#ifdef __KERNEL__
-static inline void setup_cputime_one_jiffy(void) { }
-#endif
-#else
-
-#include <linux/types.h>
-#include <linux/time.h>
-#include <asm/div64.h>
-#include <asm/time.h>
-#include <asm/param.h>
-
-typedef u64 __nocast cputime_t;
-typedef u64 __nocast cputime64_t;
-
-#ifdef __KERNEL__
-
-/*
- * One jiffy in timebase units computed during initialization
- */
-extern cputime_t cputime_one_jiffy;
-
-/*
- * Convert cputime <-> jiffies
- */
-extern u64 __cputime_jiffies_factor;
-DECLARE_PER_CPU(unsigned long, cputime_last_delta);
-DECLARE_PER_CPU(unsigned long, cputime_scaled_last_delta);
-
-static inline unsigned long cputime_to_jiffies(const cputime_t ct)
-{
-	return mulhdu((__force u64) ct, __cputime_jiffies_factor);
-}
-
-/* Estimate the scaled cputime by scaling the real cputime based on
- * the last scaled to real ratio */
-static inline cputime_t cputime_to_scaled(const cputime_t ct)
-{
-	if (cpu_has_feature(CPU_FTR_SPURR) &&
-	    __get_cpu_var(cputime_last_delta))
-		return (__force u64) ct *
-			__get_cpu_var(cputime_scaled_last_delta) /
-			__get_cpu_var(cputime_last_delta);
-	return ct;
-}
-
-static inline cputime_t jiffies_to_cputime(const unsigned long jif)
-{
-	u64 ct;
-	unsigned long sec;
-
-	/* have to be a little careful about overflow */
-	ct = jif % HZ;
-	sec = jif / HZ;
-	if (ct) {
-		ct *= tb_ticks_per_sec;
-		do_div(ct, HZ);
-	}
-	if (sec)
-		ct += (cputime_t) sec * tb_ticks_per_sec;
-	return (__force cputime_t) ct;
-}
-
-static inline void setup_cputime_one_jiffy(void)
-{
-	cputime_one_jiffy = jiffies_to_cputime(1);
-}
-
-static inline cputime64_t jiffies64_to_cputime64(const u64 jif)
-{
-	u64 ct;
-	u64 sec;
-
-	/* have to be a little careful about overflow */
-	ct = jif % HZ;
-	sec = jif / HZ;
-	if (ct) {
-		ct *= tb_ticks_per_sec;
-		do_div(ct, HZ);
-	}
-	if (sec)
-		ct += (u64) sec * tb_ticks_per_sec;
-	return (__force cputime64_t) ct;
-}
-
-static inline u64 cputime64_to_jiffies64(const cputime_t ct)
-{
-	return mulhdu((__force u64) ct, __cputime_jiffies_factor);
-}
-
-/*
- * Convert cputime <-> microseconds
- */
-extern u64 __cputime_usec_factor;
-
-static inline unsigned long cputime_to_usecs(const cputime_t ct)
-{
-	return mulhdu((__force u64) ct, __cputime_usec_factor);
-}
-
-static inline cputime_t usecs_to_cputime(const unsigned long us)
-{
-	u64 ct;
-	unsigned long sec;
-
-	/* have to be a little careful about overflow */
-	ct = us % 1000000;
-	sec = us / 1000000;
-	if (ct) {
-		ct *= tb_ticks_per_sec;
-		do_div(ct, 1000000);
-	}
-	if (sec)
-		ct += (cputime_t) sec * tb_ticks_per_sec;
-	return (__force cputime_t) ct;
-}
-
-#define usecs_to_cputime64(us)		usecs_to_cputime(us)
-
-/*
- * Convert cputime <-> seconds
- */
-extern u64 __cputime_sec_factor;
-
-static inline unsigned long cputime_to_secs(const cputime_t ct)
-{
-	return mulhdu((__force u64) ct, __cputime_sec_factor);
-}
-
-static inline cputime_t secs_to_cputime(const unsigned long sec)
-{
-	return (__force cputime_t)((u64) sec * tb_ticks_per_sec);
-}
-
-/*
- * Convert cputime <-> timespec
- */
-static inline void cputime_to_timespec(const cputime_t ct, struct timespec *p)
-{
-	u64 x = (__force u64) ct;
-	unsigned int frac;
-
-	frac = do_div(x, tb_ticks_per_sec);
-	p->tv_sec = x;
-	x = (u64) frac * 1000000000;
-	do_div(x, tb_ticks_per_sec);
-	p->tv_nsec = x;
-}
-
-static inline cputime_t timespec_to_cputime(const struct timespec *p)
-{
-	u64 ct;
-
-	ct = (u64) p->tv_nsec * tb_ticks_per_sec;
-	do_div(ct, 1000000000);
-	return (__force cputime_t)(ct + (u64) p->tv_sec * tb_ticks_per_sec);
-}
-
-/*
- * Convert cputime <-> timeval
- */
-static inline void cputime_to_timeval(const cputime_t ct, struct timeval *p)
-{
-	u64 x = (__force u64) ct;
-	unsigned int frac;
-
-	frac = do_div(x, tb_ticks_per_sec);
-	p->tv_sec = x;
-	x = (u64) frac * 1000000;
-	do_div(x, tb_ticks_per_sec);
-	p->tv_usec = x;
-}
-
-static inline cputime_t timeval_to_cputime(const struct timeval *p)
-{
-	u64 ct;
-
-	ct = (u64) p->tv_usec * tb_ticks_per_sec;
-	do_div(ct, 1000000);
-	return (__force cputime_t)(ct + (u64) p->tv_sec * tb_ticks_per_sec);
-}
-
-/*
- * Convert cputime <-> clock_t (units of 1/USER_HZ seconds)
- */
-extern u64 __cputime_clockt_factor;
-
-static inline unsigned long cputime_to_clock_t(const cputime_t ct)
-{
-	return mulhdu((__force u64) ct, __cputime_clockt_factor);
-}
-
-static inline cputime_t clock_t_to_cputime(const unsigned long clk)
-{
-	u64 ct;
-	unsigned long sec;
-
-	/* have to be a little careful about overflow */
-	ct = clk % USER_HZ;
-	sec = clk / USER_HZ;
-	if (ct) {
-		ct *= tb_ticks_per_sec;
-		do_div(ct, USER_HZ);
-	}
-	if (sec)
-		ct += (u64) sec * tb_ticks_per_sec;
-	return (__force cputime_t) ct;
-}
-
-#define cputime64_to_clock_t(ct)	cputime_to_clock_t((cputime_t)(ct))
-
-#endif /* __KERNEL__ */
-#endif /* CONFIG_VIRT_CPU_ACCOUNTING */
-#endif /* __POWERPC_CPUTIME_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/current.h b/ANDROID_3.4.5/arch/powerpc/include/asm/current.h
deleted file mode 100644
index e2c7f069..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/current.h
+++ /dev/null
@@ -1,40 +0,0 @@
-#ifndef _ASM_POWERPC_CURRENT_H
-#define _ASM_POWERPC_CURRENT_H
-#ifdef __KERNEL__
-
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-struct task_struct;
-
-#ifdef __powerpc64__
-#include <linux/stddef.h>
-#include <asm/paca.h>
-
-static inline struct task_struct *get_current(void)
-{
-	struct task_struct *task;
-
-	__asm__ __volatile__("ld %0,%1(13)"
-	: "=r" (task)
-	: "i" (offsetof(struct paca_struct, __current)));
-
-	return task;
-}
-#define current	get_current()
-
-#else
-
-/*
- * We keep `current' in r2 for speed.
- */
-register struct task_struct *current asm ("r2");
-
-#endif
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_CURRENT_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/dbdma.h b/ANDROID_3.4.5/arch/powerpc/include/asm/dbdma.h
deleted file mode 100644
index e23f07e7..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/dbdma.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * Definitions for using the Apple Descriptor-Based DMA controller
- * in Power Macintosh computers.
- *
- * Copyright (C) 1996 Paul Mackerras.
- */
-
-#ifdef __KERNEL__
-#ifndef _ASM_DBDMA_H_
-#define _ASM_DBDMA_H_
-/*
- * DBDMA control/status registers.  All little-endian.
- */
-struct dbdma_regs {
-    unsigned int control;	/* lets you change bits in status */
-    unsigned int status;	/* DMA and device status bits (see below) */
-    unsigned int cmdptr_hi;	/* upper 32 bits of command address */
-    unsigned int cmdptr;	/* (lower 32 bits of) command address (phys) */
-    unsigned int intr_sel;	/* select interrupt condition bit */
-    unsigned int br_sel;	/* select branch condition bit */
-    unsigned int wait_sel;	/* select wait condition bit */
-    unsigned int xfer_mode;
-    unsigned int data2ptr_hi;
-    unsigned int data2ptr;
-    unsigned int res1;
-    unsigned int address_hi;
-    unsigned int br_addr_hi;
-    unsigned int res2[3];
-};
-
-/* Bits in control and status registers */
-#define RUN	0x8000
-#define PAUSE	0x4000
-#define FLUSH	0x2000
-#define WAKE	0x1000
-#define DEAD	0x0800
-#define ACTIVE	0x0400
-#define BT	0x0100
-#define DEVSTAT	0x00ff
-
-/*
- * DBDMA command structure.  These fields are all little-endian!
- */
-struct dbdma_cmd {
-    unsigned short req_count;	/* requested byte transfer count */
-    unsigned short command;	/* command word (has bit-fields) */
-    unsigned int   phy_addr;	/* physical data address */
-    unsigned int   cmd_dep;	/* command-dependent field */
-    unsigned short res_count;	/* residual count after completion */
-    unsigned short xfer_status;	/* transfer status */
-};
-
-/* DBDMA command values in command field */
-#define OUTPUT_MORE	0	/* transfer memory data to stream */
-#define OUTPUT_LAST	0x1000	/* ditto followed by end marker */
-#define INPUT_MORE	0x2000	/* transfer stream data to memory */
-#define INPUT_LAST	0x3000	/* ditto, expect end marker */
-#define STORE_WORD	0x4000	/* write word (4 bytes) to device reg */
-#define LOAD_WORD	0x5000	/* read word (4 bytes) from device reg */
-#define DBDMA_NOP	0x6000	/* do nothing */
-#define DBDMA_STOP	0x7000	/* suspend processing */
-
-/* Key values in command field */
-#define KEY_STREAM0	0	/* usual data stream */
-#define KEY_STREAM1	0x100	/* control/status stream */
-#define KEY_STREAM2	0x200	/* device-dependent stream */
-#define KEY_STREAM3	0x300	/* device-dependent stream */
-#define KEY_REGS	0x500	/* device register space */
-#define KEY_SYSTEM	0x600	/* system memory-mapped space */
-#define KEY_DEVICE	0x700	/* device memory-mapped space */
-
-/* Interrupt control values in command field */
-#define INTR_NEVER	0	/* don't interrupt */
-#define INTR_IFSET	0x10	/* intr if condition bit is 1 */
-#define INTR_IFCLR	0x20	/* intr if condition bit is 0 */
-#define INTR_ALWAYS	0x30	/* always interrupt */
-
-/* Branch control values in command field */
-#define BR_NEVER	0	/* don't branch */
-#define BR_IFSET	0x4	/* branch if condition bit is 1 */
-#define BR_IFCLR	0x8	/* branch if condition bit is 0 */
-#define BR_ALWAYS	0xc	/* always branch */
-
-/* Wait control values in command field */
-#define WAIT_NEVER	0	/* don't wait */
-#define WAIT_IFSET	1	/* wait if condition bit is 1 */
-#define WAIT_IFCLR	2	/* wait if condition bit is 0 */
-#define WAIT_ALWAYS	3	/* always wait */
-
-/* Align an address for a DBDMA command structure */
-#define DBDMA_ALIGN(x)	(((unsigned long)(x) + sizeof(struct dbdma_cmd) - 1) \
-			 & -sizeof(struct dbdma_cmd))
-
-/* Useful macros */
-#define DBDMA_DO_STOP(regs) do {				\
-	out_le32(&((regs)->control), (RUN|FLUSH)<<16);		\
-	while(in_le32(&((regs)->status)) & (ACTIVE|FLUSH))	\
-		; \
-} while(0)
-
-#define DBDMA_DO_RESET(regs) do {				\
-	out_le32(&((regs)->control), (ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN)<<16);\
-	while(in_le32(&((regs)->status)) & (RUN)) \
-		; \
-} while(0)
-
-#endif /* _ASM_DBDMA_H_ */
-#endif /* __KERNEL__ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/dbell.h b/ANDROID_3.4.5/arch/powerpc/include/asm/dbell.h
deleted file mode 100644
index efa74ac4..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/dbell.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright 2009 Freescale Semicondutor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- *
- * provides masks and opcode images for use by code generation, emulation
- * and for instructions that older assemblers might not know about
- */
-#ifndef _ASM_POWERPC_DBELL_H
-#define _ASM_POWERPC_DBELL_H
-
-#include <linux/smp.h>
-#include <linux/threads.h>
-
-#include <asm/ppc-opcode.h>
-
-#define PPC_DBELL_MSG_BRDCAST	(0x04000000)
-#define PPC_DBELL_TYPE(x)	(((x) & 0xf) << (63-36))
-enum ppc_dbell {
-	PPC_DBELL = 0,		/* doorbell */
-	PPC_DBELL_CRIT = 1,	/* critical doorbell */
-	PPC_G_DBELL = 2,	/* guest doorbell */
-	PPC_G_DBELL_CRIT = 3,	/* guest critical doorbell */
-	PPC_G_DBELL_MC = 4,	/* guest mcheck doorbell */
-};
-
-extern void doorbell_cause_ipi(int cpu, unsigned long data);
-extern void doorbell_exception(struct pt_regs *regs);
-extern void doorbell_setup_this_cpu(void);
-
-static inline void ppc_msgsnd(enum ppc_dbell type, u32 flags, u32 tag)
-{
-	u32 msg = PPC_DBELL_TYPE(type) | (flags & PPC_DBELL_MSG_BRDCAST) |
-			(tag & 0x07ffffff);
-
-	__asm__ __volatile__ (PPC_MSGSND(%0) : : "r" (msg));
-}
-
-#endif /* _ASM_POWERPC_DBELL_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/dcr-generic.h b/ANDROID_3.4.5/arch/powerpc/include/asm/dcr-generic.h
deleted file mode 100644
index 35b71599..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/dcr-generic.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * (c) Copyright 2006 Benjamin Herrenschmidt, IBM Corp.
- *                    <benh@kernel.crashing.org>
- *
- *   This program is free software;  you can redistribute it and/or modify
- *   it under the terms of the GNU General Public License as published by
- *   the Free Software Foundation; either version 2 of the License, or
- *   (at your option) any later version.
- *
- *   This program is distributed in the hope that it will be useful,
- *   but WITHOUT ANY WARRANTY;  without even the implied warranty of
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
- *   the GNU General Public License for more details.
- *
- *   You should have received a copy of the GNU General Public License
- *   along with this program;  if not, write to the Free Software
- *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#ifndef _ASM_POWERPC_DCR_GENERIC_H
-#define _ASM_POWERPC_DCR_GENERIC_H
-#ifdef __KERNEL__
-#ifndef __ASSEMBLY__
-
-enum host_type_t {DCR_HOST_MMIO, DCR_HOST_NATIVE, DCR_HOST_INVALID};
-
-typedef struct {
-	enum host_type_t type;
-	union {
-		dcr_host_mmio_t mmio;
-		dcr_host_native_t native;
-	} host;
-} dcr_host_t;
-
-extern bool dcr_map_ok_generic(dcr_host_t host);
-
-extern dcr_host_t dcr_map_generic(struct device_node *dev, unsigned int dcr_n,
-			  unsigned int dcr_c);
-extern void dcr_unmap_generic(dcr_host_t host, unsigned int dcr_c);
-
-extern u32 dcr_read_generic(dcr_host_t host, unsigned int dcr_n);
-
-extern void dcr_write_generic(dcr_host_t host, unsigned int dcr_n, u32 value);
-
-#endif /* __ASSEMBLY__ */
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_DCR_GENERIC_H */
-
-
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/dcr-mmio.h b/ANDROID_3.4.5/arch/powerpc/include/asm/dcr-mmio.h
deleted file mode 100644
index acd491db..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/dcr-mmio.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * (c) Copyright 2006 Benjamin Herrenschmidt, IBM Corp.
- *                    <benh@kernel.crashing.org>
- *
- *   This program is free software;  you can redistribute it and/or modify
- *   it under the terms of the GNU General Public License as published by
- *   the Free Software Foundation; either version 2 of the License, or
- *   (at your option) any later version.
- *
- *   This program is distributed in the hope that it will be useful,
- *   but WITHOUT ANY WARRANTY;  without even the implied warranty of
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
- *   the GNU General Public License for more details.
- *
- *   You should have received a copy of the GNU General Public License
- *   along with this program;  if not, write to the Free Software
- *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#ifndef _ASM_POWERPC_DCR_MMIO_H
-#define _ASM_POWERPC_DCR_MMIO_H
-#ifdef __KERNEL__
-
-#include <asm/io.h>
-
-typedef struct {
-	void __iomem *token;
-	unsigned int stride;
-	unsigned int base;
-} dcr_host_mmio_t;
-
-static inline bool dcr_map_ok_mmio(dcr_host_mmio_t host)
-{
-	return host.token != NULL;
-}
-
-extern dcr_host_mmio_t dcr_map_mmio(struct device_node *dev,
-				    unsigned int dcr_n,
-				    unsigned int dcr_c);
-extern void dcr_unmap_mmio(dcr_host_mmio_t host, unsigned int dcr_c);
-
-static inline u32 dcr_read_mmio(dcr_host_mmio_t host, unsigned int dcr_n)
-{
-	return in_be32(host.token + ((host.base + dcr_n) * host.stride));
-}
-
-static inline void dcr_write_mmio(dcr_host_mmio_t host,
-				  unsigned int dcr_n,
-				  u32 value)
-{
-	out_be32(host.token + ((host.base + dcr_n) * host.stride), value);
-}
-
-extern u64 of_translate_dcr_address(struct device_node *dev,
-				    unsigned int dcr_n,
-				    unsigned int *stride);
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_DCR_MMIO_H */
-
-
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/dcr-native.h b/ANDROID_3.4.5/arch/powerpc/include/asm/dcr-native.h
deleted file mode 100644
index 7d2e6235..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/dcr-native.h
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * (c) Copyright 2006 Benjamin Herrenschmidt, IBM Corp.
- *                    <benh@kernel.crashing.org>
- *
- *   This program is free software;  you can redistribute it and/or modify
- *   it under the terms of the GNU General Public License as published by
- *   the Free Software Foundation; either version 2 of the License, or
- *   (at your option) any later version.
- *
- *   This program is distributed in the hope that it will be useful,
- *   but WITHOUT ANY WARRANTY;  without even the implied warranty of
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
- *   the GNU General Public License for more details.
- *
- *   You should have received a copy of the GNU General Public License
- *   along with this program;  if not, write to the Free Software
- *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#ifndef _ASM_POWERPC_DCR_NATIVE_H
-#define _ASM_POWERPC_DCR_NATIVE_H
-#ifdef __KERNEL__
-#ifndef __ASSEMBLY__
-
-#include <linux/spinlock.h>
-#include <asm/cputable.h>
-
-typedef struct {
-	unsigned int base;
-} dcr_host_native_t;
-
-static inline bool dcr_map_ok_native(dcr_host_native_t host)
-{
-	return 1;
-}
-
-#define dcr_map_native(dev, dcr_n, dcr_c) \
-	((dcr_host_native_t){ .base = (dcr_n) })
-#define dcr_unmap_native(host, dcr_c)		do {} while (0)
-#define dcr_read_native(host, dcr_n)		mfdcr(dcr_n + host.base)
-#define dcr_write_native(host, dcr_n, value)	mtdcr(dcr_n + host.base, value)
-
-/* Table based DCR accessors */
-extern void __mtdcr(unsigned int reg, unsigned int val);
-extern unsigned int __mfdcr(unsigned int reg);
-
-/* mfdcrx/mtdcrx instruction based accessors. We hand code
- * the opcodes in order not to depend on newer binutils
- */
-static inline unsigned int mfdcrx(unsigned int reg)
-{
-	unsigned int ret;
-	asm volatile(".long 0x7c000206 | (%0 << 21) | (%1 << 16)"
-		     : "=r" (ret) : "r" (reg));
-	return ret;
-}
-
-static inline void mtdcrx(unsigned int reg, unsigned int val)
-{
-	asm volatile(".long 0x7c000306 | (%0 << 21) | (%1 << 16)"
-		     : : "r" (val), "r" (reg));
-}
-
-#define mfdcr(rn)						\
-	({unsigned int rval;					\
-	if (__builtin_constant_p(rn) && rn < 1024)		\
-		asm volatile("mfdcr %0," __stringify(rn)	\
-		              : "=r" (rval));			\
-	else if (likely(cpu_has_feature(CPU_FTR_INDEXED_DCR)))	\
-		rval = mfdcrx(rn);				\
-	else							\
-		rval = __mfdcr(rn);				\
-	rval;})
-
-#define mtdcr(rn, v)						\
-do {								\
-	if (__builtin_constant_p(rn) && rn < 1024)		\
-		asm volatile("mtdcr " __stringify(rn) ",%0"	\
-			      : : "r" (v)); 			\
-	else if (likely(cpu_has_feature(CPU_FTR_INDEXED_DCR)))	\
-		mtdcrx(rn, v);					\
-	else							\
-		__mtdcr(rn, v);					\
-} while (0)
-
-/* R/W of indirect DCRs make use of standard naming conventions for DCRs */
-extern spinlock_t dcr_ind_lock;
-
-static inline unsigned __mfdcri(int base_addr, int base_data, int reg)
-{
-	unsigned long flags;
-	unsigned int val;
-
-	spin_lock_irqsave(&dcr_ind_lock, flags);
-	if (cpu_has_feature(CPU_FTR_INDEXED_DCR)) {
-		mtdcrx(base_addr, reg);
-		val = mfdcrx(base_data);
-	} else {
-		__mtdcr(base_addr, reg);
-		val = __mfdcr(base_data);
-	}
-	spin_unlock_irqrestore(&dcr_ind_lock, flags);
-	return val;
-}
-
-static inline void __mtdcri(int base_addr, int base_data, int reg,
-			    unsigned val)
-{
-	unsigned long flags;
-
-	spin_lock_irqsave(&dcr_ind_lock, flags);
-	if (cpu_has_feature(CPU_FTR_INDEXED_DCR)) {
-		mtdcrx(base_addr, reg);
-		mtdcrx(base_data, val);
-	} else {
-		__mtdcr(base_addr, reg);
-		__mtdcr(base_data, val);
-	}
-	spin_unlock_irqrestore(&dcr_ind_lock, flags);
-}
-
-static inline void __dcri_clrset(int base_addr, int base_data, int reg,
-				 unsigned clr, unsigned set)
-{
-	unsigned long flags;
-	unsigned int val;
-
-	spin_lock_irqsave(&dcr_ind_lock, flags);
-	if (cpu_has_feature(CPU_FTR_INDEXED_DCR)) {
-		mtdcrx(base_addr, reg);
-		val = (mfdcrx(base_data) & ~clr) | set;
-		mtdcrx(base_data, val);
-	} else {
-		__mtdcr(base_addr, reg);
-		val = (__mfdcr(base_data) & ~clr) | set;
-		__mtdcr(base_data, val);
-	}
-	spin_unlock_irqrestore(&dcr_ind_lock, flags);
-}
-
-#define mfdcri(base, reg)	__mfdcri(DCRN_ ## base ## _CONFIG_ADDR,	\
-					 DCRN_ ## base ## _CONFIG_DATA,	\
-					 reg)
-
-#define mtdcri(base, reg, data)	__mtdcri(DCRN_ ## base ## _CONFIG_ADDR,	\
-					 DCRN_ ## base ## _CONFIG_DATA,	\
-					 reg, data)
-
-#define dcri_clrset(base, reg, clr, set)	__dcri_clrset(DCRN_ ## base ## _CONFIG_ADDR,	\
-							      DCRN_ ## base ## _CONFIG_DATA,	\
-							      reg, clr, set)
-
-#endif /* __ASSEMBLY__ */
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_DCR_NATIVE_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/dcr-regs.h b/ANDROID_3.4.5/arch/powerpc/include/asm/dcr-regs.h
deleted file mode 100644
index 380274de..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/dcr-regs.h
+++ /dev/null
@@ -1,183 +0,0 @@
-/*
- * Common DCR / SDR / CPR register definitions used on various IBM/AMCC
- * 4xx processors
- *
- *    Copyright 2007 Benjamin Herrenschmidt, IBM Corp
- *                   <benh@kernel.crashing.org>
- *
- * Mostly lifted from asm-ppc/ibm4xx.h by
- *
- *    Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
- *
- */
-
-#ifndef __DCR_REGS_H__
-#define __DCR_REGS_H__
-
-/*
- * Most DCRs used for controlling devices such as the MAL, DMA engine,
- * etc... are obtained for the device tree.
- *
- * The definitions in this files are fixed DCRs and indirect DCRs that
- * are commonly used outside of specific drivers or refer to core
- * common registers that may occasionally have to be tweaked outside
- * of the driver main register set
- */
-
-/* CPRs (440GX and 440SP/440SPe) */
-#define DCRN_CPR0_CONFIG_ADDR	0xc
-#define DCRN_CPR0_CONFIG_DATA	0xd
-
-/* SDRs (440GX and 440SP/440SPe) */
-#define DCRN_SDR0_CONFIG_ADDR 	0xe
-#define DCRN_SDR0_CONFIG_DATA	0xf
-
-#define SDR0_PFC0		0x4100
-#define SDR0_PFC1		0x4101
-#define SDR0_PFC1_EPS		0x1c00000
-#define SDR0_PFC1_EPS_SHIFT	22
-#define SDR0_PFC1_RMII		0x02000000
-#define SDR0_MFR		0x4300
-#define SDR0_MFR_TAH0 		0x80000000  	/* TAHOE0 Enable */
-#define SDR0_MFR_TAH1 		0x40000000  	/* TAHOE1 Enable */
-#define SDR0_MFR_PCM  		0x10000000  	/* PPC440GP irq compat mode */
-#define SDR0_MFR_ECS  		0x08000000  	/* EMAC int clk */
-#define SDR0_MFR_T0TXFL		0x00080000
-#define SDR0_MFR_T0TXFH		0x00040000
-#define SDR0_MFR_T1TXFL		0x00020000
-#define SDR0_MFR_T1TXFH		0x00010000
-#define SDR0_MFR_E0TXFL		0x00008000
-#define SDR0_MFR_E0TXFH		0x00004000
-#define SDR0_MFR_E0RXFL		0x00002000
-#define SDR0_MFR_E0RXFH		0x00001000
-#define SDR0_MFR_E1TXFL		0x00000800
-#define SDR0_MFR_E1TXFH		0x00000400
-#define SDR0_MFR_E1RXFL		0x00000200
-#define SDR0_MFR_E1RXFH		0x00000100
-#define SDR0_MFR_E2TXFL		0x00000080
-#define SDR0_MFR_E2TXFH		0x00000040
-#define SDR0_MFR_E2RXFL		0x00000020
-#define SDR0_MFR_E2RXFH		0x00000010
-#define SDR0_MFR_E3TXFL		0x00000008
-#define SDR0_MFR_E3TXFH		0x00000004
-#define SDR0_MFR_E3RXFL		0x00000002
-#define SDR0_MFR_E3RXFH		0x00000001
-#define SDR0_UART0		0x0120
-#define SDR0_UART1		0x0121
-#define SDR0_UART2		0x0122
-#define SDR0_UART3		0x0123
-#define SDR0_CUST0		0x4000
-
-/* SDR for 405EZ */
-#define DCRN_SDR_ICINTSTAT	0x4510
-#define ICINTSTAT_ICRX	0x80000000
-#define ICINTSTAT_ICTX0	0x40000000
-#define ICINTSTAT_ICTX1 0x20000000
-#define ICINTSTAT_ICTX	0x60000000
-
-/* SDRs (460EX/460GT) */
-#define SDR0_ETH_CFG		0x4103
-#define SDR0_ETH_CFG_ECS	0x00000100	/* EMAC int clk source */
-
-/*
- * All those DCR register addresses are offsets from the base address
- * for the SRAM0 controller (e.g. 0x20 on 440GX). The base address is
- * excluded here and configured in the device tree.
- */
-#define DCRN_SRAM0_SB0CR	0x00
-#define DCRN_SRAM0_SB1CR	0x01
-#define DCRN_SRAM0_SB2CR	0x02
-#define DCRN_SRAM0_SB3CR	0x03
-#define  SRAM_SBCR_BU_MASK	0x00000180
-#define  SRAM_SBCR_BS_64KB	0x00000800
-#define  SRAM_SBCR_BU_RO	0x00000080
-#define  SRAM_SBCR_BU_RW	0x00000180
-#define DCRN_SRAM0_BEAR		0x04
-#define DCRN_SRAM0_BESR0	0x05
-#define DCRN_SRAM0_BESR1	0x06
-#define DCRN_SRAM0_PMEG		0x07
-#define DCRN_SRAM0_CID		0x08
-#define DCRN_SRAM0_REVID	0x09
-#define DCRN_SRAM0_DPC		0x0a
-#define  SRAM_DPC_ENABLE	0x80000000
-
-/*
- * All those DCR register addresses are offsets from the base address
- * for the SRAM0 controller (e.g. 0x30 on 440GX). The base address is
- * excluded here and configured in the device tree.
- */
-#define DCRN_L2C0_CFG		0x00
-#define  L2C_CFG_L2M		0x80000000
-#define  L2C_CFG_ICU		0x40000000
-#define  L2C_CFG_DCU		0x20000000
-#define  L2C_CFG_DCW_MASK	0x1e000000
-#define  L2C_CFG_TPC		0x01000000
-#define  L2C_CFG_CPC		0x00800000
-#define  L2C_CFG_FRAN		0x00200000
-#define  L2C_CFG_SS_MASK	0x00180000
-#define  L2C_CFG_SS_256		0x00000000
-#define  L2C_CFG_CPIM		0x00040000
-#define  L2C_CFG_TPIM		0x00020000
-#define  L2C_CFG_LIM		0x00010000
-#define  L2C_CFG_PMUX_MASK	0x00007000
-#define  L2C_CFG_PMUX_SNP	0x00000000
-#define  L2C_CFG_PMUX_IF	0x00001000
-#define  L2C_CFG_PMUX_DF	0x00002000
-#define  L2C_CFG_PMUX_DS	0x00003000
-#define  L2C_CFG_PMIM		0x00000800
-#define  L2C_CFG_TPEI		0x00000400
-#define  L2C_CFG_CPEI		0x00000200
-#define  L2C_CFG_NAM		0x00000100
-#define  L2C_CFG_SMCM		0x00000080
-#define  L2C_CFG_NBRM		0x00000040
-#define  L2C_CFG_RDBW		0x00000008	/* only 460EX/GT */
-#define DCRN_L2C0_CMD		0x01
-#define  L2C_CMD_CLR		0x80000000
-#define  L2C_CMD_DIAG		0x40000000
-#define  L2C_CMD_INV		0x20000000
-#define  L2C_CMD_CCP		0x10000000
-#define  L2C_CMD_CTE		0x08000000
-#define  L2C_CMD_STRC		0x04000000
-#define  L2C_CMD_STPC		0x02000000
-#define  L2C_CMD_RPMC		0x01000000
-#define  L2C_CMD_HCC		0x00800000
-#define DCRN_L2C0_ADDR		0x02
-#define DCRN_L2C0_DATA		0x03
-#define DCRN_L2C0_SR		0x04
-#define  L2C_SR_CC		0x80000000
-#define  L2C_SR_CPE		0x40000000
-#define  L2C_SR_TPE		0x20000000
-#define  L2C_SR_LRU		0x10000000
-#define  L2C_SR_PCS		0x08000000
-#define DCRN_L2C0_REVID		0x05
-#define DCRN_L2C0_SNP0		0x06
-#define DCRN_L2C0_SNP1		0x07
-#define  L2C_SNP_BA_MASK	0xffff0000
-#define  L2C_SNP_SSR_MASK	0x0000f000
-#define  L2C_SNP_SSR_32G	0x0000f000
-#define  L2C_SNP_ESR		0x00000800
-
-/*
- * DCR register offsets for 440SP/440SPe I2O/DMA controller.
- * The base address is configured in the device tree.
- */
-#define DCRN_I2O0_IBAL		0x006
-#define DCRN_I2O0_IBAH		0x007
-#define I2O_REG_ENABLE		0x00000001	/* Enable I2O/DMA access */
-
-/* 440SP/440SPe Software Reset DCR */
-#define DCRN_SDR0_SRST		0x0200
-#define DCRN_SDR0_SRST_I2ODMA	(0x80000000 >> 15)	/* Reset I2O/DMA */
-
-/* 440SP/440SPe Memory Queue DCR offsets */
-#define DCRN_MQ0_XORBA		0x04
-#define DCRN_MQ0_CF2H		0x06
-#define DCRN_MQ0_CFBHL		0x0f
-#define DCRN_MQ0_BAUH		0x10
-
-/* HB/LL Paths Configuration Register */
-#define MQ0_CFBHL_TPLM		28
-#define MQ0_CFBHL_HBCL		23
-#define MQ0_CFBHL_POLY		15
-
-#endif /* __DCR_REGS_H__ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/dcr.h b/ANDROID_3.4.5/arch/powerpc/include/asm/dcr.h
deleted file mode 100644
index 9d6851cf..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/dcr.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * (c) Copyright 2006 Benjamin Herrenschmidt, IBM Corp.
- *                    <benh@kernel.crashing.org>
- *
- *   This program is free software;  you can redistribute it and/or modify
- *   it under the terms of the GNU General Public License as published by
- *   the Free Software Foundation; either version 2 of the License, or
- *   (at your option) any later version.
- *
- *   This program is distributed in the hope that it will be useful,
- *   but WITHOUT ANY WARRANTY;  without even the implied warranty of
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
- *   the GNU General Public License for more details.
- *
- *   You should have received a copy of the GNU General Public License
- *   along with this program;  if not, write to the Free Software
- *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#ifndef _ASM_POWERPC_DCR_H
-#define _ASM_POWERPC_DCR_H
-#ifdef __KERNEL__
-#ifndef __ASSEMBLY__
-#ifdef CONFIG_PPC_DCR
-
-#ifdef CONFIG_PPC_DCR_NATIVE
-#include <asm/dcr-native.h>
-#endif
-
-#ifdef CONFIG_PPC_DCR_MMIO
-#include <asm/dcr-mmio.h>
-#endif
-
-
-/* Indirection layer for providing both NATIVE and MMIO support. */
-
-#if defined(CONFIG_PPC_DCR_NATIVE) && defined(CONFIG_PPC_DCR_MMIO)
-
-#include <asm/dcr-generic.h>
-
-#define DCR_MAP_OK(host)	dcr_map_ok_generic(host)
-#define dcr_map(dev, dcr_n, dcr_c) dcr_map_generic(dev, dcr_n, dcr_c)
-#define dcr_unmap(host, dcr_c) dcr_unmap_generic(host, dcr_c)
-#define dcr_read(host, dcr_n) dcr_read_generic(host, dcr_n)
-#define dcr_write(host, dcr_n, value) dcr_write_generic(host, dcr_n, value)
-
-#else
-
-#ifdef CONFIG_PPC_DCR_NATIVE
-typedef dcr_host_native_t dcr_host_t;
-#define DCR_MAP_OK(host)	dcr_map_ok_native(host)
-#define dcr_map(dev, dcr_n, dcr_c) dcr_map_native(dev, dcr_n, dcr_c)
-#define dcr_unmap(host, dcr_c) dcr_unmap_native(host, dcr_c)
-#define dcr_read(host, dcr_n) dcr_read_native(host, dcr_n)
-#define dcr_write(host, dcr_n, value) dcr_write_native(host, dcr_n, value)
-#else
-typedef dcr_host_mmio_t dcr_host_t;
-#define DCR_MAP_OK(host)	dcr_map_ok_mmio(host)
-#define dcr_map(dev, dcr_n, dcr_c) dcr_map_mmio(dev, dcr_n, dcr_c)
-#define dcr_unmap(host, dcr_c) dcr_unmap_mmio(host, dcr_c)
-#define dcr_read(host, dcr_n) dcr_read_mmio(host, dcr_n)
-#define dcr_write(host, dcr_n, value) dcr_write_mmio(host, dcr_n, value)
-#endif
-
-#endif /* defined(CONFIG_PPC_DCR_NATIVE) && defined(CONFIG_PPC_DCR_MMIO) */
-
-/*
- * additional helpers to read the DCR * base from the device-tree
- */
-struct device_node;
-extern unsigned int dcr_resource_start(const struct device_node *np,
-				       unsigned int index);
-extern unsigned int dcr_resource_len(const struct device_node *np,
-				     unsigned int index);
-#endif /* CONFIG_PPC_DCR */
-#endif /* __ASSEMBLY__ */
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_DCR_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/debug.h b/ANDROID_3.4.5/arch/powerpc/include/asm/debug.h
deleted file mode 100644
index 716d2f08..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/debug.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
- */
-#ifndef _ASM_POWERPC_DEBUG_H
-#define _ASM_POWERPC_DEBUG_H
-
-struct pt_regs;
-
-extern struct dentry *powerpc_debugfs_root;
-
-#if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
-
-extern int (*__debugger)(struct pt_regs *regs);
-extern int (*__debugger_ipi)(struct pt_regs *regs);
-extern int (*__debugger_bpt)(struct pt_regs *regs);
-extern int (*__debugger_sstep)(struct pt_regs *regs);
-extern int (*__debugger_iabr_match)(struct pt_regs *regs);
-extern int (*__debugger_dabr_match)(struct pt_regs *regs);
-extern int (*__debugger_fault_handler)(struct pt_regs *regs);
-
-#define DEBUGGER_BOILERPLATE(__NAME) \
-static inline int __NAME(struct pt_regs *regs) \
-{ \
-	if (unlikely(__ ## __NAME)) \
-		return __ ## __NAME(regs); \
-	return 0; \
-}
-
-DEBUGGER_BOILERPLATE(debugger)
-DEBUGGER_BOILERPLATE(debugger_ipi)
-DEBUGGER_BOILERPLATE(debugger_bpt)
-DEBUGGER_BOILERPLATE(debugger_sstep)
-DEBUGGER_BOILERPLATE(debugger_iabr_match)
-DEBUGGER_BOILERPLATE(debugger_dabr_match)
-DEBUGGER_BOILERPLATE(debugger_fault_handler)
-
-#else
-static inline int debugger(struct pt_regs *regs) { return 0; }
-static inline int debugger_ipi(struct pt_regs *regs) { return 0; }
-static inline int debugger_bpt(struct pt_regs *regs) { return 0; }
-static inline int debugger_sstep(struct pt_regs *regs) { return 0; }
-static inline int debugger_iabr_match(struct pt_regs *regs) { return 0; }
-static inline int debugger_dabr_match(struct pt_regs *regs) { return 0; }
-static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; }
-#endif
-
-extern int set_dabr(unsigned long dabr);
-#ifdef CONFIG_PPC_ADV_DEBUG_REGS
-extern void do_send_trap(struct pt_regs *regs, unsigned long address,
-			 unsigned long error_code, int signal_code, int brkpt);
-#else
-extern void do_dabr(struct pt_regs *regs, unsigned long address,
-		    unsigned long error_code);
-#endif
-
-#endif /* _ASM_POWERPC_DEBUG_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/delay.h b/ANDROID_3.4.5/arch/powerpc/include/asm/delay.h
deleted file mode 100644
index 52e4d54d..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/delay.h
+++ /dev/null
@@ -1,72 +0,0 @@
-#ifndef _ASM_POWERPC_DELAY_H
-#define _ASM_POWERPC_DELAY_H
-#ifdef __KERNEL__
-
-#include <asm/time.h>
-
-/*
- * Copyright 1996, Paul Mackerras.
- * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- *
- * PPC64 Support added by Dave Engebretsen, Todd Inglett, Mike Corrigan,
- * Anton Blanchard.
- */
-
-extern void __delay(unsigned long loops);
-extern void udelay(unsigned long usecs);
-
-/*
- * On shared processor machines the generic implementation of mdelay can
- * result in large errors. While each iteration of the loop inside mdelay
- * is supposed to take 1ms, the hypervisor could sleep our partition for
- * longer (eg 10ms). With the right timing these errors can add up.
- *
- * Since there is no 32bit overflow issue on 64bit kernels, just call
- * udelay directly.
- */
-#ifdef CONFIG_PPC64
-#define mdelay(n)	udelay((n) * 1000)
-#endif
-
-/**
- * spin_event_timeout - spin until a condition gets true or a timeout elapses
- * @condition: a C expression to evalate
- * @timeout: timeout, in microseconds
- * @delay: the number of microseconds to delay between each evaluation of
- *         @condition
- *
- * The process spins until the condition evaluates to true (non-zero) or the
- * timeout elapses.  The return value of this macro is the value of
- * @condition when the loop terminates. This allows you to determine the cause
- * of the loop terminates.  If the return value is zero, then you know a
- * timeout has occurred.
- *
- * This primary purpose of this macro is to poll on a hardware register
- * until a status bit changes.  The timeout ensures that the loop still
- * terminates even if the bit never changes.  The delay is for devices that
- * need a delay in between successive reads.
- *
- * gcc will optimize out the if-statement if @delay is a constant.
- */
-#define spin_event_timeout(condition, timeout, delay)                          \
-({                                                                             \
-	typeof(condition) __ret;                                               \
-	unsigned long __loops = tb_ticks_per_usec * timeout;                   \
-	unsigned long __start = get_tbl();                                     \
-	while (!(__ret = (condition)) && (tb_ticks_since(__start) <= __loops)) \
-		if (delay)                                                     \
-			udelay(delay);                                         \
-		else                                                           \
-			cpu_relax();                                           \
-	if (!__ret)                                                            \
-		__ret = (condition);                                           \
-	__ret;		                                                       \
-})
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_DELAY_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/device.h b/ANDROID_3.4.5/arch/powerpc/include/asm/device.h
deleted file mode 100644
index 63d5ca49..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/device.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Arch specific extensions to struct device
- *
- * This file is released under the GPLv2
- */
-#ifndef _ASM_POWERPC_DEVICE_H
-#define _ASM_POWERPC_DEVICE_H
-
-struct dma_map_ops;
-struct device_node;
-
-/*
- * Arch extensions to struct device.
- *
- * When adding fields, consider macio_add_one_device in
- * drivers/macintosh/macio_asic.c
- */
-struct dev_archdata {
-	/* DMA operations on that device */
-	struct dma_map_ops	*dma_ops;
-
-	/*
-	 * When an iommu is in use, dma_data is used as a ptr to the base of the
-	 * iommu_table.  Otherwise, it is a simple numerical offset.
-	 */
-	union {
-		dma_addr_t	dma_offset;
-		void		*iommu_table_base;
-	} dma_data;
-
-#ifdef CONFIG_SWIOTLB
-	dma_addr_t		max_direct_dma_addr;
-#endif
-#ifdef CONFIG_EEH
-	struct eeh_dev		*edev;
-#endif
-};
-
-struct pdev_archdata {
-	u64 dma_mask;
-};
-
-#define ARCH_HAS_DMA_GET_REQUIRED_MASK
-
-#endif /* _ASM_POWERPC_DEVICE_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/disassemble.h b/ANDROID_3.4.5/arch/powerpc/include/asm/disassemble.h
deleted file mode 100644
index 9b198d1b..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/disassemble.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, version 2, as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
- *
- * Copyright IBM Corp. 2008
- *
- * Authors: Hollis Blanchard <hollisb@us.ibm.com>
- */
-
-#ifndef __ASM_PPC_DISASSEMBLE_H__
-#define __ASM_PPC_DISASSEMBLE_H__
-
-#include <linux/types.h>
-
-static inline unsigned int get_op(u32 inst)
-{
-	return inst >> 26;
-}
-
-static inline unsigned int get_xop(u32 inst)
-{
-	return (inst >> 1) & 0x3ff;
-}
-
-static inline unsigned int get_sprn(u32 inst)
-{
-	return ((inst >> 16) & 0x1f) | ((inst >> 6) & 0x3e0);
-}
-
-static inline unsigned int get_dcrn(u32 inst)
-{
-	return ((inst >> 16) & 0x1f) | ((inst >> 6) & 0x3e0);
-}
-
-static inline unsigned int get_rt(u32 inst)
-{
-	return (inst >> 21) & 0x1f;
-}
-
-static inline unsigned int get_rs(u32 inst)
-{
-	return (inst >> 21) & 0x1f;
-}
-
-static inline unsigned int get_ra(u32 inst)
-{
-	return (inst >> 16) & 0x1f;
-}
-
-static inline unsigned int get_rb(u32 inst)
-{
-	return (inst >> 11) & 0x1f;
-}
-
-static inline unsigned int get_rc(u32 inst)
-{
-	return inst & 0x1;
-}
-
-static inline unsigned int get_ws(u32 inst)
-{
-	return (inst >> 11) & 0x1f;
-}
-
-static inline unsigned int get_d(u32 inst)
-{
-	return inst & 0xffff;
-}
-
-#endif /* __ASM_PPC_DISASSEMBLE_H__ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/div64.h b/ANDROID_3.4.5/arch/powerpc/include/asm/div64.h
deleted file mode 100644
index 6cd978ce..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/div64.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/div64.h>
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/dma-mapping.h b/ANDROID_3.4.5/arch/powerpc/include/asm/dma-mapping.h
deleted file mode 100644
index 62678e36..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/dma-mapping.h
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- * Copyright (C) 2004 IBM
- *
- * Implements the generic device dma API for powerpc.
- * the pci and vio busses
- */
-#ifndef _ASM_DMA_MAPPING_H
-#define _ASM_DMA_MAPPING_H
-#ifdef __KERNEL__
-
-#include <linux/types.h>
-#include <linux/cache.h>
-/* need struct page definitions */
-#include <linux/mm.h>
-#include <linux/scatterlist.h>
-#include <linux/dma-attrs.h>
-#include <linux/dma-debug.h>
-#include <asm/io.h>
-#include <asm/swiotlb.h>
-
-#define DMA_ERROR_CODE		(~(dma_addr_t)0x0)
-
-/* Some dma direct funcs must be visible for use in other dma_ops */
-extern void *dma_direct_alloc_coherent(struct device *dev, size_t size,
-				       dma_addr_t *dma_handle, gfp_t flag,
-				       struct dma_attrs *attrs);
-extern void dma_direct_free_coherent(struct device *dev, size_t size,
-				     void *vaddr, dma_addr_t dma_handle,
-				     struct dma_attrs *attrs);
-
-
-#ifdef CONFIG_NOT_COHERENT_CACHE
-/*
- * DMA-consistent mapping functions for PowerPCs that don't support
- * cache snooping.  These allocate/free a region of uncached mapped
- * memory space for use with DMA devices.  Alternatively, you could
- * allocate the space "normally" and use the cache management functions
- * to ensure it is consistent.
- */
-struct device;
-extern void *__dma_alloc_coherent(struct device *dev, size_t size,
-				  dma_addr_t *handle, gfp_t gfp);
-extern void __dma_free_coherent(size_t size, void *vaddr);
-extern void __dma_sync(void *vaddr, size_t size, int direction);
-extern void __dma_sync_page(struct page *page, unsigned long offset,
-				 size_t size, int direction);
-extern unsigned long __dma_get_coherent_pfn(unsigned long cpu_addr);
-
-#else /* ! CONFIG_NOT_COHERENT_CACHE */
-/*
- * Cache coherent cores.
- */
-
-#define __dma_alloc_coherent(dev, gfp, size, handle)	NULL
-#define __dma_free_coherent(size, addr)		((void)0)
-#define __dma_sync(addr, size, rw)		((void)0)
-#define __dma_sync_page(pg, off, sz, rw)	((void)0)
-
-#endif /* ! CONFIG_NOT_COHERENT_CACHE */
-
-static inline unsigned long device_to_mask(struct device *dev)
-{
-	if (dev->dma_mask && *dev->dma_mask)
-		return *dev->dma_mask;
-	/* Assume devices without mask can take 32 bit addresses */
-	return 0xfffffffful;
-}
-
-/*
- * Available generic sets of operations
- */
-#ifdef CONFIG_PPC64
-extern struct dma_map_ops dma_iommu_ops;
-#endif
-extern struct dma_map_ops dma_direct_ops;
-
-static inline struct dma_map_ops *get_dma_ops(struct device *dev)
-{
-	/* We don't handle the NULL dev case for ISA for now. We could
-	 * do it via an out of line call but it is not needed for now. The
-	 * only ISA DMA device we support is the floppy and we have a hack
-	 * in the floppy driver directly to get a device for us.
-	 */
-	if (unlikely(dev == NULL))
-		return NULL;
-
-	return dev->archdata.dma_ops;
-}
-
-static inline void set_dma_ops(struct device *dev, struct dma_map_ops *ops)
-{
-	dev->archdata.dma_ops = ops;
-}
-
-/*
- * get_dma_offset()
- *
- * Get the dma offset on configurations where the dma address can be determined
- * from the physical address by looking at a simple offset.  Direct dma and
- * swiotlb use this function, but it is typically not used by implementations
- * with an iommu.
- */
-static inline dma_addr_t get_dma_offset(struct device *dev)
-{
-	if (dev)
-		return dev->archdata.dma_data.dma_offset;
-
-	return PCI_DRAM_OFFSET;
-}
-
-static inline void set_dma_offset(struct device *dev, dma_addr_t off)
-{
-	if (dev)
-		dev->archdata.dma_data.dma_offset = off;
-}
-
-/* this will be removed soon */
-#define flush_write_buffers()
-
-#include <asm-generic/dma-mapping-common.h>
-
-static inline int dma_supported(struct device *dev, u64 mask)
-{
-	struct dma_map_ops *dma_ops = get_dma_ops(dev);
-
-	if (unlikely(dma_ops == NULL))
-		return 0;
-	if (dma_ops->dma_supported == NULL)
-		return 1;
-	return dma_ops->dma_supported(dev, mask);
-}
-
-extern int dma_set_mask(struct device *dev, u64 dma_mask);
-
-#define dma_alloc_coherent(d,s,h,f)	dma_alloc_attrs(d,s,h,f,NULL)
-
-static inline void *dma_alloc_attrs(struct device *dev, size_t size,
-				    dma_addr_t *dma_handle, gfp_t flag,
-				    struct dma_attrs *attrs)
-{
-	struct dma_map_ops *dma_ops = get_dma_ops(dev);
-	void *cpu_addr;
-
-	BUG_ON(!dma_ops);
-
-	cpu_addr = dma_ops->alloc(dev, size, dma_handle, flag, attrs);
-
-	debug_dma_alloc_coherent(dev, size, *dma_handle, cpu_addr);
-
-	return cpu_addr;
-}
-
-#define dma_free_coherent(d,s,c,h) dma_free_attrs(d,s,c,h,NULL)
-
-static inline void dma_free_attrs(struct device *dev, size_t size,
-				  void *cpu_addr, dma_addr_t dma_handle,
-				  struct dma_attrs *attrs)
-{
-	struct dma_map_ops *dma_ops = get_dma_ops(dev);
-
-	BUG_ON(!dma_ops);
-
-	debug_dma_free_coherent(dev, size, cpu_addr, dma_handle);
-
-	dma_ops->free(dev, size, cpu_addr, dma_handle, attrs);
-}
-
-static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
-{
-	struct dma_map_ops *dma_ops = get_dma_ops(dev);
-
-	if (dma_ops->mapping_error)
-		return dma_ops->mapping_error(dev, dma_addr);
-
-#ifdef CONFIG_PPC64
-	return (dma_addr == DMA_ERROR_CODE);
-#else
-	return 0;
-#endif
-}
-
-static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
-{
-#ifdef CONFIG_SWIOTLB
-	struct dev_archdata *sd = &dev->archdata;
-
-	if (sd->max_direct_dma_addr && addr + size > sd->max_direct_dma_addr)
-		return 0;
-#endif
-
-	if (!dev->dma_mask)
-		return 0;
-
-	return addr + size - 1 <= *dev->dma_mask;
-}
-
-static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
-{
-	return paddr + get_dma_offset(dev);
-}
-
-static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
-{
-	return daddr - get_dma_offset(dev);
-}
-
-#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
-#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
-
-extern int dma_mmap_coherent(struct device *, struct vm_area_struct *,
-			     void *, dma_addr_t, size_t);
-#define ARCH_HAS_DMA_MMAP_COHERENT
-
-
-static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
-		enum dma_data_direction direction)
-{
-	BUG_ON(direction == DMA_NONE);
-	__dma_sync(vaddr, size, (int)direction);
-}
-
-#endif /* __KERNEL__ */
-#endif	/* _ASM_DMA_MAPPING_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/dma.h b/ANDROID_3.4.5/arch/powerpc/include/asm/dma.h
deleted file mode 100644
index f6813e91..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/dma.h
+++ /dev/null
@@ -1,355 +0,0 @@
-#ifndef _ASM_POWERPC_DMA_H
-#define _ASM_POWERPC_DMA_H
-#ifdef __KERNEL__
-
-/*
- * Defines for using and allocating dma channels.
- * Written by Hennus Bergman, 1992.
- * High DMA channel support & info by Hannu Savolainen
- * and John Boyd, Nov. 1992.
- * Changes for ppc sound by Christoph Nadig
- */
-
-/*
- * Note: Adapted for PowerPC by Gary Thomas
- * Modified by Cort Dougan <cort@cs.nmt.edu>
- *
- * None of this really applies for Power Macintoshes.  There is
- * basically just enough here to get kernel/dma.c to compile.
- *
- * There may be some comments or restrictions made here which are
- * not valid for the PReP platform.  Take what you read
- * with a grain of salt.
- */
-
-#include <asm/io.h>
-#include <linux/spinlock.h>
-
-#ifndef MAX_DMA_CHANNELS
-#define MAX_DMA_CHANNELS	8
-#endif
-
-/* The maximum address that we can perform a DMA transfer to on this platform */
-/* Doesn't really apply... */
-#define MAX_DMA_ADDRESS		(~0UL)
-
-#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
-#define dma_outb	outb_p
-#else
-#define dma_outb	outb
-#endif
-
-#define dma_inb		inb
-
-/*
- * NOTES about DMA transfers:
- *
- *  controller 1: channels 0-3, byte operations, ports 00-1F
- *  controller 2: channels 4-7, word operations, ports C0-DF
- *
- *  - ALL registers are 8 bits only, regardless of transfer size
- *  - channel 4 is not used - cascades 1 into 2.
- *  - channels 0-3 are byte - addresses/counts are for physical bytes
- *  - channels 5-7 are word - addresses/counts are for physical words
- *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
- *  - transfer count loaded to registers is 1 less than actual count
- *  - controller 2 offsets are all even (2x offsets for controller 1)
- *  - page registers for 5-7 don't use data bit 0, represent 128K pages
- *  - page registers for 0-3 use bit 0, represent 64K pages
- *
- * On PReP, DMA transfers are limited to the lower 16MB of _physical_ memory.
- * On CHRP, the W83C553F (and VLSI Tollgate?) support full 32 bit addressing.
- * Note that addresses loaded into registers must be _physical_ addresses,
- * not logical addresses (which may differ if paging is active).
- *
- *  Address mapping for channels 0-3:
- *
- *   A23 ... A16 A15 ... A8  A7 ... A0    (Physical addresses)
- *    |  ...  |   |  ... |   |  ... |
- *    |  ...  |   |  ... |   |  ... |
- *    |  ...  |   |  ... |   |  ... |
- *   P7  ...  P0  A7 ... A0  A7 ... A0
- * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
- *
- *  Address mapping for channels 5-7:
- *
- *   A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0    (Physical addresses)
- *    |  ...  |   \   \   ... \  \  \  ... \  \
- *    |  ...  |    \   \   ... \  \  \  ... \  (not used)
- *    |  ...  |     \   \   ... \  \  \  ... \
- *   P7  ...  P1 (0) A7 A6  ... A0 A7 A6 ... A0
- * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
- *
- * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
- * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
- * the hardware level, so odd-byte transfers aren't possible).
- *
- * Transfer count (_not # bytes_) is limited to 64K, represented as actual
- * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
- * and up to 128K bytes may be transferred on channels 5-7 in one operation.
- *
- */
-
-/* 8237 DMA controllers */
-#define IO_DMA1_BASE	0x00	/* 8 bit slave DMA, channels 0..3 */
-#define IO_DMA2_BASE	0xC0	/* 16 bit master DMA, ch 4(=slave input)..7 */
-
-/* DMA controller registers */
-#define DMA1_CMD_REG		0x08	/* command register (w) */
-#define DMA1_STAT_REG		0x08	/* status register (r) */
-#define DMA1_REQ_REG		0x09	/* request register (w) */
-#define DMA1_MASK_REG		0x0A	/* single-channel mask (w) */
-#define DMA1_MODE_REG		0x0B	/* mode register (w) */
-#define DMA1_CLEAR_FF_REG	0x0C	/* clear pointer flip-flop (w) */
-#define DMA1_TEMP_REG		0x0D	/* Temporary Register (r) */
-#define DMA1_RESET_REG		0x0D	/* Master Clear (w) */
-#define DMA1_CLR_MASK_REG	0x0E	/* Clear Mask */
-#define DMA1_MASK_ALL_REG	0x0F	/* all-channels mask (w) */
-
-#define DMA2_CMD_REG		0xD0	/* command register (w) */
-#define DMA2_STAT_REG		0xD0	/* status register (r) */
-#define DMA2_REQ_REG		0xD2	/* request register (w) */
-#define DMA2_MASK_REG		0xD4	/* single-channel mask (w) */
-#define DMA2_MODE_REG		0xD6	/* mode register (w) */
-#define DMA2_CLEAR_FF_REG	0xD8	/* clear pointer flip-flop (w) */
-#define DMA2_TEMP_REG		0xDA	/* Temporary Register (r) */
-#define DMA2_RESET_REG		0xDA	/* Master Clear (w) */
-#define DMA2_CLR_MASK_REG	0xDC	/* Clear Mask */
-#define DMA2_MASK_ALL_REG	0xDE	/* all-channels mask (w) */
-
-#define DMA_ADDR_0		0x00	/* DMA address registers */
-#define DMA_ADDR_1		0x02
-#define DMA_ADDR_2		0x04
-#define DMA_ADDR_3		0x06
-#define DMA_ADDR_4		0xC0
-#define DMA_ADDR_5		0xC4
-#define DMA_ADDR_6		0xC8
-#define DMA_ADDR_7		0xCC
-
-#define DMA_CNT_0		0x01	/* DMA count registers */
-#define DMA_CNT_1		0x03
-#define DMA_CNT_2		0x05
-#define DMA_CNT_3		0x07
-#define DMA_CNT_4		0xC2
-#define DMA_CNT_5		0xC6
-#define DMA_CNT_6		0xCA
-#define DMA_CNT_7		0xCE
-
-#define DMA_LO_PAGE_0		0x87	/* DMA page registers */
-#define DMA_LO_PAGE_1		0x83
-#define DMA_LO_PAGE_2		0x81
-#define DMA_LO_PAGE_3		0x82
-#define DMA_LO_PAGE_5		0x8B
-#define DMA_LO_PAGE_6		0x89
-#define DMA_LO_PAGE_7		0x8A
-
-#define DMA_HI_PAGE_0		0x487	/* DMA page registers */
-#define DMA_HI_PAGE_1		0x483
-#define DMA_HI_PAGE_2		0x481
-#define DMA_HI_PAGE_3		0x482
-#define DMA_HI_PAGE_5		0x48B
-#define DMA_HI_PAGE_6		0x489
-#define DMA_HI_PAGE_7		0x48A
-
-#define DMA1_EXT_REG		0x40B
-#define DMA2_EXT_REG		0x4D6
-
-#ifndef __powerpc64__
-    /* in arch/ppc/kernel/setup.c -- Cort */
-    extern unsigned int DMA_MODE_WRITE;
-    extern unsigned int DMA_MODE_READ;
-    extern unsigned long ISA_DMA_THRESHOLD;
-#else
-    #define DMA_MODE_READ	0x44	/* I/O to memory, no autoinit, increment, single mode */
-    #define DMA_MODE_WRITE	0x48	/* memory to I/O, no autoinit, increment, single mode */
-#endif
-
-#define DMA_MODE_CASCADE	0xC0	/* pass thru DREQ->HRQ, DACK<-HLDA only */
-
-#define DMA_AUTOINIT		0x10
-
-extern spinlock_t dma_spin_lock;
-
-static __inline__ unsigned long claim_dma_lock(void)
-{
-	unsigned long flags;
-	spin_lock_irqsave(&dma_spin_lock, flags);
-	return flags;
-}
-
-static __inline__ void release_dma_lock(unsigned long flags)
-{
-	spin_unlock_irqrestore(&dma_spin_lock, flags);
-}
-
-/* enable/disable a specific DMA channel */
-static __inline__ void enable_dma(unsigned int dmanr)
-{
-	unsigned char ucDmaCmd = 0x00;
-
-	if (dmanr != 4) {
-		dma_outb(0, DMA2_MASK_REG);	/* This may not be enabled */
-		dma_outb(ucDmaCmd, DMA2_CMD_REG);	/* Enable group */
-	}
-	if (dmanr <= 3) {
-		dma_outb(dmanr, DMA1_MASK_REG);
-		dma_outb(ucDmaCmd, DMA1_CMD_REG);	/* Enable group */
-	} else {
-		dma_outb(dmanr & 3, DMA2_MASK_REG);
-	}
-}
-
-static __inline__ void disable_dma(unsigned int dmanr)
-{
-	if (dmanr <= 3)
-		dma_outb(dmanr | 4, DMA1_MASK_REG);
-	else
-		dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
-}
-
-/* Clear the 'DMA Pointer Flip Flop'.
- * Write 0 for LSB/MSB, 1 for MSB/LSB access.
- * Use this once to initialize the FF to a known state.
- * After that, keep track of it. :-)
- * --- In order to do that, the DMA routines below should ---
- * --- only be used while interrupts are disabled! ---
- */
-static __inline__ void clear_dma_ff(unsigned int dmanr)
-{
-	if (dmanr <= 3)
-		dma_outb(0, DMA1_CLEAR_FF_REG);
-	else
-		dma_outb(0, DMA2_CLEAR_FF_REG);
-}
-
-/* set mode (above) for a specific DMA channel */
-static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
-{
-	if (dmanr <= 3)
-		dma_outb(mode | dmanr, DMA1_MODE_REG);
-	else
-		dma_outb(mode | (dmanr & 3), DMA2_MODE_REG);
-}
-
-/* Set only the page register bits of the transfer address.
- * This is used for successive transfers when we know the contents of
- * the lower 16 bits of the DMA current address register, but a 64k boundary
- * may have been crossed.
- */
-static __inline__ void set_dma_page(unsigned int dmanr, int pagenr)
-{
-	switch (dmanr) {
-	case 0:
-		dma_outb(pagenr, DMA_LO_PAGE_0);
-		dma_outb(pagenr >> 8, DMA_HI_PAGE_0);
-		break;
-	case 1:
-		dma_outb(pagenr, DMA_LO_PAGE_1);
-		dma_outb(pagenr >> 8, DMA_HI_PAGE_1);
-		break;
-	case 2:
-		dma_outb(pagenr, DMA_LO_PAGE_2);
-		dma_outb(pagenr >> 8, DMA_HI_PAGE_2);
-		break;
-	case 3:
-		dma_outb(pagenr, DMA_LO_PAGE_3);
-		dma_outb(pagenr >> 8, DMA_HI_PAGE_3);
-		break;
-	case 5:
-		dma_outb(pagenr & 0xfe, DMA_LO_PAGE_5);
-		dma_outb(pagenr >> 8, DMA_HI_PAGE_5);
-		break;
-	case 6:
-		dma_outb(pagenr & 0xfe, DMA_LO_PAGE_6);
-		dma_outb(pagenr >> 8, DMA_HI_PAGE_6);
-		break;
-	case 7:
-		dma_outb(pagenr & 0xfe, DMA_LO_PAGE_7);
-		dma_outb(pagenr >> 8, DMA_HI_PAGE_7);
-		break;
-	}
-}
-
-/* Set transfer address & page bits for specific DMA channel.
- * Assumes dma flipflop is clear.
- */
-static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int phys)
-{
-	if (dmanr <= 3) {
-		dma_outb(phys & 0xff,
-			 ((dmanr & 3) << 1) + IO_DMA1_BASE);
-		dma_outb((phys >> 8) & 0xff,
-			 ((dmanr & 3) << 1) + IO_DMA1_BASE);
-	} else {
-		dma_outb((phys >> 1) & 0xff,
-			 ((dmanr & 3) << 2) + IO_DMA2_BASE);
-		dma_outb((phys >> 9) & 0xff,
-			 ((dmanr & 3) << 2) + IO_DMA2_BASE);
-	}
-	set_dma_page(dmanr, phys >> 16);
-}
-
-
-/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
- * a specific DMA channel.
- * You must ensure the parameters are valid.
- * NOTE: from a manual: "the number of transfers is one more
- * than the initial word count"! This is taken into account.
- * Assumes dma flip-flop is clear.
- * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
- */
-static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
-{
-	count--;
-	if (dmanr <= 3) {
-		dma_outb(count & 0xff,
-			 ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
-		dma_outb((count >> 8) & 0xff,
-			 ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
-	} else {
-		dma_outb((count >> 1) & 0xff,
-			 ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
-		dma_outb((count >> 9) & 0xff,
-			 ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
-	}
-}
-
-
-/* Get DMA residue count. After a DMA transfer, this
- * should return zero. Reading this while a DMA transfer is
- * still in progress will return unpredictable results.
- * If called before the channel has been used, it may return 1.
- * Otherwise, it returns the number of _bytes_ left to transfer.
- *
- * Assumes DMA flip-flop is clear.
- */
-static __inline__ int get_dma_residue(unsigned int dmanr)
-{
-	unsigned int io_port = (dmanr <= 3)
-	    ? ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE
-	    : ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE;
-
-	/* using short to get 16-bit wrap around */
-	unsigned short count;
-
-	count = 1 + dma_inb(io_port);
-	count += dma_inb(io_port) << 8;
-
-	return (dmanr <= 3) ? count : (count << 1);
-}
-
-/* These are in kernel/dma.c: */
-
-/* reserve a DMA channel */
-extern int request_dma(unsigned int dmanr, const char *device_id);
-/* release it again */
-extern void free_dma(unsigned int dmanr);
-
-#ifdef CONFIG_PCI
-extern int isa_dma_bridge_buggy;
-#else
-#define isa_dma_bridge_buggy	(0)
-#endif
-
-#endif /* __KERNEL__ */
-#endif	/* _ASM_POWERPC_DMA_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/edac.h b/ANDROID_3.4.5/arch/powerpc/include/asm/edac.h
deleted file mode 100644
index 6ead88bb..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/edac.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * PPC EDAC common defs
- *
- * Author: Dave Jiang <djiang@mvista.com>
- *
- * 2007 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef ASM_EDAC_H
-#define ASM_EDAC_H
-/*
- * ECC atomic, DMA, SMP and interrupt safe scrub function.
- * Implements the per arch atomic_scrub() that EDAC use for software
- * ECC scrubbing.  It reads memory and then writes back the original
- * value, allowing the hardware to detect and correct memory errors.
- */
-static __inline__ void atomic_scrub(void *va, u32 size)
-{
-	unsigned int *virt_addr = va;
-	unsigned int temp;
-	unsigned int i;
-
-	for (i = 0; i < size / sizeof(*virt_addr); i++, virt_addr++) {
-		/* Very carefully read and write to memory atomically
-		 * so we are interrupt, DMA and SMP safe.
-		 */
-		__asm__ __volatile__ ("\n\
-				1:	lwarx	%0,0,%1\n\
-					stwcx.	%0,0,%1\n\
-					bne-	1b\n\
-					isync"
-					: "=&r"(temp)
-					: "r"(virt_addr)
-					: "cr0", "memory");
-	}
-}
-
-#endif
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/eeh.h b/ANDROID_3.4.5/arch/powerpc/include/asm/eeh.h
deleted file mode 100644
index d60f9981..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/eeh.h
+++ /dev/null
@@ -1,291 +0,0 @@
-/*
- * Copyright (C) 2001  Dave Engebretsen & Todd Inglett IBM Corporation.
- * Copyright 2001-2012 IBM Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-
-#ifndef _POWERPC_EEH_H
-#define _POWERPC_EEH_H
-#ifdef __KERNEL__
-
-#include <linux/init.h>
-#include <linux/list.h>
-#include <linux/string.h>
-
-struct pci_dev;
-struct pci_bus;
-struct device_node;
-
-#ifdef CONFIG_EEH
-
-/*
- * The struct is used to trace EEH state for the associated
- * PCI device node or PCI device. In future, it might
- * represent PE as well so that the EEH device to form
- * another tree except the currently existing tree of PCI
- * buses and PCI devices
- */
-#define EEH_MODE_SUPPORTED	(1<<0)	/* EEH supported on the device	*/
-#define EEH_MODE_NOCHECK	(1<<1)	/* EEH check should be skipped	*/
-#define EEH_MODE_ISOLATED	(1<<2)	/* The device has been isolated	*/
-#define EEH_MODE_RECOVERING	(1<<3)	/* Recovering the device	*/
-#define EEH_MODE_IRQ_DISABLED	(1<<4)	/* Interrupt disabled		*/
-
-struct eeh_dev {
-	int mode;			/* EEH mode			*/
-	int class_code;			/* Class code of the device	*/
-	int config_addr;		/* Config address		*/
-	int pe_config_addr;		/* PE config address		*/
-	int check_count;		/* Times of ignored error	*/
-	int freeze_count;		/* Times of froze up		*/
-	int false_positives;		/* Times of reported #ff's	*/
-	u32 config_space[16];		/* Saved PCI config space	*/
-	struct pci_controller *phb;	/* Associated PHB		*/
-	struct device_node *dn;		/* Associated device node	*/
-	struct pci_dev *pdev;		/* Associated PCI device	*/
-};
-
-static inline struct device_node *eeh_dev_to_of_node(struct eeh_dev *edev)
-{
-	return edev->dn;
-}
-
-static inline struct pci_dev *eeh_dev_to_pci_dev(struct eeh_dev *edev)
-{
-	return edev->pdev;
-}
-
-/*
- * The struct is used to trace the registered EEH operation
- * callback functions. Actually, those operation callback
- * functions are heavily platform dependent. That means the
- * platform should register its own EEH operation callback
- * functions before any EEH further operations.
- */
-#define EEH_OPT_DISABLE		0	/* EEH disable	*/
-#define EEH_OPT_ENABLE		1	/* EEH enable	*/
-#define EEH_OPT_THAW_MMIO	2	/* MMIO enable	*/
-#define EEH_OPT_THAW_DMA	3	/* DMA enable	*/
-#define EEH_STATE_UNAVAILABLE	(1 << 0)	/* State unavailable	*/
-#define EEH_STATE_NOT_SUPPORT	(1 << 1)	/* EEH not supported	*/
-#define EEH_STATE_RESET_ACTIVE	(1 << 2)	/* Active reset		*/
-#define EEH_STATE_MMIO_ACTIVE	(1 << 3)	/* Active MMIO		*/
-#define EEH_STATE_DMA_ACTIVE	(1 << 4)	/* Active DMA		*/
-#define EEH_STATE_MMIO_ENABLED	(1 << 5)	/* MMIO enabled		*/
-#define EEH_STATE_DMA_ENABLED	(1 << 6)	/* DMA enabled		*/
-#define EEH_RESET_DEACTIVATE	0	/* Deactivate the PE reset	*/
-#define EEH_RESET_HOT		1	/* Hot reset			*/
-#define EEH_RESET_FUNDAMENTAL	3	/* Fundamental reset		*/
-#define EEH_LOG_TEMP		1	/* EEH temporary error log	*/
-#define EEH_LOG_PERM		2	/* EEH permanent error log	*/
-
-struct eeh_ops {
-	char *name;
-	int (*init)(void);
-	int (*set_option)(struct device_node *dn, int option);
-	int (*get_pe_addr)(struct device_node *dn);
-	int (*get_state)(struct device_node *dn, int *state);
-	int (*reset)(struct device_node *dn, int option);
-	int (*wait_state)(struct device_node *dn, int max_wait);
-	int (*get_log)(struct device_node *dn, int severity, char *drv_log, unsigned long len);
-	int (*configure_bridge)(struct device_node *dn);
-	int (*read_config)(struct device_node *dn, int where, int size, u32 *val);
-	int (*write_config)(struct device_node *dn, int where, int size, u32 val);
-};
-
-extern struct eeh_ops *eeh_ops;
-extern int eeh_subsystem_enabled;
-
-/*
- * Max number of EEH freezes allowed before we consider the device
- * to be permanently disabled.
- */
-#define EEH_MAX_ALLOWED_FREEZES 5
-
-void * __devinit eeh_dev_init(struct device_node *dn, void *data);
-void __devinit eeh_dev_phb_init_dynamic(struct pci_controller *phb);
-void __init eeh_dev_phb_init(void);
-void __init eeh_init(void);
-#ifdef CONFIG_PPC_PSERIES
-int __init eeh_pseries_init(void);
-#endif
-int __init eeh_ops_register(struct eeh_ops *ops);
-int __exit eeh_ops_unregister(const char *name);
-unsigned long eeh_check_failure(const volatile void __iomem *token,
-				unsigned long val);
-int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev);
-void __init pci_addr_cache_build(void);
-void eeh_add_device_tree_early(struct device_node *);
-void eeh_add_device_tree_late(struct pci_bus *);
-void eeh_remove_bus_device(struct pci_dev *);
-
-/**
- * EEH_POSSIBLE_ERROR() -- test for possible MMIO failure.
- *
- * If this macro yields TRUE, the caller relays to eeh_check_failure()
- * which does further tests out of line.
- */
-#define EEH_POSSIBLE_ERROR(val, type)	((val) == (type)~0 && eeh_subsystem_enabled)
-
-/*
- * Reads from a device which has been isolated by EEH will return
- * all 1s.  This macro gives an all-1s value of the given size (in
- * bytes: 1, 2, or 4) for comparing with the result of a read.
- */
-#define EEH_IO_ERROR_VALUE(size)	(~0U >> ((4 - (size)) * 8))
-
-#else /* !CONFIG_EEH */
-
-static inline void *eeh_dev_init(struct device_node *dn, void *data)
-{
-	return NULL;
-}
-
-static inline void eeh_dev_phb_init_dynamic(struct pci_controller *phb) { }
-
-static inline void eeh_dev_phb_init(void) { }
-
-static inline void eeh_init(void) { }
-
-#ifdef CONFIG_PPC_PSERIES
-static inline int eeh_pseries_init(void)
-{
-	return 0;
-}
-#endif /* CONFIG_PPC_PSERIES */
-
-static inline unsigned long eeh_check_failure(const volatile void __iomem *token, unsigned long val)
-{
-	return val;
-}
-
-static inline int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev)
-{
-	return 0;
-}
-
-static inline void pci_addr_cache_build(void) { }
-
-static inline void eeh_add_device_tree_early(struct device_node *dn) { }
-
-static inline void eeh_add_device_tree_late(struct pci_bus *bus) { }
-
-static inline void eeh_remove_bus_device(struct pci_dev *dev) { }
-#define EEH_POSSIBLE_ERROR(val, type) (0)
-#define EEH_IO_ERROR_VALUE(size) (-1UL)
-#endif /* CONFIG_EEH */
-
-#ifdef CONFIG_PPC64
-/*
- * MMIO read/write operations with EEH support.
- */
-static inline u8 eeh_readb(const volatile void __iomem *addr)
-{
-	u8 val = in_8(addr);
-	if (EEH_POSSIBLE_ERROR(val, u8))
-		return eeh_check_failure(addr, val);
-	return val;
-}
-
-static inline u16 eeh_readw(const volatile void __iomem *addr)
-{
-	u16 val = in_le16(addr);
-	if (EEH_POSSIBLE_ERROR(val, u16))
-		return eeh_check_failure(addr, val);
-	return val;
-}
-
-static inline u32 eeh_readl(const volatile void __iomem *addr)
-{
-	u32 val = in_le32(addr);
-	if (EEH_POSSIBLE_ERROR(val, u32))
-		return eeh_check_failure(addr, val);
-	return val;
-}
-
-static inline u64 eeh_readq(const volatile void __iomem *addr)
-{
-	u64 val = in_le64(addr);
-	if (EEH_POSSIBLE_ERROR(val, u64))
-		return eeh_check_failure(addr, val);
-	return val;
-}
-
-static inline u16 eeh_readw_be(const volatile void __iomem *addr)
-{
-	u16 val = in_be16(addr);
-	if (EEH_POSSIBLE_ERROR(val, u16))
-		return eeh_check_failure(addr, val);
-	return val;
-}
-
-static inline u32 eeh_readl_be(const volatile void __iomem *addr)
-{
-	u32 val = in_be32(addr);
-	if (EEH_POSSIBLE_ERROR(val, u32))
-		return eeh_check_failure(addr, val);
-	return val;
-}
-
-static inline u64 eeh_readq_be(const volatile void __iomem *addr)
-{
-	u64 val = in_be64(addr);
-	if (EEH_POSSIBLE_ERROR(val, u64))
-		return eeh_check_failure(addr, val);
-	return val;
-}
-
-static inline void eeh_memcpy_fromio(void *dest, const
-				     volatile void __iomem *src,
-				     unsigned long n)
-{
-	_memcpy_fromio(dest, src, n);
-
-	/* Look for ffff's here at dest[n].  Assume that at least 4 bytes
-	 * were copied. Check all four bytes.
-	 */
-	if (n >= 4 && EEH_POSSIBLE_ERROR(*((u32 *)(dest + n - 4)), u32))
-		eeh_check_failure(src, *((u32 *)(dest + n - 4)));
-}
-
-/* in-string eeh macros */
-static inline void eeh_readsb(const volatile void __iomem *addr, void * buf,
-			      int ns)
-{
-	_insb(addr, buf, ns);
-	if (EEH_POSSIBLE_ERROR((*(((u8*)buf)+ns-1)), u8))
-		eeh_check_failure(addr, *(u8*)buf);
-}
-
-static inline void eeh_readsw(const volatile void __iomem *addr, void * buf,
-			      int ns)
-{
-	_insw(addr, buf, ns);
-	if (EEH_POSSIBLE_ERROR((*(((u16*)buf)+ns-1)), u16))
-		eeh_check_failure(addr, *(u16*)buf);
-}
-
-static inline void eeh_readsl(const volatile void __iomem *addr, void * buf,
-			      int nl)
-{
-	_insl(addr, buf, nl);
-	if (EEH_POSSIBLE_ERROR((*(((u32*)buf)+nl-1)), u32))
-		eeh_check_failure(addr, *(u32*)buf);
-}
-
-#endif /* CONFIG_PPC64 */
-#endif /* __KERNEL__ */
-#endif /* _POWERPC_EEH_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/eeh_event.h b/ANDROID_3.4.5/arch/powerpc/include/asm/eeh_event.h
deleted file mode 100644
index c68b012b..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/eeh_event.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- *
- * Copyright (c) 2005 Linas Vepstas <linas@linas.org>
- */
-
-#ifndef ASM_POWERPC_EEH_EVENT_H
-#define ASM_POWERPC_EEH_EVENT_H
-#ifdef __KERNEL__
-
-/*
- * structure holding pci controller data that describes a
- * change in the isolation status of a PCI slot.  A pointer
- * to this struct is passed as the data pointer in a notify
- * callback.
- */
-struct eeh_event {
-	struct list_head	list;	/* to form event queue	*/
-	struct eeh_dev		*edev;	/* EEH device		*/
-};
-
-int eeh_send_failure_event(struct eeh_dev *edev);
-struct eeh_dev *handle_eeh_events(struct eeh_event *);
-
-#endif /* __KERNEL__ */
-#endif /* ASM_POWERPC_EEH_EVENT_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/ehv_pic.h b/ANDROID_3.4.5/arch/powerpc/include/asm/ehv_pic.h
deleted file mode 100644
index dc7d48e3..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/ehv_pic.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * EHV_PIC private definitions and structure.
- *
- * Copyright 2008-2010 Freescale Semiconductor, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-#ifndef __EHV_PIC_H__
-#define __EHV_PIC_H__
-
-#include <linux/irq.h>
-
-#define NR_EHV_PIC_INTS 1024
-
-#define EHV_PIC_INFO(name) EHV_PIC_##name
-
-#define EHV_PIC_VECPRI_POLARITY_NEGATIVE 0
-#define EHV_PIC_VECPRI_POLARITY_POSITIVE 1
-#define EHV_PIC_VECPRI_SENSE_EDGE 0
-#define EHV_PIC_VECPRI_SENSE_LEVEL 0x2
-#define EHV_PIC_VECPRI_POLARITY_MASK 0x1
-#define EHV_PIC_VECPRI_SENSE_MASK 0x2
-
-struct ehv_pic {
-	/* The remapper for this EHV_PIC */
-	struct irq_domain	*irqhost;
-
-	/* The "linux" controller struct */
-	struct irq_chip	hc_irq;
-
-	/* core int flag */
-	int coreint_flag;
-};
-
-void ehv_pic_init(void);
-unsigned int ehv_pic_get_irq(void);
-
-#endif /* __EHV_PIC_H__ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/elf.h b/ANDROID_3.4.5/arch/powerpc/include/asm/elf.h
deleted file mode 100644
index 3bf9cca3..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/elf.h
+++ /dev/null
@@ -1,438 +0,0 @@
-#ifndef _ASM_POWERPC_ELF_H
-#define _ASM_POWERPC_ELF_H
-
-#ifdef __KERNEL__
-#include <linux/sched.h>	/* for task_struct */
-#include <asm/page.h>
-#include <asm/string.h>
-#endif
-
-#include <linux/types.h>
-
-#include <asm/ptrace.h>
-#include <asm/cputable.h>
-#include <asm/auxvec.h>
-
-/* PowerPC relocations defined by the ABIs */
-#define R_PPC_NONE		0
-#define R_PPC_ADDR32		1	/* 32bit absolute address */
-#define R_PPC_ADDR24		2	/* 26bit address, 2 bits ignored.  */
-#define R_PPC_ADDR16		3	/* 16bit absolute address */
-#define R_PPC_ADDR16_LO		4	/* lower 16bit of absolute address */
-#define R_PPC_ADDR16_HI		5	/* high 16bit of absolute address */
-#define R_PPC_ADDR16_HA		6	/* adjusted high 16bit */
-#define R_PPC_ADDR14		7	/* 16bit address, 2 bits ignored */
-#define R_PPC_ADDR14_BRTAKEN	8
-#define R_PPC_ADDR14_BRNTAKEN	9
-#define R_PPC_REL24		10	/* PC relative 26 bit */
-#define R_PPC_REL14		11	/* PC relative 16 bit */
-#define R_PPC_REL14_BRTAKEN	12
-#define R_PPC_REL14_BRNTAKEN	13
-#define R_PPC_GOT16		14
-#define R_PPC_GOT16_LO		15
-#define R_PPC_GOT16_HI		16
-#define R_PPC_GOT16_HA		17
-#define R_PPC_PLTREL24		18
-#define R_PPC_COPY		19
-#define R_PPC_GLOB_DAT		20
-#define R_PPC_JMP_SLOT		21
-#define R_PPC_RELATIVE		22
-#define R_PPC_LOCAL24PC		23
-#define R_PPC_UADDR32		24
-#define R_PPC_UADDR16		25
-#define R_PPC_REL32		26
-#define R_PPC_PLT32		27
-#define R_PPC_PLTREL32		28
-#define R_PPC_PLT16_LO		29
-#define R_PPC_PLT16_HI		30
-#define R_PPC_PLT16_HA		31
-#define R_PPC_SDAREL16		32
-#define R_PPC_SECTOFF		33
-#define R_PPC_SECTOFF_LO	34
-#define R_PPC_SECTOFF_HI	35
-#define R_PPC_SECTOFF_HA	36
-
-/* PowerPC relocations defined for the TLS access ABI.  */
-#define R_PPC_TLS		67 /* none	(sym+add)@tls */
-#define R_PPC_DTPMOD32		68 /* word32	(sym+add)@dtpmod */
-#define R_PPC_TPREL16		69 /* half16*	(sym+add)@tprel */
-#define R_PPC_TPREL16_LO	70 /* half16	(sym+add)@tprel@l */
-#define R_PPC_TPREL16_HI	71 /* half16	(sym+add)@tprel@h */
-#define R_PPC_TPREL16_HA	72 /* half16	(sym+add)@tprel@ha */
-#define R_PPC_TPREL32		73 /* word32	(sym+add)@tprel */
-#define R_PPC_DTPREL16		74 /* half16*	(sym+add)@dtprel */
-#define R_PPC_DTPREL16_LO	75 /* half16	(sym+add)@dtprel@l */
-#define R_PPC_DTPREL16_HI	76 /* half16	(sym+add)@dtprel@h */
-#define R_PPC_DTPREL16_HA	77 /* half16	(sym+add)@dtprel@ha */
-#define R_PPC_DTPREL32		78 /* word32	(sym+add)@dtprel */
-#define R_PPC_GOT_TLSGD16	79 /* half16*	(sym+add)@got@tlsgd */
-#define R_PPC_GOT_TLSGD16_LO	80 /* half16	(sym+add)@got@tlsgd@l */
-#define R_PPC_GOT_TLSGD16_HI	81 /* half16	(sym+add)@got@tlsgd@h */
-#define R_PPC_GOT_TLSGD16_HA	82 /* half16	(sym+add)@got@tlsgd@ha */
-#define R_PPC_GOT_TLSLD16	83 /* half16*	(sym+add)@got@tlsld */
-#define R_PPC_GOT_TLSLD16_LO	84 /* half16	(sym+add)@got@tlsld@l */
-#define R_PPC_GOT_TLSLD16_HI	85 /* half16	(sym+add)@got@tlsld@h */
-#define R_PPC_GOT_TLSLD16_HA	86 /* half16	(sym+add)@got@tlsld@ha */
-#define R_PPC_GOT_TPREL16	87 /* half16*	(sym+add)@got@tprel */
-#define R_PPC_GOT_TPREL16_LO	88 /* half16	(sym+add)@got@tprel@l */
-#define R_PPC_GOT_TPREL16_HI	89 /* half16	(sym+add)@got@tprel@h */
-#define R_PPC_GOT_TPREL16_HA	90 /* half16	(sym+add)@got@tprel@ha */
-#define R_PPC_GOT_DTPREL16	91 /* half16*	(sym+add)@got@dtprel */
-#define R_PPC_GOT_DTPREL16_LO	92 /* half16*	(sym+add)@got@dtprel@l */
-#define R_PPC_GOT_DTPREL16_HI	93 /* half16*	(sym+add)@got@dtprel@h */
-#define R_PPC_GOT_DTPREL16_HA	94 /* half16*	(sym+add)@got@dtprel@ha */
-
-/* keep this the last entry. */
-#define R_PPC_NUM		95
-
-/*
- * ELF register definitions..
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#define ELF_NGREG	48	/* includes nip, msr, lr, etc. */
-#define ELF_NFPREG	33	/* includes fpscr */
-
-typedef unsigned long elf_greg_t64;
-typedef elf_greg_t64 elf_gregset_t64[ELF_NGREG];
-
-typedef unsigned int elf_greg_t32;
-typedef elf_greg_t32 elf_gregset_t32[ELF_NGREG];
-typedef elf_gregset_t32 compat_elf_gregset_t;
-
-/*
- * ELF_ARCH, CLASS, and DATA are used to set parameters in the core dumps.
- */
-#ifdef __powerpc64__
-# define ELF_NVRREG32	33	/* includes vscr & vrsave stuffed together */
-# define ELF_NVRREG	34	/* includes vscr & vrsave in split vectors */
-# define ELF_NVSRHALFREG 32	/* Half the vsx registers */
-# define ELF_GREG_TYPE	elf_greg_t64
-#else
-# define ELF_NEVRREG	34	/* includes acc (as 2) */
-# define ELF_NVRREG	33	/* includes vscr */
-# define ELF_GREG_TYPE	elf_greg_t32
-# define ELF_ARCH	EM_PPC
-# define ELF_CLASS	ELFCLASS32
-# define ELF_DATA	ELFDATA2MSB
-#endif /* __powerpc64__ */
-
-#ifndef ELF_ARCH
-# define ELF_ARCH	EM_PPC64
-# define ELF_CLASS	ELFCLASS64
-# define ELF_DATA	ELFDATA2MSB
-  typedef elf_greg_t64 elf_greg_t;
-  typedef elf_gregset_t64 elf_gregset_t;
-#else
-  /* Assumption: ELF_ARCH == EM_PPC and ELF_CLASS == ELFCLASS32 */
-  typedef elf_greg_t32 elf_greg_t;
-  typedef elf_gregset_t32 elf_gregset_t;
-#endif /* ELF_ARCH */
-
-/* Floating point registers */
-typedef double elf_fpreg_t;
-typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
-
-/* Altivec registers */
-/*
- * The entries with indexes 0-31 contain the corresponding vector registers. 
- * The entry with index 32 contains the vscr as the last word (offset 12) 
- * within the quadword.  This allows the vscr to be stored as either a 
- * quadword (since it must be copied via a vector register to/from storage) 
- * or as a word.  
- *
- * 64-bit kernel notes: The entry at index 33 contains the vrsave as the first  
- * word (offset 0) within the quadword.
- *
- * This definition of the VMX state is compatible with the current PPC32 
- * ptrace interface.  This allows signal handling and ptrace to use the same 
- * structures.  This also simplifies the implementation of a bi-arch 
- * (combined (32- and 64-bit) gdb.
- *
- * Note that it's _not_ compatible with 32 bits ucontext which stuffs the
- * vrsave along with vscr and so only uses 33 vectors for the register set
- */
-typedef __vector128 elf_vrreg_t;
-typedef elf_vrreg_t elf_vrregset_t[ELF_NVRREG];
-#ifdef __powerpc64__
-typedef elf_vrreg_t elf_vrregset_t32[ELF_NVRREG32];
-typedef elf_fpreg_t elf_vsrreghalf_t32[ELF_NVSRHALFREG];
-#endif
-
-#ifdef __KERNEL__
-/*
- * This is used to ensure we don't load something for the wrong architecture.
- */
-#define elf_check_arch(x) ((x)->e_machine == ELF_ARCH)
-#define compat_elf_check_arch(x)	((x)->e_machine == EM_PPC)
-
-#define CORE_DUMP_USE_REGSET
-#define ELF_EXEC_PAGESIZE	PAGE_SIZE
-
-/* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
-   use of this is to invoke "./ld.so someprog" to test out a new version of
-   the loader.  We need to make sure that it is out of the way of the program
-   that it will "exec", and that there is sufficient room for the brk.  */
-
-extern unsigned long randomize_et_dyn(unsigned long base);
-#define ELF_ET_DYN_BASE		(randomize_et_dyn(0x20000000))
-
-/*
- * Our registers are always unsigned longs, whether we're a 32 bit
- * process or 64 bit, on either a 64 bit or 32 bit kernel.
- *
- * This macro relies on elf_regs[i] having the right type to truncate to,
- * either u32 or u64.  It defines the body of the elf_core_copy_regs
- * function, either the native one with elf_gregset_t elf_regs or
- * the 32-bit one with elf_gregset_t32 elf_regs.
- */
-#define PPC_ELF_CORE_COPY_REGS(elf_regs, regs) \
-	int i, nregs = min(sizeof(*regs) / sizeof(unsigned long), \
-			   (size_t)ELF_NGREG);			  \
-	for (i = 0; i < nregs; i++) \
-		elf_regs[i] = ((unsigned long *) regs)[i]; \
-	memset(&elf_regs[i], 0, (ELF_NGREG - i) * sizeof(elf_regs[0]))
-
-/* Common routine for both 32-bit and 64-bit native processes */
-static inline void ppc_elf_core_copy_regs(elf_gregset_t elf_regs,
-					  struct pt_regs *regs)
-{
-	PPC_ELF_CORE_COPY_REGS(elf_regs, regs);
-}
-#define ELF_CORE_COPY_REGS(gregs, regs) ppc_elf_core_copy_regs(gregs, regs);
-
-typedef elf_vrregset_t elf_fpxregset_t;
-
-/* ELF_HWCAP yields a mask that user programs can use to figure out what
-   instruction set this cpu supports.  This could be done in userspace,
-   but it's not easy, and we've already done it here.  */
-# define ELF_HWCAP	(cur_cpu_spec->cpu_user_features)
-
-/* This yields a string that ld.so will use to load implementation
-   specific libraries for optimization.  This is more specific in
-   intent than poking at uname or /proc/cpuinfo.  */
-
-#define ELF_PLATFORM	(cur_cpu_spec->platform)
-
-/* While ELF_PLATFORM indicates the ISA supported by the platform, it
- * may not accurately reflect the underlying behavior of the hardware
- * (as in the case of running in Power5+ compatibility mode on a
- * Power6 machine).  ELF_BASE_PLATFORM allows ld.so to load libraries
- * that are tuned for the real hardware.
- */
-#define ELF_BASE_PLATFORM (powerpc_base_platform)
-
-#ifdef __powerpc64__
-# define ELF_PLAT_INIT(_r, load_addr)	do {	\
-	_r->gpr[2] = load_addr; 		\
-} while (0)
-#endif /* __powerpc64__ */
-
-#ifdef __powerpc64__
-# define SET_PERSONALITY(ex)					\
-do {								\
-	if ((ex).e_ident[EI_CLASS] == ELFCLASS32)		\
-		set_thread_flag(TIF_32BIT);			\
-	else							\
-		clear_thread_flag(TIF_32BIT);			\
-	if (personality(current->personality) != PER_LINUX32)	\
-		set_personality(PER_LINUX |			\
-			(current->personality & (~PER_MASK)));	\
-} while (0)
-/*
- * An executable for which elf_read_implies_exec() returns TRUE will
- * have the READ_IMPLIES_EXEC personality flag set automatically. This
- * is only required to work around bugs in old 32bit toolchains. Since
- * the 64bit ABI has never had these issues dont enable the workaround
- * even if we have an executable stack.
- */
-# define elf_read_implies_exec(ex, exec_stk) (is_32bit_task() ? \
-		(exec_stk == EXSTACK_DEFAULT) : 0)
-#else 
-# define SET_PERSONALITY(ex) \
-  set_personality(PER_LINUX | (current->personality & (~PER_MASK)))
-# define elf_read_implies_exec(ex, exec_stk) (exec_stk == EXSTACK_DEFAULT)
-#endif /* __powerpc64__ */
-
-extern int dcache_bsize;
-extern int icache_bsize;
-extern int ucache_bsize;
-
-/* vDSO has arch_setup_additional_pages */
-#define ARCH_HAS_SETUP_ADDITIONAL_PAGES
-struct linux_binprm;
-extern int arch_setup_additional_pages(struct linux_binprm *bprm,
-				       int uses_interp);
-#define VDSO_AUX_ENT(a,b) NEW_AUX_ENT(a,b)
-
-/* 1GB for 64bit, 8MB for 32bit */
-#define STACK_RND_MASK (is_32bit_task() ? \
-	(0x7ff >> (PAGE_SHIFT - 12)) : \
-	(0x3ffff >> (PAGE_SHIFT - 12)))
-
-extern unsigned long arch_randomize_brk(struct mm_struct *mm);
-#define arch_randomize_brk arch_randomize_brk
-
-#endif /* __KERNEL__ */
-
-/*
- * The requirements here are:
- * - keep the final alignment of sp (sp & 0xf)
- * - make sure the 32-bit value at the first 16 byte aligned position of
- *   AUXV is greater than 16 for glibc compatibility.
- *   AT_IGNOREPPC is used for that.
- * - for compatibility with glibc ARCH_DLINFO must always be defined on PPC,
- *   even if DLINFO_ARCH_ITEMS goes to zero or is undefined.
- * update AT_VECTOR_SIZE_ARCH if the number of NEW_AUX_ENT entries changes
- */
-#define ARCH_DLINFO							\
-do {									\
-	/* Handle glibc compatibility. */				\
-	NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC);			\
-	NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC);			\
-	/* Cache size items */						\
-	NEW_AUX_ENT(AT_DCACHEBSIZE, dcache_bsize);			\
-	NEW_AUX_ENT(AT_ICACHEBSIZE, icache_bsize);			\
-	NEW_AUX_ENT(AT_UCACHEBSIZE, ucache_bsize);			\
-	VDSO_AUX_ENT(AT_SYSINFO_EHDR, current->mm->context.vdso_base);	\
-} while (0)
-
-/* PowerPC64 relocations defined by the ABIs */
-#define R_PPC64_NONE    R_PPC_NONE
-#define R_PPC64_ADDR32  R_PPC_ADDR32  /* 32bit absolute address.  */
-#define R_PPC64_ADDR24  R_PPC_ADDR24  /* 26bit address, word aligned.  */
-#define R_PPC64_ADDR16  R_PPC_ADDR16  /* 16bit absolute address. */
-#define R_PPC64_ADDR16_LO R_PPC_ADDR16_LO /* lower 16bits of abs. address.  */
-#define R_PPC64_ADDR16_HI R_PPC_ADDR16_HI /* high 16bits of abs. address. */
-#define R_PPC64_ADDR16_HA R_PPC_ADDR16_HA /* adjusted high 16bits.  */
-#define R_PPC64_ADDR14 R_PPC_ADDR14   /* 16bit address, word aligned.  */
-#define R_PPC64_ADDR14_BRTAKEN  R_PPC_ADDR14_BRTAKEN
-#define R_PPC64_ADDR14_BRNTAKEN R_PPC_ADDR14_BRNTAKEN
-#define R_PPC64_REL24   R_PPC_REL24 /* PC relative 26 bit, word aligned.  */
-#define R_PPC64_REL14   R_PPC_REL14 /* PC relative 16 bit. */
-#define R_PPC64_REL14_BRTAKEN   R_PPC_REL14_BRTAKEN
-#define R_PPC64_REL14_BRNTAKEN  R_PPC_REL14_BRNTAKEN
-#define R_PPC64_GOT16     R_PPC_GOT16
-#define R_PPC64_GOT16_LO  R_PPC_GOT16_LO
-#define R_PPC64_GOT16_HI  R_PPC_GOT16_HI
-#define R_PPC64_GOT16_HA  R_PPC_GOT16_HA
-
-#define R_PPC64_COPY      R_PPC_COPY
-#define R_PPC64_GLOB_DAT  R_PPC_GLOB_DAT
-#define R_PPC64_JMP_SLOT  R_PPC_JMP_SLOT
-#define R_PPC64_RELATIVE  R_PPC_RELATIVE
-
-#define R_PPC64_UADDR32   R_PPC_UADDR32
-#define R_PPC64_UADDR16   R_PPC_UADDR16
-#define R_PPC64_REL32     R_PPC_REL32
-#define R_PPC64_PLT32     R_PPC_PLT32
-#define R_PPC64_PLTREL32  R_PPC_PLTREL32
-#define R_PPC64_PLT16_LO  R_PPC_PLT16_LO
-#define R_PPC64_PLT16_HI  R_PPC_PLT16_HI
-#define R_PPC64_PLT16_HA  R_PPC_PLT16_HA
-
-#define R_PPC64_SECTOFF     R_PPC_SECTOFF
-#define R_PPC64_SECTOFF_LO  R_PPC_SECTOFF_LO
-#define R_PPC64_SECTOFF_HI  R_PPC_SECTOFF_HI
-#define R_PPC64_SECTOFF_HA  R_PPC_SECTOFF_HA
-#define R_PPC64_ADDR30          37  /* word30 (S + A - P) >> 2.  */
-#define R_PPC64_ADDR64          38  /* doubleword64 S + A.  */
-#define R_PPC64_ADDR16_HIGHER   39  /* half16 #higher(S + A).  */
-#define R_PPC64_ADDR16_HIGHERA  40  /* half16 #highera(S + A).  */
-#define R_PPC64_ADDR16_HIGHEST  41  /* half16 #highest(S + A).  */
-#define R_PPC64_ADDR16_HIGHESTA 42  /* half16 #highesta(S + A). */
-#define R_PPC64_UADDR64     43  /* doubleword64 S + A.  */
-#define R_PPC64_REL64       44  /* doubleword64 S + A - P.  */
-#define R_PPC64_PLT64       45  /* doubleword64 L + A.  */
-#define R_PPC64_PLTREL64    46  /* doubleword64 L + A - P.  */
-#define R_PPC64_TOC16       47  /* half16* S + A - .TOC.  */
-#define R_PPC64_TOC16_LO    48  /* half16 #lo(S + A - .TOC.).  */
-#define R_PPC64_TOC16_HI    49  /* half16 #hi(S + A - .TOC.).  */
-#define R_PPC64_TOC16_HA    50  /* half16 #ha(S + A - .TOC.).  */
-#define R_PPC64_TOC         51  /* doubleword64 .TOC. */
-#define R_PPC64_PLTGOT16    52  /* half16* M + A.  */
-#define R_PPC64_PLTGOT16_LO 53  /* half16 #lo(M + A).  */
-#define R_PPC64_PLTGOT16_HI 54  /* half16 #hi(M + A).  */
-#define R_PPC64_PLTGOT16_HA 55  /* half16 #ha(M + A).  */
-
-#define R_PPC64_ADDR16_DS      56 /* half16ds* (S + A) >> 2.  */
-#define R_PPC64_ADDR16_LO_DS   57 /* half16ds  #lo(S + A) >> 2.  */
-#define R_PPC64_GOT16_DS       58 /* half16ds* (G + A) >> 2.  */
-#define R_PPC64_GOT16_LO_DS    59 /* half16ds  #lo(G + A) >> 2.  */
-#define R_PPC64_PLT16_LO_DS    60 /* half16ds  #lo(L + A) >> 2.  */
-#define R_PPC64_SECTOFF_DS     61 /* half16ds* (R + A) >> 2.  */
-#define R_PPC64_SECTOFF_LO_DS  62 /* half16ds  #lo(R + A) >> 2.  */
-#define R_PPC64_TOC16_DS       63 /* half16ds* (S + A - .TOC.) >> 2.  */
-#define R_PPC64_TOC16_LO_DS    64 /* half16ds  #lo(S + A - .TOC.) >> 2.  */
-#define R_PPC64_PLTGOT16_DS    65 /* half16ds* (M + A) >> 2.  */
-#define R_PPC64_PLTGOT16_LO_DS 66 /* half16ds  #lo(M + A) >> 2.  */
-
-/* PowerPC64 relocations defined for the TLS access ABI.  */
-#define R_PPC64_TLS		67 /* none	(sym+add)@tls */
-#define R_PPC64_DTPMOD64	68 /* doubleword64 (sym+add)@dtpmod */
-#define R_PPC64_TPREL16		69 /* half16*	(sym+add)@tprel */
-#define R_PPC64_TPREL16_LO	70 /* half16	(sym+add)@tprel@l */
-#define R_PPC64_TPREL16_HI	71 /* half16	(sym+add)@tprel@h */
-#define R_PPC64_TPREL16_HA	72 /* half16	(sym+add)@tprel@ha */
-#define R_PPC64_TPREL64		73 /* doubleword64 (sym+add)@tprel */
-#define R_PPC64_DTPREL16	74 /* half16*	(sym+add)@dtprel */
-#define R_PPC64_DTPREL16_LO	75 /* half16	(sym+add)@dtprel@l */
-#define R_PPC64_DTPREL16_HI	76 /* half16	(sym+add)@dtprel@h */
-#define R_PPC64_DTPREL16_HA	77 /* half16	(sym+add)@dtprel@ha */
-#define R_PPC64_DTPREL64	78 /* doubleword64 (sym+add)@dtprel */
-#define R_PPC64_GOT_TLSGD16	79 /* half16*	(sym+add)@got@tlsgd */
-#define R_PPC64_GOT_TLSGD16_LO	80 /* half16	(sym+add)@got@tlsgd@l */
-#define R_PPC64_GOT_TLSGD16_HI	81 /* half16	(sym+add)@got@tlsgd@h */
-#define R_PPC64_GOT_TLSGD16_HA	82 /* half16	(sym+add)@got@tlsgd@ha */
-#define R_PPC64_GOT_TLSLD16	83 /* half16*	(sym+add)@got@tlsld */
-#define R_PPC64_GOT_TLSLD16_LO	84 /* half16	(sym+add)@got@tlsld@l */
-#define R_PPC64_GOT_TLSLD16_HI	85 /* half16	(sym+add)@got@tlsld@h */
-#define R_PPC64_GOT_TLSLD16_HA	86 /* half16	(sym+add)@got@tlsld@ha */
-#define R_PPC64_GOT_TPREL16_DS	87 /* half16ds*	(sym+add)@got@tprel */
-#define R_PPC64_GOT_TPREL16_LO_DS 88 /* half16ds (sym+add)@got@tprel@l */
-#define R_PPC64_GOT_TPREL16_HI	89 /* half16	(sym+add)@got@tprel@h */
-#define R_PPC64_GOT_TPREL16_HA	90 /* half16	(sym+add)@got@tprel@ha */
-#define R_PPC64_GOT_DTPREL16_DS	91 /* half16ds*	(sym+add)@got@dtprel */
-#define R_PPC64_GOT_DTPREL16_LO_DS 92 /* half16ds (sym+add)@got@dtprel@l */
-#define R_PPC64_GOT_DTPREL16_HI	93 /* half16	(sym+add)@got@dtprel@h */
-#define R_PPC64_GOT_DTPREL16_HA	94 /* half16	(sym+add)@got@dtprel@ha */
-#define R_PPC64_TPREL16_DS	95 /* half16ds*	(sym+add)@tprel */
-#define R_PPC64_TPREL16_LO_DS	96 /* half16ds	(sym+add)@tprel@l */
-#define R_PPC64_TPREL16_HIGHER	97 /* half16	(sym+add)@tprel@higher */
-#define R_PPC64_TPREL16_HIGHERA	98 /* half16	(sym+add)@tprel@highera */
-#define R_PPC64_TPREL16_HIGHEST	99 /* half16	(sym+add)@tprel@highest */
-#define R_PPC64_TPREL16_HIGHESTA 100 /* half16	(sym+add)@tprel@highesta */
-#define R_PPC64_DTPREL16_DS	101 /* half16ds* (sym+add)@dtprel */
-#define R_PPC64_DTPREL16_LO_DS	102 /* half16ds	(sym+add)@dtprel@l */
-#define R_PPC64_DTPREL16_HIGHER	103 /* half16	(sym+add)@dtprel@higher */
-#define R_PPC64_DTPREL16_HIGHERA 104 /* half16	(sym+add)@dtprel@highera */
-#define R_PPC64_DTPREL16_HIGHEST 105 /* half16	(sym+add)@dtprel@highest */
-#define R_PPC64_DTPREL16_HIGHESTA 106 /* half16	(sym+add)@dtprel@highesta */
-
-/* Keep this the last entry.  */
-#define R_PPC64_NUM		107
-
-/* There's actually a third entry here, but it's unused */
-struct ppc64_opd_entry
-{
-	unsigned long funcaddr;
-	unsigned long r2;
-};
-
-#ifdef  __KERNEL__
-
-#ifdef CONFIG_SPU_BASE
-/* Notes used in ET_CORE. Note name is "SPU/<fd>/<filename>". */
-#define NT_SPU		1
-
-#define ARCH_HAVE_EXTRA_ELF_NOTES
-
-#endif /* CONFIG_SPU_BASE */
-
-#endif /* __KERNEL */
-
-#endif /* _ASM_POWERPC_ELF_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/emergency-restart.h b/ANDROID_3.4.5/arch/powerpc/include/asm/emergency-restart.h
deleted file mode 100644
index 3711bd9d..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/emergency-restart.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/emergency-restart.h>
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/emulated_ops.h b/ANDROID_3.4.5/arch/powerpc/include/asm/emulated_ops.h
deleted file mode 100644
index 63f2a22e..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/emulated_ops.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- *  Copyright 2007 Sony Corporation
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; version 2 of the License.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program.
- *  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef _ASM_POWERPC_EMULATED_OPS_H
-#define _ASM_POWERPC_EMULATED_OPS_H
-
-#include <linux/atomic.h>
-#include <linux/perf_event.h>
-
-
-#ifdef CONFIG_PPC_EMULATED_STATS
-
-struct ppc_emulated_entry {
-	const char *name;
-	atomic_t val;
-};
-
-extern struct ppc_emulated {
-#ifdef CONFIG_ALTIVEC
-	struct ppc_emulated_entry altivec;
-#endif
-	struct ppc_emulated_entry dcba;
-	struct ppc_emulated_entry dcbz;
-	struct ppc_emulated_entry fp_pair;
-	struct ppc_emulated_entry isel;
-	struct ppc_emulated_entry mcrxr;
-	struct ppc_emulated_entry mfpvr;
-	struct ppc_emulated_entry multiple;
-	struct ppc_emulated_entry popcntb;
-	struct ppc_emulated_entry spe;
-	struct ppc_emulated_entry string;
-	struct ppc_emulated_entry unaligned;
-#ifdef CONFIG_MATH_EMULATION
-	struct ppc_emulated_entry math;
-#elif defined(CONFIG_8XX_MINIMAL_FPEMU)
-	struct ppc_emulated_entry 8xx;
-#endif
-#ifdef CONFIG_VSX
-	struct ppc_emulated_entry vsx;
-#endif
-#ifdef CONFIG_PPC64
-	struct ppc_emulated_entry mfdscr;
-	struct ppc_emulated_entry mtdscr;
-#endif
-} ppc_emulated;
-
-extern u32 ppc_warn_emulated;
-
-extern void ppc_warn_emulated_print(const char *type);
-
-#define __PPC_WARN_EMULATED(type)					 \
-	do {								 \
-		atomic_inc(&ppc_emulated.type.val);			 \
-		if (ppc_warn_emulated)					 \
-			ppc_warn_emulated_print(ppc_emulated.type.name); \
-	} while (0)
-
-#else /* !CONFIG_PPC_EMULATED_STATS */
-
-#define __PPC_WARN_EMULATED(type)	do { } while (0)
-
-#endif /* !CONFIG_PPC_EMULATED_STATS */
-
-#define PPC_WARN_EMULATED(type, regs)					\
-	do {								\
-		perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,		\
-			1, regs, 0);					\
-		__PPC_WARN_EMULATED(type);				\
-	} while (0)
-
-#define PPC_WARN_ALIGNMENT(type, regs)					\
-	do {								\
-		perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS,		\
-			1, regs, regs->dar);				\
-		__PPC_WARN_EMULATED(type);				\
-	} while (0)
-
-#endif /* _ASM_POWERPC_EMULATED_OPS_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/epapr_hcalls.h b/ANDROID_3.4.5/arch/powerpc/include/asm/epapr_hcalls.h
deleted file mode 100644
index 976835d8..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/epapr_hcalls.h
+++ /dev/null
@@ -1,507 +0,0 @@
-/*
- * ePAPR hcall interface
- *
- * Copyright 2008-2011 Freescale Semiconductor, Inc.
- *
- * Author: Timur Tabi <timur@freescale.com>
- *
- * This file is provided under a dual BSD/GPL license.  When using or
- * redistributing this file, you may do so under either license.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Freescale Semiconductor nor the
- *       names of its contributors may be used to endorse or promote products
- *       derived from this software without specific prior written permission.
- *
- *
- * ALTERNATIVELY, this software may be distributed under the terms of the
- * GNU General Public License ("GPL") as published by the Free Software
- * Foundation, either version 2 of that License or (at your option) any
- * later version.
- *
- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/* A "hypercall" is an "sc 1" instruction.  This header file file provides C
- * wrapper functions for the ePAPR hypervisor interface.  It is inteded
- * for use by Linux device drivers and other operating systems.
- *
- * The hypercalls are implemented as inline assembly, rather than assembly
- * language functions in a .S file, for optimization.  It allows
- * the caller to issue the hypercall instruction directly, improving both
- * performance and memory footprint.
- */
-
-#ifndef _EPAPR_HCALLS_H
-#define _EPAPR_HCALLS_H
-
-#include <linux/types.h>
-#include <linux/errno.h>
-#include <asm/byteorder.h>
-
-#define EV_BYTE_CHANNEL_SEND		1
-#define EV_BYTE_CHANNEL_RECEIVE		2
-#define EV_BYTE_CHANNEL_POLL		3
-#define EV_INT_SET_CONFIG		4
-#define EV_INT_GET_CONFIG		5
-#define EV_INT_SET_MASK			6
-#define EV_INT_GET_MASK			7
-#define EV_INT_IACK			9
-#define EV_INT_EOI			10
-#define EV_INT_SEND_IPI			11
-#define EV_INT_SET_TASK_PRIORITY	12
-#define EV_INT_GET_TASK_PRIORITY	13
-#define EV_DOORBELL_SEND		14
-#define EV_MSGSND			15
-#define EV_IDLE				16
-
-/* vendor ID: epapr */
-#define EV_LOCAL_VENDOR_ID		0	/* for private use */
-#define EV_EPAPR_VENDOR_ID		1
-#define EV_FSL_VENDOR_ID		2	/* Freescale Semiconductor */
-#define EV_IBM_VENDOR_ID		3	/* IBM */
-#define EV_GHS_VENDOR_ID		4	/* Green Hills Software */
-#define EV_ENEA_VENDOR_ID		5	/* Enea */
-#define EV_WR_VENDOR_ID			6	/* Wind River Systems */
-#define EV_AMCC_VENDOR_ID		7	/* Applied Micro Circuits */
-#define EV_KVM_VENDOR_ID		42	/* KVM */
-
-/* The max number of bytes that a byte channel can send or receive per call */
-#define EV_BYTE_CHANNEL_MAX_BYTES	16
-
-
-#define _EV_HCALL_TOKEN(id, num) (((id) << 16) | (num))
-#define EV_HCALL_TOKEN(hcall_num) _EV_HCALL_TOKEN(EV_EPAPR_VENDOR_ID, hcall_num)
-
-/* epapr error codes */
-#define EV_EPERM		1	/* Operation not permitted */
-#define EV_ENOENT		2	/*  Entry Not Found */
-#define EV_EIO			3	/* I/O error occured */
-#define EV_EAGAIN		4	/* The operation had insufficient
-					 * resources to complete and should be
-					 * retried
-					 */
-#define EV_ENOMEM		5	/* There was insufficient memory to
-					 * complete the operation */
-#define EV_EFAULT		6	/* Bad guest address */
-#define EV_ENODEV		7	/* No such device */
-#define EV_EINVAL		8	/* An argument supplied to the hcall
-					   was out of range or invalid */
-#define EV_INTERNAL		9	/* An internal error occured */
-#define EV_CONFIG		10	/* A configuration error was detected */
-#define EV_INVALID_STATE	11	/* The object is in an invalid state */
-#define EV_UNIMPLEMENTED	12	/* Unimplemented hypercall */
-#define EV_BUFFER_OVERFLOW	13	/* Caller-supplied buffer too small */
-
-/*
- * Hypercall register clobber list
- *
- * These macros are used to define the list of clobbered registers during a
- * hypercall.  Technically, registers r0 and r3-r12 are always clobbered,
- * but the gcc inline assembly syntax does not allow us to specify registers
- * on the clobber list that are also on the input/output list.  Therefore,
- * the lists of clobbered registers depends on the number of register
- * parmeters ("+r" and "=r") passed to the hypercall.
- *
- * Each assembly block should use one of the HCALL_CLOBBERSx macros.  As a
- * general rule, 'x' is the number of parameters passed to the assembly
- * block *except* for r11.
- *
- * If you're not sure, just use the smallest value of 'x' that does not
- * generate a compilation error.  Because these are static inline functions,
- * the compiler will only check the clobber list for a function if you
- * compile code that calls that function.
- *
- * r3 and r11 are not included in any clobbers list because they are always
- * listed as output registers.
- *
- * XER, CTR, and LR are currently listed as clobbers because it's uncertain
- * whether they will be clobbered.
- *
- * Note that r11 can be used as an output parameter.
- *
- * The "memory" clobber is only necessary for hcalls where the Hypervisor
- * will read or write guest memory. However, we add it to all hcalls because
- * the impact is minimal, and we want to ensure that it's present for the
- * hcalls that need it.
-*/
-
-/* List of common clobbered registers.  Do not use this macro. */
-#define EV_HCALL_CLOBBERS "r0", "r12", "xer", "ctr", "lr", "cc", "memory"
-
-#define EV_HCALL_CLOBBERS8 EV_HCALL_CLOBBERS
-#define EV_HCALL_CLOBBERS7 EV_HCALL_CLOBBERS8, "r10"
-#define EV_HCALL_CLOBBERS6 EV_HCALL_CLOBBERS7, "r9"
-#define EV_HCALL_CLOBBERS5 EV_HCALL_CLOBBERS6, "r8"
-#define EV_HCALL_CLOBBERS4 EV_HCALL_CLOBBERS5, "r7"
-#define EV_HCALL_CLOBBERS3 EV_HCALL_CLOBBERS4, "r6"
-#define EV_HCALL_CLOBBERS2 EV_HCALL_CLOBBERS3, "r5"
-#define EV_HCALL_CLOBBERS1 EV_HCALL_CLOBBERS2, "r4"
-
-
-/*
- * We use "uintptr_t" to define a register because it's guaranteed to be a
- * 32-bit integer on a 32-bit platform, and a 64-bit integer on a 64-bit
- * platform.
- *
- * All registers are either input/output or output only.  Registers that are
- * initialized before making the hypercall are input/output.  All
- * input/output registers are represented with "+r".  Output-only registers
- * are represented with "=r".  Do not specify any unused registers.  The
- * clobber list will tell the compiler that the hypercall modifies those
- * registers, which is good enough.
- */
-
-/**
- * ev_int_set_config - configure the specified interrupt
- * @interrupt: the interrupt number
- * @config: configuration for this interrupt
- * @priority: interrupt priority
- * @destination: destination CPU number
- *
- * Returns 0 for success, or an error code.
- */
-static inline unsigned int ev_int_set_config(unsigned int interrupt,
-	uint32_t config, unsigned int priority, uint32_t destination)
-{
-	register uintptr_t r11 __asm__("r11");
-	register uintptr_t r3 __asm__("r3");
-	register uintptr_t r4 __asm__("r4");
-	register uintptr_t r5 __asm__("r5");
-	register uintptr_t r6 __asm__("r6");
-
-	r11 = EV_HCALL_TOKEN(EV_INT_SET_CONFIG);
-	r3  = interrupt;
-	r4  = config;
-	r5  = priority;
-	r6  = destination;
-
-	__asm__ __volatile__ ("sc 1"
-		: "+r" (r11), "+r" (r3), "+r" (r4), "+r" (r5), "+r" (r6)
-		: : EV_HCALL_CLOBBERS4
-	);
-
-	return r3;
-}
-
-/**
- * ev_int_get_config - return the config of the specified interrupt
- * @interrupt: the interrupt number
- * @config: returned configuration for this interrupt
- * @priority: returned interrupt priority
- * @destination: returned destination CPU number
- *
- * Returns 0 for success, or an error code.
- */
-static inline unsigned int ev_int_get_config(unsigned int interrupt,
-	uint32_t *config, unsigned int *priority, uint32_t *destination)
-{
-	register uintptr_t r11 __asm__("r11");
-	register uintptr_t r3 __asm__("r3");
-	register uintptr_t r4 __asm__("r4");
-	register uintptr_t r5 __asm__("r5");
-	register uintptr_t r6 __asm__("r6");
-
-	r11 = EV_HCALL_TOKEN(EV_INT_GET_CONFIG);
-	r3 = interrupt;
-
-	__asm__ __volatile__ ("sc 1"
-		: "+r" (r11), "+r" (r3), "=r" (r4), "=r" (r5), "=r" (r6)
-		: : EV_HCALL_CLOBBERS4
-	);
-
-	*config = r4;
-	*priority = r5;
-	*destination = r6;
-
-	return r3;
-}
-
-/**
- * ev_int_set_mask - sets the mask for the specified interrupt source
- * @interrupt: the interrupt number
- * @mask: 0=enable interrupts, 1=disable interrupts
- *
- * Returns 0 for success, or an error code.
- */
-static inline unsigned int ev_int_set_mask(unsigned int interrupt,
-	unsigned int mask)
-{
-	register uintptr_t r11 __asm__("r11");
-	register uintptr_t r3 __asm__("r3");
-	register uintptr_t r4 __asm__("r4");
-
-	r11 = EV_HCALL_TOKEN(EV_INT_SET_MASK);
-	r3 = interrupt;
-	r4 = mask;
-
-	__asm__ __volatile__ ("sc 1"
-		: "+r" (r11), "+r" (r3), "+r" (r4)
-		: : EV_HCALL_CLOBBERS2
-	);
-
-	return r3;
-}
-
-/**
- * ev_int_get_mask - returns the mask for the specified interrupt source
- * @interrupt: the interrupt number
- * @mask: returned mask for this interrupt (0=enabled, 1=disabled)
- *
- * Returns 0 for success, or an error code.
- */
-static inline unsigned int ev_int_get_mask(unsigned int interrupt,
-	unsigned int *mask)
-{
-	register uintptr_t r11 __asm__("r11");
-	register uintptr_t r3 __asm__("r3");
-	register uintptr_t r4 __asm__("r4");
-
-	r11 = EV_HCALL_TOKEN(EV_INT_GET_MASK);
-	r3 = interrupt;
-
-	__asm__ __volatile__ ("sc 1"
-		: "+r" (r11), "+r" (r3), "=r" (r4)
-		: : EV_HCALL_CLOBBERS2
-	);
-
-	*mask = r4;
-
-	return r3;
-}
-
-/**
- * ev_int_eoi - signal the end of interrupt processing
- * @interrupt: the interrupt number
- *
- * This function signals the end of processing for the the specified
- * interrupt, which must be the interrupt currently in service. By
- * definition, this is also the highest-priority interrupt.
- *
- * Returns 0 for success, or an error code.
- */
-static inline unsigned int ev_int_eoi(unsigned int interrupt)
-{
-	register uintptr_t r11 __asm__("r11");
-	register uintptr_t r3 __asm__("r3");
-
-	r11 = EV_HCALL_TOKEN(EV_INT_EOI);
-	r3 = interrupt;
-
-	__asm__ __volatile__ ("sc 1"
-		: "+r" (r11), "+r" (r3)
-		: : EV_HCALL_CLOBBERS1
-	);
-
-	return r3;
-}
-
-/**
- * ev_byte_channel_send - send characters to a byte stream
- * @handle: byte stream handle
- * @count: (input) num of chars to send, (output) num chars sent
- * @buffer: pointer to a 16-byte buffer
- *
- * @buffer must be at least 16 bytes long, because all 16 bytes will be
- * read from memory into registers, even if count < 16.
- *
- * Returns 0 for success, or an error code.
- */
-static inline unsigned int ev_byte_channel_send(unsigned int handle,
-	unsigned int *count, const char buffer[EV_BYTE_CHANNEL_MAX_BYTES])
-{
-	register uintptr_t r11 __asm__("r11");
-	register uintptr_t r3 __asm__("r3");
-	register uintptr_t r4 __asm__("r4");
-	register uintptr_t r5 __asm__("r5");
-	register uintptr_t r6 __asm__("r6");
-	register uintptr_t r7 __asm__("r7");
-	register uintptr_t r8 __asm__("r8");
-	const uint32_t *p = (const uint32_t *) buffer;
-
-	r11 = EV_HCALL_TOKEN(EV_BYTE_CHANNEL_SEND);
-	r3 = handle;
-	r4 = *count;
-	r5 = be32_to_cpu(p[0]);
-	r6 = be32_to_cpu(p[1]);
-	r7 = be32_to_cpu(p[2]);
-	r8 = be32_to_cpu(p[3]);
-
-	__asm__ __volatile__ ("sc 1"
-		: "+r" (r11), "+r" (r3),
-		  "+r" (r4), "+r" (r5), "+r" (r6), "+r" (r7), "+r" (r8)
-		: : EV_HCALL_CLOBBERS6
-	);
-
-	*count = r4;
-
-	return r3;
-}
-
-/**
- * ev_byte_channel_receive - fetch characters from a byte channel
- * @handle: byte channel handle
- * @count: (input) max num of chars to receive, (output) num chars received
- * @buffer: pointer to a 16-byte buffer
- *
- * The size of @buffer must be at least 16 bytes, even if you request fewer
- * than 16 characters, because we always write 16 bytes to @buffer.  This is
- * for performance reasons.
- *
- * Returns 0 for success, or an error code.
- */
-static inline unsigned int ev_byte_channel_receive(unsigned int handle,
-	unsigned int *count, char buffer[EV_BYTE_CHANNEL_MAX_BYTES])
-{
-	register uintptr_t r11 __asm__("r11");
-	register uintptr_t r3 __asm__("r3");
-	register uintptr_t r4 __asm__("r4");
-	register uintptr_t r5 __asm__("r5");
-	register uintptr_t r6 __asm__("r6");
-	register uintptr_t r7 __asm__("r7");
-	register uintptr_t r8 __asm__("r8");
-	uint32_t *p = (uint32_t *) buffer;
-
-	r11 = EV_HCALL_TOKEN(EV_BYTE_CHANNEL_RECEIVE);
-	r3 = handle;
-	r4 = *count;
-
-	__asm__ __volatile__ ("sc 1"
-		: "+r" (r11), "+r" (r3), "+r" (r4),
-		  "=r" (r5), "=r" (r6), "=r" (r7), "=r" (r8)
-		: : EV_HCALL_CLOBBERS6
-	);
-
-	*count = r4;
-	p[0] = cpu_to_be32(r5);
-	p[1] = cpu_to_be32(r6);
-	p[2] = cpu_to_be32(r7);
-	p[3] = cpu_to_be32(r8);
-
-	return r3;
-}
-
-/**
- * ev_byte_channel_poll - returns the status of the byte channel buffers
- * @handle: byte channel handle
- * @rx_count: returned count of bytes in receive queue
- * @tx_count: returned count of free space in transmit queue
- *
- * This function reports the amount of data in the receive queue (i.e. the
- * number of bytes you can read), and the amount of free space in the transmit
- * queue (i.e. the number of bytes you can write).
- *
- * Returns 0 for success, or an error code.
- */
-static inline unsigned int ev_byte_channel_poll(unsigned int handle,
-	unsigned int *rx_count,	unsigned int *tx_count)
-{
-	register uintptr_t r11 __asm__("r11");
-	register uintptr_t r3 __asm__("r3");
-	register uintptr_t r4 __asm__("r4");
-	register uintptr_t r5 __asm__("r5");
-
-	r11 = EV_HCALL_TOKEN(EV_BYTE_CHANNEL_POLL);
-	r3 = handle;
-
-	__asm__ __volatile__ ("sc 1"
-		: "+r" (r11), "+r" (r3), "=r" (r4), "=r" (r5)
-		: : EV_HCALL_CLOBBERS3
-	);
-
-	*rx_count = r4;
-	*tx_count = r5;
-
-	return r3;
-}
-
-/**
- * ev_int_iack - acknowledge an interrupt
- * @handle: handle to the target interrupt controller
- * @vector: returned interrupt vector
- *
- * If handle is zero, the function returns the next interrupt source
- * number to be handled irrespective of the hierarchy or cascading
- * of interrupt controllers. If non-zero, specifies a handle to the
- * interrupt controller that is the target of the acknowledge.
- *
- * Returns 0 for success, or an error code.
- */
-static inline unsigned int ev_int_iack(unsigned int handle,
-	unsigned int *vector)
-{
-	register uintptr_t r11 __asm__("r11");
-	register uintptr_t r3 __asm__("r3");
-	register uintptr_t r4 __asm__("r4");
-
-	r11 = EV_HCALL_TOKEN(EV_INT_IACK);
-	r3 = handle;
-
-	__asm__ __volatile__ ("sc 1"
-		: "+r" (r11), "+r" (r3), "=r" (r4)
-		: : EV_HCALL_CLOBBERS2
-	);
-
-	*vector = r4;
-
-	return r3;
-}
-
-/**
- * ev_doorbell_send - send a doorbell to another partition
- * @handle: doorbell send handle
- *
- * Returns 0 for success, or an error code.
- */
-static inline unsigned int ev_doorbell_send(unsigned int handle)
-{
-	register uintptr_t r11 __asm__("r11");
-	register uintptr_t r3 __asm__("r3");
-
-	r11 = EV_HCALL_TOKEN(EV_DOORBELL_SEND);
-	r3 = handle;
-
-	__asm__ __volatile__ ("sc 1"
-		: "+r" (r11), "+r" (r3)
-		: : EV_HCALL_CLOBBERS1
-	);
-
-	return r3;
-}
-
-/**
- * ev_idle -- wait for next interrupt on this core
- *
- * Returns 0 for success, or an error code.
- */
-static inline unsigned int ev_idle(void)
-{
-	register uintptr_t r11 __asm__("r11");
-	register uintptr_t r3 __asm__("r3");
-
-	r11 = EV_HCALL_TOKEN(EV_IDLE);
-
-	__asm__ __volatile__ ("sc 1"
-		: "+r" (r11), "=r" (r3)
-		: : EV_HCALL_CLOBBERS1
-	);
-
-	return r3;
-}
-
-#endif
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/errno.h b/ANDROID_3.4.5/arch/powerpc/include/asm/errno.h
deleted file mode 100644
index 8c145fd1..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/errno.h
+++ /dev/null
@@ -1,11 +0,0 @@
-#ifndef _ASM_POWERPC_ERRNO_H
-#define _ASM_POWERPC_ERRNO_H
-
-#include <asm-generic/errno.h>
-
-#undef	EDEADLOCK
-#define	EDEADLOCK	58	/* File locking deadlock error */
-
-#define _LAST_ERRNO	516
-
-#endif	/* _ASM_POWERPC_ERRNO_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/exception-64e.h b/ANDROID_3.4.5/arch/powerpc/include/asm/exception-64e.h
deleted file mode 100644
index ac13addb..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/exception-64e.h
+++ /dev/null
@@ -1,221 +0,0 @@
-/*
- *  Definitions for use by exception code on Book3-E
- *
- *  Copyright (C) 2008 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
- *
- *  This program is free software; you can redistribute it and/or
- *  modify it under the terms of the GNU General Public License
- *  as published by the Free Software Foundation; either version
- *  2 of the License, or (at your option) any later version.
- */
-#ifndef _ASM_POWERPC_EXCEPTION_64E_H
-#define _ASM_POWERPC_EXCEPTION_64E_H
-
-/*
- * SPRGs usage an other considerations...
- *
- * Since TLB miss and other standard exceptions can be interrupted by
- * critical exceptions which can themselves be interrupted by machine
- * checks, and since the two later can themselves cause a TLB miss when
- * hitting the linear mapping for the kernel stacks, we need to be a bit
- * creative on how we use SPRGs.
- *
- * The base idea is that we have one SRPG reserved for critical and one
- * for machine check interrupts. Those are used to save a GPR that can
- * then be used to get the PACA, and store as much context as we need
- * to save in there. That includes saving the SPRGs used by the TLB miss
- * handler for linear mapping misses and the associated SRR0/1 due to
- * the above re-entrancy issue.
- *
- * So here's the current usage pattern. It's done regardless of which
- * SPRGs are user-readable though, thus we might have to change some of
- * this later. In order to do that more easily, we use special constants
- * for naming them
- *
- * WARNING: Some of these SPRGs are user readable. We need to do something
- * about it as some point by making sure they can't be used to leak kernel
- * critical data
- */
-
-
-/* We are out of SPRGs so we save some things in the PACA. The normal
- * exception frame is smaller than the CRIT or MC one though
- */
-#define EX_R1		(0 * 8)
-#define EX_CR		(1 * 8)
-#define EX_R10		(2 * 8)
-#define EX_R11		(3 * 8)
-#define EX_R14		(4 * 8)
-#define EX_R15		(5 * 8)
-
-/*
- * The TLB miss exception uses different slots.
- *
- * The bolted variant uses only the first six fields,
- * which in combination with pgd and kernel_pgd fits in
- * one 64-byte cache line.
- */
-
-#define EX_TLB_R10	( 0 * 8)
-#define EX_TLB_R11	( 1 * 8)
-#define EX_TLB_R14	( 2 * 8)
-#define EX_TLB_R15	( 3 * 8)
-#define EX_TLB_R16	( 4 * 8)
-#define EX_TLB_CR	( 5 * 8)
-#define EX_TLB_R12	( 6 * 8)
-#define EX_TLB_R13	( 7 * 8)
-#define EX_TLB_DEAR	( 8 * 8) /* Level 0 and 2 only */
-#define EX_TLB_ESR	( 9 * 8) /* Level 0 and 2 only */
-#define EX_TLB_SRR0	(10 * 8)
-#define EX_TLB_SRR1	(11 * 8)
-#ifdef CONFIG_BOOK3E_MMU_TLB_STATS
-#define EX_TLB_R8	(12 * 8)
-#define EX_TLB_R9	(13 * 8)
-#define EX_TLB_LR	(14 * 8)
-#define EX_TLB_SIZE	(15 * 8)
-#else
-#define EX_TLB_SIZE	(12 * 8)
-#endif
-
-#define	START_EXCEPTION(label)						\
-	.globl exc_##label##_book3e;					\
-exc_##label##_book3e:
-
-/* TLB miss exception prolog
- *
- * This prolog handles re-entrancy (up to 3 levels supported in the PACA
- * though we currently don't test for overflow). It provides you with a
- * re-entrancy safe working space of r10...r16 and CR with r12 being used
- * as the exception area pointer in the PACA for that level of re-entrancy
- * and r13 containing the PACA pointer.
- *
- * SRR0 and SRR1 are saved, but DEAR and ESR are not, since they don't apply
- * as-is for instruction exceptions. It's up to the actual exception code
- * to save them as well if required.
- */
-#define TLB_MISS_PROLOG							    \
-	mtspr	SPRN_SPRG_TLB_SCRATCH,r12;				    \
-	mfspr	r12,SPRN_SPRG_TLB_EXFRAME;				    \
-	std	r10,EX_TLB_R10(r12);					    \
-	mfcr	r10;							    \
-	std	r11,EX_TLB_R11(r12);					    \
-	mfspr	r11,SPRN_SPRG_TLB_SCRATCH;				    \
-	std	r13,EX_TLB_R13(r12);					    \
-	mfspr	r13,SPRN_SPRG_PACA;					    \
-	std	r14,EX_TLB_R14(r12);					    \
-	addi	r14,r12,EX_TLB_SIZE;					    \
-	std	r15,EX_TLB_R15(r12);					    \
-	mfspr	r15,SPRN_SRR1;						    \
-	std	r16,EX_TLB_R16(r12);					    \
-	mfspr	r16,SPRN_SRR0;						    \
-	std	r10,EX_TLB_CR(r12);					    \
-	std	r11,EX_TLB_R12(r12);					    \
-	mtspr	SPRN_SPRG_TLB_EXFRAME,r14;				    \
-	std	r15,EX_TLB_SRR1(r12);					    \
-	std	r16,EX_TLB_SRR0(r12);					    \
-	TLB_MISS_PROLOG_STATS
-
-/* And these are the matching epilogs that restores things
- *
- * There are 3 epilogs:
- *
- * - SUCCESS       : Unwinds one level
- * - ERROR         : restore from level 0 and reset
- * - ERROR_SPECIAL : restore from current level and reset
- *
- * Normal errors use ERROR, that is, they restore the initial fault context
- * and trigger a fault. However, there is a special case for linear mapping
- * errors. Those should basically never happen, but if they do happen, we
- * want the error to point out the context that did that linear mapping
- * fault, not the initial level 0 (basically, we got a bogus PGF or something
- * like that). For userland errors on the linear mapping, there is no
- * difference since those are always level 0 anyway
- */
-
-#define TLB_MISS_RESTORE(freg)						    \
-	ld	r14,EX_TLB_CR(r12);					    \
-	ld	r10,EX_TLB_R10(r12);					    \
-	ld	r15,EX_TLB_SRR0(r12);					    \
-	ld	r16,EX_TLB_SRR1(r12);					    \
-	mtspr	SPRN_SPRG_TLB_EXFRAME,freg;				    \
-	ld	r11,EX_TLB_R11(r12);					    \
-	mtcr	r14;							    \
-	ld	r13,EX_TLB_R13(r12);					    \
-	ld	r14,EX_TLB_R14(r12);					    \
-	mtspr	SPRN_SRR0,r15;						    \
-	ld	r15,EX_TLB_R15(r12);					    \
-	mtspr	SPRN_SRR1,r16;						    \
-	TLB_MISS_RESTORE_STATS						    \
-	ld	r16,EX_TLB_R16(r12);					    \
-	ld	r12,EX_TLB_R12(r12);					    \
-
-#define TLB_MISS_EPILOG_SUCCESS						    \
-	TLB_MISS_RESTORE(r12)
-
-#define TLB_MISS_EPILOG_ERROR						    \
-	addi	r12,r13,PACA_EXTLB;					    \
-	TLB_MISS_RESTORE(r12)
-
-#define TLB_MISS_EPILOG_ERROR_SPECIAL					    \
-	addi	r11,r13,PACA_EXTLB;					    \
-	TLB_MISS_RESTORE(r11)
-
-#ifdef CONFIG_BOOK3E_MMU_TLB_STATS
-#define TLB_MISS_PROLOG_STATS						    \
-	mflr	r10;							    \
-	std	r8,EX_TLB_R8(r12);					    \
-	std	r9,EX_TLB_R9(r12);					    \
-	std	r10,EX_TLB_LR(r12);
-#define TLB_MISS_RESTORE_STATS					            \
-	ld	r16,EX_TLB_LR(r12);					    \
-	ld	r9,EX_TLB_R9(r12);					    \
-	ld	r8,EX_TLB_R8(r12);					    \
-	mtlr	r16;
-#define TLB_MISS_PROLOG_STATS_BOLTED						    \
-	mflr	r10;							    \
-	std	r8,PACA_EXTLB+EX_TLB_R8(r13);				    \
-	std	r9,PACA_EXTLB+EX_TLB_R9(r13);				    \
-	std	r10,PACA_EXTLB+EX_TLB_LR(r13);
-#define TLB_MISS_RESTORE_STATS_BOLTED					            \
-	ld	r16,PACA_EXTLB+EX_TLB_LR(r13);				    \
-	ld	r9,PACA_EXTLB+EX_TLB_R9(r13);				    \
-	ld	r8,PACA_EXTLB+EX_TLB_R8(r13);				    \
-	mtlr	r16;
-#define TLB_MISS_STATS_D(name)						    \
-	addi	r9,r13,MMSTAT_DSTATS+name;				    \
-	bl	.tlb_stat_inc;
-#define TLB_MISS_STATS_I(name)						    \
-	addi	r9,r13,MMSTAT_ISTATS+name;				    \
-	bl	.tlb_stat_inc;
-#define TLB_MISS_STATS_X(name)						    \
-	ld	r8,PACA_EXTLB+EX_TLB_ESR(r13);				    \
-	cmpdi	cr2,r8,-1;						    \
-	beq	cr2,61f;						    \
-	addi	r9,r13,MMSTAT_DSTATS+name;				    \
-	b	62f;							    \
-61:	addi	r9,r13,MMSTAT_ISTATS+name;				    \
-62:	bl	.tlb_stat_inc;
-#define TLB_MISS_STATS_SAVE_INFO					    \
-	std	r14,EX_TLB_ESR(r12);	/* save ESR */
-#define TLB_MISS_STATS_SAVE_INFO_BOLTED					    \
-	std	r14,PACA_EXTLB+EX_TLB_ESR(r13);	/* save ESR */
-#else
-#define TLB_MISS_PROLOG_STATS
-#define TLB_MISS_RESTORE_STATS
-#define TLB_MISS_PROLOG_STATS_BOLTED
-#define TLB_MISS_RESTORE_STATS_BOLTED
-#define TLB_MISS_STATS_D(name)
-#define TLB_MISS_STATS_I(name)
-#define TLB_MISS_STATS_X(name)
-#define TLB_MISS_STATS_Y(name)
-#define TLB_MISS_STATS_SAVE_INFO
-#define TLB_MISS_STATS_SAVE_INFO_BOLTED
-#endif
-
-#define SET_IVOR(vector_number, vector_offset)	\
-	li	r3,vector_offset@l; 		\
-	ori	r3,r3,interrupt_base_book3e@l;	\
-	mtspr	SPRN_IVOR##vector_number,r3;
-
-#endif /* _ASM_POWERPC_EXCEPTION_64E_H */
-
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/exception-64s.h b/ANDROID_3.4.5/arch/powerpc/include/asm/exception-64s.h
deleted file mode 100644
index d58fc4e4..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/exception-64s.h
+++ /dev/null
@@ -1,344 +0,0 @@
-#ifndef _ASM_POWERPC_EXCEPTION_H
-#define _ASM_POWERPC_EXCEPTION_H
-/*
- * Extracted from head_64.S
- *
- *  PowerPC version
- *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
- *
- *  Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
- *    Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
- *  Adapted for Power Macintosh by Paul Mackerras.
- *  Low-level exception handlers and MMU support
- *  rewritten by Paul Mackerras.
- *    Copyright (C) 1996 Paul Mackerras.
- *
- *  Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
- *    Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
- *
- *  This file contains the low-level support and setup for the
- *  PowerPC-64 platform, including trap and interrupt dispatch.
- *
- *  This program is free software; you can redistribute it and/or
- *  modify it under the terms of the GNU General Public License
- *  as published by the Free Software Foundation; either version
- *  2 of the License, or (at your option) any later version.
- */
-/*
- * The following macros define the code that appears as
- * the prologue to each of the exception handlers.  They
- * are split into two parts to allow a single kernel binary
- * to be used for pSeries and iSeries.
- *
- * We make as much of the exception code common between native
- * exception handlers (including pSeries LPAR) and iSeries LPAR
- * implementations as possible.
- */
-
-#define EX_R9		0
-#define EX_R10		8
-#define EX_R11		16
-#define EX_R12		24
-#define EX_R13		32
-#define EX_SRR0		40
-#define EX_DAR		48
-#define EX_DSISR	56
-#define EX_CCR		60
-#define EX_R3		64
-#define EX_LR		72
-#define EX_CFAR		80
-
-/*
- * We're short on space and time in the exception prolog, so we can't
- * use the normal SET_REG_IMMEDIATE macro. Normally we just need the
- * low halfword of the address, but for Kdump we need the whole low
- * word.
- */
-#define LOAD_HANDLER(reg, label)					\
-	addi	reg,reg,(label)-_stext;	/* virt addr of handler ... */
-
-/* Exception register prefixes */
-#define EXC_HV	H
-#define EXC_STD
-
-#define __EXCEPTION_PROLOG_1(area, extra, vec)				\
-	GET_PACA(r13);							\
-	std	r9,area+EX_R9(r13);	/* save r9 - r12 */		\
-	std	r10,area+EX_R10(r13);					\
-	BEGIN_FTR_SECTION_NESTED(66);					\
-	mfspr	r10,SPRN_CFAR;						\
-	std	r10,area+EX_CFAR(r13);					\
-	END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66);		\
-	mfcr	r9;							\
-	extra(vec);							\
-	std	r11,area+EX_R11(r13);					\
-	std	r12,area+EX_R12(r13);					\
-	GET_SCRATCH0(r10);						\
-	std	r10,area+EX_R13(r13)
-#define EXCEPTION_PROLOG_1(area, extra, vec)				\
-	__EXCEPTION_PROLOG_1(area, extra, vec)
-
-#define __EXCEPTION_PROLOG_PSERIES_1(label, h)				\
-	ld	r12,PACAKBASE(r13);	/* get high part of &label */	\
-	ld	r10,PACAKMSR(r13);	/* get MSR value for kernel */	\
-	mfspr	r11,SPRN_##h##SRR0;	/* save SRR0 */			\
-	LOAD_HANDLER(r12,label)						\
-	mtspr	SPRN_##h##SRR0,r12;					\
-	mfspr	r12,SPRN_##h##SRR1;	/* and SRR1 */			\
-	mtspr	SPRN_##h##SRR1,r10;					\
-	h##rfid;							\
-	b	.	/* prevent speculative execution */
-#define EXCEPTION_PROLOG_PSERIES_1(label, h)				\
-	__EXCEPTION_PROLOG_PSERIES_1(label, h)
-
-#define EXCEPTION_PROLOG_PSERIES(area, label, h, extra, vec)		\
-	EXCEPTION_PROLOG_1(area, extra, vec);				\
-	EXCEPTION_PROLOG_PSERIES_1(label, h);
-
-#define __KVMTEST(n)							\
-	lbz	r10,HSTATE_IN_GUEST(r13);			\
-	cmpwi	r10,0;							\
-	bne	do_kvm_##n
-
-#define __KVM_HANDLER(area, h, n)					\
-do_kvm_##n:								\
-	ld	r10,area+EX_R10(r13);					\
-	stw	r9,HSTATE_SCRATCH1(r13);			\
-	ld	r9,area+EX_R9(r13);					\
-	std	r12,HSTATE_SCRATCH0(r13);			\
-	li	r12,n;							\
-	b	kvmppc_interrupt
-
-#define __KVM_HANDLER_SKIP(area, h, n)					\
-do_kvm_##n:								\
-	cmpwi	r10,KVM_GUEST_MODE_SKIP;				\
-	ld	r10,area+EX_R10(r13);					\
-	beq	89f;							\
-	stw	r9,HSTATE_SCRATCH1(r13);			\
-	ld	r9,area+EX_R9(r13);					\
-	std	r12,HSTATE_SCRATCH0(r13);			\
-	li	r12,n;							\
-	b	kvmppc_interrupt;					\
-89:	mtocrf	0x80,r9;						\
-	ld	r9,area+EX_R9(r13);					\
-	b	kvmppc_skip_##h##interrupt
-
-#ifdef CONFIG_KVM_BOOK3S_64_HANDLER
-#define KVMTEST(n)			__KVMTEST(n)
-#define KVM_HANDLER(area, h, n)		__KVM_HANDLER(area, h, n)
-#define KVM_HANDLER_SKIP(area, h, n)	__KVM_HANDLER_SKIP(area, h, n)
-
-#else
-#define KVMTEST(n)
-#define KVM_HANDLER(area, h, n)
-#define KVM_HANDLER_SKIP(area, h, n)
-#endif
-
-#ifdef CONFIG_KVM_BOOK3S_PR
-#define KVMTEST_PR(n)			__KVMTEST(n)
-#define KVM_HANDLER_PR(area, h, n)	__KVM_HANDLER(area, h, n)
-#define KVM_HANDLER_PR_SKIP(area, h, n)	__KVM_HANDLER_SKIP(area, h, n)
-
-#else
-#define KVMTEST_PR(n)
-#define KVM_HANDLER_PR(area, h, n)
-#define KVM_HANDLER_PR_SKIP(area, h, n)
-#endif
-
-#define NOTEST(n)
-
-/*
- * The common exception prolog is used for all except a few exceptions
- * such as a segment miss on a kernel address.  We have to be prepared
- * to take another exception from the point where we first touch the
- * kernel stack onwards.
- *
- * On entry r13 points to the paca, r9-r13 are saved in the paca,
- * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
- * SRR1, and relocation is on.
- */
-#define EXCEPTION_PROLOG_COMMON(n, area)				   \
-	andi.	r10,r12,MSR_PR;		/* See if coming from user	*/ \
-	mr	r10,r1;			/* Save r1			*/ \
-	subi	r1,r1,INT_FRAME_SIZE;	/* alloc frame on kernel stack	*/ \
-	beq-	1f;							   \
-	ld	r1,PACAKSAVE(r13);	/* kernel stack to use		*/ \
-1:	cmpdi	cr1,r1,0;		/* check if r1 is in userspace	*/ \
-	blt+	cr1,3f;			/* abort if it is		*/ \
-	li	r1,(n);			/* will be reloaded later	*/ \
-	sth	r1,PACA_TRAP_SAVE(r13);					   \
-	std	r3,area+EX_R3(r13);					   \
-	addi	r3,r13,area;		/* r3 -> where regs are saved*/	   \
-	b	bad_stack;						   \
-3:	std	r9,_CCR(r1);		/* save CR in stackframe	*/ \
-	std	r11,_NIP(r1);		/* save SRR0 in stackframe	*/ \
-	std	r12,_MSR(r1);		/* save SRR1 in stackframe	*/ \
-	std	r10,0(r1);		/* make stack chain pointer	*/ \
-	std	r0,GPR0(r1);		/* save r0 in stackframe	*/ \
-	std	r10,GPR1(r1);		/* save r1 in stackframe	*/ \
-	ACCOUNT_CPU_USER_ENTRY(r9, r10);				   \
-	std	r2,GPR2(r1);		/* save r2 in stackframe	*/ \
-	SAVE_4GPRS(3, r1);		/* save r3 - r6 in stackframe	*/ \
-	SAVE_2GPRS(7, r1);		/* save r7, r8 in stackframe	*/ \
-	ld	r9,area+EX_R9(r13);	/* move r9, r10 to stackframe	*/ \
-	ld	r10,area+EX_R10(r13);					   \
-	std	r9,GPR9(r1);						   \
-	std	r10,GPR10(r1);						   \
-	ld	r9,area+EX_R11(r13);	/* move r11 - r13 to stackframe	*/ \
-	ld	r10,area+EX_R12(r13);					   \
-	ld	r11,area+EX_R13(r13);					   \
-	std	r9,GPR11(r1);						   \
-	std	r10,GPR12(r1);						   \
-	std	r11,GPR13(r1);						   \
-	BEGIN_FTR_SECTION_NESTED(66);					   \
-	ld	r10,area+EX_CFAR(r13);					   \
-	std	r10,ORIG_GPR3(r1);					   \
-	END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66);		   \
-	ld	r2,PACATOC(r13);	/* get kernel TOC into r2	*/ \
-	mflr	r9;			/* save LR in stackframe	*/ \
-	std	r9,_LINK(r1);						   \
-	mfctr	r10;			/* save CTR in stackframe	*/ \
-	std	r10,_CTR(r1);						   \
-	lbz	r10,PACASOFTIRQEN(r13);				   \
-	mfspr	r11,SPRN_XER;		/* save XER in stackframe	*/ \
-	std	r10,SOFTE(r1);						   \
-	std	r11,_XER(r1);						   \
-	li	r9,(n)+1;						   \
-	std	r9,_TRAP(r1);		/* set trap number		*/ \
-	li	r10,0;							   \
-	ld	r11,exception_marker@toc(r2);				   \
-	std	r10,RESULT(r1);		/* clear regs->result		*/ \
-	std	r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame	*/ \
-	ACCOUNT_STOLEN_TIME
-
-/*
- * Exception vectors.
- */
-#define STD_EXCEPTION_PSERIES(loc, vec, label)		\
-	. = loc;					\
-	.globl label##_pSeries;				\
-label##_pSeries:					\
-	HMT_MEDIUM;					\
-	SET_SCRATCH0(r13);		/* save r13 */		\
-	EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common,	\
-				 EXC_STD, KVMTEST_PR, vec)
-
-#define STD_EXCEPTION_HV(loc, vec, label)		\
-	. = loc;					\
-	.globl label##_hv;				\
-label##_hv:						\
-	HMT_MEDIUM;					\
-	SET_SCRATCH0(r13);	/* save r13 */			\
-	EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common,	\
-				 EXC_HV, KVMTEST, vec)
-
-/* This associate vector numbers with bits in paca->irq_happened */
-#define SOFTEN_VALUE_0x500	PACA_IRQ_EE
-#define SOFTEN_VALUE_0x502	PACA_IRQ_EE
-#define SOFTEN_VALUE_0x900	PACA_IRQ_DEC
-#define SOFTEN_VALUE_0x982	PACA_IRQ_DEC
-
-#define __SOFTEN_TEST(h, vec)						\
-	lbz	r10,PACASOFTIRQEN(r13);					\
-	cmpwi	r10,0;							\
-	li	r10,SOFTEN_VALUE_##vec;					\
-	beq	masked_##h##interrupt
-#define _SOFTEN_TEST(h, vec)	__SOFTEN_TEST(h, vec)
-
-#define SOFTEN_TEST_PR(vec)						\
-	KVMTEST_PR(vec);						\
-	_SOFTEN_TEST(EXC_STD, vec)
-
-#define SOFTEN_TEST_HV(vec)						\
-	KVMTEST(vec);							\
-	_SOFTEN_TEST(EXC_HV, vec)
-
-#define SOFTEN_TEST_HV_201(vec)						\
-	KVMTEST(vec);							\
-	_SOFTEN_TEST(EXC_STD, vec)
-
-#define __MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra)		\
-	HMT_MEDIUM;							\
-	SET_SCRATCH0(r13);    /* save r13 */				\
-	__EXCEPTION_PROLOG_1(PACA_EXGEN, extra, vec);		\
-	EXCEPTION_PROLOG_PSERIES_1(label##_common, h);
-#define _MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra)		\
-	__MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra)
-
-#define MASKABLE_EXCEPTION_PSERIES(loc, vec, label)			\
-	. = loc;							\
-	.globl label##_pSeries;						\
-label##_pSeries:							\
-	_MASKABLE_EXCEPTION_PSERIES(vec, label,				\
-				    EXC_STD, SOFTEN_TEST_PR)
-
-#define MASKABLE_EXCEPTION_HV(loc, vec, label)				\
-	. = loc;							\
-	.globl label##_hv;						\
-label##_hv:								\
-	_MASKABLE_EXCEPTION_PSERIES(vec, label,				\
-				    EXC_HV, SOFTEN_TEST_HV)
-
-/*
- * Our exception common code can be passed various "additions"
- * to specify the behaviour of interrupts, whether to kick the
- * runlatch, etc...
- */
-
-/* Exception addition: Hard disable interrupts */
-#define DISABLE_INTS	SOFT_DISABLE_INTS(r10,r11)
-
-#define ADD_NVGPRS				\
-	bl	.save_nvgprs
-
-#define RUNLATCH_ON				\
-BEGIN_FTR_SECTION				\
-	clrrdi	r3,r1,THREAD_SHIFT;		\
-	ld	r4,TI_LOCAL_FLAGS(r3);		\
-	andi.	r0,r4,_TLF_RUNLATCH;		\
-	beql	ppc64_runlatch_on_trampoline;	\
-END_FTR_SECTION_IFSET(CPU_FTR_CTRL)
-
-#define EXCEPTION_COMMON(trap, label, hdlr, ret, additions)	\
-	.align	7;						\
-	.globl label##_common;					\
-label##_common:							\
-	EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN);		\
-	additions;						\
-	addi	r3,r1,STACK_FRAME_OVERHEAD;			\
-	bl	hdlr;						\
-	b	ret
-
-#define STD_EXCEPTION_COMMON(trap, label, hdlr)			\
-	EXCEPTION_COMMON(trap, label, hdlr, ret_from_except,	\
-			 ADD_NVGPRS;DISABLE_INTS)
-
-/*
- * Like STD_EXCEPTION_COMMON, but for exceptions that can occur
- * in the idle task and therefore need the special idle handling
- * (finish nap and runlatch)
- */
-#define STD_EXCEPTION_COMMON_ASYNC(trap, label, hdlr)		  \
-	EXCEPTION_COMMON(trap, label, hdlr, ret_from_except_lite, \
-			 FINISH_NAP;RUNLATCH_ON;DISABLE_INTS)
-
-/*
- * When the idle code in power4_idle puts the CPU into NAP mode,
- * it has to do so in a loop, and relies on the external interrupt
- * and decrementer interrupt entry code to get it out of the loop.
- * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags
- * to signal that it is in the loop and needs help to get out.
- */
-#ifdef CONFIG_PPC_970_NAP
-#define FINISH_NAP				\
-BEGIN_FTR_SECTION				\
-	clrrdi	r11,r1,THREAD_SHIFT;		\
-	ld	r9,TI_LOCAL_FLAGS(r11);		\
-	andi.	r10,r9,_TLF_NAPPING;		\
-	bnel	power4_fixup_nap;		\
-END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
-#else
-#define FINISH_NAP
-#endif
-
-#endif	/* _ASM_POWERPC_EXCEPTION_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/exec.h b/ANDROID_3.4.5/arch/powerpc/include/asm/exec.h
deleted file mode 100644
index 8196e9c7..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/exec.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
- */
-#ifndef _ASM_POWERPC_EXEC_H
-#define _ASM_POWERPC_EXEC_H
-
-extern unsigned long arch_align_stack(unsigned long sp);
-
-#endif /* _ASM_POWERPC_EXEC_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/fadump.h b/ANDROID_3.4.5/arch/powerpc/include/asm/fadump.h
deleted file mode 100644
index 88dbf965..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/fadump.h
+++ /dev/null
@@ -1,218 +0,0 @@
-/*
- * Firmware Assisted dump header file.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Copyright 2011 IBM Corporation
- * Author: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
- */
-
-#ifndef __PPC64_FA_DUMP_H__
-#define __PPC64_FA_DUMP_H__
-
-#ifdef CONFIG_FA_DUMP
-
-/*
- * The RMA region will be saved for later dumping when kernel crashes.
- * RMA is Real Mode Area, the first block of logical memory address owned
- * by logical partition, containing the storage that may be accessed with
- * translate off.
- */
-#define RMA_START	0x0
-#define RMA_END		(ppc64_rma_size)
-
-/*
- * On some Power systems where RMO is 128MB, it still requires minimum of
- * 256MB for kernel to boot successfully. When kdump infrastructure is
- * configured to save vmcore over network, we run into OOM issue while
- * loading modules related to network setup. Hence we need aditional 64M
- * of memory to avoid OOM issue.
- */
-#define MIN_BOOT_MEM	(((RMA_END < (0x1UL << 28)) ? (0x1UL << 28) : RMA_END) \
-			+ (0x1UL << 26))
-
-#define memblock_num_regions(memblock_type)	(memblock.memblock_type.cnt)
-
-#ifndef ELF_CORE_EFLAGS
-#define ELF_CORE_EFLAGS 0
-#endif
-
-/* Firmware provided dump sections */
-#define FADUMP_CPU_STATE_DATA	0x0001
-#define FADUMP_HPTE_REGION	0x0002
-#define FADUMP_REAL_MODE_REGION	0x0011
-
-/* Dump request flag */
-#define FADUMP_REQUEST_FLAG	0x00000001
-
-/* FAD commands */
-#define FADUMP_REGISTER		1
-#define FADUMP_UNREGISTER	2
-#define FADUMP_INVALIDATE	3
-
-/* Dump status flag */
-#define FADUMP_ERROR_FLAG	0x2000
-
-#define FADUMP_CPU_ID_MASK	((1UL << 32) - 1)
-
-#define CPU_UNKNOWN		(~((u32)0))
-
-/* Utility macros */
-#define SKIP_TO_NEXT_CPU(reg_entry)			\
-({							\
-	while (reg_entry->reg_id != REG_ID("CPUEND"))	\
-		reg_entry++;				\
-	reg_entry++;					\
-})
-
-/* Kernel Dump section info */
-struct fadump_section {
-	u32	request_flag;
-	u16	source_data_type;
-	u16	error_flags;
-	u64	source_address;
-	u64	source_len;
-	u64	bytes_dumped;
-	u64	destination_address;
-};
-
-/* ibm,configure-kernel-dump header. */
-struct fadump_section_header {
-	u32	dump_format_version;
-	u16	dump_num_sections;
-	u16	dump_status_flag;
-	u32	offset_first_dump_section;
-
-	/* Fields for disk dump option. */
-	u32	dd_block_size;
-	u64	dd_block_offset;
-	u64	dd_num_blocks;
-	u32	dd_offset_disk_path;
-
-	/* Maximum time allowed to prevent an automatic dump-reboot. */
-	u32	max_time_auto;
-};
-
-/*
- * Firmware Assisted dump memory structure. This structure is required for
- * registering future kernel dump with power firmware through rtas call.
- *
- * No disk dump option. Hence disk dump path string section is not included.
- */
-struct fadump_mem_struct {
-	struct fadump_section_header	header;
-
-	/* Kernel dump sections */
-	struct fadump_section		cpu_state_data;
-	struct fadump_section		hpte_region;
-	struct fadump_section		rmr_region;
-};
-
-/* Firmware-assisted dump configuration details. */
-struct fw_dump {
-	unsigned long	cpu_state_data_size;
-	unsigned long	hpte_region_size;
-	unsigned long	boot_memory_size;
-	unsigned long	reserve_dump_area_start;
-	unsigned long	reserve_dump_area_size;
-	/* cmd line option during boot */
-	unsigned long	reserve_bootvar;
-
-	unsigned long	fadumphdr_addr;
-	unsigned long	cpu_notes_buf;
-	unsigned long	cpu_notes_buf_size;
-
-	int		ibm_configure_kernel_dump;
-
-	unsigned long	fadump_enabled:1;
-	unsigned long	fadump_supported:1;
-	unsigned long	dump_active:1;
-	unsigned long	dump_registered:1;
-};
-
-/*
- * Copy the ascii values for first 8 characters from a string into u64
- * variable at their respective indexes.
- * e.g.
- *  The string "FADMPINF" will be converted into 0x4641444d50494e46
- */
-static inline u64 str_to_u64(const char *str)
-{
-	u64 val = 0;
-	int i;
-
-	for (i = 0; i < sizeof(val); i++)
-		val = (*str) ? (val << 8) | *str++ : val << 8;
-	return val;
-}
-#define STR_TO_HEX(x)	str_to_u64(x)
-#define REG_ID(x)	str_to_u64(x)
-
-#define FADUMP_CRASH_INFO_MAGIC		STR_TO_HEX("FADMPINF")
-#define REGSAVE_AREA_MAGIC		STR_TO_HEX("REGSAVE")
-
-/* The firmware-assisted dump format.
- *
- * The register save area is an area in the partition's memory used to preserve
- * the register contents (CPU state data) for the active CPUs during a firmware
- * assisted dump. The dump format contains register save area header followed
- * by register entries. Each list of registers for a CPU starts with
- * "CPUSTRT" and ends with "CPUEND".
- */
-
-/* Register save area header. */
-struct fadump_reg_save_area_header {
-	u64		magic_number;
-	u32		version;
-	u32		num_cpu_offset;
-};
-
-/* Register entry. */
-struct fadump_reg_entry {
-	u64		reg_id;
-	u64		reg_value;
-};
-
-/* fadump crash info structure */
-struct fadump_crash_info_header {
-	u64		magic_number;
-	u64		elfcorehdr_addr;
-	u32		crashing_cpu;
-	struct pt_regs	regs;
-	struct cpumask	cpu_online_mask;
-};
-
-/* Crash memory ranges */
-#define INIT_CRASHMEM_RANGES	(INIT_MEMBLOCK_REGIONS + 2)
-
-struct fad_crash_memory_ranges {
-	unsigned long long	base;
-	unsigned long long	size;
-};
-
-extern int early_init_dt_scan_fw_dump(unsigned long node,
-		const char *uname, int depth, void *data);
-extern int fadump_reserve_mem(void);
-extern int setup_fadump(void);
-extern int is_fadump_active(void);
-extern void crash_fadump(struct pt_regs *, const char *);
-extern void fadump_cleanup(void);
-
-extern void vmcore_cleanup(void);
-#else	/* CONFIG_FA_DUMP */
-static inline int is_fadump_active(void) { return 0; }
-static inline void crash_fadump(struct pt_regs *regs, const char *str) { }
-#endif
-#endif
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/fb.h b/ANDROID_3.4.5/arch/powerpc/include/asm/fb.h
deleted file mode 100644
index 411af8d1..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/fb.h
+++ /dev/null
@@ -1,21 +0,0 @@
-#ifndef _ASM_FB_H_
-#define _ASM_FB_H_
-
-#include <linux/fb.h>
-#include <linux/fs.h>
-#include <asm/page.h>
-
-static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
-				unsigned long off)
-{
-	vma->vm_page_prot = phys_mem_access_prot(file, off >> PAGE_SHIFT,
-						 vma->vm_end - vma->vm_start,
-						 vma->vm_page_prot);
-}
-
-static inline int fb_is_primary_device(struct fb_info *info)
-{
-	return 0;
-}
-
-#endif /* _ASM_FB_H_ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/fcntl.h b/ANDROID_3.4.5/arch/powerpc/include/asm/fcntl.h
deleted file mode 100644
index ce5c4516..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/fcntl.h
+++ /dev/null
@@ -1,11 +0,0 @@
-#ifndef _ASM_FCNTL_H
-#define _ASM_FCNTL_H
-
-#define O_DIRECTORY      040000	/* must be a directory */
-#define O_NOFOLLOW      0100000	/* don't follow links */
-#define O_LARGEFILE     0200000
-#define O_DIRECT	0400000	/* direct disk access hint */
-
-#include <asm-generic/fcntl.h>
-
-#endif /* _ASM_FCNTL_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/feature-fixups.h b/ANDROID_3.4.5/arch/powerpc/include/asm/feature-fixups.h
deleted file mode 100644
index 9a67a38b..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/feature-fixups.h
+++ /dev/null
@@ -1,187 +0,0 @@
-#ifndef __ASM_POWERPC_FEATURE_FIXUPS_H
-#define __ASM_POWERPC_FEATURE_FIXUPS_H
-
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-/*
- * Feature section common macros
- *
- * Note that the entries now contain offsets between the table entry
- * and the code rather than absolute code pointers in order to be
- * useable with the vdso shared library. There is also an assumption
- * that values will be negative, that is, the fixup table has to be
- * located after the code it fixes up.
- */
-#if defined(CONFIG_PPC64) && !defined(__powerpc64__)
-/* 64 bits kernel, 32 bits code (ie. vdso32) */
-#define FTR_ENTRY_LONG		.llong
-#define FTR_ENTRY_OFFSET	.long 0xffffffff; .long
-#elif defined(CONFIG_PPC64)
-#define FTR_ENTRY_LONG		.llong
-#define FTR_ENTRY_OFFSET	.llong
-#else
-#define FTR_ENTRY_LONG		.long
-#define FTR_ENTRY_OFFSET	.long
-#endif
-
-#define START_FTR_SECTION(label)	label##1:
-
-#define FTR_SECTION_ELSE_NESTED(label)			\
-label##2:						\
-	.pushsection __ftr_alt_##label,"a";		\
-	.align 2;					\
-label##3:
-
-#define MAKE_FTR_SECTION_ENTRY(msk, val, label, sect)		\
-label##4:							\
-	.popsection;						\
-	.pushsection sect,"a";					\
-	.align 3;						\
-label##5:							\
-	FTR_ENTRY_LONG msk;					\
-	FTR_ENTRY_LONG val;					\
-	FTR_ENTRY_OFFSET label##1b-label##5b;			\
-	FTR_ENTRY_OFFSET label##2b-label##5b;			\
-	FTR_ENTRY_OFFSET label##3b-label##5b;			\
-	FTR_ENTRY_OFFSET label##4b-label##5b;			\
-	.ifgt (label##4b- label##3b)-(label##2b- label##1b);	\
-	.error "Feature section else case larger than body";	\
-	.endif;							\
-	.popsection;
-
-
-/* CPU feature dependent sections */
-#define BEGIN_FTR_SECTION_NESTED(label)	START_FTR_SECTION(label)
-#define BEGIN_FTR_SECTION		START_FTR_SECTION(97)
-
-#define END_FTR_SECTION_NESTED(msk, val, label) 		\
-	FTR_SECTION_ELSE_NESTED(label)				\
-	MAKE_FTR_SECTION_ENTRY(msk, val, label, __ftr_fixup)
-
-#define END_FTR_SECTION(msk, val)		\
-	END_FTR_SECTION_NESTED(msk, val, 97)
-
-#define END_FTR_SECTION_IFSET(msk)	END_FTR_SECTION((msk), (msk))
-#define END_FTR_SECTION_IFCLR(msk)	END_FTR_SECTION((msk), 0)
-
-/* CPU feature sections with alternatives, use BEGIN_FTR_SECTION to start */
-#define FTR_SECTION_ELSE	FTR_SECTION_ELSE_NESTED(97)
-#define ALT_FTR_SECTION_END_NESTED(msk, val, label)	\
-	MAKE_FTR_SECTION_ENTRY(msk, val, label, __ftr_fixup)
-#define ALT_FTR_SECTION_END_NESTED_IFSET(msk, label)	\
-	ALT_FTR_SECTION_END_NESTED(msk, msk, label)
-#define ALT_FTR_SECTION_END_NESTED_IFCLR(msk, label)	\
-	ALT_FTR_SECTION_END_NESTED(msk, 0, label)
-#define ALT_FTR_SECTION_END(msk, val)	\
-	ALT_FTR_SECTION_END_NESTED(msk, val, 97)
-#define ALT_FTR_SECTION_END_IFSET(msk)	\
-	ALT_FTR_SECTION_END_NESTED_IFSET(msk, 97)
-#define ALT_FTR_SECTION_END_IFCLR(msk)	\
-	ALT_FTR_SECTION_END_NESTED_IFCLR(msk, 97)
-
-/* MMU feature dependent sections */
-#define BEGIN_MMU_FTR_SECTION_NESTED(label)	START_FTR_SECTION(label)
-#define BEGIN_MMU_FTR_SECTION			START_FTR_SECTION(97)
-
-#define END_MMU_FTR_SECTION_NESTED(msk, val, label) 		\
-	FTR_SECTION_ELSE_NESTED(label)				\
-	MAKE_FTR_SECTION_ENTRY(msk, val, label, __mmu_ftr_fixup)
-
-#define END_MMU_FTR_SECTION(msk, val)		\
-	END_MMU_FTR_SECTION_NESTED(msk, val, 97)
-
-#define END_MMU_FTR_SECTION_IFSET(msk)	END_MMU_FTR_SECTION((msk), (msk))
-#define END_MMU_FTR_SECTION_IFCLR(msk)	END_MMU_FTR_SECTION((msk), 0)
-
-/* MMU feature sections with alternatives, use BEGIN_FTR_SECTION to start */
-#define MMU_FTR_SECTION_ELSE_NESTED(label)	FTR_SECTION_ELSE_NESTED(label)
-#define MMU_FTR_SECTION_ELSE	MMU_FTR_SECTION_ELSE_NESTED(97)
-#define ALT_MMU_FTR_SECTION_END_NESTED(msk, val, label)	\
-	MAKE_FTR_SECTION_ENTRY(msk, val, label, __mmu_ftr_fixup)
-#define ALT_MMU_FTR_SECTION_END_NESTED_IFSET(msk, label)	\
-	ALT_MMU_FTR_SECTION_END_NESTED(msk, msk, label)
-#define ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(msk, label)	\
-	ALT_MMU_FTR_SECTION_END_NESTED(msk, 0, label)
-#define ALT_MMU_FTR_SECTION_END(msk, val)	\
-	ALT_MMU_FTR_SECTION_END_NESTED(msk, val, 97)
-#define ALT_MMU_FTR_SECTION_END_IFSET(msk)	\
-	ALT_MMU_FTR_SECTION_END_NESTED_IFSET(msk, 97)
-#define ALT_MMU_FTR_SECTION_END_IFCLR(msk)	\
-	ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(msk, 97)
-
-/* Firmware feature dependent sections */
-#define BEGIN_FW_FTR_SECTION_NESTED(label)	START_FTR_SECTION(label)
-#define BEGIN_FW_FTR_SECTION			START_FTR_SECTION(97)
-
-#define END_FW_FTR_SECTION_NESTED(msk, val, label) 		\
-	FTR_SECTION_ELSE_NESTED(label)				\
-	MAKE_FTR_SECTION_ENTRY(msk, val, label, __fw_ftr_fixup)
-
-#define END_FW_FTR_SECTION(msk, val)		\
-	END_FW_FTR_SECTION_NESTED(msk, val, 97)
-
-#define END_FW_FTR_SECTION_IFSET(msk)	END_FW_FTR_SECTION((msk), (msk))
-#define END_FW_FTR_SECTION_IFCLR(msk)	END_FW_FTR_SECTION((msk), 0)
-
-/* Firmware feature sections with alternatives */
-#define FW_FTR_SECTION_ELSE_NESTED(label)	FTR_SECTION_ELSE_NESTED(label)
-#define FW_FTR_SECTION_ELSE	FTR_SECTION_ELSE_NESTED(97)
-#define ALT_FW_FTR_SECTION_END_NESTED(msk, val, label)	\
-	MAKE_FTR_SECTION_ENTRY(msk, val, label, __fw_ftr_fixup)
-#define ALT_FW_FTR_SECTION_END_NESTED_IFSET(msk, label)	\
-	ALT_FW_FTR_SECTION_END_NESTED(msk, msk, label)
-#define ALT_FW_FTR_SECTION_END_NESTED_IFCLR(msk, label)	\
-	ALT_FW_FTR_SECTION_END_NESTED(msk, 0, label)
-#define ALT_FW_FTR_SECTION_END(msk, val)	\
-	ALT_FW_FTR_SECTION_END_NESTED(msk, val, 97)
-#define ALT_FW_FTR_SECTION_END_IFSET(msk)	\
-	ALT_FW_FTR_SECTION_END_NESTED_IFSET(msk, 97)
-#define ALT_FW_FTR_SECTION_END_IFCLR(msk)	\
-	ALT_FW_FTR_SECTION_END_NESTED_IFCLR(msk, 97)
-
-#ifndef __ASSEMBLY__
-
-#define ASM_FTR_IF(section_if, section_else, msk, val)	\
-	stringify_in_c(BEGIN_FTR_SECTION)			\
-	section_if "; "						\
-	stringify_in_c(FTR_SECTION_ELSE)			\
-	section_else "; "					\
-	stringify_in_c(ALT_FTR_SECTION_END((msk), (val)))
-
-#define ASM_FTR_IFSET(section_if, section_else, msk)	\
-	ASM_FTR_IF(section_if, section_else, (msk), (msk))
-
-#define ASM_FTR_IFCLR(section_if, section_else, msk)	\
-	ASM_FTR_IF(section_if, section_else, (msk), 0)
-
-#define ASM_MMU_FTR_IF(section_if, section_else, msk, val)	\
-	stringify_in_c(BEGIN_MMU_FTR_SECTION)			\
-	section_if "; "						\
-	stringify_in_c(MMU_FTR_SECTION_ELSE)			\
-	section_else "; "					\
-	stringify_in_c(ALT_MMU_FTR_SECTION_END((msk), (val)))
-
-#define ASM_MMU_FTR_IFSET(section_if, section_else, msk)	\
-	ASM_MMU_FTR_IF(section_if, section_else, (msk), (msk))
-
-#define ASM_MMU_FTR_IFCLR(section_if, section_else, msk)	\
-	ASM_MMU_FTR_IF(section_if, section_else, (msk), 0)
-
-#endif /* __ASSEMBLY__ */
-
-/* LWSYNC feature sections */
-#define START_LWSYNC_SECTION(label)	label##1:
-#define MAKE_LWSYNC_SECTION_ENTRY(label, sect)		\
-label##2:						\
-	.pushsection sect,"a";				\
-	.align 2;					\
-label##3:					       	\
-	FTR_ENTRY_OFFSET label##1b-label##3b;		\
-	.popsection;
-
-#endif /* __ASM_POWERPC_FEATURE_FIXUPS_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/firmware.h b/ANDROID_3.4.5/arch/powerpc/include/asm/firmware.h
deleted file mode 100644
index ad0b751b..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/firmware.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- *  Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
- *
- *  Modifications for ppc64:
- *      Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
- *
- *  This program is free software; you can redistribute it and/or
- *  modify it under the terms of the GNU General Public License
- *  as published by the Free Software Foundation; either version
- *  2 of the License, or (at your option) any later version.
- */
-#ifndef __ASM_POWERPC_FIRMWARE_H
-#define __ASM_POWERPC_FIRMWARE_H
-
-#ifdef __KERNEL__
-
-#include <asm/asm-compat.h>
-#include <asm/feature-fixups.h>
-
-/* firmware feature bitmask values */
-#define FIRMWARE_MAX_FEATURES 63
-
-#define FW_FEATURE_PFT		ASM_CONST(0x0000000000000001)
-#define FW_FEATURE_TCE		ASM_CONST(0x0000000000000002)
-#define FW_FEATURE_SPRG0	ASM_CONST(0x0000000000000004)
-#define FW_FEATURE_DABR		ASM_CONST(0x0000000000000008)
-#define FW_FEATURE_COPY		ASM_CONST(0x0000000000000010)
-#define FW_FEATURE_ASR		ASM_CONST(0x0000000000000020)
-#define FW_FEATURE_DEBUG	ASM_CONST(0x0000000000000040)
-#define FW_FEATURE_TERM		ASM_CONST(0x0000000000000080)
-#define FW_FEATURE_PERF		ASM_CONST(0x0000000000000100)
-#define FW_FEATURE_DUMP		ASM_CONST(0x0000000000000200)
-#define FW_FEATURE_INTERRUPT	ASM_CONST(0x0000000000000400)
-#define FW_FEATURE_MIGRATE	ASM_CONST(0x0000000000000800)
-#define FW_FEATURE_PERFMON	ASM_CONST(0x0000000000001000)
-#define FW_FEATURE_CRQ		ASM_CONST(0x0000000000002000)
-#define FW_FEATURE_VIO		ASM_CONST(0x0000000000004000)
-#define FW_FEATURE_RDMA		ASM_CONST(0x0000000000008000)
-#define FW_FEATURE_LLAN		ASM_CONST(0x0000000000010000)
-#define FW_FEATURE_BULK_REMOVE	ASM_CONST(0x0000000000020000)
-#define FW_FEATURE_XDABR	ASM_CONST(0x0000000000040000)
-#define FW_FEATURE_MULTITCE	ASM_CONST(0x0000000000080000)
-#define FW_FEATURE_SPLPAR	ASM_CONST(0x0000000000100000)
-#define FW_FEATURE_LPAR		ASM_CONST(0x0000000000400000)
-#define FW_FEATURE_PS3_LV1	ASM_CONST(0x0000000000800000)
-#define FW_FEATURE_BEAT		ASM_CONST(0x0000000001000000)
-#define FW_FEATURE_CMO		ASM_CONST(0x0000000002000000)
-#define FW_FEATURE_VPHN		ASM_CONST(0x0000000004000000)
-#define FW_FEATURE_XCMO		ASM_CONST(0x0000000008000000)
-#define FW_FEATURE_OPAL		ASM_CONST(0x0000000010000000)
-#define FW_FEATURE_OPALv2	ASM_CONST(0x0000000020000000)
-
-#ifndef __ASSEMBLY__
-
-enum {
-#ifdef CONFIG_PPC64
-	FW_FEATURE_PSERIES_POSSIBLE = FW_FEATURE_PFT | FW_FEATURE_TCE |
-		FW_FEATURE_SPRG0 | FW_FEATURE_DABR | FW_FEATURE_COPY |
-		FW_FEATURE_ASR | FW_FEATURE_DEBUG | FW_FEATURE_TERM |
-		FW_FEATURE_PERF | FW_FEATURE_DUMP | FW_FEATURE_INTERRUPT |
-		FW_FEATURE_MIGRATE | FW_FEATURE_PERFMON | FW_FEATURE_CRQ |
-		FW_FEATURE_VIO | FW_FEATURE_RDMA | FW_FEATURE_LLAN |
-		FW_FEATURE_BULK_REMOVE | FW_FEATURE_XDABR |
-		FW_FEATURE_MULTITCE | FW_FEATURE_SPLPAR | FW_FEATURE_LPAR |
-		FW_FEATURE_CMO | FW_FEATURE_VPHN | FW_FEATURE_XCMO,
-	FW_FEATURE_PSERIES_ALWAYS = 0,
-	FW_FEATURE_POWERNV_POSSIBLE = FW_FEATURE_OPAL | FW_FEATURE_OPALv2,
-	FW_FEATURE_POWERNV_ALWAYS = 0,
-	FW_FEATURE_PS3_POSSIBLE = FW_FEATURE_LPAR | FW_FEATURE_PS3_LV1,
-	FW_FEATURE_PS3_ALWAYS = FW_FEATURE_LPAR | FW_FEATURE_PS3_LV1,
-	FW_FEATURE_CELLEB_POSSIBLE = FW_FEATURE_LPAR | FW_FEATURE_BEAT,
-	FW_FEATURE_CELLEB_ALWAYS = 0,
-	FW_FEATURE_NATIVE_POSSIBLE = 0,
-	FW_FEATURE_NATIVE_ALWAYS = 0,
-	FW_FEATURE_POSSIBLE =
-#ifdef CONFIG_PPC_PSERIES
-		FW_FEATURE_PSERIES_POSSIBLE |
-#endif
-#ifdef CONFIG_PPC_POWERNV
-		FW_FEATURE_POWERNV_POSSIBLE |
-#endif
-#ifdef CONFIG_PPC_PS3
-		FW_FEATURE_PS3_POSSIBLE |
-#endif
-#ifdef CONFIG_PPC_CELLEB
-		FW_FEATURE_CELLEB_POSSIBLE |
-#endif
-#ifdef CONFIG_PPC_NATIVE
-		FW_FEATURE_NATIVE_ALWAYS |
-#endif
-		0,
-	FW_FEATURE_ALWAYS =
-#ifdef CONFIG_PPC_PSERIES
-		FW_FEATURE_PSERIES_ALWAYS &
-#endif
-#ifdef CONFIG_PPC_POWERNV
-		FW_FEATURE_POWERNV_ALWAYS &
-#endif
-#ifdef CONFIG_PPC_PS3
-		FW_FEATURE_PS3_ALWAYS &
-#endif
-#ifdef CONFIG_PPC_CELLEB
-		FW_FEATURE_CELLEB_ALWAYS &
-#endif
-#ifdef CONFIG_PPC_NATIVE
-		FW_FEATURE_NATIVE_ALWAYS &
-#endif
-		FW_FEATURE_POSSIBLE,
-
-#else /* CONFIG_PPC64 */
-	FW_FEATURE_POSSIBLE = 0,
-	FW_FEATURE_ALWAYS = 0,
-#endif
-};
-
-/* This is used to identify firmware features which are available
- * to the kernel.
- */
-extern unsigned long	powerpc_firmware_features;
-
-#define firmware_has_feature(feature)					\
-	((FW_FEATURE_ALWAYS & (feature)) ||				\
-		(FW_FEATURE_POSSIBLE & powerpc_firmware_features & (feature)))
-
-extern void system_reset_fwnmi(void);
-extern void machine_check_fwnmi(void);
-
-/* This is true if we are using the firmware NMI handler (typically LPAR) */
-extern int fwnmi_active;
-
-extern unsigned int __start___fw_ftr_fixup, __stop___fw_ftr_fixup;
-
-#endif /* __ASSEMBLY__ */
-#endif /* __KERNEL__ */
-#endif /* __ASM_POWERPC_FIRMWARE_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/fixmap.h b/ANDROID_3.4.5/arch/powerpc/include/asm/fixmap.h
deleted file mode 100644
index 5c2c0233..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/fixmap.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * fixmap.h: compile-time virtual memory allocation
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1998 Ingo Molnar
- *
- * Copyright 2008 Freescale Semiconductor Inc.
- *   Port to powerpc added by Kumar Gala
- */
-
-#ifndef _ASM_FIXMAP_H
-#define _ASM_FIXMAP_H
-
-#ifndef __ASSEMBLY__
-#include <linux/kernel.h>
-#include <asm/page.h>
-#ifdef CONFIG_HIGHMEM
-#include <linux/threads.h>
-#include <asm/kmap_types.h>
-#endif
-
-#define FIXADDR_TOP	((unsigned long)(-PAGE_SIZE))
-
-/*
- * Here we define all the compile-time 'special' virtual
- * addresses. The point is to have a constant address at
- * compile time, but to set the physical address only
- * in the boot process. We allocate these special addresses
- * from the end of virtual memory (0xfffff000) backwards.
- * Also this lets us do fail-safe vmalloc(), we
- * can guarantee that these special addresses and
- * vmalloc()-ed addresses never overlap.
- *
- * these 'compile-time allocated' memory buffers are
- * fixed-size 4k pages. (or larger if used with an increment
- * highger than 1) use fixmap_set(idx,phys) to associate
- * physical memory with fixmap indices.
- *
- * TLB entries of such buffers will not be flushed across
- * task switches.
- */
-enum fixed_addresses {
-	FIX_HOLE,
-	/* reserve the top 128K for early debugging purposes */
-	FIX_EARLY_DEBUG_TOP = FIX_HOLE,
-	FIX_EARLY_DEBUG_BASE = FIX_EARLY_DEBUG_TOP+((128*1024)/PAGE_SIZE)-1,
-#ifdef CONFIG_HIGHMEM
-	FIX_KMAP_BEGIN,	/* reserved pte's for temporary kernel mappings */
-	FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1,
-#endif
-	/* FIX_PCIE_MCFG, */
-	__end_of_fixed_addresses
-};
-
-extern void __set_fixmap (enum fixed_addresses idx,
-					phys_addr_t phys, pgprot_t flags);
-
-#define set_fixmap(idx, phys) \
-		__set_fixmap(idx, phys, PAGE_KERNEL)
-/*
- * Some hardware wants to get fixmapped without caching.
- */
-#define set_fixmap_nocache(idx, phys) \
-		__set_fixmap(idx, phys, PAGE_KERNEL_NCG)
-
-#define clear_fixmap(idx) \
-		__set_fixmap(idx, 0, __pgprot(0))
-
-#define __FIXADDR_SIZE	(__end_of_fixed_addresses << PAGE_SHIFT)
-#define FIXADDR_START		(FIXADDR_TOP - __FIXADDR_SIZE)
-
-#define __fix_to_virt(x)	(FIXADDR_TOP - ((x) << PAGE_SHIFT))
-#define __virt_to_fix(x)	((FIXADDR_TOP - ((x)&PAGE_MASK)) >> PAGE_SHIFT)
-
-extern void __this_fixmap_does_not_exist(void);
-
-/*
- * 'index to address' translation. If anyone tries to use the idx
- * directly without tranlation, we catch the bug with a NULL-deference
- * kernel oops. Illegal ranges of incoming indices are caught too.
- */
-static __always_inline unsigned long fix_to_virt(const unsigned int idx)
-{
-	/*
-	 * this branch gets completely eliminated after inlining,
-	 * except when someone tries to use fixaddr indices in an
-	 * illegal way. (such as mixing up address types or using
-	 * out-of-range indices).
-	 *
-	 * If it doesn't get removed, the linker will complain
-	 * loudly with a reasonably clear error message..
-	 */
-	if (idx >= __end_of_fixed_addresses)
-		__this_fixmap_does_not_exist();
-
-        return __fix_to_virt(idx);
-}
-
-static inline unsigned long virt_to_fix(const unsigned long vaddr)
-{
-	BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START);
-	return __virt_to_fix(vaddr);
-}
-
-#endif /* !__ASSEMBLY__ */
-#endif
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/floppy.h b/ANDROID_3.4.5/arch/powerpc/include/asm/floppy.h
deleted file mode 100644
index 936a904a..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/floppy.h
+++ /dev/null
@@ -1,213 +0,0 @@
-/*
- * Architecture specific parts of the Floppy driver
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1995
- */
-#ifndef __ASM_POWERPC_FLOPPY_H
-#define __ASM_POWERPC_FLOPPY_H
-#ifdef __KERNEL__
-
-#include <asm/machdep.h>
-
-#define fd_inb(port)		inb_p(port)
-#define fd_outb(value,port)	outb_p(value,port)
-
-#define fd_enable_dma()         enable_dma(FLOPPY_DMA)
-#define fd_disable_dma()	 fd_ops->_disable_dma(FLOPPY_DMA)
-#define fd_free_dma()           fd_ops->_free_dma(FLOPPY_DMA)
-#define fd_clear_dma_ff()       clear_dma_ff(FLOPPY_DMA)
-#define fd_set_dma_mode(mode)   set_dma_mode(FLOPPY_DMA, mode)
-#define fd_set_dma_count(count) set_dma_count(FLOPPY_DMA, count)
-#define fd_get_dma_residue()    fd_ops->_get_dma_residue(FLOPPY_DMA)
-#define fd_enable_irq()         enable_irq(FLOPPY_IRQ)
-#define fd_disable_irq()        disable_irq(FLOPPY_IRQ)
-#define fd_cacheflush(addr,size) /* nothing */
-#define fd_free_irq()           free_irq(FLOPPY_IRQ, NULL);
-
-#include <linux/pci.h>
-#include <asm/ppc-pci.h>	/* for isa_bridge_pcidev */
-
-#define fd_dma_setup(addr,size,mode,io) fd_ops->_dma_setup(addr,size,mode,io)
-
-static int fd_request_dma(void);
-
-struct fd_dma_ops {
-	void (*_disable_dma)(unsigned int dmanr);
-	void (*_free_dma)(unsigned int dmanr);
-	int (*_get_dma_residue)(unsigned int dummy);
-	int (*_dma_setup)(char *addr, unsigned long size, int mode, int io);
-};
-
-static int virtual_dma_count;
-static int virtual_dma_residue;
-static char *virtual_dma_addr;
-static int virtual_dma_mode;
-static int doing_vdma;
-static struct fd_dma_ops *fd_ops;
-
-static irqreturn_t floppy_hardint(int irq, void *dev_id)
-{
-	unsigned char st;
-	int lcount;
-	char *lptr;
-
-	if (!doing_vdma)
-		return floppy_interrupt(irq, dev_id);
-
-
-	st = 1;
-	for (lcount=virtual_dma_count, lptr=virtual_dma_addr;
-	     lcount; lcount--, lptr++) {
-		st=inb(virtual_dma_port+4) & 0xa0 ;
-		if (st != 0xa0)
-			break;
-		if (virtual_dma_mode)
-			outb_p(*lptr, virtual_dma_port+5);
-		else
-			*lptr = inb_p(virtual_dma_port+5);
-	}
-	virtual_dma_count = lcount;
-	virtual_dma_addr = lptr;
-	st = inb(virtual_dma_port+4);
-
-	if (st == 0x20)
-		return IRQ_HANDLED;
-	if (!(st & 0x20)) {
-		virtual_dma_residue += virtual_dma_count;
-		virtual_dma_count=0;
-		doing_vdma = 0;
-		floppy_interrupt(irq, dev_id);
-		return IRQ_HANDLED;
-	}
-	return IRQ_HANDLED;
-}
-
-static void vdma_disable_dma(unsigned int dummy)
-{
-	doing_vdma = 0;
-	virtual_dma_residue += virtual_dma_count;
-	virtual_dma_count=0;
-}
-
-static void vdma_nop(unsigned int dummy)
-{
-}
-
-
-static int vdma_get_dma_residue(unsigned int dummy)
-{
-	return virtual_dma_count + virtual_dma_residue;
-}
-
-
-static int fd_request_irq(void)
-{
-	if (can_use_virtual_dma)
-		return request_irq(FLOPPY_IRQ, floppy_hardint,
-				   0, "floppy", NULL);
-	else
-		return request_irq(FLOPPY_IRQ, floppy_interrupt,
-				   0, "floppy", NULL);
-}
-
-static int vdma_dma_setup(char *addr, unsigned long size, int mode, int io)
-{
-	doing_vdma = 1;
-	virtual_dma_port = io;
-	virtual_dma_mode = (mode  == DMA_MODE_WRITE);
-	virtual_dma_addr = addr;
-	virtual_dma_count = size;
-	virtual_dma_residue = 0;
-	return 0;
-}
-
-static int hard_dma_setup(char *addr, unsigned long size, int mode, int io)
-{
-	static unsigned long prev_size;
-	static dma_addr_t bus_addr = 0;
-	static char *prev_addr;
-	static int prev_dir;
-	int dir;
-
-	doing_vdma = 0;
-	dir = (mode == DMA_MODE_READ) ? PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE;
-
-	if (bus_addr 
-	    && (addr != prev_addr || size != prev_size || dir != prev_dir)) {
-		/* different from last time -- unmap prev */
-		pci_unmap_single(isa_bridge_pcidev, bus_addr, prev_size, prev_dir);
-		bus_addr = 0;
-	}
-
-	if (!bus_addr)	/* need to map it */
-		bus_addr = pci_map_single(isa_bridge_pcidev, addr, size, dir);
-
-	/* remember this one as prev */
-	prev_addr = addr;
-	prev_size = size;
-	prev_dir = dir;
-
-	fd_clear_dma_ff();
-	fd_cacheflush(addr, size);
-	fd_set_dma_mode(mode);
-	set_dma_addr(FLOPPY_DMA, bus_addr);
-	fd_set_dma_count(size);
-	virtual_dma_port = io;
-	fd_enable_dma();
-
-	return 0;
-}
-
-static struct fd_dma_ops real_dma_ops =
-{
-	._disable_dma = disable_dma,
-	._free_dma = free_dma,
-	._get_dma_residue = get_dma_residue,
-	._dma_setup = hard_dma_setup
-};
-
-static struct fd_dma_ops virt_dma_ops =
-{
-	._disable_dma = vdma_disable_dma,
-	._free_dma = vdma_nop,
-	._get_dma_residue = vdma_get_dma_residue,
-	._dma_setup = vdma_dma_setup
-};
-
-static int fd_request_dma(void)
-{
-	if (can_use_virtual_dma & 1) {
-		fd_ops = &virt_dma_ops;
-		return 0;
-	}
-	else {
-		fd_ops = &real_dma_ops;
-		return request_dma(FLOPPY_DMA, "floppy");
-	}
-}
-
-static int FDC1 = 0x3f0;
-static int FDC2 = -1;
-
-/*
- * Again, the CMOS information not available
- */
-#define FLOPPY0_TYPE 6
-#define FLOPPY1_TYPE 0
-
-#define N_FDC 2			/* Don't change this! */
-#define N_DRIVE 8
-
-/*
- * The PowerPC has no problems with floppy DMA crossing 64k borders.
- */
-#define CROSS_64KB(a,s)	(0)
-
-#define EXTRA_FLOPPY_PARAMS
-
-#endif /* __KERNEL__ */
-#endif /* __ASM_POWERPC_FLOPPY_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/fs_pd.h b/ANDROID_3.4.5/arch/powerpc/include/asm/fs_pd.h
deleted file mode 100644
index 9361cd53..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/fs_pd.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * Platform information definitions.
- *
- * 2006 (c) MontaVista Software, Inc.
- * Vitaly Bordug <vbordug@ru.mvista.com>
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#ifndef FS_PD_H
-#define FS_PD_H
-#include <sysdev/fsl_soc.h>
-#include <asm/time.h>
-
-#ifdef CONFIG_CPM2
-#include <asm/cpm2.h>
-
-#if defined(CONFIG_8260)
-#include <asm/mpc8260.h>
-#endif
-
-#define cpm2_map(member) (&cpm2_immr->member)
-#define cpm2_map_size(member, size) (&cpm2_immr->member)
-#define cpm2_unmap(addr) do {} while(0)
-#endif
-
-#ifdef CONFIG_8xx
-#include <asm/8xx_immap.h>
-#include <asm/mpc8xx.h>
-
-extern immap_t __iomem *mpc8xx_immr;
-
-#define immr_map(member) (&mpc8xx_immr->member)
-#define immr_map_size(member, size) (&mpc8xx_immr->member)
-#define immr_unmap(addr) do {} while (0)
-#endif
-
-static inline int uart_baudrate(void)
-{
-        return get_baudrate();
-}
-
-static inline int uart_clock(void)
-{
-        return ppc_proc_freq;
-}
-
-#endif
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/fsl_85xx_cache_sram.h b/ANDROID_3.4.5/arch/powerpc/include/asm/fsl_85xx_cache_sram.h
deleted file mode 100644
index 2af2bdc3..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/fsl_85xx_cache_sram.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright 2009 Freescale Semiconductor, Inc.
- *
- * Cache SRAM handling for QorIQ platform
- *
- * Author: Vivek Mahajan <vivek.mahajan@freescale.com>
-
- * This file is derived from the original work done
- * by Sylvain Munaut for the Bestcomm SRAM allocator.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ASM_POWERPC_FSL_85XX_CACHE_SRAM_H__
-#define __ASM_POWERPC_FSL_85XX_CACHE_SRAM_H__
-
-#include <asm/rheap.h>
-#include <linux/spinlock.h>
-
-/*
- * Cache-SRAM
- */
-
-struct mpc85xx_cache_sram {
-	phys_addr_t base_phys;
-	void *base_virt;
-	unsigned int size;
-	rh_info_t *rh;
-	spinlock_t lock;
-};
-
-extern void mpc85xx_cache_sram_free(void *ptr);
-extern void *mpc85xx_cache_sram_alloc(unsigned int size,
-				  phys_addr_t *phys, unsigned int align);
-
-#endif /* __AMS_POWERPC_FSL_85XX_CACHE_SRAM_H__ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/fsl_gtm.h b/ANDROID_3.4.5/arch/powerpc/include/asm/fsl_gtm.h
deleted file mode 100644
index 8e8c9b50..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/fsl_gtm.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Freescale General-purpose Timers Module
- *
- * Copyright (c) Freescale Semicondutor, Inc. 2006.
- *               Shlomi Gridish <gridish@freescale.com>
- *               Jerry Huang <Chang-Ming.Huang@freescale.com>
- * Copyright (c) MontaVista Software, Inc. 2008.
- *               Anton Vorontsov <avorontsov@ru.mvista.com>
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-#ifndef __ASM_FSL_GTM_H
-#define __ASM_FSL_GTM_H
-
-#include <linux/types.h>
-
-struct gtm;
-
-struct gtm_timer {
-	unsigned int irq;
-
-	struct gtm *gtm;
-	bool requested;
-	u8 __iomem *gtcfr;
-	__be16 __iomem *gtmdr;
-	__be16 __iomem *gtpsr;
-	__be16 __iomem *gtcnr;
-	__be16 __iomem *gtrfr;
-	__be16 __iomem *gtevr;
-};
-
-extern struct gtm_timer *gtm_get_timer16(void);
-extern struct gtm_timer *gtm_get_specific_timer16(struct gtm *gtm,
-						  unsigned int timer);
-extern void gtm_put_timer16(struct gtm_timer *tmr);
-extern int gtm_set_timer16(struct gtm_timer *tmr, unsigned long usec,
-			     bool reload);
-extern int gtm_set_exact_timer16(struct gtm_timer *tmr, u16 usec,
-				 bool reload);
-extern void gtm_stop_timer16(struct gtm_timer *tmr);
-extern void gtm_ack_timer16(struct gtm_timer *tmr, u16 events);
-
-#endif /* __ASM_FSL_GTM_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/fsl_guts.h b/ANDROID_3.4.5/arch/powerpc/include/asm/fsl_guts.h
deleted file mode 100644
index aa4c4885..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/fsl_guts.h
+++ /dev/null
@@ -1,185 +0,0 @@
-/**
- * Freecale 85xx and 86xx Global Utilties register set
- *
- * Authors: Jeff Brown
- *          Timur Tabi <timur@freescale.com>
- *
- * Copyright 2004,2007,2012 Freescale Semiconductor, Inc
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-#ifndef __ASM_POWERPC_FSL_GUTS_H__
-#define __ASM_POWERPC_FSL_GUTS_H__
-#ifdef __KERNEL__
-
-/**
- * Global Utility Registers.
- *
- * Not all registers defined in this structure are available on all chips, so
- * you are expected to know whether a given register actually exists on your
- * chip before you access it.
- *
- * Also, some registers are similar on different chips but have slightly
- * different names.  In these cases, one name is chosen to avoid extraneous
- * #ifdefs.
- */
-struct ccsr_guts {
-	__be32	porpllsr;	/* 0x.0000 - POR PLL Ratio Status Register */
-	__be32	porbmsr;	/* 0x.0004 - POR Boot Mode Status Register */
-	__be32	porimpscr;	/* 0x.0008 - POR I/O Impedance Status and Control Register */
-	__be32	pordevsr;	/* 0x.000c - POR I/O Device Status Register */
-	__be32	pordbgmsr;	/* 0x.0010 - POR Debug Mode Status Register */
-	__be32	pordevsr2;	/* 0x.0014 - POR device status register 2 */
-	u8	res018[0x20 - 0x18];
-	__be32	porcir;		/* 0x.0020 - POR Configuration Information Register */
-	u8	res024[0x30 - 0x24];
-	__be32	gpiocr;		/* 0x.0030 - GPIO Control Register */
-	u8	res034[0x40 - 0x34];
-	__be32	gpoutdr;	/* 0x.0040 - General-Purpose Output Data Register */
-	u8	res044[0x50 - 0x44];
-	__be32	gpindr;		/* 0x.0050 - General-Purpose Input Data Register */
-	u8	res054[0x60 - 0x54];
-	__be32	pmuxcr;		/* 0x.0060 - Alternate Function Signal Multiplex Control */
-        __be32  pmuxcr2;	/* 0x.0064 - Alternate function signal multiplex control 2 */
-        __be32  dmuxcr;		/* 0x.0068 - DMA Mux Control Register */
-        u8	res06c[0x70 - 0x6c];
-	__be32	devdisr;	/* 0x.0070 - Device Disable Control */
-	__be32	devdisr2;	/* 0x.0074 - Device Disable Control 2 */
-	u8	res078[0x7c - 0x78];
-	__be32  pmjcr;		/* 0x.007c - 4 Power Management Jog Control Register */
-	__be32	powmgtcsr;	/* 0x.0080 - Power Management Status and Control Register */
-	__be32  pmrccr;		/* 0x.0084 - Power Management Reset Counter Configuration Register */
-	__be32  pmpdccr;	/* 0x.0088 - Power Management Power Down Counter Configuration Register */
-	__be32  pmcdr;		/* 0x.008c - 4Power management clock disable register */
-	__be32	mcpsumr;	/* 0x.0090 - Machine Check Summary Register */
-	__be32	rstrscr;	/* 0x.0094 - Reset Request Status and Control Register */
-	__be32  ectrstcr;	/* 0x.0098 - Exception reset control register */
-	__be32  autorstsr;	/* 0x.009c - Automatic reset status register */
-	__be32	pvr;		/* 0x.00a0 - Processor Version Register */
-	__be32	svr;		/* 0x.00a4 - System Version Register */
-	u8	res0a8[0xb0 - 0xa8];
-	__be32	rstcr;		/* 0x.00b0 - Reset Control Register */
-	u8	res0b4[0xc0 - 0xb4];
-	__be32  iovselsr;	/* 0x.00c0 - I/O voltage select status register
-					     Called 'elbcvselcr' on 86xx SOCs */
-	u8	res0c4[0x224 - 0xc4];
-	__be32  iodelay1;	/* 0x.0224 - IO delay control register 1 */
-	__be32  iodelay2;	/* 0x.0228 - IO delay control register 2 */
-	u8	res22c[0x800 - 0x22c];
-	__be32	clkdvdr;	/* 0x.0800 - Clock Divide Register */
-	u8	res804[0x900 - 0x804];
-	__be32	ircr;		/* 0x.0900 - Infrared Control Register */
-	u8	res904[0x908 - 0x904];
-	__be32	dmacr;		/* 0x.0908 - DMA Control Register */
-	u8	res90c[0x914 - 0x90c];
-	__be32	elbccr;		/* 0x.0914 - eLBC Control Register */
-	u8	res918[0xb20 - 0x918];
-	__be32	ddr1clkdr;	/* 0x.0b20 - DDR1 Clock Disable Register */
-	__be32	ddr2clkdr;	/* 0x.0b24 - DDR2 Clock Disable Register */
-	__be32	ddrclkdr;	/* 0x.0b28 - DDR Clock Disable Register */
-	u8	resb2c[0xe00 - 0xb2c];
-	__be32	clkocr;		/* 0x.0e00 - Clock Out Select Register */
-	u8	rese04[0xe10 - 0xe04];
-	__be32	ddrdllcr;	/* 0x.0e10 - DDR DLL Control Register */
-	u8	rese14[0xe20 - 0xe14];
-	__be32	lbcdllcr;	/* 0x.0e20 - LBC DLL Control Register */
-	__be32  cpfor;		/* 0x.0e24 - L2 charge pump fuse override register */
-	u8	rese28[0xf04 - 0xe28];
-	__be32	srds1cr0;	/* 0x.0f04 - SerDes1 Control Register 0 */
-	__be32	srds1cr1;	/* 0x.0f08 - SerDes1 Control Register 0 */
-	u8	resf0c[0xf2c - 0xf0c];
-	__be32  itcr;		/* 0x.0f2c - Internal transaction control register */
-	u8	resf30[0xf40 - 0xf30];
-	__be32	srds2cr0;	/* 0x.0f40 - SerDes2 Control Register 0 */
-	__be32	srds2cr1;	/* 0x.0f44 - SerDes2 Control Register 0 */
-} __attribute__ ((packed));
-
-
-/* Alternate function signal multiplex control */
-#define MPC85xx_PMUXCR_QE(x) (0x8000 >> (x))
-
-#ifdef CONFIG_PPC_86xx
-
-#define CCSR_GUTS_DMACR_DEV_SSI	0	/* DMA controller/channel set to SSI */
-#define CCSR_GUTS_DMACR_DEV_IR	1	/* DMA controller/channel set to IR */
-
-/*
- * Set the DMACR register in the GUTS
- *
- * The DMACR register determines the source of initiated transfers for each
- * channel on each DMA controller.  Rather than have a bunch of repetitive
- * macros for the bit patterns, we just have a function that calculates
- * them.
- *
- * guts: Pointer to GUTS structure
- * co: The DMA controller (0 or 1)
- * ch: The channel on the DMA controller (0, 1, 2, or 3)
- * device: The device to set as the source (CCSR_GUTS_DMACR_DEV_xx)
- */
-static inline void guts_set_dmacr(struct ccsr_guts __iomem *guts,
-	unsigned int co, unsigned int ch, unsigned int device)
-{
-	unsigned int shift = 16 + (8 * (1 - co) + 2 * (3 - ch));
-
-	clrsetbits_be32(&guts->dmacr, 3 << shift, device << shift);
-}
-
-#define CCSR_GUTS_PMUXCR_LDPSEL		0x00010000
-#define CCSR_GUTS_PMUXCR_SSI1_MASK	0x0000C000	/* Bitmask for SSI1 */
-#define CCSR_GUTS_PMUXCR_SSI1_LA	0x00000000	/* Latched address */
-#define CCSR_GUTS_PMUXCR_SSI1_HI	0x00004000	/* High impedance */
-#define CCSR_GUTS_PMUXCR_SSI1_SSI	0x00008000	/* Used for SSI1 */
-#define CCSR_GUTS_PMUXCR_SSI2_MASK	0x00003000	/* Bitmask for SSI2 */
-#define CCSR_GUTS_PMUXCR_SSI2_LA	0x00000000	/* Latched address */
-#define CCSR_GUTS_PMUXCR_SSI2_HI	0x00001000	/* High impedance */
-#define CCSR_GUTS_PMUXCR_SSI2_SSI	0x00002000	/* Used for SSI2 */
-#define CCSR_GUTS_PMUXCR_LA_22_25_LA	0x00000000	/* Latched Address */
-#define CCSR_GUTS_PMUXCR_LA_22_25_HI	0x00000400	/* High impedance */
-#define CCSR_GUTS_PMUXCR_DBGDRV		0x00000200	/* Signals not driven */
-#define CCSR_GUTS_PMUXCR_DMA2_0		0x00000008
-#define CCSR_GUTS_PMUXCR_DMA2_3		0x00000004
-#define CCSR_GUTS_PMUXCR_DMA1_0		0x00000002
-#define CCSR_GUTS_PMUXCR_DMA1_3		0x00000001
-
-/*
- * Set the DMA external control bits in the GUTS
- *
- * The DMA external control bits in the PMUXCR are only meaningful for
- * channels 0 and 3.  Any other channels are ignored.
- *
- * guts: Pointer to GUTS structure
- * co: The DMA controller (0 or 1)
- * ch: The channel on the DMA controller (0, 1, 2, or 3)
- * value: the new value for the bit (0 or 1)
- */
-static inline void guts_set_pmuxcr_dma(struct ccsr_guts __iomem *guts,
-	unsigned int co, unsigned int ch, unsigned int value)
-{
-	if ((ch == 0) || (ch == 3)) {
-		unsigned int shift = 2 * (co + 1) - (ch & 1) - 1;
-
-		clrsetbits_be32(&guts->pmuxcr, 1 << shift, value << shift);
-	}
-}
-
-#define CCSR_GUTS_CLKDVDR_PXCKEN	0x80000000
-#define CCSR_GUTS_CLKDVDR_SSICKEN	0x20000000
-#define CCSR_GUTS_CLKDVDR_PXCKINV	0x10000000
-#define CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT 25
-#define CCSR_GUTS_CLKDVDR_PXCKDLY_MASK	0x06000000
-#define CCSR_GUTS_CLKDVDR_PXCKDLY(x) \
-	(((x) & 3) << CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT)
-#define CCSR_GUTS_CLKDVDR_PXCLK_SHIFT	16
-#define CCSR_GUTS_CLKDVDR_PXCLK_MASK	0x001F0000
-#define CCSR_GUTS_CLKDVDR_PXCLK(x) (((x) & 31) << CCSR_GUTS_CLKDVDR_PXCLK_SHIFT)
-#define CCSR_GUTS_CLKDVDR_SSICLK_MASK	0x000000FF
-#define CCSR_GUTS_CLKDVDR_SSICLK(x) ((x) & CCSR_GUTS_CLKDVDR_SSICLK_MASK)
-
-#endif
-
-#endif
-#endif
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/fsl_hcalls.h b/ANDROID_3.4.5/arch/powerpc/include/asm/fsl_hcalls.h
deleted file mode 100644
index 922d9b5f..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/fsl_hcalls.h
+++ /dev/null
@@ -1,655 +0,0 @@
-/*
- * Freescale hypervisor call interface
- *
- * Copyright 2008-2010 Freescale Semiconductor, Inc.
- *
- * Author: Timur Tabi <timur@freescale.com>
- *
- * This file is provided under a dual BSD/GPL license.  When using or
- * redistributing this file, you may do so under either license.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Freescale Semiconductor nor the
- *       names of its contributors may be used to endorse or promote products
- *       derived from this software without specific prior written permission.
- *
- *
- * ALTERNATIVELY, this software may be distributed under the terms of the
- * GNU General Public License ("GPL") as published by the Free Software
- * Foundation, either version 2 of that License or (at your option) any
- * later version.
- *
- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _FSL_HCALLS_H
-#define _FSL_HCALLS_H
-
-#include <linux/types.h>
-#include <linux/errno.h>
-#include <asm/byteorder.h>
-#include <asm/epapr_hcalls.h>
-
-#define FH_API_VERSION			1
-
-#define FH_ERR_GET_INFO			1
-#define FH_PARTITION_GET_DTPROP		2
-#define FH_PARTITION_SET_DTPROP		3
-#define FH_PARTITION_RESTART		4
-#define FH_PARTITION_GET_STATUS		5
-#define FH_PARTITION_START		6
-#define FH_PARTITION_STOP		7
-#define FH_PARTITION_MEMCPY		8
-#define FH_DMA_ENABLE			9
-#define FH_DMA_DISABLE			10
-#define FH_SEND_NMI			11
-#define FH_VMPIC_GET_MSIR		12
-#define FH_SYSTEM_RESET			13
-#define FH_GET_CORE_STATE		14
-#define FH_ENTER_NAP			15
-#define FH_EXIT_NAP			16
-#define FH_CLAIM_DEVICE			17
-#define FH_PARTITION_STOP_DMA		18
-
-/* vendor ID: Freescale Semiconductor */
-#define FH_HCALL_TOKEN(num)		_EV_HCALL_TOKEN(EV_FSL_VENDOR_ID, num)
-
-/*
- * We use "uintptr_t" to define a register because it's guaranteed to be a
- * 32-bit integer on a 32-bit platform, and a 64-bit integer on a 64-bit
- * platform.
- *
- * All registers are either input/output or output only.  Registers that are
- * initialized before making the hypercall are input/output.  All
- * input/output registers are represented with "+r".  Output-only registers
- * are represented with "=r".  Do not specify any unused registers.  The
- * clobber list will tell the compiler that the hypercall modifies those
- * registers, which is good enough.
- */
-
-/**
- * fh_send_nmi - send NMI to virtual cpu(s).
- * @vcpu_mask: send NMI to virtual cpu(s) specified by this mask.
- *
- * Returns 0 for success, or EINVAL for invalid vcpu_mask.
- */
-static inline unsigned int fh_send_nmi(unsigned int vcpu_mask)
-{
-	register uintptr_t r11 __asm__("r11");
-	register uintptr_t r3 __asm__("r3");
-
-	r11 = FH_HCALL_TOKEN(FH_SEND_NMI);
-	r3 = vcpu_mask;
-
-	__asm__ __volatile__ ("sc 1"
-		: "+r" (r11), "+r" (r3)
-		: : EV_HCALL_CLOBBERS1
-	);
-
-	return r3;
-}
-
-/* Arbitrary limits to avoid excessive memory allocation in hypervisor */
-#define FH_DTPROP_MAX_PATHLEN 4096
-#define FH_DTPROP_MAX_PROPLEN 32768
-
-/**
- * fh_partiton_get_dtprop - get a property from a guest device tree.
- * @handle: handle of partition whose device tree is to be accessed
- * @dtpath_addr: physical address of device tree path to access
- * @propname_addr: physical address of name of property
- * @propvalue_addr: physical address of property value buffer
- * @propvalue_len: length of buffer on entry, length of property on return
- *
- * Returns zero on success, non-zero on error.
- */
-static inline unsigned int fh_partition_get_dtprop(int handle,
-						   uint64_t dtpath_addr,
-						   uint64_t propname_addr,
-						   uint64_t propvalue_addr,
-						   uint32_t *propvalue_len)
-{
-	register uintptr_t r11 __asm__("r11");
-	register uintptr_t r3 __asm__("r3");
-	register uintptr_t r4 __asm__("r4");
-	register uintptr_t r5 __asm__("r5");
-	register uintptr_t r6 __asm__("r6");
-	register uintptr_t r7 __asm__("r7");
-	register uintptr_t r8 __asm__("r8");
-	register uintptr_t r9 __asm__("r9");
-	register uintptr_t r10 __asm__("r10");
-
-	r11 = FH_HCALL_TOKEN(FH_PARTITION_GET_DTPROP);
-	r3 = handle;
-
-#ifdef CONFIG_PHYS_64BIT
-	r4 = dtpath_addr >> 32;
-	r6 = propname_addr >> 32;
-	r8 = propvalue_addr >> 32;
-#else
-	r4 = 0;
-	r6 = 0;
-	r8 = 0;
-#endif
-	r5 = (uint32_t)dtpath_addr;
-	r7 = (uint32_t)propname_addr;
-	r9 = (uint32_t)propvalue_addr;
-	r10 = *propvalue_len;
-
-	__asm__ __volatile__ ("sc 1"
-		: "+r" (r11),
-		  "+r" (r3), "+r" (r4), "+r" (r5), "+r" (r6), "+r" (r7),
-		  "+r" (r8), "+r" (r9), "+r" (r10)
-		: : EV_HCALL_CLOBBERS8
-	);
-
-	*propvalue_len = r4;
-	return r3;
-}
-
-/**
- * Set a property in a guest device tree.
- * @handle: handle of partition whose device tree is to be accessed
- * @dtpath_addr: physical address of device tree path to access
- * @propname_addr: physical address of name of property
- * @propvalue_addr: physical address of property value
- * @propvalue_len: length of property
- *
- * Returns zero on success, non-zero on error.
- */
-static inline unsigned int fh_partition_set_dtprop(int handle,
-						   uint64_t dtpath_addr,
-						   uint64_t propname_addr,
-						   uint64_t propvalue_addr,
-						   uint32_t propvalue_len)
-{
-	register uintptr_t r11 __asm__("r11");
-	register uintptr_t r3 __asm__("r3");
-	register uintptr_t r4 __asm__("r4");
-	register uintptr_t r6 __asm__("r6");
-	register uintptr_t r8 __asm__("r8");
-	register uintptr_t r5 __asm__("r5");
-	register uintptr_t r7 __asm__("r7");
-	register uintptr_t r9 __asm__("r9");
-	register uintptr_t r10 __asm__("r10");
-
-	r11 = FH_HCALL_TOKEN(FH_PARTITION_SET_DTPROP);
-	r3 = handle;
-
-#ifdef CONFIG_PHYS_64BIT
-	r4 = dtpath_addr >> 32;
-	r6 = propname_addr >> 32;
-	r8 = propvalue_addr >> 32;
-#else
-	r4 = 0;
-	r6 = 0;
-	r8 = 0;
-#endif
-	r5 = (uint32_t)dtpath_addr;
-	r7 = (uint32_t)propname_addr;
-	r9 = (uint32_t)propvalue_addr;
-	r10 = propvalue_len;
-
-	__asm__ __volatile__ ("sc 1"
-		: "+r" (r11),
-		  "+r" (r3), "+r" (r4), "+r" (r5), "+r" (r6), "+r" (r7),
-		  "+r" (r8), "+r" (r9), "+r" (r10)
-		: : EV_HCALL_CLOBBERS8
-	);
-
-	return r3;
-}
-
-/**
- * fh_partition_restart - reboot the current partition
- * @partition: partition ID
- *
- * Returns an error code if reboot failed.  Does not return if it succeeds.
- */
-static inline unsigned int fh_partition_restart(unsigned int partition)
-{
-	register uintptr_t r11 __asm__("r11");
-	register uintptr_t r3 __asm__("r3");
-
-	r11 = FH_HCALL_TOKEN(FH_PARTITION_RESTART);
-	r3 = partition;
-
-	__asm__ __volatile__ ("sc 1"
-		: "+r" (r11), "+r" (r3)
-		: : EV_HCALL_CLOBBERS1
-	);
-
-	return r3;
-}
-
-#define FH_PARTITION_STOPPED	0
-#define FH_PARTITION_RUNNING	1
-#define FH_PARTITION_STARTING	2
-#define FH_PARTITION_STOPPING	3
-#define FH_PARTITION_PAUSING	4
-#define FH_PARTITION_PAUSED	5
-#define FH_PARTITION_RESUMING	6
-
-/**
- * fh_partition_get_status - gets the status of a partition
- * @partition: partition ID
- * @status: returned status code
- *
- * Returns 0 for success, or an error code.
- */
-static inline unsigned int fh_partition_get_status(unsigned int partition,
-	unsigned int *status)
-{
-	register uintptr_t r11 __asm__("r11");
-	register uintptr_t r3 __asm__("r3");
-	register uintptr_t r4 __asm__("r4");
-
-	r11 = FH_HCALL_TOKEN(FH_PARTITION_GET_STATUS);
-	r3 = partition;
-
-	__asm__ __volatile__ ("sc 1"
-		: "+r" (r11), "+r" (r3), "=r" (r4)
-		: : EV_HCALL_CLOBBERS2
-	);
-
-	*status = r4;
-
-	return r3;
-}
-
-/**
- * fh_partition_start - boots and starts execution of the specified partition
- * @partition: partition ID
- * @entry_point: guest physical address to start execution
- *
- * The hypervisor creates a 1-to-1 virtual/physical IMA mapping, so at boot
- * time, guest physical address are the same as guest virtual addresses.
- *
- * Returns 0 for success, or an error code.
- */
-static inline unsigned int fh_partition_start(unsigned int partition,
-	uint32_t entry_point, int load)
-{
-	register uintptr_t r11 __asm__("r11");
-	register uintptr_t r3 __asm__("r3");
-	register uintptr_t r4 __asm__("r4");
-	register uintptr_t r5 __asm__("r5");
-
-	r11 = FH_HCALL_TOKEN(FH_PARTITION_START);
-	r3 = partition;
-	r4 = entry_point;
-	r5 = load;
-
-	__asm__ __volatile__ ("sc 1"
-		: "+r" (r11), "+r" (r3), "+r" (r4), "+r" (r5)
-		: : EV_HCALL_CLOBBERS3
-	);
-
-	return r3;
-}
-
-/**
- * fh_partition_stop - stops another partition
- * @partition: partition ID
- *
- * Returns 0 for success, or an error code.
- */
-static inline unsigned int fh_partition_stop(unsigned int partition)
-{
-	register uintptr_t r11 __asm__("r11");
-	register uintptr_t r3 __asm__("r3");
-
-	r11 = FH_HCALL_TOKEN(FH_PARTITION_STOP);
-	r3 = partition;
-
-	__asm__ __volatile__ ("sc 1"
-		: "+r" (r11), "+r" (r3)
-		: : EV_HCALL_CLOBBERS1
-	);
-
-	return r3;
-}
-
-/**
- * struct fh_sg_list: definition of the fh_partition_memcpy S/G list
- * @source: guest physical address to copy from
- * @target: guest physical address to copy to
- * @size: number of bytes to copy
- * @reserved: reserved, must be zero
- *
- * The scatter/gather list for fh_partition_memcpy() is an array of these
- * structures.  The array must be guest physically contiguous.
- *
- * This structure must be aligned on 32-byte boundary, so that no single
- * strucuture can span two pages.
- */
-struct fh_sg_list {
-	uint64_t source;   /**< guest physical address to copy from */
-	uint64_t target;   /**< guest physical address to copy to */
-	uint64_t size;     /**< number of bytes to copy */
-	uint64_t reserved; /**< reserved, must be zero */
-} __attribute__ ((aligned(32)));
-
-/**
- * fh_partition_memcpy - copies data from one guest to another
- * @source: the ID of the partition to copy from
- * @target: the ID of the partition to copy to
- * @sg_list: guest physical address of an array of &fh_sg_list structures
- * @count: the number of entries in @sg_list
- *
- * Returns 0 for success, or an error code.
- */
-static inline unsigned int fh_partition_memcpy(unsigned int source,
-	unsigned int target, phys_addr_t sg_list, unsigned int count)
-{
-	register uintptr_t r11 __asm__("r11");
-	register uintptr_t r3 __asm__("r3");
-	register uintptr_t r4 __asm__("r4");
-	register uintptr_t r5 __asm__("r5");
-	register uintptr_t r6 __asm__("r6");
-	register uintptr_t r7 __asm__("r7");
-
-	r11 = FH_HCALL_TOKEN(FH_PARTITION_MEMCPY);
-	r3 = source;
-	r4 = target;
-	r5 = (uint32_t) sg_list;
-
-#ifdef CONFIG_PHYS_64BIT
-	r6 = sg_list >> 32;
-#else
-	r6 = 0;
-#endif
-	r7 = count;
-
-	__asm__ __volatile__ ("sc 1"
-		: "+r" (r11),
-		  "+r" (r3), "+r" (r4), "+r" (r5), "+r" (r6), "+r" (r7)
-		: : EV_HCALL_CLOBBERS5
-	);
-
-	return r3;
-}
-
-/**
- * fh_dma_enable - enable DMA for the specified device
- * @liodn: the LIODN of the I/O device for which to enable DMA
- *
- * Returns 0 for success, or an error code.
- */
-static inline unsigned int fh_dma_enable(unsigned int liodn)
-{
-	register uintptr_t r11 __asm__("r11");
-	register uintptr_t r3 __asm__("r3");
-
-	r11 = FH_HCALL_TOKEN(FH_DMA_ENABLE);
-	r3 = liodn;
-
-	__asm__ __volatile__ ("sc 1"
-		: "+r" (r11), "+r" (r3)
-		: : EV_HCALL_CLOBBERS1
-	);
-
-	return r3;
-}
-
-/**
- * fh_dma_disable - disable DMA for the specified device
- * @liodn: the LIODN of the I/O device for which to disable DMA
- *
- * Returns 0 for success, or an error code.
- */
-static inline unsigned int fh_dma_disable(unsigned int liodn)
-{
-	register uintptr_t r11 __asm__("r11");
-	register uintptr_t r3 __asm__("r3");
-
-	r11 = FH_HCALL_TOKEN(FH_DMA_DISABLE);
-	r3 = liodn;
-
-	__asm__ __volatile__ ("sc 1"
-		: "+r" (r11), "+r" (r3)
-		: : EV_HCALL_CLOBBERS1
-	);
-
-	return r3;
-}
-
-
-/**
- * fh_vmpic_get_msir - returns the MPIC-MSI register value
- * @interrupt: the interrupt number
- * @msir_val: returned MPIC-MSI register value
- *
- * Returns 0 for success, or an error code.
- */
-static inline unsigned int fh_vmpic_get_msir(unsigned int interrupt,
-	unsigned int *msir_val)
-{
-	register uintptr_t r11 __asm__("r11");
-	register uintptr_t r3 __asm__("r3");
-	register uintptr_t r4 __asm__("r4");
-
-	r11 = FH_HCALL_TOKEN(FH_VMPIC_GET_MSIR);
-	r3 = interrupt;
-
-	__asm__ __volatile__ ("sc 1"
-		: "+r" (r11), "+r" (r3), "=r" (r4)
-		: : EV_HCALL_CLOBBERS2
-	);
-
-	*msir_val = r4;
-
-	return r3;
-}
-
-/**
- * fh_system_reset - reset the system
- *
- * Returns 0 for success, or an error code.
- */
-static inline unsigned int fh_system_reset(void)
-{
-	register uintptr_t r11 __asm__("r11");
-	register uintptr_t r3 __asm__("r3");
-
-	r11 = FH_HCALL_TOKEN(FH_SYSTEM_RESET);
-
-	__asm__ __volatile__ ("sc 1"
-		: "+r" (r11), "=r" (r3)
-		: : EV_HCALL_CLOBBERS1
-	);
-
-	return r3;
-}
-
-
-/**
- * fh_err_get_info - get platform error information
- * @queue id:
- * 0 for guest error event queue
- * 1 for global error event queue
- *
- * @pointer to store the platform error data:
- * platform error data is returned in registers r4 - r11
- *
- * Returns 0 for success, or an error code.
- */
-static inline unsigned int fh_err_get_info(int queue, uint32_t *bufsize,
-	uint32_t addr_hi, uint32_t addr_lo, int peek)
-{
-	register uintptr_t r11 __asm__("r11");
-	register uintptr_t r3 __asm__("r3");
-	register uintptr_t r4 __asm__("r4");
-	register uintptr_t r5 __asm__("r5");
-	register uintptr_t r6 __asm__("r6");
-	register uintptr_t r7 __asm__("r7");
-
-	r11 = FH_HCALL_TOKEN(FH_ERR_GET_INFO);
-	r3 = queue;
-	r4 = *bufsize;
-	r5 = addr_hi;
-	r6 = addr_lo;
-	r7 = peek;
-
-	__asm__ __volatile__ ("sc 1"
-		: "+r" (r11), "+r" (r3), "+r" (r4), "+r" (r5), "+r" (r6),
-		  "+r" (r7)
-		: : EV_HCALL_CLOBBERS5
-	);
-
-	*bufsize = r4;
-
-	return r3;
-}
-
-
-#define FH_VCPU_RUN	0
-#define FH_VCPU_IDLE	1
-#define FH_VCPU_NAP	2
-
-/**
- * fh_get_core_state - get the state of a vcpu
- *
- * @handle: handle of partition containing the vcpu
- * @vcpu: vcpu number within the partition
- * @state:the current state of the vcpu, see FH_VCPU_*
- *
- * Returns 0 for success, or an error code.
- */
-static inline unsigned int fh_get_core_state(unsigned int handle,
-	unsigned int vcpu, unsigned int *state)
-{
-	register uintptr_t r11 __asm__("r11");
-	register uintptr_t r3 __asm__("r3");
-	register uintptr_t r4 __asm__("r4");
-
-	r11 = FH_HCALL_TOKEN(FH_GET_CORE_STATE);
-	r3 = handle;
-	r4 = vcpu;
-
-	__asm__ __volatile__ ("sc 1"
-		: "+r" (r11), "+r" (r3), "+r" (r4)
-		: : EV_HCALL_CLOBBERS2
-	);
-
-	*state = r4;
-	return r3;
-}
-
-/**
- * fh_enter_nap - enter nap on a vcpu
- *
- * Note that though the API supports entering nap on a vcpu other
- * than the caller, this may not be implmented and may return EINVAL.
- *
- * @handle: handle of partition containing the vcpu
- * @vcpu: vcpu number within the partition
- *
- * Returns 0 for success, or an error code.
- */
-static inline unsigned int fh_enter_nap(unsigned int handle, unsigned int vcpu)
-{
-	register uintptr_t r11 __asm__("r11");
-	register uintptr_t r3 __asm__("r3");
-	register uintptr_t r4 __asm__("r4");
-
-	r11 = FH_HCALL_TOKEN(FH_ENTER_NAP);
-	r3 = handle;
-	r4 = vcpu;
-
-	__asm__ __volatile__ ("sc 1"
-		: "+r" (r11), "+r" (r3), "+r" (r4)
-		: : EV_HCALL_CLOBBERS2
-	);
-
-	return r3;
-}
-
-/**
- * fh_exit_nap - exit nap on a vcpu
- * @handle: handle of partition containing the vcpu
- * @vcpu: vcpu number within the partition
- *
- * Returns 0 for success, or an error code.
- */
-static inline unsigned int fh_exit_nap(unsigned int handle, unsigned int vcpu)
-{
-	register uintptr_t r11 __asm__("r11");
-	register uintptr_t r3 __asm__("r3");
-	register uintptr_t r4 __asm__("r4");
-
-	r11 = FH_HCALL_TOKEN(FH_EXIT_NAP);
-	r3 = handle;
-	r4 = vcpu;
-
-	__asm__ __volatile__ ("sc 1"
-		: "+r" (r11), "+r" (r3), "+r" (r4)
-		: : EV_HCALL_CLOBBERS2
-	);
-
-	return r3;
-}
-/**
- * fh_claim_device - claim a "claimable" shared device
- * @handle: fsl,hv-device-handle of node to claim
- *
- * Returns 0 for success, or an error code.
- */
-static inline unsigned int fh_claim_device(unsigned int handle)
-{
-	register uintptr_t r11 __asm__("r11");
-	register uintptr_t r3 __asm__("r3");
-
-	r11 = FH_HCALL_TOKEN(FH_CLAIM_DEVICE);
-	r3 = handle;
-
-	__asm__ __volatile__ ("sc 1"
-		: "+r" (r11), "+r" (r3)
-		: : EV_HCALL_CLOBBERS1
-	);
-
-	return r3;
-}
-
-/**
- * Run deferred DMA disabling on a partition's private devices
- *
- * This applies to devices which a partition owns either privately,
- * or which are claimable and still actively owned by that partition,
- * and which do not have the no-dma-disable property.
- *
- * @handle: partition (must be stopped) whose DMA is to be disabled
- *
- * Returns 0 for success, or an error code.
- */
-static inline unsigned int fh_partition_stop_dma(unsigned int handle)
-{
-	register uintptr_t r11 __asm__("r11");
-	register uintptr_t r3 __asm__("r3");
-
-	r11 = FH_HCALL_TOKEN(FH_PARTITION_STOP_DMA);
-	r3 = handle;
-
-	__asm__ __volatile__ ("sc 1"
-		: "+r" (r11), "+r" (r3)
-		: : EV_HCALL_CLOBBERS1
-	);
-
-	return r3;
-}
-#endif
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/fsl_ifc.h b/ANDROID_3.4.5/arch/powerpc/include/asm/fsl_ifc.h
deleted file mode 100644
index b9550129..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/fsl_ifc.h
+++ /dev/null
@@ -1,834 +0,0 @@
-/* Freescale Integrated Flash Controller
- *
- * Copyright 2011 Freescale Semiconductor, Inc
- *
- * Author: Dipen Dudhat <dipen.dudhat@freescale.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#ifndef __ASM_FSL_IFC_H
-#define __ASM_FSL_IFC_H
-
-#include <linux/compiler.h>
-#include <linux/types.h>
-#include <linux/io.h>
-
-#include <linux/of_platform.h>
-#include <linux/interrupt.h>
-
-#define FSL_IFC_BANK_COUNT 4
-
-/*
- * CSPR - Chip Select Property Register
- */
-#define CSPR_BA				0xFFFF0000
-#define CSPR_BA_SHIFT			16
-#define CSPR_PORT_SIZE			0x00000180
-#define CSPR_PORT_SIZE_SHIFT		7
-/* Port Size 8 bit */
-#define CSPR_PORT_SIZE_8		0x00000080
-/* Port Size 16 bit */
-#define CSPR_PORT_SIZE_16		0x00000100
-/* Port Size 32 bit */
-#define CSPR_PORT_SIZE_32		0x00000180
-/* Write Protect */
-#define CSPR_WP				0x00000040
-#define CSPR_WP_SHIFT			6
-/* Machine Select */
-#define CSPR_MSEL			0x00000006
-#define CSPR_MSEL_SHIFT			1
-/* NOR */
-#define CSPR_MSEL_NOR			0x00000000
-/* NAND */
-#define CSPR_MSEL_NAND			0x00000002
-/* GPCM */
-#define CSPR_MSEL_GPCM			0x00000004
-/* Bank Valid */
-#define CSPR_V				0x00000001
-#define CSPR_V_SHIFT			0
-
-/*
- * Address Mask Register
- */
-#define IFC_AMASK_MASK			0xFFFF0000
-#define IFC_AMASK_SHIFT			16
-#define IFC_AMASK(n)			(IFC_AMASK_MASK << \
-					(__ilog2(n) - IFC_AMASK_SHIFT))
-
-/*
- * Chip Select Option Register IFC_NAND Machine
- */
-/* Enable ECC Encoder */
-#define CSOR_NAND_ECC_ENC_EN		0x80000000
-#define CSOR_NAND_ECC_MODE_MASK		0x30000000
-/* 4 bit correction per 520 Byte sector */
-#define CSOR_NAND_ECC_MODE_4		0x00000000
-/* 8 bit correction per 528 Byte sector */
-#define CSOR_NAND_ECC_MODE_8		0x10000000
-/* Enable ECC Decoder */
-#define CSOR_NAND_ECC_DEC_EN		0x04000000
-/* Row Address Length */
-#define CSOR_NAND_RAL_MASK		0x01800000
-#define CSOR_NAND_RAL_SHIFT		20
-#define CSOR_NAND_RAL_1			0x00000000
-#define CSOR_NAND_RAL_2			0x00800000
-#define CSOR_NAND_RAL_3			0x01000000
-#define CSOR_NAND_RAL_4			0x01800000
-/* Page Size 512b, 2k, 4k */
-#define CSOR_NAND_PGS_MASK		0x00180000
-#define CSOR_NAND_PGS_SHIFT		16
-#define CSOR_NAND_PGS_512		0x00000000
-#define CSOR_NAND_PGS_2K		0x00080000
-#define CSOR_NAND_PGS_4K		0x00100000
-/* Spare region Size */
-#define CSOR_NAND_SPRZ_MASK		0x0000E000
-#define CSOR_NAND_SPRZ_SHIFT		13
-#define CSOR_NAND_SPRZ_16		0x00000000
-#define CSOR_NAND_SPRZ_64		0x00002000
-#define CSOR_NAND_SPRZ_128		0x00004000
-#define CSOR_NAND_SPRZ_210		0x00006000
-#define CSOR_NAND_SPRZ_218		0x00008000
-#define CSOR_NAND_SPRZ_224		0x0000A000
-/* Pages Per Block */
-#define CSOR_NAND_PB_MASK		0x00000700
-#define CSOR_NAND_PB_SHIFT		8
-#define CSOR_NAND_PB(n)		((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT)
-/* Time for Read Enable High to Output High Impedance */
-#define CSOR_NAND_TRHZ_MASK		0x0000001C
-#define CSOR_NAND_TRHZ_SHIFT		2
-#define CSOR_NAND_TRHZ_20		0x00000000
-#define CSOR_NAND_TRHZ_40		0x00000004
-#define CSOR_NAND_TRHZ_60		0x00000008
-#define CSOR_NAND_TRHZ_80		0x0000000C
-#define CSOR_NAND_TRHZ_100		0x00000010
-/* Buffer control disable */
-#define CSOR_NAND_BCTLD			0x00000001
-
-/*
- * Chip Select Option Register - NOR Flash Mode
- */
-/* Enable Address shift Mode */
-#define CSOR_NOR_ADM_SHFT_MODE_EN	0x80000000
-/* Page Read Enable from NOR device */
-#define CSOR_NOR_PGRD_EN		0x10000000
-/* AVD Toggle Enable during Burst Program */
-#define CSOR_NOR_AVD_TGL_PGM_EN		0x01000000
-/* Address Data Multiplexing Shift */
-#define CSOR_NOR_ADM_MASK		0x0003E000
-#define CSOR_NOR_ADM_SHIFT_SHIFT	13
-#define CSOR_NOR_ADM_SHIFT(n)	((n) << CSOR_NOR_ADM_SHIFT_SHIFT)
-/* Type of the NOR device hooked */
-#define CSOR_NOR_NOR_MODE_AYSNC_NOR	0x00000000
-#define CSOR_NOR_NOR_MODE_AVD_NOR	0x00000020
-/* Time for Read Enable High to Output High Impedance */
-#define CSOR_NOR_TRHZ_MASK		0x0000001C
-#define CSOR_NOR_TRHZ_SHIFT		2
-#define CSOR_NOR_TRHZ_20		0x00000000
-#define CSOR_NOR_TRHZ_40		0x00000004
-#define CSOR_NOR_TRHZ_60		0x00000008
-#define CSOR_NOR_TRHZ_80		0x0000000C
-#define CSOR_NOR_TRHZ_100		0x00000010
-/* Buffer control disable */
-#define CSOR_NOR_BCTLD			0x00000001
-
-/*
- * Chip Select Option Register - GPCM Mode
- */
-/* GPCM Mode - Normal */
-#define CSOR_GPCM_GPMODE_NORMAL		0x00000000
-/* GPCM Mode - GenericASIC */
-#define CSOR_GPCM_GPMODE_ASIC		0x80000000
-/* Parity Mode odd/even */
-#define CSOR_GPCM_PARITY_EVEN		0x40000000
-/* Parity Checking enable/disable */
-#define CSOR_GPCM_PAR_EN		0x20000000
-/* GPCM Timeout Count */
-#define CSOR_GPCM_GPTO_MASK		0x0F000000
-#define CSOR_GPCM_GPTO_SHIFT		24
-#define CSOR_GPCM_GPTO(n)	((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT)
-/* GPCM External Access Termination mode for read access */
-#define CSOR_GPCM_RGETA_EXT		0x00080000
-/* GPCM External Access Termination mode for write access */
-#define CSOR_GPCM_WGETA_EXT		0x00040000
-/* Address Data Multiplexing Shift */
-#define CSOR_GPCM_ADM_MASK		0x0003E000
-#define CSOR_GPCM_ADM_SHIFT_SHIFT	13
-#define CSOR_GPCM_ADM_SHIFT(n)	((n) << CSOR_GPCM_ADM_SHIFT_SHIFT)
-/* Generic ASIC Parity error indication delay */
-#define CSOR_GPCM_GAPERRD_MASK		0x00000180
-#define CSOR_GPCM_GAPERRD_SHIFT		7
-#define CSOR_GPCM_GAPERRD(n)	(((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT)
-/* Time for Read Enable High to Output High Impedance */
-#define CSOR_GPCM_TRHZ_MASK		0x0000001C
-#define CSOR_GPCM_TRHZ_20		0x00000000
-#define CSOR_GPCM_TRHZ_40		0x00000004
-#define CSOR_GPCM_TRHZ_60		0x00000008
-#define CSOR_GPCM_TRHZ_80		0x0000000C
-#define CSOR_GPCM_TRHZ_100		0x00000010
-/* Buffer control disable */
-#define CSOR_GPCM_BCTLD			0x00000001
-
-/*
- * Ready Busy Status Register (RB_STAT)
- */
-/* CSn is READY */
-#define IFC_RB_STAT_READY_CS0		0x80000000
-#define IFC_RB_STAT_READY_CS1		0x40000000
-#define IFC_RB_STAT_READY_CS2		0x20000000
-#define IFC_RB_STAT_READY_CS3		0x10000000
-
-/*
- * General Control Register (GCR)
- */
-#define IFC_GCR_MASK			0x8000F800
-/* reset all IFC hardware */
-#define IFC_GCR_SOFT_RST_ALL		0x80000000
-/* Turnaroud Time of external buffer */
-#define IFC_GCR_TBCTL_TRN_TIME		0x0000F800
-#define IFC_GCR_TBCTL_TRN_TIME_SHIFT	11
-
-/*
- * Common Event and Error Status Register (CM_EVTER_STAT)
- */
-/* Chip select error */
-#define IFC_CM_EVTER_STAT_CSER		0x80000000
-
-/*
- * Common Event and Error Enable Register (CM_EVTER_EN)
- */
-/* Chip select error checking enable */
-#define IFC_CM_EVTER_EN_CSEREN		0x80000000
-
-/*
- * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN)
- */
-/* Chip select error interrupt enable */
-#define IFC_CM_EVTER_INTR_EN_CSERIREN	0x80000000
-
-/*
- * Common Transfer Error Attribute Register-0 (CM_ERATTR0)
- */
-/* transaction type of error Read/Write */
-#define IFC_CM_ERATTR0_ERTYP_READ	0x80000000
-#define IFC_CM_ERATTR0_ERAID		0x0FF00000
-#define IFC_CM_ERATTR0_ERAID_SHIFT	20
-#define IFC_CM_ERATTR0_ESRCID		0x0000FF00
-#define IFC_CM_ERATTR0_ESRCID_SHIFT	8
-
-/*
- * Clock Control Register (CCR)
- */
-#define IFC_CCR_MASK			0x0F0F8800
-/* Clock division ratio */
-#define IFC_CCR_CLK_DIV_MASK		0x0F000000
-#define IFC_CCR_CLK_DIV_SHIFT		24
-#define IFC_CCR_CLK_DIV(n)		((n-1) << IFC_CCR_CLK_DIV_SHIFT)
-/* IFC Clock Delay */
-#define IFC_CCR_CLK_DLY_MASK		0x000F0000
-#define IFC_CCR_CLK_DLY_SHIFT		16
-#define IFC_CCR_CLK_DLY(n)		((n) << IFC_CCR_CLK_DLY_SHIFT)
-/* Invert IFC clock before sending out */
-#define IFC_CCR_INV_CLK_EN		0x00008000
-/* Fedback IFC Clock */
-#define IFC_CCR_FB_IFC_CLK_SEL		0x00000800
-
-/*
- * Clock Status Register (CSR)
- */
-/* Clk is stable */
-#define IFC_CSR_CLK_STAT_STABLE		0x80000000
-
-/*
- * IFC_NAND Machine Specific Registers
- */
-/*
- * NAND Configuration Register (NCFGR)
- */
-/* Auto Boot Mode */
-#define IFC_NAND_NCFGR_BOOT		0x80000000
-/* Addressing Mode-ROW0+n/COL0 */
-#define IFC_NAND_NCFGR_ADDR_MODE_RC0	0x00000000
-/* Addressing Mode-ROW0+n/COL0+n */
-#define IFC_NAND_NCFGR_ADDR_MODE_RC1	0x00400000
-/* Number of loop iterations of FIR sequences for multi page operations */
-#define IFC_NAND_NCFGR_NUM_LOOP_MASK	0x0000F000
-#define IFC_NAND_NCFGR_NUM_LOOP_SHIFT	12
-#define IFC_NAND_NCFGR_NUM_LOOP(n)	((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT)
-/* Number of wait cycles */
-#define IFC_NAND_NCFGR_NUM_WAIT_MASK	0x000000FF
-#define IFC_NAND_NCFGR_NUM_WAIT_SHIFT	0
-
-/*
- * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1)
- */
-/* General purpose FCM flash command bytes CMD0-CMD7 */
-#define IFC_NAND_FCR0_CMD0		0xFF000000
-#define IFC_NAND_FCR0_CMD0_SHIFT	24
-#define IFC_NAND_FCR0_CMD1		0x00FF0000
-#define IFC_NAND_FCR0_CMD1_SHIFT	16
-#define IFC_NAND_FCR0_CMD2		0x0000FF00
-#define IFC_NAND_FCR0_CMD2_SHIFT	8
-#define IFC_NAND_FCR0_CMD3		0x000000FF
-#define IFC_NAND_FCR0_CMD3_SHIFT	0
-#define IFC_NAND_FCR1_CMD4		0xFF000000
-#define IFC_NAND_FCR1_CMD4_SHIFT	24
-#define IFC_NAND_FCR1_CMD5		0x00FF0000
-#define IFC_NAND_FCR1_CMD5_SHIFT	16
-#define IFC_NAND_FCR1_CMD6		0x0000FF00
-#define IFC_NAND_FCR1_CMD6_SHIFT	8
-#define IFC_NAND_FCR1_CMD7		0x000000FF
-#define IFC_NAND_FCR1_CMD7_SHIFT	0
-
-/*
- * Flash ROW and COL Address Register (ROWn, COLn)
- */
-/* Main/spare region locator */
-#define IFC_NAND_COL_MS			0x80000000
-/* Column Address */
-#define IFC_NAND_COL_CA_MASK		0x00000FFF
-
-/*
- * NAND Flash Byte Count Register (NAND_BC)
- */
-/* Byte Count for read/Write */
-#define IFC_NAND_BC			0x000001FF
-
-/*
- * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2)
- */
-/* NAND Machine specific opcodes OP0-OP14*/
-#define IFC_NAND_FIR0_OP0		0xFC000000
-#define IFC_NAND_FIR0_OP0_SHIFT		26
-#define IFC_NAND_FIR0_OP1		0x03F00000
-#define IFC_NAND_FIR0_OP1_SHIFT		20
-#define IFC_NAND_FIR0_OP2		0x000FC000
-#define IFC_NAND_FIR0_OP2_SHIFT		14
-#define IFC_NAND_FIR0_OP3		0x00003F00
-#define IFC_NAND_FIR0_OP3_SHIFT		8
-#define IFC_NAND_FIR0_OP4		0x000000FC
-#define IFC_NAND_FIR0_OP4_SHIFT		2
-#define IFC_NAND_FIR1_OP5		0xFC000000
-#define IFC_NAND_FIR1_OP5_SHIFT		26
-#define IFC_NAND_FIR1_OP6		0x03F00000
-#define IFC_NAND_FIR1_OP6_SHIFT		20
-#define IFC_NAND_FIR1_OP7		0x000FC000
-#define IFC_NAND_FIR1_OP7_SHIFT		14
-#define IFC_NAND_FIR1_OP8		0x00003F00
-#define IFC_NAND_FIR1_OP8_SHIFT		8
-#define IFC_NAND_FIR1_OP9		0x000000FC
-#define IFC_NAND_FIR1_OP9_SHIFT		2
-#define IFC_NAND_FIR2_OP10		0xFC000000
-#define IFC_NAND_FIR2_OP10_SHIFT	26
-#define IFC_NAND_FIR2_OP11		0x03F00000
-#define IFC_NAND_FIR2_OP11_SHIFT	20
-#define IFC_NAND_FIR2_OP12		0x000FC000
-#define IFC_NAND_FIR2_OP12_SHIFT	14
-#define IFC_NAND_FIR2_OP13		0x00003F00
-#define IFC_NAND_FIR2_OP13_SHIFT	8
-#define IFC_NAND_FIR2_OP14		0x000000FC
-#define IFC_NAND_FIR2_OP14_SHIFT	2
-
-/*
- * Instruction opcodes to be programmed
- * in FIR registers- 6bits
- */
-enum ifc_nand_fir_opcodes {
-	IFC_FIR_OP_NOP,
-	IFC_FIR_OP_CA0,
-	IFC_FIR_OP_CA1,
-	IFC_FIR_OP_CA2,
-	IFC_FIR_OP_CA3,
-	IFC_FIR_OP_RA0,
-	IFC_FIR_OP_RA1,
-	IFC_FIR_OP_RA2,
-	IFC_FIR_OP_RA3,
-	IFC_FIR_OP_CMD0,
-	IFC_FIR_OP_CMD1,
-	IFC_FIR_OP_CMD2,
-	IFC_FIR_OP_CMD3,
-	IFC_FIR_OP_CMD4,
-	IFC_FIR_OP_CMD5,
-	IFC_FIR_OP_CMD6,
-	IFC_FIR_OP_CMD7,
-	IFC_FIR_OP_CW0,
-	IFC_FIR_OP_CW1,
-	IFC_FIR_OP_CW2,
-	IFC_FIR_OP_CW3,
-	IFC_FIR_OP_CW4,
-	IFC_FIR_OP_CW5,
-	IFC_FIR_OP_CW6,
-	IFC_FIR_OP_CW7,
-	IFC_FIR_OP_WBCD,
-	IFC_FIR_OP_RBCD,
-	IFC_FIR_OP_BTRD,
-	IFC_FIR_OP_RDSTAT,
-	IFC_FIR_OP_NWAIT,
-	IFC_FIR_OP_WFR,
-	IFC_FIR_OP_SBRD,
-	IFC_FIR_OP_UA,
-	IFC_FIR_OP_RB,
-};
-
-/*
- * NAND Chip Select Register (NAND_CSEL)
- */
-#define IFC_NAND_CSEL			0x0C000000
-#define IFC_NAND_CSEL_SHIFT		26
-#define IFC_NAND_CSEL_CS0		0x00000000
-#define IFC_NAND_CSEL_CS1		0x04000000
-#define IFC_NAND_CSEL_CS2		0x08000000
-#define IFC_NAND_CSEL_CS3		0x0C000000
-
-/*
- * NAND Operation Sequence Start (NANDSEQ_STRT)
- */
-/* NAND Flash Operation Start */
-#define IFC_NAND_SEQ_STRT_FIR_STRT	0x80000000
-/* Automatic Erase */
-#define IFC_NAND_SEQ_STRT_AUTO_ERS	0x00800000
-/* Automatic Program */
-#define IFC_NAND_SEQ_STRT_AUTO_PGM	0x00100000
-/* Automatic Copyback */
-#define IFC_NAND_SEQ_STRT_AUTO_CPB	0x00020000
-/* Automatic Read Operation */
-#define IFC_NAND_SEQ_STRT_AUTO_RD	0x00004000
-/* Automatic Status Read */
-#define IFC_NAND_SEQ_STRT_AUTO_STAT_RD	0x00000800
-
-/*
- * NAND Event and Error Status Register (NAND_EVTER_STAT)
- */
-/* Operation Complete */
-#define IFC_NAND_EVTER_STAT_OPC		0x80000000
-/* Flash Timeout Error */
-#define IFC_NAND_EVTER_STAT_FTOER	0x08000000
-/* Write Protect Error */
-#define IFC_NAND_EVTER_STAT_WPER	0x04000000
-/* ECC Error */
-#define IFC_NAND_EVTER_STAT_ECCER	0x02000000
-/* RCW Load Done */
-#define IFC_NAND_EVTER_STAT_RCW_DN	0x00008000
-/* Boot Loadr Done */
-#define IFC_NAND_EVTER_STAT_BOOT_DN	0x00004000
-/* Bad Block Indicator search select */
-#define IFC_NAND_EVTER_STAT_BBI_SRCH_SE	0x00000800
-
-/*
- * NAND Flash Page Read Completion Event Status Register
- * (PGRDCMPL_EVT_STAT)
- */
-#define PGRDCMPL_EVT_STAT_MASK		0xFFFF0000
-/* Small Page 0-15 Done */
-#define PGRDCMPL_EVT_STAT_SECTION_SP(n)	(1 << (31 - (n)))
-/* Large Page(2K) 0-3 Done */
-#define PGRDCMPL_EVT_STAT_LP_2K(n)	(0xF << (28 - (n)*4))
-/* Large Page(4K) 0-1 Done */
-#define PGRDCMPL_EVT_STAT_LP_4K(n)	(0xFF << (24 - (n)*8))
-
-/*
- * NAND Event and Error Enable Register (NAND_EVTER_EN)
- */
-/* Operation complete event enable */
-#define IFC_NAND_EVTER_EN_OPC_EN	0x80000000
-/* Page read complete event enable */
-#define IFC_NAND_EVTER_EN_PGRDCMPL_EN	0x20000000
-/* Flash Timeout error enable */
-#define IFC_NAND_EVTER_EN_FTOER_EN	0x08000000
-/* Write Protect error enable */
-#define IFC_NAND_EVTER_EN_WPER_EN	0x04000000
-/* ECC error logging enable */
-#define IFC_NAND_EVTER_EN_ECCER_EN	0x02000000
-
-/*
- * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN)
- */
-/* Enable interrupt for operation complete */
-#define IFC_NAND_EVTER_INTR_OPCIR_EN		0x80000000
-/* Enable interrupt for Page read complete */
-#define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN	0x20000000
-/* Enable interrupt for Flash timeout error */
-#define IFC_NAND_EVTER_INTR_FTOERIR_EN		0x08000000
-/* Enable interrupt for Write protect error */
-#define IFC_NAND_EVTER_INTR_WPERIR_EN		0x04000000
-/* Enable interrupt for ECC error*/
-#define IFC_NAND_EVTER_INTR_ECCERIR_EN		0x02000000
-
-/*
- * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0)
- */
-#define IFC_NAND_ERATTR0_MASK		0x0C080000
-/* Error on CS0-3 for NAND */
-#define IFC_NAND_ERATTR0_ERCS_CS0	0x00000000
-#define IFC_NAND_ERATTR0_ERCS_CS1	0x04000000
-#define IFC_NAND_ERATTR0_ERCS_CS2	0x08000000
-#define IFC_NAND_ERATTR0_ERCS_CS3	0x0C000000
-/* Transaction type of error Read/Write */
-#define IFC_NAND_ERATTR0_ERTTYPE_READ	0x00080000
-
-/*
- * NAND Flash Status Register (NAND_FSR)
- */
-/* First byte of data read from read status op */
-#define IFC_NAND_NFSR_RS0		0xFF000000
-/* Second byte of data read from read status op */
-#define IFC_NAND_NFSR_RS1		0x00FF0000
-
-/*
- * ECC Error Status Registers (ECCSTAT0-ECCSTAT3)
- */
-/* Number of ECC errors on sector n (n = 0-15) */
-#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK	0x0F000000
-#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT	24
-#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK	0x000F0000
-#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT	16
-#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK	0x00000F00
-#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT	8
-#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK	0x0000000F
-#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT	0
-#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK	0x0F000000
-#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT	24
-#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK	0x000F0000
-#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT	16
-#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK	0x00000F00
-#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT	8
-#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK	0x0000000F
-#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT	0
-#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK	0x0F000000
-#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT	24
-#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK	0x000F0000
-#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT	16
-#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK	0x00000F00
-#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT	8
-#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK	0x0000000F
-#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT	0
-#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK	0x0F000000
-#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT	24
-#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK	0x000F0000
-#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT	16
-#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK	0x00000F00
-#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT	8
-#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK	0x0000000F
-#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT	0
-
-/*
- * NAND Control Register (NANDCR)
- */
-#define IFC_NAND_NCR_FTOCNT_MASK	0x1E000000
-#define IFC_NAND_NCR_FTOCNT_SHIFT	25
-#define IFC_NAND_NCR_FTOCNT(n)	((_ilog2(n) - 8)  << IFC_NAND_NCR_FTOCNT_SHIFT)
-
-/*
- * NAND_AUTOBOOT_TRGR
- */
-/* Trigger RCW load */
-#define IFC_NAND_AUTOBOOT_TRGR_RCW_LD	0x80000000
-/* Trigget Auto Boot */
-#define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD	0x20000000
-
-/*
- * NAND_MDR
- */
-/* 1st read data byte when opcode SBRD */
-#define IFC_NAND_MDR_RDATA0		0xFF000000
-/* 2nd read data byte when opcode SBRD */
-#define IFC_NAND_MDR_RDATA1		0x00FF0000
-
-/*
- * NOR Machine Specific Registers
- */
-/*
- * NOR Event and Error Status Register (NOR_EVTER_STAT)
- */
-/* NOR Command Sequence Operation Complete */
-#define IFC_NOR_EVTER_STAT_OPC_NOR	0x80000000
-/* Write Protect Error */
-#define IFC_NOR_EVTER_STAT_WPER		0x04000000
-/* Command Sequence Timeout Error */
-#define IFC_NOR_EVTER_STAT_STOER	0x01000000
-
-/*
- * NOR Event and Error Enable Register (NOR_EVTER_EN)
- */
-/* NOR Command Seq complete event enable */
-#define IFC_NOR_EVTER_EN_OPCEN_NOR	0x80000000
-/* Write Protect Error Checking Enable */
-#define IFC_NOR_EVTER_EN_WPEREN		0x04000000
-/* Timeout Error Enable */
-#define IFC_NOR_EVTER_EN_STOEREN	0x01000000
-
-/*
- * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN)
- */
-/* Enable interrupt for OPC complete */
-#define IFC_NOR_EVTER_INTR_OPCEN_NOR	0x80000000
-/* Enable interrupt for write protect error */
-#define IFC_NOR_EVTER_INTR_WPEREN	0x04000000
-/* Enable interrupt for timeout error */
-#define IFC_NOR_EVTER_INTR_STOEREN	0x01000000
-
-/*
- * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0)
- */
-/* Source ID for error transaction */
-#define IFC_NOR_ERATTR0_ERSRCID		0xFF000000
-/* AXI ID for error transation */
-#define IFC_NOR_ERATTR0_ERAID		0x000FF000
-/* Chip select corresponds to NOR error */
-#define IFC_NOR_ERATTR0_ERCS_CS0	0x00000000
-#define IFC_NOR_ERATTR0_ERCS_CS1	0x00000010
-#define IFC_NOR_ERATTR0_ERCS_CS2	0x00000020
-#define IFC_NOR_ERATTR0_ERCS_CS3	0x00000030
-/* Type of transaction read/write */
-#define IFC_NOR_ERATTR0_ERTYPE_READ	0x00000001
-
-/*
- * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2)
- */
-#define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP	0x000F0000
-#define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER	0x00000F00
-
-/*
- * NOR Control Register (NORCR)
- */
-#define IFC_NORCR_MASK			0x0F0F0000
-/* No. of Address/Data Phase */
-#define IFC_NORCR_NUM_PHASE_MASK	0x0F000000
-#define IFC_NORCR_NUM_PHASE_SHIFT	24
-#define IFC_NORCR_NUM_PHASE(n)	((n-1) << IFC_NORCR_NUM_PHASE_SHIFT)
-/* Sequence Timeout Count */
-#define IFC_NORCR_STOCNT_MASK		0x000F0000
-#define IFC_NORCR_STOCNT_SHIFT		16
-#define IFC_NORCR_STOCNT(n)	((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT)
-
-/*
- * GPCM Machine specific registers
- */
-/*
- * GPCM Event and Error Status Register (GPCM_EVTER_STAT)
- */
-/* Timeout error */
-#define IFC_GPCM_EVTER_STAT_TOER	0x04000000
-/* Parity error */
-#define IFC_GPCM_EVTER_STAT_PER		0x01000000
-
-/*
- * GPCM Event and Error Enable Register (GPCM_EVTER_EN)
- */
-/* Timeout error enable */
-#define IFC_GPCM_EVTER_EN_TOER_EN	0x04000000
-/* Parity error enable */
-#define IFC_GPCM_EVTER_EN_PER_EN	0x01000000
-
-/*
- * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN)
- */
-/* Enable Interrupt for timeout error */
-#define IFC_GPCM_EEIER_TOERIR_EN	0x04000000
-/* Enable Interrupt for Parity error */
-#define IFC_GPCM_EEIER_PERIR_EN		0x01000000
-
-/*
- * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0)
- */
-/* Source ID for error transaction */
-#define IFC_GPCM_ERATTR0_ERSRCID	0xFF000000
-/* AXI ID for error transaction */
-#define IFC_GPCM_ERATTR0_ERAID		0x000FF000
-/* Chip select corresponds to GPCM error */
-#define IFC_GPCM_ERATTR0_ERCS_CS0	0x00000000
-#define IFC_GPCM_ERATTR0_ERCS_CS1	0x00000040
-#define IFC_GPCM_ERATTR0_ERCS_CS2	0x00000080
-#define IFC_GPCM_ERATTR0_ERCS_CS3	0x000000C0
-/* Type of transaction read/Write */
-#define IFC_GPCM_ERATTR0_ERTYPE_READ	0x00000001
-
-/*
- * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2)
- */
-/* On which beat of address/data parity error is observed */
-#define IFC_GPCM_ERATTR2_PERR_BEAT		0x00000C00
-/* Parity Error on byte */
-#define IFC_GPCM_ERATTR2_PERR_BYTE		0x000000F0
-/* Parity Error reported in addr or data phase */
-#define IFC_GPCM_ERATTR2_PERR_DATA_PHASE	0x00000001
-
-/*
- * GPCM Status Register (GPCM_STAT)
- */
-#define IFC_GPCM_STAT_BSY		0x80000000  /* GPCM is busy */
-
-/*
- * IFC Controller NAND Machine registers
- */
-struct fsl_ifc_nand {
-	__be32 ncfgr;
-	u32 res1[0x4];
-	__be32 nand_fcr0;
-	__be32 nand_fcr1;
-	u32 res2[0x8];
-	__be32 row0;
-	u32 res3;
-	__be32 col0;
-	u32 res4;
-	__be32 row1;
-	u32 res5;
-	__be32 col1;
-	u32 res6;
-	__be32 row2;
-	u32 res7;
-	__be32 col2;
-	u32 res8;
-	__be32 row3;
-	u32 res9;
-	__be32 col3;
-	u32 res10[0x24];
-	__be32 nand_fbcr;
-	u32 res11;
-	__be32 nand_fir0;
-	__be32 nand_fir1;
-	__be32 nand_fir2;
-	u32 res12[0x10];
-	__be32 nand_csel;
-	u32 res13;
-	__be32 nandseq_strt;
-	u32 res14;
-	__be32 nand_evter_stat;
-	u32 res15;
-	__be32 pgrdcmpl_evt_stat;
-	u32 res16[0x2];
-	__be32 nand_evter_en;
-	u32 res17[0x2];
-	__be32 nand_evter_intr_en;
-	u32 res18[0x2];
-	__be32 nand_erattr0;
-	__be32 nand_erattr1;
-	u32 res19[0x10];
-	__be32 nand_fsr;
-	u32 res20;
-	__be32 nand_eccstat[4];
-	u32 res21[0x20];
-	__be32 nanndcr;
-	u32 res22[0x2];
-	__be32 nand_autoboot_trgr;
-	u32 res23;
-	__be32 nand_mdr;
-	u32 res24[0x5C];
-};
-
-/*
- * IFC controller NOR Machine registers
- */
-struct fsl_ifc_nor {
-	__be32 nor_evter_stat;
-	u32 res1[0x2];
-	__be32 nor_evter_en;
-	u32 res2[0x2];
-	__be32 nor_evter_intr_en;
-	u32 res3[0x2];
-	__be32 nor_erattr0;
-	__be32 nor_erattr1;
-	__be32 nor_erattr2;
-	u32 res4[0x4];
-	__be32 norcr;
-	u32 res5[0xEF];
-};
-
-/*
- * IFC controller GPCM Machine registers
- */
-struct fsl_ifc_gpcm {
-	__be32 gpcm_evter_stat;
-	u32 res1[0x2];
-	__be32 gpcm_evter_en;
-	u32 res2[0x2];
-	__be32 gpcm_evter_intr_en;
-	u32 res3[0x2];
-	__be32 gpcm_erattr0;
-	__be32 gpcm_erattr1;
-	__be32 gpcm_erattr2;
-	__be32 gpcm_stat;
-	u32 res4[0x1F3];
-};
-
-/*
- * IFC Controller Registers
- */
-struct fsl_ifc_regs {
-	__be32 ifc_rev;
-	u32 res1[0x3];
-	struct {
-		__be32 cspr;
-		u32 res2[0x2];
-	} cspr_cs[FSL_IFC_BANK_COUNT];
-	u32 res3[0x18];
-	struct {
-		__be32 amask;
-		u32 res4[0x2];
-	} amask_cs[FSL_IFC_BANK_COUNT];
-	u32 res5[0x18];
-	struct {
-		__be32 csor;
-		u32 res6[0x2];
-	} csor_cs[FSL_IFC_BANK_COUNT];
-	u32 res7[0x18];
-	struct {
-		__be32 ftim[4];
-		u32 res8[0x8];
-	} ftim_cs[FSL_IFC_BANK_COUNT];
-	u32 res9[0x60];
-	__be32 rb_stat;
-	u32 res10[0x2];
-	__be32 ifc_gcr;
-	u32 res11[0x2];
-	__be32 cm_evter_stat;
-	u32 res12[0x2];
-	__be32 cm_evter_en;
-	u32 res13[0x2];
-	__be32 cm_evter_intr_en;
-	u32 res14[0x2];
-	__be32 cm_erattr0;
-	__be32 cm_erattr1;
-	u32 res15[0x2];
-	__be32 ifc_ccr;
-	__be32 ifc_csr;
-	u32 res16[0x2EB];
-	struct fsl_ifc_nand ifc_nand;
-	struct fsl_ifc_nor ifc_nor;
-	struct fsl_ifc_gpcm ifc_gpcm;
-};
-
-extern unsigned int convert_ifc_address(phys_addr_t addr_base);
-extern int fsl_ifc_find(phys_addr_t addr_base);
-
-/* overview of the fsl ifc controller */
-
-struct fsl_ifc_ctrl {
-	/* device info */
-	struct device			*dev;
-	struct fsl_ifc_regs __iomem	*regs;
-	int				irq;
-	int				nand_irq;
-	spinlock_t			lock;
-	void				*nand;
-
-	u32 nand_stat;
-	wait_queue_head_t nand_wait;
-};
-
-extern struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
-
-
-#endif /* __ASM_FSL_IFC_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/fsl_lbc.h b/ANDROID_3.4.5/arch/powerpc/include/asm/fsl_lbc.h
deleted file mode 100644
index 420b4536..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/fsl_lbc.h
+++ /dev/null
@@ -1,306 +0,0 @@
-/* Freescale Local Bus Controller
- *
- * Copyright © 2006-2007, 2010 Freescale Semiconductor
- *
- * Authors: Nick Spence <nick.spence@freescale.com>,
- *          Scott Wood <scottwood@freescale.com>
- *          Jack Lan <jack.lan@freescale.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#ifndef __ASM_FSL_LBC_H
-#define __ASM_FSL_LBC_H
-
-#include <linux/compiler.h>
-#include <linux/types.h>
-#include <linux/io.h>
-#include <linux/device.h>
-#include <linux/spinlock.h>
-
-struct fsl_lbc_bank {
-	__be32 br;             /**< Base Register  */
-#define BR_BA           0xFFFF8000
-#define BR_BA_SHIFT             15
-#define BR_PS           0x00001800
-#define BR_PS_SHIFT             11
-#define BR_PS_8         0x00000800  /* Port Size 8 bit */
-#define BR_PS_16        0x00001000  /* Port Size 16 bit */
-#define BR_PS_32        0x00001800  /* Port Size 32 bit */
-#define BR_DECC         0x00000600
-#define BR_DECC_SHIFT            9
-#define BR_DECC_OFF     0x00000000  /* HW ECC checking and generation off */
-#define BR_DECC_CHK     0x00000200  /* HW ECC checking on, generation off */
-#define BR_DECC_CHK_GEN 0x00000400  /* HW ECC checking and generation on */
-#define BR_WP           0x00000100
-#define BR_WP_SHIFT              8
-#define BR_MSEL         0x000000E0
-#define BR_MSEL_SHIFT            5
-#define BR_MS_GPCM      0x00000000  /* GPCM */
-#define BR_MS_FCM       0x00000020  /* FCM */
-#define BR_MS_SDRAM     0x00000060  /* SDRAM */
-#define BR_MS_UPMA      0x00000080  /* UPMA */
-#define BR_MS_UPMB      0x000000A0  /* UPMB */
-#define BR_MS_UPMC      0x000000C0  /* UPMC */
-#define BR_V            0x00000001
-#define BR_V_SHIFT               0
-#define BR_RES          ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V)
-
-	__be32 or;             /**< Base Register  */
-#define OR0 0x5004
-#define OR1 0x500C
-#define OR2 0x5014
-#define OR3 0x501C
-#define OR4 0x5024
-#define OR5 0x502C
-#define OR6 0x5034
-#define OR7 0x503C
-
-#define OR_FCM_AM               0xFFFF8000
-#define OR_FCM_AM_SHIFT                 15
-#define OR_FCM_BCTLD            0x00001000
-#define OR_FCM_BCTLD_SHIFT              12
-#define OR_FCM_PGS              0x00000400
-#define OR_FCM_PGS_SHIFT                10
-#define OR_FCM_CSCT             0x00000200
-#define OR_FCM_CSCT_SHIFT                9
-#define OR_FCM_CST              0x00000100
-#define OR_FCM_CST_SHIFT                 8
-#define OR_FCM_CHT              0x00000080
-#define OR_FCM_CHT_SHIFT                 7
-#define OR_FCM_SCY              0x00000070
-#define OR_FCM_SCY_SHIFT                 4
-#define OR_FCM_SCY_1            0x00000010
-#define OR_FCM_SCY_2            0x00000020
-#define OR_FCM_SCY_3            0x00000030
-#define OR_FCM_SCY_4            0x00000040
-#define OR_FCM_SCY_5            0x00000050
-#define OR_FCM_SCY_6            0x00000060
-#define OR_FCM_SCY_7            0x00000070
-#define OR_FCM_RST              0x00000008
-#define OR_FCM_RST_SHIFT                 3
-#define OR_FCM_TRLX             0x00000004
-#define OR_FCM_TRLX_SHIFT                2
-#define OR_FCM_EHTR             0x00000002
-#define OR_FCM_EHTR_SHIFT                1
-};
-
-struct fsl_lbc_regs {
-	struct fsl_lbc_bank bank[12];
-	u8 res0[0x8];
-	__be32 mar;             /**< UPM Address Register */
-	u8 res1[0x4];
-	__be32 mamr;            /**< UPMA Mode Register */
-#define MxMR_OP_NO	(0 << 28) /**< normal operation */
-#define MxMR_OP_WA	(1 << 28) /**< write array */
-#define MxMR_OP_RA	(2 << 28) /**< read array */
-#define MxMR_OP_RP	(3 << 28) /**< run pattern */
-#define MxMR_MAD	0x3f      /**< machine address */
-	__be32 mbmr;            /**< UPMB Mode Register */
-	__be32 mcmr;            /**< UPMC Mode Register */
-	u8 res2[0x8];
-	__be32 mrtpr;           /**< Memory Refresh Timer Prescaler Register */
-	__be32 mdr;             /**< UPM Data Register */
-	u8 res3[0x4];
-	__be32 lsor;            /**< Special Operation Initiation Register */
-	__be32 lsdmr;           /**< SDRAM Mode Register */
-	u8 res4[0x8];
-	__be32 lurt;            /**< UPM Refresh Timer */
-	__be32 lsrt;            /**< SDRAM Refresh Timer */
-	u8 res5[0x8];
-	__be32 ltesr;           /**< Transfer Error Status Register */
-#define LTESR_BM   0x80000000
-#define LTESR_FCT  0x40000000
-#define LTESR_PAR  0x20000000
-#define LTESR_WP   0x04000000
-#define LTESR_ATMW 0x00800000
-#define LTESR_ATMR 0x00400000
-#define LTESR_CS   0x00080000
-#define LTESR_UPM  0x00000002
-#define LTESR_CC   0x00000001
-#define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
-#define LTESR_MASK      (LTESR_BM | LTESR_FCT | LTESR_PAR | LTESR_WP \
-			 | LTESR_ATMW | LTESR_ATMR | LTESR_CS | LTESR_UPM \
-			 | LTESR_CC)
-#define LTESR_CLEAR	0xFFFFFFFF
-#define LTECCR_CLEAR	0xFFFFFFFF
-#define LTESR_STATUS	LTESR_MASK
-#define LTEIR_ENABLE	LTESR_MASK
-#define LTEDR_ENABLE	0x00000000
-	__be32 ltedr;           /**< Transfer Error Disable Register */
-	__be32 lteir;           /**< Transfer Error Interrupt Register */
-	__be32 lteatr;          /**< Transfer Error Attributes Register */
-	__be32 ltear;           /**< Transfer Error Address Register */
-	__be32 lteccr;          /**< Transfer Error ECC Register */
-	u8 res6[0x8];
-	__be32 lbcr;            /**< Configuration Register */
-#define LBCR_LDIS  0x80000000
-#define LBCR_LDIS_SHIFT    31
-#define LBCR_BCTLC 0x00C00000
-#define LBCR_BCTLC_SHIFT   22
-#define LBCR_AHD   0x00200000
-#define LBCR_LPBSE 0x00020000
-#define LBCR_LPBSE_SHIFT   17
-#define LBCR_EPAR  0x00010000
-#define LBCR_EPAR_SHIFT    16
-#define LBCR_BMT   0x0000FF00
-#define LBCR_BMT_SHIFT      8
-#define LBCR_BMTPS 0x0000000F
-#define LBCR_BMTPS_SHIFT    0
-#define LBCR_INIT  0x00040000
-	__be32 lcrr;            /**< Clock Ratio Register */
-#define LCRR_DBYP    0x80000000
-#define LCRR_DBYP_SHIFT      31
-#define LCRR_BUFCMDC 0x30000000
-#define LCRR_BUFCMDC_SHIFT   28
-#define LCRR_ECL     0x03000000
-#define LCRR_ECL_SHIFT       24
-#define LCRR_EADC    0x00030000
-#define LCRR_EADC_SHIFT      16
-#define LCRR_CLKDIV  0x0000000F
-#define LCRR_CLKDIV_SHIFT     0
-	u8 res7[0x8];
-	__be32 fmr;             /**< Flash Mode Register */
-#define FMR_CWTO     0x0000F000
-#define FMR_CWTO_SHIFT       12
-#define FMR_BOOT     0x00000800
-#define FMR_ECCM     0x00000100
-#define FMR_AL       0x00000030
-#define FMR_AL_SHIFT          4
-#define FMR_OP       0x00000003
-#define FMR_OP_SHIFT          0
-	__be32 fir;             /**< Flash Instruction Register */
-#define FIR_OP0      0xF0000000
-#define FIR_OP0_SHIFT        28
-#define FIR_OP1      0x0F000000
-#define FIR_OP1_SHIFT        24
-#define FIR_OP2      0x00F00000
-#define FIR_OP2_SHIFT        20
-#define FIR_OP3      0x000F0000
-#define FIR_OP3_SHIFT        16
-#define FIR_OP4      0x0000F000
-#define FIR_OP4_SHIFT        12
-#define FIR_OP5      0x00000F00
-#define FIR_OP5_SHIFT         8
-#define FIR_OP6      0x000000F0
-#define FIR_OP6_SHIFT         4
-#define FIR_OP7      0x0000000F
-#define FIR_OP7_SHIFT         0
-#define FIR_OP_NOP   0x0	/* No operation and end of sequence */
-#define FIR_OP_CA    0x1        /* Issue current column address */
-#define FIR_OP_PA    0x2        /* Issue current block+page address */
-#define FIR_OP_UA    0x3        /* Issue user defined address */
-#define FIR_OP_CM0   0x4        /* Issue command from FCR[CMD0] */
-#define FIR_OP_CM1   0x5        /* Issue command from FCR[CMD1] */
-#define FIR_OP_CM2   0x6        /* Issue command from FCR[CMD2] */
-#define FIR_OP_CM3   0x7        /* Issue command from FCR[CMD3] */
-#define FIR_OP_WB    0x8        /* Write FBCR bytes from FCM buffer */
-#define FIR_OP_WS    0x9        /* Write 1 or 2 bytes from MDR[AS] */
-#define FIR_OP_RB    0xA        /* Read FBCR bytes to FCM buffer */
-#define FIR_OP_RS    0xB        /* Read 1 or 2 bytes to MDR[AS] */
-#define FIR_OP_CW0   0xC        /* Wait then issue FCR[CMD0] */
-#define FIR_OP_CW1   0xD        /* Wait then issue FCR[CMD1] */
-#define FIR_OP_RBW   0xE        /* Wait then read FBCR bytes */
-#define FIR_OP_RSW   0xE        /* Wait then read 1 or 2 bytes */
-	__be32 fcr;             /**< Flash Command Register */
-#define FCR_CMD0     0xFF000000
-#define FCR_CMD0_SHIFT       24
-#define FCR_CMD1     0x00FF0000
-#define FCR_CMD1_SHIFT       16
-#define FCR_CMD2     0x0000FF00
-#define FCR_CMD2_SHIFT        8
-#define FCR_CMD3     0x000000FF
-#define FCR_CMD3_SHIFT        0
-	__be32 fbar;            /**< Flash Block Address Register */
-#define FBAR_BLK     0x00FFFFFF
-	__be32 fpar;            /**< Flash Page Address Register */
-#define FPAR_SP_PI   0x00007C00
-#define FPAR_SP_PI_SHIFT     10
-#define FPAR_SP_MS   0x00000200
-#define FPAR_SP_CI   0x000001FF
-#define FPAR_SP_CI_SHIFT      0
-#define FPAR_LP_PI   0x0003F000
-#define FPAR_LP_PI_SHIFT     12
-#define FPAR_LP_MS   0x00000800
-#define FPAR_LP_CI   0x000007FF
-#define FPAR_LP_CI_SHIFT      0
-	__be32 fbcr;            /**< Flash Byte Count Register */
-#define FBCR_BC      0x00000FFF
-};
-
-/*
- * FSL UPM routines
- */
-struct fsl_upm {
-	__be32 __iomem *mxmr;
-	int width;
-};
-
-extern u32 fsl_lbc_addr(phys_addr_t addr_base);
-extern int fsl_lbc_find(phys_addr_t addr_base);
-extern int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm);
-
-/**
- * fsl_upm_start_pattern - start UPM patterns execution
- * @upm:	pointer to the fsl_upm structure obtained via fsl_upm_find
- * @pat_offset:	UPM pattern offset for the command to be executed
- *
- * This routine programmes UPM so the next memory access that hits an UPM
- * will trigger pattern execution, starting at pat_offset.
- */
-static inline void fsl_upm_start_pattern(struct fsl_upm *upm, u8 pat_offset)
-{
-	clrsetbits_be32(upm->mxmr, MxMR_MAD, MxMR_OP_RP | pat_offset);
-}
-
-/**
- * fsl_upm_end_pattern - end UPM patterns execution
- * @upm:	pointer to the fsl_upm structure obtained via fsl_upm_find
- *
- * This routine reverts UPM to normal operation mode.
- */
-static inline void fsl_upm_end_pattern(struct fsl_upm *upm)
-{
-	clrbits32(upm->mxmr, MxMR_OP_RP);
-
-	while (in_be32(upm->mxmr) & MxMR_OP_RP)
-		cpu_relax();
-}
-
-/* overview of the fsl lbc controller */
-
-struct fsl_lbc_ctrl {
-	/* device info */
-	struct device			*dev;
-	struct fsl_lbc_regs __iomem	*regs;
-	int				irq;
-	wait_queue_head_t		irq_wait;
-	spinlock_t			lock;
-	void				*nand;
-
-	/* status read from LTESR by irq handler */
-	unsigned int			irq_status;
-
-#ifdef CONFIG_SUSPEND
-	/* save regs when system go to deep-sleep */
-	struct fsl_lbc_regs		*saved_regs;
-#endif
-};
-
-extern int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base,
-			       u32 mar);
-extern struct fsl_lbc_ctrl *fsl_lbc_ctrl_dev;
-
-#endif /* __ASM_FSL_LBC_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/ftrace.h b/ANDROID_3.4.5/arch/powerpc/include/asm/ftrace.h
deleted file mode 100644
index 169d039e..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/ftrace.h
+++ /dev/null
@@ -1,77 +0,0 @@
-#ifndef _ASM_POWERPC_FTRACE
-#define _ASM_POWERPC_FTRACE
-
-#ifdef CONFIG_FUNCTION_TRACER
-#define MCOUNT_ADDR		((long)(_mcount))
-#define MCOUNT_INSN_SIZE	4 /* sizeof mcount call */
-
-#ifdef __ASSEMBLY__
-
-/* Based off of objdump optput from glibc */
-
-#define MCOUNT_SAVE_FRAME			\
-	stwu	r1,-48(r1);			\
-	stw	r3, 12(r1);			\
-	stw	r4, 16(r1);			\
-	stw	r5, 20(r1);			\
-	stw	r6, 24(r1);			\
-	mflr	r3;				\
-	lwz	r4, 52(r1);			\
-	mfcr	r5;				\
-	stw	r7, 28(r1);			\
-	stw	r8, 32(r1);			\
-	stw	r9, 36(r1);			\
-	stw	r10,40(r1);			\
-	stw	r3, 44(r1);			\
-	stw	r5, 8(r1)
-
-#define MCOUNT_RESTORE_FRAME			\
-	lwz	r6, 8(r1);			\
-	lwz	r0, 44(r1);			\
-	lwz	r3, 12(r1);			\
-	mtctr	r0;				\
-	lwz	r4, 16(r1);			\
-	mtcr	r6;				\
-	lwz	r5, 20(r1);			\
-	lwz	r6, 24(r1);			\
-	lwz	r0, 52(r1);			\
-	lwz	r7, 28(r1);			\
-	lwz	r8, 32(r1);			\
-	mtlr	r0;				\
-	lwz	r9, 36(r1);			\
-	lwz	r10,40(r1);			\
-	addi	r1, r1, 48
-
-#else /* !__ASSEMBLY__ */
-extern void _mcount(void);
-
-#ifdef CONFIG_DYNAMIC_FTRACE
-static inline unsigned long ftrace_call_adjust(unsigned long addr)
-{
-       /* reloction of mcount call site is the same as the address */
-       return addr;
-}
-
-struct dyn_arch_ftrace {
-	struct module *mod;
-};
-#endif /*  CONFIG_DYNAMIC_FTRACE */
-#endif /* __ASSEMBLY__ */
-
-#endif
-
-#if defined(CONFIG_FTRACE_SYSCALLS) && defined(CONFIG_PPC64) && !defined(__ASSEMBLY__)
-#define ARCH_HAS_SYSCALL_MATCH_SYM_NAME
-static inline bool arch_syscall_match_sym_name(const char *sym, const char *name)
-{
-	/*
-	 * Compare the symbol name with the system call name. Skip the .sys or .SyS
-	 * prefix from the symbol name and the sys prefix from the system call name and
-	 * just match the rest. This is only needed on ppc64 since symbol names on
-	 * 32bit do not start with a period so the generic function will work.
-	 */
-	return !strcmp(sym + 4, name + 3);
-}
-#endif /* CONFIG_FTRACE_SYSCALLS && CONFIG_PPC64 && !__ASSEMBLY__ */
-
-#endif /* _ASM_POWERPC_FTRACE */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/futex.h b/ANDROID_3.4.5/arch/powerpc/include/asm/futex.h
deleted file mode 100644
index 2a9cf845..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/futex.h
+++ /dev/null
@@ -1,121 +0,0 @@
-#ifndef _ASM_POWERPC_FUTEX_H
-#define _ASM_POWERPC_FUTEX_H
-
-#ifdef __KERNEL__
-
-#include <linux/futex.h>
-#include <linux/uaccess.h>
-#include <asm/errno.h>
-#include <asm/synch.h>
-#include <asm/asm-compat.h>
-
-#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
-  __asm__ __volatile ( \
-	PPC_ATOMIC_ENTRY_BARRIER \
-"1:	lwarx	%0,0,%2\n" \
-	insn \
-	PPC405_ERR77(0, %2) \
-"2:	stwcx.	%1,0,%2\n" \
-	"bne-	1b\n" \
-	PPC_ATOMIC_EXIT_BARRIER \
-	"li	%1,0\n" \
-"3:	.section .fixup,\"ax\"\n" \
-"4:	li	%1,%3\n" \
-	"b	3b\n" \
-	".previous\n" \
-	".section __ex_table,\"a\"\n" \
-	".align 3\n" \
-	PPC_LONG "1b,4b,2b,4b\n" \
-	".previous" \
-	: "=&r" (oldval), "=&r" (ret) \
-	: "b" (uaddr), "i" (-EFAULT), "r" (oparg) \
-	: "cr0", "memory")
-
-static inline int futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
-{
-	int op = (encoded_op >> 28) & 7;
-	int cmp = (encoded_op >> 24) & 15;
-	int oparg = (encoded_op << 8) >> 20;
-	int cmparg = (encoded_op << 20) >> 20;
-	int oldval = 0, ret;
-	if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
-		oparg = 1 << oparg;
-
-	if (! access_ok (VERIFY_WRITE, uaddr, sizeof(u32)))
-		return -EFAULT;
-
-	pagefault_disable();
-
-	switch (op) {
-	case FUTEX_OP_SET:
-		__futex_atomic_op("mr %1,%4\n", ret, oldval, uaddr, oparg);
-		break;
-	case FUTEX_OP_ADD:
-		__futex_atomic_op("add %1,%0,%4\n", ret, oldval, uaddr, oparg);
-		break;
-	case FUTEX_OP_OR:
-		__futex_atomic_op("or %1,%0,%4\n", ret, oldval, uaddr, oparg);
-		break;
-	case FUTEX_OP_ANDN:
-		__futex_atomic_op("andc %1,%0,%4\n", ret, oldval, uaddr, oparg);
-		break;
-	case FUTEX_OP_XOR:
-		__futex_atomic_op("xor %1,%0,%4\n", ret, oldval, uaddr, oparg);
-		break;
-	default:
-		ret = -ENOSYS;
-	}
-
-	pagefault_enable();
-
-	if (!ret) {
-		switch (cmp) {
-		case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
-		case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
-		case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
-		case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
-		case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
-		case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
-		default: ret = -ENOSYS;
-		}
-	}
-	return ret;
-}
-
-static inline int
-futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
-			      u32 oldval, u32 newval)
-{
-	int ret = 0;
-	u32 prev;
-
-	if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
-		return -EFAULT;
-
-        __asm__ __volatile__ (
-        PPC_ATOMIC_ENTRY_BARRIER
-"1:     lwarx   %1,0,%3         # futex_atomic_cmpxchg_inatomic\n\
-        cmpw    0,%1,%4\n\
-        bne-    3f\n"
-        PPC405_ERR77(0,%3)
-"2:     stwcx.  %5,0,%3\n\
-        bne-    1b\n"
-        PPC_ATOMIC_EXIT_BARRIER
-"3:	.section .fixup,\"ax\"\n\
-4:	li	%0,%6\n\
-	b	3b\n\
-	.previous\n\
-	.section __ex_table,\"a\"\n\
-	.align 3\n\
-	" PPC_LONG "1b,4b,2b,4b\n\
-	.previous" \
-        : "+r" (ret), "=&r" (prev), "+m" (*uaddr)
-        : "r" (uaddr), "r" (oldval), "r" (newval), "i" (-EFAULT)
-        : "cc", "memory");
-
-	*uval = prev;
-        return ret;
-}
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_FUTEX_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/gpio.h b/ANDROID_3.4.5/arch/powerpc/include/asm/gpio.h
deleted file mode 100644
index 38762edb..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/gpio.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * Generic GPIO API implementation for PowerPC.
- *
- * Copyright (c) 2007-2008  MontaVista Software, Inc.
- *
- * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef __ASM_POWERPC_GPIO_H
-#define __ASM_POWERPC_GPIO_H
-
-#include <linux/errno.h>
-#include <asm-generic/gpio.h>
-
-#ifdef CONFIG_GPIOLIB
-
-/*
- * We don't (yet) implement inlined/rapid versions for on-chip gpios.
- * Just call gpiolib.
- */
-static inline int gpio_get_value(unsigned int gpio)
-{
-	return __gpio_get_value(gpio);
-}
-
-static inline void gpio_set_value(unsigned int gpio, int value)
-{
-	__gpio_set_value(gpio, value);
-}
-
-static inline int gpio_cansleep(unsigned int gpio)
-{
-	return __gpio_cansleep(gpio);
-}
-
-static inline int gpio_to_irq(unsigned int gpio)
-{
-	return __gpio_to_irq(gpio);
-}
-
-static inline int irq_to_gpio(unsigned int irq)
-{
-	return -EINVAL;
-}
-
-#endif /* CONFIG_GPIOLIB */
-
-#endif /* __ASM_POWERPC_GPIO_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/grackle.h b/ANDROID_3.4.5/arch/powerpc/include/asm/grackle.h
deleted file mode 100644
index bd7812a5..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/grackle.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef _ASM_POWERPC_GRACKLE_H
-#define _ASM_POWERPC_GRACKLE_H
-#ifdef __KERNEL__
-/*
- * Functions for setting up and using a MPC106 northbridge
- */
-
-#include <asm/pci-bridge.h>
-
-extern void setup_grackle(struct pci_controller *hose);
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_GRACKLE_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/hardirq.h b/ANDROID_3.4.5/arch/powerpc/include/asm/hardirq.h
deleted file mode 100644
index 3147a297..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/hardirq.h
+++ /dev/null
@@ -1,29 +0,0 @@
-#ifndef _ASM_POWERPC_HARDIRQ_H
-#define _ASM_POWERPC_HARDIRQ_H
-
-#include <linux/threads.h>
-#include <linux/irq.h>
-
-typedef struct {
-	unsigned int __softirq_pending;
-	unsigned int timer_irqs;
-	unsigned int pmu_irqs;
-	unsigned int mce_exceptions;
-	unsigned int spurious_irqs;
-} ____cacheline_aligned irq_cpustat_t;
-
-DECLARE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
-
-#define __ARCH_IRQ_STAT
-
-#define local_softirq_pending()	__get_cpu_var(irq_stat).__softirq_pending
-
-static inline void ack_bad_irq(unsigned int irq)
-{
-	printk(KERN_CRIT "unexpected IRQ trap at vector %02x\n", irq);
-}
-
-extern u64 arch_irq_stat_cpu(unsigned int cpu);
-#define arch_irq_stat_cpu	arch_irq_stat_cpu
-
-#endif /* _ASM_POWERPC_HARDIRQ_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/heathrow.h b/ANDROID_3.4.5/arch/powerpc/include/asm/heathrow.h
deleted file mode 100644
index 93f54958..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/heathrow.h
+++ /dev/null
@@ -1,67 +0,0 @@
-#ifndef _ASM_POWERPC_HEATHROW_H
-#define _ASM_POWERPC_HEATHROW_H
-#ifdef __KERNEL__
-/*
- * heathrow.h: definitions for using the "Heathrow" I/O controller chip.
- *
- * Grabbed from Open Firmware definitions on a PowerBook G3 Series
- *
- * Copyright (C) 1997 Paul Mackerras.
- */
-
-/* Front light color on Yikes/B&W G3. 32 bits */
-#define HEATHROW_FRONT_LIGHT		0x32 /* (set to 0 or 0xffffffff) */
-
-/* Brightness/contrast (gossamer iMac ?). 8 bits */
-#define HEATHROW_BRIGHTNESS_CNTL	0x32
-#define HEATHROW_CONTRAST_CNTL		0x33
-
-/* offset from ohare base for feature control register */
-#define HEATHROW_MBCR			0x34	/* Media bay control */
-#define HEATHROW_FCR			0x38	/* Feature control */
-#define HEATHROW_AUX_CNTL_REG		0x3c	/* Aux control */
-
-/*
- * Bits in feature control register.
- * Bits postfixed with a _N are in inverse logic
- */
-#define HRW_SCC_TRANS_EN_N	0x00000001	/* Also controls modem power */
-#define HRW_BAY_POWER_N		0x00000002
-#define HRW_BAY_PCI_ENABLE	0x00000004
-#define HRW_BAY_IDE_ENABLE	0x00000008
-#define HRW_BAY_FLOPPY_ENABLE	0x00000010
-#define HRW_IDE0_ENABLE		0x00000020
-#define HRW_IDE0_RESET_N	0x00000040
-#define HRW_BAY_DEV_MASK	0x0000001c
-#define HRW_BAY_RESET_N		0x00000080
-#define HRW_IOBUS_ENABLE	0x00000100	/* Internal IDE ? */
-#define HRW_SCC_ENABLE		0x00000200
-#define HRW_MESH_ENABLE		0x00000400
-#define HRW_SWIM_ENABLE		0x00000800
-#define HRW_SOUND_POWER_N	0x00001000
-#define HRW_SOUND_CLK_ENABLE	0x00002000
-#define HRW_SCCA_IO		0x00004000
-#define HRW_SCCB_IO		0x00008000
-#define HRW_PORT_OR_DESK_VIA_N	0x00010000	/* This one is 0 on PowerBook */
-#define HRW_PWM_MON_ID_N	0x00020000	/* ??? (0) */
-#define HRW_HOOK_MB_CNT_N	0x00040000	/* ??? (0) */
-#define HRW_SWIM_CLONE_FLOPPY	0x00080000	/* ??? (0) */
-#define HRW_AUD_RUN22		0x00100000	/* ??? (1) */
-#define HRW_SCSI_LINK_MODE	0x00200000	/* Read ??? (1) */
-#define HRW_ARB_BYPASS		0x00400000	/* Disable internal PCI arbitrer */
-#define HRW_IDE1_RESET_N	0x00800000	/* Media bay */
-#define HRW_SLOW_SCC_PCLK	0x01000000	/* ??? (0) */
-#define HRW_RESET_SCC		0x02000000
-#define HRW_MFDC_CELL_ENABLE	0x04000000	/* ??? (0) */
-#define HRW_USE_MFDC		0x08000000	/* ??? (0) */
-#define HRW_BMAC_IO_ENABLE	0x60000000	/* two bits, not documented in OF */
-#define HRW_BMAC_RESET		0x80000000	/* not documented in OF */
-
-/* We OR those features at boot on desktop G3s */
-#define HRW_DEFAULTS		(HRW_SCCA_IO | HRW_SCCB_IO | HRW_SCC_ENABLE)
-
-/* Looks like Heathrow has some sort of GPIOs as well... */
-#define HRW_GPIO_MODEM_RESET	0x6d
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_HEATHROW_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/highmem.h b/ANDROID_3.4.5/arch/powerpc/include/asm/highmem.h
deleted file mode 100644
index caaf6e00..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/highmem.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * highmem.h: virtual kernel memory mappings for high memory
- *
- * PowerPC version, stolen from the i386 version.
- *
- * Used in CONFIG_HIGHMEM systems for memory pages which
- * are not addressable by direct kernel virtual addresses.
- *
- * Copyright (C) 1999 Gerhard Wichert, Siemens AG
- *		      Gerhard.Wichert@pdb.siemens.de
- *
- *
- * Redesigned the x86 32-bit VM architecture to deal with
- * up to 16 Terrabyte physical memory. With current x86 CPUs
- * we now support up to 64 Gigabytes physical RAM.
- *
- * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
- */
-
-#ifndef _ASM_HIGHMEM_H
-#define _ASM_HIGHMEM_H
-
-#ifdef __KERNEL__
-
-#include <linux/interrupt.h>
-#include <asm/kmap_types.h>
-#include <asm/tlbflush.h>
-#include <asm/page.h>
-#include <asm/fixmap.h>
-
-extern pte_t *kmap_pte;
-extern pgprot_t kmap_prot;
-extern pte_t *pkmap_page_table;
-
-/*
- * Right now we initialize only a single pte table. It can be extended
- * easily, subsequent pte tables have to be allocated in one physical
- * chunk of RAM.
- */
-/*
- * We use one full pte table with 4K pages. And with 16K/64K/256K pages pte
- * table covers enough memory (32MB/512MB/2GB resp.), so that both FIXMAP
- * and PKMAP can be placed in a single pte table. We use 512 pages for PKMAP
- * in case of 16K/64K/256K page sizes.
- */
-#ifdef CONFIG_PPC_4K_PAGES
-#define PKMAP_ORDER	PTE_SHIFT
-#else
-#define PKMAP_ORDER	9
-#endif
-#define LAST_PKMAP	(1 << PKMAP_ORDER)
-#ifndef CONFIG_PPC_4K_PAGES
-#define PKMAP_BASE	(FIXADDR_START - PAGE_SIZE*(LAST_PKMAP + 1))
-#else
-#define PKMAP_BASE	((FIXADDR_START - PAGE_SIZE*(LAST_PKMAP + 1)) & PMD_MASK)
-#endif
-#define LAST_PKMAP_MASK	(LAST_PKMAP-1)
-#define PKMAP_NR(virt)  ((virt-PKMAP_BASE) >> PAGE_SHIFT)
-#define PKMAP_ADDR(nr)  (PKMAP_BASE + ((nr) << PAGE_SHIFT))
-
-extern void *kmap_high(struct page *page);
-extern void kunmap_high(struct page *page);
-extern void *kmap_atomic_prot(struct page *page, pgprot_t prot);
-extern void __kunmap_atomic(void *kvaddr);
-
-static inline void *kmap(struct page *page)
-{
-	might_sleep();
-	if (!PageHighMem(page))
-		return page_address(page);
-	return kmap_high(page);
-}
-
-static inline void kunmap(struct page *page)
-{
-	BUG_ON(in_interrupt());
-	if (!PageHighMem(page))
-		return;
-	kunmap_high(page);
-}
-
-static inline void *kmap_atomic(struct page *page)
-{
-	return kmap_atomic_prot(page, kmap_prot);
-}
-
-static inline struct page *kmap_atomic_to_page(void *ptr)
-{
-	unsigned long idx, vaddr = (unsigned long) ptr;
-	pte_t *pte;
-
-	if (vaddr < FIXADDR_START)
-		return virt_to_page(ptr);
-
-	idx = virt_to_fix(vaddr);
-	pte = kmap_pte - (idx - FIX_KMAP_BEGIN);
-	return pte_page(*pte);
-}
-
-
-#define flush_cache_kmaps()	flush_cache_all()
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_HIGHMEM_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/hugetlb.h b/ANDROID_3.4.5/arch/powerpc/include/asm/hugetlb.h
deleted file mode 100644
index dfdb95bc..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/hugetlb.h
+++ /dev/null
@@ -1,175 +0,0 @@
-#ifndef _ASM_POWERPC_HUGETLB_H
-#define _ASM_POWERPC_HUGETLB_H
-
-#ifdef CONFIG_HUGETLB_PAGE
-#include <asm/page.h>
-
-extern struct kmem_cache *hugepte_cache;
-
-static inline pte_t *hugepd_page(hugepd_t hpd)
-{
-	BUG_ON(!hugepd_ok(hpd));
-	return (pte_t *)((hpd.pd & ~HUGEPD_SHIFT_MASK) | PD_HUGE);
-}
-
-static inline unsigned int hugepd_shift(hugepd_t hpd)
-{
-	return hpd.pd & HUGEPD_SHIFT_MASK;
-}
-
-static inline pte_t *hugepte_offset(hugepd_t *hpdp, unsigned long addr,
-				    unsigned pdshift)
-{
-	/*
-	 * On FSL BookE, we have multiple higher-level table entries that
-	 * point to the same hugepte.  Just use the first one since they're all
-	 * identical.  So for that case, idx=0.
-	 */
-	unsigned long idx = 0;
-
-	pte_t *dir = hugepd_page(*hpdp);
-#ifndef CONFIG_PPC_FSL_BOOK3E
-	idx = (addr & ((1UL << pdshift) - 1)) >> hugepd_shift(*hpdp);
-#endif
-
-	return dir + idx;
-}
-
-pte_t *huge_pte_offset_and_shift(struct mm_struct *mm,
-				 unsigned long addr, unsigned *shift);
-
-void flush_dcache_icache_hugepage(struct page *page);
-
-#if defined(CONFIG_PPC_MM_SLICES) || defined(CONFIG_PPC_SUBPAGE_PROT)
-int is_hugepage_only_range(struct mm_struct *mm, unsigned long addr,
-			   unsigned long len);
-#else
-static inline int is_hugepage_only_range(struct mm_struct *mm,
-					 unsigned long addr,
-					 unsigned long len)
-{
-	return 0;
-}
-#endif
-
-void book3e_hugetlb_preload(struct vm_area_struct *vma, unsigned long ea,
-			    pte_t pte);
-void flush_hugetlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
-
-void hugetlb_free_pgd_range(struct mmu_gather *tlb, unsigned long addr,
-			    unsigned long end, unsigned long floor,
-			    unsigned long ceiling);
-
-/*
- * The version of vma_mmu_pagesize() in arch/powerpc/mm/hugetlbpage.c needs
- * to override the version in mm/hugetlb.c
- */
-#define vma_mmu_pagesize vma_mmu_pagesize
-
-/*
- * If the arch doesn't supply something else, assume that hugepage
- * size aligned regions are ok without further preparation.
- */
-static inline int prepare_hugepage_range(struct file *file,
-			unsigned long addr, unsigned long len)
-{
-	struct hstate *h = hstate_file(file);
-	if (len & ~huge_page_mask(h))
-		return -EINVAL;
-	if (addr & ~huge_page_mask(h))
-		return -EINVAL;
-	return 0;
-}
-
-static inline void hugetlb_prefault_arch_hook(struct mm_struct *mm)
-{
-}
-
-
-static inline void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
-				   pte_t *ptep, pte_t pte)
-{
-	set_pte_at(mm, addr, ptep, pte);
-}
-
-static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
-					    unsigned long addr, pte_t *ptep)
-{
-#ifdef CONFIG_PPC64
-	return __pte(pte_update(mm, addr, ptep, ~0UL, 1));
-#else
-	return __pte(pte_update(ptep, ~0UL, 0));
-#endif
-}
-
-static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
-					 unsigned long addr, pte_t *ptep)
-{
-	pte_t pte;
-	pte = huge_ptep_get_and_clear(vma->vm_mm, addr, ptep);
-	flush_tlb_page(vma, addr);
-}
-
-static inline int huge_pte_none(pte_t pte)
-{
-	return pte_none(pte);
-}
-
-static inline pte_t huge_pte_wrprotect(pte_t pte)
-{
-	return pte_wrprotect(pte);
-}
-
-static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
-					     unsigned long addr, pte_t *ptep,
-					     pte_t pte, int dirty)
-{
-#ifdef HUGETLB_NEED_PRELOAD
-	/*
-	 * The "return 1" forces a call of update_mmu_cache, which will write a
-	 * TLB entry.  Without this, platforms that don't do a write of the TLB
-	 * entry in the TLB miss handler asm will fault ad infinitum.
-	 */
-	ptep_set_access_flags(vma, addr, ptep, pte, dirty);
-	return 1;
-#else
-	return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
-#endif
-}
-
-static inline pte_t huge_ptep_get(pte_t *ptep)
-{
-	return *ptep;
-}
-
-static inline int arch_prepare_hugepage(struct page *page)
-{
-	return 0;
-}
-
-static inline void arch_release_hugepage(struct page *page)
-{
-}
-
-#else /* ! CONFIG_HUGETLB_PAGE */
-static inline void flush_hugetlb_page(struct vm_area_struct *vma,
-				      unsigned long vmaddr)
-{
-}
-#endif /* CONFIG_HUGETLB_PAGE */
-
-
-/*
- * FSL Book3E platforms require special gpage handling - the gpages
- * are reserved early in the boot process by memblock instead of via
- * the .dts as on IBM platforms.
- */
-#if defined(CONFIG_HUGETLB_PAGE) && defined(CONFIG_PPC_FSL_BOOK3E)
-extern void __init reserve_hugetlb_gpages(void);
-#else
-static inline void reserve_hugetlb_gpages(void)
-{
-}
-#endif
-
-#endif /* _ASM_POWERPC_HUGETLB_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/hvcall.h b/ANDROID_3.4.5/arch/powerpc/include/asm/hvcall.h
deleted file mode 100644
index 1c324ff5..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/hvcall.h
+++ /dev/null
@@ -1,355 +0,0 @@
-#ifndef _ASM_POWERPC_HVCALL_H
-#define _ASM_POWERPC_HVCALL_H
-#ifdef __KERNEL__
-
-#define HVSC			.long 0x44000022
-
-#define H_SUCCESS	0
-#define H_BUSY		1	/* Hardware busy -- retry later */
-#define H_CLOSED	2	/* Resource closed */
-#define H_NOT_AVAILABLE 3
-#define H_CONSTRAINED	4	/* Resource request constrained to max allowed */
-#define H_PARTIAL       5
-#define H_IN_PROGRESS	14	/* Kind of like busy */
-#define H_PAGE_REGISTERED 15
-#define H_PARTIAL_STORE   16
-#define H_PENDING	17	/* returned from H_POLL_PENDING */
-#define H_CONTINUE	18	/* Returned from H_Join on success */
-#define H_LONG_BUSY_START_RANGE		9900  /* Start of long busy range */
-#define H_LONG_BUSY_ORDER_1_MSEC	9900  /* Long busy, hint that 1msec \
-						 is a good time to retry */
-#define H_LONG_BUSY_ORDER_10_MSEC	9901  /* Long busy, hint that 10msec \
-						 is a good time to retry */
-#define H_LONG_BUSY_ORDER_100_MSEC 	9902  /* Long busy, hint that 100msec \
-						 is a good time to retry */
-#define H_LONG_BUSY_ORDER_1_SEC		9903  /* Long busy, hint that 1sec \
-						 is a good time to retry */
-#define H_LONG_BUSY_ORDER_10_SEC	9904  /* Long busy, hint that 10sec \
-						 is a good time to retry */
-#define H_LONG_BUSY_ORDER_100_SEC	9905  /* Long busy, hint that 100sec \
-						 is a good time to retry */
-#define H_LONG_BUSY_END_RANGE		9905  /* End of long busy range */
-
-/* Internal value used in book3s_hv kvm support; not returned to guests */
-#define H_TOO_HARD	9999
-
-#define H_HARDWARE	-1	/* Hardware error */
-#define H_FUNCTION	-2	/* Function not supported */
-#define H_PRIVILEGE	-3	/* Caller not privileged */
-#define H_PARAMETER	-4	/* Parameter invalid, out-of-range or conflicting */
-#define H_BAD_MODE	-5	/* Illegal msr value */
-#define H_PTEG_FULL	-6	/* PTEG is full */
-#define H_NOT_FOUND	-7	/* PTE was not found" */
-#define H_RESERVED_DABR	-8	/* DABR address is reserved by the hypervisor on this processor" */
-#define H_NO_MEM	-9
-#define H_AUTHORITY	-10
-#define H_PERMISSION	-11
-#define H_DROPPED	-12
-#define H_SOURCE_PARM	-13
-#define H_DEST_PARM	-14
-#define H_REMOTE_PARM	-15
-#define H_RESOURCE	-16
-#define H_ADAPTER_PARM  -17
-#define H_RH_PARM       -18
-#define H_RCQ_PARM      -19
-#define H_SCQ_PARM      -20
-#define H_EQ_PARM       -21
-#define H_RT_PARM       -22
-#define H_ST_PARM       -23
-#define H_SIGT_PARM     -24
-#define H_TOKEN_PARM    -25
-#define H_MLENGTH_PARM  -27
-#define H_MEM_PARM      -28
-#define H_MEM_ACCESS_PARM -29
-#define H_ATTR_PARM     -30
-#define H_PORT_PARM     -31
-#define H_MCG_PARM      -32
-#define H_VL_PARM       -33
-#define H_TSIZE_PARM    -34
-#define H_TRACE_PARM    -35
-
-#define H_MASK_PARM     -37
-#define H_MCG_FULL      -38
-#define H_ALIAS_EXIST   -39
-#define H_P_COUNTER     -40
-#define H_TABLE_FULL    -41
-#define H_ALT_TABLE     -42
-#define H_MR_CONDITION  -43
-#define H_NOT_ENOUGH_RESOURCES -44
-#define H_R_STATE       -45
-#define H_RESCINDEND    -46
-#define H_MULTI_THREADS_ACTIVE -9005
-
-
-/* Long Busy is a condition that can be returned by the firmware
- * when a call cannot be completed now, but the identical call
- * should be retried later.  This prevents calls blocking in the
- * firmware for long periods of time.  Annoyingly the firmware can return
- * a range of return codes, hinting at how long we should wait before
- * retrying.  If you don't care for the hint, the macro below is a good
- * way to check for the long_busy return codes
- */
-#define H_IS_LONG_BUSY(x)  ((x >= H_LONG_BUSY_START_RANGE) \
-			     && (x <= H_LONG_BUSY_END_RANGE))
-
-/* Flags */
-#define H_LARGE_PAGE		(1UL<<(63-16))
-#define H_EXACT			(1UL<<(63-24))	/* Use exact PTE or return H_PTEG_FULL */
-#define H_R_XLATE		(1UL<<(63-25))	/* include a valid logical page num in the pte if the valid bit is set */
-#define H_READ_4		(1UL<<(63-26))	/* Return 4 PTEs */
-#define H_PAGE_STATE_CHANGE	(1UL<<(63-28))
-#define H_PAGE_UNUSED		((1UL<<(63-29)) | (1UL<<(63-30)))
-#define H_PAGE_SET_UNUSED	(H_PAGE_STATE_CHANGE | H_PAGE_UNUSED)
-#define H_PAGE_SET_LOANED	(H_PAGE_SET_UNUSED | (1UL<<(63-31)))
-#define H_PAGE_SET_ACTIVE	H_PAGE_STATE_CHANGE
-#define H_AVPN			(1UL<<(63-32))	/* An avpn is provided as a sanity test */
-#define H_ANDCOND		(1UL<<(63-33))
-#define H_LOCAL			(1UL<<(63-35))
-#define H_ICACHE_INVALIDATE	(1UL<<(63-40))	/* icbi, etc.  (ignored for IO pages) */
-#define H_ICACHE_SYNCHRONIZE	(1UL<<(63-41))	/* dcbst, icbi, etc (ignored for IO pages */
-#define H_COALESCE_CAND	(1UL<<(63-42))	/* page is a good candidate for coalescing */
-#define H_ZERO_PAGE		(1UL<<(63-48))	/* zero the page before mapping (ignored for IO pages) */
-#define H_COPY_PAGE		(1UL<<(63-49))
-#define H_N			(1UL<<(63-61))
-#define H_PP1			(1UL<<(63-62))
-#define H_PP2			(1UL<<(63-63))
-
-/* VASI States */
-#define H_VASI_INVALID          0
-#define H_VASI_ENABLED          1
-#define H_VASI_ABORTED          2
-#define H_VASI_SUSPENDING       3
-#define H_VASI_SUSPENDED        4
-#define H_VASI_RESUMED          5
-#define H_VASI_COMPLETED        6
-
-/* DABRX flags */
-#define H_DABRX_HYPERVISOR	(1UL<<(63-61))
-#define H_DABRX_KERNEL		(1UL<<(63-62))
-#define H_DABRX_USER		(1UL<<(63-63))
-
-/* Each control block has to be on a 4K boundary */
-#define H_CB_ALIGNMENT          4096
-
-/* pSeries hypervisor opcodes */
-#define H_REMOVE		0x04
-#define H_ENTER			0x08
-#define H_READ			0x0c
-#define H_CLEAR_MOD		0x10
-#define H_CLEAR_REF		0x14
-#define H_PROTECT		0x18
-#define H_GET_TCE		0x1c
-#define H_PUT_TCE		0x20
-#define H_SET_SPRG0		0x24
-#define H_SET_DABR		0x28
-#define H_PAGE_INIT		0x2c
-#define H_SET_ASR		0x30
-#define H_ASR_ON		0x34
-#define H_ASR_OFF		0x38
-#define H_LOGICAL_CI_LOAD	0x3c
-#define H_LOGICAL_CI_STORE	0x40
-#define H_LOGICAL_CACHE_LOAD	0x44
-#define H_LOGICAL_CACHE_STORE	0x48
-#define H_LOGICAL_ICBI		0x4c
-#define H_LOGICAL_DCBF		0x50
-#define H_GET_TERM_CHAR		0x54
-#define H_PUT_TERM_CHAR		0x58
-#define H_REAL_TO_LOGICAL	0x5c
-#define H_HYPERVISOR_DATA	0x60
-#define H_EOI			0x64
-#define H_CPPR			0x68
-#define H_IPI			0x6c
-#define H_IPOLL			0x70
-#define H_XIRR			0x74
-#define H_PERFMON		0x7c
-#define H_MIGRATE_DMA		0x78
-#define H_REGISTER_VPA		0xDC
-#define H_CEDE			0xE0
-#define H_CONFER		0xE4
-#define H_PROD			0xE8
-#define H_GET_PPP		0xEC
-#define H_SET_PPP		0xF0
-#define H_PURR			0xF4
-#define H_PIC			0xF8
-#define H_REG_CRQ		0xFC
-#define H_FREE_CRQ		0x100
-#define H_VIO_SIGNAL		0x104
-#define H_SEND_CRQ		0x108
-#define H_COPY_RDMA		0x110
-#define H_REGISTER_LOGICAL_LAN	0x114
-#define H_FREE_LOGICAL_LAN	0x118
-#define H_ADD_LOGICAL_LAN_BUFFER 0x11C
-#define H_SEND_LOGICAL_LAN	0x120
-#define H_BULK_REMOVE		0x124
-#define H_MULTICAST_CTRL	0x130
-#define H_SET_XDABR		0x134
-#define H_STUFF_TCE		0x138
-#define H_PUT_TCE_INDIRECT	0x13C
-#define H_CHANGE_LOGICAL_LAN_MAC 0x14C
-#define H_VTERM_PARTNER_INFO	0x150
-#define H_REGISTER_VTERM	0x154
-#define H_FREE_VTERM		0x158
-#define H_RESET_EVENTS          0x15C
-#define H_ALLOC_RESOURCE        0x160
-#define H_FREE_RESOURCE         0x164
-#define H_MODIFY_QP             0x168
-#define H_QUERY_QP              0x16C
-#define H_REREGISTER_PMR        0x170
-#define H_REGISTER_SMR          0x174
-#define H_QUERY_MR              0x178
-#define H_QUERY_MW              0x17C
-#define H_QUERY_HCA             0x180
-#define H_QUERY_PORT            0x184
-#define H_MODIFY_PORT           0x188
-#define H_DEFINE_AQP1           0x18C
-#define H_GET_TRACE_BUFFER      0x190
-#define H_DEFINE_AQP0           0x194
-#define H_RESIZE_MR             0x198
-#define H_ATTACH_MCQP           0x19C
-#define H_DETACH_MCQP           0x1A0
-#define H_CREATE_RPT            0x1A4
-#define H_REMOVE_RPT            0x1A8
-#define H_REGISTER_RPAGES       0x1AC
-#define H_DISABLE_AND_GETC      0x1B0
-#define H_ERROR_DATA            0x1B4
-#define H_GET_HCA_INFO          0x1B8
-#define H_GET_PERF_COUNT        0x1BC
-#define H_MANAGE_TRACE          0x1C0
-#define H_FREE_LOGICAL_LAN_BUFFER 0x1D4
-#define H_QUERY_INT_STATE       0x1E4
-#define H_POLL_PENDING		0x1D8
-#define H_ILLAN_ATTRIBUTES	0x244
-#define H_MODIFY_HEA_QP		0x250
-#define H_QUERY_HEA_QP		0x254
-#define H_QUERY_HEA		0x258
-#define H_QUERY_HEA_PORT	0x25C
-#define H_MODIFY_HEA_PORT	0x260
-#define H_REG_BCMC		0x264
-#define H_DEREG_BCMC		0x268
-#define H_REGISTER_HEA_RPAGES	0x26C
-#define H_DISABLE_AND_GET_HEA	0x270
-#define H_GET_HEA_INFO		0x274
-#define H_ALLOC_HEA_RESOURCE	0x278
-#define H_ADD_CONN		0x284
-#define H_DEL_CONN		0x288
-#define H_JOIN			0x298
-#define H_VASI_STATE            0x2A4
-#define H_ENABLE_CRQ		0x2B0
-#define H_GET_EM_PARMS		0x2B8
-#define H_SET_MPP		0x2D0
-#define H_GET_MPP		0x2D4
-#define H_HOME_NODE_ASSOCIATIVITY 0x2EC
-#define H_BEST_ENERGY		0x2F4
-#define H_GET_MPP_X		0x314
-#define MAX_HCALL_OPCODE	H_GET_MPP_X
-
-#ifndef __ASSEMBLY__
-
-/**
- * plpar_hcall_norets: - Make a pseries hypervisor call with no return arguments
- * @opcode: The hypervisor call to make.
- *
- * This call supports up to 7 arguments and only returns the status of
- * the hcall. Use this version where possible, its slightly faster than
- * the other plpar_hcalls.
- */
-long plpar_hcall_norets(unsigned long opcode, ...);
-
-/**
- * plpar_hcall: - Make a pseries hypervisor call
- * @opcode: The hypervisor call to make.
- * @retbuf: Buffer to store up to 4 return arguments in.
- *
- * This call supports up to 6 arguments and 4 return arguments. Use
- * PLPAR_HCALL_BUFSIZE to size the return argument buffer.
- *
- * Used for all but the craziest of phyp interfaces (see plpar_hcall9)
- */
-#define PLPAR_HCALL_BUFSIZE 4
-long plpar_hcall(unsigned long opcode, unsigned long *retbuf, ...);
-
-/**
- * plpar_hcall_raw: - Make a hypervisor call without calculating hcall stats
- * @opcode: The hypervisor call to make.
- * @retbuf: Buffer to store up to 4 return arguments in.
- *
- * This call supports up to 6 arguments and 4 return arguments. Use
- * PLPAR_HCALL_BUFSIZE to size the return argument buffer.
- *
- * Used when phyp interface needs to be called in real mode. Similar to
- * plpar_hcall, but plpar_hcall_raw works in real mode and does not
- * calculate hypervisor call statistics.
- */
-long plpar_hcall_raw(unsigned long opcode, unsigned long *retbuf, ...);
-
-/**
- * plpar_hcall9: - Make a pseries hypervisor call with up to 9 return arguments
- * @opcode: The hypervisor call to make.
- * @retbuf: Buffer to store up to 9 return arguments in.
- *
- * This call supports up to 9 arguments and 9 return arguments. Use
- * PLPAR_HCALL9_BUFSIZE to size the return argument buffer.
- */
-#define PLPAR_HCALL9_BUFSIZE 9
-long plpar_hcall9(unsigned long opcode, unsigned long *retbuf, ...);
-long plpar_hcall9_raw(unsigned long opcode, unsigned long *retbuf, ...);
-
-/* For hcall instrumentation.  One structure per-hcall, per-CPU */
-struct hcall_stats {
-	unsigned long	num_calls;	/* number of calls (on this CPU) */
-	unsigned long	tb_total;	/* total wall time (mftb) of calls. */
-	unsigned long	purr_total;	/* total cpu time (PURR) of calls. */
-	unsigned long	tb_start;
-	unsigned long	purr_start;
-};
-#define HCALL_STAT_ARRAY_SIZE	((MAX_HCALL_OPCODE >> 2) + 1)
-
-struct hvcall_mpp_data {
-	unsigned long entitled_mem;
-	unsigned long mapped_mem;
-	unsigned short group_num;
-	unsigned short pool_num;
-	unsigned char mem_weight;
-	unsigned char unallocated_mem_weight;
-	unsigned long unallocated_entitlement;  /* value in bytes */
-	unsigned long pool_size;
-	signed long loan_request;
-	unsigned long backing_mem;
-};
-
-int h_get_mpp(struct hvcall_mpp_data *);
-
-struct hvcall_mpp_x_data {
-	unsigned long coalesced_bytes;
-	unsigned long pool_coalesced_bytes;
-	unsigned long pool_purr_cycles;
-	unsigned long pool_spurr_cycles;
-	unsigned long reserved[3];
-};
-
-int h_get_mpp_x(struct hvcall_mpp_x_data *mpp_x_data);
-
-#ifdef CONFIG_PPC_PSERIES
-extern int CMO_PrPSP;
-extern int CMO_SecPSP;
-extern unsigned long CMO_PageSize;
-
-static inline int cmo_get_primary_psp(void)
-{
-	return CMO_PrPSP;
-}
-
-static inline int cmo_get_secondary_psp(void)
-{
-	return CMO_SecPSP;
-}
-
-static inline unsigned long cmo_get_page_size(void)
-{
-	return CMO_PageSize;
-}
-#endif /* CONFIG_PPC_PSERIES */
-
-#endif /* __ASSEMBLY__ */
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_HVCALL_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/hvconsole.h b/ANDROID_3.4.5/arch/powerpc/include/asm/hvconsole.h
deleted file mode 100644
index 35ea69e8..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/hvconsole.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * hvconsole.h
- * Copyright (C) 2004 Ryan S Arnold, IBM Corporation
- *
- * LPAR console support.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-
-#ifndef _PPC64_HVCONSOLE_H
-#define _PPC64_HVCONSOLE_H
-#ifdef __KERNEL__
-
-/*
- * PSeries firmware will only send/recv up to 16 bytes of character data per
- * hcall.
- */
-#define MAX_VIO_PUT_CHARS	16
-#define SIZE_VIO_GET_CHARS	16
-
-/*
- * Vio firmware always attempts to fetch MAX_VIO_GET_CHARS chars.  The 'count'
- * parm is included to conform to put_chars() function pointer template
- */
-extern int hvc_get_chars(uint32_t vtermno, char *buf, int count);
-extern int hvc_put_chars(uint32_t vtermno, const char *buf, int count);
-
-#endif /* __KERNEL__ */
-#endif /* _PPC64_HVCONSOLE_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/hvcserver.h b/ANDROID_3.4.5/arch/powerpc/include/asm/hvcserver.h
deleted file mode 100644
index 67d7da3a..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/hvcserver.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * hvcserver.h
- * Copyright (C) 2004 Ryan S Arnold, IBM Corporation
- *
- * PPC64 virtual I/O console server support.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-
-#ifndef _PPC64_HVCSERVER_H
-#define _PPC64_HVCSERVER_H
-#ifdef __KERNEL__
-
-#include <linux/list.h>
-
-/* Converged Location Code length */
-#define HVCS_CLC_LENGTH	79
-
-/**
- * hvcs_partner_info - an element in a list of partner info
- * @node: list_head denoting this partner_info struct's position in the list of
- *	partner info.
- * @unit_address: The partner unit address of this entry.
- * @partition_ID: The partner partition ID of this entry.
- * @location_code: The converged location code of this entry + 1 char for the
- *	null-term.
- *
- * This structure outlines the format that partner info is presented to a caller
- * of the hvcs partner info fetching functions.  These are strung together into
- * a list using linux kernel lists.
- */
-struct hvcs_partner_info {
-	struct list_head node;
-	uint32_t unit_address;
-	uint32_t partition_ID;
-	char location_code[HVCS_CLC_LENGTH + 1]; /* CLC + 1 null-term char */
-};
-
-extern int hvcs_free_partner_info(struct list_head *head);
-extern int hvcs_get_partner_info(uint32_t unit_address,
-		struct list_head *head, unsigned long *pi_buff);
-extern int hvcs_register_connection(uint32_t unit_address,
-		uint32_t p_partition_ID, uint32_t p_unit_address);
-extern int hvcs_free_connection(uint32_t unit_address);
-
-#endif /* __KERNEL__ */
-#endif /* _PPC64_HVCSERVER_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/hvsi.h b/ANDROID_3.4.5/arch/powerpc/include/asm/hvsi.h
deleted file mode 100644
index d3f64f36..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/hvsi.h
+++ /dev/null
@@ -1,94 +0,0 @@
-#ifndef _HVSI_H
-#define _HVSI_H
-
-#define VS_DATA_PACKET_HEADER           0xff
-#define VS_CONTROL_PACKET_HEADER        0xfe
-#define VS_QUERY_PACKET_HEADER          0xfd
-#define VS_QUERY_RESPONSE_PACKET_HEADER 0xfc
-
-/* control verbs */
-#define VSV_SET_MODEM_CTL    1 /* to service processor only */
-#define VSV_MODEM_CTL_UPDATE 2 /* from service processor only */
-#define VSV_CLOSE_PROTOCOL   3
-
-/* query verbs */
-#define VSV_SEND_VERSION_NUMBER 1
-#define VSV_SEND_MODEM_CTL_STATUS 2
-
-/* yes, these masks are not consecutive. */
-#define HVSI_TSDTR 0x01
-#define HVSI_TSCD  0x20
-
-#define HVSI_MAX_OUTGOING_DATA 12
-#define HVSI_VERSION 1
-
-struct hvsi_header {
-	uint8_t  type;
-	uint8_t  len;
-	uint16_t seqno;
-} __attribute__((packed));
-
-struct hvsi_data {
-	struct hvsi_header hdr;
-	uint8_t  data[HVSI_MAX_OUTGOING_DATA];
-} __attribute__((packed));
-
-struct hvsi_control {
-	struct hvsi_header hdr;
-	uint16_t verb;
-	/* optional depending on verb: */
-	uint32_t word;
-	uint32_t mask;
-} __attribute__((packed));
-
-struct hvsi_query {
-	struct hvsi_header hdr;
-	uint16_t verb;
-} __attribute__((packed));
-
-struct hvsi_query_response {
-	struct hvsi_header hdr;
-	uint16_t verb;
-	uint16_t query_seqno;
-	union {
-		uint8_t  version;
-		uint32_t mctrl_word;
-	} u;
-} __attribute__((packed));
-
-/* hvsi lib struct definitions */
-#define HVSI_INBUF_SIZE		255
-struct tty_struct;
-struct hvsi_priv {
-	unsigned int	inbuf_len;	/* data in input buffer */
-	unsigned char	inbuf[HVSI_INBUF_SIZE];
-	unsigned int	inbuf_cur;	/* Cursor in input buffer */
-	unsigned int	inbuf_pktlen;	/* packet lenght from cursor */
-	atomic_t	seqno;		/* packet sequence number */
-	unsigned int	opened:1;	/* driver opened */
-	unsigned int	established:1;	/* protocol established */
-	unsigned int 	is_console:1;	/* used as a kernel console device */
-	unsigned int	mctrl_update:1;	/* modem control updated */
-	unsigned short	mctrl;		/* modem control */
-	struct tty_struct *tty;		/* tty structure */
-	int (*get_chars)(uint32_t termno, char *buf, int count);
-	int (*put_chars)(uint32_t termno, const char *buf, int count);
-	uint32_t	termno;
-};
-
-/* hvsi lib functions */
-struct hvc_struct;
-extern void hvsilib_init(struct hvsi_priv *pv,
-			 int (*get_chars)(uint32_t termno, char *buf, int count),
-			 int (*put_chars)(uint32_t termno, const char *buf,
-					  int count),
-			 int termno, int is_console);
-extern int hvsilib_open(struct hvsi_priv *pv, struct hvc_struct *hp);
-extern void hvsilib_close(struct hvsi_priv *pv, struct hvc_struct *hp);
-extern int hvsilib_read_mctrl(struct hvsi_priv *pv);
-extern int hvsilib_write_mctrl(struct hvsi_priv *pv, int dtr);
-extern void hvsilib_establish(struct hvsi_priv *pv);
-extern int hvsilib_get_chars(struct hvsi_priv *pv, char *buf, int count);
-extern int hvsilib_put_chars(struct hvsi_priv *pv, const char *buf, int count);
-
-#endif /* _HVSI_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/hw_breakpoint.h b/ANDROID_3.4.5/arch/powerpc/include/asm/hw_breakpoint.h
deleted file mode 100644
index be04330a..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/hw_breakpoint.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * PowerPC BookIII S hardware breakpoint definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Copyright 2010, IBM Corporation.
- * Author: K.Prasad <prasad@linux.vnet.ibm.com>
- *
- */
-
-#ifndef _PPC_BOOK3S_64_HW_BREAKPOINT_H
-#define _PPC_BOOK3S_64_HW_BREAKPOINT_H
-
-#ifdef	__KERNEL__
-#ifdef CONFIG_HAVE_HW_BREAKPOINT
-
-struct arch_hw_breakpoint {
-	bool		extraneous_interrupt;
-	u8		len; /* length of the target data symbol */
-	int		type;
-	unsigned long	address;
-};
-
-#include <linux/kdebug.h>
-#include <asm/reg.h>
-#include <asm/debug.h>
-
-struct perf_event;
-struct pmu;
-struct perf_sample_data;
-
-#define HW_BREAKPOINT_ALIGN 0x7
-/* Maximum permissible length of any HW Breakpoint */
-#define HW_BREAKPOINT_LEN 0x8
-
-extern int hw_breakpoint_slots(int type);
-extern int arch_bp_generic_fields(int type, int *gen_bp_type);
-extern int arch_check_bp_in_kernelspace(struct perf_event *bp);
-extern int arch_validate_hwbkpt_settings(struct perf_event *bp);
-extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
-						unsigned long val, void *data);
-int arch_install_hw_breakpoint(struct perf_event *bp);
-void arch_uninstall_hw_breakpoint(struct perf_event *bp);
-void hw_breakpoint_pmu_read(struct perf_event *bp);
-extern void flush_ptrace_hw_breakpoint(struct task_struct *tsk);
-
-extern struct pmu perf_ops_bp;
-extern void ptrace_triggered(struct perf_event *bp,
-			struct perf_sample_data *data, struct pt_regs *regs);
-static inline void hw_breakpoint_disable(void)
-{
-	set_dabr(0);
-}
-extern void thread_change_pc(struct task_struct *tsk, struct pt_regs *regs);
-
-#else	/* CONFIG_HAVE_HW_BREAKPOINT */
-static inline void hw_breakpoint_disable(void) { }
-static inline void thread_change_pc(struct task_struct *tsk,
-					struct pt_regs *regs) { }
-#endif	/* CONFIG_HAVE_HW_BREAKPOINT */
-#endif	/* __KERNEL__ */
-#endif	/* _PPC_BOOK3S_64_HW_BREAKPOINT_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/hw_irq.h b/ANDROID_3.4.5/arch/powerpc/include/asm/hw_irq.h
deleted file mode 100644
index 907e9fdd..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/hw_irq.h
+++ /dev/null
@@ -1,208 +0,0 @@
-/*
- * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
- */
-#ifndef _ASM_POWERPC_HW_IRQ_H
-#define _ASM_POWERPC_HW_IRQ_H
-
-#ifdef __KERNEL__
-
-#include <linux/errno.h>
-#include <linux/compiler.h>
-#include <asm/ptrace.h>
-#include <asm/processor.h>
-
-#ifdef CONFIG_PPC64
-
-/*
- * PACA flags in paca->irq_happened.
- *
- * This bits are set when interrupts occur while soft-disabled
- * and allow a proper replay. Additionally, PACA_IRQ_HARD_DIS
- * is set whenever we manually hard disable.
- */
-#define PACA_IRQ_HARD_DIS	0x01
-#define PACA_IRQ_DBELL		0x02
-#define PACA_IRQ_EE		0x04
-#define PACA_IRQ_DEC		0x08 /* Or FIT */
-#define PACA_IRQ_EE_EDGE	0x10 /* BookE only */
-
-#endif /* CONFIG_PPC64 */
-
-#ifndef __ASSEMBLY__
-
-extern void __replay_interrupt(unsigned int vector);
-
-extern void timer_interrupt(struct pt_regs *);
-
-#ifdef CONFIG_PPC64
-#include <asm/paca.h>
-
-static inline unsigned long arch_local_save_flags(void)
-{
-	unsigned long flags;
-
-	asm volatile(
-		"lbz %0,%1(13)"
-		: "=r" (flags)
-		: "i" (offsetof(struct paca_struct, soft_enabled)));
-
-	return flags;
-}
-
-static inline unsigned long arch_local_irq_disable(void)
-{
-	unsigned long flags, zero;
-
-	asm volatile(
-		"li %1,0; lbz %0,%2(13); stb %1,%2(13)"
-		: "=r" (flags), "=&r" (zero)
-		: "i" (offsetof(struct paca_struct, soft_enabled))
-		: "memory");
-
-	return flags;
-}
-
-extern void arch_local_irq_restore(unsigned long);
-
-static inline void arch_local_irq_enable(void)
-{
-	arch_local_irq_restore(1);
-}
-
-static inline unsigned long arch_local_irq_save(void)
-{
-	return arch_local_irq_disable();
-}
-
-static inline bool arch_irqs_disabled_flags(unsigned long flags)
-{
-	return flags == 0;
-}
-
-static inline bool arch_irqs_disabled(void)
-{
-	return arch_irqs_disabled_flags(arch_local_save_flags());
-}
-
-#ifdef CONFIG_PPC_BOOK3E
-#define __hard_irq_enable()	asm volatile("wrteei 1" : : : "memory")
-#define __hard_irq_disable()	asm volatile("wrteei 0" : : : "memory")
-#else
-#define __hard_irq_enable()	__mtmsrd(local_paca->kernel_msr | MSR_EE, 1)
-#define __hard_irq_disable()	__mtmsrd(local_paca->kernel_msr, 1)
-#endif
-
-static inline void hard_irq_disable(void)
-{
-	__hard_irq_disable();
-	get_paca()->soft_enabled = 0;
-	get_paca()->irq_happened |= PACA_IRQ_HARD_DIS;
-}
-
-/* include/linux/interrupt.h needs hard_irq_disable to be a macro */
-#define hard_irq_disable	hard_irq_disable
-
-static inline bool lazy_irq_pending(void)
-{
-	return !!(get_paca()->irq_happened & ~PACA_IRQ_HARD_DIS);
-}
-
-/*
- * This is called by asynchronous interrupts to conditionally
- * re-enable hard interrupts when soft-disabled after having
- * cleared the source of the interrupt
- */
-static inline void may_hard_irq_enable(void)
-{
-	get_paca()->irq_happened &= ~PACA_IRQ_HARD_DIS;
-	if (!(get_paca()->irq_happened & PACA_IRQ_EE))
-		__hard_irq_enable();
-}
-
-static inline bool arch_irq_disabled_regs(struct pt_regs *regs)
-{
-	return !regs->softe;
-}
-
-extern bool prep_irq_for_idle(void);
-
-#else /* CONFIG_PPC64 */
-
-#define SET_MSR_EE(x)	mtmsr(x)
-
-static inline unsigned long arch_local_save_flags(void)
-{
-	return mfmsr();
-}
-
-static inline void arch_local_irq_restore(unsigned long flags)
-{
-#if defined(CONFIG_BOOKE)
-	asm volatile("wrtee %0" : : "r" (flags) : "memory");
-#else
-	mtmsr(flags);
-#endif
-}
-
-static inline unsigned long arch_local_irq_save(void)
-{
-	unsigned long flags = arch_local_save_flags();
-#ifdef CONFIG_BOOKE
-	asm volatile("wrteei 0" : : : "memory");
-#else
-	SET_MSR_EE(flags & ~MSR_EE);
-#endif
-	return flags;
-}
-
-static inline void arch_local_irq_disable(void)
-{
-#ifdef CONFIG_BOOKE
-	asm volatile("wrteei 0" : : : "memory");
-#else
-	arch_local_irq_save();
-#endif
-}
-
-static inline void arch_local_irq_enable(void)
-{
-#ifdef CONFIG_BOOKE
-	asm volatile("wrteei 1" : : : "memory");
-#else
-	unsigned long msr = mfmsr();
-	SET_MSR_EE(msr | MSR_EE);
-#endif
-}
-
-static inline bool arch_irqs_disabled_flags(unsigned long flags)
-{
-	return (flags & MSR_EE) == 0;
-}
-
-static inline bool arch_irqs_disabled(void)
-{
-	return arch_irqs_disabled_flags(arch_local_save_flags());
-}
-
-#define hard_irq_disable()		arch_local_irq_disable()
-
-static inline bool arch_irq_disabled_regs(struct pt_regs *regs)
-{
-	return !(regs->msr & MSR_EE);
-}
-
-static inline void may_hard_irq_enable(void) { }
-
-#endif /* CONFIG_PPC64 */
-
-#define ARCH_IRQ_INIT_FLAGS	IRQ_NOREQUEST
-
-/*
- * interrupt-retrigger: should we handle this via lost interrupts and IPIs
- * or should we not care like we do now ? --BenH.
- */
-struct irq_chip;
-
-#endif  /* __ASSEMBLY__ */
-#endif	/* __KERNEL__ */
-#endif	/* _ASM_POWERPC_HW_IRQ_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/hydra.h b/ANDROID_3.4.5/arch/powerpc/include/asm/hydra.h
deleted file mode 100644
index 5b0c98bd..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/hydra.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- *  include/asm-ppc/hydra.h -- Mac I/O `Hydra' definitions
- *
- *  Copyright (C) 1997 Geert Uytterhoeven
- *
- *  This file is based on the following documentation:
- *
- *	Macintosh Technology in the Common Hardware Reference Platform
- *	Apple Computer, Inc.
- *
- *	© Copyright 1995 Apple Computer, Inc. All rights reserved.
- *
- *  It's available online from http://www.cpu.lu/~mlan/ftp/MacTech.pdf
- *  You can obtain paper copies of this book from computer bookstores or by
- *  writing Morgan Kaufmann Publishers, Inc., 340 Pine Street, Sixth Floor, San
- *  Francisco, CA 94104. Reference ISBN 1-55860-393-X.
- *
- *  This file is subject to the terms and conditions of the GNU General Public
- *  License.  See the file COPYING in the main directory of this archive
- *  for more details.
- */
-
-#ifndef _ASMPPC_HYDRA_H
-#define _ASMPPC_HYDRA_H
-
-#ifdef __KERNEL__
-
-struct Hydra {
-    /* DBDMA Controller Register Space */
-    char Pad1[0x30];
-    u_int CachePD;
-    u_int IDs;
-    u_int Feature_Control;
-    char Pad2[0x7fc4];
-    /* DBDMA Channel Register Space */
-    char SCSI_DMA[0x100];
-    char Pad3[0x300];
-    char SCCA_Tx_DMA[0x100];
-    char SCCA_Rx_DMA[0x100];
-    char SCCB_Tx_DMA[0x100];
-    char SCCB_Rx_DMA[0x100];
-    char Pad4[0x7800];
-    /* Device Register Space */
-    char SCSI[0x1000];
-    char ADB[0x1000];
-    char SCC_Legacy[0x1000];
-    char SCC[0x1000];
-    char Pad9[0x2000];
-    char VIA[0x2000];
-    char Pad10[0x28000];
-    char OpenPIC[0x40000];
-};
-
-extern volatile struct Hydra __iomem *Hydra;
-
-
-    /*
-     *  Feature Control Register
-     */
-
-#define HYDRA_FC_SCC_CELL_EN	0x00000001	/* Enable SCC Clock */
-#define HYDRA_FC_SCSI_CELL_EN	0x00000002	/* Enable SCSI Clock */
-#define HYDRA_FC_SCCA_ENABLE	0x00000004	/* Enable SCC A Lines */
-#define HYDRA_FC_SCCB_ENABLE	0x00000008	/* Enable SCC B Lines */
-#define HYDRA_FC_ARB_BYPASS	0x00000010	/* Bypass Internal Arbiter */
-#define HYDRA_FC_RESET_SCC	0x00000020	/* Reset SCC */
-#define HYDRA_FC_MPIC_ENABLE	0x00000040	/* Enable OpenPIC */
-#define HYDRA_FC_SLOW_SCC_PCLK	0x00000080	/* 1=15.6672, 0=25 MHz */
-#define HYDRA_FC_MPIC_IS_MASTER	0x00000100	/* OpenPIC Master Mode */
-
-
-    /*
-     *  OpenPIC Interrupt Sources
-     */
-
-#define HYDRA_INT_SIO		0
-#define HYDRA_INT_SCSI_DMA	1
-#define HYDRA_INT_SCCA_TX_DMA	2
-#define HYDRA_INT_SCCA_RX_DMA	3
-#define HYDRA_INT_SCCB_TX_DMA	4
-#define HYDRA_INT_SCCB_RX_DMA	5
-#define HYDRA_INT_SCSI		6
-#define HYDRA_INT_SCCA		7
-#define HYDRA_INT_SCCB		8
-#define HYDRA_INT_VIA		9
-#define HYDRA_INT_ADB		10
-#define HYDRA_INT_ADB_NMI	11
-#define HYDRA_INT_EXT1		12	/* PCI IRQW */
-#define HYDRA_INT_EXT2		13	/* PCI IRQX */
-#define HYDRA_INT_EXT3		14	/* PCI IRQY */
-#define HYDRA_INT_EXT4		15	/* PCI IRQZ */
-#define HYDRA_INT_EXT5		16	/* IDE Primay/Secondary */
-#define HYDRA_INT_EXT6		17	/* IDE Secondary */
-#define HYDRA_INT_EXT7		18	/* Power Off Request */
-#define HYDRA_INT_SPARE		19
-
-extern int hydra_init(void);
-extern void macio_adb_init(void);
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASMPPC_HYDRA_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/i8259.h b/ANDROID_3.4.5/arch/powerpc/include/asm/i8259.h
deleted file mode 100644
index c3fdfbd5..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/i8259.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef _ASM_POWERPC_I8259_H
-#define _ASM_POWERPC_I8259_H
-#ifdef __KERNEL__
-
-#include <linux/irq.h>
-
-extern void i8259_init(struct device_node *node, unsigned long intack_addr);
-extern unsigned int i8259_irq(void);
-extern struct irq_domain *i8259_get_host(void);
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_I8259_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/ibmebus.h b/ANDROID_3.4.5/arch/powerpc/include/asm/ibmebus.h
deleted file mode 100644
index 1a9d9aea..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/ibmebus.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * IBM PowerPC eBus Infrastructure Support.
- *
- * Copyright (c) 2005 IBM Corporation
- *  Joachim Fenkes <fenkes@de.ibm.com>
- *  Heiko J Schick <schickhj@de.ibm.com>
- *
- * All rights reserved.
- *
- * This source code is distributed under a dual license of GPL v2.0 and OpenIB
- * BSD.
- *
- * OpenIB BSD License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials
- * provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
- * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _ASM_EBUS_H
-#define _ASM_EBUS_H
-#ifdef __KERNEL__
-
-#include <linux/device.h>
-#include <linux/interrupt.h>
-#include <linux/mod_devicetable.h>
-#include <linux/of_device.h>
-#include <linux/of_platform.h>
-
-extern struct bus_type ibmebus_bus_type;
-
-int ibmebus_register_driver(struct of_platform_driver *drv);
-void ibmebus_unregister_driver(struct of_platform_driver *drv);
-
-int ibmebus_request_irq(u32 ist, irq_handler_t handler,
-			unsigned long irq_flags, const char *devname,
-			void *dev_id);
-void ibmebus_free_irq(u32 ist, void *dev_id);
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_IBMEBUS_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/ide.h b/ANDROID_3.4.5/arch/powerpc/include/asm/ide.h
deleted file mode 100644
index da01b20a..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/ide.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- *  Copyright (C) 1994-1996 Linus Torvalds & authors
- *
- *  This file contains the powerpc architecture specific IDE code.
- */
-#ifndef _ASM_POWERPC_IDE_H
-#define _ASM_POWERPC_IDE_H
-
-#include <linux/compiler.h>
-#include <asm/io.h>
-
-#define __ide_mm_insw(p, a, c)	readsw((void __iomem *)(p), (a), (c))
-#define __ide_mm_insl(p, a, c)	readsl((void __iomem *)(p), (a), (c))
-#define __ide_mm_outsw(p, a, c)	writesw((void __iomem *)(p), (a), (c))
-#define __ide_mm_outsl(p, a, c)	writesl((void __iomem *)(p), (a), (c))
-
-#endif /* _ASM_POWERPC_IDE_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/immap_cpm2.h b/ANDROID_3.4.5/arch/powerpc/include/asm/immap_cpm2.h
deleted file mode 100644
index 7c64fda5..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/immap_cpm2.h
+++ /dev/null
@@ -1,647 +0,0 @@
-/*
- * CPM2 Internal Memory Map
- * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
- *
- * The Internal Memory Map for devices with CPM2 on them.  This
- * is the superset of all CPM2 devices (8260, 8266, 8280, 8272,
- * 8560).
- */
-#ifdef __KERNEL__
-#ifndef __IMMAP_CPM2__
-#define __IMMAP_CPM2__
-
-#include <linux/types.h>
-
-/* System configuration registers.
-*/
-typedef	struct sys_82xx_conf {
-	u32	sc_siumcr;
-	u32	sc_sypcr;
-	u8	res1[6];
-	u16	sc_swsr;
-	u8	res2[20];
-	u32	sc_bcr;
-	u8	sc_ppc_acr;
-	u8	res3[3];
-	u32	sc_ppc_alrh;
-	u32	sc_ppc_alrl;
-	u8	sc_lcl_acr;
-	u8	res4[3];
-	u32	sc_lcl_alrh;
-	u32	sc_lcl_alrl;
-	u32	sc_tescr1;
-	u32	sc_tescr2;
-	u32	sc_ltescr1;
-	u32	sc_ltescr2;
-	u32	sc_pdtea;
-	u8	sc_pdtem;
-	u8	res5[3];
-	u32	sc_ldtea;
-	u8	sc_ldtem;
-	u8	res6[163];
-} sysconf_82xx_cpm2_t;
-
-typedef	struct sys_85xx_conf {
-	u32	sc_cear;
-	u16	sc_ceer;
-	u16	sc_cemr;
-	u8	res1[70];
-	u32	sc_smaer;
-	u8	res2[4];
-	u32	sc_smevr;
-	u32	sc_smctr;
-	u32	sc_lmaer;
-	u8	res3[4];
-	u32	sc_lmevr;
-	u32	sc_lmctr;
-	u8	res4[144];
-} sysconf_85xx_cpm2_t;
-
-typedef union sys_conf {
-	sysconf_82xx_cpm2_t	siu_82xx;
-	sysconf_85xx_cpm2_t	siu_85xx;
-} sysconf_cpm2_t;
-
-
-
-/* Memory controller registers.
-*/
-typedef struct	mem_ctlr {
-	u32	memc_br0;
-	u32	memc_or0;
-	u32	memc_br1;
-	u32	memc_or1;
-	u32	memc_br2;
-	u32	memc_or2;
-	u32	memc_br3;
-	u32	memc_or3;
-	u32	memc_br4;
-	u32	memc_or4;
-	u32	memc_br5;
-	u32	memc_or5;
-	u32	memc_br6;
-	u32	memc_or6;
-	u32	memc_br7;
-	u32	memc_or7;
-	u32	memc_br8;
-	u32	memc_or8;
-	u32	memc_br9;
-	u32	memc_or9;
-	u32	memc_br10;
-	u32	memc_or10;
-	u32	memc_br11;
-	u32	memc_or11;
-	u8	res1[8];
-	u32	memc_mar;
-	u8	res2[4];
-	u32	memc_mamr;
-	u32	memc_mbmr;
-	u32	memc_mcmr;
-	u8	res3[8];
-	u16	memc_mptpr;
-	u8	res4[2];
-	u32	memc_mdr;
-	u8	res5[4];
-	u32	memc_psdmr;
-	u32	memc_lsdmr;
-	u8	memc_purt;
-	u8	res6[3];
-	u8	memc_psrt;
-	u8	res7[3];
-	u8	memc_lurt;
-	u8	res8[3];
-	u8	memc_lsrt;
-	u8	res9[3];
-	u32	memc_immr;
-	u32	memc_pcibr0;
-	u32	memc_pcibr1;
-	u8	res10[16];
-	u32	memc_pcimsk0;
-	u32	memc_pcimsk1;
-	u8	res11[52];
-} memctl_cpm2_t;
-
-/* System Integration Timers.
-*/
-typedef struct	sys_int_timers {
-	u8	res1[32];
-	u16	sit_tmcntsc;
-	u8	res2[2];
-	u32	sit_tmcnt;
-	u8	res3[4];
-	u32	sit_tmcntal;
-	u8	res4[16];
-	u16	sit_piscr;
-	u8	res5[2];
-	u32	sit_pitc;
-	u32	sit_pitr;
-	u8      res6[94];
-	u8	res7[390];
-} sit_cpm2_t;
-
-#define PISCR_PIRQ_MASK		((u16)0xff00)
-#define PISCR_PS		((u16)0x0080)
-#define PISCR_PIE		((u16)0x0004)
-#define PISCR_PTF		((u16)0x0002)
-#define PISCR_PTE		((u16)0x0001)
-
-/* PCI Controller.
-*/
-typedef struct pci_ctlr {
-	u32	pci_omisr;
-	u32	pci_omimr;
-	u8	res1[8];
-	u32	pci_ifqpr;
-	u32	pci_ofqpr;
-	u8	res2[8];
-	u32	pci_imr0;
-	u32	pci_imr1;
-	u32	pci_omr0;
-	u32	pci_omr1;
-	u32	pci_odr;
-	u8	res3[4];
-	u32	pci_idr;
-	u8	res4[20];
-	u32	pci_imisr;
-	u32	pci_imimr;
-	u8	res5[24];
-	u32	pci_ifhpr;
-	u8	res6[4];
-	u32	pci_iftpr;
-	u8	res7[4];
-	u32	pci_iphpr;
-	u8	res8[4];
-	u32	pci_iptpr;
-	u8	res9[4];
-	u32	pci_ofhpr;
-	u8	res10[4];
-	u32	pci_oftpr;
-	u8	res11[4];
-	u32	pci_ophpr;
-	u8	res12[4];
-	u32	pci_optpr;
-	u8	res13[8];
-	u32	pci_mucr;
-	u8	res14[8];
-	u32	pci_qbar;
-	u8	res15[12];
-	u32	pci_dmamr0;
-	u32	pci_dmasr0;
-	u32	pci_dmacdar0;
-	u8	res16[4];
-	u32	pci_dmasar0;
-	u8	res17[4];
-	u32	pci_dmadar0;
-	u8	res18[4];
-	u32	pci_dmabcr0;
-	u32	pci_dmandar0;
-	u8	res19[86];
-	u32	pci_dmamr1;
-	u32	pci_dmasr1;
-	u32	pci_dmacdar1;
-	u8	res20[4];
-	u32	pci_dmasar1;
-	u8	res21[4];
-	u32	pci_dmadar1;
-	u8	res22[4];
-	u32	pci_dmabcr1;
-	u32	pci_dmandar1;
-	u8	res23[88];
-	u32	pci_dmamr2;
-	u32	pci_dmasr2;
-	u32	pci_dmacdar2;
-	u8	res24[4];
-	u32	pci_dmasar2;
-	u8	res25[4];
-	u32	pci_dmadar2;
-	u8	res26[4];
-	u32	pci_dmabcr2;
-	u32	pci_dmandar2;
-	u8	res27[88];
-	u32	pci_dmamr3;
-	u32	pci_dmasr3;
-	u32	pci_dmacdar3;
-	u8	res28[4];
-	u32	pci_dmasar3;
-	u8	res29[4];
-	u32	pci_dmadar3;
-	u8	res30[4];
-	u32	pci_dmabcr3;
-	u32	pci_dmandar3;
-	u8	res31[344];
-	u32	pci_potar0;
-	u8	res32[4];
-	u32	pci_pobar0;
-	u8	res33[4];
-	u32	pci_pocmr0;
-	u8	res34[4];
-	u32	pci_potar1;
-	u8	res35[4];
-	u32	pci_pobar1;
-	u8	res36[4];
-	u32	pci_pocmr1;
-	u8	res37[4];
-	u32	pci_potar2;
-	u8	res38[4];
-	u32	pci_pobar2;
-	u8	res39[4];
-	u32	pci_pocmr2;
-	u8	res40[50];
-	u32	pci_ptcr;
-	u32	pci_gpcr;
-	u32	pci_gcr;
-	u32	pci_esr;
-	u32	pci_emr;
-	u32	pci_ecr;
-	u32	pci_eacr;
-	u8	res41[4];
-	u32	pci_edcr;
-	u8	res42[4];
-	u32	pci_eccr;
-	u8	res43[44];
-	u32	pci_pitar1;
-	u8	res44[4];
-	u32	pci_pibar1;
-	u8	res45[4];
-	u32	pci_picmr1;
-	u8	res46[4];
-	u32	pci_pitar0;
-	u8	res47[4];
-	u32	pci_pibar0;
-	u8	res48[4];
-	u32	pci_picmr0;
-	u8	res49[4];
-	u32	pci_cfg_addr;
-	u32	pci_cfg_data;
-	u32	pci_int_ack;
-	u8	res50[756];
-} pci_cpm2_t;
-
-/* Interrupt Controller.
-*/
-typedef struct interrupt_controller {
-	u16	ic_sicr;
-	u8	res1[2];
-	u32	ic_sivec;
-	u32	ic_sipnrh;
-	u32	ic_sipnrl;
-	u32	ic_siprr;
-	u32	ic_scprrh;
-	u32	ic_scprrl;
-	u32	ic_simrh;
-	u32	ic_simrl;
-	u32	ic_siexr;
-	u8	res2[88];
-} intctl_cpm2_t;
-
-/* Clocks and Reset.
-*/
-typedef struct clk_and_reset {
-	u32	car_sccr;
-	u8	res1[4];
-	u32	car_scmr;
-	u8	res2[4];
-	u32	car_rsr;
-	u32	car_rmr;
-	u8	res[104];
-} car_cpm2_t;
-
-/* Input/Output Port control/status registers.
- * Names consistent with processor manual, although they are different
- * from the original 8xx names.......
- */
-typedef struct io_port {
-	u32	iop_pdira;
-	u32	iop_ppara;
-	u32	iop_psora;
-	u32	iop_podra;
-	u32	iop_pdata;
-	u8	res1[12];
-	u32	iop_pdirb;
-	u32	iop_pparb;
-	u32	iop_psorb;
-	u32	iop_podrb;
-	u32	iop_pdatb;
-	u8	res2[12];
-	u32	iop_pdirc;
-	u32	iop_pparc;
-	u32	iop_psorc;
-	u32	iop_podrc;
-	u32	iop_pdatc;
-	u8	res3[12];
-	u32	iop_pdird;
-	u32	iop_ppard;
-	u32	iop_psord;
-	u32	iop_podrd;
-	u32	iop_pdatd;
-	u8	res4[12];
-} iop_cpm2_t;
-
-/* Communication Processor Module Timers
-*/
-typedef struct cpm_timers {
-	u8	cpmt_tgcr1;
-	u8	res1[3];
-	u8	cpmt_tgcr2;
-	u8	res2[11];
-	u16	cpmt_tmr1;
-	u16	cpmt_tmr2;
-	u16	cpmt_trr1;
-	u16	cpmt_trr2;
-	u16	cpmt_tcr1;
-	u16	cpmt_tcr2;
-	u16	cpmt_tcn1;
-	u16	cpmt_tcn2;
-	u16	cpmt_tmr3;
-	u16	cpmt_tmr4;
-	u16	cpmt_trr3;
-	u16	cpmt_trr4;
-	u16	cpmt_tcr3;
-	u16	cpmt_tcr4;
-	u16	cpmt_tcn3;
-	u16	cpmt_tcn4;
-	u16	cpmt_ter1;
-	u16	cpmt_ter2;
-	u16	cpmt_ter3;
-	u16	cpmt_ter4;
-	u8	res3[584];
-} cpmtimer_cpm2_t;
-
-/* DMA control/status registers.
-*/
-typedef struct sdma_csr {
-	u8	res0[24];
-	u8	sdma_sdsr;
-	u8	res1[3];
-	u8	sdma_sdmr;
-	u8	res2[3];
-	u8	sdma_idsr1;
-	u8	res3[3];
-	u8	sdma_idmr1;
-	u8	res4[3];
-	u8	sdma_idsr2;
-	u8	res5[3];
-	u8	sdma_idmr2;
-	u8	res6[3];
-	u8	sdma_idsr3;
-	u8	res7[3];
-	u8	sdma_idmr3;
-	u8	res8[3];
-	u8	sdma_idsr4;
-	u8	res9[3];
-	u8	sdma_idmr4;
-	u8	res10[707];
-} sdma_cpm2_t;
-
-/* Fast controllers
-*/
-typedef struct fcc {
-	u32	fcc_gfmr;
-	u32	fcc_fpsmr;
-	u16	fcc_ftodr;
-	u8	res1[2];
-	u16	fcc_fdsr;
-	u8	res2[2];
-	u16	fcc_fcce;
-	u8	res3[2];
-	u16	fcc_fccm;
-	u8	res4[2];
-	u8	fcc_fccs;
-	u8	res5[3];
-	u8	fcc_ftirr_phy[4];
-} fcc_t;
-
-/* Fast controllers continued
- */
-typedef struct fcc_c {
-	u32	fcc_firper;
-	u32	fcc_firer;
-	u32	fcc_firsr_hi;
-	u32	fcc_firsr_lo;
-	u8	fcc_gfemr;
-	u8	res1[15];
-} fcc_c_t;
-
-/* TC Layer
- */
-typedef struct tclayer {
-	u16	tc_tcmode;
-	u16	tc_cdsmr;
-	u16	tc_tcer;
-	u16	tc_rcc;
-	u16	tc_tcmr;
-	u16	tc_fcc;
-	u16	tc_ccc;
-	u16	tc_icc;
-	u16	tc_tcc;
-	u16	tc_ecc;
-	u8	res1[12];
-} tclayer_t;
-
-
-/* I2C
-*/
-typedef struct i2c {
-	u8	i2c_i2mod;
-	u8	res1[3];
-	u8	i2c_i2add;
-	u8	res2[3];
-	u8	i2c_i2brg;
-	u8	res3[3];
-	u8	i2c_i2com;
-	u8	res4[3];
-	u8	i2c_i2cer;
-	u8	res5[3];
-	u8	i2c_i2cmr;
-	u8	res6[331];
-} i2c_cpm2_t;
-
-typedef struct scc {		/* Serial communication channels */
-	u32	scc_gsmrl;
-	u32	scc_gsmrh;
-	u16	scc_psmr;
-	u8	res1[2];
-	u16	scc_todr;
-	u16	scc_dsr;
-	u16	scc_scce;
-	u8	res2[2];
-	u16	scc_sccm;
-	u8	res3;
-	u8	scc_sccs;
-	u8	res4[8];
-} scc_t;
-
-typedef struct smc {		/* Serial management channels */
-	u8	res1[2];
-	u16	smc_smcmr;
-	u8	res2[2];
-	u8	smc_smce;
-	u8	res3[3];
-	u8	smc_smcm;
-	u8	res4[5];
-} smc_t;
-
-/* Serial Peripheral Interface.
-*/
-typedef struct spi_ctrl {
-	u16	spi_spmode;
-	u8	res1[4];
-	u8	spi_spie;
-	u8	res2[3];
-	u8	spi_spim;
-	u8	res3[2];
-	u8	spi_spcom;
-	u8	res4[82];
-} spictl_cpm2_t;
-
-/* CPM Mux.
-*/
-typedef struct cpmux {
-	u8	cmx_si1cr;
-	u8	res1;
-	u8	cmx_si2cr;
-	u8	res2;
-	u32	cmx_fcr;
-	u32	cmx_scr;
-	u8	cmx_smr;
-	u8	res3;
-	u16	cmx_uar;
-	u8	res4[16];
-} cpmux_t;
-
-/* SIRAM control
-*/
-typedef struct siram {
-	u16	si_amr;
-	u16	si_bmr;
-	u16	si_cmr;
-	u16	si_dmr;
-	u8	si_gmr;
-	u8	res1;
-	u8	si_cmdr;
-	u8	res2;
-	u8	si_str;
-	u8	res3;
-	u16	si_rsr;
-} siramctl_t;
-
-typedef struct mcc {
-	u16	mcc_mcce;
-	u8	res1[2];
-	u16	mcc_mccm;
-	u8	res2[2];
-	u8	mcc_mccf;
-	u8	res3[7];
-} mcc_t;
-
-typedef struct comm_proc {
-	u32	cp_cpcr;
-	u32	cp_rccr;
-	u8	res1[14];
-	u16	cp_rter;
-	u8	res2[2];
-	u16	cp_rtmr;
-	u16	cp_rtscr;
-	u8	res3[2];
-	u32	cp_rtsr;
-	u8	res4[12];
-} cpm_cpm2_t;
-
-/* USB Controller.
-*/
-typedef struct cpm_usb_ctlr {
-	u8	usb_usmod;
-	u8	usb_usadr;
-	u8	usb_uscom;
-	u8	res1[1];
-	__be16  usb_usep[4];
-	u8	res2[4];
-	__be16  usb_usber;
-	u8	res3[2];
-	__be16  usb_usbmr;
-	u8	usb_usbs;
-	u8	res4[7];
-} usb_cpm2_t;
-
-/* ...and the whole thing wrapped up....
-*/
-
-typedef struct immap {
-	/* Some references are into the unique and known dpram spaces,
-	 * others are from the generic base.
-	 */
-#define im_dprambase	im_dpram1
-	u8		im_dpram1[16*1024];
-	u8		res1[16*1024];
-	u8		im_dpram2[4*1024];
-	u8		res2[8*1024];
-	u8		im_dpram3[4*1024];
-	u8		res3[16*1024];
-
-	sysconf_cpm2_t	im_siu_conf;	/* SIU Configuration */
-	memctl_cpm2_t	im_memctl;	/* Memory Controller */
-	sit_cpm2_t	im_sit;		/* System Integration Timers */
-	pci_cpm2_t	im_pci;		/* PCI Controller */
-	intctl_cpm2_t	im_intctl;	/* Interrupt Controller */
-	car_cpm2_t	im_clkrst;	/* Clocks and reset */
-	iop_cpm2_t	im_ioport;	/* IO Port control/status */
-	cpmtimer_cpm2_t	im_cpmtimer;	/* CPM timers */
-	sdma_cpm2_t	im_sdma;	/* SDMA control/status */
-
-	fcc_t		im_fcc[3];	/* Three FCCs */
-	u8		res4z[32];
-	fcc_c_t		im_fcc_c[3];	/* Continued FCCs */
-
-	u8		res4[32];
-
-	tclayer_t	im_tclayer[8];	/* Eight TCLayers */
-	u16		tc_tcgsr;
-	u16		tc_tcger;
-
-	/* First set of baud rate generators.
-	*/
-	u8		res[236];
-	u32		im_brgc5;
-	u32		im_brgc6;
-	u32		im_brgc7;
-	u32		im_brgc8;
-
-	u8		res5[608];
-
-	i2c_cpm2_t	im_i2c;		/* I2C control/status */
-	cpm_cpm2_t	im_cpm;		/* Communication processor */
-
-	/* Second set of baud rate generators.
-	*/
-	u32		im_brgc1;
-	u32		im_brgc2;
-	u32		im_brgc3;
-	u32		im_brgc4;
-
-	scc_t		im_scc[4];	/* Four SCCs */
-	smc_t		im_smc[2];	/* Couple of SMCs */
-	spictl_cpm2_t	im_spi;		/* A SPI */
-	cpmux_t		im_cpmux;	/* CPM clock route mux */
-	siramctl_t	im_siramctl1;	/* First SI RAM Control */
-	mcc_t		im_mcc1;	/* First MCC */
-	siramctl_t	im_siramctl2;	/* Second SI RAM Control */
-	mcc_t		im_mcc2;	/* Second MCC */
-	usb_cpm2_t	im_usb;		/* USB Controller */
-
-	u8		res6[1153];
-
-	u16		im_si1txram[256];
-	u8		res7[512];
-	u16		im_si1rxram[256];
-	u8		res8[512];
-	u16		im_si2txram[256];
-	u8		res9[512];
-	u16		im_si2rxram[256];
-	u8		res10[512];
-	u8		res11[4096];
-} cpm2_map_t;
-
-extern cpm2_map_t __iomem *cpm2_immr;
-
-#endif /* __IMMAP_CPM2__ */
-#endif /* __KERNEL__ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/immap_qe.h b/ANDROID_3.4.5/arch/powerpc/include/asm/immap_qe.h
deleted file mode 100644
index 0edb6842..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/immap_qe.h
+++ /dev/null
@@ -1,489 +0,0 @@
-/*
- * QUICC Engine (QE) Internal Memory Map.
- * The Internal Memory Map for devices with QE on them. This
- * is the superset of all QE devices (8360, etc.).
-
- * Copyright (C) 2006. Freescale Semicondutor, Inc. All rights reserved.
- *
- * Authors: 	Shlomi Gridish <gridish@freescale.com>
- * 		Li Yang <leoli@freescale.com>
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-#ifndef _ASM_POWERPC_IMMAP_QE_H
-#define _ASM_POWERPC_IMMAP_QE_H
-#ifdef __KERNEL__
-
-#include <linux/kernel.h>
-#include <asm/io.h>
-
-#define QE_IMMAP_SIZE	(1024 * 1024)	/* 1MB from 1MB+IMMR */
-
-/* QE I-RAM */
-struct qe_iram {
-	__be32	iadd;		/* I-RAM Address Register */
-	__be32	idata;		/* I-RAM Data Register */
-	u8	res0[0x78];
-} __attribute__ ((packed));
-
-/* QE Interrupt Controller */
-struct qe_ic_regs {
-	__be32	qicr;
-	__be32	qivec;
-	__be32	qripnr;
-	__be32	qipnr;
-	__be32	qipxcc;
-	__be32	qipycc;
-	__be32	qipwcc;
-	__be32	qipzcc;
-	__be32	qimr;
-	__be32	qrimr;
-	__be32	qicnr;
-	u8	res0[0x4];
-	__be32	qiprta;
-	__be32	qiprtb;
-	u8	res1[0x4];
-	__be32	qricr;
-	u8	res2[0x20];
-	__be32	qhivec;
-	u8	res3[0x1C];
-} __attribute__ ((packed));
-
-/* Communications Processor */
-struct cp_qe {
-	__be32	cecr;		/* QE command register */
-	__be32	ceccr;		/* QE controller configuration register */
-	__be32	cecdr;		/* QE command data register */
-	u8	res0[0xA];
-	__be16	ceter;		/* QE timer event register */
-	u8	res1[0x2];
-	__be16	cetmr;		/* QE timers mask register */
-	__be32	cetscr;		/* QE time-stamp timer control register */
-	__be32	cetsr1;		/* QE time-stamp register 1 */
-	__be32	cetsr2;		/* QE time-stamp register 2 */
-	u8	res2[0x8];
-	__be32	cevter;		/* QE virtual tasks event register */
-	__be32	cevtmr;		/* QE virtual tasks mask register */
-	__be16	cercr;		/* QE RAM control register */
-	u8	res3[0x2];
-	u8	res4[0x24];
-	__be16	ceexe1;		/* QE external request 1 event register */
-	u8	res5[0x2];
-	__be16	ceexm1;		/* QE external request 1 mask register */
-	u8	res6[0x2];
-	__be16	ceexe2;		/* QE external request 2 event register */
-	u8	res7[0x2];
-	__be16	ceexm2;		/* QE external request 2 mask register */
-	u8	res8[0x2];
-	__be16	ceexe3;		/* QE external request 3 event register */
-	u8	res9[0x2];
-	__be16	ceexm3;		/* QE external request 3 mask register */
-	u8	res10[0x2];
-	__be16	ceexe4;		/* QE external request 4 event register */
-	u8	res11[0x2];
-	__be16	ceexm4;		/* QE external request 4 mask register */
-	u8	res12[0x3A];
-	__be32	ceurnr;		/* QE microcode revision number register */
-	u8	res13[0x244];
-} __attribute__ ((packed));
-
-/* QE Multiplexer */
-struct qe_mux {
-	__be32	cmxgcr;		/* CMX general clock route register */
-	__be32	cmxsi1cr_l;	/* CMX SI1 clock route low register */
-	__be32	cmxsi1cr_h;	/* CMX SI1 clock route high register */
-	__be32	cmxsi1syr;	/* CMX SI1 SYNC route register */
-	__be32	cmxucr[4];	/* CMX UCCx clock route registers */
-	__be32	cmxupcr;	/* CMX UPC clock route register */
-	u8	res0[0x1C];
-} __attribute__ ((packed));
-
-/* QE Timers */
-struct qe_timers {
-	u8	gtcfr1;		/* Timer 1 and Timer 2 global config register*/
-	u8	res0[0x3];
-	u8	gtcfr2;		/* Timer 3 and timer 4 global config register*/
-	u8	res1[0xB];
-	__be16	gtmdr1;		/* Timer 1 mode register */
-	__be16	gtmdr2;		/* Timer 2 mode register */
-	__be16	gtrfr1;		/* Timer 1 reference register */
-	__be16	gtrfr2;		/* Timer 2 reference register */
-	__be16	gtcpr1;		/* Timer 1 capture register */
-	__be16	gtcpr2;		/* Timer 2 capture register */
-	__be16	gtcnr1;		/* Timer 1 counter */
-	__be16	gtcnr2;		/* Timer 2 counter */
-	__be16	gtmdr3;		/* Timer 3 mode register */
-	__be16	gtmdr4;		/* Timer 4 mode register */
-	__be16	gtrfr3;		/* Timer 3 reference register */
-	__be16	gtrfr4;		/* Timer 4 reference register */
-	__be16	gtcpr3;		/* Timer 3 capture register */
-	__be16	gtcpr4;		/* Timer 4 capture register */
-	__be16	gtcnr3;		/* Timer 3 counter */
-	__be16	gtcnr4;		/* Timer 4 counter */
-	__be16	gtevr1;		/* Timer 1 event register */
-	__be16	gtevr2;		/* Timer 2 event register */
-	__be16	gtevr3;		/* Timer 3 event register */
-	__be16	gtevr4;		/* Timer 4 event register */
-	__be16	gtps;		/* Timer 1 prescale register */
-	u8 res2[0x46];
-} __attribute__ ((packed));
-
-/* BRG */
-struct qe_brg {
-	__be32	brgc[16];	/* BRG configuration registers */
-	u8	res0[0x40];
-} __attribute__ ((packed));
-
-/* SPI */
-struct spi {
-	u8	res0[0x20];
-	__be32	spmode;		/* SPI mode register */
-	u8	res1[0x2];
-	u8	spie;		/* SPI event register */
-	u8	res2[0x1];
-	u8	res3[0x2];
-	u8	spim;		/* SPI mask register */
-	u8	res4[0x1];
-	u8	res5[0x1];
-	u8	spcom;		/* SPI command register */
-	u8	res6[0x2];
-	__be32	spitd;		/* SPI transmit data register (cpu mode) */
-	__be32	spird;		/* SPI receive data register (cpu mode) */
-	u8	res7[0x8];
-} __attribute__ ((packed));
-
-/* SI */
-struct si1 {
-	__be16	siamr1;		/* SI1 TDMA mode register */
-	__be16	sibmr1;		/* SI1 TDMB mode register */
-	__be16	sicmr1;		/* SI1 TDMC mode register */
-	__be16	sidmr1;		/* SI1 TDMD mode register */
-	u8	siglmr1_h;	/* SI1 global mode register high */
-	u8	res0[0x1];
-	u8	sicmdr1_h;	/* SI1 command register high */
-	u8	res2[0x1];
-	u8	sistr1_h;	/* SI1 status register high */
-	u8	res3[0x1];
-	__be16	sirsr1_h;	/* SI1 RAM shadow address register high */
-	u8	sitarc1;	/* SI1 RAM counter Tx TDMA */
-	u8	sitbrc1;	/* SI1 RAM counter Tx TDMB */
-	u8	sitcrc1;	/* SI1 RAM counter Tx TDMC */
-	u8	sitdrc1;	/* SI1 RAM counter Tx TDMD */
-	u8	sirarc1;	/* SI1 RAM counter Rx TDMA */
-	u8	sirbrc1;	/* SI1 RAM counter Rx TDMB */
-	u8	sircrc1;	/* SI1 RAM counter Rx TDMC */
-	u8	sirdrc1;	/* SI1 RAM counter Rx TDMD */
-	u8	res4[0x8];
-	__be16	siemr1;		/* SI1 TDME mode register 16 bits */
-	__be16	sifmr1;		/* SI1 TDMF mode register 16 bits */
-	__be16	sigmr1;		/* SI1 TDMG mode register 16 bits */
-	__be16	sihmr1;		/* SI1 TDMH mode register 16 bits */
-	u8	siglmg1_l;	/* SI1 global mode register low 8 bits */
-	u8	res5[0x1];
-	u8	sicmdr1_l;	/* SI1 command register low 8 bits */
-	u8	res6[0x1];
-	u8	sistr1_l;	/* SI1 status register low 8 bits */
-	u8	res7[0x1];
-	__be16	sirsr1_l;	/* SI1 RAM shadow address register low 16 bits*/
-	u8	siterc1;	/* SI1 RAM counter Tx TDME 8 bits */
-	u8	sitfrc1;	/* SI1 RAM counter Tx TDMF 8 bits */
-	u8	sitgrc1;	/* SI1 RAM counter Tx TDMG 8 bits */
-	u8	sithrc1;	/* SI1 RAM counter Tx TDMH 8 bits */
-	u8	sirerc1;	/* SI1 RAM counter Rx TDME 8 bits */
-	u8	sirfrc1;	/* SI1 RAM counter Rx TDMF 8 bits */
-	u8	sirgrc1;	/* SI1 RAM counter Rx TDMG 8 bits */
-	u8	sirhrc1;	/* SI1 RAM counter Rx TDMH 8 bits */
-	u8	res8[0x8];
-	__be32	siml1;		/* SI1 multiframe limit register */
-	u8	siedm1;		/* SI1 extended diagnostic mode register */
-	u8	res9[0xBB];
-} __attribute__ ((packed));
-
-/* SI Routing Tables */
-struct sir {
-	u8 	tx[0x400];
-	u8	rx[0x400];
-	u8	res0[0x800];
-} __attribute__ ((packed));
-
-/* USB Controller */
-struct qe_usb_ctlr {
-	u8	usb_usmod;
-	u8	usb_usadr;
-	u8	usb_uscom;
-	u8	res1[1];
-	__be16  usb_usep[4];
-	u8	res2[4];
-	__be16	usb_usber;
-	u8	res3[2];
-	__be16	usb_usbmr;
-	u8	res4[1];
-	u8	usb_usbs;
-	__be16	usb_ussft;
-	u8	res5[2];
-	__be16	usb_usfrn;
-	u8	res6[0x22];
-} __attribute__ ((packed));
-
-/* MCC */
-struct qe_mcc {
-	__be32	mcce;		/* MCC event register */
-	__be32	mccm;		/* MCC mask register */
-	__be32	mccf;		/* MCC configuration register */
-	__be32	merl;		/* MCC emergency request level register */
-	u8	res0[0xF0];
-} __attribute__ ((packed));
-
-/* QE UCC Slow */
-struct ucc_slow {
-	__be32	gumr_l;		/* UCCx general mode register (low) */
-	__be32	gumr_h;		/* UCCx general mode register (high) */
-	__be16	upsmr;		/* UCCx protocol-specific mode register */
-	u8	res0[0x2];
-	__be16	utodr;		/* UCCx transmit on demand register */
-	__be16	udsr;		/* UCCx data synchronization register */
-	__be16	ucce;		/* UCCx event register */
-	u8	res1[0x2];
-	__be16	uccm;		/* UCCx mask register */
-	u8	res2[0x1];
-	u8	uccs;		/* UCCx status register */
-	u8	res3[0x24];
-	__be16	utpt;
-	u8	res4[0x52];
-	u8	guemr;		/* UCC general extended mode register */
-} __attribute__ ((packed));
-
-/* QE UCC Fast */
-struct ucc_fast {
-	__be32	gumr;		/* UCCx general mode register */
-	__be32	upsmr;		/* UCCx protocol-specific mode register */
-	__be16	utodr;		/* UCCx transmit on demand register */
-	u8	res0[0x2];
-	__be16	udsr;		/* UCCx data synchronization register */
-	u8	res1[0x2];
-	__be32	ucce;		/* UCCx event register */
-	__be32	uccm;		/* UCCx mask register */
-	u8	uccs;		/* UCCx status register */
-	u8	res2[0x7];
-	__be32	urfb;		/* UCC receive FIFO base */
-	__be16	urfs;		/* UCC receive FIFO size */
-	u8	res3[0x2];
-	__be16	urfet;		/* UCC receive FIFO emergency threshold */
-	__be16	urfset;		/* UCC receive FIFO special emergency
-				   threshold */
-	__be32	utfb;		/* UCC transmit FIFO base */
-	__be16	utfs;		/* UCC transmit FIFO size */
-	u8	res4[0x2];
-	__be16	utfet;		/* UCC transmit FIFO emergency threshold */
-	u8	res5[0x2];
-	__be16	utftt;		/* UCC transmit FIFO transmit threshold */
-	u8	res6[0x2];
-	__be16	utpt;		/* UCC transmit polling timer */
-	u8	res7[0x2];
-	__be32	urtry;		/* UCC retry counter register */
-	u8	res8[0x4C];
-	u8	guemr;		/* UCC general extended mode register */
-} __attribute__ ((packed));
-
-struct ucc {
-	union {
-		struct	ucc_slow slow;
-		struct	ucc_fast fast;
-		u8	res[0x200];	/* UCC blocks are 512 bytes each */
-	};
-} __attribute__ ((packed));
-
-/* MultiPHY UTOPIA POS Controllers (UPC) */
-struct upc {
-	__be32	upgcr;		/* UTOPIA/POS general configuration register */
-	__be32	uplpa;		/* UTOPIA/POS last PHY address */
-	__be32	uphec;		/* ATM HEC register */
-	__be32	upuc;		/* UTOPIA/POS UCC configuration */
-	__be32	updc1;		/* UTOPIA/POS device 1 configuration */
-	__be32	updc2;		/* UTOPIA/POS device 2 configuration */
-	__be32	updc3;		/* UTOPIA/POS device 3 configuration */
-	__be32	updc4;		/* UTOPIA/POS device 4 configuration */
-	__be32	upstpa;		/* UTOPIA/POS STPA threshold */
-	u8	res0[0xC];
-	__be32	updrs1_h;	/* UTOPIA/POS device 1 rate select */
-	__be32	updrs1_l;	/* UTOPIA/POS device 1 rate select */
-	__be32	updrs2_h;	/* UTOPIA/POS device 2 rate select */
-	__be32	updrs2_l;	/* UTOPIA/POS device 2 rate select */
-	__be32	updrs3_h;	/* UTOPIA/POS device 3 rate select */
-	__be32	updrs3_l;	/* UTOPIA/POS device 3 rate select */
-	__be32	updrs4_h;	/* UTOPIA/POS device 4 rate select */
-	__be32	updrs4_l;	/* UTOPIA/POS device 4 rate select */
-	__be32	updrp1;		/* UTOPIA/POS device 1 receive priority low */
-	__be32	updrp2;		/* UTOPIA/POS device 2 receive priority low */
-	__be32	updrp3;		/* UTOPIA/POS device 3 receive priority low */
-	__be32	updrp4;		/* UTOPIA/POS device 4 receive priority low */
-	__be32	upde1;		/* UTOPIA/POS device 1 event */
-	__be32	upde2;		/* UTOPIA/POS device 2 event */
-	__be32	upde3;		/* UTOPIA/POS device 3 event */
-	__be32	upde4;		/* UTOPIA/POS device 4 event */
-	__be16	uprp1;
-	__be16	uprp2;
-	__be16	uprp3;
-	__be16	uprp4;
-	u8	res1[0x8];
-	__be16	uptirr1_0;	/* Device 1 transmit internal rate 0 */
-	__be16	uptirr1_1;	/* Device 1 transmit internal rate 1 */
-	__be16	uptirr1_2;	/* Device 1 transmit internal rate 2 */
-	__be16	uptirr1_3;	/* Device 1 transmit internal rate 3 */
-	__be16	uptirr2_0;	/* Device 2 transmit internal rate 0 */
-	__be16	uptirr2_1;	/* Device 2 transmit internal rate 1 */
-	__be16	uptirr2_2;	/* Device 2 transmit internal rate 2 */
-	__be16	uptirr2_3;	/* Device 2 transmit internal rate 3 */
-	__be16	uptirr3_0;	/* Device 3 transmit internal rate 0 */
-	__be16	uptirr3_1;	/* Device 3 transmit internal rate 1 */
-	__be16	uptirr3_2;	/* Device 3 transmit internal rate 2 */
-	__be16	uptirr3_3;	/* Device 3 transmit internal rate 3 */
-	__be16	uptirr4_0;	/* Device 4 transmit internal rate 0 */
-	__be16	uptirr4_1;	/* Device 4 transmit internal rate 1 */
-	__be16	uptirr4_2;	/* Device 4 transmit internal rate 2 */
-	__be16	uptirr4_3;	/* Device 4 transmit internal rate 3 */
-	__be32	uper1;		/* Device 1 port enable register */
-	__be32	uper2;		/* Device 2 port enable register */
-	__be32	uper3;		/* Device 3 port enable register */
-	__be32	uper4;		/* Device 4 port enable register */
-	u8	res2[0x150];
-} __attribute__ ((packed));
-
-/* SDMA */
-struct sdma {
-	__be32	sdsr;		/* Serial DMA status register */
-	__be32	sdmr;		/* Serial DMA mode register */
-	__be32	sdtr1;		/* SDMA system bus threshold register */
-	__be32	sdtr2;		/* SDMA secondary bus threshold register */
-	__be32	sdhy1;		/* SDMA system bus hysteresis register */
-	__be32	sdhy2;		/* SDMA secondary bus hysteresis register */
-	__be32	sdta1;		/* SDMA system bus address register */
-	__be32	sdta2;		/* SDMA secondary bus address register */
-	__be32	sdtm1;		/* SDMA system bus MSNUM register */
-	__be32	sdtm2;		/* SDMA secondary bus MSNUM register */
-	u8	res0[0x10];
-	__be32	sdaqr;		/* SDMA address bus qualify register */
-	__be32	sdaqmr;		/* SDMA address bus qualify mask register */
-	u8	res1[0x4];
-	__be32	sdebcr;		/* SDMA CAM entries base register */
-	u8	res2[0x38];
-} __attribute__ ((packed));
-
-/* Debug Space */
-struct dbg {
-	__be32	bpdcr;		/* Breakpoint debug command register */
-	__be32	bpdsr;		/* Breakpoint debug status register */
-	__be32	bpdmr;		/* Breakpoint debug mask register */
-	__be32	bprmrr0;	/* Breakpoint request mode risc register 0 */
-	__be32	bprmrr1;	/* Breakpoint request mode risc register 1 */
-	u8	res0[0x8];
-	__be32	bprmtr0;	/* Breakpoint request mode trb register 0 */
-	__be32	bprmtr1;	/* Breakpoint request mode trb register 1 */
-	u8	res1[0x8];
-	__be32	bprmir;		/* Breakpoint request mode immediate register */
-	__be32	bprmsr;		/* Breakpoint request mode serial register */
-	__be32	bpemr;		/* Breakpoint exit mode register */
-	u8	res2[0x48];
-} __attribute__ ((packed));
-
-/*
- * RISC Special Registers (Trap and Breakpoint).  These are described in
- * the QE Developer's Handbook.
- */
-struct rsp {
-	__be32 tibcr[16];	/* Trap/instruction breakpoint control regs */
-	u8 res0[64];
-	__be32 ibcr0;
-	__be32 ibs0;
-	__be32 ibcnr0;
-	u8 res1[4];
-	__be32 ibcr1;
-	__be32 ibs1;
-	__be32 ibcnr1;
-	__be32 npcr;
-	__be32 dbcr;
-	__be32 dbar;
-	__be32 dbamr;
-	__be32 dbsr;
-	__be32 dbcnr;
-	u8 res2[12];
-	__be32 dbdr_h;
-	__be32 dbdr_l;
-	__be32 dbdmr_h;
-	__be32 dbdmr_l;
-	__be32 bsr;
-	__be32 bor;
-	__be32 bior;
-	u8 res3[4];
-	__be32 iatr[4];
-	__be32 eccr;		/* Exception control configuration register */
-	__be32 eicr;
-	u8 res4[0x100-0xf8];
-} __attribute__ ((packed));
-
-struct qe_immap {
-	struct qe_iram		iram;		/* I-RAM */
-	struct qe_ic_regs	ic;		/* Interrupt Controller */
-	struct cp_qe		cp;		/* Communications Processor */
-	struct qe_mux		qmx;		/* QE Multiplexer */
-	struct qe_timers	qet;		/* QE Timers */
-	struct spi		spi[0x2];	/* spi */
-	struct qe_mcc		mcc;		/* mcc */
-	struct qe_brg		brg;		/* brg */
-	struct qe_usb_ctlr	usb;		/* USB */
-	struct si1		si1;		/* SI */
-	u8			res11[0x800];
-	struct sir		sir;		/* SI Routing Tables */
-	struct ucc		ucc1;		/* ucc1 */
-	struct ucc		ucc3;		/* ucc3 */
-	struct ucc		ucc5;		/* ucc5 */
-	struct ucc		ucc7;		/* ucc7 */
-	u8			res12[0x600];
-	struct upc		upc1;		/* MultiPHY UTOPIA POS Ctrlr 1*/
-	struct ucc		ucc2;		/* ucc2 */
-	struct ucc		ucc4;		/* ucc4 */
-	struct ucc		ucc6;		/* ucc6 */
-	struct ucc		ucc8;		/* ucc8 */
-	u8			res13[0x600];
-	struct upc		upc2;		/* MultiPHY UTOPIA POS Ctrlr 2*/
-	struct sdma		sdma;		/* SDMA */
-	struct dbg		dbg;		/* 0x104080 - 0x1040FF
-						   Debug Space */
-	struct rsp		rsp[0x2];	/* 0x104100 - 0x1042FF
-						   RISC Special Registers
-						   (Trap and Breakpoint) */
-	u8			res14[0x300];	/* 0x104300 - 0x1045FF */
-	u8			res15[0x3A00];	/* 0x104600 - 0x107FFF */
-	u8			res16[0x8000];	/* 0x108000 - 0x110000 */
-	u8			muram[0xC000];	/* 0x110000 - 0x11C000
-						   Multi-user RAM */
-	u8			res17[0x24000];	/* 0x11C000 - 0x140000 */
-	u8			res18[0xC0000];	/* 0x140000 - 0x200000 */
-} __attribute__ ((packed));
-
-extern struct qe_immap __iomem *qe_immr;
-extern phys_addr_t get_qe_base(void);
-
-/*
- * Returns the offset within the QE address space of the given pointer.
- *
- * Note that the QE does not support 36-bit physical addresses, so if
- * get_qe_base() returns a number above 4GB, the caller will probably fail.
- */
-static inline phys_addr_t immrbar_virt_to_phys(void *address)
-{
-	void *q = (void *)qe_immr;
-
-	/* Is it a MURAM address? */
-	if ((address >= q) && (address < (q + QE_IMMAP_SIZE)))
-		return get_qe_base() + (address - q);
-
-	/* It's an address returned by kmalloc */
-	return virt_to_phys(address);
-}
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_IMMAP_QE_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/io-defs.h b/ANDROID_3.4.5/arch/powerpc/include/asm/io-defs.h
deleted file mode 100644
index 44d7927a..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/io-defs.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* This file is meant to be include multiple times by other headers */
-/* last 2 argments are used by platforms/cell/io-workarounds.[ch] */
-
-DEF_PCI_AC_RET(readb, u8, (const PCI_IO_ADDR addr), (addr), mem, addr)
-DEF_PCI_AC_RET(readw, u16, (const PCI_IO_ADDR addr), (addr), mem, addr)
-DEF_PCI_AC_RET(readl, u32, (const PCI_IO_ADDR addr), (addr), mem, addr)
-DEF_PCI_AC_RET(readw_be, u16, (const PCI_IO_ADDR addr), (addr), mem, addr)
-DEF_PCI_AC_RET(readl_be, u32, (const PCI_IO_ADDR addr), (addr), mem, addr)
-DEF_PCI_AC_NORET(writeb, (u8 val, PCI_IO_ADDR addr), (val, addr), mem, addr)
-DEF_PCI_AC_NORET(writew, (u16 val, PCI_IO_ADDR addr), (val, addr), mem, addr)
-DEF_PCI_AC_NORET(writel, (u32 val, PCI_IO_ADDR addr), (val, addr), mem, addr)
-DEF_PCI_AC_NORET(writew_be, (u16 val, PCI_IO_ADDR addr), (val, addr), mem, addr)
-DEF_PCI_AC_NORET(writel_be, (u32 val, PCI_IO_ADDR addr), (val, addr), mem, addr)
-
-#ifdef __powerpc64__
-DEF_PCI_AC_RET(readq, u64, (const PCI_IO_ADDR addr), (addr), mem, addr)
-DEF_PCI_AC_RET(readq_be, u64, (const PCI_IO_ADDR addr), (addr), mem, addr)
-DEF_PCI_AC_NORET(writeq, (u64 val, PCI_IO_ADDR addr), (val, addr), mem, addr)
-DEF_PCI_AC_NORET(writeq_be, (u64 val, PCI_IO_ADDR addr), (val, addr), mem, addr)
-#endif /* __powerpc64__ */
-
-DEF_PCI_AC_RET(inb, u8, (unsigned long port), (port), pio, port)
-DEF_PCI_AC_RET(inw, u16, (unsigned long port), (port), pio, port)
-DEF_PCI_AC_RET(inl, u32, (unsigned long port), (port), pio, port)
-DEF_PCI_AC_NORET(outb, (u8 val, unsigned long port), (val, port), pio, port)
-DEF_PCI_AC_NORET(outw, (u16 val, unsigned long port), (val, port), pio, port)
-DEF_PCI_AC_NORET(outl, (u32 val, unsigned long port), (val, port), pio, port)
-
-DEF_PCI_AC_NORET(readsb, (const PCI_IO_ADDR a, void *b, unsigned long c),
-		 (a, b, c), mem, a)
-DEF_PCI_AC_NORET(readsw, (const PCI_IO_ADDR a, void *b, unsigned long c),
-		 (a, b, c), mem, a)
-DEF_PCI_AC_NORET(readsl, (const PCI_IO_ADDR a, void *b, unsigned long c),
-		 (a, b, c), mem, a)
-DEF_PCI_AC_NORET(writesb, (PCI_IO_ADDR a, const void *b, unsigned long c),
-		 (a, b, c), mem, a)
-DEF_PCI_AC_NORET(writesw, (PCI_IO_ADDR a, const void *b, unsigned long c),
-		 (a, b, c), mem, a)
-DEF_PCI_AC_NORET(writesl, (PCI_IO_ADDR a, const void *b, unsigned long c),
-		 (a, b, c), mem, a)
-
-DEF_PCI_AC_NORET(insb, (unsigned long p, void *b, unsigned long c),
-		 (p, b, c), pio, p)
-DEF_PCI_AC_NORET(insw, (unsigned long p, void *b, unsigned long c),
-		 (p, b, c), pio, p)
-DEF_PCI_AC_NORET(insl, (unsigned long p, void *b, unsigned long c),
-		 (p, b, c), pio, p)
-DEF_PCI_AC_NORET(outsb, (unsigned long p, const void *b, unsigned long c),
-		 (p, b, c), pio, p)
-DEF_PCI_AC_NORET(outsw, (unsigned long p, const void *b, unsigned long c),
-		 (p, b, c), pio, p)
-DEF_PCI_AC_NORET(outsl, (unsigned long p, const void *b, unsigned long c),
-		 (p, b, c), pio, p)
-
-DEF_PCI_AC_NORET(memset_io, (PCI_IO_ADDR a, int c, unsigned long n),
-		 (a, c, n), mem, a)
-DEF_PCI_AC_NORET(memcpy_fromio, (void *d, const PCI_IO_ADDR s, unsigned long n),
-		 (d, s, n), mem, s)
-DEF_PCI_AC_NORET(memcpy_toio, (PCI_IO_ADDR d, const void *s, unsigned long n),
-		 (d, s, n), mem, d)
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/io-workarounds.h b/ANDROID_3.4.5/arch/powerpc/include/asm/io-workarounds.h
deleted file mode 100644
index fbae4928..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/io-workarounds.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Support PCI IO workaround
- *
- * (C) Copyright 2007-2008 TOSHIBA CORPORATION
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#ifndef _IO_WORKAROUNDS_H
-#define _IO_WORKAROUNDS_H
-
-#include <linux/io.h>
-#include <asm/pci-bridge.h>
-
-/* Bus info */
-struct iowa_bus {
-	struct pci_controller *phb;
-	struct ppc_pci_io *ops;
-	void   *private;
-};
-
-void __devinit iowa_register_bus(struct pci_controller *, struct ppc_pci_io *,
-				 int (*)(struct iowa_bus *, void *), void *);
-struct iowa_bus *iowa_mem_find_bus(const PCI_IO_ADDR);
-struct iowa_bus *iowa_pio_find_bus(unsigned long);
-
-extern struct ppc_pci_io spiderpci_ops;
-extern int spiderpci_iowa_init(struct iowa_bus *, void *);
-
-#define SPIDER_PCI_REG_BASE		0xd000
-#define SPIDER_PCI_REG_SIZE		0x1000
-#define SPIDER_PCI_VCI_CNTL_STAT	0x0110
-#define SPIDER_PCI_DUMMY_READ		0x0810
-#define SPIDER_PCI_DUMMY_READ_BASE	0x0814
-
-#endif /* _IO_WORKAROUNDS_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/io.h b/ANDROID_3.4.5/arch/powerpc/include/asm/io.h
deleted file mode 100644
index a3855b81..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/io.h
+++ /dev/null
@@ -1,795 +0,0 @@
-#ifndef _ASM_POWERPC_IO_H
-#define _ASM_POWERPC_IO_H
-#ifdef __KERNEL__
-
-#define ARCH_HAS_IOREMAP_WC
-
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-/* Check of existence of legacy devices */
-extern int check_legacy_ioport(unsigned long base_port);
-#define I8042_DATA_REG	0x60
-#define FDC_BASE	0x3f0
-/* only relevant for PReP */
-#define _PIDXR		0x279
-#define _PNPWRP		0xa79
-#define PNPBIOS_BASE	0xf000
-
-#include <linux/device.h>
-#include <linux/io.h>
-
-#include <linux/compiler.h>
-#include <asm/page.h>
-#include <asm/byteorder.h>
-#include <asm/synch.h>
-#include <asm/delay.h>
-#include <asm/mmu.h>
-
-#include <asm-generic/iomap.h>
-
-#ifdef CONFIG_PPC64
-#include <asm/paca.h>
-#endif
-
-#define SIO_CONFIG_RA	0x398
-#define SIO_CONFIG_RD	0x399
-
-#define SLOW_DOWN_IO
-
-/* 32 bits uses slightly different variables for the various IO
- * bases. Most of this file only uses _IO_BASE though which we
- * define properly based on the platform
- */
-#ifndef CONFIG_PCI
-#define _IO_BASE	0
-#define _ISA_MEM_BASE	0
-#define PCI_DRAM_OFFSET 0
-#elif defined(CONFIG_PPC32)
-#define _IO_BASE	isa_io_base
-#define _ISA_MEM_BASE	isa_mem_base
-#define PCI_DRAM_OFFSET	pci_dram_offset
-#else
-#define _IO_BASE	pci_io_base
-#define _ISA_MEM_BASE	isa_mem_base
-#define PCI_DRAM_OFFSET	0
-#endif
-
-extern unsigned long isa_io_base;
-extern unsigned long pci_io_base;
-extern unsigned long pci_dram_offset;
-
-extern resource_size_t isa_mem_base;
-
-#if defined(CONFIG_PPC32) && defined(CONFIG_PPC_INDIRECT_IO)
-#error CONFIG_PPC_INDIRECT_IO is not yet supported on 32 bits
-#endif
-
-/*
- *
- * Low level MMIO accessors
- *
- * This provides the non-bus specific accessors to MMIO. Those are PowerPC
- * specific and thus shouldn't be used in generic code. The accessors
- * provided here are:
- *
- *	in_8, in_le16, in_be16, in_le32, in_be32, in_le64, in_be64
- *	out_8, out_le16, out_be16, out_le32, out_be32, out_le64, out_be64
- *	_insb, _insw_ns, _insl_ns, _outsb, _outsw_ns, _outsl_ns
- *
- * Those operate directly on a kernel virtual address. Note that the prototype
- * for the out_* accessors has the arguments in opposite order from the usual
- * linux PCI accessors. Unlike those, they take the address first and the value
- * next.
- *
- * Note: I might drop the _ns suffix on the stream operations soon as it is
- * simply normal for stream operations to not swap in the first place.
- *
- */
-
-#ifdef CONFIG_PPC64
-#define IO_SET_SYNC_FLAG()	do { local_paca->io_sync = 1; } while(0)
-#else
-#define IO_SET_SYNC_FLAG()
-#endif
-
-/* gcc 4.0 and older doesn't have 'Z' constraint */
-#if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ == 0)
-#define DEF_MMIO_IN_LE(name, size, insn)				\
-static inline u##size name(const volatile u##size __iomem *addr)	\
-{									\
-	u##size ret;							\
-	__asm__ __volatile__("sync;"#insn" %0,0,%1;twi 0,%0,0;isync"	\
-		: "=r" (ret) : "r" (addr), "m" (*addr) : "memory");	\
-	return ret;							\
-}
-
-#define DEF_MMIO_OUT_LE(name, size, insn) 				\
-static inline void name(volatile u##size __iomem *addr, u##size val)	\
-{									\
-	__asm__ __volatile__("sync;"#insn" %1,0,%2"			\
-		: "=m" (*addr) : "r" (val), "r" (addr) : "memory");	\
-	IO_SET_SYNC_FLAG();						\
-}
-#else /* newer gcc */
-#define DEF_MMIO_IN_LE(name, size, insn)				\
-static inline u##size name(const volatile u##size __iomem *addr)	\
-{									\
-	u##size ret;							\
-	__asm__ __volatile__("sync;"#insn" %0,%y1;twi 0,%0,0;isync"	\
-		: "=r" (ret) : "Z" (*addr) : "memory");			\
-	return ret;							\
-}
-
-#define DEF_MMIO_OUT_LE(name, size, insn) 				\
-static inline void name(volatile u##size __iomem *addr, u##size val)	\
-{									\
-	__asm__ __volatile__("sync;"#insn" %1,%y0"			\
-		: "=Z" (*addr) : "r" (val) : "memory");			\
-	IO_SET_SYNC_FLAG();						\
-}
-#endif
-
-#define DEF_MMIO_IN_BE(name, size, insn)				\
-static inline u##size name(const volatile u##size __iomem *addr)	\
-{									\
-	u##size ret;							\
-	__asm__ __volatile__("sync;"#insn"%U1%X1 %0,%1;twi 0,%0,0;isync"\
-		: "=r" (ret) : "m" (*addr) : "memory");			\
-	return ret;							\
-}
-
-#define DEF_MMIO_OUT_BE(name, size, insn)				\
-static inline void name(volatile u##size __iomem *addr, u##size val)	\
-{									\
-	__asm__ __volatile__("sync;"#insn"%U0%X0 %1,%0"			\
-		: "=m" (*addr) : "r" (val) : "memory");			\
-	IO_SET_SYNC_FLAG();						\
-}
-
-
-DEF_MMIO_IN_BE(in_8,     8, lbz);
-DEF_MMIO_IN_BE(in_be16, 16, lhz);
-DEF_MMIO_IN_BE(in_be32, 32, lwz);
-DEF_MMIO_IN_LE(in_le16, 16, lhbrx);
-DEF_MMIO_IN_LE(in_le32, 32, lwbrx);
-
-DEF_MMIO_OUT_BE(out_8,     8, stb);
-DEF_MMIO_OUT_BE(out_be16, 16, sth);
-DEF_MMIO_OUT_BE(out_be32, 32, stw);
-DEF_MMIO_OUT_LE(out_le16, 16, sthbrx);
-DEF_MMIO_OUT_LE(out_le32, 32, stwbrx);
-
-#ifdef __powerpc64__
-DEF_MMIO_OUT_BE(out_be64, 64, std);
-DEF_MMIO_IN_BE(in_be64, 64, ld);
-
-/* There is no asm instructions for 64 bits reverse loads and stores */
-static inline u64 in_le64(const volatile u64 __iomem *addr)
-{
-	return swab64(in_be64(addr));
-}
-
-static inline void out_le64(volatile u64 __iomem *addr, u64 val)
-{
-	out_be64(addr, swab64(val));
-}
-#endif /* __powerpc64__ */
-
-/*
- * Low level IO stream instructions are defined out of line for now
- */
-extern void _insb(const volatile u8 __iomem *addr, void *buf, long count);
-extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count);
-extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count);
-extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count);
-extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count);
-extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count);
-
-/* The _ns naming is historical and will be removed. For now, just #define
- * the non _ns equivalent names
- */
-#define _insw	_insw_ns
-#define _insl	_insl_ns
-#define _outsw	_outsw_ns
-#define _outsl	_outsl_ns
-
-
-/*
- * memset_io, memcpy_toio, memcpy_fromio base implementations are out of line
- */
-
-extern void _memset_io(volatile void __iomem *addr, int c, unsigned long n);
-extern void _memcpy_fromio(void *dest, const volatile void __iomem *src,
-			   unsigned long n);
-extern void _memcpy_toio(volatile void __iomem *dest, const void *src,
-			 unsigned long n);
-
-/*
- *
- * PCI and standard ISA accessors
- *
- * Those are globally defined linux accessors for devices on PCI or ISA
- * busses. They follow the Linux defined semantics. The current implementation
- * for PowerPC is as close as possible to the x86 version of these, and thus
- * provides fairly heavy weight barriers for the non-raw versions
- *
- * In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_IO
- * allowing the platform to provide its own implementation of some or all
- * of the accessors.
- */
-
-/*
- * Include the EEH definitions when EEH is enabled only so they don't get
- * in the way when building for 32 bits
- */
-#ifdef CONFIG_EEH
-#include <asm/eeh.h>
-#endif
-
-/* Shortcut to the MMIO argument pointer */
-#define PCI_IO_ADDR	volatile void __iomem *
-
-/* Indirect IO address tokens:
- *
- * When CONFIG_PPC_INDIRECT_IO is set, the platform can provide hooks
- * on all IOs. (Note that this is all 64 bits only for now)
- *
- * To help platforms who may need to differenciate MMIO addresses in
- * their hooks, a bitfield is reserved for use by the platform near the
- * top of MMIO addresses (not PIO, those have to cope the hard way).
- *
- * This bit field is 12 bits and is at the top of the IO virtual
- * addresses PCI_IO_INDIRECT_TOKEN_MASK.
- *
- * The kernel virtual space is thus:
- *
- *  0xD000000000000000		: vmalloc
- *  0xD000080000000000		: PCI PHB IO space
- *  0xD000080080000000		: ioremap
- *  0xD0000fffffffffff		: end of ioremap region
- *
- * Since the top 4 bits are reserved as the region ID, we use thus
- * the next 12 bits and keep 4 bits available for the future if the
- * virtual address space is ever to be extended.
- *
- * The direct IO mapping operations will then mask off those bits
- * before doing the actual access, though that only happen when
- * CONFIG_PPC_INDIRECT_IO is set, thus be careful when you use that
- * mechanism
- */
-
-#ifdef CONFIG_PPC_INDIRECT_IO
-#define PCI_IO_IND_TOKEN_MASK	0x0fff000000000000ul
-#define PCI_IO_IND_TOKEN_SHIFT	48
-#define PCI_FIX_ADDR(addr)						\
-	((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK))
-#define PCI_GET_ADDR_TOKEN(addr)					\
-	(((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >> 		\
-		PCI_IO_IND_TOKEN_SHIFT)
-#define PCI_SET_ADDR_TOKEN(addr, token) 				\
-do {									\
-	unsigned long __a = (unsigned long)(addr);			\
-	__a &= ~PCI_IO_IND_TOKEN_MASK;					\
-	__a |= ((unsigned long)(token)) << PCI_IO_IND_TOKEN_SHIFT;	\
-	(addr) = (void __iomem *)__a;					\
-} while(0)
-#else
-#define PCI_FIX_ADDR(addr) (addr)
-#endif
-
-
-/*
- * Non ordered and non-swapping "raw" accessors
- */
-
-static inline unsigned char __raw_readb(const volatile void __iomem *addr)
-{
-	return *(volatile unsigned char __force *)PCI_FIX_ADDR(addr);
-}
-static inline unsigned short __raw_readw(const volatile void __iomem *addr)
-{
-	return *(volatile unsigned short __force *)PCI_FIX_ADDR(addr);
-}
-static inline unsigned int __raw_readl(const volatile void __iomem *addr)
-{
-	return *(volatile unsigned int __force *)PCI_FIX_ADDR(addr);
-}
-static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
-{
-	*(volatile unsigned char __force *)PCI_FIX_ADDR(addr) = v;
-}
-static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
-{
-	*(volatile unsigned short __force *)PCI_FIX_ADDR(addr) = v;
-}
-static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
-{
-	*(volatile unsigned int __force *)PCI_FIX_ADDR(addr) = v;
-}
-
-#ifdef __powerpc64__
-static inline unsigned long __raw_readq(const volatile void __iomem *addr)
-{
-	return *(volatile unsigned long __force *)PCI_FIX_ADDR(addr);
-}
-static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr)
-{
-	*(volatile unsigned long __force *)PCI_FIX_ADDR(addr) = v;
-}
-#endif /* __powerpc64__ */
-
-/*
- *
- * PCI PIO and MMIO accessors.
- *
- *
- * On 32 bits, PIO operations have a recovery mechanism in case they trigger
- * machine checks (which they occasionally do when probing non existing
- * IO ports on some platforms, like PowerMac and 8xx).
- * I always found it to be of dubious reliability and I am tempted to get
- * rid of it one of these days. So if you think it's important to keep it,
- * please voice up asap. We never had it for 64 bits and I do not intend
- * to port it over
- */
-
-#ifdef CONFIG_PPC32
-
-#define __do_in_asm(name, op)				\
-static inline unsigned int name(unsigned int port)	\
-{							\
-	unsigned int x;					\
-	__asm__ __volatile__(				\
-		"sync\n"				\
-		"0:"	op "	%0,0,%1\n"		\
-		"1:	twi	0,%0,0\n"		\
-		"2:	isync\n"			\
-		"3:	nop\n"				\
-		"4:\n"					\
-		".section .fixup,\"ax\"\n"		\
-		"5:	li	%0,-1\n"		\
-		"	b	4b\n"			\
-		".previous\n"				\
-		".section __ex_table,\"a\"\n"		\
-		"	.align	2\n"			\
-		"	.long	0b,5b\n"		\
-		"	.long	1b,5b\n"		\
-		"	.long	2b,5b\n"		\
-		"	.long	3b,5b\n"		\
-		".previous"				\
-		: "=&r" (x)				\
-		: "r" (port + _IO_BASE)			\
-		: "memory");  				\
-	return x;					\
-}
-
-#define __do_out_asm(name, op)				\
-static inline void name(unsigned int val, unsigned int port) \
-{							\
-	__asm__ __volatile__(				\
-		"sync\n"				\
-		"0:" op " %0,0,%1\n"			\
-		"1:	sync\n"				\
-		"2:\n"					\
-		".section __ex_table,\"a\"\n"		\
-		"	.align	2\n"			\
-		"	.long	0b,2b\n"		\
-		"	.long	1b,2b\n"		\
-		".previous"				\
-		: : "r" (val), "r" (port + _IO_BASE)	\
-		: "memory");   	   	   		\
-}
-
-__do_in_asm(_rec_inb, "lbzx")
-__do_in_asm(_rec_inw, "lhbrx")
-__do_in_asm(_rec_inl, "lwbrx")
-__do_out_asm(_rec_outb, "stbx")
-__do_out_asm(_rec_outw, "sthbrx")
-__do_out_asm(_rec_outl, "stwbrx")
-
-#endif /* CONFIG_PPC32 */
-
-/* The "__do_*" operations below provide the actual "base" implementation
- * for each of the defined accessors. Some of them use the out_* functions
- * directly, some of them still use EEH, though we might change that in the
- * future. Those macros below provide the necessary argument swapping and
- * handling of the IO base for PIO.
- *
- * They are themselves used by the macros that define the actual accessors
- * and can be used by the hooks if any.
- *
- * Note that PIO operations are always defined in terms of their corresonding
- * MMIO operations. That allows platforms like iSeries who want to modify the
- * behaviour of both to only hook on the MMIO version and get both. It's also
- * possible to hook directly at the toplevel PIO operation if they have to
- * be handled differently
- */
-#define __do_writeb(val, addr)	out_8(PCI_FIX_ADDR(addr), val)
-#define __do_writew(val, addr)	out_le16(PCI_FIX_ADDR(addr), val)
-#define __do_writel(val, addr)	out_le32(PCI_FIX_ADDR(addr), val)
-#define __do_writeq(val, addr)	out_le64(PCI_FIX_ADDR(addr), val)
-#define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val)
-#define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val)
-#define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val)
-
-#ifdef CONFIG_EEH
-#define __do_readb(addr)	eeh_readb(PCI_FIX_ADDR(addr))
-#define __do_readw(addr)	eeh_readw(PCI_FIX_ADDR(addr))
-#define __do_readl(addr)	eeh_readl(PCI_FIX_ADDR(addr))
-#define __do_readq(addr)	eeh_readq(PCI_FIX_ADDR(addr))
-#define __do_readw_be(addr)	eeh_readw_be(PCI_FIX_ADDR(addr))
-#define __do_readl_be(addr)	eeh_readl_be(PCI_FIX_ADDR(addr))
-#define __do_readq_be(addr)	eeh_readq_be(PCI_FIX_ADDR(addr))
-#else /* CONFIG_EEH */
-#define __do_readb(addr)	in_8(PCI_FIX_ADDR(addr))
-#define __do_readw(addr)	in_le16(PCI_FIX_ADDR(addr))
-#define __do_readl(addr)	in_le32(PCI_FIX_ADDR(addr))
-#define __do_readq(addr)	in_le64(PCI_FIX_ADDR(addr))
-#define __do_readw_be(addr)	in_be16(PCI_FIX_ADDR(addr))
-#define __do_readl_be(addr)	in_be32(PCI_FIX_ADDR(addr))
-#define __do_readq_be(addr)	in_be64(PCI_FIX_ADDR(addr))
-#endif /* !defined(CONFIG_EEH) */
-
-#ifdef CONFIG_PPC32
-#define __do_outb(val, port)	_rec_outb(val, port)
-#define __do_outw(val, port)	_rec_outw(val, port)
-#define __do_outl(val, port)	_rec_outl(val, port)
-#define __do_inb(port)		_rec_inb(port)
-#define __do_inw(port)		_rec_inw(port)
-#define __do_inl(port)		_rec_inl(port)
-#else /* CONFIG_PPC32 */
-#define __do_outb(val, port)	writeb(val,(PCI_IO_ADDR)_IO_BASE+port);
-#define __do_outw(val, port)	writew(val,(PCI_IO_ADDR)_IO_BASE+port);
-#define __do_outl(val, port)	writel(val,(PCI_IO_ADDR)_IO_BASE+port);
-#define __do_inb(port)		readb((PCI_IO_ADDR)_IO_BASE + port);
-#define __do_inw(port)		readw((PCI_IO_ADDR)_IO_BASE + port);
-#define __do_inl(port)		readl((PCI_IO_ADDR)_IO_BASE + port);
-#endif /* !CONFIG_PPC32 */
-
-#ifdef CONFIG_EEH
-#define __do_readsb(a, b, n)	eeh_readsb(PCI_FIX_ADDR(a), (b), (n))
-#define __do_readsw(a, b, n)	eeh_readsw(PCI_FIX_ADDR(a), (b), (n))
-#define __do_readsl(a, b, n)	eeh_readsl(PCI_FIX_ADDR(a), (b), (n))
-#else /* CONFIG_EEH */
-#define __do_readsb(a, b, n)	_insb(PCI_FIX_ADDR(a), (b), (n))
-#define __do_readsw(a, b, n)	_insw(PCI_FIX_ADDR(a), (b), (n))
-#define __do_readsl(a, b, n)	_insl(PCI_FIX_ADDR(a), (b), (n))
-#endif /* !CONFIG_EEH */
-#define __do_writesb(a, b, n)	_outsb(PCI_FIX_ADDR(a),(b),(n))
-#define __do_writesw(a, b, n)	_outsw(PCI_FIX_ADDR(a),(b),(n))
-#define __do_writesl(a, b, n)	_outsl(PCI_FIX_ADDR(a),(b),(n))
-
-#define __do_insb(p, b, n)	readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
-#define __do_insw(p, b, n)	readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
-#define __do_insl(p, b, n)	readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
-#define __do_outsb(p, b, n)	writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
-#define __do_outsw(p, b, n)	writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
-#define __do_outsl(p, b, n)	writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
-
-#define __do_memset_io(addr, c, n)	\
-				_memset_io(PCI_FIX_ADDR(addr), c, n)
-#define __do_memcpy_toio(dst, src, n)	\
-				_memcpy_toio(PCI_FIX_ADDR(dst), src, n)
-
-#ifdef CONFIG_EEH
-#define __do_memcpy_fromio(dst, src, n)	\
-				eeh_memcpy_fromio(dst, PCI_FIX_ADDR(src), n)
-#else /* CONFIG_EEH */
-#define __do_memcpy_fromio(dst, src, n)	\
-				_memcpy_fromio(dst,PCI_FIX_ADDR(src),n)
-#endif /* !CONFIG_EEH */
-
-#ifdef CONFIG_PPC_INDIRECT_PIO
-#define DEF_PCI_HOOK_pio(x)	x
-#else
-#define DEF_PCI_HOOK_pio(x)	NULL
-#endif
-
-#ifdef CONFIG_PPC_INDIRECT_MMIO
-#define DEF_PCI_HOOK_mem(x)	x
-#else
-#define DEF_PCI_HOOK_mem(x)	NULL
-#endif
-
-/* Structure containing all the hooks */
-extern struct ppc_pci_io {
-
-#define DEF_PCI_AC_RET(name, ret, at, al, space, aa)	ret (*name) at;
-#define DEF_PCI_AC_NORET(name, at, al, space, aa)	void (*name) at;
-
-#include <asm/io-defs.h>
-
-#undef DEF_PCI_AC_RET
-#undef DEF_PCI_AC_NORET
-
-} ppc_pci_io;
-
-/* The inline wrappers */
-#define DEF_PCI_AC_RET(name, ret, at, al, space, aa)		\
-static inline ret name at					\
-{								\
-	if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL)	\
-		return ppc_pci_io.name al;			\
-	return __do_##name al;					\
-}
-
-#define DEF_PCI_AC_NORET(name, at, al, space, aa)		\
-static inline void name at					\
-{								\
-	if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL)		\
-		ppc_pci_io.name al;				\
-	else							\
-		__do_##name al;					\
-}
-
-#include <asm/io-defs.h>
-
-#undef DEF_PCI_AC_RET
-#undef DEF_PCI_AC_NORET
-
-/* Some drivers check for the presence of readq & writeq with
- * a #ifdef, so we make them happy here.
- */
-#ifdef __powerpc64__
-#define readq	readq
-#define writeq	writeq
-#endif
-
-/*
- * Convert a physical pointer to a virtual kernel pointer for /dev/mem
- * access
- */
-#define xlate_dev_mem_ptr(p)	__va(p)
-
-/*
- * Convert a virtual cached pointer to an uncached pointer
- */
-#define xlate_dev_kmem_ptr(p)	p
-
-/*
- * We don't do relaxed operations yet, at least not with this semantic
- */
-#define readb_relaxed(addr) readb(addr)
-#define readw_relaxed(addr) readw(addr)
-#define readl_relaxed(addr) readl(addr)
-#define readq_relaxed(addr) readq(addr)
-
-#ifdef CONFIG_PPC32
-#define mmiowb()
-#else
-/*
- * Enforce synchronisation of stores vs. spin_unlock
- * (this does it explicitly, though our implementation of spin_unlock
- * does it implicitely too)
- */
-static inline void mmiowb(void)
-{
-	unsigned long tmp;
-
-	__asm__ __volatile__("sync; li %0,0; stb %0,%1(13)"
-	: "=&r" (tmp) : "i" (offsetof(struct paca_struct, io_sync))
-	: "memory");
-}
-#endif /* !CONFIG_PPC32 */
-
-static inline void iosync(void)
-{
-        __asm__ __volatile__ ("sync" : : : "memory");
-}
-
-/* Enforce in-order execution of data I/O.
- * No distinction between read/write on PPC; use eieio for all three.
- * Those are fairly week though. They don't provide a barrier between
- * MMIO and cacheable storage nor do they provide a barrier vs. locks,
- * they only provide barriers between 2 __raw MMIO operations and
- * possibly break write combining.
- */
-#define iobarrier_rw() eieio()
-#define iobarrier_r()  eieio()
-#define iobarrier_w()  eieio()
-
-
-/*
- * output pause versions need a delay at least for the
- * w83c105 ide controller in a p610.
- */
-#define inb_p(port)             inb(port)
-#define outb_p(val, port)       (udelay(1), outb((val), (port)))
-#define inw_p(port)             inw(port)
-#define outw_p(val, port)       (udelay(1), outw((val), (port)))
-#define inl_p(port)             inl(port)
-#define outl_p(val, port)       (udelay(1), outl((val), (port)))
-
-
-#define IO_SPACE_LIMIT ~(0UL)
-
-
-/**
- * ioremap     -   map bus memory into CPU space
- * @address:   bus address of the memory
- * @size:      size of the resource to map
- *
- * ioremap performs a platform specific sequence of operations to
- * make bus memory CPU accessible via the readb/readw/readl/writeb/
- * writew/writel functions and the other mmio helpers. The returned
- * address is not guaranteed to be usable directly as a virtual
- * address.
- *
- * We provide a few variations of it:
- *
- * * ioremap is the standard one and provides non-cacheable guarded mappings
- *   and can be hooked by the platform via ppc_md
- *
- * * ioremap_prot allows to specify the page flags as an argument and can
- *   also be hooked by the platform via ppc_md.
- *
- * * ioremap_nocache is identical to ioremap
- *
- * * ioremap_wc enables write combining
- *
- * * iounmap undoes such a mapping and can be hooked
- *
- * * __ioremap_at (and the pending __iounmap_at) are low level functions to
- *   create hand-made mappings for use only by the PCI code and cannot
- *   currently be hooked. Must be page aligned.
- *
- * * __ioremap is the low level implementation used by ioremap and
- *   ioremap_prot and cannot be hooked (but can be used by a hook on one
- *   of the previous ones)
- *
- * * __ioremap_caller is the same as above but takes an explicit caller
- *   reference rather than using __builtin_return_address(0)
- *
- * * __iounmap, is the low level implementation used by iounmap and cannot
- *   be hooked (but can be used by a hook on iounmap)
- *
- */
-extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
-extern void __iomem *ioremap_prot(phys_addr_t address, unsigned long size,
-				  unsigned long flags);
-extern void __iomem *ioremap_wc(phys_addr_t address, unsigned long size);
-#define ioremap_nocache(addr, size)	ioremap((addr), (size))
-
-extern void iounmap(volatile void __iomem *addr);
-
-extern void __iomem *__ioremap(phys_addr_t, unsigned long size,
-			       unsigned long flags);
-extern void __iomem *__ioremap_caller(phys_addr_t, unsigned long size,
-				      unsigned long flags, void *caller);
-
-extern void __iounmap(volatile void __iomem *addr);
-
-extern void __iomem * __ioremap_at(phys_addr_t pa, void *ea,
-				   unsigned long size, unsigned long flags);
-extern void __iounmap_at(void *ea, unsigned long size);
-
-/*
- * When CONFIG_PPC_INDIRECT_IO is set, we use the generic iomap implementation
- * which needs some additional definitions here. They basically allow PIO
- * space overall to be 1GB. This will work as long as we never try to use
- * iomap to map MMIO below 1GB which should be fine on ppc64
- */
-#define HAVE_ARCH_PIO_SIZE		1
-#define PIO_OFFSET			0x00000000UL
-#define PIO_MASK			(FULL_IO_SIZE - 1)
-#define PIO_RESERVED			(FULL_IO_SIZE)
-
-#define mmio_read16be(addr)		readw_be(addr)
-#define mmio_read32be(addr)		readl_be(addr)
-#define mmio_write16be(val, addr)	writew_be(val, addr)
-#define mmio_write32be(val, addr)	writel_be(val, addr)
-#define mmio_insb(addr, dst, count)	readsb(addr, dst, count)
-#define mmio_insw(addr, dst, count)	readsw(addr, dst, count)
-#define mmio_insl(addr, dst, count)	readsl(addr, dst, count)
-#define mmio_outsb(addr, src, count)	writesb(addr, src, count)
-#define mmio_outsw(addr, src, count)	writesw(addr, src, count)
-#define mmio_outsl(addr, src, count)	writesl(addr, src, count)
-
-/**
- *	virt_to_phys	-	map virtual addresses to physical
- *	@address: address to remap
- *
- *	The returned physical address is the physical (CPU) mapping for
- *	the memory address given. It is only valid to use this function on
- *	addresses directly mapped or allocated via kmalloc.
- *
- *	This function does not give bus mappings for DMA transfers. In
- *	almost all conceivable cases a device driver should not be using
- *	this function
- */
-static inline unsigned long virt_to_phys(volatile void * address)
-{
-	return __pa((unsigned long)address);
-}
-
-/**
- *	phys_to_virt	-	map physical address to virtual
- *	@address: address to remap
- *
- *	The returned virtual address is a current CPU mapping for
- *	the memory address given. It is only valid to use this function on
- *	addresses that have a kernel mapping
- *
- *	This function does not handle bus mappings for DMA transfers. In
- *	almost all conceivable cases a device driver should not be using
- *	this function
- */
-static inline void * phys_to_virt(unsigned long address)
-{
-	return (void *)__va(address);
-}
-
-/*
- * Change "struct page" to physical address.
- */
-#define page_to_phys(page)	((phys_addr_t)page_to_pfn(page) << PAGE_SHIFT)
-
-/*
- * 32 bits still uses virt_to_bus() for it's implementation of DMA
- * mappings se we have to keep it defined here. We also have some old
- * drivers (shame shame shame) that use bus_to_virt() and haven't been
- * fixed yet so I need to define it here.
- */
-#ifdef CONFIG_PPC32
-
-static inline unsigned long virt_to_bus(volatile void * address)
-{
-        if (address == NULL)
-		return 0;
-        return __pa(address) + PCI_DRAM_OFFSET;
-}
-
-static inline void * bus_to_virt(unsigned long address)
-{
-        if (address == 0)
-		return NULL;
-        return __va(address - PCI_DRAM_OFFSET);
-}
-
-#define page_to_bus(page)	(page_to_phys(page) + PCI_DRAM_OFFSET)
-
-#endif /* CONFIG_PPC32 */
-
-/* access ports */
-#define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) |  (_v))
-#define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
-
-#define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) |  (_v))
-#define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v))
-
-#define setbits8(_addr, _v) out_8((_addr), in_8(_addr) |  (_v))
-#define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v))
-
-/* Clear and set bits in one shot.  These macros can be used to clear and
- * set multiple bits in a register using a single read-modify-write.  These
- * macros can also be used to set a multiple-bit bit pattern using a mask,
- * by specifying the mask in the 'clear' parameter and the new bit pattern
- * in the 'set' parameter.
- */
-
-#define clrsetbits(type, addr, clear, set) \
-	out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
-
-#ifdef __powerpc64__
-#define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set)
-#define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set)
-#endif
-
-#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
-#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
-
-#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
-#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
-
-#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
-
-void __iomem *devm_ioremap_prot(struct device *dev, resource_size_t offset,
-				size_t size, unsigned long flags);
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_POWERPC_IO_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/io_event_irq.h b/ANDROID_3.4.5/arch/powerpc/include/asm/io_event_irq.h
deleted file mode 100644
index b1a9a1be..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/io_event_irq.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright 2010, 2011 Mark Nelson and Tseng-Hui (Frank) Lin, IBM Corporation
- *
- *  This program is free software; you can redistribute it and/or
- *  modify it under the terms of the GNU General Public License
- *  as published by the Free Software Foundation; either version
- *  2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_POWERPC_IO_EVENT_IRQ_H
-#define _ASM_POWERPC_IO_EVENT_IRQ_H
-
-#include <linux/types.h>
-#include <linux/notifier.h>
-
-#define PSERIES_IOEI_RPC_MAX_LEN 216
-
-#define PSERIES_IOEI_TYPE_ERR_DETECTED		0x01
-#define PSERIES_IOEI_TYPE_ERR_RECOVERED		0x02
-#define PSERIES_IOEI_TYPE_EVENT			0x03
-#define PSERIES_IOEI_TYPE_RPC_PASS_THRU		0x04
-
-#define PSERIES_IOEI_SUBTYPE_NOT_APP		0x00
-#define PSERIES_IOEI_SUBTYPE_REBALANCE_REQ	0x01
-#define PSERIES_IOEI_SUBTYPE_NODE_ONLINE	0x03
-#define PSERIES_IOEI_SUBTYPE_NODE_OFFLINE	0x04
-#define PSERIES_IOEI_SUBTYPE_DUMP_SIZE_CHANGE	0x05
-#define PSERIES_IOEI_SUBTYPE_TORRENT_IRV_UPDATE	0x06
-#define PSERIES_IOEI_SUBTYPE_TORRENT_HFI_CFGED	0x07
-
-#define PSERIES_IOEI_SCOPE_NOT_APP		0x00
-#define PSERIES_IOEI_SCOPE_RIO_HUB		0x36
-#define PSERIES_IOEI_SCOPE_RIO_BRIDGE		0x37
-#define PSERIES_IOEI_SCOPE_PHB			0x38
-#define PSERIES_IOEI_SCOPE_EADS_GLOBAL		0x39
-#define PSERIES_IOEI_SCOPE_EADS_SLOT		0x3A
-#define PSERIES_IOEI_SCOPE_TORRENT_HUB		0x3B
-#define PSERIES_IOEI_SCOPE_SERVICE_PROC		0x51
-
-/* Platform Event Log Format, Version 6, data portition of IO event section */
-struct pseries_io_event {
-	uint8_t event_type;		/* 0x00 IO-Event Type		*/
-	uint8_t rpc_data_len;		/* 0x01 RPC data length		*/
-	uint8_t scope;			/* 0x02 Error/Event Scope	*/
-	uint8_t event_subtype;		/* 0x03 I/O-Event Sub-Type	*/
-	uint32_t drc_index;		/* 0x04 DRC Index		*/
-	uint8_t rpc_data[PSERIES_IOEI_RPC_MAX_LEN];
-					/* 0x08 RPC Data (0-216 bytes,	*/
-					/* padded to 4 bytes alignment)	*/
-};
-
-extern struct atomic_notifier_head pseries_ioei_notifier_list;
-
-#endif /* _ASM_POWERPC_IO_EVENT_IRQ_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/ioctl.h b/ANDROID_3.4.5/arch/powerpc/include/asm/ioctl.h
deleted file mode 100644
index 57d68304..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/ioctl.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef _ASM_POWERPC_IOCTL_H
-#define _ASM_POWERPC_IOCTL_H
-
-#define _IOC_SIZEBITS	13
-#define _IOC_DIRBITS	3
-
-#define _IOC_NONE	1U
-#define _IOC_READ	2U
-#define _IOC_WRITE	4U
-
-#include <asm-generic/ioctl.h>
-
-#endif	/* _ASM_POWERPC_IOCTL_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/ioctls.h b/ANDROID_3.4.5/arch/powerpc/include/asm/ioctls.h
deleted file mode 100644
index e9b78870..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/ioctls.h
+++ /dev/null
@@ -1,116 +0,0 @@
-#ifndef _ASM_POWERPC_IOCTLS_H
-#define _ASM_POWERPC_IOCTLS_H
-
-#include <asm/ioctl.h>
-
-#define FIOCLEX		_IO('f', 1)
-#define FIONCLEX	_IO('f', 2)
-#define FIOASYNC	_IOW('f', 125, int)
-#define FIONBIO		_IOW('f', 126, int)
-#define FIONREAD	_IOR('f', 127, int)
-#define TIOCINQ		FIONREAD
-#define FIOQSIZE	_IOR('f', 128, loff_t)
-
-#define TIOCGETP	_IOR('t', 8, struct sgttyb)
-#define TIOCSETP	_IOW('t', 9, struct sgttyb)
-#define TIOCSETN	_IOW('t', 10, struct sgttyb)	/* TIOCSETP wo flush */
-
-#define TIOCSETC	_IOW('t', 17, struct tchars)
-#define TIOCGETC	_IOR('t', 18, struct tchars)
-#define TCGETS		_IOR('t', 19, struct termios)
-#define TCSETS		_IOW('t', 20, struct termios)
-#define TCSETSW		_IOW('t', 21, struct termios)
-#define TCSETSF		_IOW('t', 22, struct termios)
-
-#define TCGETA		_IOR('t', 23, struct termio)
-#define TCSETA		_IOW('t', 24, struct termio)
-#define TCSETAW		_IOW('t', 25, struct termio)
-#define TCSETAF		_IOW('t', 28, struct termio)
-
-#define TCSBRK		_IO('t', 29)
-#define TCXONC		_IO('t', 30)
-#define TCFLSH		_IO('t', 31)
-
-#define TIOCSWINSZ	_IOW('t', 103, struct winsize)
-#define TIOCGWINSZ	_IOR('t', 104, struct winsize)
-#define	TIOCSTART	_IO('t', 110)		/* start output, like ^Q */
-#define	TIOCSTOP	_IO('t', 111)		/* stop output, like ^S */
-#define TIOCOUTQ        _IOR('t', 115, int)     /* output queue size */
-
-#define TIOCGLTC	_IOR('t', 116, struct ltchars)
-#define TIOCSLTC	_IOW('t', 117, struct ltchars)
-#define TIOCSPGRP	_IOW('t', 118, int)
-#define TIOCGPGRP	_IOR('t', 119, int)
-
-#define TIOCEXCL	0x540C
-#define TIOCNXCL	0x540D
-#define TIOCSCTTY	0x540E
-
-#define TIOCSTI		0x5412
-#define TIOCMGET	0x5415
-#define TIOCMBIS	0x5416
-#define TIOCMBIC	0x5417
-#define TIOCMSET	0x5418
-# define TIOCM_LE	0x001
-# define TIOCM_DTR	0x002
-# define TIOCM_RTS	0x004
-# define TIOCM_ST	0x008
-# define TIOCM_SR	0x010
-# define TIOCM_CTS	0x020
-# define TIOCM_CAR	0x040
-# define TIOCM_RNG	0x080
-# define TIOCM_DSR	0x100
-# define TIOCM_CD	TIOCM_CAR
-# define TIOCM_RI	TIOCM_RNG
-#define TIOCM_OUT1	0x2000
-#define TIOCM_OUT2	0x4000
-#define TIOCM_LOOP	0x8000
-
-#define TIOCGSOFTCAR	0x5419
-#define TIOCSSOFTCAR	0x541A
-#define TIOCLINUX	0x541C
-#define TIOCCONS	0x541D
-#define TIOCGSERIAL	0x541E
-#define TIOCSSERIAL	0x541F
-#define TIOCPKT		0x5420
-# define TIOCPKT_DATA		 0
-# define TIOCPKT_FLUSHREAD	 1
-# define TIOCPKT_FLUSHWRITE	 2
-# define TIOCPKT_STOP		 4
-# define TIOCPKT_START		 8
-# define TIOCPKT_NOSTOP		16
-# define TIOCPKT_DOSTOP		32
-# define TIOCPKT_IOCTL		64
-
-
-#define TIOCNOTTY	0x5422
-#define TIOCSETD	0x5423
-#define TIOCGETD	0x5424
-#define TCSBRKP		0x5425	/* Needed for POSIX tcsendbreak() */
-#define TIOCSBRK	0x5427  /* BSD compatibility */
-#define TIOCCBRK	0x5428  /* BSD compatibility */
-#define TIOCGSID	0x5429  /* Return the session ID of FD */
-#define TIOCGRS485	0x542e
-#define TIOCSRS485	0x542f
-#define TIOCGPTN	_IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
-#define TIOCSPTLCK	_IOW('T',0x31, int)  /* Lock/unlock Pty */
-#define TIOCGDEV	_IOR('T',0x32, unsigned int) /* Get primary device node of /dev/console */
-#define TIOCSIG		_IOW('T',0x36, int)  /* Generate signal on Pty slave */
-#define TIOCVHANGUP	0x5437
-
-#define TIOCSERCONFIG	0x5453
-#define TIOCSERGWILD	0x5454
-#define TIOCSERSWILD	0x5455
-#define TIOCGLCKTRMIOS	0x5456
-#define TIOCSLCKTRMIOS	0x5457
-#define TIOCSERGSTRUCT	0x5458 /* For debugging only */
-#define TIOCSERGETLSR   0x5459 /* Get line status register */
-  /* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
-# define TIOCSER_TEMT    0x01	/* Transmitter physically empty */
-#define TIOCSERGETMULTI 0x545A /* Get multiport config  */
-#define TIOCSERSETMULTI 0x545B /* Set multiport config */
-
-#define TIOCMIWAIT	0x545C	/* wait for a change on serial input line(s) */
-#define TIOCGICOUNT	0x545D	/* read serial port inline interrupt counts */
-
-#endif	/* _ASM_POWERPC_IOCTLS_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/iommu.h b/ANDROID_3.4.5/arch/powerpc/include/asm/iommu.h
deleted file mode 100644
index 957a83f4..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/iommu.h
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
- * Rewrite, cleanup:
- * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
- * 
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- * 
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- * 
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-
-#ifndef _ASM_IOMMU_H
-#define _ASM_IOMMU_H
-#ifdef __KERNEL__
-
-#include <linux/compiler.h>
-#include <linux/spinlock.h>
-#include <linux/device.h>
-#include <linux/dma-mapping.h>
-#include <linux/bitops.h>
-#include <asm/machdep.h>
-#include <asm/types.h>
-
-#define IOMMU_PAGE_SHIFT      12
-#define IOMMU_PAGE_SIZE       (ASM_CONST(1) << IOMMU_PAGE_SHIFT)
-#define IOMMU_PAGE_MASK       (~((1 << IOMMU_PAGE_SHIFT) - 1))
-#define IOMMU_PAGE_ALIGN(addr) _ALIGN_UP(addr, IOMMU_PAGE_SIZE)
-
-/* Boot time flags */
-extern int iommu_is_off;
-extern int iommu_force_on;
-
-/* Pure 2^n version of get_order */
-static __inline__ __attribute_const__ int get_iommu_order(unsigned long size)
-{
-	return __ilog2((size - 1) >> IOMMU_PAGE_SHIFT) + 1;
-}
-
-
-/*
- * IOMAP_MAX_ORDER defines the largest contiguous block
- * of dma space we can get.  IOMAP_MAX_ORDER = 13
- * allows up to 2**12 pages (4096 * 4096) = 16 MB
- */
-#define IOMAP_MAX_ORDER		13
-
-struct iommu_table {
-	unsigned long  it_busno;     /* Bus number this table belongs to */
-	unsigned long  it_size;      /* Size of iommu table in entries */
-	unsigned long  it_offset;    /* Offset into global table */
-	unsigned long  it_base;      /* mapped address of tce table */
-	unsigned long  it_index;     /* which iommu table this is */
-	unsigned long  it_type;      /* type: PCI or Virtual Bus */
-	unsigned long  it_blocksize; /* Entries in each block (cacheline) */
-	unsigned long  it_hint;      /* Hint for next alloc */
-	unsigned long  it_largehint; /* Hint for large allocs */
-	unsigned long  it_halfpoint; /* Breaking point for small/large allocs */
-	spinlock_t     it_lock;      /* Protects it_map */
-	unsigned long *it_map;       /* A simple allocation bitmap for now */
-};
-
-struct scatterlist;
-
-static inline void set_iommu_table_base(struct device *dev, void *base)
-{
-	dev->archdata.dma_data.iommu_table_base = base;
-}
-
-static inline void *get_iommu_table_base(struct device *dev)
-{
-	return dev->archdata.dma_data.iommu_table_base;
-}
-
-/* Frees table for an individual device node */
-extern void iommu_free_table(struct iommu_table *tbl, const char *node_name);
-
-/* Initializes an iommu_table based in values set in the passed-in
- * structure
- */
-extern struct iommu_table *iommu_init_table(struct iommu_table * tbl,
-					    int nid);
-
-extern int iommu_map_sg(struct device *dev, struct iommu_table *tbl,
-			struct scatterlist *sglist, int nelems,
-			unsigned long mask, enum dma_data_direction direction,
-			struct dma_attrs *attrs);
-extern void iommu_unmap_sg(struct iommu_table *tbl, struct scatterlist *sglist,
-			   int nelems, enum dma_data_direction direction,
-			   struct dma_attrs *attrs);
-
-extern void *iommu_alloc_coherent(struct device *dev, struct iommu_table *tbl,
-				  size_t size, dma_addr_t *dma_handle,
-				  unsigned long mask, gfp_t flag, int node);
-extern void iommu_free_coherent(struct iommu_table *tbl, size_t size,
-				void *vaddr, dma_addr_t dma_handle);
-extern dma_addr_t iommu_map_page(struct device *dev, struct iommu_table *tbl,
-				 struct page *page, unsigned long offset,
-				 size_t size, unsigned long mask,
-				 enum dma_data_direction direction,
-				 struct dma_attrs *attrs);
-extern void iommu_unmap_page(struct iommu_table *tbl, dma_addr_t dma_handle,
-			     size_t size, enum dma_data_direction direction,
-			     struct dma_attrs *attrs);
-
-extern void iommu_init_early_pSeries(void);
-extern void iommu_init_early_dart(void);
-extern void iommu_init_early_pasemi(void);
-
-#ifdef CONFIG_PCI
-extern void pci_iommu_init(void);
-extern void pci_direct_iommu_init(void);
-#else
-static inline void pci_iommu_init(void) { }
-#endif
-
-extern void alloc_dart_table(void);
-#if defined(CONFIG_PPC64) && defined(CONFIG_PM)
-static inline void iommu_save(void)
-{
-	if (ppc_md.iommu_save)
-		ppc_md.iommu_save();
-}
-
-static inline void iommu_restore(void)
-{
-	if (ppc_md.iommu_restore)
-		ppc_md.iommu_restore();
-}
-#endif
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_IOMMU_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/ipcbuf.h b/ANDROID_3.4.5/arch/powerpc/include/asm/ipcbuf.h
deleted file mode 100644
index 2c3e1d94..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/ipcbuf.h
+++ /dev/null
@@ -1,34 +0,0 @@
-#ifndef _ASM_POWERPC_IPCBUF_H
-#define _ASM_POWERPC_IPCBUF_H
-
-/*
- * The ipc64_perm structure for the powerpc is identical to
- * kern_ipc_perm as we have always had 32-bit UIDs and GIDs in the
- * kernel.  Note extra padding because this structure is passed back
- * and forth between kernel and user space.  Pad space is left for:
- *	- 1 32-bit value to fill up for 8-byte alignment
- *	- 2 miscellaneous 64-bit values
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/types.h>
-
-struct ipc64_perm
-{
-	__kernel_key_t	key;
-	__kernel_uid_t	uid;
-	__kernel_gid_t	gid;
-	__kernel_uid_t	cuid;
-	__kernel_gid_t	cgid;
-	__kernel_mode_t	mode;
-	unsigned int	seq;
-	unsigned int	__pad1;
-	unsigned long long __unused1;
-	unsigned long long __unused2;
-};
-
-#endif /* _ASM_POWERPC_IPCBUF_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/ipic.h b/ANDROID_3.4.5/arch/powerpc/include/asm/ipic.h
deleted file mode 100644
index fb598299..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/ipic.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * IPIC external definitions and structure.
- *
- * Maintainer: Kumar Gala <galak@kernel.crashing.org>
- *
- * Copyright 2005 Freescale Semiconductor, Inc
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-#ifdef __KERNEL__
-#ifndef __ASM_IPIC_H__
-#define __ASM_IPIC_H__
-
-#include <linux/irq.h>
-
-/* Flags when we init the IPIC */
-#define IPIC_SPREADMODE_GRP_A	0x00000001
-#define IPIC_SPREADMODE_GRP_B	0x00000002
-#define IPIC_SPREADMODE_GRP_C	0x00000004
-#define IPIC_SPREADMODE_GRP_D	0x00000008
-#define IPIC_SPREADMODE_MIX_A	0x00000010
-#define IPIC_SPREADMODE_MIX_B	0x00000020
-#define IPIC_DISABLE_MCP_OUT	0x00000040
-#define IPIC_IRQ0_MCP		0x00000080
-
-/* IPIC registers offsets */
-#define IPIC_SICFR	0x00	/* System Global Interrupt Configuration Register */
-#define IPIC_SIVCR	0x04	/* System Global Interrupt Vector Register */
-#define IPIC_SIPNR_H	0x08	/* System Internal Interrupt Pending Register (HIGH) */
-#define IPIC_SIPNR_L	0x0C	/* System Internal Interrupt Pending Register (LOW) */
-#define IPIC_SIPRR_A	0x10	/* System Internal Interrupt group A Priority Register */
-#define IPIC_SIPRR_B	0x14	/* System Internal Interrupt group B Priority Register */
-#define IPIC_SIPRR_C	0x18	/* System Internal Interrupt group C Priority Register */
-#define IPIC_SIPRR_D	0x1C	/* System Internal Interrupt group D Priority Register */
-#define IPIC_SIMSR_H	0x20	/* System Internal Interrupt Mask Register (HIGH) */
-#define IPIC_SIMSR_L	0x24	/* System Internal Interrupt Mask Register (LOW) */
-#define IPIC_SICNR	0x28	/* System Internal Interrupt Control Register */
-#define IPIC_SEPNR	0x2C	/* System External Interrupt Pending Register */
-#define IPIC_SMPRR_A	0x30	/* System Mixed Interrupt group A Priority Register */
-#define IPIC_SMPRR_B	0x34	/* System Mixed Interrupt group B Priority Register */
-#define IPIC_SEMSR	0x38	/* System External Interrupt Mask Register */
-#define IPIC_SECNR	0x3C	/* System External Interrupt Control Register */
-#define IPIC_SERSR	0x40	/* System Error Status Register */
-#define IPIC_SERMR	0x44	/* System Error Mask Register */
-#define IPIC_SERCR	0x48	/* System Error Control Register */
-#define IPIC_SIFCR_H	0x50	/* System Internal Interrupt Force Register (HIGH) */
-#define IPIC_SIFCR_L	0x54	/* System Internal Interrupt Force Register (LOW) */
-#define IPIC_SEFCR	0x58	/* System External Interrupt Force Register */
-#define IPIC_SERFR	0x5C	/* System Error Force Register */
-#define IPIC_SCVCR	0x60	/* System Critical Interrupt Vector Register */
-#define IPIC_SMVCR	0x64	/* System Management Interrupt Vector Register */
-
-enum ipic_prio_grp {
-	IPIC_INT_GRP_A = IPIC_SIPRR_A,
-	IPIC_INT_GRP_D = IPIC_SIPRR_D,
-	IPIC_MIX_GRP_A = IPIC_SMPRR_A,
-	IPIC_MIX_GRP_B = IPIC_SMPRR_B,
-};
-
-enum ipic_mcp_irq {
-	IPIC_MCP_IRQ0 = 0,
-	IPIC_MCP_WDT  = 1,
-	IPIC_MCP_SBA  = 2,
-	IPIC_MCP_PCI1 = 5,
-	IPIC_MCP_PCI2 = 6,
-	IPIC_MCP_MU   = 7,
-};
-
-extern int ipic_set_priority(unsigned int irq, unsigned int priority);
-extern void ipic_set_highest_priority(unsigned int irq);
-extern void ipic_set_default_priority(void);
-extern void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq);
-extern void ipic_disable_mcp(enum ipic_mcp_irq mcp_irq);
-extern u32 ipic_get_mcp_status(void);
-extern void ipic_clear_mcp_status(u32 mask);
-
-extern struct ipic * ipic_init(struct device_node *node, unsigned int flags);
-extern unsigned int ipic_get_irq(void);
-
-#endif /* __ASM_IPIC_H__ */
-#endif /* __KERNEL__ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/irq.h b/ANDROID_3.4.5/arch/powerpc/include/asm/irq.h
deleted file mode 100644
index 0e40843a..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/irq.h
+++ /dev/null
@@ -1,79 +0,0 @@
-#ifdef __KERNEL__
-#ifndef _ASM_POWERPC_IRQ_H
-#define _ASM_POWERPC_IRQ_H
-
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/irqdomain.h>
-#include <linux/threads.h>
-#include <linux/list.h>
-#include <linux/radix-tree.h>
-
-#include <asm/types.h>
-#include <linux/atomic.h>
-
-
-extern atomic_t ppc_n_lost_interrupts;
-
-/* This number is used when no interrupt has been assigned */
-#define NO_IRQ			(0)
-
-/* Total number of virq in the platform */
-#define NR_IRQS		CONFIG_NR_IRQS
-
-/* Same thing, used by the generic IRQ code */
-#define NR_IRQS_LEGACY		NUM_ISA_INTERRUPTS
-
-extern irq_hw_number_t virq_to_hw(unsigned int virq);
-
-/**
- * irq_early_init - Init irq remapping subsystem
- */
-extern void irq_early_init(void);
-
-static __inline__ int irq_canonicalize(int irq)
-{
-	return irq;
-}
-
-extern int distribute_irqs;
-
-struct irqaction;
-struct pt_regs;
-
-#define __ARCH_HAS_DO_SOFTIRQ
-
-#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
-/*
- * Per-cpu stacks for handling critical, debug and machine check
- * level interrupts.
- */
-extern struct thread_info *critirq_ctx[NR_CPUS];
-extern struct thread_info *dbgirq_ctx[NR_CPUS];
-extern struct thread_info *mcheckirq_ctx[NR_CPUS];
-extern void exc_lvl_ctx_init(void);
-#else
-#define exc_lvl_ctx_init()
-#endif
-
-/*
- * Per-cpu stacks for handling hard and soft interrupts.
- */
-extern struct thread_info *hardirq_ctx[NR_CPUS];
-extern struct thread_info *softirq_ctx[NR_CPUS];
-
-extern void irq_ctx_init(void);
-extern void call_do_softirq(struct thread_info *tp);
-extern int call_handle_irq(int irq, void *p1,
-			   struct thread_info *tp, void *func);
-extern void do_IRQ(struct pt_regs *regs);
-
-int irq_choose_cpu(const struct cpumask *mask);
-
-#endif /* _ASM_IRQ_H */
-#endif /* __KERNEL__ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/irq_regs.h b/ANDROID_3.4.5/arch/powerpc/include/asm/irq_regs.h
deleted file mode 100644
index ba94b51a..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/irq_regs.h
+++ /dev/null
@@ -1,2 +0,0 @@
-#include <asm-generic/irq_regs.h>
-
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/irqflags.h b/ANDROID_3.4.5/arch/powerpc/include/asm/irqflags.h
deleted file mode 100644
index 6f9b6e23..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/irqflags.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * IRQ flags handling
- */
-#ifndef _ASM_IRQFLAGS_H
-#define _ASM_IRQFLAGS_H
-
-#ifndef __ASSEMBLY__
-/*
- * Get definitions for arch_local_save_flags(x), etc.
- */
-#include <asm/hw_irq.h>
-
-#else
-#ifdef CONFIG_TRACE_IRQFLAGS
-#ifdef CONFIG_IRQSOFF_TRACER
-/*
- * Since the ftrace irqsoff latency trace checks CALLER_ADDR1,
- * which is the stack frame here, we need to force a stack frame
- * in case we came from user space.
- */
-#define TRACE_WITH_FRAME_BUFFER(func)		\
-	mflr	r0;				\
-	stdu	r1, -32(r1);			\
-	std	r0, 16(r1);			\
-	stdu	r1, -32(r1);			\
-	bl func;				\
-	ld	r1, 0(r1);			\
-	ld	r1, 0(r1);
-#else
-#define TRACE_WITH_FRAME_BUFFER(func)		\
-	bl func;
-#endif
-
-/*
- * Most of the CPU's IRQ-state tracing is done from assembly code; we
- * have to call a C function so call a wrapper that saves all the
- * C-clobbered registers.
- */
-#define TRACE_ENABLE_INTS	TRACE_WITH_FRAME_BUFFER(.trace_hardirqs_on)
-#define TRACE_DISABLE_INTS	TRACE_WITH_FRAME_BUFFER(.trace_hardirqs_off)
-
-/*
- * This is used by assembly code to soft-disable interrupts
- */
-#define SOFT_DISABLE_INTS(__rA, __rB)		\
-	lbz	__rA,PACASOFTIRQEN(r13);	\
-	lbz	__rB,PACAIRQHAPPENED(r13);	\
-	cmpwi	cr0,__rA,0;			\
-	li	__rA,0;				\
-	ori	__rB,__rB,PACA_IRQ_HARD_DIS;	\
-	stb	__rB,PACAIRQHAPPENED(r13);	\
-	beq	44f;				\
-	stb	__rA,PACASOFTIRQEN(r13);	\
-	TRACE_DISABLE_INTS;			\
-44:
-
-#else
-#define TRACE_ENABLE_INTS
-#define TRACE_DISABLE_INTS
-
-#define SOFT_DISABLE_INTS(__rA, __rB)		\
-	lbz	__rA,PACAIRQHAPPENED(r13);	\
-	li	__rB,0;				\
-	ori	__rA,__rA,PACA_IRQ_HARD_DIS;	\
-	stb	__rB,PACASOFTIRQEN(r13);	\
-	stb	__rA,PACAIRQHAPPENED(r13)
-#endif
-#endif
-
-#endif
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/jump_label.h b/ANDROID_3.4.5/arch/powerpc/include/asm/jump_label.h
deleted file mode 100644
index ae098c43..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/jump_label.h
+++ /dev/null
@@ -1,45 +0,0 @@
-#ifndef _ASM_POWERPC_JUMP_LABEL_H
-#define _ASM_POWERPC_JUMP_LABEL_H
-
-/*
- * Copyright 2010 Michael Ellerman, IBM Corp.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/types.h>
-
-#include <asm/feature-fixups.h>
-
-#define JUMP_ENTRY_TYPE		stringify_in_c(FTR_ENTRY_LONG)
-#define JUMP_LABEL_NOP_SIZE	4
-
-static __always_inline bool arch_static_branch(struct static_key *key)
-{
-	asm goto("1:\n\t"
-		 "nop\n\t"
-		 ".pushsection __jump_table,  \"aw\"\n\t"
-		 JUMP_ENTRY_TYPE "1b, %l[l_yes], %c0\n\t"
-		 ".popsection \n\t"
-		 : :  "i" (key) : : l_yes);
-	return false;
-l_yes:
-	return true;
-}
-
-#ifdef CONFIG_PPC64
-typedef u64 jump_label_t;
-#else
-typedef u32 jump_label_t;
-#endif
-
-struct jump_entry {
-	jump_label_t code;
-	jump_label_t target;
-	jump_label_t key;
-};
-
-#endif /* _ASM_POWERPC_JUMP_LABEL_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/kdebug.h b/ANDROID_3.4.5/arch/powerpc/include/asm/kdebug.h
deleted file mode 100644
index ae6d2067..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/kdebug.h
+++ /dev/null
@@ -1,15 +0,0 @@
-#ifndef _ASM_POWERPC_KDEBUG_H
-#define _ASM_POWERPC_KDEBUG_H
-#ifdef __KERNEL__
-
-/* Grossly misnamed. */
-enum die_val {
-	DIE_OOPS = 1,
-	DIE_IABR_MATCH,
-	DIE_DABR_MATCH,
-	DIE_BPT,
-	DIE_SSTEP,
-};
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_KDEBUG_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/kdump.h b/ANDROID_3.4.5/arch/powerpc/include/asm/kdump.h
deleted file mode 100644
index c9776202..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/kdump.h
+++ /dev/null
@@ -1,46 +0,0 @@
-#ifndef _PPC64_KDUMP_H
-#define _PPC64_KDUMP_H
-
-#include <asm/page.h>
-
-#define KDUMP_KERNELBASE	0x2000000
-
-/* How many bytes to reserve at zero for kdump. The reserve limit should
- * be greater or equal to the trampoline's end address.
- * Reserve to the end of the FWNMI area, see head_64.S */
-#define KDUMP_RESERVE_LIMIT	0x10000 /* 64K */
-
-#ifdef CONFIG_CRASH_DUMP
-
-/*
- * On PPC64 translation is disabled during trampoline setup, so we use
- * physical addresses. Though on PPC32 translation is already enabled,
- * so we can't do the same. Luckily create_trampoline() creates relative
- * branches, so we can just add the PAGE_OFFSET and don't worry about it.
- */
-#ifdef __powerpc64__
-#define KDUMP_TRAMPOLINE_START	0x0100
-#define KDUMP_TRAMPOLINE_END	0x3000
-#else
-#define KDUMP_TRAMPOLINE_START	(0x0100 + PAGE_OFFSET)
-#define KDUMP_TRAMPOLINE_END	(0x3000 + PAGE_OFFSET)
-#endif /* __powerpc64__ */
-
-#define KDUMP_MIN_TCE_ENTRIES	2048
-
-#endif /* CONFIG_CRASH_DUMP */
-
-#ifndef __ASSEMBLY__
-
-#if defined(CONFIG_CRASH_DUMP) && !defined(CONFIG_NONSTATIC_KERNEL)
-extern void reserve_kdump_trampoline(void);
-extern void setup_kdump_trampoline(void);
-#else
-/* !CRASH_DUMP || !NONSTATIC_KERNEL */
-static inline void reserve_kdump_trampoline(void) { ; }
-static inline void setup_kdump_trampoline(void) { ; }
-#endif
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* __PPC64_KDUMP_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/kexec.h b/ANDROID_3.4.5/arch/powerpc/include/asm/kexec.h
deleted file mode 100644
index 16d7e33d..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/kexec.h
+++ /dev/null
@@ -1,113 +0,0 @@
-#ifndef _ASM_POWERPC_KEXEC_H
-#define _ASM_POWERPC_KEXEC_H
-#ifdef __KERNEL__
-
-#if defined(CONFIG_FSL_BOOKE) || defined(CONFIG_44x)
-
-/*
- * On FSL-BookE we setup a 1:1 mapping which covers the first 2GiB of memory
- * and therefore we can only deal with memory within this range
- */
-#define KEXEC_SOURCE_MEMORY_LIMIT	(2 * 1024 * 1024 * 1024UL - 1)
-#define KEXEC_DESTINATION_MEMORY_LIMIT	(2 * 1024 * 1024 * 1024UL - 1)
-#define KEXEC_CONTROL_MEMORY_LIMIT	(2 * 1024 * 1024 * 1024UL - 1)
-
-#else
-
-/*
- * Maximum page that is mapped directly into kernel memory.
- * XXX: Since we copy virt we can use any page we allocate
- */
-#define KEXEC_SOURCE_MEMORY_LIMIT (-1UL)
-
-/*
- * Maximum address we can reach in physical address mode.
- * XXX: I want to allow initrd in highmem. Otherwise set to rmo on LPAR.
- */
-#define KEXEC_DESTINATION_MEMORY_LIMIT (-1UL)
-
-/* Maximum address we can use for the control code buffer */
-#ifdef __powerpc64__
-#define KEXEC_CONTROL_MEMORY_LIMIT (-1UL)
-#else
-/* TASK_SIZE, probably left over from use_mm ?? */
-#define KEXEC_CONTROL_MEMORY_LIMIT TASK_SIZE
-#endif
-#endif
-
-#define KEXEC_CONTROL_PAGE_SIZE 4096
-
-/* The native architecture */
-#ifdef __powerpc64__
-#define KEXEC_ARCH KEXEC_ARCH_PPC64
-#else
-#define KEXEC_ARCH KEXEC_ARCH_PPC
-#endif
-
-#define KEXEC_STATE_NONE 0
-#define KEXEC_STATE_IRQS_OFF 1
-#define KEXEC_STATE_REAL_MODE 2
-
-#ifndef __ASSEMBLY__
-#include <asm/reg.h>
-
-typedef void (*crash_shutdown_t)(void);
-
-#ifdef CONFIG_KEXEC
-
-/*
- * This function is responsible for capturing register states if coming
- * via panic or invoking dump using sysrq-trigger.
- */
-static inline void crash_setup_regs(struct pt_regs *newregs,
-					struct pt_regs *oldregs)
-{
-	if (oldregs)
-		memcpy(newregs, oldregs, sizeof(*newregs));
-	else
-		ppc_save_regs(newregs);
-}
-
-extern void kexec_smp_wait(void);	/* get and clear naca physid, wait for
-					  master to copy new code to 0 */
-extern int crashing_cpu;
-extern void crash_send_ipi(void (*crash_ipi_callback)(struct pt_regs *));
-
-struct kimage;
-struct pt_regs;
-extern void default_machine_kexec(struct kimage *image);
-extern int default_machine_kexec_prepare(struct kimage *image);
-extern void default_machine_crash_shutdown(struct pt_regs *regs);
-extern int crash_shutdown_register(crash_shutdown_t handler);
-extern int crash_shutdown_unregister(crash_shutdown_t handler);
-
-extern void machine_kexec_simple(struct kimage *image);
-extern void crash_kexec_secondary(struct pt_regs *regs);
-extern int overlaps_crashkernel(unsigned long start, unsigned long size);
-extern void reserve_crashkernel(void);
-extern void machine_kexec_mask_interrupts(void);
-
-#else /* !CONFIG_KEXEC */
-static inline void crash_kexec_secondary(struct pt_regs *regs) { }
-
-static inline int overlaps_crashkernel(unsigned long start, unsigned long size)
-{
-	return 0;
-}
-
-static inline void reserve_crashkernel(void) { ; }
-
-static inline int crash_shutdown_register(crash_shutdown_t handler)
-{
-	return 0;
-}
-
-static inline int crash_shutdown_unregister(crash_shutdown_t handler)
-{
-	return 0;
-}
-
-#endif /* CONFIG_KEXEC */
-#endif /* ! __ASSEMBLY__ */
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_KEXEC_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/keylargo.h b/ANDROID_3.4.5/arch/powerpc/include/asm/keylargo.h
deleted file mode 100644
index 2156315d..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/keylargo.h
+++ /dev/null
@@ -1,261 +0,0 @@
-#ifndef _ASM_POWERPC_KEYLARGO_H
-#define _ASM_POWERPC_KEYLARGO_H
-#ifdef __KERNEL__
-/*
- * keylargo.h: definitions for using the "KeyLargo" I/O controller chip.
- *
- */
-
-/* "Pangea" chipset has keylargo device-id 0x25 while core99
- * has device-id 0x22. The rev. of the pangea one is 0, so we
- * fake an artificial rev. in keylargo_rev by oring 0x100
- */
-#define KL_PANGEA_REV		0x100
-
-/* offset from base for feature control registers */
-#define KEYLARGO_MBCR		0x34	/* KL Only, Media bay control/status */
-#define KEYLARGO_FCR0		0x38
-#define KEYLARGO_FCR1		0x3c
-#define KEYLARGO_FCR2		0x40
-#define KEYLARGO_FCR3		0x44
-#define KEYLARGO_FCR4		0x48
-#define KEYLARGO_FCR5		0x4c	/* Pangea only */
-
-/* K2 additional FCRs */
-#define K2_FCR6			0x34
-#define K2_FCR7			0x30
-#define K2_FCR8			0x2c
-#define K2_FCR9			0x28
-#define K2_FCR10		0x24
-
-/* GPIO registers */
-#define KEYLARGO_GPIO_LEVELS0		0x50
-#define KEYLARGO_GPIO_LEVELS1		0x54
-#define KEYLARGO_GPIO_EXTINT_0		0x58
-#define KEYLARGO_GPIO_EXTINT_CNT	18
-#define KEYLARGO_GPIO_0			0x6A
-#define KEYLARGO_GPIO_CNT		17
-#define KEYLARGO_GPIO_EXTINT_DUAL_EDGE	0x80
-#define KEYLARGO_GPIO_OUTPUT_ENABLE	0x04
-#define KEYLARGO_GPIO_OUTOUT_DATA	0x01
-#define KEYLARGO_GPIO_INPUT_DATA	0x02
-
-/* K2 does only extint GPIOs and does 51 of them */
-#define K2_GPIO_EXTINT_0		0x58
-#define K2_GPIO_EXTINT_CNT		51
-
-/* Specific GPIO regs */
-
-#define KL_GPIO_MODEM_RESET		(KEYLARGO_GPIO_0+0x03)
-#define KL_GPIO_MODEM_POWER		(KEYLARGO_GPIO_0+0x02) /* Pangea */
-
-#define KL_GPIO_SOUND_POWER		(KEYLARGO_GPIO_0+0x05)
-
-/* Hrm... this one is only to be used on Pismo. It seems to also
- * control the timebase enable on other machines. Still to be
- * experimented... --BenH.
- */
-#define KL_GPIO_FW_CABLE_POWER		(KEYLARGO_GPIO_0+0x09)
-#define KL_GPIO_TB_ENABLE		(KEYLARGO_GPIO_0+0x09)
-
-#define KL_GPIO_ETH_PHY_RESET		(KEYLARGO_GPIO_0+0x10)
-
-#define KL_GPIO_EXTINT_CPU1		(KEYLARGO_GPIO_0+0x0a)
-#define KL_GPIO_EXTINT_CPU1_ASSERT	0x04
-#define KL_GPIO_EXTINT_CPU1_RELEASE	0x38
-
-#define KL_GPIO_RESET_CPU0		(KEYLARGO_GPIO_EXTINT_0+0x03)
-#define KL_GPIO_RESET_CPU1		(KEYLARGO_GPIO_EXTINT_0+0x04)
-#define KL_GPIO_RESET_CPU2		(KEYLARGO_GPIO_EXTINT_0+0x0f)
-#define KL_GPIO_RESET_CPU3		(KEYLARGO_GPIO_EXTINT_0+0x10)
-
-#define KL_GPIO_PMU_MESSAGE_IRQ		(KEYLARGO_GPIO_EXTINT_0+0x09)
-#define KL_GPIO_PMU_MESSAGE_BIT		KEYLARGO_GPIO_INPUT_DATA
-
-#define KL_GPIO_MEDIABAY_IRQ		(KEYLARGO_GPIO_EXTINT_0+0x0e)
-
-#define KL_GPIO_AIRPORT_0		(KEYLARGO_GPIO_EXTINT_0+0x0a)
-#define KL_GPIO_AIRPORT_1		(KEYLARGO_GPIO_EXTINT_0+0x0d)
-#define KL_GPIO_AIRPORT_2		(KEYLARGO_GPIO_0+0x0d)
-#define KL_GPIO_AIRPORT_3		(KEYLARGO_GPIO_0+0x0e)
-#define KL_GPIO_AIRPORT_4		(KEYLARGO_GPIO_0+0x0f)
-
-/*
- * Bits in feature control register. Those bits different for K2 are
- * listed separately
- */
-#define KL_MBCR_MB0_PCI_ENABLE		0x00000800	/* exist ? */
-#define KL_MBCR_MB0_IDE_ENABLE		0x00001000
-#define KL_MBCR_MB0_FLOPPY_ENABLE	0x00002000	/* exist ? */
-#define KL_MBCR_MB0_SOUND_ENABLE	0x00004000	/* hrm... */
-#define KL_MBCR_MB0_DEV_MASK		0x00007800
-#define KL_MBCR_MB0_DEV_POWER		0x00000400
-#define KL_MBCR_MB0_DEV_RESET		0x00000200
-#define KL_MBCR_MB0_ENABLE		0x00000100
-#define KL_MBCR_MB1_PCI_ENABLE		0x08000000	/* exist ? */
-#define KL_MBCR_MB1_IDE_ENABLE		0x10000000
-#define KL_MBCR_MB1_FLOPPY_ENABLE	0x20000000	/* exist ? */
-#define KL_MBCR_MB1_SOUND_ENABLE	0x40000000	/* hrm... */
-#define KL_MBCR_MB1_DEV_MASK		0x78000000
-#define KL_MBCR_MB1_DEV_POWER		0x04000000
-#define KL_MBCR_MB1_DEV_RESET		0x02000000
-#define KL_MBCR_MB1_ENABLE		0x01000000
-
-#define KL0_SCC_B_INTF_ENABLE		0x00000001	/* (KL Only) */
-#define KL0_SCC_A_INTF_ENABLE		0x00000002
-#define KL0_SCC_SLOWPCLK		0x00000004
-#define KL0_SCC_RESET			0x00000008
-#define KL0_SCCA_ENABLE			0x00000010
-#define KL0_SCCB_ENABLE			0x00000020
-#define KL0_SCC_CELL_ENABLE		0x00000040
-#define KL0_IRDA_HIGH_BAND		0x00000100	/* (KL Only) */
-#define KL0_IRDA_SOURCE2_SEL		0x00000200	/* (KL Only) */
-#define KL0_IRDA_SOURCE1_SEL		0x00000400	/* (KL Only) */
-#define KL0_PG_USB0_PMI_ENABLE		0x00000400	/* (Pangea/Intrepid Only) */
-#define KL0_IRDA_RESET			0x00000800	/* (KL Only) */
-#define KL0_PG_USB0_REF_SUSPEND_SEL	0x00000800	/* (Pangea/Intrepid Only) */
-#define KL0_IRDA_DEFAULT1		0x00001000	/* (KL Only) */
-#define KL0_PG_USB0_REF_SUSPEND		0x00001000	/* (Pangea/Intrepid Only) */
-#define KL0_IRDA_DEFAULT0		0x00002000	/* (KL Only) */
-#define KL0_PG_USB0_PAD_SUSPEND		0x00002000	/* (Pangea/Intrepid Only) */
-#define KL0_IRDA_FAST_CONNECT		0x00004000	/* (KL Only) */
-#define KL0_PG_USB1_PMI_ENABLE		0x00004000	/* (Pangea/Intrepid Only) */
-#define KL0_IRDA_ENABLE			0x00008000	/* (KL Only) */
-#define KL0_PG_USB1_REF_SUSPEND_SEL	0x00008000	/* (Pangea/Intrepid Only) */
-#define KL0_IRDA_CLK32_ENABLE		0x00010000	/* (KL Only) */
-#define KL0_PG_USB1_REF_SUSPEND		0x00010000	/* (Pangea/Intrepid Only) */
-#define KL0_IRDA_CLK19_ENABLE		0x00020000	/* (KL Only) */
-#define KL0_PG_USB1_PAD_SUSPEND		0x00020000	/* (Pangea/Intrepid Only) */
-#define KL0_USB0_PAD_SUSPEND0		0x00040000
-#define KL0_USB0_PAD_SUSPEND1		0x00080000
-#define KL0_USB0_CELL_ENABLE		0x00100000
-#define KL0_USB1_PAD_SUSPEND0		0x00400000
-#define KL0_USB1_PAD_SUSPEND1		0x00800000
-#define KL0_USB1_CELL_ENABLE		0x01000000
-#define KL0_USB_REF_SUSPEND		0x10000000	/* (KL Only) */
-
-#define KL0_SERIAL_ENABLE		(KL0_SCC_B_INTF_ENABLE | \
-					KL0_SCC_SLOWPCLK | \
-					KL0_SCC_CELL_ENABLE | KL0_SCCA_ENABLE)
-
-#define KL1_USB2_PMI_ENABLE		0x00000001	/* Intrepid only */
-#define KL1_AUDIO_SEL_22MCLK		0x00000002	/* KL/Pangea only */
-#define KL1_USB2_REF_SUSPEND_SEL	0x00000002	/* Intrepid only */
-#define KL1_USB2_REF_SUSPEND		0x00000004	/* Intrepid only */
-#define KL1_AUDIO_CLK_ENABLE_BIT	0x00000008	/* KL/Pangea only */
-#define KL1_USB2_PAD_SUSPEND_SEL	0x00000008	/* Intrepid only */
-#define KL1_USB2_PAD_SUSPEND0		0x00000010	/* Intrepid only */
-#define KL1_AUDIO_CLK_OUT_ENABLE	0x00000020	/* KL/Pangea only */
-#define KL1_USB2_PAD_SUSPEND1		0x00000020	/* Intrepid only */
-#define KL1_AUDIO_CELL_ENABLE		0x00000040	/* KL/Pangea only */
-#define KL1_USB2_CELL_ENABLE		0x00000040	/* Intrepid only */
-#define KL1_AUDIO_CHOOSE		0x00000080	/* KL/Pangea only */
-#define KL1_I2S0_CHOOSE			0x00000200	/* KL Only */
-#define KL1_I2S0_CELL_ENABLE		0x00000400
-#define KL1_I2S0_CLK_ENABLE_BIT		0x00001000
-#define KL1_I2S0_ENABLE			0x00002000
-#define KL1_I2S1_CELL_ENABLE		0x00020000
-#define KL1_I2S1_CLK_ENABLE_BIT		0x00080000
-#define KL1_I2S1_ENABLE			0x00100000
-#define KL1_EIDE0_ENABLE		0x00800000	/* KL/Intrepid Only */
-#define KL1_EIDE0_RESET_N		0x01000000	/* KL/Intrepid Only */
-#define KL1_EIDE1_ENABLE		0x04000000	/* KL Only */
-#define KL1_EIDE1_RESET_N		0x08000000	/* KL Only */
-#define KL1_UIDE_ENABLE			0x20000000	/* KL/Pangea Only */
-#define KL1_UIDE_RESET_N		0x40000000	/* KL/Pangea Only */
-
-#define KL2_IOBUS_ENABLE		0x00000002
-#define KL2_SLEEP_STATE_BIT		0x00000100	/* KL Only */
-#define KL2_PG_STOP_ALL_CLOCKS		0x00000100	/* Pangea Only */
-#define KL2_MPIC_ENABLE			0x00020000
-#define KL2_CARDSLOT_RESET		0x00040000	/* Pangea/Intrepid Only */
-#define KL2_ALT_DATA_OUT		0x02000000	/* KL Only ??? */
-#define KL2_MEM_IS_BIG			0x04000000
-#define KL2_CARDSEL_16			0x08000000
-
-#define KL3_SHUTDOWN_PLL_TOTAL		0x00000001	/* KL/Pangea only */
-#define KL3_SHUTDOWN_PLLKW6		0x00000002	/* KL/Pangea only */
-#define KL3_IT_SHUTDOWN_PLL3		0x00000002	/* Intrepid only */
-#define KL3_SHUTDOWN_PLLKW4		0x00000004	/* KL/Pangea only */
-#define KL3_IT_SHUTDOWN_PLL2		0x00000004	/* Intrepid only */
-#define KL3_SHUTDOWN_PLLKW35		0x00000008	/* KL/Pangea only */
-#define KL3_IT_SHUTDOWN_PLL1		0x00000008	/* Intrepid only */
-#define KL3_SHUTDOWN_PLLKW12		0x00000010	/* KL Only */
-#define KL3_IT_ENABLE_PLL3_SHUTDOWN	0x00000010	/* Intrepid only */
-#define KL3_PLL_RESET			0x00000020	/* KL/Pangea only */
-#define KL3_IT_ENABLE_PLL2_SHUTDOWN	0x00000020	/* Intrepid only */
-#define KL3_IT_ENABLE_PLL1_SHUTDOWN	0x00000010	/* Intrepid only */
-#define KL3_SHUTDOWN_PLL2X		0x00000080	/* KL Only */
-#define KL3_CLK66_ENABLE		0x00000100	/* KL Only */
-#define KL3_CLK49_ENABLE		0x00000200
-#define KL3_CLK45_ENABLE		0x00000400
-#define KL3_CLK31_ENABLE		0x00000800	/* KL/Pangea only */
-#define KL3_TIMER_CLK18_ENABLE		0x00001000
-#define KL3_I2S1_CLK18_ENABLE		0x00002000
-#define KL3_I2S0_CLK18_ENABLE		0x00004000
-#define KL3_VIA_CLK16_ENABLE		0x00008000	/* KL/Pangea only */
-#define KL3_IT_VIA_CLK32_ENABLE		0x00008000	/* Intrepid only */
-#define KL3_STOPPING33_ENABLED		0x00080000	/* KL Only */
-#define KL3_PG_PLL_ENABLE_TEST		0x00080000	/* Pangea Only */
-
-/* Intrepid USB bus 2, port 0,1 */
-#define KL3_IT_PORT_WAKEUP_ENABLE(p)		(0x00080000 << ((p)<<3))
-#define KL3_IT_PORT_RESUME_WAKE_EN(p)		(0x00040000 << ((p)<<3))
-#define KL3_IT_PORT_CONNECT_WAKE_EN(p)		(0x00020000 << ((p)<<3))
-#define KL3_IT_PORT_DISCONNECT_WAKE_EN(p)	(0x00010000 << ((p)<<3))
-#define KL3_IT_PORT_RESUME_STAT(p)		(0x00300000 << ((p)<<3))
-#define KL3_IT_PORT_CONNECT_STAT(p)		(0x00200000 << ((p)<<3))
-#define KL3_IT_PORT_DISCONNECT_STAT(p)		(0x00100000 << ((p)<<3))
-
-/* Port 0,1 : bus 0, port 2,3 : bus 1 */
-#define KL4_PORT_WAKEUP_ENABLE(p)	(0x00000008 << ((p)<<3))
-#define KL4_PORT_RESUME_WAKE_EN(p)	(0x00000004 << ((p)<<3))
-#define KL4_PORT_CONNECT_WAKE_EN(p)	(0x00000002 << ((p)<<3))
-#define KL4_PORT_DISCONNECT_WAKE_EN(p)	(0x00000001 << ((p)<<3))
-#define KL4_PORT_RESUME_STAT(p)		(0x00000040 << ((p)<<3))
-#define KL4_PORT_CONNECT_STAT(p)	(0x00000020 << ((p)<<3))
-#define KL4_PORT_DISCONNECT_STAT(p)	(0x00000010 << ((p)<<3))
-
-/* Pangea and Intrepid only */
-#define KL5_VIA_USE_CLK31		0000000001	/* Pangea Only */
-#define KL5_SCC_USE_CLK31		0x00000002	/* Pangea Only */
-#define KL5_PWM_CLK32_EN		0x00000004
-#define KL5_CLK3_68_EN			0x00000010
-#define KL5_CLK32_EN			0x00000020
-
-
-/* K2 definitions */
-#define K2_FCR0_USB0_SWRESET		0x00200000
-#define K2_FCR0_USB1_SWRESET		0x02000000
-#define K2_FCR0_RING_PME_DISABLE	0x08000000
-
-#define K2_FCR1_PCI1_BUS_RESET_N	0x00000010
-#define K2_FCR1_PCI1_SLEEP_RESET_EN	0x00000020
-#define K2_FCR1_I2S0_CELL_ENABLE	0x00000400
-#define K2_FCR1_I2S0_RESET		0x00000800
-#define K2_FCR1_I2S0_CLK_ENABLE_BIT	0x00001000
-#define K2_FCR1_I2S0_ENABLE    		0x00002000
-#define K2_FCR1_PCI1_CLK_ENABLE		0x00004000
-#define K2_FCR1_FW_CLK_ENABLE		0x00008000
-#define K2_FCR1_FW_RESET_N		0x00010000
-#define K2_FCR1_I2S1_CELL_ENABLE	0x00020000
-#define K2_FCR1_I2S1_CLK_ENABLE_BIT	0x00080000
-#define K2_FCR1_I2S1_ENABLE		0x00100000
-#define K2_FCR1_GMAC_CLK_ENABLE		0x00400000
-#define K2_FCR1_GMAC_POWER_DOWN		0x00800000
-#define K2_FCR1_GMAC_RESET_N		0x01000000
-#define K2_FCR1_SATA_CLK_ENABLE		0x02000000
-#define K2_FCR1_SATA_POWER_DOWN		0x04000000
-#define K2_FCR1_SATA_RESET_N		0x08000000
-#define K2_FCR1_UATA_CLK_ENABLE		0x10000000
-#define K2_FCR1_UATA_RESET_N		0x40000000
-#define K2_FCR1_UATA_CHOOSE_CLK66	0x80000000
-
-/* Shasta definitions */
-#define SH_FCR1_I2S2_CELL_ENABLE	0x00000010
-#define SH_FCR1_I2S2_CLK_ENABLE_BIT	0x00000040
-#define SH_FCR1_I2S2_ENABLE		0x00000080
-#define SH_FCR3_I2S2_CLK18_ENABLE	0x00008000
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_KEYLARGO_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/kgdb.h b/ANDROID_3.4.5/arch/powerpc/include/asm/kgdb.h
deleted file mode 100644
index 9db24e77..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/kgdb.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * The PowerPC (32/64) specific defines / externs for KGDB.  Based on
- * the previous 32bit and 64bit specific files, which had the following
- * copyrights:
- *
- * PPC64 Mods (C) 2005 Frank Rowand (frowand@mvista.com)
- * PPC Mods (C) 2004 Tom Rini (trini@mvista.com)
- * PPC Mods (C) 2003 John Whitney (john.whitney@timesys.com)
- * PPC Mods (C) 1998 Michael Tesch (tesch@cs.wisc.edu)
- *
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- * Author: Tom Rini <trini@kernel.crashing.org>
- *
- * 2006 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifdef __KERNEL__
-#ifndef __POWERPC_KGDB_H__
-#define __POWERPC_KGDB_H__
-
-#ifndef __ASSEMBLY__
-
-#define BREAK_INSTR_SIZE	4
-#define BUFMAX			((NUMREGBYTES * 2) + 512)
-#define OUTBUFMAX		((NUMREGBYTES * 2) + 512)
-static inline void arch_kgdb_breakpoint(void)
-{
-	asm(".long 0x7d821008"); /* twge r2, r2 */
-}
-#define CACHE_FLUSH_IS_SAFE	1
-#define DBG_MAX_REG_NUM     70
-
-/* The number bytes of registers we have to save depends on a few
- * things.  For 64bit we default to not including vector registers and
- * vector state registers. */
-#ifdef CONFIG_PPC64
-/*
- * 64 bit (8 byte) registers:
- *   32 gpr, 32 fpr, nip, msr, link, ctr
- * 32 bit (4 byte) registers:
- *   ccr, xer, fpscr
- */
-#define NUMREGBYTES		((68 * 8) + (3 * 4))
-#define NUMCRITREGBYTES		184
-#else /* CONFIG_PPC32 */
-/* On non-E500 family PPC32 we determine the size by picking the last
- * register we need, but on E500 we skip sections so we list what we
- * need to store, and add it up. */
-#ifndef CONFIG_E500
-#define MAXREG			(PT_FPSCR+1)
-#else
-/* 32 GPRs (8 bytes), nip, msr, ccr, link, ctr, xer, acc (8 bytes), spefscr*/
-#define MAXREG                 ((32*2)+6+2+1)
-#endif
-#define NUMREGBYTES		(MAXREG * sizeof(int))
-/* CR/LR, R1, R2, R13-R31 inclusive. */
-#define NUMCRITREGBYTES		(23 * sizeof(int))
-#endif /* 32/64 */
-#endif /* !(__ASSEMBLY__) */
-#endif /* !__POWERPC_KGDB_H__ */
-#endif /* __KERNEL__ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/kmap_types.h b/ANDROID_3.4.5/arch/powerpc/include/asm/kmap_types.h
deleted file mode 100644
index bca8fdcd..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/kmap_types.h
+++ /dev/null
@@ -1,45 +0,0 @@
-#ifndef _ASM_POWERPC_KMAP_TYPES_H
-#define _ASM_POWERPC_KMAP_TYPES_H
-
-#ifdef __KERNEL__
-
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-enum km_type {
-	KM_BOUNCE_READ,
-	KM_SKB_SUNRPC_DATA,
-	KM_SKB_DATA_SOFTIRQ,
-	KM_USER0,
-	KM_USER1,
-	KM_BIO_SRC_IRQ,
-	KM_BIO_DST_IRQ,
-	KM_PTE0,
-	KM_PTE1,
-	KM_IRQ0,
-	KM_IRQ1,
-	KM_SOFTIRQ0,
-	KM_SOFTIRQ1,
-	KM_PPC_SYNC_PAGE,
-	KM_PPC_SYNC_ICACHE,
-	KM_KDB,
-	KM_TYPE_NR
-};
-
-/*
- * This is a temporary build fix that (so they say on lkml....) should no longer
- * be required after 2.6.33, because of changes planned to the kmap code.
- * Let's try to remove this cruft then.
- */
-#ifdef CONFIG_DEBUG_HIGHMEM
-#define KM_NMI		(-1)
-#define KM_NMI_PTE	(-1)
-#define KM_IRQ_PTE	(-1)
-#endif
-
-#endif	/* __KERNEL__ */
-#endif	/* _ASM_POWERPC_KMAP_TYPES_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/kprobes.h b/ANDROID_3.4.5/arch/powerpc/include/asm/kprobes.h
deleted file mode 100644
index be0171af..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/kprobes.h
+++ /dev/null
@@ -1,118 +0,0 @@
-#ifndef _ASM_POWERPC_KPROBES_H
-#define _ASM_POWERPC_KPROBES_H
-#ifdef __KERNEL__
-/*
- *  Kernel Probes (KProbes)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Copyright (C) IBM Corporation, 2002, 2004
- *
- * 2002-Oct	Created by Vamsi Krishna S <vamsi_krishna@in.ibm.com> Kernel
- *		Probes initial implementation ( includes suggestions from
- *		Rusty Russell).
- * 2004-Nov	Modified for PPC64 by Ananth N Mavinakayanahalli
- *		<ananth@in.ibm.com>
- */
-#include <linux/types.h>
-#include <linux/ptrace.h>
-#include <linux/percpu.h>
-
-#define  __ARCH_WANT_KPROBES_INSN_SLOT
-
-struct pt_regs;
-struct kprobe;
-
-typedef unsigned int kprobe_opcode_t;
-#define BREAKPOINT_INSTRUCTION	0x7fe00008	/* trap */
-#define MAX_INSN_SIZE 1
-
-#define IS_TW(instr)		(((instr) & 0xfc0007fe) == 0x7c000008)
-#define IS_TD(instr)		(((instr) & 0xfc0007fe) == 0x7c000088)
-#define IS_TDI(instr)		(((instr) & 0xfc000000) == 0x08000000)
-#define IS_TWI(instr)		(((instr) & 0xfc000000) == 0x0c000000)
-
-#ifdef CONFIG_PPC64
-/*
- * 64bit powerpc uses function descriptors.
- * Handle cases where:
- * 		- User passes a <.symbol> or <module:.symbol>
- * 		- User passes a <symbol> or <module:symbol>
- * 		- User passes a non-existent symbol, kallsyms_lookup_name
- * 		  returns 0. Don't deref the NULL pointer in that case
- */
-#define kprobe_lookup_name(name, addr)					\
-{									\
-	addr = (kprobe_opcode_t *)kallsyms_lookup_name(name);		\
-	if (addr) {							\
-		char *colon;						\
-		if ((colon = strchr(name, ':')) != NULL) {		\
-			colon++;					\
-			if (*colon != '\0' && *colon != '.')		\
-				addr = *(kprobe_opcode_t **)addr;	\
-		} else if (name[0] != '.')				\
-			addr = *(kprobe_opcode_t **)addr;		\
-	} else {							\
-		char dot_name[KSYM_NAME_LEN];				\
-		dot_name[0] = '.';					\
-		dot_name[1] = '\0';					\
-		strncat(dot_name, name, KSYM_NAME_LEN - 2);		\
-		addr = (kprobe_opcode_t *)kallsyms_lookup_name(dot_name); \
-	}								\
-}
-
-#define is_trap(instr)	(IS_TW(instr) || IS_TD(instr) || \
-			IS_TWI(instr) || IS_TDI(instr))
-#else
-/* Use stock kprobe_lookup_name since ppc32 doesn't use function descriptors */
-#define is_trap(instr)	(IS_TW(instr) || IS_TWI(instr))
-#endif
-
-#define flush_insn_slot(p)	do { } while (0)
-#define kretprobe_blacklist_size 0
-
-void kretprobe_trampoline(void);
-extern void arch_remove_kprobe(struct kprobe *p);
-
-/* Architecture specific copy of original instruction */
-struct arch_specific_insn {
-	/* copy of original instruction */
-	kprobe_opcode_t *insn;
-	/*
-	 * Set in kprobes code, initially to 0. If the instruction can be
-	 * eumulated, this is set to 1, if not, to -1.
-	 */
-	int boostable;
-};
-
-struct prev_kprobe {
-	struct kprobe *kp;
-	unsigned long status;
-	unsigned long saved_msr;
-};
-
-/* per-cpu kprobe control block */
-struct kprobe_ctlblk {
-	unsigned long kprobe_status;
-	unsigned long kprobe_saved_msr;
-	struct pt_regs jprobe_saved_regs;
-	struct prev_kprobe prev_kprobe;
-};
-
-extern int kprobe_exceptions_notify(struct notifier_block *self,
-					unsigned long val, void *data);
-extern int kprobe_fault_handler(struct pt_regs *regs, int trapnr);
-#endif /* __KERNEL__ */
-#endif	/* _ASM_POWERPC_KPROBES_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/kvm.h b/ANDROID_3.4.5/arch/powerpc/include/asm/kvm.h
deleted file mode 100644
index b921c3f4..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/kvm.h
+++ /dev/null
@@ -1,329 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, version 2, as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
- *
- * Copyright IBM Corp. 2007
- *
- * Authors: Hollis Blanchard <hollisb@us.ibm.com>
- */
-
-#ifndef __LINUX_KVM_POWERPC_H
-#define __LINUX_KVM_POWERPC_H
-
-#include <linux/types.h>
-
-/* Select powerpc specific features in <linux/kvm.h> */
-#define __KVM_HAVE_SPAPR_TCE
-#define __KVM_HAVE_PPC_SMT
-
-struct kvm_regs {
-	__u64 pc;
-	__u64 cr;
-	__u64 ctr;
-	__u64 lr;
-	__u64 xer;
-	__u64 msr;
-	__u64 srr0;
-	__u64 srr1;
-	__u64 pid;
-
-	__u64 sprg0;
-	__u64 sprg1;
-	__u64 sprg2;
-	__u64 sprg3;
-	__u64 sprg4;
-	__u64 sprg5;
-	__u64 sprg6;
-	__u64 sprg7;
-
-	__u64 gpr[32];
-};
-
-#define KVM_SREGS_E_IMPL_NONE	0
-#define KVM_SREGS_E_IMPL_FSL	1
-
-#define KVM_SREGS_E_FSL_PIDn	(1 << 0) /* PID1/PID2 */
-
-/*
- * Feature bits indicate which sections of the sregs struct are valid,
- * both in KVM_GET_SREGS and KVM_SET_SREGS.  On KVM_SET_SREGS, registers
- * corresponding to unset feature bits will not be modified.  This allows
- * restoring a checkpoint made without that feature, while keeping the
- * default values of the new registers.
- *
- * KVM_SREGS_E_BASE contains:
- * CSRR0/1 (refers to SRR2/3 on 40x)
- * ESR
- * DEAR
- * MCSR
- * TSR
- * TCR
- * DEC
- * TB
- * VRSAVE (USPRG0)
- */
-#define KVM_SREGS_E_BASE		(1 << 0)
-
-/*
- * KVM_SREGS_E_ARCH206 contains:
- *
- * PIR
- * MCSRR0/1
- * DECAR
- * IVPR
- */
-#define KVM_SREGS_E_ARCH206		(1 << 1)
-
-/*
- * Contains EPCR, plus the upper half of 64-bit registers
- * that are 32-bit on 32-bit implementations.
- */
-#define KVM_SREGS_E_64			(1 << 2)
-
-#define KVM_SREGS_E_SPRG8		(1 << 3)
-#define KVM_SREGS_E_MCIVPR		(1 << 4)
-
-/*
- * IVORs are used -- contains IVOR0-15, plus additional IVORs
- * in combination with an appropriate feature bit.
- */
-#define KVM_SREGS_E_IVOR		(1 << 5)
-
-/*
- * Contains MAS0-4, MAS6-7, TLBnCFG, MMUCFG.
- * Also TLBnPS if MMUCFG[MAVN] = 1.
- */
-#define KVM_SREGS_E_ARCH206_MMU		(1 << 6)
-
-/* DBSR, DBCR, IAC, DAC, DVC */
-#define KVM_SREGS_E_DEBUG		(1 << 7)
-
-/* Enhanced debug -- DSRR0/1, SPRG9 */
-#define KVM_SREGS_E_ED			(1 << 8)
-
-/* Embedded Floating Point (SPE) -- IVOR32-34 if KVM_SREGS_E_IVOR */
-#define KVM_SREGS_E_SPE			(1 << 9)
-
-/* External Proxy (EXP) -- EPR */
-#define KVM_SREGS_EXP			(1 << 10)
-
-/* External PID (E.PD) -- EPSC/EPLC */
-#define KVM_SREGS_E_PD			(1 << 11)
-
-/* Processor Control (E.PC) -- IVOR36-37 if KVM_SREGS_E_IVOR */
-#define KVM_SREGS_E_PC			(1 << 12)
-
-/* Page table (E.PT) -- EPTCFG */
-#define KVM_SREGS_E_PT			(1 << 13)
-
-/* Embedded Performance Monitor (E.PM) -- IVOR35 if KVM_SREGS_E_IVOR */
-#define KVM_SREGS_E_PM			(1 << 14)
-
-/*
- * Special updates:
- *
- * Some registers may change even while a vcpu is not running.
- * To avoid losing these changes, by default these registers are
- * not updated by KVM_SET_SREGS.  To force an update, set the bit
- * in u.e.update_special corresponding to the register to be updated.
- *
- * The update_special field is zero on return from KVM_GET_SREGS.
- *
- * When restoring a checkpoint, the caller can set update_special
- * to 0xffffffff to ensure that everything is restored, even new features
- * that the caller doesn't know about.
- */
-#define KVM_SREGS_E_UPDATE_MCSR		(1 << 0)
-#define KVM_SREGS_E_UPDATE_TSR		(1 << 1)
-#define KVM_SREGS_E_UPDATE_DEC		(1 << 2)
-#define KVM_SREGS_E_UPDATE_DBSR		(1 << 3)
-
-/*
- * In KVM_SET_SREGS, reserved/pad fields must be left untouched from a
- * previous KVM_GET_REGS.
- *
- * Unless otherwise indicated, setting any register with KVM_SET_SREGS
- * directly sets its value.  It does not trigger any special semantics such
- * as write-one-to-clear.  Calling KVM_SET_SREGS on an unmodified struct
- * just received from KVM_GET_SREGS is always a no-op.
- */
-struct kvm_sregs {
-	__u32 pvr;
-	union {
-		struct {
-			__u64 sdr1;
-			struct {
-				struct {
-					__u64 slbe;
-					__u64 slbv;
-				} slb[64];
-			} ppc64;
-			struct {
-				__u32 sr[16];
-				__u64 ibat[8];
-				__u64 dbat[8];
-			} ppc32;
-		} s;
-		struct {
-			union {
-				struct { /* KVM_SREGS_E_IMPL_FSL */
-					__u32 features; /* KVM_SREGS_E_FSL_ */
-					__u32 svr;
-					__u64 mcar;
-					__u32 hid0;
-
-					/* KVM_SREGS_E_FSL_PIDn */
-					__u32 pid1, pid2;
-				} fsl;
-				__u8 pad[256];
-			} impl;
-
-			__u32 features; /* KVM_SREGS_E_ */
-			__u32 impl_id;	/* KVM_SREGS_E_IMPL_ */
-			__u32 update_special; /* KVM_SREGS_E_UPDATE_ */
-			__u32 pir;	/* read-only */
-			__u64 sprg8;
-			__u64 sprg9;	/* E.ED */
-			__u64 csrr0;
-			__u64 dsrr0;	/* E.ED */
-			__u64 mcsrr0;
-			__u32 csrr1;
-			__u32 dsrr1;	/* E.ED */
-			__u32 mcsrr1;
-			__u32 esr;
-			__u64 dear;
-			__u64 ivpr;
-			__u64 mcivpr;
-			__u64 mcsr;	/* KVM_SREGS_E_UPDATE_MCSR */
-
-			__u32 tsr;	/* KVM_SREGS_E_UPDATE_TSR */
-			__u32 tcr;
-			__u32 decar;
-			__u32 dec;	/* KVM_SREGS_E_UPDATE_DEC */
-
-			/*
-			 * Userspace can read TB directly, but the
-			 * value reported here is consistent with "dec".
-			 *
-			 * Read-only.
-			 */
-			__u64 tb;
-
-			__u32 dbsr;	/* KVM_SREGS_E_UPDATE_DBSR */
-			__u32 dbcr[3];
-			__u32 iac[4];
-			__u32 dac[2];
-			__u32 dvc[2];
-			__u8 num_iac;	/* read-only */
-			__u8 num_dac;	/* read-only */
-			__u8 num_dvc;	/* read-only */
-			__u8 pad;
-
-			__u32 epr;	/* EXP */
-			__u32 vrsave;	/* a.k.a. USPRG0 */
-			__u32 epcr;	/* KVM_SREGS_E_64 */
-
-			__u32 mas0;
-			__u32 mas1;
-			__u64 mas2;
-			__u64 mas7_3;
-			__u32 mas4;
-			__u32 mas6;
-
-			__u32 ivor_low[16]; /* IVOR0-15 */
-			__u32 ivor_high[18]; /* IVOR32+, plus room to expand */
-
-			__u32 mmucfg;	/* read-only */
-			__u32 eptcfg;	/* E.PT, read-only */
-			__u32 tlbcfg[4];/* read-only */
-			__u32 tlbps[4]; /* read-only */
-
-			__u32 eplc, epsc; /* E.PD */
-		} e;
-		__u8 pad[1020];
-	} u;
-};
-
-struct kvm_fpu {
-	__u64 fpr[32];
-};
-
-struct kvm_debug_exit_arch {
-};
-
-/* for KVM_SET_GUEST_DEBUG */
-struct kvm_guest_debug_arch {
-};
-
-/* definition of registers in kvm_run */
-struct kvm_sync_regs {
-};
-
-#define KVM_INTERRUPT_SET	-1U
-#define KVM_INTERRUPT_UNSET	-2U
-#define KVM_INTERRUPT_SET_LEVEL	-3U
-
-#define KVM_CPU_440		1
-#define KVM_CPU_E500V2		2
-#define KVM_CPU_3S_32		3
-#define KVM_CPU_3S_64		4
-
-/* for KVM_CAP_SPAPR_TCE */
-struct kvm_create_spapr_tce {
-	__u64 liobn;
-	__u32 window_size;
-};
-
-/* for KVM_ALLOCATE_RMA */
-struct kvm_allocate_rma {
-	__u64 rma_size;
-};
-
-struct kvm_book3e_206_tlb_entry {
-	__u32 mas8;
-	__u32 mas1;
-	__u64 mas2;
-	__u64 mas7_3;
-};
-
-struct kvm_book3e_206_tlb_params {
-	/*
-	 * For mmu types KVM_MMU_FSL_BOOKE_NOHV and KVM_MMU_FSL_BOOKE_HV:
-	 *
-	 * - The number of ways of TLB0 must be a power of two between 2 and
-	 *   16.
-	 * - TLB1 must be fully associative.
-	 * - The size of TLB0 must be a multiple of the number of ways, and
-	 *   the number of sets must be a power of two.
-	 * - The size of TLB1 may not exceed 64 entries.
-	 * - TLB0 supports 4 KiB pages.
-	 * - The page sizes supported by TLB1 are as indicated by
-	 *   TLB1CFG (if MMUCFG[MAVN] = 0) or TLB1PS (if MMUCFG[MAVN] = 1)
-	 *   as returned by KVM_GET_SREGS.
-	 * - TLB2 and TLB3 are reserved, and their entries in tlb_sizes[]
-	 *   and tlb_ways[] must be zero.
-	 *
-	 * tlb_ways[n] = tlb_sizes[n] means the array is fully associative.
-	 *
-	 * KVM will adjust TLBnCFG based on the sizes configured here,
-	 * though arrays greater than 2048 entries will have TLBnCFG[NENTRY]
-	 * set to zero.
-	 */
-	__u32 tlb_sizes[4];
-	__u32 tlb_ways[4];
-	__u32 reserved[8];
-};
-
-#define KVM_REG_PPC_HIOR	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x1)
-
-#endif /* __LINUX_KVM_POWERPC_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/kvm_44x.h b/ANDROID_3.4.5/arch/powerpc/include/asm/kvm_44x.h
deleted file mode 100644
index a0e57618..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/kvm_44x.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, version 2, as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
- *
- * Copyright IBM Corp. 2008
- *
- * Authors: Hollis Blanchard <hollisb@us.ibm.com>
- */
-
-#ifndef __ASM_44X_H__
-#define __ASM_44X_H__
-
-#include <linux/kvm_host.h>
-
-#define PPC44x_TLB_SIZE 64
-
-/* If the guest is expecting it, this can be as large as we like; we'd just
- * need to find some way of advertising it. */
-#define KVM44x_GUEST_TLB_SIZE 64
-
-struct kvmppc_44x_tlbe {
-	u32 tid; /* Only the low 8 bits are used. */
-	u32 word0;
-	u32 word1;
-	u32 word2;
-};
-
-struct kvmppc_44x_shadow_ref {
-	struct page *page;
-	u16 gtlb_index;
-	u8 writeable;
-	u8 tid;
-};
-
-struct kvmppc_vcpu_44x {
-	/* Unmodified copy of the guest's TLB. */
-	struct kvmppc_44x_tlbe guest_tlb[KVM44x_GUEST_TLB_SIZE];
-
-	/* References to guest pages in the hardware TLB. */
-	struct kvmppc_44x_shadow_ref shadow_refs[PPC44x_TLB_SIZE];
-
-	/* State of the shadow TLB at guest context switch time. */
-	struct kvmppc_44x_tlbe shadow_tlb[PPC44x_TLB_SIZE];
-	u8 shadow_tlb_mod[PPC44x_TLB_SIZE];
-
-	struct kvm_vcpu vcpu;
-};
-
-static inline struct kvmppc_vcpu_44x *to_44x(struct kvm_vcpu *vcpu)
-{
-	return container_of(vcpu, struct kvmppc_vcpu_44x, vcpu);
-}
-
-void kvmppc_44x_tlb_put(struct kvm_vcpu *vcpu);
-void kvmppc_44x_tlb_load(struct kvm_vcpu *vcpu);
-
-#endif /* __ASM_44X_H__ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/kvm_asm.h b/ANDROID_3.4.5/arch/powerpc/include/asm/kvm_asm.h
deleted file mode 100644
index 7b1f0e0f..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/kvm_asm.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, version 2, as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
- *
- * Copyright IBM Corp. 2008
- *
- * Authors: Hollis Blanchard <hollisb@us.ibm.com>
- */
-
-#ifndef __POWERPC_KVM_ASM_H__
-#define __POWERPC_KVM_ASM_H__
-
-/* IVPR must be 64KiB-aligned. */
-#define VCPU_SIZE_ORDER 4
-#define VCPU_SIZE_LOG   (VCPU_SIZE_ORDER + 12)
-#define VCPU_TLB_PGSZ   PPC44x_TLB_64K
-#define VCPU_SIZE_BYTES (1<<VCPU_SIZE_LOG)
-
-#define BOOKE_INTERRUPT_CRITICAL 0
-#define BOOKE_INTERRUPT_MACHINE_CHECK 1
-#define BOOKE_INTERRUPT_DATA_STORAGE 2
-#define BOOKE_INTERRUPT_INST_STORAGE 3
-#define BOOKE_INTERRUPT_EXTERNAL 4
-#define BOOKE_INTERRUPT_ALIGNMENT 5
-#define BOOKE_INTERRUPT_PROGRAM 6
-#define BOOKE_INTERRUPT_FP_UNAVAIL 7
-#define BOOKE_INTERRUPT_SYSCALL 8
-#define BOOKE_INTERRUPT_AP_UNAVAIL 9
-#define BOOKE_INTERRUPT_DECREMENTER 10
-#define BOOKE_INTERRUPT_FIT 11
-#define BOOKE_INTERRUPT_WATCHDOG 12
-#define BOOKE_INTERRUPT_DTLB_MISS 13
-#define BOOKE_INTERRUPT_ITLB_MISS 14
-#define BOOKE_INTERRUPT_DEBUG 15
-
-/* E500 */
-#define BOOKE_INTERRUPT_SPE_UNAVAIL 32
-#define BOOKE_INTERRUPT_SPE_FP_DATA 33
-#define BOOKE_INTERRUPT_SPE_FP_ROUND 34
-#define BOOKE_INTERRUPT_PERFORMANCE_MONITOR 35
-
-/* book3s */
-
-#define BOOK3S_INTERRUPT_SYSTEM_RESET	0x100
-#define BOOK3S_INTERRUPT_MACHINE_CHECK	0x200
-#define BOOK3S_INTERRUPT_DATA_STORAGE	0x300
-#define BOOK3S_INTERRUPT_DATA_SEGMENT	0x380
-#define BOOK3S_INTERRUPT_INST_STORAGE	0x400
-#define BOOK3S_INTERRUPT_INST_SEGMENT	0x480
-#define BOOK3S_INTERRUPT_EXTERNAL	0x500
-#define BOOK3S_INTERRUPT_EXTERNAL_LEVEL	0x501
-#define BOOK3S_INTERRUPT_EXTERNAL_HV	0x502
-#define BOOK3S_INTERRUPT_ALIGNMENT	0x600
-#define BOOK3S_INTERRUPT_PROGRAM	0x700
-#define BOOK3S_INTERRUPT_FP_UNAVAIL	0x800
-#define BOOK3S_INTERRUPT_DECREMENTER	0x900
-#define BOOK3S_INTERRUPT_HV_DECREMENTER	0x980
-#define BOOK3S_INTERRUPT_SYSCALL	0xc00
-#define BOOK3S_INTERRUPT_TRACE		0xd00
-#define BOOK3S_INTERRUPT_H_DATA_STORAGE	0xe00
-#define BOOK3S_INTERRUPT_H_INST_STORAGE	0xe20
-#define BOOK3S_INTERRUPT_H_EMUL_ASSIST	0xe40
-#define BOOK3S_INTERRUPT_PERFMON	0xf00
-#define BOOK3S_INTERRUPT_ALTIVEC	0xf20
-#define BOOK3S_INTERRUPT_VSX		0xf40
-
-#define BOOK3S_IRQPRIO_SYSTEM_RESET		0
-#define BOOK3S_IRQPRIO_DATA_SEGMENT		1
-#define BOOK3S_IRQPRIO_INST_SEGMENT		2
-#define BOOK3S_IRQPRIO_DATA_STORAGE		3
-#define BOOK3S_IRQPRIO_INST_STORAGE		4
-#define BOOK3S_IRQPRIO_ALIGNMENT		5
-#define BOOK3S_IRQPRIO_PROGRAM			6
-#define BOOK3S_IRQPRIO_FP_UNAVAIL		7
-#define BOOK3S_IRQPRIO_ALTIVEC			8
-#define BOOK3S_IRQPRIO_VSX			9
-#define BOOK3S_IRQPRIO_SYSCALL			10
-#define BOOK3S_IRQPRIO_MACHINE_CHECK		11
-#define BOOK3S_IRQPRIO_DEBUG			12
-#define BOOK3S_IRQPRIO_EXTERNAL			13
-#define BOOK3S_IRQPRIO_DECREMENTER		14
-#define BOOK3S_IRQPRIO_PERFORMANCE_MONITOR	15
-#define BOOK3S_IRQPRIO_EXTERNAL_LEVEL		16
-#define BOOK3S_IRQPRIO_MAX			17
-
-#define BOOK3S_HFLAG_DCBZ32			0x1
-#define BOOK3S_HFLAG_SLB			0x2
-#define BOOK3S_HFLAG_PAIRED_SINGLE		0x4
-#define BOOK3S_HFLAG_NATIVE_PS			0x8
-
-#define RESUME_FLAG_NV          (1<<0)  /* Reload guest nonvolatile state? */
-#define RESUME_FLAG_HOST        (1<<1)  /* Resume host? */
-
-#define RESUME_GUEST            0
-#define RESUME_GUEST_NV         RESUME_FLAG_NV
-#define RESUME_HOST             RESUME_FLAG_HOST
-#define RESUME_HOST_NV          (RESUME_FLAG_HOST|RESUME_FLAG_NV)
-
-#define KVM_GUEST_MODE_NONE	0
-#define KVM_GUEST_MODE_GUEST	1
-#define KVM_GUEST_MODE_SKIP	2
-
-#define KVM_INST_FETCH_FAILED	-1
-
-#endif /* __POWERPC_KVM_ASM_H__ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/kvm_book3s.h b/ANDROID_3.4.5/arch/powerpc/include/asm/kvm_book3s.h
deleted file mode 100644
index fd07f43d..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/kvm_book3s.h
+++ /dev/null
@@ -1,456 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, version 2, as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
- *
- * Copyright SUSE Linux Products GmbH 2009
- *
- * Authors: Alexander Graf <agraf@suse.de>
- */
-
-#ifndef __ASM_KVM_BOOK3S_H__
-#define __ASM_KVM_BOOK3S_H__
-
-#include <linux/types.h>
-#include <linux/kvm_host.h>
-#include <asm/kvm_book3s_asm.h>
-
-struct kvmppc_bat {
-	u64 raw;
-	u32 bepi;
-	u32 bepi_mask;
-	u32 brpn;
-	u8 wimg;
-	u8 pp;
-	bool vs		: 1;
-	bool vp		: 1;
-};
-
-struct kvmppc_sid_map {
-	u64 guest_vsid;
-	u64 guest_esid;
-	u64 host_vsid;
-	bool valid	: 1;
-};
-
-#define SID_MAP_BITS    9
-#define SID_MAP_NUM     (1 << SID_MAP_BITS)
-#define SID_MAP_MASK    (SID_MAP_NUM - 1)
-
-#ifdef CONFIG_PPC_BOOK3S_64
-#define SID_CONTEXTS	1
-#else
-#define SID_CONTEXTS	128
-#define VSID_POOL_SIZE	(SID_CONTEXTS * 16)
-#endif
-
-struct hpte_cache {
-	struct hlist_node list_pte;
-	struct hlist_node list_pte_long;
-	struct hlist_node list_vpte;
-	struct hlist_node list_vpte_long;
-	struct rcu_head rcu_head;
-	u64 host_va;
-	u64 pfn;
-	ulong slot;
-	struct kvmppc_pte pte;
-};
-
-struct kvmppc_vcpu_book3s {
-	struct kvm_vcpu vcpu;
-	struct kvmppc_book3s_shadow_vcpu *shadow_vcpu;
-	struct kvmppc_sid_map sid_map[SID_MAP_NUM];
-	struct {
-		u64 esid;
-		u64 vsid;
-	} slb_shadow[64];
-	u8 slb_shadow_max;
-	struct kvmppc_bat ibat[8];
-	struct kvmppc_bat dbat[8];
-	u64 hid[6];
-	u64 gqr[8];
-	u64 sdr1;
-	u64 hior;
-	u64 msr_mask;
-#ifdef CONFIG_PPC_BOOK3S_32
-	u32 vsid_pool[VSID_POOL_SIZE];
-	u32 vsid_next;
-#else
-	u64 proto_vsid_first;
-	u64 proto_vsid_max;
-	u64 proto_vsid_next;
-#endif
-	int context_id[SID_CONTEXTS];
-
-	bool hior_explicit;		/* HIOR is set by ioctl, not PVR */
-
-	struct hlist_head hpte_hash_pte[HPTEG_HASH_NUM_PTE];
-	struct hlist_head hpte_hash_pte_long[HPTEG_HASH_NUM_PTE_LONG];
-	struct hlist_head hpte_hash_vpte[HPTEG_HASH_NUM_VPTE];
-	struct hlist_head hpte_hash_vpte_long[HPTEG_HASH_NUM_VPTE_LONG];
-	int hpte_cache_count;
-	spinlock_t mmu_lock;
-};
-
-#define CONTEXT_HOST		0
-#define CONTEXT_GUEST		1
-#define CONTEXT_GUEST_END	2
-
-#define VSID_REAL	0x1fffffffffc00000ULL
-#define VSID_BAT	0x1fffffffffb00000ULL
-#define VSID_REAL_DR	0x2000000000000000ULL
-#define VSID_REAL_IR	0x4000000000000000ULL
-#define VSID_PR		0x8000000000000000ULL
-
-extern void kvmppc_mmu_pte_flush(struct kvm_vcpu *vcpu, ulong ea, ulong ea_mask);
-extern void kvmppc_mmu_pte_vflush(struct kvm_vcpu *vcpu, u64 vp, u64 vp_mask);
-extern void kvmppc_mmu_pte_pflush(struct kvm_vcpu *vcpu, ulong pa_start, ulong pa_end);
-extern void kvmppc_set_msr(struct kvm_vcpu *vcpu, u64 new_msr);
-extern void kvmppc_set_pvr(struct kvm_vcpu *vcpu, u32 pvr);
-extern void kvmppc_mmu_book3s_64_init(struct kvm_vcpu *vcpu);
-extern void kvmppc_mmu_book3s_32_init(struct kvm_vcpu *vcpu);
-extern void kvmppc_mmu_book3s_hv_init(struct kvm_vcpu *vcpu);
-extern int kvmppc_mmu_map_page(struct kvm_vcpu *vcpu, struct kvmppc_pte *pte);
-extern int kvmppc_mmu_map_segment(struct kvm_vcpu *vcpu, ulong eaddr);
-extern void kvmppc_mmu_flush_segments(struct kvm_vcpu *vcpu);
-extern int kvmppc_book3s_hv_page_fault(struct kvm_run *run,
-			struct kvm_vcpu *vcpu, unsigned long addr,
-			unsigned long status);
-extern long kvmppc_hv_find_lock_hpte(struct kvm *kvm, gva_t eaddr,
-			unsigned long slb_v, unsigned long valid);
-
-extern void kvmppc_mmu_hpte_cache_map(struct kvm_vcpu *vcpu, struct hpte_cache *pte);
-extern struct hpte_cache *kvmppc_mmu_hpte_cache_next(struct kvm_vcpu *vcpu);
-extern void kvmppc_mmu_hpte_destroy(struct kvm_vcpu *vcpu);
-extern int kvmppc_mmu_hpte_init(struct kvm_vcpu *vcpu);
-extern void kvmppc_mmu_invalidate_pte(struct kvm_vcpu *vcpu, struct hpte_cache *pte);
-extern int kvmppc_mmu_hpte_sysinit(void);
-extern void kvmppc_mmu_hpte_sysexit(void);
-extern int kvmppc_mmu_hv_init(void);
-
-extern int kvmppc_ld(struct kvm_vcpu *vcpu, ulong *eaddr, int size, void *ptr, bool data);
-extern int kvmppc_st(struct kvm_vcpu *vcpu, ulong *eaddr, int size, void *ptr, bool data);
-extern void kvmppc_book3s_queue_irqprio(struct kvm_vcpu *vcpu, unsigned int vec);
-extern void kvmppc_inject_interrupt(struct kvm_vcpu *vcpu, int vec, u64 flags);
-extern void kvmppc_set_bat(struct kvm_vcpu *vcpu, struct kvmppc_bat *bat,
-			   bool upper, u32 val);
-extern void kvmppc_giveup_ext(struct kvm_vcpu *vcpu, ulong msr);
-extern int kvmppc_emulate_paired_single(struct kvm_run *run, struct kvm_vcpu *vcpu);
-extern pfn_t kvmppc_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn);
-extern void kvmppc_add_revmap_chain(struct kvm *kvm, struct revmap_entry *rev,
-			unsigned long *rmap, long pte_index, int realmode);
-extern void kvmppc_invalidate_hpte(struct kvm *kvm, unsigned long *hptep,
-			unsigned long pte_index);
-void kvmppc_clear_ref_hpte(struct kvm *kvm, unsigned long *hptep,
-			unsigned long pte_index);
-extern void *kvmppc_pin_guest_page(struct kvm *kvm, unsigned long addr,
-			unsigned long *nb_ret);
-extern void kvmppc_unpin_guest_page(struct kvm *kvm, void *addr);
-extern long kvmppc_virtmode_h_enter(struct kvm_vcpu *vcpu, unsigned long flags,
-			long pte_index, unsigned long pteh, unsigned long ptel);
-extern long kvmppc_h_enter(struct kvm_vcpu *vcpu, unsigned long flags,
-			long pte_index, unsigned long pteh, unsigned long ptel);
-extern long kvmppc_hv_get_dirty_log(struct kvm *kvm,
-			struct kvm_memory_slot *memslot);
-
-extern void kvmppc_entry_trampoline(void);
-extern void kvmppc_hv_entry_trampoline(void);
-extern void kvmppc_load_up_fpu(void);
-extern void kvmppc_load_up_altivec(void);
-extern void kvmppc_load_up_vsx(void);
-extern u32 kvmppc_alignment_dsisr(struct kvm_vcpu *vcpu, unsigned int inst);
-extern ulong kvmppc_alignment_dar(struct kvm_vcpu *vcpu, unsigned int inst);
-extern int kvmppc_h_pr(struct kvm_vcpu *vcpu, unsigned long cmd);
-
-static inline struct kvmppc_vcpu_book3s *to_book3s(struct kvm_vcpu *vcpu)
-{
-	return container_of(vcpu, struct kvmppc_vcpu_book3s, vcpu);
-}
-
-extern void kvm_return_point(void);
-
-/* Also add subarch specific defines */
-
-#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
-#include <asm/kvm_book3s_32.h>
-#endif
-#ifdef CONFIG_KVM_BOOK3S_64_HANDLER
-#include <asm/kvm_book3s_64.h>
-#endif
-
-#ifdef CONFIG_KVM_BOOK3S_PR
-
-static inline unsigned long kvmppc_interrupt_offset(struct kvm_vcpu *vcpu)
-{
-	return to_book3s(vcpu)->hior;
-}
-
-static inline void kvmppc_update_int_pending(struct kvm_vcpu *vcpu,
-			unsigned long pending_now, unsigned long old_pending)
-{
-	if (pending_now)
-		vcpu->arch.shared->int_pending = 1;
-	else if (old_pending)
-		vcpu->arch.shared->int_pending = 0;
-}
-
-static inline void kvmppc_set_gpr(struct kvm_vcpu *vcpu, int num, ulong val)
-{
-	if ( num < 14 ) {
-		struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
-		svcpu->gpr[num] = val;
-		svcpu_put(svcpu);
-		to_book3s(vcpu)->shadow_vcpu->gpr[num] = val;
-	} else
-		vcpu->arch.gpr[num] = val;
-}
-
-static inline ulong kvmppc_get_gpr(struct kvm_vcpu *vcpu, int num)
-{
-	if ( num < 14 ) {
-		struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
-		ulong r = svcpu->gpr[num];
-		svcpu_put(svcpu);
-		return r;
-	} else
-		return vcpu->arch.gpr[num];
-}
-
-static inline void kvmppc_set_cr(struct kvm_vcpu *vcpu, u32 val)
-{
-	struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
-	svcpu->cr = val;
-	svcpu_put(svcpu);
-	to_book3s(vcpu)->shadow_vcpu->cr = val;
-}
-
-static inline u32 kvmppc_get_cr(struct kvm_vcpu *vcpu)
-{
-	struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
-	u32 r;
-	r = svcpu->cr;
-	svcpu_put(svcpu);
-	return r;
-}
-
-static inline void kvmppc_set_xer(struct kvm_vcpu *vcpu, u32 val)
-{
-	struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
-	svcpu->xer = val;
-	to_book3s(vcpu)->shadow_vcpu->xer = val;
-	svcpu_put(svcpu);
-}
-
-static inline u32 kvmppc_get_xer(struct kvm_vcpu *vcpu)
-{
-	struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
-	u32 r;
-	r = svcpu->xer;
-	svcpu_put(svcpu);
-	return r;
-}
-
-static inline void kvmppc_set_ctr(struct kvm_vcpu *vcpu, ulong val)
-{
-	struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
-	svcpu->ctr = val;
-	svcpu_put(svcpu);
-}
-
-static inline ulong kvmppc_get_ctr(struct kvm_vcpu *vcpu)
-{
-	struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
-	ulong r;
-	r = svcpu->ctr;
-	svcpu_put(svcpu);
-	return r;
-}
-
-static inline void kvmppc_set_lr(struct kvm_vcpu *vcpu, ulong val)
-{
-	struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
-	svcpu->lr = val;
-	svcpu_put(svcpu);
-}
-
-static inline ulong kvmppc_get_lr(struct kvm_vcpu *vcpu)
-{
-	struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
-	ulong r;
-	r = svcpu->lr;
-	svcpu_put(svcpu);
-	return r;
-}
-
-static inline void kvmppc_set_pc(struct kvm_vcpu *vcpu, ulong val)
-{
-	struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
-	svcpu->pc = val;
-	svcpu_put(svcpu);
-}
-
-static inline ulong kvmppc_get_pc(struct kvm_vcpu *vcpu)
-{
-	struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
-	ulong r;
-	r = svcpu->pc;
-	svcpu_put(svcpu);
-	return r;
-}
-
-static inline u32 kvmppc_get_last_inst(struct kvm_vcpu *vcpu)
-{
-	ulong pc = kvmppc_get_pc(vcpu);
-	struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
-	u32 r;
-
-	/* Load the instruction manually if it failed to do so in the
-	 * exit path */
-	if (svcpu->last_inst == KVM_INST_FETCH_FAILED)
-		kvmppc_ld(vcpu, &pc, sizeof(u32), &svcpu->last_inst, false);
-
-	r = svcpu->last_inst;
-	svcpu_put(svcpu);
-	return r;
-}
-
-static inline ulong kvmppc_get_fault_dar(struct kvm_vcpu *vcpu)
-{
-	struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
-	ulong r;
-	r = svcpu->fault_dar;
-	svcpu_put(svcpu);
-	return r;
-}
-
-static inline bool kvmppc_critical_section(struct kvm_vcpu *vcpu)
-{
-	ulong crit_raw = vcpu->arch.shared->critical;
-	ulong crit_r1 = kvmppc_get_gpr(vcpu, 1);
-	bool crit;
-
-	/* Truncate crit indicators in 32 bit mode */
-	if (!(vcpu->arch.shared->msr & MSR_SF)) {
-		crit_raw &= 0xffffffff;
-		crit_r1 &= 0xffffffff;
-	}
-
-	/* Critical section when crit == r1 */
-	crit = (crit_raw == crit_r1);
-	/* ... and we're in supervisor mode */
-	crit = crit && !(vcpu->arch.shared->msr & MSR_PR);
-
-	return crit;
-}
-#else /* CONFIG_KVM_BOOK3S_PR */
-
-static inline unsigned long kvmppc_interrupt_offset(struct kvm_vcpu *vcpu)
-{
-	return 0;
-}
-
-static inline void kvmppc_update_int_pending(struct kvm_vcpu *vcpu,
-			unsigned long pending_now, unsigned long old_pending)
-{
-}
-
-static inline void kvmppc_set_gpr(struct kvm_vcpu *vcpu, int num, ulong val)
-{
-	vcpu->arch.gpr[num] = val;
-}
-
-static inline ulong kvmppc_get_gpr(struct kvm_vcpu *vcpu, int num)
-{
-	return vcpu->arch.gpr[num];
-}
-
-static inline void kvmppc_set_cr(struct kvm_vcpu *vcpu, u32 val)
-{
-	vcpu->arch.cr = val;
-}
-
-static inline u32 kvmppc_get_cr(struct kvm_vcpu *vcpu)
-{
-	return vcpu->arch.cr;
-}
-
-static inline void kvmppc_set_xer(struct kvm_vcpu *vcpu, u32 val)
-{
-	vcpu->arch.xer = val;
-}
-
-static inline u32 kvmppc_get_xer(struct kvm_vcpu *vcpu)
-{
-	return vcpu->arch.xer;
-}
-
-static inline void kvmppc_set_ctr(struct kvm_vcpu *vcpu, ulong val)
-{
-	vcpu->arch.ctr = val;
-}
-
-static inline ulong kvmppc_get_ctr(struct kvm_vcpu *vcpu)
-{
-	return vcpu->arch.ctr;
-}
-
-static inline void kvmppc_set_lr(struct kvm_vcpu *vcpu, ulong val)
-{
-	vcpu->arch.lr = val;
-}
-
-static inline ulong kvmppc_get_lr(struct kvm_vcpu *vcpu)
-{
-	return vcpu->arch.lr;
-}
-
-static inline void kvmppc_set_pc(struct kvm_vcpu *vcpu, ulong val)
-{
-	vcpu->arch.pc = val;
-}
-
-static inline ulong kvmppc_get_pc(struct kvm_vcpu *vcpu)
-{
-	return vcpu->arch.pc;
-}
-
-static inline u32 kvmppc_get_last_inst(struct kvm_vcpu *vcpu)
-{
-	ulong pc = kvmppc_get_pc(vcpu);
-
-	/* Load the instruction manually if it failed to do so in the
-	 * exit path */
-	if (vcpu->arch.last_inst == KVM_INST_FETCH_FAILED)
-		kvmppc_ld(vcpu, &pc, sizeof(u32), &vcpu->arch.last_inst, false);
-
-	return vcpu->arch.last_inst;
-}
-
-static inline ulong kvmppc_get_fault_dar(struct kvm_vcpu *vcpu)
-{
-	return vcpu->arch.fault_dar;
-}
-
-static inline bool kvmppc_critical_section(struct kvm_vcpu *vcpu)
-{
-	return false;
-}
-#endif
-
-/* Magic register values loaded into r3 and r4 before the 'sc' assembly
- * instruction for the OSI hypercalls */
-#define OSI_SC_MAGIC_R3			0x113724FA
-#define OSI_SC_MAGIC_R4			0x77810F9B
-
-#define INS_DCBZ			0x7c0007ec
-
-#endif /* __ASM_KVM_BOOK3S_H__ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/kvm_book3s_32.h b/ANDROID_3.4.5/arch/powerpc/include/asm/kvm_book3s_32.h
deleted file mode 100644
index 38040ff8..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/kvm_book3s_32.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, version 2, as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
- *
- * Copyright SUSE Linux Products GmbH 2010
- *
- * Authors: Alexander Graf <agraf@suse.de>
- */
-
-#ifndef __ASM_KVM_BOOK3S_32_H__
-#define __ASM_KVM_BOOK3S_32_H__
-
-static inline struct kvmppc_book3s_shadow_vcpu *svcpu_get(struct kvm_vcpu *vcpu)
-{
-	return to_book3s(vcpu)->shadow_vcpu;
-}
-
-static inline void svcpu_put(struct kvmppc_book3s_shadow_vcpu *svcpu)
-{
-}
-
-#define PTE_SIZE	12
-#define VSID_ALL	0
-#define SR_INVALID	0x00000001	/* VSID 1 should always be unused */
-#define SR_KP		0x20000000
-#define PTE_V		0x80000000
-#define PTE_SEC		0x00000040
-#define PTE_M		0x00000010
-#define PTE_R		0x00000100
-#define PTE_C		0x00000080
-
-#define SID_SHIFT	28
-#define ESID_MASK	0xf0000000
-#define VSID_MASK	0x00fffffff0000000ULL
-
-#endif /* __ASM_KVM_BOOK3S_32_H__ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/kvm_book3s_64.h b/ANDROID_3.4.5/arch/powerpc/include/asm/kvm_book3s_64.h
deleted file mode 100644
index b0c08b14..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/kvm_book3s_64.h
+++ /dev/null
@@ -1,243 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, version 2, as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
- *
- * Copyright SUSE Linux Products GmbH 2010
- *
- * Authors: Alexander Graf <agraf@suse.de>
- */
-
-#ifndef __ASM_KVM_BOOK3S_64_H__
-#define __ASM_KVM_BOOK3S_64_H__
-
-#ifdef CONFIG_KVM_BOOK3S_PR
-static inline struct kvmppc_book3s_shadow_vcpu *svcpu_get(struct kvm_vcpu *vcpu)
-{
-	preempt_disable();
-	return &get_paca()->shadow_vcpu;
-}
-
-static inline void svcpu_put(struct kvmppc_book3s_shadow_vcpu *svcpu)
-{
-	preempt_enable();
-}
-#endif
-
-#define SPAPR_TCE_SHIFT		12
-
-#ifdef CONFIG_KVM_BOOK3S_64_HV
-/* For now use fixed-size 16MB page table */
-#define HPT_ORDER	24
-#define HPT_NPTEG	(1ul << (HPT_ORDER - 7))	/* 128B per pteg */
-#define HPT_NPTE	(HPT_NPTEG << 3)		/* 8 PTEs per PTEG */
-#define HPT_HASH_MASK	(HPT_NPTEG - 1)
-#endif
-
-#define VRMA_VSID	0x1ffffffUL	/* 1TB VSID reserved for VRMA */
-
-/*
- * We use a lock bit in HPTE dword 0 to synchronize updates and
- * accesses to each HPTE, and another bit to indicate non-present
- * HPTEs.
- */
-#define HPTE_V_HVLOCK	0x40UL
-#define HPTE_V_ABSENT	0x20UL
-
-static inline long try_lock_hpte(unsigned long *hpte, unsigned long bits)
-{
-	unsigned long tmp, old;
-
-	asm volatile("	ldarx	%0,0,%2\n"
-		     "	and.	%1,%0,%3\n"
-		     "	bne	2f\n"
-		     "	ori	%0,%0,%4\n"
-		     "  stdcx.	%0,0,%2\n"
-		     "	beq+	2f\n"
-		     "	li	%1,%3\n"
-		     "2:	isync"
-		     : "=&r" (tmp), "=&r" (old)
-		     : "r" (hpte), "r" (bits), "i" (HPTE_V_HVLOCK)
-		     : "cc", "memory");
-	return old == 0;
-}
-
-static inline unsigned long compute_tlbie_rb(unsigned long v, unsigned long r,
-					     unsigned long pte_index)
-{
-	unsigned long rb, va_low;
-
-	rb = (v & ~0x7fUL) << 16;		/* AVA field */
-	va_low = pte_index >> 3;
-	if (v & HPTE_V_SECONDARY)
-		va_low = ~va_low;
-	/* xor vsid from AVA */
-	if (!(v & HPTE_V_1TB_SEG))
-		va_low ^= v >> 12;
-	else
-		va_low ^= v >> 24;
-	va_low &= 0x7ff;
-	if (v & HPTE_V_LARGE) {
-		rb |= 1;			/* L field */
-		if (cpu_has_feature(CPU_FTR_ARCH_206) &&
-		    (r & 0xff000)) {
-			/* non-16MB large page, must be 64k */
-			/* (masks depend on page size) */
-			rb |= 0x1000;		/* page encoding in LP field */
-			rb |= (va_low & 0x7f) << 16; /* 7b of VA in AVA/LP field */
-			rb |= (va_low & 0xfe);	/* AVAL field (P7 doesn't seem to care) */
-		}
-	} else {
-		/* 4kB page */
-		rb |= (va_low & 0x7ff) << 12;	/* remaining 11b of VA */
-	}
-	rb |= (v >> 54) & 0x300;		/* B field */
-	return rb;
-}
-
-static inline unsigned long hpte_page_size(unsigned long h, unsigned long l)
-{
-	/* only handle 4k, 64k and 16M pages for now */
-	if (!(h & HPTE_V_LARGE))
-		return 1ul << 12;		/* 4k page */
-	if ((l & 0xf000) == 0x1000 && cpu_has_feature(CPU_FTR_ARCH_206))
-		return 1ul << 16;		/* 64k page */
-	if ((l & 0xff000) == 0)
-		return 1ul << 24;		/* 16M page */
-	return 0;				/* error */
-}
-
-static inline unsigned long hpte_rpn(unsigned long ptel, unsigned long psize)
-{
-	return ((ptel & HPTE_R_RPN) & ~(psize - 1)) >> PAGE_SHIFT;
-}
-
-static inline int hpte_is_writable(unsigned long ptel)
-{
-	unsigned long pp = ptel & (HPTE_R_PP0 | HPTE_R_PP);
-
-	return pp != PP_RXRX && pp != PP_RXXX;
-}
-
-static inline unsigned long hpte_make_readonly(unsigned long ptel)
-{
-	if ((ptel & HPTE_R_PP0) || (ptel & HPTE_R_PP) == PP_RWXX)
-		ptel = (ptel & ~HPTE_R_PP) | PP_RXXX;
-	else
-		ptel |= PP_RXRX;
-	return ptel;
-}
-
-static inline int hpte_cache_flags_ok(unsigned long ptel, unsigned long io_type)
-{
-	unsigned int wimg = ptel & HPTE_R_WIMG;
-
-	/* Handle SAO */
-	if (wimg == (HPTE_R_W | HPTE_R_I | HPTE_R_M) &&
-	    cpu_has_feature(CPU_FTR_ARCH_206))
-		wimg = HPTE_R_M;
-
-	if (!io_type)
-		return wimg == HPTE_R_M;
-
-	return (wimg & (HPTE_R_W | HPTE_R_I)) == io_type;
-}
-
-/*
- * Lock and read a linux PTE.  If it's present and writable, atomically
- * set dirty and referenced bits and return the PTE, otherwise return 0.
- */
-static inline pte_t kvmppc_read_update_linux_pte(pte_t *p, int writing)
-{
-	pte_t pte, tmp;
-
-	/* wait until _PAGE_BUSY is clear then set it atomically */
-	__asm__ __volatile__ (
-		"1:	ldarx	%0,0,%3\n"
-		"	andi.	%1,%0,%4\n"
-		"	bne-	1b\n"
-		"	ori	%1,%0,%4\n"
-		"	stdcx.	%1,0,%3\n"
-		"	bne-	1b"
-		: "=&r" (pte), "=&r" (tmp), "=m" (*p)
-		: "r" (p), "i" (_PAGE_BUSY)
-		: "cc");
-
-	if (pte_present(pte)) {
-		pte = pte_mkyoung(pte);
-		if (writing && pte_write(pte))
-			pte = pte_mkdirty(pte);
-	}
-
-	*p = pte;	/* clears _PAGE_BUSY */
-
-	return pte;
-}
-
-/* Return HPTE cache control bits corresponding to Linux pte bits */
-static inline unsigned long hpte_cache_bits(unsigned long pte_val)
-{
-#if _PAGE_NO_CACHE == HPTE_R_I && _PAGE_WRITETHRU == HPTE_R_W
-	return pte_val & (HPTE_R_W | HPTE_R_I);
-#else
-	return ((pte_val & _PAGE_NO_CACHE) ? HPTE_R_I : 0) +
-		((pte_val & _PAGE_WRITETHRU) ? HPTE_R_W : 0);
-#endif
-}
-
-static inline bool hpte_read_permission(unsigned long pp, unsigned long key)
-{
-	if (key)
-		return PP_RWRX <= pp && pp <= PP_RXRX;
-	return 1;
-}
-
-static inline bool hpte_write_permission(unsigned long pp, unsigned long key)
-{
-	if (key)
-		return pp == PP_RWRW;
-	return pp <= PP_RWRW;
-}
-
-static inline int hpte_get_skey_perm(unsigned long hpte_r, unsigned long amr)
-{
-	unsigned long skey;
-
-	skey = ((hpte_r & HPTE_R_KEY_HI) >> 57) |
-		((hpte_r & HPTE_R_KEY_LO) >> 9);
-	return (amr >> (62 - 2 * skey)) & 3;
-}
-
-static inline void lock_rmap(unsigned long *rmap)
-{
-	do {
-		while (test_bit(KVMPPC_RMAP_LOCK_BIT, rmap))
-			cpu_relax();
-	} while (test_and_set_bit_lock(KVMPPC_RMAP_LOCK_BIT, rmap));
-}
-
-static inline void unlock_rmap(unsigned long *rmap)
-{
-	__clear_bit_unlock(KVMPPC_RMAP_LOCK_BIT, rmap);
-}
-
-static inline bool slot_is_aligned(struct kvm_memory_slot *memslot,
-				   unsigned long pagesize)
-{
-	unsigned long mask = (pagesize >> PAGE_SHIFT) - 1;
-
-	if (pagesize <= PAGE_SIZE)
-		return 1;
-	return !(memslot->base_gfn & mask) && !(memslot->npages & mask);
-}
-
-#endif /* __ASM_KVM_BOOK3S_64_H__ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/kvm_book3s_asm.h b/ANDROID_3.4.5/arch/powerpc/include/asm/kvm_book3s_asm.h
deleted file mode 100644
index 1f2f5b61..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/kvm_book3s_asm.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, version 2, as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
- *
- * Copyright SUSE Linux Products GmbH 2009
- *
- * Authors: Alexander Graf <agraf@suse.de>
- */
-
-#ifndef __ASM_KVM_BOOK3S_ASM_H__
-#define __ASM_KVM_BOOK3S_ASM_H__
-
-#ifdef __ASSEMBLY__
-
-#ifdef CONFIG_KVM_BOOK3S_HANDLER
-
-#include <asm/kvm_asm.h>
-
-.macro DO_KVM intno
-	.if (\intno == BOOK3S_INTERRUPT_SYSTEM_RESET) || \
-	    (\intno == BOOK3S_INTERRUPT_MACHINE_CHECK) || \
-	    (\intno == BOOK3S_INTERRUPT_DATA_STORAGE) || \
-	    (\intno == BOOK3S_INTERRUPT_INST_STORAGE) || \
-	    (\intno == BOOK3S_INTERRUPT_DATA_SEGMENT) || \
-	    (\intno == BOOK3S_INTERRUPT_INST_SEGMENT) || \
-	    (\intno == BOOK3S_INTERRUPT_EXTERNAL) || \
-	    (\intno == BOOK3S_INTERRUPT_EXTERNAL_HV) || \
-	    (\intno == BOOK3S_INTERRUPT_ALIGNMENT) || \
-	    (\intno == BOOK3S_INTERRUPT_PROGRAM) || \
-	    (\intno == BOOK3S_INTERRUPT_FP_UNAVAIL) || \
-	    (\intno == BOOK3S_INTERRUPT_DECREMENTER) || \
-	    (\intno == BOOK3S_INTERRUPT_SYSCALL) || \
-	    (\intno == BOOK3S_INTERRUPT_TRACE) || \
-	    (\intno == BOOK3S_INTERRUPT_PERFMON) || \
-	    (\intno == BOOK3S_INTERRUPT_ALTIVEC) || \
-	    (\intno == BOOK3S_INTERRUPT_VSX)
-
-	b	kvmppc_trampoline_\intno
-kvmppc_resume_\intno:
-
-	.endif
-.endm
-
-#else
-
-.macro DO_KVM intno
-.endm
-
-#endif /* CONFIG_KVM_BOOK3S_HANDLER */
-
-#else  /*__ASSEMBLY__ */
-
-/*
- * This struct goes in the PACA on 64-bit processors.  It is used
- * to store host state that needs to be saved when we enter a guest
- * and restored when we exit, but isn't specific to any particular
- * guest or vcpu.  It also has some scratch fields used by the guest
- * exit code.
- */
-struct kvmppc_host_state {
-	ulong host_r1;
-	ulong host_r2;
-	ulong host_msr;
-	ulong vmhandler;
-	ulong scratch0;
-	ulong scratch1;
-	u8 in_guest;
-	u8 restore_hid5;
-	u8 napping;
-
-#ifdef CONFIG_KVM_BOOK3S_64_HV
-	struct kvm_vcpu *kvm_vcpu;
-	struct kvmppc_vcore *kvm_vcore;
-	unsigned long xics_phys;
-	u64 dabr;
-	u64 host_mmcr[3];
-	u32 host_pmc[8];
-	u64 host_purr;
-	u64 host_spurr;
-	u64 host_dscr;
-	u64 dec_expires;
-#endif
-};
-
-struct kvmppc_book3s_shadow_vcpu {
-	ulong gpr[14];
-	u32 cr;
-	u32 xer;
-
-	u32 fault_dsisr;
-	u32 last_inst;
-	ulong ctr;
-	ulong lr;
-	ulong pc;
-	ulong shadow_srr1;
-	ulong fault_dar;
-
-#ifdef CONFIG_PPC_BOOK3S_32
-	u32     sr[16];			/* Guest SRs */
-
-	struct kvmppc_host_state hstate;
-#endif
-
-#ifdef CONFIG_PPC_BOOK3S_64
-	u8 slb_max;			/* highest used guest slb entry */
-	struct  {
-		u64     esid;
-		u64     vsid;
-	} slb[64];			/* guest SLB */
-#endif
-};
-
-#endif /*__ASSEMBLY__ */
-
-#endif /* __ASM_KVM_BOOK3S_ASM_H__ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/kvm_booke.h b/ANDROID_3.4.5/arch/powerpc/include/asm/kvm_booke.h
deleted file mode 100644
index a90e0918..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/kvm_booke.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, version 2, as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
- *
- * Copyright SUSE Linux Products GmbH 2010
- *
- * Authors: Alexander Graf <agraf@suse.de>
- */
-
-#ifndef __ASM_KVM_BOOKE_H__
-#define __ASM_KVM_BOOKE_H__
-
-#include <linux/types.h>
-#include <linux/kvm_host.h>
-
-static inline void kvmppc_set_gpr(struct kvm_vcpu *vcpu, int num, ulong val)
-{
-	vcpu->arch.gpr[num] = val;
-}
-
-static inline ulong kvmppc_get_gpr(struct kvm_vcpu *vcpu, int num)
-{
-	return vcpu->arch.gpr[num];
-}
-
-static inline void kvmppc_set_cr(struct kvm_vcpu *vcpu, u32 val)
-{
-	vcpu->arch.cr = val;
-}
-
-static inline u32 kvmppc_get_cr(struct kvm_vcpu *vcpu)
-{
-	return vcpu->arch.cr;
-}
-
-static inline void kvmppc_set_xer(struct kvm_vcpu *vcpu, u32 val)
-{
-	vcpu->arch.xer = val;
-}
-
-static inline u32 kvmppc_get_xer(struct kvm_vcpu *vcpu)
-{
-	return vcpu->arch.xer;
-}
-
-static inline u32 kvmppc_get_last_inst(struct kvm_vcpu *vcpu)
-{
-	return vcpu->arch.last_inst;
-}
-
-static inline void kvmppc_set_ctr(struct kvm_vcpu *vcpu, ulong val)
-{
-	vcpu->arch.ctr = val;
-}
-
-static inline ulong kvmppc_get_ctr(struct kvm_vcpu *vcpu)
-{
-	return vcpu->arch.ctr;
-}
-
-static inline void kvmppc_set_lr(struct kvm_vcpu *vcpu, ulong val)
-{
-	vcpu->arch.lr = val;
-}
-
-static inline ulong kvmppc_get_lr(struct kvm_vcpu *vcpu)
-{
-	return vcpu->arch.lr;
-}
-
-static inline void kvmppc_set_pc(struct kvm_vcpu *vcpu, ulong val)
-{
-	vcpu->arch.pc = val;
-}
-
-static inline ulong kvmppc_get_pc(struct kvm_vcpu *vcpu)
-{
-	return vcpu->arch.pc;
-}
-
-static inline ulong kvmppc_get_fault_dar(struct kvm_vcpu *vcpu)
-{
-	return vcpu->arch.fault_dear;
-}
-
-static inline ulong kvmppc_get_msr(struct kvm_vcpu *vcpu)
-{
-	return vcpu->arch.shared->msr;
-}
-#endif /* __ASM_KVM_BOOKE_H__ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/kvm_e500.h b/ANDROID_3.4.5/arch/powerpc/include/asm/kvm_e500.h
deleted file mode 100644
index 8cd50a51..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/kvm_e500.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All rights reserved.
- *
- * Author: Yu Liu, <yu.liu@freescale.com>
- *
- * Description:
- * This file is derived from arch/powerpc/include/asm/kvm_44x.h,
- * by Hollis Blanchard <hollisb@us.ibm.com>.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, version 2, as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_KVM_E500_H__
-#define __ASM_KVM_E500_H__
-
-#include <linux/kvm_host.h>
-
-#define BOOKE_INTERRUPT_SIZE 36
-
-#define E500_PID_NUM   3
-#define E500_TLB_NUM   2
-
-#define E500_TLB_VALID 1
-#define E500_TLB_DIRTY 2
-
-struct tlbe_ref {
-	pfn_t pfn;
-	unsigned int flags; /* E500_TLB_* */
-};
-
-struct tlbe_priv {
-	struct tlbe_ref ref; /* TLB0 only -- TLB1 uses tlb_refs */
-};
-
-struct vcpu_id_table;
-
-struct kvmppc_e500_tlb_params {
-	int entries, ways, sets;
-};
-
-struct kvmppc_vcpu_e500 {
-	/* Unmodified copy of the guest's TLB -- shared with host userspace. */
-	struct kvm_book3e_206_tlb_entry *gtlb_arch;
-
-	/* Starting entry number in gtlb_arch[] */
-	int gtlb_offset[E500_TLB_NUM];
-
-	/* KVM internal information associated with each guest TLB entry */
-	struct tlbe_priv *gtlb_priv[E500_TLB_NUM];
-
-	struct kvmppc_e500_tlb_params gtlb_params[E500_TLB_NUM];
-
-	unsigned int gtlb_nv[E500_TLB_NUM];
-
-	/*
-	 * information associated with each host TLB entry --
-	 * TLB1 only for now.  If/when guest TLB1 entries can be
-	 * mapped with host TLB0, this will be used for that too.
-	 *
-	 * We don't want to use this for guest TLB0 because then we'd
-	 * have the overhead of doing the translation again even if
-	 * the entry is still in the guest TLB (e.g. we swapped out
-	 * and back, and our host TLB entries got evicted).
-	 */
-	struct tlbe_ref *tlb_refs[E500_TLB_NUM];
-	unsigned int host_tlb1_nv;
-
-	u32 host_pid[E500_PID_NUM];
-	u32 pid[E500_PID_NUM];
-	u32 svr;
-
-	/* vcpu id table */
-	struct vcpu_id_table *idt;
-
-	u32 l1csr0;
-	u32 l1csr1;
-	u32 hid0;
-	u32 hid1;
-	u32 tlb0cfg;
-	u32 tlb1cfg;
-	u64 mcar;
-
-	struct page **shared_tlb_pages;
-	int num_shared_tlb_pages;
-
-	struct kvm_vcpu vcpu;
-};
-
-static inline struct kvmppc_vcpu_e500 *to_e500(struct kvm_vcpu *vcpu)
-{
-	return container_of(vcpu, struct kvmppc_vcpu_e500, vcpu);
-}
-
-#endif /* __ASM_KVM_E500_H__ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/kvm_fpu.h b/ANDROID_3.4.5/arch/powerpc/include/asm/kvm_fpu.h
deleted file mode 100644
index 92daae13..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/kvm_fpu.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, version 2, as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
- *
- * Copyright Novell Inc. 2010
- *
- * Authors: Alexander Graf <agraf@suse.de>
- */
-
-#ifndef __ASM_KVM_FPU_H__
-#define __ASM_KVM_FPU_H__
-
-#include <linux/types.h>
-
-extern void fps_fres(u64 *fpscr, u32 *dst, u32 *src1);
-extern void fps_frsqrte(u64 *fpscr, u32 *dst, u32 *src1);
-extern void fps_fsqrts(u64 *fpscr, u32 *dst, u32 *src1);
-
-extern void fps_fadds(u64 *fpscr, u32 *dst, u32 *src1, u32 *src2);
-extern void fps_fdivs(u64 *fpscr, u32 *dst, u32 *src1, u32 *src2);
-extern void fps_fmuls(u64 *fpscr, u32 *dst, u32 *src1, u32 *src2);
-extern void fps_fsubs(u64 *fpscr, u32 *dst, u32 *src1, u32 *src2);
-
-extern void fps_fmadds(u64 *fpscr, u32 *dst, u32 *src1, u32 *src2,
-		       u32 *src3);
-extern void fps_fmsubs(u64 *fpscr, u32 *dst, u32 *src1, u32 *src2,
-		       u32 *src3);
-extern void fps_fnmadds(u64 *fpscr, u32 *dst, u32 *src1, u32 *src2,
-		        u32 *src3);
-extern void fps_fnmsubs(u64 *fpscr, u32 *dst, u32 *src1, u32 *src2,
-		        u32 *src3);
-extern void fps_fsel(u64 *fpscr, u32 *dst, u32 *src1, u32 *src2,
-		     u32 *src3);
-
-#define FPD_ONE_IN(name) extern void fpd_ ## name(u64 *fpscr, u32 *cr, \
-				u64 *dst, u64 *src1);
-#define FPD_TWO_IN(name) extern void fpd_ ## name(u64 *fpscr, u32 *cr, \
-				u64 *dst, u64 *src1, u64 *src2);
-#define FPD_THREE_IN(name) extern void fpd_ ## name(u64 *fpscr, u32 *cr, \
-				u64 *dst, u64 *src1, u64 *src2, u64 *src3);
-
-extern void fpd_fcmpu(u64 *fpscr, u32 *cr, u64 *src1, u64 *src2);
-extern void fpd_fcmpo(u64 *fpscr, u32 *cr, u64 *src1, u64 *src2);
-
-FPD_ONE_IN(fsqrts)
-FPD_ONE_IN(frsqrtes)
-FPD_ONE_IN(fres)
-FPD_ONE_IN(frsp)
-FPD_ONE_IN(fctiw)
-FPD_ONE_IN(fctiwz)
-FPD_ONE_IN(fsqrt)
-FPD_ONE_IN(fre)
-FPD_ONE_IN(frsqrte)
-FPD_ONE_IN(fneg)
-FPD_ONE_IN(fabs)
-FPD_TWO_IN(fadds)
-FPD_TWO_IN(fsubs)
-FPD_TWO_IN(fdivs)
-FPD_TWO_IN(fmuls)
-FPD_TWO_IN(fcpsgn)
-FPD_TWO_IN(fdiv)
-FPD_TWO_IN(fadd)
-FPD_TWO_IN(fmul)
-FPD_TWO_IN(fsub)
-FPD_THREE_IN(fmsubs)
-FPD_THREE_IN(fmadds)
-FPD_THREE_IN(fnmsubs)
-FPD_THREE_IN(fnmadds)
-FPD_THREE_IN(fsel)
-FPD_THREE_IN(fmsub)
-FPD_THREE_IN(fmadd)
-FPD_THREE_IN(fnmsub)
-FPD_THREE_IN(fnmadd)
-
-extern void kvm_cvt_fd(u32 *from, u64 *to);
-extern void kvm_cvt_df(u64 *from, u32 *to);
-
-#endif
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/kvm_host.h b/ANDROID_3.4.5/arch/powerpc/include/asm/kvm_host.h
deleted file mode 100644
index 52eb9c1f..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/kvm_host.h
+++ /dev/null
@@ -1,501 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, version 2, as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
- *
- * Copyright IBM Corp. 2007
- *
- * Authors: Hollis Blanchard <hollisb@us.ibm.com>
- */
-
-#ifndef __POWERPC_KVM_HOST_H__
-#define __POWERPC_KVM_HOST_H__
-
-#include <linux/mutex.h>
-#include <linux/hrtimer.h>
-#include <linux/interrupt.h>
-#include <linux/types.h>
-#include <linux/kvm_types.h>
-#include <linux/threads.h>
-#include <linux/spinlock.h>
-#include <linux/kvm_para.h>
-#include <linux/list.h>
-#include <linux/atomic.h>
-#include <asm/kvm_asm.h>
-#include <asm/processor.h>
-#include <asm/page.h>
-
-#define KVM_MAX_VCPUS		NR_CPUS
-#define KVM_MAX_VCORES		NR_CPUS
-#define KVM_MEMORY_SLOTS 32
-/* memory slots that does not exposed to userspace */
-#define KVM_PRIVATE_MEM_SLOTS 4
-#define KVM_MEM_SLOTS_NUM (KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS)
-
-#ifdef CONFIG_KVM_MMIO
-#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
-#endif
-
-#ifdef CONFIG_KVM_BOOK3S_64_HV
-#include <linux/mmu_notifier.h>
-
-#define KVM_ARCH_WANT_MMU_NOTIFIER
-
-struct kvm;
-extern int kvm_unmap_hva(struct kvm *kvm, unsigned long hva);
-extern int kvm_age_hva(struct kvm *kvm, unsigned long hva);
-extern int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);
-extern void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
-
-#endif
-
-/* We don't currently support large pages. */
-#define KVM_HPAGE_GFN_SHIFT(x)	0
-#define KVM_NR_PAGE_SIZES	1
-#define KVM_PAGES_PER_HPAGE(x)	(1UL<<31)
-
-#define HPTEG_CACHE_NUM			(1 << 15)
-#define HPTEG_HASH_BITS_PTE		13
-#define HPTEG_HASH_BITS_PTE_LONG	12
-#define HPTEG_HASH_BITS_VPTE		13
-#define HPTEG_HASH_BITS_VPTE_LONG	5
-#define HPTEG_HASH_NUM_PTE		(1 << HPTEG_HASH_BITS_PTE)
-#define HPTEG_HASH_NUM_PTE_LONG		(1 << HPTEG_HASH_BITS_PTE_LONG)
-#define HPTEG_HASH_NUM_VPTE		(1 << HPTEG_HASH_BITS_VPTE)
-#define HPTEG_HASH_NUM_VPTE_LONG	(1 << HPTEG_HASH_BITS_VPTE_LONG)
-
-/* Physical Address Mask - allowed range of real mode RAM access */
-#define KVM_PAM			0x0fffffffffffffffULL
-
-struct kvm;
-struct kvm_run;
-struct kvm_vcpu;
-
-struct lppaca;
-struct slb_shadow;
-struct dtl;
-
-struct kvm_vm_stat {
-	u32 remote_tlb_flush;
-};
-
-struct kvm_vcpu_stat {
-	u32 sum_exits;
-	u32 mmio_exits;
-	u32 dcr_exits;
-	u32 signal_exits;
-	u32 light_exits;
-	/* Account for special types of light exits: */
-	u32 itlb_real_miss_exits;
-	u32 itlb_virt_miss_exits;
-	u32 dtlb_real_miss_exits;
-	u32 dtlb_virt_miss_exits;
-	u32 syscall_exits;
-	u32 isi_exits;
-	u32 dsi_exits;
-	u32 emulated_inst_exits;
-	u32 dec_exits;
-	u32 ext_intr_exits;
-	u32 halt_wakeup;
-#ifdef CONFIG_PPC_BOOK3S
-	u32 pf_storage;
-	u32 pf_instruc;
-	u32 sp_storage;
-	u32 sp_instruc;
-	u32 queue_intr;
-	u32 ld;
-	u32 ld_slow;
-	u32 st;
-	u32 st_slow;
-#endif
-};
-
-enum kvm_exit_types {
-	MMIO_EXITS,
-	DCR_EXITS,
-	SIGNAL_EXITS,
-	ITLB_REAL_MISS_EXITS,
-	ITLB_VIRT_MISS_EXITS,
-	DTLB_REAL_MISS_EXITS,
-	DTLB_VIRT_MISS_EXITS,
-	SYSCALL_EXITS,
-	ISI_EXITS,
-	DSI_EXITS,
-	EMULATED_INST_EXITS,
-	EMULATED_MTMSRWE_EXITS,
-	EMULATED_WRTEE_EXITS,
-	EMULATED_MTSPR_EXITS,
-	EMULATED_MFSPR_EXITS,
-	EMULATED_MTMSR_EXITS,
-	EMULATED_MFMSR_EXITS,
-	EMULATED_TLBSX_EXITS,
-	EMULATED_TLBWE_EXITS,
-	EMULATED_RFI_EXITS,
-	DEC_EXITS,
-	EXT_INTR_EXITS,
-	HALT_WAKEUP,
-	USR_PR_INST,
-	FP_UNAVAIL,
-	DEBUG_EXITS,
-	TIMEINGUEST,
-	__NUMBER_OF_KVM_EXIT_TYPES
-};
-
-/* allow access to big endian 32bit upper/lower parts and 64bit var */
-struct kvmppc_exit_timing {
-	union {
-		u64 tv64;
-		struct {
-			u32 tbu, tbl;
-		} tv32;
-	};
-};
-
-struct kvmppc_pginfo {
-	unsigned long pfn;
-	atomic_t refcnt;
-};
-
-struct kvmppc_spapr_tce_table {
-	struct list_head list;
-	struct kvm *kvm;
-	u64 liobn;
-	u32 window_size;
-	struct page *pages[0];
-};
-
-struct kvmppc_linear_info {
-	void		*base_virt;
-	unsigned long	 base_pfn;
-	unsigned long	 npages;
-	struct list_head list;
-	atomic_t	 use_count;
-	int		 type;
-};
-
-/*
- * The reverse mapping array has one entry for each HPTE,
- * which stores the guest's view of the second word of the HPTE
- * (including the guest physical address of the mapping),
- * plus forward and backward pointers in a doubly-linked ring
- * of HPTEs that map the same host page.  The pointers in this
- * ring are 32-bit HPTE indexes, to save space.
- */
-struct revmap_entry {
-	unsigned long guest_rpte;
-	unsigned int forw, back;
-};
-
-/*
- * We use the top bit of each memslot->rmap entry as a lock bit,
- * and bit 32 as a present flag.  The bottom 32 bits are the
- * index in the guest HPT of a HPTE that points to the page.
- */
-#define KVMPPC_RMAP_LOCK_BIT	63
-#define KVMPPC_RMAP_RC_SHIFT	32
-#define KVMPPC_RMAP_REFERENCED	(HPTE_R_R << KVMPPC_RMAP_RC_SHIFT)
-#define KVMPPC_RMAP_CHANGED	(HPTE_R_C << KVMPPC_RMAP_RC_SHIFT)
-#define KVMPPC_RMAP_PRESENT	0x100000000ul
-#define KVMPPC_RMAP_INDEX	0xfffffffful
-
-/* Low-order bits in kvm->arch.slot_phys[][] */
-#define KVMPPC_PAGE_ORDER_MASK	0x1f
-#define KVMPPC_PAGE_NO_CACHE	HPTE_R_I	/* 0x20 */
-#define KVMPPC_PAGE_WRITETHRU	HPTE_R_W	/* 0x40 */
-#define KVMPPC_GOT_PAGE		0x80
-
-struct kvm_arch_memory_slot {
-};
-
-struct kvm_arch {
-#ifdef CONFIG_KVM_BOOK3S_64_HV
-	unsigned long hpt_virt;
-	struct revmap_entry *revmap;
-	unsigned int lpid;
-	unsigned int host_lpid;
-	unsigned long host_lpcr;
-	unsigned long sdr1;
-	unsigned long host_sdr1;
-	int tlbie_lock;
-	unsigned long lpcr;
-	unsigned long rmor;
-	struct kvmppc_linear_info *rma;
-	unsigned long vrma_slb_v;
-	int rma_setup_done;
-	int using_mmu_notifiers;
-	struct list_head spapr_tce_tables;
-	spinlock_t slot_phys_lock;
-	unsigned long *slot_phys[KVM_MEM_SLOTS_NUM];
-	int slot_npages[KVM_MEM_SLOTS_NUM];
-	unsigned short last_vcpu[NR_CPUS];
-	struct kvmppc_vcore *vcores[KVM_MAX_VCORES];
-	struct kvmppc_linear_info *hpt_li;
-#endif /* CONFIG_KVM_BOOK3S_64_HV */
-};
-
-/*
- * Struct for a virtual core.
- * Note: entry_exit_count combines an entry count in the bottom 8 bits
- * and an exit count in the next 8 bits.  This is so that we can
- * atomically increment the entry count iff the exit count is 0
- * without taking the lock.
- */
-struct kvmppc_vcore {
-	int n_runnable;
-	int n_busy;
-	int num_threads;
-	int entry_exit_count;
-	int n_woken;
-	int nap_count;
-	int napping_threads;
-	u16 pcpu;
-	u8 vcore_state;
-	u8 in_guest;
-	struct list_head runnable_threads;
-	spinlock_t lock;
-	wait_queue_head_t wq;
-};
-
-#define VCORE_ENTRY_COUNT(vc)	((vc)->entry_exit_count & 0xff)
-#define VCORE_EXIT_COUNT(vc)	((vc)->entry_exit_count >> 8)
-
-/* Values for vcore_state */
-#define VCORE_INACTIVE	0
-#define VCORE_RUNNING	1
-#define VCORE_EXITING	2
-#define VCORE_SLEEPING	3
-
-struct kvmppc_pte {
-	ulong eaddr;
-	u64 vpage;
-	ulong raddr;
-	bool may_read		: 1;
-	bool may_write		: 1;
-	bool may_execute	: 1;
-};
-
-struct kvmppc_mmu {
-	/* book3s_64 only */
-	void (*slbmte)(struct kvm_vcpu *vcpu, u64 rb, u64 rs);
-	u64  (*slbmfee)(struct kvm_vcpu *vcpu, u64 slb_nr);
-	u64  (*slbmfev)(struct kvm_vcpu *vcpu, u64 slb_nr);
-	void (*slbie)(struct kvm_vcpu *vcpu, u64 slb_nr);
-	void (*slbia)(struct kvm_vcpu *vcpu);
-	/* book3s */
-	void (*mtsrin)(struct kvm_vcpu *vcpu, u32 srnum, ulong value);
-	u32  (*mfsrin)(struct kvm_vcpu *vcpu, u32 srnum);
-	int  (*xlate)(struct kvm_vcpu *vcpu, gva_t eaddr, struct kvmppc_pte *pte, bool data);
-	void (*reset_msr)(struct kvm_vcpu *vcpu);
-	void (*tlbie)(struct kvm_vcpu *vcpu, ulong addr, bool large);
-	int  (*esid_to_vsid)(struct kvm_vcpu *vcpu, ulong esid, u64 *vsid);
-	u64  (*ea_to_vp)(struct kvm_vcpu *vcpu, gva_t eaddr, bool data);
-	bool (*is_dcbz32)(struct kvm_vcpu *vcpu);
-};
-
-struct kvmppc_slb {
-	u64 esid;
-	u64 vsid;
-	u64 orige;
-	u64 origv;
-	bool valid	: 1;
-	bool Ks		: 1;
-	bool Kp		: 1;
-	bool nx		: 1;
-	bool large	: 1;	/* PTEs are 16MB */
-	bool tb		: 1;	/* 1TB segment */
-	bool class	: 1;
-};
-
-struct kvm_vcpu_arch {
-	ulong host_stack;
-	u32 host_pid;
-#ifdef CONFIG_PPC_BOOK3S
-	struct kvmppc_slb slb[64];
-	int slb_max;		/* 1 + index of last valid entry in slb[] */
-	int slb_nr;		/* total number of entries in SLB */
-	struct kvmppc_mmu mmu;
-#endif
-
-	ulong gpr[32];
-
-	u64 fpr[32];
-	u64 fpscr;
-
-#ifdef CONFIG_SPE
-	ulong evr[32];
-	ulong spefscr;
-	ulong host_spefscr;
-	u64 acc;
-#endif
-#ifdef CONFIG_ALTIVEC
-	vector128 vr[32];
-	vector128 vscr;
-#endif
-
-#ifdef CONFIG_VSX
-	u64 vsr[64];
-#endif
-
-#ifdef CONFIG_PPC_BOOK3S
-	/* For Gekko paired singles */
-	u32 qpr[32];
-#endif
-
-	ulong pc;
-	ulong ctr;
-	ulong lr;
-
-	ulong xer;
-	u32 cr;
-
-#ifdef CONFIG_PPC_BOOK3S
-	ulong hflags;
-	ulong guest_owned_ext;
-	ulong purr;
-	ulong spurr;
-	ulong dscr;
-	ulong amr;
-	ulong uamor;
-	u32 ctrl;
-	ulong dabr;
-#endif
-	u32 vrsave; /* also USPRG0 */
-	u32 mmucr;
-	ulong shadow_msr;
-	ulong csrr0;
-	ulong csrr1;
-	ulong dsrr0;
-	ulong dsrr1;
-	ulong mcsrr0;
-	ulong mcsrr1;
-	ulong mcsr;
-	u32 dec;
-	u32 decar;
-	u32 tbl;
-	u32 tbu;
-	u32 tcr;
-	ulong tsr; /* we need to perform set/clr_bits() which requires ulong */
-	u32 ivor[64];
-	ulong ivpr;
-	u32 pvr;
-
-	u32 shadow_pid;
-	u32 shadow_pid1;
-	u32 pid;
-	u32 swap_pid;
-
-	u32 ccr0;
-	u32 ccr1;
-	u32 dbcr0;
-	u32 dbcr1;
-	u32 dbsr;
-
-	u64 mmcr[3];
-	u32 pmc[8];
-
-#ifdef CONFIG_KVM_EXIT_TIMING
-	struct mutex exit_timing_lock;
-	struct kvmppc_exit_timing timing_exit;
-	struct kvmppc_exit_timing timing_last_enter;
-	u32 last_exit_type;
-	u32 timing_count_type[__NUMBER_OF_KVM_EXIT_TYPES];
-	u64 timing_sum_duration[__NUMBER_OF_KVM_EXIT_TYPES];
-	u64 timing_sum_quad_duration[__NUMBER_OF_KVM_EXIT_TYPES];
-	u64 timing_min_duration[__NUMBER_OF_KVM_EXIT_TYPES];
-	u64 timing_max_duration[__NUMBER_OF_KVM_EXIT_TYPES];
-	u64 timing_last_exit;
-	struct dentry *debugfs_exit_timing;
-#endif
-
-#ifdef CONFIG_PPC_BOOK3S
-	ulong fault_dar;
-	u32 fault_dsisr;
-#endif
-
-#ifdef CONFIG_BOOKE
-	ulong fault_dear;
-	ulong fault_esr;
-	ulong queued_dear;
-	ulong queued_esr;
-#endif
-	gpa_t paddr_accessed;
-
-	u8 io_gpr; /* GPR used as IO source/target */
-	u8 mmio_is_bigendian;
-	u8 mmio_sign_extend;
-	u8 dcr_needed;
-	u8 dcr_is_write;
-	u8 osi_needed;
-	u8 osi_enabled;
-	u8 papr_enabled;
-	u8 sane;
-	u8 cpu_type;
-	u8 hcall_needed;
-
-	u32 cpr0_cfgaddr; /* holds the last set cpr0_cfgaddr */
-
-	struct hrtimer dec_timer;
-	struct tasklet_struct tasklet;
-	u64 dec_jiffies;
-	u64 dec_expires;
-	unsigned long pending_exceptions;
-	u16 last_cpu;
-	u8 ceded;
-	u8 prodded;
-	u32 last_inst;
-
-	struct lppaca *vpa;
-	struct slb_shadow *slb_shadow;
-	struct dtl *dtl;
-	struct dtl *dtl_end;
-
-	wait_queue_head_t *wqp;
-	struct kvmppc_vcore *vcore;
-	int ret;
-	int trap;
-	int state;
-	int ptid;
-	bool timer_running;
-	wait_queue_head_t cpu_run;
-
-	struct kvm_vcpu_arch_shared *shared;
-	unsigned long magic_page_pa; /* phys addr to map the magic page to */
-	unsigned long magic_page_ea; /* effect. addr to map the magic page to */
-
-#ifdef CONFIG_KVM_BOOK3S_64_HV
-	struct kvm_vcpu_arch_shared shregs;
-
-	unsigned long pgfault_addr;
-	long pgfault_index;
-	unsigned long pgfault_hpte[2];
-
-	struct list_head run_list;
-	struct task_struct *run_task;
-	struct kvm_run *kvm_run;
-	pgd_t *pgdir;
-#endif
-};
-
-/* Values for vcpu->arch.state */
-#define KVMPPC_VCPU_STOPPED		0
-#define KVMPPC_VCPU_BUSY_IN_HOST	1
-#define KVMPPC_VCPU_RUNNABLE		2
-
-/* Values for vcpu->arch.io_gpr */
-#define KVM_MMIO_REG_MASK	0x001f
-#define KVM_MMIO_REG_EXT_MASK	0xffe0
-#define KVM_MMIO_REG_GPR	0x0000
-#define KVM_MMIO_REG_FPR	0x0020
-#define KVM_MMIO_REG_QPR	0x0040
-#define KVM_MMIO_REG_FQPR	0x0060
-
-#endif /* __POWERPC_KVM_HOST_H__ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/kvm_para.h b/ANDROID_3.4.5/arch/powerpc/include/asm/kvm_para.h
deleted file mode 100644
index 7b754e74..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/kvm_para.h
+++ /dev/null
@@ -1,211 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, version 2, as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
- *
- * Copyright IBM Corp. 2008
- *
- * Authors: Hollis Blanchard <hollisb@us.ibm.com>
- */
-
-#ifndef __POWERPC_KVM_PARA_H__
-#define __POWERPC_KVM_PARA_H__
-
-#include <linux/types.h>
-
-/*
- * Additions to this struct must only occur at the end, and should be
- * accompanied by a KVM_MAGIC_FEAT flag to advertise that they are present
- * (albeit not necessarily relevant to the current target hardware platform).
- *
- * Struct fields are always 32 or 64 bit aligned, depending on them being 32
- * or 64 bit wide respectively.
- *
- * See Documentation/virtual/kvm/ppc-pv.txt
- */
-struct kvm_vcpu_arch_shared {
-	__u64 scratch1;
-	__u64 scratch2;
-	__u64 scratch3;
-	__u64 critical;		/* Guest may not get interrupts if == r1 */
-	__u64 sprg0;
-	__u64 sprg1;
-	__u64 sprg2;
-	__u64 sprg3;
-	__u64 srr0;
-	__u64 srr1;
-	__u64 dar;		/* dear on BookE */
-	__u64 msr;
-	__u32 dsisr;
-	__u32 int_pending;	/* Tells the guest if we have an interrupt */
-	__u32 sr[16];
-	__u32 mas0;
-	__u32 mas1;
-	__u64 mas7_3;
-	__u64 mas2;
-	__u32 mas4;
-	__u32 mas6;
-	__u32 esr;
-	__u32 pir;
-
-	/*
-	 * SPRG4-7 are user-readable, so we can only keep these consistent
-	 * between the shared area and the real registers when there's an
-	 * intervening exit to KVM.  This also applies to SPRG3 on some
-	 * chips.
-	 *
-	 * This suffices for access by guest userspace, since in PR-mode
-	 * KVM, an exit must occur when changing the guest's MSR[PR].
-	 * If the guest kernel writes to SPRG3-7 via the shared area, it
-	 * must also use the shared area for reading while in kernel space.
-	 */
-	__u64 sprg4;
-	__u64 sprg5;
-	__u64 sprg6;
-	__u64 sprg7;
-};
-
-#define KVM_SC_MAGIC_R0		0x4b564d21 /* "KVM!" */
-#define HC_VENDOR_KVM		(42 << 16)
-#define HC_EV_SUCCESS		0
-#define HC_EV_UNIMPLEMENTED	12
-
-#define KVM_FEATURE_MAGIC_PAGE	1
-
-#define KVM_MAGIC_FEAT_SR		(1 << 0)
-
-/* MASn, ESR, PIR, and high SPRGs */
-#define KVM_MAGIC_FEAT_MAS0_TO_SPRG7	(1 << 1)
-
-#ifdef __KERNEL__
-
-#ifdef CONFIG_KVM_GUEST
-
-#include <linux/of.h>
-
-static inline int kvm_para_available(void)
-{
-	struct device_node *hyper_node;
-
-	hyper_node = of_find_node_by_path("/hypervisor");
-	if (!hyper_node)
-		return 0;
-
-	if (!of_device_is_compatible(hyper_node, "linux,kvm"))
-		return 0;
-
-	return 1;
-}
-
-extern unsigned long kvm_hypercall(unsigned long *in,
-				   unsigned long *out,
-				   unsigned long nr);
-
-#else
-
-static inline int kvm_para_available(void)
-{
-	return 0;
-}
-
-static unsigned long kvm_hypercall(unsigned long *in,
-				   unsigned long *out,
-				   unsigned long nr)
-{
-	return HC_EV_UNIMPLEMENTED;
-}
-
-#endif
-
-static inline long kvm_hypercall0_1(unsigned int nr, unsigned long *r2)
-{
-	unsigned long in[8];
-	unsigned long out[8];
-	unsigned long r;
-
-	r = kvm_hypercall(in, out, nr | HC_VENDOR_KVM);
-	*r2 = out[0];
-
-	return r;
-}
-
-static inline long kvm_hypercall0(unsigned int nr)
-{
-	unsigned long in[8];
-	unsigned long out[8];
-
-	return kvm_hypercall(in, out, nr | HC_VENDOR_KVM);
-}
-
-static inline long kvm_hypercall1(unsigned int nr, unsigned long p1)
-{
-	unsigned long in[8];
-	unsigned long out[8];
-
-	in[0] = p1;
-	return kvm_hypercall(in, out, nr | HC_VENDOR_KVM);
-}
-
-static inline long kvm_hypercall2(unsigned int nr, unsigned long p1,
-				  unsigned long p2)
-{
-	unsigned long in[8];
-	unsigned long out[8];
-
-	in[0] = p1;
-	in[1] = p2;
-	return kvm_hypercall(in, out, nr | HC_VENDOR_KVM);
-}
-
-static inline long kvm_hypercall3(unsigned int nr, unsigned long p1,
-				  unsigned long p2, unsigned long p3)
-{
-	unsigned long in[8];
-	unsigned long out[8];
-
-	in[0] = p1;
-	in[1] = p2;
-	in[2] = p3;
-	return kvm_hypercall(in, out, nr | HC_VENDOR_KVM);
-}
-
-static inline long kvm_hypercall4(unsigned int nr, unsigned long p1,
-				  unsigned long p2, unsigned long p3,
-				  unsigned long p4)
-{
-	unsigned long in[8];
-	unsigned long out[8];
-
-	in[0] = p1;
-	in[1] = p2;
-	in[2] = p3;
-	in[3] = p4;
-	return kvm_hypercall(in, out, nr | HC_VENDOR_KVM);
-}
-
-
-static inline unsigned int kvm_arch_para_features(void)
-{
-	unsigned long r;
-
-	if (!kvm_para_available())
-		return 0;
-
-	if(kvm_hypercall0_1(KVM_HC_FEATURES, &r))
-		return 0;
-
-	return r;
-}
-
-#endif /* __KERNEL__ */
-
-#endif /* __POWERPC_KVM_PARA_H__ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/kvm_ppc.h b/ANDROID_3.4.5/arch/powerpc/include/asm/kvm_ppc.h
deleted file mode 100644
index 9d6dee0f..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/kvm_ppc.h
+++ /dev/null
@@ -1,207 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, version 2, as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
- *
- * Copyright IBM Corp. 2008
- *
- * Authors: Hollis Blanchard <hollisb@us.ibm.com>
- */
-
-#ifndef __POWERPC_KVM_PPC_H__
-#define __POWERPC_KVM_PPC_H__
-
-/* This file exists just so we can dereference kvm_vcpu, avoiding nested header
- * dependencies. */
-
-#include <linux/mutex.h>
-#include <linux/timer.h>
-#include <linux/types.h>
-#include <linux/kvm_types.h>
-#include <linux/kvm_host.h>
-#ifdef CONFIG_PPC_BOOK3S
-#include <asm/kvm_book3s.h>
-#else
-#include <asm/kvm_booke.h>
-#endif
-#ifdef CONFIG_KVM_BOOK3S_64_HANDLER
-#include <asm/paca.h>
-#endif
-
-enum emulation_result {
-	EMULATE_DONE,         /* no further processing */
-	EMULATE_DO_MMIO,      /* kvm_run filled with MMIO request */
-	EMULATE_DO_DCR,       /* kvm_run filled with DCR request */
-	EMULATE_FAIL,         /* can't emulate this instruction */
-	EMULATE_AGAIN,        /* something went wrong. go again */
-};
-
-extern int kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu);
-extern int __kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu);
-extern char kvmppc_handlers_start[];
-extern unsigned long kvmppc_handler_len;
-extern void kvmppc_handler_highmem(void);
-
-extern void kvmppc_dump_vcpu(struct kvm_vcpu *vcpu);
-extern int kvmppc_handle_load(struct kvm_run *run, struct kvm_vcpu *vcpu,
-                              unsigned int rt, unsigned int bytes,
-                              int is_bigendian);
-extern int kvmppc_handle_loads(struct kvm_run *run, struct kvm_vcpu *vcpu,
-                               unsigned int rt, unsigned int bytes,
-                               int is_bigendian);
-extern int kvmppc_handle_store(struct kvm_run *run, struct kvm_vcpu *vcpu,
-                               u64 val, unsigned int bytes, int is_bigendian);
-
-extern int kvmppc_emulate_instruction(struct kvm_run *run,
-                                      struct kvm_vcpu *vcpu);
-extern int kvmppc_emulate_mmio(struct kvm_run *run, struct kvm_vcpu *vcpu);
-extern void kvmppc_emulate_dec(struct kvm_vcpu *vcpu);
-extern u32 kvmppc_get_dec(struct kvm_vcpu *vcpu, u64 tb);
-extern void kvmppc_decrementer_func(unsigned long data);
-extern int kvmppc_sanity_check(struct kvm_vcpu *vcpu);
-
-/* Core-specific hooks */
-
-extern void kvmppc_mmu_map(struct kvm_vcpu *vcpu, u64 gvaddr, gpa_t gpaddr,
-                           unsigned int gtlb_idx);
-extern void kvmppc_mmu_priv_switch(struct kvm_vcpu *vcpu, int usermode);
-extern void kvmppc_mmu_switch_pid(struct kvm_vcpu *vcpu, u32 pid);
-extern void kvmppc_mmu_destroy(struct kvm_vcpu *vcpu);
-extern int kvmppc_mmu_init(struct kvm_vcpu *vcpu);
-extern int kvmppc_mmu_dtlb_index(struct kvm_vcpu *vcpu, gva_t eaddr);
-extern int kvmppc_mmu_itlb_index(struct kvm_vcpu *vcpu, gva_t eaddr);
-extern gpa_t kvmppc_mmu_xlate(struct kvm_vcpu *vcpu, unsigned int gtlb_index,
-                              gva_t eaddr);
-extern void kvmppc_mmu_dtlb_miss(struct kvm_vcpu *vcpu);
-extern void kvmppc_mmu_itlb_miss(struct kvm_vcpu *vcpu);
-
-extern struct kvm_vcpu *kvmppc_core_vcpu_create(struct kvm *kvm,
-                                                unsigned int id);
-extern void kvmppc_core_vcpu_free(struct kvm_vcpu *vcpu);
-extern int kvmppc_core_vcpu_setup(struct kvm_vcpu *vcpu);
-extern int kvmppc_core_check_processor_compat(void);
-extern int kvmppc_core_vcpu_translate(struct kvm_vcpu *vcpu,
-                                      struct kvm_translation *tr);
-
-extern void kvmppc_core_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
-extern void kvmppc_core_vcpu_put(struct kvm_vcpu *vcpu);
-
-extern void kvmppc_core_prepare_to_enter(struct kvm_vcpu *vcpu);
-extern int kvmppc_core_pending_dec(struct kvm_vcpu *vcpu);
-extern void kvmppc_core_queue_program(struct kvm_vcpu *vcpu, ulong flags);
-extern void kvmppc_core_queue_dec(struct kvm_vcpu *vcpu);
-extern void kvmppc_core_dequeue_dec(struct kvm_vcpu *vcpu);
-extern void kvmppc_core_queue_external(struct kvm_vcpu *vcpu,
-                                       struct kvm_interrupt *irq);
-extern void kvmppc_core_dequeue_external(struct kvm_vcpu *vcpu,
-                                         struct kvm_interrupt *irq);
-
-extern int kvmppc_core_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu,
-                                  unsigned int op, int *advance);
-extern int kvmppc_core_emulate_mtspr(struct kvm_vcpu *vcpu, int sprn, int rs);
-extern int kvmppc_core_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, int rt);
-
-extern int kvmppc_booke_init(void);
-extern void kvmppc_booke_exit(void);
-
-extern void kvmppc_core_destroy_mmu(struct kvm_vcpu *vcpu);
-extern int kvmppc_kvm_pv(struct kvm_vcpu *vcpu);
-extern void kvmppc_map_magic(struct kvm_vcpu *vcpu);
-
-extern long kvmppc_alloc_hpt(struct kvm *kvm);
-extern void kvmppc_free_hpt(struct kvm *kvm);
-extern long kvmppc_prepare_vrma(struct kvm *kvm,
-				struct kvm_userspace_memory_region *mem);
-extern void kvmppc_map_vrma(struct kvm_vcpu *vcpu,
-			struct kvm_memory_slot *memslot, unsigned long porder);
-extern int kvmppc_pseries_do_hcall(struct kvm_vcpu *vcpu);
-extern long kvm_vm_ioctl_create_spapr_tce(struct kvm *kvm,
-				struct kvm_create_spapr_tce *args);
-extern long kvm_vm_ioctl_allocate_rma(struct kvm *kvm,
-				struct kvm_allocate_rma *rma);
-extern struct kvmppc_linear_info *kvm_alloc_rma(void);
-extern void kvm_release_rma(struct kvmppc_linear_info *ri);
-extern struct kvmppc_linear_info *kvm_alloc_hpt(void);
-extern void kvm_release_hpt(struct kvmppc_linear_info *li);
-extern int kvmppc_core_init_vm(struct kvm *kvm);
-extern void kvmppc_core_destroy_vm(struct kvm *kvm);
-extern int kvmppc_core_prepare_memory_region(struct kvm *kvm,
-				struct kvm_userspace_memory_region *mem);
-extern void kvmppc_core_commit_memory_region(struct kvm *kvm,
-				struct kvm_userspace_memory_region *mem);
-
-/*
- * Cuts out inst bits with ordering according to spec.
- * That means the leftmost bit is zero. All given bits are included.
- */
-static inline u32 kvmppc_get_field(u64 inst, int msb, int lsb)
-{
-	u32 r;
-	u32 mask;
-
-	BUG_ON(msb > lsb);
-
-	mask = (1 << (lsb - msb + 1)) - 1;
-	r = (inst >> (63 - lsb)) & mask;
-
-	return r;
-}
-
-/*
- * Replaces inst bits with ordering according to spec.
- */
-static inline u32 kvmppc_set_field(u64 inst, int msb, int lsb, int value)
-{
-	u32 r;
-	u32 mask;
-
-	BUG_ON(msb > lsb);
-
-	mask = ((1 << (lsb - msb + 1)) - 1) << (63 - lsb);
-	r = (inst & ~mask) | ((value << (63 - lsb)) & mask);
-
-	return r;
-}
-
-void kvmppc_core_get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs);
-int kvmppc_core_set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs);
-
-void kvmppc_get_sregs_ivor(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs);
-int kvmppc_set_sregs_ivor(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs);
-
-int kvm_vcpu_ioctl_get_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg);
-int kvm_vcpu_ioctl_set_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg);
-
-void kvmppc_set_pid(struct kvm_vcpu *vcpu, u32 pid);
-
-#ifdef CONFIG_KVM_BOOK3S_64_HV
-static inline void kvmppc_set_xics_phys(int cpu, unsigned long addr)
-{
-	paca[cpu].kvm_hstate.xics_phys = addr;
-}
-
-extern void kvm_linear_init(void);
-
-#else
-static inline void kvmppc_set_xics_phys(int cpu, unsigned long addr)
-{}
-
-static inline void kvm_linear_init(void)
-{}
-#endif
-
-int kvm_vcpu_ioctl_config_tlb(struct kvm_vcpu *vcpu,
-			      struct kvm_config_tlb *cfg);
-int kvm_vcpu_ioctl_dirty_tlb(struct kvm_vcpu *vcpu,
-			     struct kvm_dirty_tlb *cfg);
-
-#endif /* __POWERPC_KVM_PPC_H__ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/libata-portmap.h b/ANDROID_3.4.5/arch/powerpc/include/asm/libata-portmap.h
deleted file mode 100644
index 4d851804..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/libata-portmap.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef __ASM_POWERPC_LIBATA_PORTMAP_H
-#define __ASM_POWERPC_LIBATA_PORTMAP_H
-
-#define ATA_PRIMARY_CMD	0x1F0
-#define ATA_PRIMARY_CTL	0x3F6
-#define ATA_PRIMARY_IRQ(dev)	pci_get_legacy_ide_irq(dev, 0)
-
-#define ATA_SECONDARY_CMD	0x170
-#define ATA_SECONDARY_CTL	0x376
-#define ATA_SECONDARY_IRQ(dev)	pci_get_legacy_ide_irq(dev, 1)
-
-#endif
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/linkage.h b/ANDROID_3.4.5/arch/powerpc/include/asm/linkage.h
deleted file mode 100644
index e1c4ac1c..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/linkage.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_POWERPC_LINKAGE_H
-#define _ASM_POWERPC_LINKAGE_H
-
-/* Nothing to see here... */
-
-#endif	/* _ASM_POWERPC_LINKAGE_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/local.h b/ANDROID_3.4.5/arch/powerpc/include/asm/local.h
deleted file mode 100644
index b8da9136..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/local.h
+++ /dev/null
@@ -1,175 +0,0 @@
-#ifndef _ARCH_POWERPC_LOCAL_H
-#define _ARCH_POWERPC_LOCAL_H
-
-#include <linux/percpu.h>
-#include <linux/atomic.h>
-
-typedef struct
-{
-	atomic_long_t a;
-} local_t;
-
-#define LOCAL_INIT(i)	{ ATOMIC_LONG_INIT(i) }
-
-#define local_read(l)	atomic_long_read(&(l)->a)
-#define local_set(l,i)	atomic_long_set(&(l)->a, (i))
-
-#define local_add(i,l)	atomic_long_add((i),(&(l)->a))
-#define local_sub(i,l)	atomic_long_sub((i),(&(l)->a))
-#define local_inc(l)	atomic_long_inc(&(l)->a)
-#define local_dec(l)	atomic_long_dec(&(l)->a)
-
-static __inline__ long local_add_return(long a, local_t *l)
-{
-	long t;
-
-	__asm__ __volatile__(
-"1:"	PPC_LLARX(%0,0,%2,0) "			# local_add_return\n\
-	add	%0,%1,%0\n"
-	PPC405_ERR77(0,%2)
-	PPC_STLCX	"%0,0,%2 \n\
-	bne-	1b"
-	: "=&r" (t)
-	: "r" (a), "r" (&(l->a.counter))
-	: "cc", "memory");
-
-	return t;
-}
-
-#define local_add_negative(a, l)	(local_add_return((a), (l)) < 0)
-
-static __inline__ long local_sub_return(long a, local_t *l)
-{
-	long t;
-
-	__asm__ __volatile__(
-"1:"	PPC_LLARX(%0,0,%2,0) "			# local_sub_return\n\
-	subf	%0,%1,%0\n"
-	PPC405_ERR77(0,%2)
-	PPC_STLCX	"%0,0,%2 \n\
-	bne-	1b"
-	: "=&r" (t)
-	: "r" (a), "r" (&(l->a.counter))
-	: "cc", "memory");
-
-	return t;
-}
-
-static __inline__ long local_inc_return(local_t *l)
-{
-	long t;
-
-	__asm__ __volatile__(
-"1:"	PPC_LLARX(%0,0,%1,0) "			# local_inc_return\n\
-	addic	%0,%0,1\n"
-	PPC405_ERR77(0,%1)
-	PPC_STLCX	"%0,0,%1 \n\
-	bne-	1b"
-	: "=&r" (t)
-	: "r" (&(l->a.counter))
-	: "cc", "xer", "memory");
-
-	return t;
-}
-
-/*
- * local_inc_and_test - increment and test
- * @l: pointer of type local_t
- *
- * Atomically increments @l by 1
- * and returns true if the result is zero, or false for all
- * other cases.
- */
-#define local_inc_and_test(l) (local_inc_return(l) == 0)
-
-static __inline__ long local_dec_return(local_t *l)
-{
-	long t;
-
-	__asm__ __volatile__(
-"1:"	PPC_LLARX(%0,0,%1,0) "			# local_dec_return\n\
-	addic	%0,%0,-1\n"
-	PPC405_ERR77(0,%1)
-	PPC_STLCX	"%0,0,%1\n\
-	bne-	1b"
-	: "=&r" (t)
-	: "r" (&(l->a.counter))
-	: "cc", "xer", "memory");
-
-	return t;
-}
-
-#define local_cmpxchg(l, o, n) \
-	(cmpxchg_local(&((l)->a.counter), (o), (n)))
-#define local_xchg(l, n) (xchg_local(&((l)->a.counter), (n)))
-
-/**
- * local_add_unless - add unless the number is a given value
- * @l: pointer of type local_t
- * @a: the amount to add to v...
- * @u: ...unless v is equal to u.
- *
- * Atomically adds @a to @l, so long as it was not @u.
- * Returns non-zero if @l was not @u, and zero otherwise.
- */
-static __inline__ int local_add_unless(local_t *l, long a, long u)
-{
-	long t;
-
-	__asm__ __volatile__ (
-"1:"	PPC_LLARX(%0,0,%1,0) "			# local_add_unless\n\
-	cmpw	0,%0,%3 \n\
-	beq-	2f \n\
-	add	%0,%2,%0 \n"
-	PPC405_ERR77(0,%2)
-	PPC_STLCX	"%0,0,%1 \n\
-	bne-	1b \n"
-"	subf	%0,%2,%0 \n\
-2:"
-	: "=&r" (t)
-	: "r" (&(l->a.counter)), "r" (a), "r" (u)
-	: "cc", "memory");
-
-	return t != u;
-}
-
-#define local_inc_not_zero(l) local_add_unless((l), 1, 0)
-
-#define local_sub_and_test(a, l)	(local_sub_return((a), (l)) == 0)
-#define local_dec_and_test(l)		(local_dec_return((l)) == 0)
-
-/*
- * Atomically test *l and decrement if it is greater than 0.
- * The function returns the old value of *l minus 1.
- */
-static __inline__ long local_dec_if_positive(local_t *l)
-{
-	long t;
-
-	__asm__ __volatile__(
-"1:"	PPC_LLARX(%0,0,%1,0) "			# local_dec_if_positive\n\
-	cmpwi	%0,1\n\
-	addi	%0,%0,-1\n\
-	blt-	2f\n"
-	PPC405_ERR77(0,%1)
-	PPC_STLCX	"%0,0,%1\n\
-	bne-	1b"
-	"\n\
-2:"	: "=&b" (t)
-	: "r" (&(l->a.counter))
-	: "cc", "memory");
-
-	return t;
-}
-
-/* Use these for per-cpu local_t variables: on some archs they are
- * much more efficient than these naive implementations.  Note they take
- * a variable, not an address.
- */
-
-#define __local_inc(l)		((l)->a.counter++)
-#define __local_dec(l)		((l)->a.counter++)
-#define __local_add(i,l)	((l)->a.counter+=(i))
-#define __local_sub(i,l)	((l)->a.counter-=(i))
-
-#endif /* _ARCH_POWERPC_LOCAL_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/local64.h b/ANDROID_3.4.5/arch/powerpc/include/asm/local64.h
deleted file mode 100644
index 36c93b5c..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/local64.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/local64.h>
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/lppaca.h b/ANDROID_3.4.5/arch/powerpc/include/asm/lppaca.h
deleted file mode 100644
index a76254af..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/lppaca.h
+++ /dev/null
@@ -1,217 +0,0 @@
-/*
- * lppaca.h
- * Copyright (C) 2001  Mike Corrigan IBM Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-#ifndef _ASM_POWERPC_LPPACA_H
-#define _ASM_POWERPC_LPPACA_H
-#ifdef __KERNEL__
-
-/* These definitions relate to hypervisors that only exist when using
- * a server type processor
- */
-#ifdef CONFIG_PPC_BOOK3S
-
-//=============================================================================
-//
-//	This control block contains the data that is shared between the
-//	hypervisor (PLIC) and the OS.
-//
-//
-//----------------------------------------------------------------------------
-#include <linux/cache.h>
-#include <linux/threads.h>
-#include <asm/types.h>
-#include <asm/mmu.h>
-
-/*
- * We only have to have statically allocated lppaca structs on
- * legacy iSeries, which supports at most 64 cpus.
- */
-#define NR_LPPACAS	1
-
-
-/* The Hypervisor barfs if the lppaca crosses a page boundary.  A 1k
- * alignment is sufficient to prevent this */
-struct lppaca {
-//=============================================================================
-// CACHE_LINE_1 0x0000 - 0x007F Contains read-only data
-// NOTE: The xDynXyz fields are fields that will be dynamically changed by
-// PLIC when preparing to bring a processor online or when dispatching a
-// virtual processor!
-//=============================================================================
-	u32	desc;			// Eye catcher 0xD397D781	x00-x03
-	u16	size;			// Size of this struct		x04-x05
-	u16	reserved1;		// Reserved			x06-x07
-	u16	reserved2:14;		// Reserved			x08-x09
-	u8	shared_proc:1;		// Shared processor indicator	...
-	u8	secondary_thread:1;	// Secondary thread indicator	...
-	volatile u8 dyn_proc_status:8;	// Dynamic Status of this proc	x0A-x0A
-	u8	secondary_thread_count;	// Secondary thread count	x0B-x0B
-	volatile u16 dyn_hv_phys_proc_index;// Dynamic HV Physical Proc Index0C-x0D
-	volatile u16 dyn_hv_log_proc_index;// Dynamic HV Logical Proc Indexx0E-x0F
-	u32	decr_val;   		// Value for Decr programming 	x10-x13
-	u32	pmc_val;       		// Value for PMC regs         	x14-x17
-	volatile u32 dyn_hw_node_id;	// Dynamic Hardware Node id	x18-x1B
-	volatile u32 dyn_hw_proc_id;	// Dynamic Hardware Proc Id	x1C-x1F
-	volatile u32 dyn_pir;		// Dynamic ProcIdReg value	x20-x23
-	u32	dsei_data;           	// DSEI data                  	x24-x27
-	u64	sprg3;               	// SPRG3 value                	x28-x2F
-	u8	reserved3[40];		// Reserved			x30-x57
-	volatile u8 vphn_assoc_counts[8]; // Virtual processor home node
-					// associativity change counters x58-x5F
-	u8	reserved4[32];		// Reserved			x60-x7F
-
-//=============================================================================
-// CACHE_LINE_2 0x0080 - 0x00FF Contains local read-write data
-//=============================================================================
-	// This Dword contains a byte for each type of interrupt that can occur.
-	// The IPI is a count while the others are just a binary 1 or 0.
-	union {
-		u64	any_int;
-		struct {
-			u16	reserved;	// Reserved - cleared by #mpasmbl
-			u8	xirr_int;	// Indicates xXirrValue is valid or Immed IO
-			u8	ipi_cnt;	// IPI Count
-			u8	decr_int;	// DECR interrupt occurred
-			u8	pdc_int;	// PDC interrupt occurred
-			u8	quantum_int;	// Interrupt quantum reached
-			u8	old_plic_deferred_ext_int;	// Old PLIC has a deferred XIRR pending
-		} fields;
-	} int_dword;
-
-	// Whenever any fields in this Dword are set then PLIC will defer the
-	// processing of external interrupts.  Note that PLIC will store the
-	// XIRR directly into the xXirrValue field so that another XIRR will
-	// not be presented until this one clears.  The layout of the low
-	// 4-bytes of this Dword is up to SLIC - PLIC just checks whether the
-	// entire Dword is zero or not.  A non-zero value in the low order
-	// 2-bytes will result in SLIC being granted the highest thread
-	// priority upon return.  A 0 will return to SLIC as medium priority.
-	u64	plic_defer_ints_area;	// Entire Dword
-
-	// Used to pass the real SRR0/1 from PLIC to SLIC as well as to
-	// pass the target SRR0/1 from SLIC to PLIC on a SetAsrAndRfid.
-	u64	saved_srr0;		// Saved SRR0                   x10-x17
-	u64	saved_srr1;		// Saved SRR1                   x18-x1F
-
-	// Used to pass parms from the OS to PLIC for SetAsrAndRfid
-	u64	saved_gpr3;		// Saved GPR3                   x20-x27
-	u64	saved_gpr4;		// Saved GPR4                   x28-x2F
-	union {
-		u64	saved_gpr5;	/* Saved GPR5               x30-x37 */
-		struct {
-			u8	cede_latency_hint;  /*			x30 */
-			u8	reserved[7];        /*		    x31-x36 */
-		} fields;
-	} gpr5_dword;
-
-
-	u8	dtl_enable_mask;	// Dispatch Trace Log mask	x38-x38
-	u8	donate_dedicated_cpu;	// Donate dedicated CPU cycles  x39-x39
-	u8	fpregs_in_use;		// FP regs in use               x3A-x3A
-	u8	pmcregs_in_use;		// PMC regs in use              x3B-x3B
-	volatile u32 saved_decr;	// Saved Decr Value             x3C-x3F
-	volatile u64 emulated_time_base;// Emulated TB for this thread  x40-x47
-	volatile u64 cur_plic_latency;	// Unaccounted PLIC latency     x48-x4F
-	u64	tot_plic_latency;	// Accumulated PLIC latency     x50-x57
-	u64	wait_state_cycles;	// Wait cycles for this proc    x58-x5F
-	u64	end_of_quantum;		// TB at end of quantum         x60-x67
-	u64	pdc_saved_sprg1;	// Saved SPRG1 for PMC int      x68-x6F
-	u64	pdc_saved_srr0;		// Saved SRR0 for PMC int       x70-x77
-	volatile u32 virtual_decr;	// Virtual DECR for shared procsx78-x7B
-	u16	slb_count;		// # of SLBs to maintain        x7C-x7D
-	u8	idle;			// Indicate OS is idle          x7E
-	u8	vmxregs_in_use;		// VMX registers in use         x7F
-
-
-//=============================================================================
-// CACHE_LINE_3 0x0100 - 0x017F: This line is shared with other processors
-//=============================================================================
-	// This is the yield_count.  An "odd" value (low bit on) means that
-	// the processor is yielded (either because of an OS yield or a PLIC
-	// preempt).  An even value implies that the processor is currently
-	// executing.
-	// NOTE: This value will ALWAYS be zero for dedicated processors and
-	// will NEVER be zero for shared processors (ie, initialized to a 1).
-	volatile u32 yield_count;	// PLIC increments each dispatchx00-x03
-	volatile u32 dispersion_count;	// dispatch changed phys cpu    x04-x07
-	volatile u64 cmo_faults;	// CMO page fault count         x08-x0F
-	volatile u64 cmo_fault_time;	// CMO page fault time          x10-x17
-	u8	reserved7[104];		// Reserved                     x18-x7F
-
-//=============================================================================
-// CACHE_LINE_4-5 0x0180 - 0x027F Contains PMC interrupt data
-//=============================================================================
-	u32	page_ins;		// CMO Hint - # page ins by OS  x00-x03
-	u8	reserved8[148];		// Reserved                     x04-x97
-	volatile u64 dtl_idx;		// Dispatch Trace Log head idx	x98-x9F
-	u8	reserved9[96];		// Reserved                     xA0-xFF
-} __attribute__((__aligned__(0x400)));
-
-extern struct lppaca lppaca[];
-
-#define lppaca_of(cpu)	(*paca[cpu].lppaca_ptr)
-
-/*
- * SLB shadow buffer structure as defined in the PAPR.  The save_area
- * contains adjacent ESID and VSID pairs for each shadowed SLB.  The
- * ESID is stored in the lower 64bits, then the VSID.
- */
-struct slb_shadow {
-	u32	persistent;		// Number of persistent SLBs	x00-x03
-	u32	buffer_length;		// Total shadow buffer length	x04-x07
-	u64	reserved;		// Alignment			x08-x0f
-	struct	{
-		u64     esid;
-		u64	vsid;
-	} save_area[SLB_NUM_BOLTED];	//				x10-x40
-} ____cacheline_aligned;
-
-extern struct slb_shadow slb_shadow[];
-
-/*
- * Layout of entries in the hypervisor's dispatch trace log buffer.
- */
-struct dtl_entry {
-	u8	dispatch_reason;
-	u8	preempt_reason;
-	u16	processor_id;
-	u32	enqueue_to_dispatch_time;
-	u32	ready_to_enqueue_time;
-	u32	waiting_to_ready_time;
-	u64	timebase;
-	u64	fault_addr;
-	u64	srr0;
-	u64	srr1;
-};
-
-#define DISPATCH_LOG_BYTES	4096	/* bytes per cpu */
-#define N_DISPATCH_LOG		(DISPATCH_LOG_BYTES / sizeof(struct dtl_entry))
-
-extern struct kmem_cache *dtl_cache;
-
-/*
- * When CONFIG_VIRT_CPU_ACCOUNTING = y, the cpu accounting code controls
- * reading from the dispatch trace log.  If other code wants to consume
- * DTL entries, it can set this pointer to a function that will get
- * called once for each DTL entry that gets processed.
- */
-extern void (*dtl_consumer)(struct dtl_entry *entry, u64 index);
-
-#endif /* CONFIG_PPC_BOOK3S */
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_LPPACA_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/lv1call.h b/ANDROID_3.4.5/arch/powerpc/include/asm/lv1call.h
deleted file mode 100644
index 233f9eca..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/lv1call.h
+++ /dev/null
@@ -1,349 +0,0 @@
-/*
- *  PS3 hvcall interface.
- *
- *  Copyright (C) 2006 Sony Computer Entertainment Inc.
- *  Copyright 2006 Sony Corp.
- *  Copyright 2003, 2004 (c) MontaVista Software, Inc.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; version 2 of the License.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#if !defined(_ASM_POWERPC_LV1CALL_H)
-#define _ASM_POWERPC_LV1CALL_H
-
-#if !defined(__ASSEMBLY__)
-
-#include <linux/types.h>
-#include <linux/export.h>
-
-/* lv1 call declaration macros */
-
-#define LV1_1_IN_ARG_DECL u64 in_1
-#define LV1_2_IN_ARG_DECL LV1_1_IN_ARG_DECL, u64 in_2
-#define LV1_3_IN_ARG_DECL LV1_2_IN_ARG_DECL, u64 in_3
-#define LV1_4_IN_ARG_DECL LV1_3_IN_ARG_DECL, u64 in_4
-#define LV1_5_IN_ARG_DECL LV1_4_IN_ARG_DECL, u64 in_5
-#define LV1_6_IN_ARG_DECL LV1_5_IN_ARG_DECL, u64 in_6
-#define LV1_7_IN_ARG_DECL LV1_6_IN_ARG_DECL, u64 in_7
-#define LV1_8_IN_ARG_DECL LV1_7_IN_ARG_DECL, u64 in_8
-#define LV1_1_OUT_ARG_DECL u64 *out_1
-#define LV1_2_OUT_ARG_DECL LV1_1_OUT_ARG_DECL, u64 *out_2
-#define LV1_3_OUT_ARG_DECL LV1_2_OUT_ARG_DECL, u64 *out_3
-#define LV1_4_OUT_ARG_DECL LV1_3_OUT_ARG_DECL, u64 *out_4
-#define LV1_5_OUT_ARG_DECL LV1_4_OUT_ARG_DECL, u64 *out_5
-#define LV1_6_OUT_ARG_DECL LV1_5_OUT_ARG_DECL, u64 *out_6
-#define LV1_7_OUT_ARG_DECL LV1_6_OUT_ARG_DECL, u64 *out_7
-
-#define LV1_0_IN_0_OUT_ARG_DECL void
-#define LV1_1_IN_0_OUT_ARG_DECL LV1_1_IN_ARG_DECL
-#define LV1_2_IN_0_OUT_ARG_DECL LV1_2_IN_ARG_DECL
-#define LV1_3_IN_0_OUT_ARG_DECL LV1_3_IN_ARG_DECL
-#define LV1_4_IN_0_OUT_ARG_DECL LV1_4_IN_ARG_DECL
-#define LV1_5_IN_0_OUT_ARG_DECL LV1_5_IN_ARG_DECL
-#define LV1_6_IN_0_OUT_ARG_DECL LV1_6_IN_ARG_DECL
-#define LV1_7_IN_0_OUT_ARG_DECL LV1_7_IN_ARG_DECL
-
-#define LV1_0_IN_1_OUT_ARG_DECL                    LV1_1_OUT_ARG_DECL
-#define LV1_1_IN_1_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
-#define LV1_2_IN_1_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
-#define LV1_3_IN_1_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
-#define LV1_4_IN_1_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
-#define LV1_5_IN_1_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
-#define LV1_6_IN_1_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
-#define LV1_7_IN_1_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
-#define LV1_8_IN_1_OUT_ARG_DECL LV1_8_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
-
-#define LV1_0_IN_2_OUT_ARG_DECL                    LV1_2_OUT_ARG_DECL
-#define LV1_1_IN_2_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
-#define LV1_2_IN_2_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
-#define LV1_3_IN_2_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
-#define LV1_4_IN_2_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
-#define LV1_5_IN_2_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
-#define LV1_6_IN_2_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
-#define LV1_7_IN_2_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
-
-#define LV1_0_IN_3_OUT_ARG_DECL                    LV1_3_OUT_ARG_DECL
-#define LV1_1_IN_3_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
-#define LV1_2_IN_3_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
-#define LV1_3_IN_3_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
-#define LV1_4_IN_3_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
-#define LV1_5_IN_3_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
-#define LV1_6_IN_3_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
-#define LV1_7_IN_3_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
-
-#define LV1_0_IN_4_OUT_ARG_DECL                    LV1_4_OUT_ARG_DECL
-#define LV1_1_IN_4_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
-#define LV1_2_IN_4_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
-#define LV1_3_IN_4_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
-#define LV1_4_IN_4_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
-#define LV1_5_IN_4_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
-#define LV1_6_IN_4_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
-#define LV1_7_IN_4_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
-
-#define LV1_0_IN_5_OUT_ARG_DECL                    LV1_5_OUT_ARG_DECL
-#define LV1_1_IN_5_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
-#define LV1_2_IN_5_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
-#define LV1_3_IN_5_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
-#define LV1_4_IN_5_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
-#define LV1_5_IN_5_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
-#define LV1_6_IN_5_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
-#define LV1_7_IN_5_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
-
-#define LV1_0_IN_6_OUT_ARG_DECL                    LV1_6_OUT_ARG_DECL
-#define LV1_1_IN_6_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
-#define LV1_2_IN_6_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
-#define LV1_3_IN_6_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
-#define LV1_4_IN_6_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
-#define LV1_5_IN_6_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
-#define LV1_6_IN_6_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
-#define LV1_7_IN_6_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
-
-#define LV1_0_IN_7_OUT_ARG_DECL                    LV1_7_OUT_ARG_DECL
-#define LV1_1_IN_7_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
-#define LV1_2_IN_7_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
-#define LV1_3_IN_7_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
-#define LV1_4_IN_7_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
-#define LV1_5_IN_7_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
-#define LV1_6_IN_7_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
-#define LV1_7_IN_7_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
-
-#define LV1_1_IN_ARGS in_1
-#define LV1_2_IN_ARGS LV1_1_IN_ARGS, in_2
-#define LV1_3_IN_ARGS LV1_2_IN_ARGS, in_3
-#define LV1_4_IN_ARGS LV1_3_IN_ARGS, in_4
-#define LV1_5_IN_ARGS LV1_4_IN_ARGS, in_5
-#define LV1_6_IN_ARGS LV1_5_IN_ARGS, in_6
-#define LV1_7_IN_ARGS LV1_6_IN_ARGS, in_7
-#define LV1_8_IN_ARGS LV1_7_IN_ARGS, in_8
-
-#define LV1_1_OUT_ARGS out_1
-#define LV1_2_OUT_ARGS LV1_1_OUT_ARGS, out_2
-#define LV1_3_OUT_ARGS LV1_2_OUT_ARGS, out_3
-#define LV1_4_OUT_ARGS LV1_3_OUT_ARGS, out_4
-#define LV1_5_OUT_ARGS LV1_4_OUT_ARGS, out_5
-#define LV1_6_OUT_ARGS LV1_5_OUT_ARGS, out_6
-#define LV1_7_OUT_ARGS LV1_6_OUT_ARGS, out_7
-
-#define LV1_0_IN_0_OUT_ARGS
-#define LV1_1_IN_0_OUT_ARGS LV1_1_IN_ARGS
-#define LV1_2_IN_0_OUT_ARGS LV1_2_IN_ARGS
-#define LV1_3_IN_0_OUT_ARGS LV1_3_IN_ARGS
-#define LV1_4_IN_0_OUT_ARGS LV1_4_IN_ARGS
-#define LV1_5_IN_0_OUT_ARGS LV1_5_IN_ARGS
-#define LV1_6_IN_0_OUT_ARGS LV1_6_IN_ARGS
-#define LV1_7_IN_0_OUT_ARGS LV1_7_IN_ARGS
-
-#define LV1_0_IN_1_OUT_ARGS                LV1_1_OUT_ARGS
-#define LV1_1_IN_1_OUT_ARGS LV1_1_IN_ARGS, LV1_1_OUT_ARGS
-#define LV1_2_IN_1_OUT_ARGS LV1_2_IN_ARGS, LV1_1_OUT_ARGS
-#define LV1_3_IN_1_OUT_ARGS LV1_3_IN_ARGS, LV1_1_OUT_ARGS
-#define LV1_4_IN_1_OUT_ARGS LV1_4_IN_ARGS, LV1_1_OUT_ARGS
-#define LV1_5_IN_1_OUT_ARGS LV1_5_IN_ARGS, LV1_1_OUT_ARGS
-#define LV1_6_IN_1_OUT_ARGS LV1_6_IN_ARGS, LV1_1_OUT_ARGS
-#define LV1_7_IN_1_OUT_ARGS LV1_7_IN_ARGS, LV1_1_OUT_ARGS
-#define LV1_8_IN_1_OUT_ARGS LV1_8_IN_ARGS, LV1_1_OUT_ARGS
-
-#define LV1_0_IN_2_OUT_ARGS                LV1_2_OUT_ARGS
-#define LV1_1_IN_2_OUT_ARGS LV1_1_IN_ARGS, LV1_2_OUT_ARGS
-#define LV1_2_IN_2_OUT_ARGS LV1_2_IN_ARGS, LV1_2_OUT_ARGS
-#define LV1_3_IN_2_OUT_ARGS LV1_3_IN_ARGS, LV1_2_OUT_ARGS
-#define LV1_4_IN_2_OUT_ARGS LV1_4_IN_ARGS, LV1_2_OUT_ARGS
-#define LV1_5_IN_2_OUT_ARGS LV1_5_IN_ARGS, LV1_2_OUT_ARGS
-#define LV1_6_IN_2_OUT_ARGS LV1_6_IN_ARGS, LV1_2_OUT_ARGS
-#define LV1_7_IN_2_OUT_ARGS LV1_7_IN_ARGS, LV1_2_OUT_ARGS
-
-#define LV1_0_IN_3_OUT_ARGS                LV1_3_OUT_ARGS
-#define LV1_1_IN_3_OUT_ARGS LV1_1_IN_ARGS, LV1_3_OUT_ARGS
-#define LV1_2_IN_3_OUT_ARGS LV1_2_IN_ARGS, LV1_3_OUT_ARGS
-#define LV1_3_IN_3_OUT_ARGS LV1_3_IN_ARGS, LV1_3_OUT_ARGS
-#define LV1_4_IN_3_OUT_ARGS LV1_4_IN_ARGS, LV1_3_OUT_ARGS
-#define LV1_5_IN_3_OUT_ARGS LV1_5_IN_ARGS, LV1_3_OUT_ARGS
-#define LV1_6_IN_3_OUT_ARGS LV1_6_IN_ARGS, LV1_3_OUT_ARGS
-#define LV1_7_IN_3_OUT_ARGS LV1_7_IN_ARGS, LV1_3_OUT_ARGS
-
-#define LV1_0_IN_4_OUT_ARGS                LV1_4_OUT_ARGS
-#define LV1_1_IN_4_OUT_ARGS LV1_1_IN_ARGS, LV1_4_OUT_ARGS
-#define LV1_2_IN_4_OUT_ARGS LV1_2_IN_ARGS, LV1_4_OUT_ARGS
-#define LV1_3_IN_4_OUT_ARGS LV1_3_IN_ARGS, LV1_4_OUT_ARGS
-#define LV1_4_IN_4_OUT_ARGS LV1_4_IN_ARGS, LV1_4_OUT_ARGS
-#define LV1_5_IN_4_OUT_ARGS LV1_5_IN_ARGS, LV1_4_OUT_ARGS
-#define LV1_6_IN_4_OUT_ARGS LV1_6_IN_ARGS, LV1_4_OUT_ARGS
-#define LV1_7_IN_4_OUT_ARGS LV1_7_IN_ARGS, LV1_4_OUT_ARGS
-
-#define LV1_0_IN_5_OUT_ARGS                LV1_5_OUT_ARGS
-#define LV1_1_IN_5_OUT_ARGS LV1_1_IN_ARGS, LV1_5_OUT_ARGS
-#define LV1_2_IN_5_OUT_ARGS LV1_2_IN_ARGS, LV1_5_OUT_ARGS
-#define LV1_3_IN_5_OUT_ARGS LV1_3_IN_ARGS, LV1_5_OUT_ARGS
-#define LV1_4_IN_5_OUT_ARGS LV1_4_IN_ARGS, LV1_5_OUT_ARGS
-#define LV1_5_IN_5_OUT_ARGS LV1_5_IN_ARGS, LV1_5_OUT_ARGS
-#define LV1_6_IN_5_OUT_ARGS LV1_6_IN_ARGS, LV1_5_OUT_ARGS
-#define LV1_7_IN_5_OUT_ARGS LV1_7_IN_ARGS, LV1_5_OUT_ARGS
-
-#define LV1_0_IN_6_OUT_ARGS                LV1_6_OUT_ARGS
-#define LV1_1_IN_6_OUT_ARGS LV1_1_IN_ARGS, LV1_6_OUT_ARGS
-#define LV1_2_IN_6_OUT_ARGS LV1_2_IN_ARGS, LV1_6_OUT_ARGS
-#define LV1_3_IN_6_OUT_ARGS LV1_3_IN_ARGS, LV1_6_OUT_ARGS
-#define LV1_4_IN_6_OUT_ARGS LV1_4_IN_ARGS, LV1_6_OUT_ARGS
-#define LV1_5_IN_6_OUT_ARGS LV1_5_IN_ARGS, LV1_6_OUT_ARGS
-#define LV1_6_IN_6_OUT_ARGS LV1_6_IN_ARGS, LV1_6_OUT_ARGS
-#define LV1_7_IN_6_OUT_ARGS LV1_7_IN_ARGS, LV1_6_OUT_ARGS
-
-#define LV1_0_IN_7_OUT_ARGS                LV1_7_OUT_ARGS
-#define LV1_1_IN_7_OUT_ARGS LV1_1_IN_ARGS, LV1_7_OUT_ARGS
-#define LV1_2_IN_7_OUT_ARGS LV1_2_IN_ARGS, LV1_7_OUT_ARGS
-#define LV1_3_IN_7_OUT_ARGS LV1_3_IN_ARGS, LV1_7_OUT_ARGS
-#define LV1_4_IN_7_OUT_ARGS LV1_4_IN_ARGS, LV1_7_OUT_ARGS
-#define LV1_5_IN_7_OUT_ARGS LV1_5_IN_ARGS, LV1_7_OUT_ARGS
-#define LV1_6_IN_7_OUT_ARGS LV1_6_IN_ARGS, LV1_7_OUT_ARGS
-#define LV1_7_IN_7_OUT_ARGS LV1_7_IN_ARGS, LV1_7_OUT_ARGS
-
-/*
- * This LV1_CALL() macro is for use by callers.  It expands into an
- * inline call wrapper and an underscored HV call declaration.  The
- * wrapper can be used to instrument the lv1 call interface.  The
- * file lv1call.S defines its own LV1_CALL() macro to expand into
- * the actual underscored call definition.
- */
-
-#if !defined(LV1_CALL)
-#define LV1_CALL(name, in, out, num)                               \
-  extern s64 _lv1_##name(LV1_##in##_IN_##out##_OUT_ARG_DECL);      \
-  static inline int lv1_##name(LV1_##in##_IN_##out##_OUT_ARG_DECL) \
-    {return _lv1_##name(LV1_##in##_IN_##out##_OUT_ARGS);}
-#endif
-
-#endif /* !defined(__ASSEMBLY__) */
-
-/* lv1 call table */
-
-LV1_CALL(allocate_memory,                               4, 2,   0 )
-LV1_CALL(write_htab_entry,                              4, 0,   1 )
-LV1_CALL(construct_virtual_address_space,               3, 2,   2 )
-LV1_CALL(invalidate_htab_entries,                       5, 0,   3 )
-LV1_CALL(get_virtual_address_space_id_of_ppe,           0, 1,   4 )
-LV1_CALL(query_logical_partition_address_region_info,   1, 5,   6 )
-LV1_CALL(select_virtual_address_space,                  1, 0,   7 )
-LV1_CALL(pause,                                         1, 0,   9 )
-LV1_CALL(destruct_virtual_address_space,                1, 0,  10 )
-LV1_CALL(configure_irq_state_bitmap,                    3, 0,  11 )
-LV1_CALL(connect_irq_plug_ext,                          5, 0,  12 )
-LV1_CALL(release_memory,                                1, 0,  13 )
-LV1_CALL(put_iopte,                                     5, 0,  15 )
-LV1_CALL(disconnect_irq_plug_ext,                       3, 0,  17 )
-LV1_CALL(construct_event_receive_port,                  0, 1,  18 )
-LV1_CALL(destruct_event_receive_port,                   1, 0,  19 )
-LV1_CALL(send_event_locally,                            1, 0,  24 )
-LV1_CALL(end_of_interrupt,                              1, 0,  27 )
-LV1_CALL(connect_irq_plug,                              2, 0,  28 )
-LV1_CALL(disconnect_irq_plug,                           1, 0,  29 )
-LV1_CALL(end_of_interrupt_ext,                          3, 0,  30 )
-LV1_CALL(did_update_interrupt_mask,                     2, 0,  31 )
-LV1_CALL(shutdown_logical_partition,                    1, 0,  44 )
-LV1_CALL(destruct_logical_spe,                          1, 0,  54 )
-LV1_CALL(construct_logical_spe,                         7, 6,  57 )
-LV1_CALL(set_spe_interrupt_mask,                        3, 0,  61 )
-LV1_CALL(set_spe_transition_notifier,                   3, 0,  64 )
-LV1_CALL(disable_logical_spe,                           2, 0,  65 )
-LV1_CALL(clear_spe_interrupt_status,                    4, 0,  66 )
-LV1_CALL(get_spe_interrupt_status,                      2, 1,  67 )
-LV1_CALL(get_logical_ppe_id,                            0, 1,  69 )
-LV1_CALL(set_interrupt_mask,                            5, 0,  73 )
-LV1_CALL(get_logical_partition_id,                      0, 1,  74 )
-LV1_CALL(configure_execution_time_variable,             1, 0,  77 )
-LV1_CALL(get_spe_irq_outlet,                            2, 1,  78 )
-LV1_CALL(set_spe_privilege_state_area_1_register,       3, 0,  79 )
-LV1_CALL(create_repository_node,                        6, 0,  90 )
-LV1_CALL(read_repository_node,                          5, 2,  91 )
-LV1_CALL(modify_repository_node_value,                  6, 0,  92 )
-LV1_CALL(remove_repository_node,                        4, 0,  93 )
-LV1_CALL(read_htab_entries,                             2, 5,  95 )
-LV1_CALL(set_dabr,                                      2, 0,  96 )
-LV1_CALL(get_total_execution_time,                      2, 1, 103 )
-LV1_CALL(allocate_io_segment,                           3, 1, 116 )
-LV1_CALL(release_io_segment,                            2, 0, 117 )
-LV1_CALL(construct_io_irq_outlet,                       1, 1, 120 )
-LV1_CALL(destruct_io_irq_outlet,                        1, 0, 121 )
-LV1_CALL(map_htab,                                      1, 1, 122 )
-LV1_CALL(unmap_htab,                                    1, 0, 123 )
-LV1_CALL(get_version_info,                              0, 2, 127 )
-LV1_CALL(insert_htab_entry,                             6, 3, 158 )
-LV1_CALL(read_virtual_uart,                             3, 1, 162 )
-LV1_CALL(write_virtual_uart,                            3, 1, 163 )
-LV1_CALL(set_virtual_uart_param,                        3, 0, 164 )
-LV1_CALL(get_virtual_uart_param,                        2, 1, 165 )
-LV1_CALL(configure_virtual_uart_irq,                    1, 1, 166 )
-LV1_CALL(open_device,                                   3, 0, 170 )
-LV1_CALL(close_device,                                  2, 0, 171 )
-LV1_CALL(map_device_mmio_region,                        5, 1, 172 )
-LV1_CALL(unmap_device_mmio_region,                      3, 0, 173 )
-LV1_CALL(allocate_device_dma_region,                    5, 1, 174 )
-LV1_CALL(free_device_dma_region,                        3, 0, 175 )
-LV1_CALL(map_device_dma_region,                         6, 0, 176 )
-LV1_CALL(unmap_device_dma_region,                       4, 0, 177 )
-LV1_CALL(net_add_multicast_address,                     4, 0, 185 )
-LV1_CALL(net_remove_multicast_address,                  4, 0, 186 )
-LV1_CALL(net_start_tx_dma,                              4, 0, 187 )
-LV1_CALL(net_stop_tx_dma,                               2, 0, 188 )
-LV1_CALL(net_start_rx_dma,                              4, 0, 189 )
-LV1_CALL(net_stop_rx_dma,                               2, 0, 190 )
-LV1_CALL(net_set_interrupt_status_indicator,            4, 0, 191 )
-LV1_CALL(net_set_interrupt_mask,                        4, 0, 193 )
-LV1_CALL(net_control,                                   6, 2, 194 )
-LV1_CALL(connect_interrupt_event_receive_port,          4, 0, 197 )
-LV1_CALL(disconnect_interrupt_event_receive_port,       4, 0, 198 )
-LV1_CALL(get_spe_all_interrupt_statuses,                1, 1, 199 )
-LV1_CALL(deconfigure_virtual_uart_irq,                  0, 0, 202 )
-LV1_CALL(enable_logical_spe,                            2, 0, 207 )
-LV1_CALL(gpu_open,                                      1, 0, 210 )
-LV1_CALL(gpu_close,                                     0, 0, 211 )
-LV1_CALL(gpu_device_map,                                1, 2, 212 )
-LV1_CALL(gpu_device_unmap,                              1, 0, 213 )
-LV1_CALL(gpu_memory_allocate,                           5, 2, 214 )
-LV1_CALL(gpu_memory_free,                               1, 0, 216 )
-LV1_CALL(gpu_context_allocate,                          2, 5, 217 )
-LV1_CALL(gpu_context_free,                              1, 0, 218 )
-LV1_CALL(gpu_context_iomap,                             5, 0, 221 )
-LV1_CALL(gpu_context_attribute,                         6, 0, 225 )
-LV1_CALL(gpu_context_intr,                              1, 1, 227 )
-LV1_CALL(gpu_attribute,                                 3, 0, 228 )
-LV1_CALL(get_rtc,                                       0, 2, 232 )
-LV1_CALL(set_ppe_periodic_tracer_frequency,             1, 0, 240 )
-LV1_CALL(start_ppe_periodic_tracer,                     5, 0, 241 )
-LV1_CALL(stop_ppe_periodic_tracer,                      1, 1, 242 )
-LV1_CALL(storage_read,                                  6, 1, 245 )
-LV1_CALL(storage_write,                                 6, 1, 246 )
-LV1_CALL(storage_send_device_command,                   6, 1, 248 )
-LV1_CALL(storage_get_async_status,                      1, 2, 249 )
-LV1_CALL(storage_check_async_status,                    2, 1, 254 )
-LV1_CALL(panic,                                         1, 0, 255 )
-LV1_CALL(construct_lpm,                                 6, 3, 140 )
-LV1_CALL(destruct_lpm,                                  1, 0, 141 )
-LV1_CALL(start_lpm,                                     1, 0, 142 )
-LV1_CALL(stop_lpm,                                      1, 1, 143 )
-LV1_CALL(copy_lpm_trace_buffer,                         3, 1, 144 )
-LV1_CALL(add_lpm_event_bookmark,                        5, 0, 145 )
-LV1_CALL(delete_lpm_event_bookmark,                     3, 0, 146 )
-LV1_CALL(set_lpm_interrupt_mask,                        3, 1, 147 )
-LV1_CALL(get_lpm_interrupt_status,                      1, 1, 148 )
-LV1_CALL(set_lpm_general_control,                       5, 2, 149 )
-LV1_CALL(set_lpm_interval,                              3, 1, 150 )
-LV1_CALL(set_lpm_trigger_control,                       3, 1, 151 )
-LV1_CALL(set_lpm_counter_control,                       4, 1, 152 )
-LV1_CALL(set_lpm_group_control,                         3, 1, 153 )
-LV1_CALL(set_lpm_debug_bus_control,                     3, 1, 154 )
-LV1_CALL(set_lpm_counter,                               5, 2, 155 )
-LV1_CALL(set_lpm_signal,                                7, 0, 156 )
-LV1_CALL(set_lpm_spr_trigger,                           2, 0, 157 )
-
-#endif
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/machdep.h b/ANDROID_3.4.5/arch/powerpc/include/asm/machdep.h
deleted file mode 100644
index 42ce5708..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/machdep.h
+++ /dev/null
@@ -1,343 +0,0 @@
-#ifndef _ASM_POWERPC_MACHDEP_H
-#define _ASM_POWERPC_MACHDEP_H
-#ifdef __KERNEL__
-
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/seq_file.h>
-#include <linux/init.h>
-#include <linux/dma-mapping.h>
-#include <linux/export.h>
-
-#include <asm/setup.h>
-
-/* We export this macro for external modules like Alsa to know if
- * ppc_md.feature_call is implemented or not
- */
-#define CONFIG_PPC_HAS_FEATURE_CALLS
-
-struct pt_regs;
-struct pci_bus;	
-struct device_node;
-struct iommu_table;
-struct rtc_time;
-struct file;
-struct pci_controller;
-struct kimage;
-
-struct machdep_calls {
-	char		*name;
-#ifdef CONFIG_PPC64
-	void            (*hpte_invalidate)(unsigned long slot,
-					   unsigned long va,
-					   int psize, int ssize,
-					   int local);
-	long		(*hpte_updatepp)(unsigned long slot, 
-					 unsigned long newpp, 
-					 unsigned long va,
-					 int psize, int ssize,
-					 int local);
-	void            (*hpte_updateboltedpp)(unsigned long newpp, 
-					       unsigned long ea,
-					       int psize, int ssize);
-	long		(*hpte_insert)(unsigned long hpte_group,
-				       unsigned long va,
-				       unsigned long prpn,
-				       unsigned long rflags,
-				       unsigned long vflags,
-				       int psize, int ssize);
-	long		(*hpte_remove)(unsigned long hpte_group);
-	void            (*hpte_removebolted)(unsigned long ea,
-					     int psize, int ssize);
-	void		(*flush_hash_range)(unsigned long number, int local);
-
-	/* special for kexec, to be called in real mode, linear mapping is
-	 * destroyed as well */
-	void		(*hpte_clear_all)(void);
-
-	int		(*tce_build)(struct iommu_table *tbl,
-				     long index,
-				     long npages,
-				     unsigned long uaddr,
-				     enum dma_data_direction direction,
-				     struct dma_attrs *attrs);
-	void		(*tce_free)(struct iommu_table *tbl,
-				    long index,
-				    long npages);
-	unsigned long	(*tce_get)(struct iommu_table *tbl,
-				    long index);
-	void		(*tce_flush)(struct iommu_table *tbl);
-
-	void __iomem *	(*ioremap)(phys_addr_t addr, unsigned long size,
-				   unsigned long flags, void *caller);
-	void		(*iounmap)(volatile void __iomem *token);
-
-#ifdef CONFIG_PM
-	void		(*iommu_save)(void);
-	void		(*iommu_restore)(void);
-#endif
-#endif /* CONFIG_PPC64 */
-
-	void		(*pci_dma_dev_setup)(struct pci_dev *dev);
-	void		(*pci_dma_bus_setup)(struct pci_bus *bus);
-
-	/* Platform set_dma_mask and dma_get_required_mask overrides */
-	int		(*dma_set_mask)(struct device *dev, u64 dma_mask);
-	u64		(*dma_get_required_mask)(struct device *dev);
-
-	int		(*probe)(void);
-	void		(*setup_arch)(void); /* Optional, may be NULL */
-	void		(*init_early)(void);
-	/* Optional, may be NULL. */
-	void		(*show_cpuinfo)(struct seq_file *m);
-	void		(*show_percpuinfo)(struct seq_file *m, int i);
-
-	void		(*init_IRQ)(void);
-
-	/* Return an irq, or NO_IRQ to indicate there are none pending. */
-	unsigned int	(*get_irq)(void);
-
-	/* PCI stuff */
-	/* Called after scanning the bus, before allocating resources */
-	void		(*pcibios_fixup)(void);
-	int		(*pci_probe_mode)(struct pci_bus *);
-	void		(*pci_irq_fixup)(struct pci_dev *dev);
-
-	/* To setup PHBs when using automatic OF platform driver for PCI */
-	int		(*pci_setup_phb)(struct pci_controller *host);
-
-#ifdef CONFIG_PCI_MSI
-	int		(*msi_check_device)(struct pci_dev* dev,
-					    int nvec, int type);
-	int		(*setup_msi_irqs)(struct pci_dev *dev,
-					  int nvec, int type);
-	void		(*teardown_msi_irqs)(struct pci_dev *dev);
-#endif
-
-	void		(*restart)(char *cmd);
-	void		(*power_off)(void);
-	void		(*halt)(void);
-	void		(*panic)(char *str);
-	void		(*cpu_die)(void);
-
-	long		(*time_init)(void); /* Optional, may be NULL */
-
-	int		(*set_rtc_time)(struct rtc_time *);
-	void		(*get_rtc_time)(struct rtc_time *);
-	unsigned long	(*get_boot_time)(void);
-	unsigned char 	(*rtc_read_val)(int addr);
-	void		(*rtc_write_val)(int addr, unsigned char val);
-
-	void		(*calibrate_decr)(void);
-
-	void		(*progress)(char *, unsigned short);
-
-	/* Interface for platform error logging */
-	void 		(*log_error)(char *buf, unsigned int err_type, int fatal);
-
-	unsigned char 	(*nvram_read_val)(int addr);
-	void		(*nvram_write_val)(int addr, unsigned char val);
-	ssize_t		(*nvram_write)(char *buf, size_t count, loff_t *index);
-	ssize_t		(*nvram_read)(char *buf, size_t count, loff_t *index);	
-	ssize_t		(*nvram_size)(void);		
-	void		(*nvram_sync)(void);
-
-	/* Exception handlers */
-	int		(*system_reset_exception)(struct pt_regs *regs);
-	int 		(*machine_check_exception)(struct pt_regs *regs);
-
-	/* Motherboard/chipset features. This is a kind of general purpose
-	 * hook used to control some machine specific features (like reset
-	 * lines, chip power control, etc...).
-	 */
-	long	 	(*feature_call)(unsigned int feature, ...);
-
-	/* Get legacy PCI/IDE interrupt mapping */ 
-	int		(*pci_get_legacy_ide_irq)(struct pci_dev *dev, int channel);
-	
-	/* Get access protection for /dev/mem */
-	pgprot_t	(*phys_mem_access_prot)(struct file *file,
-						unsigned long pfn,
-						unsigned long size,
-						pgprot_t vma_prot);
-
-	/* Idle loop for this platform, leave empty for default idle loop */
-	void		(*idle_loop)(void);
-
-	/*
-	 * Function for waiting for work with reduced power in idle loop;
-	 * called with interrupts disabled.
-	 */
-	void		(*power_save)(void);
-
-	/* Function to enable performance monitor counters for this
-	   platform, called once per cpu. */
-	void		(*enable_pmcs)(void);
-
-	/* Set DABR for this platform, leave empty for default implemenation */
-	int		(*set_dabr)(unsigned long dabr);
-
-#ifdef CONFIG_PPC32	/* XXX for now */
-	/* A general init function, called by ppc_init in init/main.c.
-	   May be NULL. */
-	void		(*init)(void);
-
-	void		(*kgdb_map_scc)(void);
-
-	/*
-	 * optional PCI "hooks"
-	 */
-	/* Called at then very end of pcibios_init() */
-	void (*pcibios_after_init)(void);
-
-#endif /* CONFIG_PPC32 */
-
-	/* Called in indirect_* to avoid touching devices */
-	int (*pci_exclude_device)(struct pci_controller *, unsigned char, unsigned char);
-
-	/* Called after PPC generic resource fixup to perform
-	   machine specific fixups */
-	void (*pcibios_fixup_resources)(struct pci_dev *);
-
-	/* Called for each PCI bus in the system when it's probed */
-	void (*pcibios_fixup_bus)(struct pci_bus *);
-
-	/* Called when pci_enable_device() is called. Returns 0 to
-	 * allow assignment/enabling of the device. */
-	int  (*pcibios_enable_device_hook)(struct pci_dev *);
-
-	/* Called after scan and before resource survey */
-	void (*pcibios_fixup_phb)(struct pci_controller *hose);
-
-	/* Called to shutdown machine specific hardware not already controlled
-	 * by other drivers.
-	 */
-	void (*machine_shutdown)(void);
-
-#ifdef CONFIG_KEXEC
-	void (*kexec_cpu_down)(int crash_shutdown, int secondary);
-
-	/* Called to do what every setup is needed on image and the
-	 * reboot code buffer. Returns 0 on success.
-	 * Provide your own (maybe dummy) implementation if your platform
-	 * claims to support kexec.
-	 */
-	int (*machine_kexec_prepare)(struct kimage *image);
-
-	/* Called to perform the _real_ kexec.
-	 * Do NOT allocate memory or fail here. We are past the point of
-	 * no return.
-	 */
-	void (*machine_kexec)(struct kimage *image);
-#endif /* CONFIG_KEXEC */
-
-#ifdef CONFIG_SUSPEND
-	/* These are called to disable and enable, respectively, IRQs when
-	 * entering a suspend state.  If NULL, then the generic versions
-	 * will be called.  The generic versions disable/enable the
-	 * decrementer along with interrupts.
-	 */
-	void (*suspend_disable_irqs)(void);
-	void (*suspend_enable_irqs)(void);
-#endif
-	int (*suspend_disable_cpu)(void);
-
-#ifdef CONFIG_ARCH_CPU_PROBE_RELEASE
-	ssize_t (*cpu_probe)(const char *, size_t);
-	ssize_t (*cpu_release)(const char *, size_t);
-#endif
-};
-
-extern void e500_idle(void);
-extern void power4_idle(void);
-extern void power7_idle(void);
-extern void ppc6xx_idle(void);
-extern void book3e_idle(void);
-
-/*
- * ppc_md contains a copy of the machine description structure for the
- * current platform. machine_id contains the initial address where the
- * description was found during boot.
- */
-extern struct machdep_calls ppc_md;
-extern struct machdep_calls *machine_id;
-
-#define __machine_desc __attribute__ ((__section__ (".machine.desc")))
-
-#define define_machine(name)					\
-	extern struct machdep_calls mach_##name;		\
-	EXPORT_SYMBOL(mach_##name);				\
-	struct machdep_calls mach_##name __machine_desc =
-
-#define machine_is(name) \
-	({ \
-		extern struct machdep_calls mach_##name \
-			__attribute__((weak));		 \
-		machine_id == &mach_##name; \
-	})
-
-extern void probe_machine(void);
-
-extern char cmd_line[COMMAND_LINE_SIZE];
-
-#ifdef CONFIG_PPC_PMAC
-/*
- * Power macintoshes have either a CUDA, PMU or SMU controlling
- * system reset, power, NVRAM, RTC.
- */
-typedef enum sys_ctrler_kind {
-	SYS_CTRLER_UNKNOWN = 0,
-	SYS_CTRLER_CUDA = 1,
-	SYS_CTRLER_PMU = 2,
-	SYS_CTRLER_SMU = 3,
-} sys_ctrler_t;
-extern sys_ctrler_t sys_ctrler;
-
-#endif /* CONFIG_PPC_PMAC */
-
-
-/* Functions to produce codes on the leds.
- * The SRC code should be unique for the message category and should
- * be limited to the lower 24 bits (the upper 8 are set by these funcs),
- * and (for boot & dump) should be sorted numerically in the order
- * the events occur.
- */
-/* Print a boot progress message. */
-void ppc64_boot_msg(unsigned int src, const char *msg);
-
-static inline void log_error(char *buf, unsigned int err_type, int fatal)
-{
-	if (ppc_md.log_error)
-		ppc_md.log_error(buf, err_type, fatal);
-}
-
-#define __define_machine_initcall(mach,level,fn,id) \
-	static int __init __machine_initcall_##mach##_##fn(void) { \
-		if (machine_is(mach)) return fn(); \
-		return 0; \
-	} \
-	__define_initcall(level,__machine_initcall_##mach##_##fn,id);
-
-#define machine_core_initcall(mach,fn)		__define_machine_initcall(mach,"1",fn,1)
-#define machine_core_initcall_sync(mach,fn)	__define_machine_initcall(mach,"1s",fn,1s)
-#define machine_postcore_initcall(mach,fn)	__define_machine_initcall(mach,"2",fn,2)
-#define machine_postcore_initcall_sync(mach,fn)	__define_machine_initcall(mach,"2s",fn,2s)
-#define machine_arch_initcall(mach,fn)		__define_machine_initcall(mach,"3",fn,3)
-#define machine_arch_initcall_sync(mach,fn)	__define_machine_initcall(mach,"3s",fn,3s)
-#define machine_subsys_initcall(mach,fn)	__define_machine_initcall(mach,"4",fn,4)
-#define machine_subsys_initcall_sync(mach,fn)	__define_machine_initcall(mach,"4s",fn,4s)
-#define machine_fs_initcall(mach,fn)		__define_machine_initcall(mach,"5",fn,5)
-#define machine_fs_initcall_sync(mach,fn)	__define_machine_initcall(mach,"5s",fn,5s)
-#define machine_rootfs_initcall(mach,fn)	__define_machine_initcall(mach,"rootfs",fn,rootfs)
-#define machine_device_initcall(mach,fn)	__define_machine_initcall(mach,"6",fn,6)
-#define machine_device_initcall_sync(mach,fn)	__define_machine_initcall(mach,"6s",fn,6s)
-#define machine_late_initcall(mach,fn)		__define_machine_initcall(mach,"7",fn,7)
-#define machine_late_initcall_sync(mach,fn)	__define_machine_initcall(mach,"7s",fn,7s)
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_MACHDEP_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/macio.h b/ANDROID_3.4.5/arch/powerpc/include/asm/macio.h
deleted file mode 100644
index 27af7f8b..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/macio.h
+++ /dev/null
@@ -1,144 +0,0 @@
-#ifndef __MACIO_ASIC_H__
-#define __MACIO_ASIC_H__
-#ifdef __KERNEL__
-
-#include <linux/of_device.h>
-
-extern struct bus_type macio_bus_type;
-
-/* MacIO device driver is defined later */
-struct macio_driver;
-struct macio_chip;
-
-#define MACIO_DEV_COUNT_RESOURCES	8
-#define MACIO_DEV_COUNT_IRQS		8
-
-/*
- * the macio_bus structure is used to describe a "virtual" bus
- * within a MacIO ASIC. It's typically provided by a macio_pci_asic
- * PCI device, but could be provided differently as well (nubus
- * machines using a fake OF tree).
- *
- * The pdev field can be NULL on non-PCI machines
- */
-struct macio_bus
-{
-	struct macio_chip	*chip;		/* macio_chip (private use) */
-	int			index;		/* macio chip index in system */
-#ifdef CONFIG_PCI
-	struct pci_dev		*pdev;		/* PCI device hosting this bus */
-#endif
-};
-
-/*
- * the macio_dev structure is used to describe a device
- * within an Apple MacIO ASIC.
- */
-struct macio_dev
-{
-	struct macio_bus	*bus;		/* macio bus this device is on */
-	struct macio_dev	*media_bay;	/* Device is part of a media bay */
-	struct platform_device	ofdev;
-	struct device_dma_parameters dma_parms; /* ide needs that */
-	int			n_resources;
-	struct resource		resource[MACIO_DEV_COUNT_RESOURCES];
-	int			n_interrupts;
-	struct resource		interrupt[MACIO_DEV_COUNT_IRQS];
-};
-#define	to_macio_device(d) container_of(d, struct macio_dev, ofdev.dev)
-#define	of_to_macio_device(d) container_of(d, struct macio_dev, ofdev)
-
-extern struct macio_dev *macio_dev_get(struct macio_dev *dev);
-extern void macio_dev_put(struct macio_dev *dev);
-
-/*
- * Accessors to resources & interrupts and other device
- * fields
- */
-
-static inline int macio_resource_count(struct macio_dev *dev)
-{
-	return dev->n_resources;
-}
-
-static inline unsigned long macio_resource_start(struct macio_dev *dev, int resource_no)
-{
-	return dev->resource[resource_no].start;
-}
-
-static inline unsigned long macio_resource_end(struct macio_dev *dev, int resource_no)
-{
-	return dev->resource[resource_no].end;
-}
-
-static inline unsigned long macio_resource_len(struct macio_dev *dev, int resource_no)
-{
-	struct resource *res = &dev->resource[resource_no];
-	if (res->start == 0 || res->end == 0 || res->end < res->start)
-		return 0;
-	return resource_size(res);
-}
-
-extern int macio_enable_devres(struct macio_dev *dev);
-
-extern int macio_request_resource(struct macio_dev *dev, int resource_no, const char *name);
-extern void macio_release_resource(struct macio_dev *dev, int resource_no);
-extern int macio_request_resources(struct macio_dev *dev, const char *name);
-extern void macio_release_resources(struct macio_dev *dev);
-
-static inline int macio_irq_count(struct macio_dev *dev)
-{
-	return dev->n_interrupts;
-}
-
-static inline int macio_irq(struct macio_dev *dev, int irq_no)
-{
-	return dev->interrupt[irq_no].start;
-}
-
-static inline void macio_set_drvdata(struct macio_dev *dev, void *data)
-{
-	dev_set_drvdata(&dev->ofdev.dev, data);
-}
-
-static inline void* macio_get_drvdata(struct macio_dev *dev)
-{
-	return dev_get_drvdata(&dev->ofdev.dev);
-}
-
-static inline struct device_node *macio_get_of_node(struct macio_dev *mdev)
-{
-	return mdev->ofdev.dev.of_node;
-}
-
-#ifdef CONFIG_PCI
-static inline struct pci_dev *macio_get_pci_dev(struct macio_dev *mdev)
-{
-	return mdev->bus->pdev;
-}
-#endif
-
-/*
- * A driver for a mac-io chip based device
- */
-struct macio_driver
-{
-	int	(*probe)(struct macio_dev* dev, const struct of_device_id *match);
-	int	(*remove)(struct macio_dev* dev);
-
-	int	(*suspend)(struct macio_dev* dev, pm_message_t state);
-	int	(*resume)(struct macio_dev* dev);
-	int	(*shutdown)(struct macio_dev* dev);
-
-#ifdef CONFIG_PMAC_MEDIABAY
-	void	(*mediabay_event)(struct macio_dev* dev, int mb_state);
-#endif
-	struct device_driver	driver;
-};
-#define	to_macio_driver(drv) container_of(drv,struct macio_driver, driver)
-
-extern int macio_register_driver(struct macio_driver *);
-extern void macio_unregister_driver(struct macio_driver *);
-
-#endif /* __KERNEL__ */
-#endif /* __MACIO_ASIC_H__ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/mc146818rtc.h b/ANDROID_3.4.5/arch/powerpc/include/asm/mc146818rtc.h
deleted file mode 100644
index f2741c8b..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/mc146818rtc.h
+++ /dev/null
@@ -1,36 +0,0 @@
-#ifndef _ASM_POWERPC_MC146818RTC_H
-#define _ASM_POWERPC_MC146818RTC_H
-
-/*
- * Machine dependent access functions for RTC registers.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifdef __KERNEL__
-
-#include <asm/io.h>
-
-#ifndef RTC_PORT
-#define RTC_PORT(x)	(0x70 + (x))
-#define RTC_ALWAYS_BCD	1	/* RTC operates in binary mode */
-#endif
-
-/*
- * The yet supported machines all access the RTC index register via
- * an ISA port access but the way to access the date register differs ...
- */
-#define CMOS_READ(addr) ({ \
-outb_p((addr),RTC_PORT(0)); \
-inb_p(RTC_PORT(1)); \
-})
-#define CMOS_WRITE(val, addr) ({ \
-outb_p((addr),RTC_PORT(0)); \
-outb_p((val),RTC_PORT(1)); \
-})
-
-#endif	/* __KERNEL__ */
-#endif	/* _ASM_POWERPC_MC146818RTC_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/mediabay.h b/ANDROID_3.4.5/arch/powerpc/include/asm/mediabay.h
deleted file mode 100644
index 11037a41..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/mediabay.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * mediabay.h: definitions for using the media bay
- * on PowerBook 3400 and similar computers.
- *
- * Copyright (C) 1997 Paul Mackerras.
- */
-#ifndef _PPC_MEDIABAY_H
-#define _PPC_MEDIABAY_H
-
-#ifdef __KERNEL__
-
-#define MB_FD		0	/* media bay contains floppy drive (automatic eject ?) */
-#define MB_FD1		1	/* media bay contains floppy drive (manual eject ?) */
-#define MB_SOUND	2	/* sound device ? */
-#define MB_CD		3	/* media bay contains ATA drive such as CD or ZIP */
-#define MB_PCI		5	/* media bay contains a PCI device */
-#define MB_POWER	6	/* media bay contains a Power device (???) */
-#define MB_NO		7	/* media bay contains nothing */
-
-struct macio_dev;
-
-#ifdef CONFIG_PMAC_MEDIABAY
-
-/* Check the content type of the bay, returns MB_NO if the bay is still
- * transitionning
- */
-extern int check_media_bay(struct macio_dev *bay);
-
-/* The ATA driver uses the calls below to temporarily hold on the
- * media bay callbacks while initializing the interface
- */
-extern void lock_media_bay(struct macio_dev *bay);
-extern void unlock_media_bay(struct macio_dev *bay);
-
-#else
-
-static inline int check_media_bay(struct macio_dev *bay)
-{
-	return MB_NO;
-}
-
-static inline void lock_media_bay(struct macio_dev *bay) { }
-static inline void unlock_media_bay(struct macio_dev *bay) { }
-
-#endif
-
-#endif /* __KERNEL__ */
-#endif /* _PPC_MEDIABAY_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/mman.h b/ANDROID_3.4.5/arch/powerpc/include/asm/mman.h
deleted file mode 100644
index d4a7f645..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/mman.h
+++ /dev/null
@@ -1,65 +0,0 @@
-#ifndef _ASM_POWERPC_MMAN_H
-#define _ASM_POWERPC_MMAN_H
-
-#include <asm-generic/mman-common.h>
-
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#define PROT_SAO	0x10		/* Strong Access Ordering */
-
-#define MAP_RENAME      MAP_ANONYMOUS   /* In SunOS terminology */
-#define MAP_NORESERVE   0x40            /* don't reserve swap pages */
-#define MAP_LOCKED	0x80
-
-#define MAP_GROWSDOWN	0x0100		/* stack-like segment */
-#define MAP_DENYWRITE	0x0800		/* ETXTBSY */
-#define MAP_EXECUTABLE	0x1000		/* mark it as an executable */
-
-#define MCL_CURRENT     0x2000          /* lock all currently mapped pages */
-#define MCL_FUTURE      0x4000          /* lock all additions to address space */
-
-#define MAP_POPULATE	0x8000		/* populate (prefault) pagetables */
-#define MAP_NONBLOCK	0x10000		/* do not block on IO */
-#define MAP_STACK	0x20000		/* give out an address that is best suited for process/thread stacks */
-#define MAP_HUGETLB	0x40000		/* create a huge page mapping */
-
-#ifdef __KERNEL__
-#ifdef CONFIG_PPC64
-
-#include <asm/cputable.h>
-#include <linux/mm.h>
-
-/*
- * This file is included by linux/mman.h, so we can't use cacl_vm_prot_bits()
- * here.  How important is the optimization?
- */
-static inline unsigned long arch_calc_vm_prot_bits(unsigned long prot)
-{
-	return (prot & PROT_SAO) ? VM_SAO : 0;
-}
-#define arch_calc_vm_prot_bits(prot) arch_calc_vm_prot_bits(prot)
-
-static inline pgprot_t arch_vm_get_page_prot(unsigned long vm_flags)
-{
-	return (vm_flags & VM_SAO) ? __pgprot(_PAGE_SAO) : __pgprot(0);
-}
-#define arch_vm_get_page_prot(vm_flags) arch_vm_get_page_prot(vm_flags)
-
-static inline int arch_validate_prot(unsigned long prot)
-{
-	if (prot & ~(PROT_READ | PROT_WRITE | PROT_EXEC | PROT_SEM | PROT_SAO))
-		return 0;
-	if ((prot & PROT_SAO) && !cpu_has_feature(CPU_FTR_SAO))
-		return 0;
-	return 1;
-}
-#define arch_validate_prot(prot) arch_validate_prot(prot)
-
-#endif /* CONFIG_PPC64 */
-#endif /* __KERNEL__ */
-#endif	/* _ASM_POWERPC_MMAN_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/mmu-40x.h b/ANDROID_3.4.5/arch/powerpc/include/asm/mmu-40x.h
deleted file mode 100644
index 34916865..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/mmu-40x.h
+++ /dev/null
@@ -1,67 +0,0 @@
-#ifndef _ASM_POWERPC_MMU_40X_H_
-#define _ASM_POWERPC_MMU_40X_H_
-
-/*
- * PPC40x support
- */
-
-#define PPC40X_TLB_SIZE 64
-
-/*
- * TLB entries are defined by a "high" tag portion and a "low" data
- * portion.  On all architectures, the data portion is 32-bits.
- *
- * TLB entries are managed entirely under software control by reading,
- * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx
- * instructions.
- */
-
-#define	TLB_LO          1
-#define	TLB_HI          0
-
-#define	TLB_DATA        TLB_LO
-#define	TLB_TAG         TLB_HI
-
-/* Tag portion */
-
-#define TLB_EPN_MASK    0xFFFFFC00      /* Effective Page Number */
-#define TLB_PAGESZ_MASK 0x00000380
-#define TLB_PAGESZ(x)   (((x) & 0x7) << 7)
-#define   PAGESZ_1K		0
-#define   PAGESZ_4K             1
-#define   PAGESZ_16K            2
-#define   PAGESZ_64K            3
-#define   PAGESZ_256K           4
-#define   PAGESZ_1M             5
-#define   PAGESZ_4M             6
-#define   PAGESZ_16M            7
-#define TLB_VALID       0x00000040      /* Entry is valid */
-
-/* Data portion */
-
-#define TLB_RPN_MASK    0xFFFFFC00      /* Real Page Number */
-#define TLB_PERM_MASK   0x00000300
-#define TLB_EX          0x00000200      /* Instruction execution allowed */
-#define TLB_WR          0x00000100      /* Writes permitted */
-#define TLB_ZSEL_MASK   0x000000F0
-#define TLB_ZSEL(x)     (((x) & 0xF) << 4)
-#define TLB_ATTR_MASK   0x0000000F
-#define TLB_W           0x00000008      /* Caching is write-through */
-#define TLB_I           0x00000004      /* Caching is inhibited */
-#define TLB_M           0x00000002      /* Memory is coherent */
-#define TLB_G           0x00000001      /* Memory is guarded from prefetch */
-
-#ifndef __ASSEMBLY__
-
-typedef struct {
-	unsigned int	id;
-	unsigned int	active;
-	unsigned long	vdso_base;
-} mm_context_t;
-
-#endif /* !__ASSEMBLY__ */
-
-#define mmu_virtual_psize	MMU_PAGE_4K
-#define mmu_linear_psize	MMU_PAGE_256M
-
-#endif /* _ASM_POWERPC_MMU_40X_H_ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/mmu-44x.h b/ANDROID_3.4.5/arch/powerpc/include/asm/mmu-44x.h
deleted file mode 100644
index bf52d704..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/mmu-44x.h
+++ /dev/null
@@ -1,152 +0,0 @@
-#ifndef _ASM_POWERPC_MMU_44X_H_
-#define _ASM_POWERPC_MMU_44X_H_
-/*
- * PPC440 support
- */
-
-#include <asm/page.h>
-
-#define PPC44x_MMUCR_TID	0x000000ff
-#define PPC44x_MMUCR_STS	0x00010000
-
-#define	PPC44x_TLB_PAGEID	0
-#define	PPC44x_TLB_XLAT		1
-#define	PPC44x_TLB_ATTRIB	2
-
-/* Page identification fields */
-#define PPC44x_TLB_EPN_MASK	0xfffffc00      /* Effective Page Number */
-#define	PPC44x_TLB_VALID	0x00000200      /* Valid flag */
-#define PPC44x_TLB_TS		0x00000100	/* Translation address space */
-#define PPC44x_TLB_1K		0x00000000	/* Page sizes */
-#define PPC44x_TLB_4K		0x00000010
-#define PPC44x_TLB_16K		0x00000020
-#define PPC44x_TLB_64K		0x00000030
-#define PPC44x_TLB_256K		0x00000040
-#define PPC44x_TLB_1M		0x00000050
-#define PPC44x_TLB_16M		0x00000070
-#define	PPC44x_TLB_256M		0x00000090
-
-/* Translation fields */
-#define PPC44x_TLB_RPN_MASK	0xfffffc00      /* Real Page Number */
-#define	PPC44x_TLB_ERPN_MASK	0x0000000f
-
-/* Storage attribute and access control fields */
-#define PPC44x_TLB_ATTR_MASK	0x0000ff80
-#define PPC44x_TLB_U0		0x00008000      /* User 0 */
-#define PPC44x_TLB_U1		0x00004000      /* User 1 */
-#define PPC44x_TLB_U2		0x00002000      /* User 2 */
-#define PPC44x_TLB_U3		0x00001000      /* User 3 */
-#define PPC44x_TLB_W		0x00000800      /* Caching is write-through */
-#define PPC44x_TLB_I		0x00000400      /* Caching is inhibited */
-#define PPC44x_TLB_M		0x00000200      /* Memory is coherent */
-#define PPC44x_TLB_G		0x00000100      /* Memory is guarded */
-#define PPC44x_TLB_E		0x00000080      /* Memory is little endian */
-
-#define PPC44x_TLB_PERM_MASK	0x0000003f
-#define PPC44x_TLB_UX		0x00000020      /* User execution */
-#define PPC44x_TLB_UW		0x00000010      /* User write */
-#define PPC44x_TLB_UR		0x00000008      /* User read */
-#define PPC44x_TLB_SX		0x00000004      /* Super execution */
-#define PPC44x_TLB_SW		0x00000002      /* Super write */
-#define PPC44x_TLB_SR		0x00000001      /* Super read */
-
-/* Number of TLB entries */
-#define PPC44x_TLB_SIZE		64
-
-/* 47x bits */
-#define PPC47x_MMUCR_TID	0x0000ffff
-#define PPC47x_MMUCR_STS	0x00010000
-
-/* Page identification fields */
-#define PPC47x_TLB0_EPN_MASK	0xfffff000      /* Effective Page Number */
-#define PPC47x_TLB0_VALID	0x00000800      /* Valid flag */
-#define PPC47x_TLB0_TS		0x00000400	/* Translation address space */
-#define PPC47x_TLB0_4K		0x00000000
-#define PPC47x_TLB0_16K		0x00000010
-#define PPC47x_TLB0_64K		0x00000030
-#define PPC47x_TLB0_1M		0x00000070
-#define PPC47x_TLB0_16M		0x000000f0
-#define PPC47x_TLB0_256M	0x000001f0
-#define PPC47x_TLB0_1G		0x000003f0
-#define PPC47x_TLB0_BOLTED_R	0x00000008	/* tlbre only */
-
-/* Translation fields */
-#define PPC47x_TLB1_RPN_MASK	0xfffff000      /* Real Page Number */
-#define PPC47x_TLB1_ERPN_MASK	0x000003ff
-
-/* Storage attribute and access control fields */
-#define PPC47x_TLB2_ATTR_MASK	0x0003ff80
-#define PPC47x_TLB2_IL1I	0x00020000      /* Memory is guarded */
-#define PPC47x_TLB2_IL1D	0x00010000      /* Memory is guarded */
-#define PPC47x_TLB2_U0		0x00008000      /* User 0 */
-#define PPC47x_TLB2_U1		0x00004000      /* User 1 */
-#define PPC47x_TLB2_U2		0x00002000      /* User 2 */
-#define PPC47x_TLB2_U3		0x00001000      /* User 3 */
-#define PPC47x_TLB2_W		0x00000800      /* Caching is write-through */
-#define PPC47x_TLB2_I		0x00000400      /* Caching is inhibited */
-#define PPC47x_TLB2_M		0x00000200      /* Memory is coherent */
-#define PPC47x_TLB2_G		0x00000100      /* Memory is guarded */
-#define PPC47x_TLB2_E		0x00000080      /* Memory is little endian */
-#define PPC47x_TLB2_PERM_MASK	0x0000003f
-#define PPC47x_TLB2_UX		0x00000020      /* User execution */
-#define PPC47x_TLB2_UW		0x00000010      /* User write */
-#define PPC47x_TLB2_UR		0x00000008      /* User read */
-#define PPC47x_TLB2_SX		0x00000004      /* Super execution */
-#define PPC47x_TLB2_SW		0x00000002      /* Super write */
-#define PPC47x_TLB2_SR		0x00000001      /* Super read */
-#define PPC47x_TLB2_U_RWX	(PPC47x_TLB2_UX|PPC47x_TLB2_UW|PPC47x_TLB2_UR)
-#define PPC47x_TLB2_S_RWX	(PPC47x_TLB2_SX|PPC47x_TLB2_SW|PPC47x_TLB2_SR)
-#define PPC47x_TLB2_S_RW	(PPC47x_TLB2_SW | PPC47x_TLB2_SR)
-#define PPC47x_TLB2_IMG		(PPC47x_TLB2_I | PPC47x_TLB2_M | PPC47x_TLB2_G)
-
-#ifndef __ASSEMBLY__
-
-extern unsigned int tlb_44x_hwater;
-extern unsigned int tlb_44x_index;
-
-typedef struct {
-	unsigned int	id;
-	unsigned int	active;
-	unsigned long	vdso_base;
-} mm_context_t;
-
-#endif /* !__ASSEMBLY__ */
-
-#ifndef CONFIG_PPC_EARLY_DEBUG_44x
-#define PPC44x_EARLY_TLBS	1
-#else
-#define PPC44x_EARLY_TLBS	2
-#define PPC44x_EARLY_DEBUG_VIRTADDR	(ASM_CONST(0xf0000000) \
-	| (ASM_CONST(CONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW) & 0xffff))
-#endif
-
-/* Size of the TLBs used for pinning in lowmem */
-#define PPC_PIN_SIZE	(1 << 28)	/* 256M */
-
-#if (PAGE_SHIFT == 12)
-#define PPC44x_TLBE_SIZE	PPC44x_TLB_4K
-#define PPC47x_TLBE_SIZE	PPC47x_TLB0_4K
-#define mmu_virtual_psize	MMU_PAGE_4K
-#elif (PAGE_SHIFT == 14)
-#define PPC44x_TLBE_SIZE	PPC44x_TLB_16K
-#define PPC47x_TLBE_SIZE	PPC47x_TLB0_16K
-#define mmu_virtual_psize	MMU_PAGE_16K
-#elif (PAGE_SHIFT == 16)
-#define PPC44x_TLBE_SIZE	PPC44x_TLB_64K
-#define PPC47x_TLBE_SIZE	PPC47x_TLB0_64K
-#define mmu_virtual_psize	MMU_PAGE_64K
-#elif (PAGE_SHIFT == 18)
-#define PPC44x_TLBE_SIZE	PPC44x_TLB_256K
-#define mmu_virtual_psize	MMU_PAGE_256K
-#else
-#error "Unsupported PAGE_SIZE"
-#endif
-
-#define mmu_linear_psize	MMU_PAGE_256M
-
-#define PPC44x_PGD_OFF_SHIFT	(32 - PGDIR_SHIFT + PGD_T_LOG2)
-#define PPC44x_PGD_OFF_MASK_BIT	(PGDIR_SHIFT - PGD_T_LOG2)
-#define PPC44x_PTE_ADD_SHIFT	(32 - PGDIR_SHIFT + PTE_SHIFT + PTE_T_LOG2)
-#define PPC44x_PTE_ADD_MASK_BIT	(32 - PTE_T_LOG2 - PTE_SHIFT)
-
-#endif /* _ASM_POWERPC_MMU_44X_H_ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/mmu-8xx.h b/ANDROID_3.4.5/arch/powerpc/include/asm/mmu-8xx.h
deleted file mode 100644
index 3d11d3ce..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/mmu-8xx.h
+++ /dev/null
@@ -1,149 +0,0 @@
-#ifndef _ASM_POWERPC_MMU_8XX_H_
-#define _ASM_POWERPC_MMU_8XX_H_
-/*
- * PPC8xx support
- */
-
-/* Control/status registers for the MPC8xx.
- * A write operation to these registers causes serialized access.
- * During software tablewalk, the registers used perform mask/shift-add
- * operations when written/read.  A TLB entry is created when the Mx_RPN
- * is written, and the contents of several registers are used to
- * create the entry.
- */
-#define SPRN_MI_CTR	784	/* Instruction TLB control register */
-#define MI_GPM		0x80000000	/* Set domain manager mode */
-#define MI_PPM		0x40000000	/* Set subpage protection */
-#define MI_CIDEF	0x20000000	/* Set cache inhibit when MMU dis */
-#define MI_RSV4I	0x08000000	/* Reserve 4 TLB entries */
-#define MI_PPCS		0x02000000	/* Use MI_RPN prob/priv state */
-#define MI_IDXMASK	0x00001f00	/* TLB index to be loaded */
-#define MI_RESETVAL	0x00000000	/* Value of register at reset */
-
-/* These are the Ks and Kp from the PowerPC books.  For proper operation,
- * Ks = 0, Kp = 1.
- */
-#define SPRN_MI_AP	786
-#define MI_Ks		0x80000000	/* Should not be set */
-#define MI_Kp		0x40000000	/* Should always be set */
-
-/* The effective page number register.  When read, contains the information
- * about the last instruction TLB miss.  When MI_RPN is written, bits in
- * this register are used to create the TLB entry.
- */
-#define SPRN_MI_EPN	787
-#define MI_EPNMASK	0xfffff000	/* Effective page number for entry */
-#define MI_EVALID	0x00000200	/* Entry is valid */
-#define MI_ASIDMASK	0x0000000f	/* ASID match value */
-					/* Reset value is undefined */
-
-/* A "level 1" or "segment" or whatever you want to call it register.
- * For the instruction TLB, it contains bits that get loaded into the
- * TLB entry when the MI_RPN is written.
- */
-#define SPRN_MI_TWC	789
-#define MI_APG		0x000001e0	/* Access protection group (0) */
-#define MI_GUARDED	0x00000010	/* Guarded storage */
-#define MI_PSMASK	0x0000000c	/* Mask of page size bits */
-#define MI_PS8MEG	0x0000000c	/* 8M page size */
-#define MI_PS512K	0x00000004	/* 512K page size */
-#define MI_PS4K_16K	0x00000000	/* 4K or 16K page size */
-#define MI_SVALID	0x00000001	/* Segment entry is valid */
-					/* Reset value is undefined */
-
-/* Real page number.  Defined by the pte.  Writing this register
- * causes a TLB entry to be created for the instruction TLB, using
- * additional information from the MI_EPN, and MI_TWC registers.
- */
-#define SPRN_MI_RPN	790
-
-/* Define an RPN value for mapping kernel memory to large virtual
- * pages for boot initialization.  This has real page number of 0,
- * large page size, shared page, cache enabled, and valid.
- * Also mark all subpages valid and write access.
- */
-#define MI_BOOTINIT	0x000001fd
-
-#define SPRN_MD_CTR	792	/* Data TLB control register */
-#define MD_GPM		0x80000000	/* Set domain manager mode */
-#define MD_PPM		0x40000000	/* Set subpage protection */
-#define MD_CIDEF	0x20000000	/* Set cache inhibit when MMU dis */
-#define MD_WTDEF	0x10000000	/* Set writethrough when MMU dis */
-#define MD_RSV4I	0x08000000	/* Reserve 4 TLB entries */
-#define MD_TWAM		0x04000000	/* Use 4K page hardware assist */
-#define MD_PPCS		0x02000000	/* Use MI_RPN prob/priv state */
-#define MD_IDXMASK	0x00001f00	/* TLB index to be loaded */
-#define MD_RESETVAL	0x04000000	/* Value of register at reset */
-
-#define SPRN_M_CASID	793	/* Address space ID (context) to match */
-#define MC_ASIDMASK	0x0000000f	/* Bits used for ASID value */
-
-
-/* These are the Ks and Kp from the PowerPC books.  For proper operation,
- * Ks = 0, Kp = 1.
- */
-#define SPRN_MD_AP	794
-#define MD_Ks		0x80000000	/* Should not be set */
-#define MD_Kp		0x40000000	/* Should always be set */
-
-/* The effective page number register.  When read, contains the information
- * about the last instruction TLB miss.  When MD_RPN is written, bits in
- * this register are used to create the TLB entry.
- */
-#define SPRN_MD_EPN	795
-#define MD_EPNMASK	0xfffff000	/* Effective page number for entry */
-#define MD_EVALID	0x00000200	/* Entry is valid */
-#define MD_ASIDMASK	0x0000000f	/* ASID match value */
-					/* Reset value is undefined */
-
-/* The pointer to the base address of the first level page table.
- * During a software tablewalk, reading this register provides the address
- * of the entry associated with MD_EPN.
- */
-#define SPRN_M_TWB	796
-#define	M_L1TB		0xfffff000	/* Level 1 table base address */
-#define M_L1INDX	0x00000ffc	/* Level 1 index, when read */
-					/* Reset value is undefined */
-
-/* A "level 1" or "segment" or whatever you want to call it register.
- * For the data TLB, it contains bits that get loaded into the TLB entry
- * when the MD_RPN is written.  It is also provides the hardware assist
- * for finding the PTE address during software tablewalk.
- */
-#define SPRN_MD_TWC	797
-#define MD_L2TB		0xfffff000	/* Level 2 table base address */
-#define MD_L2INDX	0xfffffe00	/* Level 2 index (*pte), when read */
-#define MD_APG		0x000001e0	/* Access protection group (0) */
-#define MD_GUARDED	0x00000010	/* Guarded storage */
-#define MD_PSMASK	0x0000000c	/* Mask of page size bits */
-#define MD_PS8MEG	0x0000000c	/* 8M page size */
-#define MD_PS512K	0x00000004	/* 512K page size */
-#define MD_PS4K_16K	0x00000000	/* 4K or 16K page size */
-#define MD_WT		0x00000002	/* Use writethrough page attribute */
-#define MD_SVALID	0x00000001	/* Segment entry is valid */
-					/* Reset value is undefined */
-
-
-/* Real page number.  Defined by the pte.  Writing this register
- * causes a TLB entry to be created for the data TLB, using
- * additional information from the MD_EPN, and MD_TWC registers.
- */
-#define SPRN_MD_RPN	798
-
-/* This is a temporary storage register that could be used to save
- * a processor working register during a tablewalk.
- */
-#define SPRN_M_TW	799
-
-#ifndef __ASSEMBLY__
-typedef struct {
-	unsigned int id;
-	unsigned int active;
-	unsigned long vdso_base;
-} mm_context_t;
-#endif /* !__ASSEMBLY__ */
-
-#define mmu_virtual_psize	MMU_PAGE_4K
-#define mmu_linear_psize	MMU_PAGE_8M
-
-#endif /* _ASM_POWERPC_MMU_8XX_H_ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/mmu-book3e.h b/ANDROID_3.4.5/arch/powerpc/include/asm/mmu-book3e.h
deleted file mode 100644
index cdb54218..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/mmu-book3e.h
+++ /dev/null
@@ -1,274 +0,0 @@
-#ifndef _ASM_POWERPC_MMU_BOOK3E_H_
-#define _ASM_POWERPC_MMU_BOOK3E_H_
-/*
- * Freescale Book-E/Book-3e (ISA 2.06+) MMU support
- */
-
-/* Book-3e defined page sizes */
-#define BOOK3E_PAGESZ_1K	0
-#define BOOK3E_PAGESZ_2K	1
-#define BOOK3E_PAGESZ_4K	2
-#define BOOK3E_PAGESZ_8K	3
-#define BOOK3E_PAGESZ_16K	4
-#define BOOK3E_PAGESZ_32K	5
-#define BOOK3E_PAGESZ_64K	6
-#define BOOK3E_PAGESZ_128K	7
-#define BOOK3E_PAGESZ_256K	8
-#define BOOK3E_PAGESZ_512K	9
-#define BOOK3E_PAGESZ_1M	10
-#define BOOK3E_PAGESZ_2M	11
-#define BOOK3E_PAGESZ_4M	12
-#define BOOK3E_PAGESZ_8M	13
-#define BOOK3E_PAGESZ_16M	14
-#define BOOK3E_PAGESZ_32M	15
-#define BOOK3E_PAGESZ_64M	16
-#define BOOK3E_PAGESZ_128M	17
-#define BOOK3E_PAGESZ_256M	18
-#define BOOK3E_PAGESZ_512M	19
-#define BOOK3E_PAGESZ_1GB	20
-#define BOOK3E_PAGESZ_2GB	21
-#define BOOK3E_PAGESZ_4GB	22
-#define BOOK3E_PAGESZ_8GB	23
-#define BOOK3E_PAGESZ_16GB	24
-#define BOOK3E_PAGESZ_32GB	25
-#define BOOK3E_PAGESZ_64GB	26
-#define BOOK3E_PAGESZ_128GB	27
-#define BOOK3E_PAGESZ_256GB	28
-#define BOOK3E_PAGESZ_512GB	29
-#define BOOK3E_PAGESZ_1TB	30
-#define BOOK3E_PAGESZ_2TB	31
-
-/* MAS registers bit definitions */
-
-#define MAS0_TLBSEL(x)		(((x) << 28) & 0x30000000)
-#define MAS0_ESEL_MASK		0x0FFF0000
-#define MAS0_ESEL_SHIFT		16
-#define MAS0_ESEL(x)		(((x) << MAS0_ESEL_SHIFT) & MAS0_ESEL_MASK)
-#define MAS0_NV(x)		((x) & 0x00000FFF)
-#define MAS0_HES		0x00004000
-#define MAS0_WQ_ALLWAYS		0x00000000
-#define MAS0_WQ_COND		0x00001000
-#define MAS0_WQ_CLR_RSRV       	0x00002000
-
-#define MAS1_VALID		0x80000000
-#define MAS1_IPROT		0x40000000
-#define MAS1_TID(x)		(((x) << 16) & 0x3FFF0000)
-#define MAS1_IND		0x00002000
-#define MAS1_TS			0x00001000
-#define MAS1_TSIZE_MASK		0x00000f80
-#define MAS1_TSIZE_SHIFT	7
-#define MAS1_TSIZE(x)		(((x) << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK)
-
-#define MAS2_EPN		0xFFFFF000
-#define MAS2_X0			0x00000040
-#define MAS2_X1			0x00000020
-#define MAS2_W			0x00000010
-#define MAS2_I			0x00000008
-#define MAS2_M			0x00000004
-#define MAS2_G			0x00000002
-#define MAS2_E			0x00000001
-#define MAS2_WIMGE_MASK		0x0000001f
-#define MAS2_EPN_MASK(size)		(~0 << (size + 10))
-#define MAS2_VAL(addr, size, flags)	((addr) & MAS2_EPN_MASK(size) | (flags))
-
-#define MAS3_RPN		0xFFFFF000
-#define MAS3_U0			0x00000200
-#define MAS3_U1			0x00000100
-#define MAS3_U2			0x00000080
-#define MAS3_U3			0x00000040
-#define MAS3_UX			0x00000020
-#define MAS3_SX			0x00000010
-#define MAS3_UW			0x00000008
-#define MAS3_SW			0x00000004
-#define MAS3_UR			0x00000002
-#define MAS3_SR			0x00000001
-#define MAS3_BAP_MASK		0x0000003f
-#define MAS3_SPSIZE		0x0000003e
-#define MAS3_SPSIZE_SHIFT	1
-
-#define MAS4_TLBSELD(x) 	MAS0_TLBSEL(x)
-#define MAS4_INDD		0x00008000	/* Default IND */
-#define MAS4_TSIZED(x)		MAS1_TSIZE(x)
-#define MAS4_X0D		0x00000040
-#define MAS4_X1D		0x00000020
-#define MAS4_WD			0x00000010
-#define MAS4_ID			0x00000008
-#define MAS4_MD			0x00000004
-#define MAS4_GD			0x00000002
-#define MAS4_ED			0x00000001
-#define MAS4_WIMGED_MASK	0x0000001f	/* Default WIMGE */
-#define MAS4_WIMGED_SHIFT	0
-#define MAS4_VLED		MAS4_X1D	/* Default VLE */
-#define MAS4_ACMD		0x000000c0	/* Default ACM */
-#define MAS4_ACMD_SHIFT		6
-#define MAS4_TSIZED_MASK	0x00000f80	/* Default TSIZE */
-#define MAS4_TSIZED_SHIFT	7
-
-#define MAS6_SPID0		0x3FFF0000
-#define MAS6_SPID1		0x00007FFE
-#define MAS6_ISIZE(x)		MAS1_TSIZE(x)
-#define MAS6_SAS		0x00000001
-#define MAS6_SPID		MAS6_SPID0
-#define MAS6_SIND 		0x00000002	/* Indirect page */
-#define MAS6_SIND_SHIFT		1
-#define MAS6_SPID_MASK		0x3fff0000
-#define MAS6_SPID_SHIFT		16
-#define MAS6_ISIZE_MASK		0x00000f80
-#define MAS6_ISIZE_SHIFT	7
-
-#define MAS7_RPN		0xFFFFFFFF
-
-/* Bit definitions for MMUCFG */
-#define MMUCFG_MAVN	0x00000003	/* MMU Architecture Version Number */
-#define MMUCFG_MAVN_V1	0x00000000	/* v1.0 */
-#define MMUCFG_MAVN_V2	0x00000001	/* v2.0 */
-#define MMUCFG_NTLBS	0x0000000c	/* Number of TLBs */
-#define MMUCFG_PIDSIZE	0x000007c0	/* PID Reg Size */
-#define MMUCFG_TWC	0x00008000	/* TLB Write Conditional (v2.0) */
-#define MMUCFG_LRAT	0x00010000	/* LRAT Supported (v2.0) */
-#define MMUCFG_RASIZE	0x00fe0000	/* Real Addr Size */
-#define MMUCFG_LPIDSIZE	0x0f000000	/* LPID Reg Size */
-
-/* Bit definitions for MMUCSR0 */
-#define MMUCSR0_TLB1FI	0x00000002	/* TLB1 Flash invalidate */
-#define MMUCSR0_TLB0FI	0x00000004	/* TLB0 Flash invalidate */
-#define MMUCSR0_TLB2FI	0x00000040	/* TLB2 Flash invalidate */
-#define MMUCSR0_TLB3FI	0x00000020	/* TLB3 Flash invalidate */
-#define MMUCSR0_TLBFI	(MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
-			 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
-#define MMUCSR0_TLB0PS	0x00000780	/* TLB0 Page Size */
-#define MMUCSR0_TLB1PS	0x00007800	/* TLB1 Page Size */
-#define MMUCSR0_TLB2PS	0x00078000	/* TLB2 Page Size */
-#define MMUCSR0_TLB3PS	0x00780000	/* TLB3 Page Size */
-
-/* MMUCFG bits */
-#define MMUCFG_MAVN_NASK	0x00000003
-#define MMUCFG_MAVN_V1_0	0x00000000
-#define MMUCFG_MAVN_V2_0	0x00000001
-#define MMUCFG_NTLB_MASK	0x0000000c
-#define MMUCFG_NTLB_SHIFT	2
-#define MMUCFG_PIDSIZE_MASK	0x000007c0
-#define MMUCFG_PIDSIZE_SHIFT	6
-#define MMUCFG_TWC		0x00008000
-#define MMUCFG_LRAT		0x00010000
-#define MMUCFG_RASIZE_MASK	0x00fe0000
-#define MMUCFG_RASIZE_SHIFT	17
-#define MMUCFG_LPIDSIZE_MASK	0x0f000000
-#define MMUCFG_LPIDSIZE_SHIFT	24
-
-/* TLBnCFG encoding */
-#define TLBnCFG_N_ENTRY		0x00000fff	/* number of entries */
-#define TLBnCFG_HES		0x00002000	/* HW select supported */
-#define TLBnCFG_IPROT		0x00008000	/* IPROT supported */
-#define TLBnCFG_GTWE		0x00010000	/* Guest can write */
-#define TLBnCFG_IND		0x00020000	/* IND entries supported */
-#define TLBnCFG_PT		0x00040000	/* Can load from page table */
-#define TLBnCFG_MINSIZE		0x00f00000	/* Minimum Page Size (v1.0) */
-#define TLBnCFG_MINSIZE_SHIFT	20
-#define TLBnCFG_MAXSIZE		0x000f0000	/* Maximum Page Size (v1.0) */
-#define TLBnCFG_MAXSIZE_SHIFT	16
-#define TLBnCFG_ASSOC		0xff000000	/* Associativity */
-#define TLBnCFG_ASSOC_SHIFT	24
-
-/* TLBnPS encoding */
-#define TLBnPS_4K		0x00000004
-#define TLBnPS_8K		0x00000008
-#define TLBnPS_16K		0x00000010
-#define TLBnPS_32K		0x00000020
-#define TLBnPS_64K		0x00000040
-#define TLBnPS_128K		0x00000080
-#define TLBnPS_256K		0x00000100
-#define TLBnPS_512K		0x00000200
-#define TLBnPS_1M 		0x00000400
-#define TLBnPS_2M 		0x00000800
-#define TLBnPS_4M 		0x00001000
-#define TLBnPS_8M 		0x00002000
-#define TLBnPS_16M		0x00004000
-#define TLBnPS_32M		0x00008000
-#define TLBnPS_64M		0x00010000
-#define TLBnPS_128M		0x00020000
-#define TLBnPS_256M		0x00040000
-#define TLBnPS_512M		0x00080000
-#define TLBnPS_1G		0x00100000
-#define TLBnPS_2G		0x00200000
-#define TLBnPS_4G		0x00400000
-#define TLBnPS_8G		0x00800000
-#define TLBnPS_16G		0x01000000
-#define TLBnPS_32G		0x02000000
-#define TLBnPS_64G		0x04000000
-#define TLBnPS_128G		0x08000000
-#define TLBnPS_256G		0x10000000
-
-/* tlbilx action encoding */
-#define TLBILX_T_ALL			0
-#define TLBILX_T_TID			1
-#define TLBILX_T_FULLMATCH		3
-#define TLBILX_T_CLASS0			4
-#define TLBILX_T_CLASS1			5
-#define TLBILX_T_CLASS2			6
-#define TLBILX_T_CLASS3			7
-
-#ifndef __ASSEMBLY__
-
-extern unsigned int tlbcam_index;
-
-typedef struct {
-	unsigned int	id;
-	unsigned int	active;
-	unsigned long	vdso_base;
-#ifdef CONFIG_PPC_ICSWX
-	struct spinlock *cop_lockp;	/* guard cop related stuff */
-	unsigned long acop;		/* mask of enabled coprocessor types */
-#endif /* CONFIG_PPC_ICSWX */
-#ifdef CONFIG_PPC_MM_SLICES
-	u64 low_slices_psize;   /* SLB page size encodings */
-	u64 high_slices_psize;  /* 4 bits per slice for now */
-	u16 user_psize;         /* page size index */
-#endif
-} mm_context_t;
-
-/* Page size definitions, common between 32 and 64-bit
- *
- *    shift : is the "PAGE_SHIFT" value for that page size
- *    penc  : is the pte encoding mask
- *
- */
-struct mmu_psize_def
-{
-	unsigned int	shift;	/* number of bits */
-	unsigned int	enc;	/* PTE encoding */
-	unsigned int    ind;    /* Corresponding indirect page size shift */
-	unsigned int	flags;
-#define MMU_PAGE_SIZE_DIRECT	0x1	/* Supported as a direct size */
-#define MMU_PAGE_SIZE_INDIRECT	0x2	/* Supported as an indirect size */
-};
-extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
-
-/* The page sizes use the same names as 64-bit hash but are
- * constants
- */
-#if defined(CONFIG_PPC_4K_PAGES)
-#define mmu_virtual_psize	MMU_PAGE_4K
-#elif defined(CONFIG_PPC_64K_PAGES)
-#define mmu_virtual_psize	MMU_PAGE_64K
-#else
-#error Unsupported page size
-#endif
-
-extern int mmu_linear_psize;
-extern int mmu_vmemmap_psize;
-
-#ifdef CONFIG_PPC64
-extern unsigned long linear_map_top;
-
-/*
- * 64-bit booke platforms don't load the tlb in the tlb miss handler code.
- * HUGETLB_NEED_PRELOAD handles this - it causes huge_ptep_set_access_flags to
- * return 1, indicating that the tlb requires preloading.
- */
-#define HUGETLB_NEED_PRELOAD
-#endif
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* _ASM_POWERPC_MMU_BOOK3E_H_ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/mmu-hash32.h b/ANDROID_3.4.5/arch/powerpc/include/asm/mmu-hash32.h
deleted file mode 100644
index 16f513e5..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/mmu-hash32.h
+++ /dev/null
@@ -1,93 +0,0 @@
-#ifndef _ASM_POWERPC_MMU_HASH32_H_
-#define _ASM_POWERPC_MMU_HASH32_H_
-/*
- * 32-bit hash table MMU support
- */
-
-/*
- * BATs
- */
-
-/* Block size masks */
-#define BL_128K	0x000
-#define BL_256K 0x001
-#define BL_512K 0x003
-#define BL_1M   0x007
-#define BL_2M   0x00F
-#define BL_4M   0x01F
-#define BL_8M   0x03F
-#define BL_16M  0x07F
-#define BL_32M  0x0FF
-#define BL_64M  0x1FF
-#define BL_128M 0x3FF
-#define BL_256M 0x7FF
-
-/* BAT Access Protection */
-#define BPP_XX	0x00		/* No access */
-#define BPP_RX	0x01		/* Read only */
-#define BPP_RW	0x02		/* Read/write */
-
-#ifndef __ASSEMBLY__
-/* Contort a phys_addr_t into the right format/bits for a BAT */
-#ifdef CONFIG_PHYS_64BIT
-#define BAT_PHYS_ADDR(x) ((u32)((x & 0x00000000fffe0000ULL) | \
-				((x & 0x0000000e00000000ULL) >> 24) | \
-				((x & 0x0000000100000000ULL) >> 30)))
-#else
-#define BAT_PHYS_ADDR(x) (x)
-#endif
-
-struct ppc_bat {
-	u32 batu;
-	u32 batl;
-};
-#endif /* !__ASSEMBLY__ */
-
-/*
- * Hash table
- */
-
-/* Values for PP (assumes Ks=0, Kp=1) */
-#define PP_RWXX	0	/* Supervisor read/write, User none */
-#define PP_RWRX 1	/* Supervisor read/write, User read */
-#define PP_RWRW 2	/* Supervisor read/write, User read/write */
-#define PP_RXRX 3	/* Supervisor read,       User read */
-
-#ifndef __ASSEMBLY__
-
-/*
- * Hardware Page Table Entry
- * Note that the xpn and x bitfields are used only by processors that
- * support extended addressing; otherwise, those bits are reserved.
- */
-struct hash_pte {
-	unsigned long v:1;	/* Entry is valid */
-	unsigned long vsid:24;	/* Virtual segment identifier */
-	unsigned long h:1;	/* Hash algorithm indicator */
-	unsigned long api:6;	/* Abbreviated page index */
-	unsigned long rpn:20;	/* Real (physical) page number */
-	unsigned long xpn:3;	/* Real page number bits 0-2, optional */
-	unsigned long r:1;	/* Referenced */
-	unsigned long c:1;	/* Changed */
-	unsigned long w:1;	/* Write-thru cache mode */
-	unsigned long i:1;	/* Cache inhibited */
-	unsigned long m:1;	/* Memory coherence */
-	unsigned long g:1;	/* Guarded */
-	unsigned long x:1;	/* Real page number bit 3, optional */
-	unsigned long pp:2;	/* Page protection */
-};
-
-typedef struct {
-	unsigned long id;
-	unsigned long vdso_base;
-} mm_context_t;
-
-#endif /* !__ASSEMBLY__ */
-
-/* We happily ignore the smaller BATs on 601, we don't actually use
- * those definitions on hash32 at the moment anyway
- */
-#define mmu_virtual_psize	MMU_PAGE_4K
-#define mmu_linear_psize	MMU_PAGE_256M
-
-#endif /* _ASM_POWERPC_MMU_HASH32_H_ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/mmu-hash64.h b/ANDROID_3.4.5/arch/powerpc/include/asm/mmu-hash64.h
deleted file mode 100644
index 1c65a598..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/mmu-hash64.h
+++ /dev/null
@@ -1,485 +0,0 @@
-#ifndef _ASM_POWERPC_MMU_HASH64_H_
-#define _ASM_POWERPC_MMU_HASH64_H_
-/*
- * PowerPC64 memory management structures
- *
- * Dave Engebretsen & Mike Corrigan <{engebret|mikejc}@us.ibm.com>
- *   PPC64 rework.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <asm/asm-compat.h>
-#include <asm/page.h>
-
-/*
- * Segment table
- */
-
-#define STE_ESID_V	0x80
-#define STE_ESID_KS	0x20
-#define STE_ESID_KP	0x10
-#define STE_ESID_N	0x08
-
-#define STE_VSID_SHIFT	12
-
-/* Location of cpu0's segment table */
-#define STAB0_PAGE	0x8
-#define STAB0_OFFSET	(STAB0_PAGE << 12)
-#define STAB0_PHYS_ADDR	(STAB0_OFFSET + PHYSICAL_START)
-
-#ifndef __ASSEMBLY__
-extern char initial_stab[];
-#endif /* ! __ASSEMBLY */
-
-/*
- * SLB
- */
-
-#define SLB_NUM_BOLTED		3
-#define SLB_CACHE_ENTRIES	8
-#define SLB_MIN_SIZE		32
-
-/* Bits in the SLB ESID word */
-#define SLB_ESID_V		ASM_CONST(0x0000000008000000) /* valid */
-
-/* Bits in the SLB VSID word */
-#define SLB_VSID_SHIFT		12
-#define SLB_VSID_SHIFT_1T	24
-#define SLB_VSID_SSIZE_SHIFT	62
-#define SLB_VSID_B		ASM_CONST(0xc000000000000000)
-#define SLB_VSID_B_256M		ASM_CONST(0x0000000000000000)
-#define SLB_VSID_B_1T		ASM_CONST(0x4000000000000000)
-#define SLB_VSID_KS		ASM_CONST(0x0000000000000800)
-#define SLB_VSID_KP		ASM_CONST(0x0000000000000400)
-#define SLB_VSID_N		ASM_CONST(0x0000000000000200) /* no-execute */
-#define SLB_VSID_L		ASM_CONST(0x0000000000000100)
-#define SLB_VSID_C		ASM_CONST(0x0000000000000080) /* class */
-#define SLB_VSID_LP		ASM_CONST(0x0000000000000030)
-#define SLB_VSID_LP_00		ASM_CONST(0x0000000000000000)
-#define SLB_VSID_LP_01		ASM_CONST(0x0000000000000010)
-#define SLB_VSID_LP_10		ASM_CONST(0x0000000000000020)
-#define SLB_VSID_LP_11		ASM_CONST(0x0000000000000030)
-#define SLB_VSID_LLP		(SLB_VSID_L|SLB_VSID_LP)
-
-#define SLB_VSID_KERNEL		(SLB_VSID_KP)
-#define SLB_VSID_USER		(SLB_VSID_KP|SLB_VSID_KS|SLB_VSID_C)
-
-#define SLBIE_C			(0x08000000)
-#define SLBIE_SSIZE_SHIFT	25
-
-/*
- * Hash table
- */
-
-#define HPTES_PER_GROUP 8
-
-#define HPTE_V_SSIZE_SHIFT	62
-#define HPTE_V_AVPN_SHIFT	7
-#define HPTE_V_AVPN		ASM_CONST(0x3fffffffffffff80)
-#define HPTE_V_AVPN_VAL(x)	(((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
-#define HPTE_V_COMPARE(x,y)	(!(((x) ^ (y)) & 0xffffffffffffff80UL))
-#define HPTE_V_BOLTED		ASM_CONST(0x0000000000000010)
-#define HPTE_V_LOCK		ASM_CONST(0x0000000000000008)
-#define HPTE_V_LARGE		ASM_CONST(0x0000000000000004)
-#define HPTE_V_SECONDARY	ASM_CONST(0x0000000000000002)
-#define HPTE_V_VALID		ASM_CONST(0x0000000000000001)
-
-#define HPTE_R_PP0		ASM_CONST(0x8000000000000000)
-#define HPTE_R_TS		ASM_CONST(0x4000000000000000)
-#define HPTE_R_KEY_HI		ASM_CONST(0x3000000000000000)
-#define HPTE_R_RPN_SHIFT	12
-#define HPTE_R_RPN		ASM_CONST(0x0ffffffffffff000)
-#define HPTE_R_PP		ASM_CONST(0x0000000000000003)
-#define HPTE_R_N		ASM_CONST(0x0000000000000004)
-#define HPTE_R_G		ASM_CONST(0x0000000000000008)
-#define HPTE_R_M		ASM_CONST(0x0000000000000010)
-#define HPTE_R_I		ASM_CONST(0x0000000000000020)
-#define HPTE_R_W		ASM_CONST(0x0000000000000040)
-#define HPTE_R_WIMG		ASM_CONST(0x0000000000000078)
-#define HPTE_R_C		ASM_CONST(0x0000000000000080)
-#define HPTE_R_R		ASM_CONST(0x0000000000000100)
-#define HPTE_R_KEY_LO		ASM_CONST(0x0000000000000e00)
-
-#define HPTE_V_1TB_SEG		ASM_CONST(0x4000000000000000)
-#define HPTE_V_VRMA_MASK	ASM_CONST(0x4001ffffff000000)
-
-/* Values for PP (assumes Ks=0, Kp=1) */
-#define PP_RWXX	0	/* Supervisor read/write, User none */
-#define PP_RWRX 1	/* Supervisor read/write, User read */
-#define PP_RWRW 2	/* Supervisor read/write, User read/write */
-#define PP_RXRX 3	/* Supervisor read,       User read */
-#define PP_RXXX	(HPTE_R_PP0 | 2)	/* Supervisor read, user none */
-
-#ifndef __ASSEMBLY__
-
-struct hash_pte {
-	unsigned long v;
-	unsigned long r;
-};
-
-extern struct hash_pte *htab_address;
-extern unsigned long htab_size_bytes;
-extern unsigned long htab_hash_mask;
-
-/*
- * Page size definition
- *
- *    shift : is the "PAGE_SHIFT" value for that page size
- *    sllp  : is a bit mask with the value of SLB L || LP to be or'ed
- *            directly to a slbmte "vsid" value
- *    penc  : is the HPTE encoding mask for the "LP" field:
- *
- */
-struct mmu_psize_def
-{
-	unsigned int	shift;	/* number of bits */
-	unsigned int	penc;	/* HPTE encoding */
-	unsigned int	tlbiel;	/* tlbiel supported for that page size */
-	unsigned long	avpnm;	/* bits to mask out in AVPN in the HPTE */
-	unsigned long	sllp;	/* SLB L||LP (exact mask to use in slbmte) */
-};
-
-#endif /* __ASSEMBLY__ */
-
-/*
- * Segment sizes.
- * These are the values used by hardware in the B field of
- * SLB entries and the first dword of MMU hashtable entries.
- * The B field is 2 bits; the values 2 and 3 are unused and reserved.
- */
-#define MMU_SEGSIZE_256M	0
-#define MMU_SEGSIZE_1T		1
-
-
-#ifndef __ASSEMBLY__
-
-/*
- * The current system page and segment sizes
- */
-extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
-extern int mmu_linear_psize;
-extern int mmu_virtual_psize;
-extern int mmu_vmalloc_psize;
-extern int mmu_vmemmap_psize;
-extern int mmu_io_psize;
-extern int mmu_kernel_ssize;
-extern int mmu_highuser_ssize;
-extern u16 mmu_slb_size;
-extern unsigned long tce_alloc_start, tce_alloc_end;
-
-/*
- * If the processor supports 64k normal pages but not 64k cache
- * inhibited pages, we have to be prepared to switch processes
- * to use 4k pages when they create cache-inhibited mappings.
- * If this is the case, mmu_ci_restrictions will be set to 1.
- */
-extern int mmu_ci_restrictions;
-
-/*
- * This function sets the AVPN and L fields of the HPTE  appropriately
- * for the page size
- */
-static inline unsigned long hpte_encode_v(unsigned long va, int psize,
-					  int ssize)
-{
-	unsigned long v;
-	v = (va >> 23) & ~(mmu_psize_defs[psize].avpnm);
-	v <<= HPTE_V_AVPN_SHIFT;
-	if (psize != MMU_PAGE_4K)
-		v |= HPTE_V_LARGE;
-	v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT;
-	return v;
-}
-
-/*
- * This function sets the ARPN, and LP fields of the HPTE appropriately
- * for the page size. We assume the pa is already "clean" that is properly
- * aligned for the requested page size
- */
-static inline unsigned long hpte_encode_r(unsigned long pa, int psize)
-{
-	unsigned long r;
-
-	/* A 4K page needs no special encoding */
-	if (psize == MMU_PAGE_4K)
-		return pa & HPTE_R_RPN;
-	else {
-		unsigned int penc = mmu_psize_defs[psize].penc;
-		unsigned int shift = mmu_psize_defs[psize].shift;
-		return (pa & ~((1ul << shift) - 1)) | (penc << 12);
-	}
-	return r;
-}
-
-/*
- * Build a VA given VSID, EA and segment size
- */
-static inline unsigned long hpt_va(unsigned long ea, unsigned long vsid,
-				   int ssize)
-{
-	if (ssize == MMU_SEGSIZE_256M)
-		return (vsid << 28) | (ea & 0xfffffffUL);
-	return (vsid << 40) | (ea & 0xffffffffffUL);
-}
-
-/*
- * This hashes a virtual address
- */
-
-static inline unsigned long hpt_hash(unsigned long va, unsigned int shift,
-				     int ssize)
-{
-	unsigned long hash, vsid;
-
-	if (ssize == MMU_SEGSIZE_256M) {
-		hash = (va >> 28) ^ ((va & 0x0fffffffUL) >> shift);
-	} else {
-		vsid = va >> 40;
-		hash = vsid ^ (vsid << 25) ^ ((va & 0xffffffffffUL) >> shift);
-	}
-	return hash & 0x7fffffffffUL;
-}
-
-extern int __hash_page_4K(unsigned long ea, unsigned long access,
-			  unsigned long vsid, pte_t *ptep, unsigned long trap,
-			  unsigned int local, int ssize, int subpage_prot);
-extern int __hash_page_64K(unsigned long ea, unsigned long access,
-			   unsigned long vsid, pte_t *ptep, unsigned long trap,
-			   unsigned int local, int ssize);
-struct mm_struct;
-unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap);
-extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap);
-int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
-		     pte_t *ptep, unsigned long trap, int local, int ssize,
-		     unsigned int shift, unsigned int mmu_psize);
-extern void hash_failure_debug(unsigned long ea, unsigned long access,
-			       unsigned long vsid, unsigned long trap,
-			       int ssize, int psize, unsigned long pte);
-extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
-			     unsigned long pstart, unsigned long prot,
-			     int psize, int ssize);
-extern void add_gpage(u64 addr, u64 page_size, unsigned long number_of_pages);
-extern void demote_segment_4k(struct mm_struct *mm, unsigned long addr);
-
-extern void hpte_init_native(void);
-extern void hpte_init_lpar(void);
-extern void hpte_init_beat(void);
-extern void hpte_init_beat_v3(void);
-
-extern void stabs_alloc(void);
-extern void slb_initialize(void);
-extern void slb_flush_and_rebolt(void);
-extern void stab_initialize(unsigned long stab);
-
-extern void slb_vmalloc_update(void);
-extern void slb_set_size(u16 size);
-#endif /* __ASSEMBLY__ */
-
-/*
- * VSID allocation
- *
- * We first generate a 36-bit "proto-VSID".  For kernel addresses this
- * is equal to the ESID, for user addresses it is:
- *	(context << 15) | (esid & 0x7fff)
- *
- * The two forms are distinguishable because the top bit is 0 for user
- * addresses, whereas the top two bits are 1 for kernel addresses.
- * Proto-VSIDs with the top two bits equal to 0b10 are reserved for
- * now.
- *
- * The proto-VSIDs are then scrambled into real VSIDs with the
- * multiplicative hash:
- *
- *	VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS
- *	where	VSID_MULTIPLIER = 268435399 = 0xFFFFFC7
- *		VSID_MODULUS = 2^36-1 = 0xFFFFFFFFF
- *
- * This scramble is only well defined for proto-VSIDs below
- * 0xFFFFFFFFF, so both proto-VSID and actual VSID 0xFFFFFFFFF are
- * reserved.  VSID_MULTIPLIER is prime, so in particular it is
- * co-prime to VSID_MODULUS, making this a 1:1 scrambling function.
- * Because the modulus is 2^n-1 we can compute it efficiently without
- * a divide or extra multiply (see below).
- *
- * This scheme has several advantages over older methods:
- *
- * 	- We have VSIDs allocated for every kernel address
- * (i.e. everything above 0xC000000000000000), except the very top
- * segment, which simplifies several things.
- *
- *	- We allow for 16 significant bits of ESID and 19 bits of
- * context for user addresses.  i.e. 16T (44 bits) of address space for
- * up to half a million contexts.
- *
- * 	- The scramble function gives robust scattering in the hash
- * table (at least based on some initial results).  The previous
- * method was more susceptible to pathological cases giving excessive
- * hash collisions.
- */
-/*
- * WARNING - If you change these you must make sure the asm
- * implementations in slb_allocate (slb_low.S), do_stab_bolted
- * (head.S) and ASM_VSID_SCRAMBLE (below) are changed accordingly.
- */
-
-#define VSID_MULTIPLIER_256M	ASM_CONST(200730139)	/* 28-bit prime */
-#define VSID_BITS_256M		36
-#define VSID_MODULUS_256M	((1UL<<VSID_BITS_256M)-1)
-
-#define VSID_MULTIPLIER_1T	ASM_CONST(12538073)	/* 24-bit prime */
-#define VSID_BITS_1T		24
-#define VSID_MODULUS_1T		((1UL<<VSID_BITS_1T)-1)
-
-#define CONTEXT_BITS		19
-#define USER_ESID_BITS		16
-#define USER_ESID_BITS_1T	4
-
-#define USER_VSID_RANGE	(1UL << (USER_ESID_BITS + SID_SHIFT))
-
-/*
- * This macro generates asm code to compute the VSID scramble
- * function.  Used in slb_allocate() and do_stab_bolted.  The function
- * computed is: (protovsid*VSID_MULTIPLIER) % VSID_MODULUS
- *
- *	rt = register continaing the proto-VSID and into which the
- *		VSID will be stored
- *	rx = scratch register (clobbered)
- *
- * 	- rt and rx must be different registers
- * 	- The answer will end up in the low VSID_BITS bits of rt.  The higher
- * 	  bits may contain other garbage, so you may need to mask the
- * 	  result.
- */
-#define ASM_VSID_SCRAMBLE(rt, rx, size)					\
-	lis	rx,VSID_MULTIPLIER_##size@h;				\
-	ori	rx,rx,VSID_MULTIPLIER_##size@l;				\
-	mulld	rt,rt,rx;		/* rt = rt * MULTIPLIER */	\
-									\
-	srdi	rx,rt,VSID_BITS_##size;					\
-	clrldi	rt,rt,(64-VSID_BITS_##size);				\
-	add	rt,rt,rx;		/* add high and low bits */	\
-	/* Now, r3 == VSID (mod 2^36-1), and lies between 0 and		\
-	 * 2^36-1+2^28-1.  That in particular means that if r3 >=	\
-	 * 2^36-1, then r3+1 has the 2^36 bit set.  So, if r3+1 has	\
-	 * the bit clear, r3 already has the answer we want, if it	\
-	 * doesn't, the answer is the low 36 bits of r3+1.  So in all	\
-	 * cases the answer is the low 36 bits of (r3 + ((r3+1) >> 36))*/\
-	addi	rx,rt,1;						\
-	srdi	rx,rx,VSID_BITS_##size;	/* extract 2^VSID_BITS bit */	\
-	add	rt,rt,rx
-
-
-#ifndef __ASSEMBLY__
-
-#ifdef CONFIG_PPC_SUBPAGE_PROT
-/*
- * For the sub-page protection option, we extend the PGD with one of
- * these.  Basically we have a 3-level tree, with the top level being
- * the protptrs array.  To optimize speed and memory consumption when
- * only addresses < 4GB are being protected, pointers to the first
- * four pages of sub-page protection words are stored in the low_prot
- * array.
- * Each page of sub-page protection words protects 1GB (4 bytes
- * protects 64k).  For the 3-level tree, each page of pointers then
- * protects 8TB.
- */
-struct subpage_prot_table {
-	unsigned long maxaddr;	/* only addresses < this are protected */
-	unsigned int **protptrs[2];
-	unsigned int *low_prot[4];
-};
-
-#define SBP_L1_BITS		(PAGE_SHIFT - 2)
-#define SBP_L2_BITS		(PAGE_SHIFT - 3)
-#define SBP_L1_COUNT		(1 << SBP_L1_BITS)
-#define SBP_L2_COUNT		(1 << SBP_L2_BITS)
-#define SBP_L2_SHIFT		(PAGE_SHIFT + SBP_L1_BITS)
-#define SBP_L3_SHIFT		(SBP_L2_SHIFT + SBP_L2_BITS)
-
-extern void subpage_prot_free(struct mm_struct *mm);
-extern void subpage_prot_init_new_context(struct mm_struct *mm);
-#else
-static inline void subpage_prot_free(struct mm_struct *mm) {}
-static inline void subpage_prot_init_new_context(struct mm_struct *mm) { }
-#endif /* CONFIG_PPC_SUBPAGE_PROT */
-
-typedef unsigned long mm_context_id_t;
-struct spinlock;
-
-typedef struct {
-	mm_context_id_t id;
-	u16 user_psize;		/* page size index */
-
-#ifdef CONFIG_PPC_MM_SLICES
-	u64 low_slices_psize;	/* SLB page size encodings */
-	u64 high_slices_psize;  /* 4 bits per slice for now */
-#else
-	u16 sllp;		/* SLB page size encoding */
-#endif
-	unsigned long vdso_base;
-#ifdef CONFIG_PPC_SUBPAGE_PROT
-	struct subpage_prot_table spt;
-#endif /* CONFIG_PPC_SUBPAGE_PROT */
-#ifdef CONFIG_PPC_ICSWX
-	struct spinlock *cop_lockp; /* guard acop and cop_pid */
-	unsigned long acop;	/* mask of enabled coprocessor types */
-	unsigned int cop_pid;	/* pid value used with coprocessors */
-#endif /* CONFIG_PPC_ICSWX */
-} mm_context_t;
-
-
-#if 0
-/*
- * The code below is equivalent to this function for arguments
- * < 2^VSID_BITS, which is all this should ever be called
- * with.  However gcc is not clever enough to compute the
- * modulus (2^n-1) without a second multiply.
- */
-#define vsid_scramble(protovsid, size) \
-	((((protovsid) * VSID_MULTIPLIER_##size) % VSID_MODULUS_##size))
-
-#else /* 1 */
-#define vsid_scramble(protovsid, size) \
-	({								 \
-		unsigned long x;					 \
-		x = (protovsid) * VSID_MULTIPLIER_##size;		 \
-		x = (x >> VSID_BITS_##size) + (x & VSID_MODULUS_##size); \
-		(x + ((x+1) >> VSID_BITS_##size)) & VSID_MODULUS_##size; \
-	})
-#endif /* 1 */
-
-/* This is only valid for addresses >= PAGE_OFFSET */
-static inline unsigned long get_kernel_vsid(unsigned long ea, int ssize)
-{
-	if (ssize == MMU_SEGSIZE_256M)
-		return vsid_scramble(ea >> SID_SHIFT, 256M);
-	return vsid_scramble(ea >> SID_SHIFT_1T, 1T);
-}
-
-/* Returns the segment size indicator for a user address */
-static inline int user_segment_size(unsigned long addr)
-{
-	/* Use 1T segments if possible for addresses >= 1T */
-	if (addr >= (1UL << SID_SHIFT_1T))
-		return mmu_highuser_ssize;
-	return MMU_SEGSIZE_256M;
-}
-
-/* This is only valid for user addresses (which are below 2^44) */
-static inline unsigned long get_vsid(unsigned long context, unsigned long ea,
-				     int ssize)
-{
-	if (ssize == MMU_SEGSIZE_256M)
-		return vsid_scramble((context << USER_ESID_BITS)
-				     | (ea >> SID_SHIFT), 256M);
-	return vsid_scramble((context << USER_ESID_BITS_1T)
-			     | (ea >> SID_SHIFT_1T), 1T);
-}
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* _ASM_POWERPC_MMU_HASH64_H_ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/mmu.h b/ANDROID_3.4.5/arch/powerpc/include/asm/mmu.h
deleted file mode 100644
index f0145522..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/mmu.h
+++ /dev/null
@@ -1,211 +0,0 @@
-#ifndef _ASM_POWERPC_MMU_H_
-#define _ASM_POWERPC_MMU_H_
-#ifdef __KERNEL__
-
-#include <linux/types.h>
-
-#include <asm/asm-compat.h>
-#include <asm/feature-fixups.h>
-
-/*
- * MMU features bit definitions
- */
-
-/*
- * First half is MMU families
- */
-#define MMU_FTR_HPTE_TABLE		ASM_CONST(0x00000001)
-#define MMU_FTR_TYPE_8xx		ASM_CONST(0x00000002)
-#define MMU_FTR_TYPE_40x		ASM_CONST(0x00000004)
-#define MMU_FTR_TYPE_44x		ASM_CONST(0x00000008)
-#define MMU_FTR_TYPE_FSL_E		ASM_CONST(0x00000010)
-#define MMU_FTR_TYPE_3E			ASM_CONST(0x00000020)
-#define MMU_FTR_TYPE_47x		ASM_CONST(0x00000040)
-
-/*
- * This is individual features
- */
-
-/* Enable use of high BAT registers */
-#define MMU_FTR_USE_HIGH_BATS		ASM_CONST(0x00010000)
-
-/* Enable >32-bit physical addresses on 32-bit processor, only used
- * by CONFIG_6xx currently as BookE supports that from day 1
- */
-#define MMU_FTR_BIG_PHYS		ASM_CONST(0x00020000)
-
-/* Enable use of broadcast TLB invalidations. We don't always set it
- * on processors that support it due to other constraints with the
- * use of such invalidations
- */
-#define MMU_FTR_USE_TLBIVAX_BCAST	ASM_CONST(0x00040000)
-
-/* Enable use of tlbilx invalidate instructions.
- */
-#define MMU_FTR_USE_TLBILX		ASM_CONST(0x00080000)
-
-/* This indicates that the processor cannot handle multiple outstanding
- * broadcast tlbivax or tlbsync. This makes the code use a spinlock
- * around such invalidate forms.
- */
-#define MMU_FTR_LOCK_BCAST_INVAL	ASM_CONST(0x00100000)
-
-/* This indicates that the processor doesn't handle way selection
- * properly and needs SW to track and update the LRU state.  This
- * is specific to an errata on e300c2/c3/c4 class parts
- */
-#define MMU_FTR_NEED_DTLB_SW_LRU	ASM_CONST(0x00200000)
-
-/* Enable use of TLB reservation.  Processor should support tlbsrx.
- * instruction and MAS0[WQ].
- */
-#define MMU_FTR_USE_TLBRSRV		ASM_CONST(0x00800000)
-
-/* Use paired MAS registers (MAS7||MAS3, etc.)
- */
-#define MMU_FTR_USE_PAIRED_MAS		ASM_CONST(0x01000000)
-
-/* MMU is SLB-based
- */
-#define MMU_FTR_SLB			ASM_CONST(0x02000000)
-
-/* Support 16M large pages
- */
-#define MMU_FTR_16M_PAGE		ASM_CONST(0x04000000)
-
-/* Supports TLBIEL variant
- */
-#define MMU_FTR_TLBIEL			ASM_CONST(0x08000000)
-
-/* Supports tlbies w/o locking
- */
-#define MMU_FTR_LOCKLESS_TLBIE		ASM_CONST(0x10000000)
-
-/* Large pages can be marked CI
- */
-#define MMU_FTR_CI_LARGE_PAGE		ASM_CONST(0x20000000)
-
-/* 1T segments available
- */
-#define MMU_FTR_1T_SEGMENT		ASM_CONST(0x40000000)
-
-/* Doesn't support the B bit (1T segment) in SLBIE
- */
-#define MMU_FTR_NO_SLBIE_B		ASM_CONST(0x80000000)
-
-/* MMU feature bit sets for various CPUs */
-#define MMU_FTRS_DEFAULT_HPTE_ARCH_V2	\
-	MMU_FTR_HPTE_TABLE | MMU_FTR_PPCAS_ARCH_V2
-#define MMU_FTRS_POWER4		MMU_FTRS_DEFAULT_HPTE_ARCH_V2
-#define MMU_FTRS_PPC970		MMU_FTRS_POWER4
-#define MMU_FTRS_POWER5		MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
-#define MMU_FTRS_POWER6		MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
-#define MMU_FTRS_POWER7		MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
-#define MMU_FTRS_CELL		MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
-				MMU_FTR_CI_LARGE_PAGE
-#define MMU_FTRS_PA6T		MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
-				MMU_FTR_CI_LARGE_PAGE | MMU_FTR_NO_SLBIE_B
-#define MMU_FTRS_A2		MMU_FTR_TYPE_3E | MMU_FTR_USE_TLBILX | \
-				MMU_FTR_USE_TLBIVAX_BCAST | \
-				MMU_FTR_LOCK_BCAST_INVAL | \
-				MMU_FTR_USE_TLBRSRV | \
-				MMU_FTR_USE_PAIRED_MAS | \
-				MMU_FTR_TLBIEL | \
-				MMU_FTR_16M_PAGE
-#ifndef __ASSEMBLY__
-#include <asm/cputable.h>
-
-#ifdef CONFIG_PPC_FSL_BOOK3E
-#include <asm/percpu.h>
-DECLARE_PER_CPU(int, next_tlbcam_idx);
-#endif
-
-static inline int mmu_has_feature(unsigned long feature)
-{
-	return (cur_cpu_spec->mmu_features & feature);
-}
-
-static inline void mmu_clear_feature(unsigned long feature)
-{
-	cur_cpu_spec->mmu_features &= ~feature;
-}
-
-extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup;
-
-/* MMU initialization */
-extern void early_init_mmu(void);
-extern void early_init_mmu_secondary(void);
-
-extern void setup_initial_memory_limit(phys_addr_t first_memblock_base,
-				       phys_addr_t first_memblock_size);
-
-#ifdef CONFIG_PPC64
-/* This is our real memory area size on ppc64 server, on embedded, we
- * make it match the size our of bolted TLB area
- */
-extern u64 ppc64_rma_size;
-#endif /* CONFIG_PPC64 */
-
-#endif /* !__ASSEMBLY__ */
-
-/* The kernel use the constants below to index in the page sizes array.
- * The use of fixed constants for this purpose is better for performances
- * of the low level hash refill handlers.
- *
- * A non supported page size has a "shift" field set to 0
- *
- * Any new page size being implemented can get a new entry in here. Whether
- * the kernel will use it or not is a different matter though. The actual page
- * size used by hugetlbfs is not defined here and may be made variable
- *
- * Note: This array ended up being a false good idea as it's growing to the
- * point where I wonder if we should replace it with something different,
- * to think about, feedback welcome. --BenH.
- */
-
-/* There are #define as they have to be used in assembly
- *
- * WARNING: If you change this list, make sure to update the array of
- * names currently in arch/powerpc/mm/hugetlbpage.c or bad things will
- * happen
- */
-#define MMU_PAGE_4K	0
-#define MMU_PAGE_16K	1
-#define MMU_PAGE_64K	2
-#define MMU_PAGE_64K_AP	3	/* "Admixed pages" (hash64 only) */
-#define MMU_PAGE_256K	4
-#define MMU_PAGE_1M	5
-#define MMU_PAGE_4M	6
-#define MMU_PAGE_8M	7
-#define MMU_PAGE_16M	8
-#define MMU_PAGE_64M	9
-#define MMU_PAGE_256M	10
-#define MMU_PAGE_1G	11
-#define MMU_PAGE_16G	12
-#define MMU_PAGE_64G	13
-
-#define MMU_PAGE_COUNT	14
-
-#if defined(CONFIG_PPC_STD_MMU_64)
-/* 64-bit classic hash table MMU */
-#  include <asm/mmu-hash64.h>
-#elif defined(CONFIG_PPC_STD_MMU_32)
-/* 32-bit classic hash table MMU */
-#  include <asm/mmu-hash32.h>
-#elif defined(CONFIG_40x)
-/* 40x-style software loaded TLB */
-#  include <asm/mmu-40x.h>
-#elif defined(CONFIG_44x)
-/* 44x-style software loaded TLB */
-#  include <asm/mmu-44x.h>
-#elif defined(CONFIG_PPC_BOOK3E_MMU)
-/* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */
-#  include <asm/mmu-book3e.h>
-#elif defined (CONFIG_PPC_8xx)
-/* Motorola/Freescale 8xx software loaded TLB */
-#  include <asm/mmu-8xx.h>
-#endif
-
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_MMU_H_ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/mmu_context.h b/ANDROID_3.4.5/arch/powerpc/include/asm/mmu_context.h
deleted file mode 100644
index a73668a5..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/mmu_context.h
+++ /dev/null
@@ -1,117 +0,0 @@
-#ifndef __ASM_POWERPC_MMU_CONTEXT_H
-#define __ASM_POWERPC_MMU_CONTEXT_H
-#ifdef __KERNEL__
-
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/sched.h>
-#include <linux/spinlock.h>
-#include <asm/mmu.h>	
-#include <asm/cputable.h>
-#include <asm-generic/mm_hooks.h>
-#include <asm/cputhreads.h>
-
-/*
- * Most if the context management is out of line
- */
-extern int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
-extern void destroy_context(struct mm_struct *mm);
-
-extern void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next);
-extern void switch_stab(struct task_struct *tsk, struct mm_struct *mm);
-extern void switch_slb(struct task_struct *tsk, struct mm_struct *mm);
-extern void set_context(unsigned long id, pgd_t *pgd);
-
-#ifdef CONFIG_PPC_BOOK3S_64
-extern int __init_new_context(void);
-extern void __destroy_context(int context_id);
-static inline void mmu_context_init(void) { }
-#else
-extern unsigned long __init_new_context(void);
-extern void __destroy_context(unsigned long context_id);
-extern void mmu_context_init(void);
-#endif
-
-extern void switch_cop(struct mm_struct *next);
-extern int use_cop(unsigned long acop, struct mm_struct *mm);
-extern void drop_cop(unsigned long acop, struct mm_struct *mm);
-
-/*
- * switch_mm is the entry point called from the architecture independent
- * code in kernel/sched.c
- */
-static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
-			     struct task_struct *tsk)
-{
-	/* Mark this context has been used on the new CPU */
-	cpumask_set_cpu(smp_processor_id(), mm_cpumask(next));
-
-	/* 32-bit keeps track of the current PGDIR in the thread struct */
-#ifdef CONFIG_PPC32
-	tsk->thread.pgdir = next->pgd;
-#endif /* CONFIG_PPC32 */
-
-	/* 64-bit Book3E keeps track of current PGD in the PACA */
-#ifdef CONFIG_PPC_BOOK3E_64
-	get_paca()->pgd = next->pgd;
-#endif
-	/* Nothing else to do if we aren't actually switching */
-	if (prev == next)
-		return;
-
-#ifdef CONFIG_PPC_ICSWX
-	/* Switch coprocessor context only if prev or next uses a coprocessor */
-	if (prev->context.acop || next->context.acop)
-		switch_cop(next);
-#endif /* CONFIG_PPC_ICSWX */
-
-	/* We must stop all altivec streams before changing the HW
-	 * context
-	 */
-#ifdef CONFIG_ALTIVEC
-	if (cpu_has_feature(CPU_FTR_ALTIVEC))
-		asm volatile ("dssall");
-#endif /* CONFIG_ALTIVEC */
-
-	/* The actual HW switching method differs between the various
-	 * sub architectures.
-	 */
-#ifdef CONFIG_PPC_STD_MMU_64
-	if (mmu_has_feature(MMU_FTR_SLB))
-		switch_slb(tsk, next);
-	else
-		switch_stab(tsk, next);
-#else
-	/* Out of line for now */
-	switch_mmu_context(prev, next);
-#endif
-
-}
-
-#define deactivate_mm(tsk,mm)	do { } while (0)
-
-/*
- * After we have set current->mm to a new value, this activates
- * the context for the new mm so we see the new mappings.
- */
-static inline void activate_mm(struct mm_struct *prev, struct mm_struct *next)
-{
-	unsigned long flags;
-
-	local_irq_save(flags);
-	switch_mm(prev, next, current);
-	local_irq_restore(flags);
-}
-
-/* We don't currently use enter_lazy_tlb() for anything */
-static inline void enter_lazy_tlb(struct mm_struct *mm,
-				  struct task_struct *tsk)
-{
-	/* 64-bit Book3E keeps track of current PGD in the PACA */
-#ifdef CONFIG_PPC_BOOK3E_64
-	get_paca()->pgd = NULL;
-#endif
-}
-
-#endif /* __KERNEL__ */
-#endif /* __ASM_POWERPC_MMU_CONTEXT_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/mmzone.h b/ANDROID_3.4.5/arch/powerpc/include/asm/mmzone.h
deleted file mode 100644
index 7b589178..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/mmzone.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Written by Kanoj Sarcar (kanoj@sgi.com) Aug 99
- *
- * PowerPC64 port:
- * Copyright (C) 2002 Anton Blanchard, IBM Corp.
- */
-#ifndef _ASM_MMZONE_H_
-#define _ASM_MMZONE_H_
-#ifdef __KERNEL__
-
-#include <linux/cpumask.h>
-
-/*
- * generic non-linear memory support:
- *
- * 1) we will not split memory into more chunks than will fit into the
- *    flags field of the struct page
- */
-
-#ifdef CONFIG_NEED_MULTIPLE_NODES
-
-extern struct pglist_data *node_data[];
-/*
- * Return a pointer to the node data for node n.
- */
-#define NODE_DATA(nid)		(node_data[nid])
-
-/*
- * Following are specific to this numa platform.
- */
-
-extern int numa_cpu_lookup_table[];
-extern cpumask_var_t node_to_cpumask_map[];
-#ifdef CONFIG_MEMORY_HOTPLUG
-extern unsigned long max_pfn;
-u64 memory_hotplug_max(void);
-#else
-#define memory_hotplug_max() memblock_end_of_DRAM()
-#endif
-
-#else
-#define memory_hotplug_max() memblock_end_of_DRAM()
-#endif /* CONFIG_NEED_MULTIPLE_NODES */
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_MMZONE_H_ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/module.h b/ANDROID_3.4.5/arch/powerpc/include/asm/module.h
deleted file mode 100644
index 0192a4ee..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/module.h
+++ /dev/null
@@ -1,96 +0,0 @@
-#ifndef _ASM_POWERPC_MODULE_H
-#define _ASM_POWERPC_MODULE_H
-#ifdef __KERNEL__
-
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/list.h>
-#include <asm/bug.h>
-
-
-#ifndef __powerpc64__
-/*
- * Thanks to Paul M for explaining this.
- *
- * PPC can only do rel jumps += 32MB, and often the kernel and other
- * modules are furthur away than this.  So, we jump to a table of
- * trampolines attached to the module (the Procedure Linkage Table)
- * whenever that happens.
- */
-
-struct ppc_plt_entry {
-	/* 16 byte jump instruction sequence (4 instructions) */
-	unsigned int jump[4];
-};
-#endif	/* __powerpc64__ */
-
-
-struct mod_arch_specific {
-#ifdef __powerpc64__
-	unsigned int stubs_section;	/* Index of stubs section in module */
-	unsigned int toc_section;	/* What section is the TOC? */
-#ifdef CONFIG_DYNAMIC_FTRACE
-	unsigned long toc;
-	unsigned long tramp;
-#endif
-
-#else /* powerpc64 */
-	/* Indices of PLT sections within module. */
-	unsigned int core_plt_section;
-	unsigned int init_plt_section;
-#ifdef CONFIG_DYNAMIC_FTRACE
-	unsigned long tramp;
-#endif
-#endif /* powerpc64 */
-
-	/* List of BUG addresses, source line numbers and filenames */
-	struct list_head bug_list;
-	struct bug_entry *bug_table;
-	unsigned int num_bugs;
-};
-
-/*
- * Select ELF headers.
- * Make empty section for module_frob_arch_sections to expand.
- */
-
-#ifdef __powerpc64__
-#    define Elf_Shdr	Elf64_Shdr
-#    define Elf_Sym	Elf64_Sym
-#    define Elf_Ehdr	Elf64_Ehdr
-#    ifdef MODULE
-	asm(".section .stubs,\"ax\",@nobits; .align 3; .previous");
-#    endif
-#else
-#    define Elf_Shdr	Elf32_Shdr
-#    define Elf_Sym	Elf32_Sym
-#    define Elf_Ehdr	Elf32_Ehdr
-#    ifdef MODULE
-	asm(".section .plt,\"ax\",@nobits; .align 3; .previous");
-	asm(".section .init.plt,\"ax\",@nobits; .align 3; .previous");
-#    endif	/* MODULE */
-#endif
-
-#ifdef CONFIG_DYNAMIC_FTRACE
-#    ifdef MODULE
-	asm(".section .ftrace.tramp,\"ax\",@nobits; .align 3; .previous");
-#    endif	/* MODULE */
-#endif
-
-
-struct exception_table_entry;
-void sort_ex_table(struct exception_table_entry *start,
-		   struct exception_table_entry *finish);
-
-#ifdef CONFIG_MODVERSIONS
-#define ARCH_RELOCATES_KCRCTAB
-
-extern const unsigned long reloc_start[];
-#endif
-#endif /* __KERNEL__ */
-#endif	/* _ASM_POWERPC_MODULE_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/mpc5121.h b/ANDROID_3.4.5/arch/powerpc/include/asm/mpc5121.h
deleted file mode 100644
index 8c0ab2ca..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/mpc5121.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * MPC5121 Prototypes and definitions
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.
- */
-
-#ifndef __ASM_POWERPC_MPC5121_H__
-#define __ASM_POWERPC_MPC5121_H__
-
-/* MPC512x Reset module registers */
-struct mpc512x_reset_module {
-	u32	rcwlr;	/* Reset Configuration Word Low Register */
-	u32	rcwhr;	/* Reset Configuration Word High Register */
-	u32	reserved1;
-	u32	reserved2;
-	u32	rsr;	/* Reset Status Register */
-	u32	rmr;	/* Reset Mode Register */
-	u32	rpr;	/* Reset Protection Register */
-	u32	rcr;	/* Reset Control Register */
-	u32	rcer;	/* Reset Control Enable Register */
-};
-
-/*
- * Clock Control Module
- */
-struct mpc512x_ccm {
-	u32	spmr;	/* System PLL Mode Register */
-	u32	sccr1;	/* System Clock Control Register 1 */
-	u32	sccr2;	/* System Clock Control Register 2 */
-	u32	scfr1;	/* System Clock Frequency Register 1 */
-	u32	scfr2;	/* System Clock Frequency Register 2 */
-	u32	scfr2s;	/* System Clock Frequency Shadow Register 2 */
-	u32	bcr;	/* Bread Crumb Register */
-	u32	p0ccr;	/* PSC0 Clock Control Register */
-	u32	p1ccr;	/* PSC1 CCR */
-	u32	p2ccr;	/* PSC2 CCR */
-	u32	p3ccr;	/* PSC3 CCR */
-	u32	p4ccr;	/* PSC4 CCR */
-	u32	p5ccr;	/* PSC5 CCR */
-	u32	p6ccr;	/* PSC6 CCR */
-	u32	p7ccr;	/* PSC7 CCR */
-	u32	p8ccr;	/* PSC8 CCR */
-	u32	p9ccr;	/* PSC9 CCR */
-	u32	p10ccr;	/* PSC10 CCR */
-	u32	p11ccr;	/* PSC11 CCR */
-	u32	spccr;	/* SPDIF Clock Control Register */
-	u32	cccr;	/* CFM Clock Control Register */
-	u32	dccr;	/* DIU Clock Control Register */
-	u32	m1ccr;	/* MSCAN1 CCR */
-	u32	m2ccr;	/* MSCAN2 CCR */
-	u32	m3ccr;	/* MSCAN3 CCR */
-	u32	m4ccr;	/* MSCAN4 CCR */
-	u8	res[0x98]; /* Reserved */
-};
-#endif /* __ASM_POWERPC_MPC5121_H__ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/mpc52xx.h b/ANDROID_3.4.5/arch/powerpc/include/asm/mpc52xx.h
deleted file mode 100644
index 1f41382e..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/mpc52xx.h
+++ /dev/null
@@ -1,363 +0,0 @@
-/*
- * Prototypes, etc. for the Freescale MPC52xx embedded cpu chips
- * May need to be cleaned as the port goes on ...
- *
- * Copyright (C) 2004-2005 Sylvain Munaut <tnt@246tNt.com>
- * Copyright (C) 2003 MontaVista, Software, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#ifndef __ASM_POWERPC_MPC52xx_H__
-#define __ASM_POWERPC_MPC52xx_H__
-
-#ifndef __ASSEMBLY__
-#include <asm/types.h>
-#include <asm/prom.h>
-#include <asm/mpc5xxx.h>
-#endif /* __ASSEMBLY__ */
-
-#include <linux/suspend.h>
-
-/* Variants of the 5200(B) */
-#define MPC5200_SVR		0x80110010
-#define MPC5200_SVR_MASK	0xfffffff0
-#define MPC5200B_SVR		0x80110020
-#define MPC5200B_SVR_MASK	0xfffffff0
-
-/* ======================================================================== */
-/* Structures mapping of some unit register set                             */
-/* ======================================================================== */
-
-#ifndef __ASSEMBLY__
-
-/* Memory Mapping Control */
-struct mpc52xx_mmap_ctl {
-	u32 mbar;		/* MMAP_CTRL + 0x00 */
-
-	u32 cs0_start;		/* MMAP_CTRL + 0x04 */
-	u32 cs0_stop;		/* MMAP_CTRL + 0x08 */
-	u32 cs1_start;		/* MMAP_CTRL + 0x0c */
-	u32 cs1_stop;		/* MMAP_CTRL + 0x10 */
-	u32 cs2_start;		/* MMAP_CTRL + 0x14 */
-	u32 cs2_stop;		/* MMAP_CTRL + 0x18 */
-	u32 cs3_start;		/* MMAP_CTRL + 0x1c */
-	u32 cs3_stop;		/* MMAP_CTRL + 0x20 */
-	u32 cs4_start;		/* MMAP_CTRL + 0x24 */
-	u32 cs4_stop;		/* MMAP_CTRL + 0x28 */
-	u32 cs5_start;		/* MMAP_CTRL + 0x2c */
-	u32 cs5_stop;		/* MMAP_CTRL + 0x30 */
-
-	u32 sdram0;		/* MMAP_CTRL + 0x34 */
-	u32 sdram1;		/* MMAP_CTRL + 0X38 */
-
-	u32 reserved[4];	/* MMAP_CTRL + 0x3c .. 0x48 */
-
-	u32 boot_start;		/* MMAP_CTRL + 0x4c */
-	u32 boot_stop;		/* MMAP_CTRL + 0x50 */
-
-	u32 ipbi_ws_ctrl;	/* MMAP_CTRL + 0x54 */
-
-	u32 cs6_start;		/* MMAP_CTRL + 0x58 */
-	u32 cs6_stop;		/* MMAP_CTRL + 0x5c */
-	u32 cs7_start;		/* MMAP_CTRL + 0x60 */
-	u32 cs7_stop;		/* MMAP_CTRL + 0x64 */
-};
-
-/* SDRAM control */
-struct mpc52xx_sdram {
-	u32 mode;		/* SDRAM + 0x00 */
-	u32 ctrl;		/* SDRAM + 0x04 */
-	u32 config1;		/* SDRAM + 0x08 */
-	u32 config2;		/* SDRAM + 0x0c */
-};
-
-/* SDMA */
-struct mpc52xx_sdma {
-	u32 taskBar;		/* SDMA + 0x00 */
-	u32 currentPointer;	/* SDMA + 0x04 */
-	u32 endPointer;		/* SDMA + 0x08 */
-	u32 variablePointer;	/* SDMA + 0x0c */
-
-	u8 IntVect1;		/* SDMA + 0x10 */
-	u8 IntVect2;		/* SDMA + 0x11 */
-	u16 PtdCntrl;		/* SDMA + 0x12 */
-
-	u32 IntPend;		/* SDMA + 0x14 */
-	u32 IntMask;		/* SDMA + 0x18 */
-
-	u16 tcr[16];		/* SDMA + 0x1c .. 0x3a */
-
-	u8 ipr[32];		/* SDMA + 0x3c .. 0x5b */
-
-	u32 cReqSelect;		/* SDMA + 0x5c */
-	u32 task_size0;		/* SDMA + 0x60 */
-	u32 task_size1;		/* SDMA + 0x64 */
-	u32 MDEDebug;		/* SDMA + 0x68 */
-	u32 ADSDebug;		/* SDMA + 0x6c */
-	u32 Value1;		/* SDMA + 0x70 */
-	u32 Value2;		/* SDMA + 0x74 */
-	u32 Control;		/* SDMA + 0x78 */
-	u32 Status;		/* SDMA + 0x7c */
-	u32 PTDDebug;		/* SDMA + 0x80 */
-};
-
-/* GPT */
-struct mpc52xx_gpt {
-	u32 mode;		/* GPTx + 0x00 */
-	u32 count;		/* GPTx + 0x04 */
-	u32 pwm;		/* GPTx + 0x08 */
-	u32 status;		/* GPTx + 0X0c */
-};
-
-/* GPIO */
-struct mpc52xx_gpio {
-	u32 port_config;	/* GPIO + 0x00 */
-	u32 simple_gpioe;	/* GPIO + 0x04 */
-	u32 simple_ode;		/* GPIO + 0x08 */
-	u32 simple_ddr;		/* GPIO + 0x0c */
-	u32 simple_dvo;		/* GPIO + 0x10 */
-	u32 simple_ival;	/* GPIO + 0x14 */
-	u8 outo_gpioe;		/* GPIO + 0x18 */
-	u8 reserved1[3];	/* GPIO + 0x19 */
-	u8 outo_dvo;		/* GPIO + 0x1c */
-	u8 reserved2[3];	/* GPIO + 0x1d */
-	u8 sint_gpioe;		/* GPIO + 0x20 */
-	u8 reserved3[3];	/* GPIO + 0x21 */
-	u8 sint_ode;		/* GPIO + 0x24 */
-	u8 reserved4[3];	/* GPIO + 0x25 */
-	u8 sint_ddr;		/* GPIO + 0x28 */
-	u8 reserved5[3];	/* GPIO + 0x29 */
-	u8 sint_dvo;		/* GPIO + 0x2c */
-	u8 reserved6[3];	/* GPIO + 0x2d */
-	u8 sint_inten;		/* GPIO + 0x30 */
-	u8 reserved7[3];	/* GPIO + 0x31 */
-	u16 sint_itype;		/* GPIO + 0x34 */
-	u16 reserved8;		/* GPIO + 0x36 */
-	u8 gpio_control;	/* GPIO + 0x38 */
-	u8 reserved9[3];	/* GPIO + 0x39 */
-	u8 sint_istat;		/* GPIO + 0x3c */
-	u8 sint_ival;		/* GPIO + 0x3d */
-	u8 bus_errs;		/* GPIO + 0x3e */
-	u8 reserved10;		/* GPIO + 0x3f */
-};
-
-#define MPC52xx_GPIO_PSC_CONFIG_UART_WITHOUT_CD	4
-#define MPC52xx_GPIO_PSC_CONFIG_UART_WITH_CD	5
-#define MPC52xx_GPIO_PCI_DIS			(1<<15)
-
-/* GPIO with WakeUp*/
-struct mpc52xx_gpio_wkup {
-	u8 wkup_gpioe;		/* GPIO_WKUP + 0x00 */
-	u8 reserved1[3];	/* GPIO_WKUP + 0x03 */
-	u8 wkup_ode;		/* GPIO_WKUP + 0x04 */
-	u8 reserved2[3];	/* GPIO_WKUP + 0x05 */
-	u8 wkup_ddr;		/* GPIO_WKUP + 0x08 */
-	u8 reserved3[3];	/* GPIO_WKUP + 0x09 */
-	u8 wkup_dvo;		/* GPIO_WKUP + 0x0C */
-	u8 reserved4[3];	/* GPIO_WKUP + 0x0D */
-	u8 wkup_inten;		/* GPIO_WKUP + 0x10 */
-	u8 reserved5[3];	/* GPIO_WKUP + 0x11 */
-	u8 wkup_iinten;		/* GPIO_WKUP + 0x14 */
-	u8 reserved6[3];	/* GPIO_WKUP + 0x15 */
-	u16 wkup_itype;		/* GPIO_WKUP + 0x18 */
-	u8 reserved7[2];	/* GPIO_WKUP + 0x1A */
-	u8 wkup_maste;		/* GPIO_WKUP + 0x1C */
-	u8 reserved8[3];	/* GPIO_WKUP + 0x1D */
-	u8 wkup_ival;		/* GPIO_WKUP + 0x20 */
-	u8 reserved9[3];	/* GPIO_WKUP + 0x21 */
-	u8 wkup_istat;		/* GPIO_WKUP + 0x24 */
-	u8 reserved10[3];	/* GPIO_WKUP + 0x25 */
-};
-
-/* XLB Bus control */
-struct mpc52xx_xlb {
-	u8 reserved[0x40];
-	u32 config;		/* XLB + 0x40 */
-	u32 version;		/* XLB + 0x44 */
-	u32 status;		/* XLB + 0x48 */
-	u32 int_enable;		/* XLB + 0x4c */
-	u32 addr_capture;	/* XLB + 0x50 */
-	u32 bus_sig_capture;	/* XLB + 0x54 */
-	u32 addr_timeout;	/* XLB + 0x58 */
-	u32 data_timeout;	/* XLB + 0x5c */
-	u32 bus_act_timeout;	/* XLB + 0x60 */
-	u32 master_pri_enable;	/* XLB + 0x64 */
-	u32 master_priority;	/* XLB + 0x68 */
-	u32 base_address;	/* XLB + 0x6c */
-	u32 snoop_window;	/* XLB + 0x70 */
-};
-
-#define MPC52xx_XLB_CFG_PLDIS		(1 << 31)
-#define MPC52xx_XLB_CFG_SNOOP		(1 << 15)
-
-/* Clock Distribution control */
-struct mpc52xx_cdm {
-	u32 jtag_id;		/* CDM + 0x00  reg0 read only */
-	u32 rstcfg;		/* CDM + 0x04  reg1 read only */
-	u32 breadcrumb;		/* CDM + 0x08  reg2 */
-
-	u8 mem_clk_sel;		/* CDM + 0x0c  reg3 byte0 */
-	u8 xlb_clk_sel;		/* CDM + 0x0d  reg3 byte1 read only */
-	u8 ipb_clk_sel;		/* CDM + 0x0e  reg3 byte2 */
-	u8 pci_clk_sel;		/* CDM + 0x0f  reg3 byte3 */
-
-	u8 ext_48mhz_en;	/* CDM + 0x10  reg4 byte0 */
-	u8 fd_enable;		/* CDM + 0x11  reg4 byte1 */
-	u16 fd_counters;	/* CDM + 0x12  reg4 byte2,3 */
-
-	u32 clk_enables;	/* CDM + 0x14  reg5 */
-
-	u8 osc_disable;		/* CDM + 0x18  reg6 byte0 */
-	u8 reserved0[3];	/* CDM + 0x19  reg6 byte1,2,3 */
-
-	u8 ccs_sleep_enable;	/* CDM + 0x1c  reg7 byte0 */
-	u8 osc_sleep_enable;	/* CDM + 0x1d  reg7 byte1 */
-	u8 reserved1;		/* CDM + 0x1e  reg7 byte2 */
-	u8 ccs_qreq_test;	/* CDM + 0x1f  reg7 byte3 */
-
-	u8 soft_reset;		/* CDM + 0x20  u8 byte0 */
-	u8 no_ckstp;		/* CDM + 0x21  u8 byte0 */
-	u8 reserved2[2];	/* CDM + 0x22  u8 byte1,2,3 */
-
-	u8 pll_lock;		/* CDM + 0x24  reg9 byte0 */
-	u8 pll_looselock;	/* CDM + 0x25  reg9 byte1 */
-	u8 pll_sm_lockwin;	/* CDM + 0x26  reg9 byte2 */
-	u8 reserved3;		/* CDM + 0x27  reg9 byte3 */
-
-	u16 reserved4;		/* CDM + 0x28  reg10 byte0,1 */
-	u16 mclken_div_psc1;	/* CDM + 0x2a  reg10 byte2,3 */
-
-	u16 reserved5;		/* CDM + 0x2c  reg11 byte0,1 */
-	u16 mclken_div_psc2;	/* CDM + 0x2e  reg11 byte2,3 */
-
-	u16 reserved6;		/* CDM + 0x30  reg12 byte0,1 */
-	u16 mclken_div_psc3;	/* CDM + 0x32  reg12 byte2,3 */
-
-	u16 reserved7;		/* CDM + 0x34  reg13 byte0,1 */
-	u16 mclken_div_psc6;	/* CDM + 0x36  reg13 byte2,3 */
-};
-
-/* Interrupt controller Register set */
-struct mpc52xx_intr {
-	u32 per_mask;		/* INTR + 0x00 */
-	u32 per_pri1;		/* INTR + 0x04 */
-	u32 per_pri2;		/* INTR + 0x08 */
-	u32 per_pri3;		/* INTR + 0x0c */
-	u32 ctrl;		/* INTR + 0x10 */
-	u32 main_mask;		/* INTR + 0x14 */
-	u32 main_pri1;		/* INTR + 0x18 */
-	u32 main_pri2;		/* INTR + 0x1c */
-	u32 reserved1;		/* INTR + 0x20 */
-	u32 enc_status;		/* INTR + 0x24 */
-	u32 crit_status;	/* INTR + 0x28 */
-	u32 main_status;	/* INTR + 0x2c */
-	u32 per_status;		/* INTR + 0x30 */
-	u32 reserved2;		/* INTR + 0x34 */
-	u32 per_error;		/* INTR + 0x38 */
-};
-
-#endif /* __ASSEMBLY__ */
-
-
-/* ========================================================================= */
-/* Prototypes for MPC52xx sysdev                                             */
-/* ========================================================================= */
-
-#ifndef __ASSEMBLY__
-
-/* mpc52xx_common.c */
-extern void mpc5200_setup_xlb_arbiter(void);
-extern void mpc52xx_declare_of_platform_devices(void);
-extern int mpc5200_psc_ac97_gpio_reset(int psc_number);
-extern void mpc52xx_map_common_devices(void);
-extern int mpc52xx_set_psc_clkdiv(int psc_id, int clkdiv);
-extern unsigned int mpc52xx_get_xtal_freq(struct device_node *node);
-extern void mpc52xx_restart(char *cmd);
-
-/* mpc52xx_gpt.c */
-struct mpc52xx_gpt_priv;
-extern struct mpc52xx_gpt_priv *mpc52xx_gpt_from_irq(int irq);
-extern int mpc52xx_gpt_start_timer(struct mpc52xx_gpt_priv *gpt, u64 period,
-                            int continuous);
-extern u64 mpc52xx_gpt_timer_period(struct mpc52xx_gpt_priv *gpt);
-extern int mpc52xx_gpt_stop_timer(struct mpc52xx_gpt_priv *gpt);
-
-/* mpc52xx_lpbfifo.c */
-#define MPC52XX_LPBFIFO_FLAG_READ		(0)
-#define MPC52XX_LPBFIFO_FLAG_WRITE		(1<<0)
-#define MPC52XX_LPBFIFO_FLAG_NO_INCREMENT	(1<<1)
-#define MPC52XX_LPBFIFO_FLAG_NO_DMA		(1<<2)
-#define MPC52XX_LPBFIFO_FLAG_POLL_DMA		(1<<3)
-
-struct mpc52xx_lpbfifo_request {
-	struct list_head list;
-
-	/* localplus bus address */
-	unsigned int cs;
-	size_t offset;
-
-	/* Memory address */
-	void *data;
-	phys_addr_t data_phys;
-
-	/* Details of transfer */
-	size_t size;
-	size_t pos;	/* current position of transfer */
-	int flags;
-
-	/* What to do when finished */
-	void (*callback)(struct mpc52xx_lpbfifo_request *);
-
-	void *priv;		/* Driver private data */
-
-	/* statistics */
-	int irq_count;
-	int irq_ticks;
-	u8 last_byte;
-	int buffer_not_done_cnt;
-};
-
-extern int mpc52xx_lpbfifo_submit(struct mpc52xx_lpbfifo_request *req);
-extern void mpc52xx_lpbfifo_abort(struct mpc52xx_lpbfifo_request *req);
-extern void mpc52xx_lpbfifo_poll(void);
-
-/* mpc52xx_pic.c */
-extern void mpc52xx_init_irq(void);
-extern unsigned int mpc52xx_get_irq(void);
-
-/* mpc52xx_pci.c */
-#ifdef CONFIG_PCI
-extern int __init mpc52xx_add_bridge(struct device_node *node);
-extern void __init mpc52xx_setup_pci(void);
-#else
-static inline void mpc52xx_setup_pci(void) { }
-#endif
-
-#endif /* __ASSEMBLY__ */
-
-#ifdef CONFIG_PM
-struct mpc52xx_suspend {
-	void (*board_suspend_prepare)(void __iomem *mbar);
-	void (*board_resume_finish)(void __iomem *mbar);
-};
-
-extern struct mpc52xx_suspend mpc52xx_suspend;
-extern int __init mpc52xx_pm_init(void);
-extern int mpc52xx_set_wakeup_gpio(u8 pin, u8 level);
-
-#ifdef CONFIG_PPC_LITE5200
-extern int __init lite5200_pm_init(void);
-
-/* lite5200 calls mpc5200 suspend functions, so here they are */
-extern int mpc52xx_pm_prepare(void);
-extern int mpc52xx_pm_enter(suspend_state_t);
-extern void mpc52xx_pm_finish(void);
-extern char saved_sram[0x4000]; /* reuse buffer from mpc52xx suspend */
-#endif
-#endif /* CONFIG_PM */
-
-#endif /* __ASM_POWERPC_MPC52xx_H__ */
-
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/mpc52xx_psc.h b/ANDROID_3.4.5/arch/powerpc/include/asm/mpc52xx_psc.h
deleted file mode 100644
index 2966df60..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/mpc52xx_psc.h
+++ /dev/null
@@ -1,302 +0,0 @@
-/*
- * include/asm-ppc/mpc52xx_psc.h
- *
- * Definitions of consts/structs to drive the Freescale MPC52xx OnChip
- * PSCs. Theses are shared between multiple drivers since a PSC can be
- * UART, AC97, IR, I2S, ... So this header is in asm-ppc.
- *
- *
- * Maintainer : Sylvain Munaut <tnt@246tNt.com>
- *
- * Based/Extracted from some header of the 2.4 originally written by
- * Dale Farnsworth <dfarnsworth@mvista.com>
- *
- * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
- * Copyright (C) 2003 MontaVista, Software, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#ifndef __ASM_MPC52xx_PSC_H__
-#define __ASM_MPC52xx_PSC_H__
-
-#include <asm/types.h>
-
-/* Max number of PSCs */
-#ifdef CONFIG_PPC_MPC512x
-#define MPC52xx_PSC_MAXNUM     12
-#else
-#define MPC52xx_PSC_MAXNUM	6
-#endif
-
-/* Programmable Serial Controller (PSC) status register bits */
-#define MPC52xx_PSC_SR_UNEX_RX	0x0001
-#define MPC52xx_PSC_SR_DATA_VAL	0x0002
-#define MPC52xx_PSC_SR_DATA_OVR	0x0004
-#define MPC52xx_PSC_SR_CMDSEND	0x0008
-#define MPC52xx_PSC_SR_CDE	0x0080
-#define MPC52xx_PSC_SR_RXRDY	0x0100
-#define MPC52xx_PSC_SR_RXFULL	0x0200
-#define MPC52xx_PSC_SR_TXRDY	0x0400
-#define MPC52xx_PSC_SR_TXEMP	0x0800
-#define MPC52xx_PSC_SR_OE	0x1000
-#define MPC52xx_PSC_SR_PE	0x2000
-#define MPC52xx_PSC_SR_FE	0x4000
-#define MPC52xx_PSC_SR_RB	0x8000
-
-/* PSC Command values */
-#define MPC52xx_PSC_RX_ENABLE		0x0001
-#define MPC52xx_PSC_RX_DISABLE		0x0002
-#define MPC52xx_PSC_TX_ENABLE		0x0004
-#define MPC52xx_PSC_TX_DISABLE		0x0008
-#define MPC52xx_PSC_SEL_MODE_REG_1	0x0010
-#define MPC52xx_PSC_RST_RX		0x0020
-#define MPC52xx_PSC_RST_TX		0x0030
-#define MPC52xx_PSC_RST_ERR_STAT	0x0040
-#define MPC52xx_PSC_RST_BRK_CHG_INT	0x0050
-#define MPC52xx_PSC_START_BRK		0x0060
-#define MPC52xx_PSC_STOP_BRK		0x0070
-
-/* PSC TxRx FIFO status bits */
-#define MPC52xx_PSC_RXTX_FIFO_ERR	0x0040
-#define MPC52xx_PSC_RXTX_FIFO_UF	0x0020
-#define MPC52xx_PSC_RXTX_FIFO_OF	0x0010
-#define MPC52xx_PSC_RXTX_FIFO_FR	0x0008
-#define MPC52xx_PSC_RXTX_FIFO_FULL	0x0004
-#define MPC52xx_PSC_RXTX_FIFO_ALARM	0x0002
-#define MPC52xx_PSC_RXTX_FIFO_EMPTY	0x0001
-
-/* PSC interrupt status/mask bits */
-#define MPC52xx_PSC_IMR_UNEX_RX_SLOT 0x0001
-#define MPC52xx_PSC_IMR_DATA_VALID	0x0002
-#define MPC52xx_PSC_IMR_DATA_OVR	0x0004
-#define MPC52xx_PSC_IMR_CMD_SEND	0x0008
-#define MPC52xx_PSC_IMR_ERROR		0x0040
-#define MPC52xx_PSC_IMR_DEOF		0x0080
-#define MPC52xx_PSC_IMR_TXRDY		0x0100
-#define MPC52xx_PSC_IMR_RXRDY		0x0200
-#define MPC52xx_PSC_IMR_DB		0x0400
-#define MPC52xx_PSC_IMR_TXEMP		0x0800
-#define MPC52xx_PSC_IMR_ORERR		0x1000
-#define MPC52xx_PSC_IMR_IPC		0x8000
-
-/* PSC input port change bits */
-#define MPC52xx_PSC_CTS			0x01
-#define MPC52xx_PSC_DCD			0x02
-#define MPC52xx_PSC_D_CTS		0x10
-#define MPC52xx_PSC_D_DCD		0x20
-
-/* PSC acr bits */
-#define MPC52xx_PSC_IEC_CTS		0x01
-#define MPC52xx_PSC_IEC_DCD		0x02
-
-/* PSC output port bits */
-#define MPC52xx_PSC_OP_RTS		0x01
-#define MPC52xx_PSC_OP_RES		0x02
-
-/* PSC mode fields */
-#define MPC52xx_PSC_MODE_5_BITS			0x00
-#define MPC52xx_PSC_MODE_6_BITS			0x01
-#define MPC52xx_PSC_MODE_7_BITS			0x02
-#define MPC52xx_PSC_MODE_8_BITS			0x03
-#define MPC52xx_PSC_MODE_BITS_MASK		0x03
-#define MPC52xx_PSC_MODE_PAREVEN		0x00
-#define MPC52xx_PSC_MODE_PARODD			0x04
-#define MPC52xx_PSC_MODE_PARFORCE		0x08
-#define MPC52xx_PSC_MODE_PARNONE		0x10
-#define MPC52xx_PSC_MODE_ERR			0x20
-#define MPC52xx_PSC_MODE_FFULL			0x40
-#define MPC52xx_PSC_MODE_RXRTS			0x80
-
-#define MPC52xx_PSC_MODE_ONE_STOP_5_BITS	0x00
-#define MPC52xx_PSC_MODE_ONE_STOP		0x07
-#define MPC52xx_PSC_MODE_TWO_STOP		0x0f
-#define MPC52xx_PSC_MODE_TXCTS			0x10
-
-#define MPC52xx_PSC_RFNUM_MASK	0x01ff
-
-#define MPC52xx_PSC_SICR_DTS1			(1 << 29)
-#define MPC52xx_PSC_SICR_SHDR			(1 << 28)
-#define MPC52xx_PSC_SICR_SIM_MASK		(0xf << 24)
-#define MPC52xx_PSC_SICR_SIM_UART		(0x0 << 24)
-#define MPC52xx_PSC_SICR_SIM_UART_DCD		(0x8 << 24)
-#define MPC52xx_PSC_SICR_SIM_CODEC_8		(0x1 << 24)
-#define MPC52xx_PSC_SICR_SIM_CODEC_16		(0x2 << 24)
-#define MPC52xx_PSC_SICR_SIM_AC97		(0x3 << 24)
-#define MPC52xx_PSC_SICR_SIM_SIR		(0x8 << 24)
-#define MPC52xx_PSC_SICR_SIM_SIR_DCD		(0xc << 24)
-#define MPC52xx_PSC_SICR_SIM_MIR		(0x5 << 24)
-#define MPC52xx_PSC_SICR_SIM_FIR		(0x6 << 24)
-#define MPC52xx_PSC_SICR_SIM_CODEC_24		(0x7 << 24)
-#define MPC52xx_PSC_SICR_SIM_CODEC_32		(0xf << 24)
-#define MPC52xx_PSC_SICR_ACRB			(0x8 << 24)
-#define MPC52xx_PSC_SICR_AWR			(1 << 30)
-#define MPC52xx_PSC_SICR_GENCLK			(1 << 23)
-#define MPC52xx_PSC_SICR_I2S			(1 << 22)
-#define MPC52xx_PSC_SICR_CLKPOL			(1 << 21)
-#define MPC52xx_PSC_SICR_SYNCPOL		(1 << 20)
-#define MPC52xx_PSC_SICR_CELLSLAVE		(1 << 19)
-#define MPC52xx_PSC_SICR_CELL2XCLK		(1 << 18)
-#define MPC52xx_PSC_SICR_ESAI			(1 << 17)
-#define MPC52xx_PSC_SICR_ENAC97			(1 << 16)
-#define MPC52xx_PSC_SICR_SPI			(1 << 15)
-#define MPC52xx_PSC_SICR_MSTR			(1 << 14)
-#define MPC52xx_PSC_SICR_CPOL			(1 << 13)
-#define MPC52xx_PSC_SICR_CPHA			(1 << 12)
-#define MPC52xx_PSC_SICR_USEEOF			(1 << 11)
-#define MPC52xx_PSC_SICR_DISABLEEOF		(1 << 10)
-
-/* Structure of the hardware registers */
-struct mpc52xx_psc {
-	u8		mode;		/* PSC + 0x00 */
-	u8		reserved0[3];
-	union {				/* PSC + 0x04 */
-		u16	status;
-		u16	clock_select;
-	} sr_csr;
-#define mpc52xx_psc_status	sr_csr.status
-#define mpc52xx_psc_clock_select sr_csr.clock_select
-	u16		reserved1;
-	u8		command;	/* PSC + 0x08 */
-	u8		reserved2[3];
-	union {				/* PSC + 0x0c */
-		u8	buffer_8;
-		u16	buffer_16;
-		u32	buffer_32;
-	} buffer;
-#define mpc52xx_psc_buffer_8	buffer.buffer_8
-#define mpc52xx_psc_buffer_16	buffer.buffer_16
-#define mpc52xx_psc_buffer_32	buffer.buffer_32
-	union {				/* PSC + 0x10 */
-		u8	ipcr;
-		u8	acr;
-	} ipcr_acr;
-#define mpc52xx_psc_ipcr	ipcr_acr.ipcr
-#define mpc52xx_psc_acr		ipcr_acr.acr
-	u8		reserved3[3];
-	union {				/* PSC + 0x14 */
-		u16	isr;
-		u16	imr;
-	} isr_imr;
-#define mpc52xx_psc_isr		isr_imr.isr
-#define mpc52xx_psc_imr		isr_imr.imr
-	u16		reserved4;
-	u8		ctur;		/* PSC + 0x18 */
-	u8		reserved5[3];
-	u8		ctlr;		/* PSC + 0x1c */
-	u8		reserved6[3];
-	/* BitClkDiv field of CCR is byte swapped in
-	 * the hardware for mpc5200/b compatibility */
-	u32		ccr;		/* PSC + 0x20 */
-	u32		ac97_slots;	/* PSC + 0x24 */
-	u32		ac97_cmd;	/* PSC + 0x28 */
-	u32		ac97_data;	/* PSC + 0x2c */
-	u8		ivr;		/* PSC + 0x30 */
-	u8		reserved8[3];
-	u8		ip;		/* PSC + 0x34 */
-	u8		reserved9[3];
-	u8		op1;		/* PSC + 0x38 */
-	u8		reserved10[3];
-	u8		op0;		/* PSC + 0x3c */
-	u8		reserved11[3];
-	u32		sicr;		/* PSC + 0x40 */
-	u8		ircr1;		/* PSC + 0x44 */
-	u8		reserved13[3];
-	u8		ircr2;		/* PSC + 0x44 */
-	u8		reserved14[3];
-	u8		irsdr;		/* PSC + 0x4c */
-	u8		reserved15[3];
-	u8		irmdr;		/* PSC + 0x50 */
-	u8		reserved16[3];
-	u8		irfdr;		/* PSC + 0x54 */
-	u8		reserved17[3];
-};
-
-struct mpc52xx_psc_fifo {
-	u16		rfnum;		/* PSC + 0x58 */
-	u16		reserved18;
-	u16		tfnum;		/* PSC + 0x5c */
-	u16		reserved19;
-	u32		rfdata;		/* PSC + 0x60 */
-	u16		rfstat;		/* PSC + 0x64 */
-	u16		reserved20;
-	u8		rfcntl;		/* PSC + 0x68 */
-	u8		reserved21[5];
-	u16		rfalarm;	/* PSC + 0x6e */
-	u16		reserved22;
-	u16		rfrptr;		/* PSC + 0x72 */
-	u16		reserved23;
-	u16		rfwptr;		/* PSC + 0x76 */
-	u16		reserved24;
-	u16		rflrfptr;	/* PSC + 0x7a */
-	u16		reserved25;
-	u16		rflwfptr;	/* PSC + 0x7e */
-	u32		tfdata;		/* PSC + 0x80 */
-	u16		tfstat;		/* PSC + 0x84 */
-	u16		reserved26;
-	u8		tfcntl;		/* PSC + 0x88 */
-	u8		reserved27[5];
-	u16		tfalarm;	/* PSC + 0x8e */
-	u16		reserved28;
-	u16		tfrptr;		/* PSC + 0x92 */
-	u16		reserved29;
-	u16		tfwptr;		/* PSC + 0x96 */
-	u16		reserved30;
-	u16		tflrfptr;	/* PSC + 0x9a */
-	u16		reserved31;
-	u16		tflwfptr;	/* PSC + 0x9e */
-};
-
-#define MPC512x_PSC_FIFO_EOF		0x100
-#define MPC512x_PSC_FIFO_RESET_SLICE	0x80
-#define MPC512x_PSC_FIFO_ENABLE_SLICE	0x01
-#define MPC512x_PSC_FIFO_ENABLE_DMA	0x04
-
-#define MPC512x_PSC_FIFO_EMPTY		0x1
-#define MPC512x_PSC_FIFO_FULL		0x2
-#define MPC512x_PSC_FIFO_ALARM		0x4
-#define MPC512x_PSC_FIFO_URERR		0x8
-#define MPC512x_PSC_FIFO_ORERR		0x01
-#define MPC512x_PSC_FIFO_MEMERROR	0x02
-
-struct mpc512x_psc_fifo {
-	u32		reserved1[10];
-	u32		txcmd;		/* PSC + 0x80 */
-	u32		txalarm;	/* PSC + 0x84 */
-	u32		txsr;		/* PSC + 0x88 */
-	u32		txisr;		/* PSC + 0x8c */
-	u32		tximr;		/* PSC + 0x90 */
-	u32		txcnt;		/* PSC + 0x94 */
-	u32		txptr;		/* PSC + 0x98 */
-	u32		txsz;		/* PSC + 0x9c */
-	u32		reserved2[7];
-	union {
-		u8	txdata_8;
-		u16	txdata_16;
-		u32	txdata_32;
-	} txdata; 			/* PSC + 0xbc */
-#define txdata_8 txdata.txdata_8
-#define txdata_16 txdata.txdata_16
-#define txdata_32 txdata.txdata_32
-	u32		rxcmd;		/* PSC + 0xc0 */
-	u32		rxalarm;	/* PSC + 0xc4 */
-	u32		rxsr;		/* PSC + 0xc8 */
-	u32		rxisr;		/* PSC + 0xcc */
-	u32		rximr;		/* PSC + 0xd0 */
-	u32		rxcnt;		/* PSC + 0xd4 */
-	u32		rxptr;		/* PSC + 0xd8 */
-	u32		rxsz;		/* PSC + 0xdc */
-	u32		reserved3[7];
-	union {
-		u8	rxdata_8;
-		u16	rxdata_16;
-		u32	rxdata_32;
-	} rxdata; 			/* PSC + 0xfc */
-#define rxdata_8 rxdata.rxdata_8
-#define rxdata_16 rxdata.rxdata_16
-#define rxdata_32 rxdata.rxdata_32
-};
-
-#endif  /* __ASM_MPC52xx_PSC_H__ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/mpc5xxx.h b/ANDROID_3.4.5/arch/powerpc/include/asm/mpc5xxx.h
deleted file mode 100644
index 5ce9c5fa..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/mpc5xxx.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
- *
- * Author: John Rigby, <jrigby@freescale.com>, Friday Apr 13 2007
- *
- * Description:
- * MPC5xxx Prototypes and definitions
- *
- * This is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-
-#ifndef __ASM_POWERPC_MPC5xxx_H__
-#define __ASM_POWERPC_MPC5xxx_H__
-
-extern unsigned long mpc5xxx_get_bus_frequency(struct device_node *node);
-
-#endif /* __ASM_POWERPC_MPC5xxx_H__ */
-
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/mpc6xx.h b/ANDROID_3.4.5/arch/powerpc/include/asm/mpc6xx.h
deleted file mode 100644
index effc2291..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/mpc6xx.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __ASM_POWERPC_MPC6xx_H
-#define __ASM_POWERPC_MPC6xx_H
-
-void mpc6xx_enter_standby(void);
-
-#endif
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/mpc8260.h b/ANDROID_3.4.5/arch/powerpc/include/asm/mpc8260.h
deleted file mode 100644
index 03317e1e..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/mpc8260.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Since there are many different boards and no standard configuration,
- * we have a unique include file for each.  Rather than change every
- * file that has to include MPC8260 configuration, they all include
- * this one and the configuration switching is done here.
- */
-#ifdef __KERNEL__
-#ifndef __ASM_POWERPC_MPC8260_H__
-#define __ASM_POWERPC_MPC8260_H__
-
-#define MPC82XX_BCR_PLDP 0x00800000 /* Pipeline Maximum Depth */
-
-#ifdef CONFIG_8260
-
-#if defined(CONFIG_PQ2ADS) || defined (CONFIG_PQ2FADS)
-#include <platforms/82xx/pq2ads.h>
-#endif
-
-#ifdef CONFIG_PCI_8260
-#include <platforms/82xx/m82xx_pci.h>
-#endif
-
-#endif /* CONFIG_8260 */
-#endif /* !__ASM_POWERPC_MPC8260_H__ */
-#endif /* __KERNEL__ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/mpc8xx.h b/ANDROID_3.4.5/arch/powerpc/include/asm/mpc8xx.h
deleted file mode 100644
index 98f3c4f1..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/mpc8xx.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* This is the single file included by all MPC8xx build options.
- * Since there are many different boards and no standard configuration,
- * we have a unique include file for each.  Rather than change every
- * file that has to include MPC8xx configuration, they all include
- * this one and the configuration switching is done here.
- */
-#ifndef __CONFIG_8xx_DEFS
-#define __CONFIG_8xx_DEFS
-
-extern struct mpc8xx_pcmcia_ops m8xx_pcmcia_ops;
-
-#endif /* __CONFIG_8xx_DEFS */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/mpic.h b/ANDROID_3.4.5/arch/powerpc/include/asm/mpic.h
deleted file mode 100644
index c9f698a9..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/mpic.h
+++ /dev/null
@@ -1,475 +0,0 @@
-#ifndef _ASM_POWERPC_MPIC_H
-#define _ASM_POWERPC_MPIC_H
-#ifdef __KERNEL__
-
-#include <linux/irq.h>
-#include <asm/dcr.h>
-#include <asm/msi_bitmap.h>
-
-/*
- * Global registers
- */
-
-#define MPIC_GREG_BASE			0x01000
-
-#define MPIC_GREG_FEATURE_0		0x00000
-#define		MPIC_GREG_FEATURE_LAST_SRC_MASK		0x07ff0000
-#define		MPIC_GREG_FEATURE_LAST_SRC_SHIFT	16
-#define		MPIC_GREG_FEATURE_LAST_CPU_MASK		0x00001f00
-#define		MPIC_GREG_FEATURE_LAST_CPU_SHIFT	8
-#define		MPIC_GREG_FEATURE_VERSION_MASK		0xff
-#define MPIC_GREG_FEATURE_1		0x00010
-#define MPIC_GREG_GLOBAL_CONF_0		0x00020
-#define		MPIC_GREG_GCONF_RESET			0x80000000
-/* On the FSL mpic implementations the Mode field is expand to be
- * 2 bits wide:
- *	0b00 = pass through (interrupts routed to IRQ0)
- *	0b01 = Mixed mode
- *	0b10 = reserved
- *	0b11 = External proxy / coreint
- */
-#define		MPIC_GREG_GCONF_COREINT			0x60000000
-#define		MPIC_GREG_GCONF_8259_PTHROU_DIS		0x20000000
-#define		MPIC_GREG_GCONF_NO_BIAS			0x10000000
-#define		MPIC_GREG_GCONF_BASE_MASK		0x000fffff
-#define		MPIC_GREG_GCONF_MCK			0x08000000
-#define MPIC_GREG_GLOBAL_CONF_1		0x00030
-#define		MPIC_GREG_GLOBAL_CONF_1_SIE		0x08000000
-#define		MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK	0x70000000
-#define		MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(r)	\
-			(((r) << 28) & MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK)
-#define MPIC_GREG_VENDOR_0		0x00040
-#define MPIC_GREG_VENDOR_1		0x00050
-#define MPIC_GREG_VENDOR_2		0x00060
-#define MPIC_GREG_VENDOR_3		0x00070
-#define MPIC_GREG_VENDOR_ID		0x00080
-#define 	MPIC_GREG_VENDOR_ID_STEPPING_MASK	0x00ff0000
-#define 	MPIC_GREG_VENDOR_ID_STEPPING_SHIFT	16
-#define 	MPIC_GREG_VENDOR_ID_DEVICE_ID_MASK	0x0000ff00
-#define 	MPIC_GREG_VENDOR_ID_DEVICE_ID_SHIFT	8
-#define 	MPIC_GREG_VENDOR_ID_VENDOR_ID_MASK	0x000000ff
-#define MPIC_GREG_PROCESSOR_INIT	0x00090
-#define MPIC_GREG_IPI_VECTOR_PRI_0	0x000a0
-#define MPIC_GREG_IPI_VECTOR_PRI_1	0x000b0
-#define MPIC_GREG_IPI_VECTOR_PRI_2	0x000c0
-#define MPIC_GREG_IPI_VECTOR_PRI_3	0x000d0
-#define MPIC_GREG_IPI_STRIDE		0x10
-#define MPIC_GREG_SPURIOUS		0x000e0
-#define MPIC_GREG_TIMER_FREQ		0x000f0
-
-/*
- *
- * Timer registers
- */
-#define MPIC_TIMER_BASE			0x01100
-#define MPIC_TIMER_STRIDE		0x40
-
-#define MPIC_TIMER_CURRENT_CNT		0x00000
-#define MPIC_TIMER_BASE_CNT		0x00010
-#define MPIC_TIMER_VECTOR_PRI		0x00020
-#define MPIC_TIMER_DESTINATION		0x00030
-
-/*
- * Per-Processor registers
- */
-
-#define MPIC_CPU_THISBASE		0x00000
-#define MPIC_CPU_BASE			0x20000
-#define MPIC_CPU_STRIDE			0x01000
-
-#define MPIC_CPU_IPI_DISPATCH_0		0x00040
-#define MPIC_CPU_IPI_DISPATCH_1		0x00050
-#define MPIC_CPU_IPI_DISPATCH_2		0x00060
-#define MPIC_CPU_IPI_DISPATCH_3		0x00070
-#define MPIC_CPU_IPI_DISPATCH_STRIDE	0x00010
-#define MPIC_CPU_CURRENT_TASK_PRI	0x00080
-#define 	MPIC_CPU_TASKPRI_MASK			0x0000000f
-#define MPIC_CPU_WHOAMI			0x00090
-#define 	MPIC_CPU_WHOAMI_MASK			0x0000001f
-#define MPIC_CPU_INTACK			0x000a0
-#define MPIC_CPU_EOI			0x000b0
-#define MPIC_CPU_MCACK			0x000c0
-
-/*
- * Per-source registers
- */
-
-#define MPIC_IRQ_BASE			0x10000
-#define MPIC_IRQ_STRIDE			0x00020
-#define MPIC_IRQ_VECTOR_PRI		0x00000
-#define 	MPIC_VECPRI_MASK			0x80000000
-#define 	MPIC_VECPRI_ACTIVITY			0x40000000	/* Read Only */
-#define 	MPIC_VECPRI_PRIORITY_MASK		0x000f0000
-#define 	MPIC_VECPRI_PRIORITY_SHIFT		16
-#define 	MPIC_VECPRI_VECTOR_MASK			0x000007ff
-#define 	MPIC_VECPRI_POLARITY_POSITIVE		0x00800000
-#define 	MPIC_VECPRI_POLARITY_NEGATIVE		0x00000000
-#define 	MPIC_VECPRI_POLARITY_MASK		0x00800000
-#define 	MPIC_VECPRI_SENSE_LEVEL			0x00400000
-#define 	MPIC_VECPRI_SENSE_EDGE			0x00000000
-#define 	MPIC_VECPRI_SENSE_MASK			0x00400000
-#define MPIC_IRQ_DESTINATION		0x00010
-
-#define MPIC_MAX_IRQ_SOURCES	2048
-#define MPIC_MAX_CPUS		32
-#define MPIC_MAX_ISU		32
-
-/*
- * Tsi108 implementation of MPIC has many differences from the original one
- */
-
-/*
- * Global registers
- */
-
-#define TSI108_GREG_BASE		0x00000
-#define TSI108_GREG_FEATURE_0		0x00000
-#define TSI108_GREG_GLOBAL_CONF_0	0x00004
-#define TSI108_GREG_VENDOR_ID		0x0000c
-#define TSI108_GREG_IPI_VECTOR_PRI_0	0x00204		/* Doorbell 0 */
-#define TSI108_GREG_IPI_STRIDE		0x0c
-#define TSI108_GREG_SPURIOUS		0x00010
-#define TSI108_GREG_TIMER_FREQ		0x00014
-
-/*
- * Timer registers
- */
-#define TSI108_TIMER_BASE		0x0030
-#define TSI108_TIMER_STRIDE		0x10
-#define TSI108_TIMER_CURRENT_CNT	0x00000
-#define TSI108_TIMER_BASE_CNT		0x00004
-#define TSI108_TIMER_VECTOR_PRI		0x00008
-#define TSI108_TIMER_DESTINATION	0x0000c
-
-/*
- * Per-Processor registers
- */
-#define TSI108_CPU_BASE			0x00300
-#define TSI108_CPU_STRIDE		0x00040
-#define TSI108_CPU_IPI_DISPATCH_0	0x00200
-#define TSI108_CPU_IPI_DISPATCH_STRIDE	0x00000
-#define TSI108_CPU_CURRENT_TASK_PRI	0x00000
-#define TSI108_CPU_WHOAMI		0xffffffff
-#define TSI108_CPU_INTACK		0x00004
-#define TSI108_CPU_EOI			0x00008
-#define TSI108_CPU_MCACK		0x00004 /* Doesn't really exist here */
-
-/*
- * Per-source registers
- */
-#define TSI108_IRQ_BASE			0x00100
-#define TSI108_IRQ_STRIDE		0x00008
-#define TSI108_IRQ_VECTOR_PRI		0x00000
-#define TSI108_VECPRI_VECTOR_MASK	0x000000ff
-#define TSI108_VECPRI_POLARITY_POSITIVE	0x01000000
-#define TSI108_VECPRI_POLARITY_NEGATIVE	0x00000000
-#define TSI108_VECPRI_SENSE_LEVEL	0x02000000
-#define TSI108_VECPRI_SENSE_EDGE	0x00000000
-#define TSI108_VECPRI_POLARITY_MASK	0x01000000
-#define TSI108_VECPRI_SENSE_MASK	0x02000000
-#define TSI108_IRQ_DESTINATION		0x00004
-
-/* weird mpic register indices and mask bits in the HW info array */
-enum {
-	MPIC_IDX_GREG_BASE = 0,
-	MPIC_IDX_GREG_FEATURE_0,
-	MPIC_IDX_GREG_GLOBAL_CONF_0,
-	MPIC_IDX_GREG_VENDOR_ID,
-	MPIC_IDX_GREG_IPI_VECTOR_PRI_0,
-	MPIC_IDX_GREG_IPI_STRIDE,
-	MPIC_IDX_GREG_SPURIOUS,
-	MPIC_IDX_GREG_TIMER_FREQ,
-
-	MPIC_IDX_TIMER_BASE,
-	MPIC_IDX_TIMER_STRIDE,
-	MPIC_IDX_TIMER_CURRENT_CNT,
-	MPIC_IDX_TIMER_BASE_CNT,
-	MPIC_IDX_TIMER_VECTOR_PRI,
-	MPIC_IDX_TIMER_DESTINATION,
-
-	MPIC_IDX_CPU_BASE,
-	MPIC_IDX_CPU_STRIDE,
-	MPIC_IDX_CPU_IPI_DISPATCH_0,
-	MPIC_IDX_CPU_IPI_DISPATCH_STRIDE,
-	MPIC_IDX_CPU_CURRENT_TASK_PRI,
-	MPIC_IDX_CPU_WHOAMI,
-	MPIC_IDX_CPU_INTACK,
-	MPIC_IDX_CPU_EOI,
-	MPIC_IDX_CPU_MCACK,
-
-	MPIC_IDX_IRQ_BASE,
-	MPIC_IDX_IRQ_STRIDE,
-	MPIC_IDX_IRQ_VECTOR_PRI,
-
-	MPIC_IDX_VECPRI_VECTOR_MASK,
-	MPIC_IDX_VECPRI_POLARITY_POSITIVE,
-	MPIC_IDX_VECPRI_POLARITY_NEGATIVE,
-	MPIC_IDX_VECPRI_SENSE_LEVEL,
-	MPIC_IDX_VECPRI_SENSE_EDGE,
-	MPIC_IDX_VECPRI_POLARITY_MASK,
-	MPIC_IDX_VECPRI_SENSE_MASK,
-	MPIC_IDX_IRQ_DESTINATION,
-	MPIC_IDX_END
-};
-
-
-#ifdef CONFIG_MPIC_U3_HT_IRQS
-/* Fixup table entry */
-struct mpic_irq_fixup
-{
-	u8 __iomem	*base;
-	u8 __iomem	*applebase;
-	u32		data;
-	unsigned int	index;
-};
-#endif /* CONFIG_MPIC_U3_HT_IRQS */
-
-
-enum mpic_reg_type {
-	mpic_access_mmio_le,
-	mpic_access_mmio_be,
-#ifdef CONFIG_PPC_DCR
-	mpic_access_dcr
-#endif
-};
-
-struct mpic_reg_bank {
-	u32 __iomem	*base;
-#ifdef CONFIG_PPC_DCR
-	dcr_host_t	dhost;
-#endif /* CONFIG_PPC_DCR */
-};
-
-struct mpic_irq_save {
-	u32		vecprio,
-			dest;
-#ifdef CONFIG_MPIC_U3_HT_IRQS
-	u32		fixup_data;
-#endif
-};
-
-/* The instance data of a given MPIC */
-struct mpic
-{
-	/* The OpenFirmware dt node for this MPIC */
-	struct device_node *node;
-
-	/* The remapper for this MPIC */
-	struct irq_domain	*irqhost;
-
-	/* The "linux" controller struct */
-	struct irq_chip		hc_irq;
-#ifdef CONFIG_MPIC_U3_HT_IRQS
-	struct irq_chip		hc_ht_irq;
-#endif
-#ifdef CONFIG_SMP
-	struct irq_chip		hc_ipi;
-#endif
-	struct irq_chip		hc_tm;
-	const char		*name;
-	/* Flags */
-	unsigned int		flags;
-	/* How many irq sources in a given ISU */
-	unsigned int		isu_size;
-	unsigned int		isu_shift;
-	unsigned int		isu_mask;
-	/* Number of sources */
-	unsigned int		num_sources;
-
-	/* vector numbers used for internal sources (ipi/timers) */
-	unsigned int		ipi_vecs[4];
-	unsigned int		timer_vecs[8];
-
-	/* Spurious vector to program into unused sources */
-	unsigned int		spurious_vec;
-
-#ifdef CONFIG_MPIC_U3_HT_IRQS
-	/* The fixup table */
-	struct mpic_irq_fixup	*fixups;
-	raw_spinlock_t	fixup_lock;
-#endif
-
-	/* Register access method */
-	enum mpic_reg_type	reg_type;
-
-	/* The physical base address of the MPIC */
-	phys_addr_t paddr;
-
-	/* The various ioremap'ed bases */
-	struct mpic_reg_bank	gregs;
-	struct mpic_reg_bank	tmregs;
-	struct mpic_reg_bank	cpuregs[MPIC_MAX_CPUS];
-	struct mpic_reg_bank	isus[MPIC_MAX_ISU];
-
-	/* Protected sources */
-	unsigned long		*protected;
-
-#ifdef CONFIG_MPIC_WEIRD
-	/* Pointer to HW info array */
-	u32			*hw_set;
-#endif
-
-#ifdef CONFIG_PCI_MSI
-	struct msi_bitmap	msi_bitmap;
-#endif
-
-#ifdef CONFIG_MPIC_BROKEN_REGREAD
-	u32			isu_reg0_shadow[MPIC_MAX_IRQ_SOURCES];
-#endif
-
-	/* link */
-	struct mpic		*next;
-
-#ifdef CONFIG_PM
-	struct mpic_irq_save	*save_data;
-#endif
-};
-
-/*
- * MPIC flags (passed to mpic_alloc)
- *
- * The top 4 bits contain an MPIC bhw id that is used to index the
- * register offsets and some masks when CONFIG_MPIC_WEIRD is set.
- * Note setting any ID (leaving those bits to 0) means standard MPIC
- */
-
-/*
- * This is a secondary ("chained") controller; it only uses the CPU0
- * registers.  Primary controllers have IPIs and affinity control.
- */
-#define MPIC_SECONDARY			0x00000001
-
-/* Set this for a big-endian MPIC */
-#define MPIC_BIG_ENDIAN			0x00000002
-/* Broken U3 MPIC */
-#define MPIC_U3_HT_IRQS			0x00000004
-/* Broken IPI registers (autodetected) */
-#define MPIC_BROKEN_IPI			0x00000008
-/* Spurious vector requires EOI */
-#define MPIC_SPV_EOI			0x00000020
-/* No passthrough disable */
-#define MPIC_NO_PTHROU_DIS		0x00000040
-/* DCR based MPIC */
-#define MPIC_USES_DCR			0x00000080
-/* MPIC has 11-bit vector fields (or larger) */
-#define MPIC_LARGE_VECTORS		0x00000100
-/* Enable delivery of prio 15 interrupts as MCK instead of EE */
-#define MPIC_ENABLE_MCK			0x00000200
-/* Disable bias among target selection, spread interrupts evenly */
-#define MPIC_NO_BIAS			0x00000400
-/* Destination only supports a single CPU at a time */
-#define MPIC_SINGLE_DEST_CPU		0x00001000
-/* Enable CoreInt delivery of interrupts */
-#define MPIC_ENABLE_COREINT		0x00002000
-/* Do not reset the MPIC during initialization */
-#define MPIC_NO_RESET			0x00004000
-/* Freescale MPIC (compatible includes "fsl,mpic") */
-#define MPIC_FSL			0x00008000
-
-/* MPIC HW modification ID */
-#define MPIC_REGSET_MASK		0xf0000000
-#define MPIC_REGSET(val)		(((val) & 0xf ) << 28)
-#define MPIC_GET_REGSET(flags)		(((flags) >> 28) & 0xf)
-
-#define	MPIC_REGSET_STANDARD		MPIC_REGSET(0)	/* Original MPIC */
-#define	MPIC_REGSET_TSI108		MPIC_REGSET(1)	/* Tsi108/109 PIC */
-
-/* Allocate the controller structure and setup the linux irq descs
- * for the range if interrupts passed in. No HW initialization is
- * actually performed.
- * 
- * @phys_addr:	physial base address of the MPIC
- * @flags:	flags, see constants above
- * @isu_size:	number of interrupts in an ISU. Use 0 to use a
- *              standard ISU-less setup (aka powermac)
- * @irq_offset: first irq number to assign to this mpic
- * @irq_count:  number of irqs to use with this mpic IRQ sources. Pass 0
- *	        to match the number of sources
- * @ipi_offset: first irq number to assign to this mpic IPI sources,
- *		used only on primary mpic
- * @senses:	array of sense values
- * @senses_num: number of entries in the array
- *
- * Note about the sense array. If none is passed, all interrupts are
- * setup to be level negative unless MPIC_U3_HT_IRQS is set in which
- * case they are edge positive (and the array is ignored anyway).
- * The values in the array start at the first source of the MPIC,
- * that is senses[0] correspond to linux irq "irq_offset".
- */
-extern struct mpic *mpic_alloc(struct device_node *node,
-			       phys_addr_t phys_addr,
-			       unsigned int flags,
-			       unsigned int isu_size,
-			       unsigned int irq_count,
-			       const char *name);
-
-/* Assign ISUs, to call before mpic_init()
- *
- * @mpic:	controller structure as returned by mpic_alloc()
- * @isu_num:	ISU number
- * @phys_addr:	physical address of the ISU
- */
-extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
-			    phys_addr_t phys_addr);
-
-
-/* Initialize the controller. After this has been called, none of the above
- * should be called again for this mpic
- */
-extern void mpic_init(struct mpic *mpic);
-
-/*
- * All of the following functions must only be used after the
- * ISUs have been assigned and the controller fully initialized
- * with mpic_init()
- */
-
-
-/* Change the priority of an interrupt. Default is 8 for irqs and
- * 10 for IPIs. You can call this on both IPIs and IRQ numbers, but the
- * IPI number is then the offset'ed (linux irq number mapped to the IPI)
- */
-extern void mpic_irq_set_priority(unsigned int irq, unsigned int pri);
-
-/* Setup a non-boot CPU */
-extern void mpic_setup_this_cpu(void);
-
-/* Clean up for kexec (or cpu offline or ...) */
-extern void mpic_teardown_this_cpu(int secondary);
-
-/* Get the current cpu priority for this cpu (0..15) */
-extern int mpic_cpu_get_priority(void);
-
-/* Set the current cpu priority for this cpu */
-extern void mpic_cpu_set_priority(int prio);
-
-/* Request IPIs on primary mpic */
-extern void mpic_request_ipis(void);
-
-/* Send a message (IPI) to a given target (cpu number or MSG_*) */
-void smp_mpic_message_pass(int target, int msg);
-
-/* Unmask a specific virq */
-extern void mpic_unmask_irq(struct irq_data *d);
-/* Mask a specific virq */
-extern void mpic_mask_irq(struct irq_data *d);
-/* EOI a specific virq */
-extern void mpic_end_irq(struct irq_data *d);
-
-/* Fetch interrupt from a given mpic */
-extern unsigned int mpic_get_one_irq(struct mpic *mpic);
-/* This one gets from the primary mpic */
-extern unsigned int mpic_get_irq(void);
-/* This one gets from the primary mpic via CoreInt*/
-extern unsigned int mpic_get_coreint_irq(void);
-/* Fetch Machine Check interrupt from primary mpic */
-extern unsigned int mpic_get_mcirq(void);
-
-/* Set the EPIC clock ratio */
-void mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio);
-
-/* Enable/Disable EPIC serial interrupt mode */
-void mpic_set_serial_int(struct mpic *mpic, int enable);
-
-#endif /* __KERNEL__ */
-#endif	/* _ASM_POWERPC_MPIC_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/mpic_msgr.h b/ANDROID_3.4.5/arch/powerpc/include/asm/mpic_msgr.h
deleted file mode 100644
index 326d33ca..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/mpic_msgr.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
- * Copyright 2011-2012, Meador Inge, Mentor Graphics Corporation.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; version 2 of the
- * License.
- *
- */
-
-#ifndef _ASM_MPIC_MSGR_H
-#define _ASM_MPIC_MSGR_H
-
-#include <linux/types.h>
-#include <linux/spinlock.h>
-#include <asm/smp.h>
-
-struct mpic_msgr {
-	u32 __iomem *base;
-	u32 __iomem *mer;
-	int irq;
-	unsigned char in_use;
-	raw_spinlock_t lock;
-	int num;
-};
-
-/* Get a message register
- *
- * @reg_num:	the MPIC message register to get
- *
- * A pointer to the message register is returned.  If
- * the message register asked for is already in use, then
- * EBUSY is returned.  If the number given is not associated
- * with an actual message register, then ENODEV is returned.
- * Successfully getting the register marks it as in use.
- */
-extern struct mpic_msgr *mpic_msgr_get(unsigned int reg_num);
-
-/* Relinquish a message register
- *
- * @msgr:	the message register to return
- *
- * Disables the given message register and marks it as free.
- * After this call has completed successully the message
- * register is available to be acquired by a call to
- * mpic_msgr_get.
- */
-extern void mpic_msgr_put(struct mpic_msgr *msgr);
-
-/* Enable a message register
- *
- * @msgr:	the message register to enable
- *
- * The given message register is enabled for sending
- * messages.
- */
-extern void mpic_msgr_enable(struct mpic_msgr *msgr);
-
-/* Disable a message register
- *
- * @msgr:	the message register to disable
- *
- * The given message register is disabled for sending
- * messages.
- */
-extern void mpic_msgr_disable(struct mpic_msgr *msgr);
-
-/* Write a message to a message register
- *
- * @msgr:	the message register to write to
- * @message:	the message to write
- *
- * The given 32-bit message is written to the given message
- * register.  Writing to an enabled message registers fires
- * an interrupt.
- */
-static inline void mpic_msgr_write(struct mpic_msgr *msgr, u32 message)
-{
-	out_be32(msgr->base, message);
-}
-
-/* Read a message from a message register
- *
- * @msgr:	the message register to read from
- *
- * Returns the 32-bit value currently in the given message register.
- * Upon reading the register any interrupts for that register are
- * cleared.
- */
-static inline u32 mpic_msgr_read(struct mpic_msgr *msgr)
-{
-	return in_be32(msgr->base);
-}
-
-/* Clear a message register
- *
- * @msgr:	the message register to clear
- *
- * Clears any interrupts associated with the given message register.
- */
-static inline void mpic_msgr_clear(struct mpic_msgr *msgr)
-{
-	(void) mpic_msgr_read(msgr);
-}
-
-/* Set the destination CPU for the message register
- *
- * @msgr:	the message register whose destination is to be set
- * @cpu_num:	the Linux CPU number to bind the message register to
- *
- * Note that the CPU number given is the CPU number used by the kernel
- * and *not* the actual hardware CPU number.
- */
-static inline void mpic_msgr_set_destination(struct mpic_msgr *msgr,
-					     u32 cpu_num)
-{
-	out_be32(msgr->base, 1 << get_hard_smp_processor_id(cpu_num));
-}
-
-/* Get the IRQ number for the message register
- * @msgr:	the message register whose IRQ is to be returned
- *
- * Returns the IRQ number associated with the given message register.
- * NO_IRQ is returned if this message register is not capable of
- * receiving interrupts.  What message register can and cannot receive
- * interrupts is specified in the device tree for the system.
- */
-static inline int mpic_msgr_get_irq(struct mpic_msgr *msgr)
-{
-	return msgr->irq;
-}
-
-#endif
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/msgbuf.h b/ANDROID_3.4.5/arch/powerpc/include/asm/msgbuf.h
deleted file mode 100644
index dd76743c..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/msgbuf.h
+++ /dev/null
@@ -1,33 +0,0 @@
-#ifndef _ASM_POWERPC_MSGBUF_H
-#define _ASM_POWERPC_MSGBUF_H
-
-/*
- * The msqid64_ds structure for the PowerPC architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- */
-
-struct msqid64_ds {
-	struct ipc64_perm msg_perm;
-#ifndef __powerpc64__
-	unsigned int	__unused1;
-#endif
-	__kernel_time_t msg_stime;	/* last msgsnd time */
-#ifndef __powerpc64__
-	unsigned int	__unused2;
-#endif
-	__kernel_time_t msg_rtime;	/* last msgrcv time */
-#ifndef __powerpc64__
-	unsigned int	__unused3;
-#endif
-	__kernel_time_t msg_ctime;	/* last change time */
-	unsigned long  msg_cbytes;	/* current number of bytes on queue */
-	unsigned long  msg_qnum;	/* number of messages in queue */
-	unsigned long  msg_qbytes;	/* max number of bytes on queue */
-	__kernel_pid_t msg_lspid;	/* pid of last msgsnd */
-	__kernel_pid_t msg_lrpid;	/* last receive pid */
-	unsigned long  __unused4;
-	unsigned long  __unused5;
-};
-
-#endif	/* _ASM_POWERPC_MSGBUF_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/msi_bitmap.h b/ANDROID_3.4.5/arch/powerpc/include/asm/msi_bitmap.h
deleted file mode 100644
index 97ac3f46..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/msi_bitmap.h
+++ /dev/null
@@ -1,35 +0,0 @@
-#ifndef _POWERPC_SYSDEV_MSI_BITMAP_H
-#define _POWERPC_SYSDEV_MSI_BITMAP_H
-
-/*
- * Copyright 2008, Michael Ellerman, IBM Corporation.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; version 2 of the
- * License.
- *
- */
-
-#include <linux/of.h>
-#include <asm/irq.h>
-
-struct msi_bitmap {
-	struct device_node	*of_node;
-	unsigned long		*bitmap;
-	spinlock_t		lock;
-	unsigned int		irq_count;
-};
-
-int msi_bitmap_alloc_hwirqs(struct msi_bitmap *bmp, int num);
-void msi_bitmap_free_hwirqs(struct msi_bitmap *bmp, unsigned int offset,
-			    unsigned int num);
-void msi_bitmap_reserve_hwirq(struct msi_bitmap *bmp, unsigned int hwirq);
-
-int msi_bitmap_reserve_dt_hwirqs(struct msi_bitmap *bmp);
-
-int msi_bitmap_alloc(struct msi_bitmap *bmp, unsigned int irq_count,
-		     struct device_node *of_node);
-void msi_bitmap_free(struct msi_bitmap *bmp);
-
-#endif /* _POWERPC_SYSDEV_MSI_BITMAP_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/mutex.h b/ANDROID_3.4.5/arch/powerpc/include/asm/mutex.h
deleted file mode 100644
index 5399f7e1..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/mutex.h
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * Optimised mutex implementation of include/asm-generic/mutex-dec.h algorithm
- */
-#ifndef _ASM_POWERPC_MUTEX_H
-#define _ASM_POWERPC_MUTEX_H
-
-static inline int __mutex_cmpxchg_lock(atomic_t *v, int old, int new)
-{
-	int t;
-
-	__asm__ __volatile__ (
-"1:	lwarx	%0,0,%1		# mutex trylock\n\
-	cmpw	0,%0,%2\n\
-	bne-	2f\n"
-	PPC405_ERR77(0,%1)
-"	stwcx.	%3,0,%1\n\
-	bne-	1b"
-	PPC_ACQUIRE_BARRIER
-	"\n\
-2:"
-	: "=&r" (t)
-	: "r" (&v->counter), "r" (old), "r" (new)
-	: "cc", "memory");
-
-	return t;
-}
-
-static inline int __mutex_dec_return_lock(atomic_t *v)
-{
-	int t;
-
-	__asm__ __volatile__(
-"1:	lwarx	%0,0,%1		# mutex lock\n\
-	addic	%0,%0,-1\n"
-	PPC405_ERR77(0,%1)
-"	stwcx.	%0,0,%1\n\
-	bne-	1b"
-	PPC_ACQUIRE_BARRIER
-	: "=&r" (t)
-	: "r" (&v->counter)
-	: "cc", "memory");
-
-	return t;
-}
-
-static inline int __mutex_inc_return_unlock(atomic_t *v)
-{
-	int t;
-
-	__asm__ __volatile__(
-	PPC_RELEASE_BARRIER
-"1:	lwarx	%0,0,%1		# mutex unlock\n\
-	addic	%0,%0,1\n"
-	PPC405_ERR77(0,%1)
-"	stwcx.	%0,0,%1 \n\
-	bne-	1b"
-	: "=&r" (t)
-	: "r" (&v->counter)
-	: "cc", "memory");
-
-	return t;
-}
-
-/**
- *  __mutex_fastpath_lock - try to take the lock by moving the count
- *                          from 1 to a 0 value
- *  @count: pointer of type atomic_t
- *  @fail_fn: function to call if the original value was not 1
- *
- * Change the count from 1 to a value lower than 1, and call <fail_fn> if
- * it wasn't 1 originally. This function MUST leave the value lower than
- * 1 even when the "1" assertion wasn't true.
- */
-static inline void
-__mutex_fastpath_lock(atomic_t *count, void (*fail_fn)(atomic_t *))
-{
-	if (unlikely(__mutex_dec_return_lock(count) < 0))
-		fail_fn(count);
-}
-
-/**
- *  __mutex_fastpath_lock_retval - try to take the lock by moving the count
- *                                 from 1 to a 0 value
- *  @count: pointer of type atomic_t
- *  @fail_fn: function to call if the original value was not 1
- *
- * Change the count from 1 to a value lower than 1, and call <fail_fn> if
- * it wasn't 1 originally. This function returns 0 if the fastpath succeeds,
- * or anything the slow path function returns.
- */
-static inline int
-__mutex_fastpath_lock_retval(atomic_t *count, int (*fail_fn)(atomic_t *))
-{
-	if (unlikely(__mutex_dec_return_lock(count) < 0))
-		return fail_fn(count);
-	return 0;
-}
-
-/**
- *  __mutex_fastpath_unlock - try to promote the count from 0 to 1
- *  @count: pointer of type atomic_t
- *  @fail_fn: function to call if the original value was not 0
- *
- * Try to promote the count from 0 to 1. If it wasn't 0, call <fail_fn>.
- * In the failure case, this function is allowed to either set the value to
- * 1, or to set it to a value lower than 1.
- */
-static inline void
-__mutex_fastpath_unlock(atomic_t *count, void (*fail_fn)(atomic_t *))
-{
-	if (unlikely(__mutex_inc_return_unlock(count) <= 0))
-		fail_fn(count);
-}
-
-#define __mutex_slowpath_needs_to_unlock()		1
-
-/**
- * __mutex_fastpath_trylock - try to acquire the mutex, without waiting
- *
- *  @count: pointer of type atomic_t
- *  @fail_fn: fallback function
- *
- * Change the count from 1 to 0, and return 1 (success), or if the count
- * was not 1, then return 0 (failure).
- */
-static inline int
-__mutex_fastpath_trylock(atomic_t *count, int (*fail_fn)(atomic_t *))
-{
-	if (likely(__mutex_cmpxchg_lock(count, 1, 0) == 1))
-		return 1;
-	return 0;
-}
-
-#endif
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/nvram.h b/ANDROID_3.4.5/arch/powerpc/include/asm/nvram.h
deleted file mode 100644
index 9d1aafe6..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/nvram.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * NVRAM definitions and access functions.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_POWERPC_NVRAM_H
-#define _ASM_POWERPC_NVRAM_H
-
-/* Signatures for nvram partitions */
-#define NVRAM_SIG_SP	0x02	/* support processor */
-#define NVRAM_SIG_OF	0x50	/* open firmware config */
-#define NVRAM_SIG_FW	0x51	/* general firmware */
-#define NVRAM_SIG_HW	0x52	/* hardware (VPD) */
-#define NVRAM_SIG_FLIP	0x5a	/* Apple flip/flop header */
-#define NVRAM_SIG_APPL	0x5f	/* Apple "system" (???) */
-#define NVRAM_SIG_SYS	0x70	/* system env vars */
-#define NVRAM_SIG_CFG	0x71	/* config data */
-#define NVRAM_SIG_ELOG	0x72	/* error log */
-#define NVRAM_SIG_VEND	0x7e	/* vendor defined */
-#define NVRAM_SIG_FREE	0x7f	/* Free space */
-#define NVRAM_SIG_OS	0xa0	/* OS defined */
-#define NVRAM_SIG_PANIC	0xa1	/* Apple OSX "panic" */
-
-#ifdef __KERNEL__
-
-#include <linux/errno.h>
-#include <linux/list.h>
-
-#ifdef CONFIG_PPC_PSERIES
-extern int nvram_write_error_log(char * buff, int length,
-					 unsigned int err_type, unsigned int err_seq);
-extern int nvram_read_error_log(char * buff, int length,
-					 unsigned int * err_type, unsigned int *err_seq);
-extern int nvram_clear_error_log(void);
-extern int pSeries_nvram_init(void);
-#endif /* CONFIG_PPC_PSERIES */
-
-#ifdef CONFIG_MMIO_NVRAM
-extern int mmio_nvram_init(void);
-#else
-static inline int mmio_nvram_init(void)
-{
-	return -ENODEV;
-}
-#endif
-
-extern int __init nvram_scan_partitions(void);
-extern loff_t nvram_create_partition(const char *name, int sig,
-				     int req_size, int min_size);
-extern int nvram_remove_partition(const char *name, int sig,
-					const char *exceptions[]);
-extern int nvram_get_partition_size(loff_t data_index);
-extern loff_t nvram_find_partition(const char *name, int sig, int *out_size);
-
-#endif /* __KERNEL__ */
-
-/* PowerMac specific nvram stuffs */
-
-enum {
-	pmac_nvram_OF,		/* Open Firmware partition */
-	pmac_nvram_XPRAM,	/* MacOS XPRAM partition */
-	pmac_nvram_NR		/* MacOS Name Registry partition */
-};
-
-#ifdef __KERNEL__
-/* Return partition offset in nvram */
-extern int	pmac_get_partition(int partition);
-
-/* Direct access to XPRAM on PowerMacs */
-extern u8	pmac_xpram_read(int xpaddr);
-extern void	pmac_xpram_write(int xpaddr, u8 data);
-
-/* Synchronize NVRAM */
-extern void	nvram_sync(void);
-
-/* Determine NVRAM size */
-extern ssize_t nvram_get_size(void);
-
-/* Normal access to NVRAM */
-extern unsigned char nvram_read_byte(int i);
-extern void nvram_write_byte(unsigned char c, int i);
-#endif
-
-/* Some offsets in XPRAM */
-#define PMAC_XPRAM_MACHINE_LOC	0xe4
-#define PMAC_XPRAM_SOUND_VOLUME	0x08
-
-/* Machine location structure in PowerMac XPRAM */
-struct pmac_machine_location {
-	unsigned int	latitude;	/* 2+30 bit Fractional number */
-	unsigned int	longitude;	/* 2+30 bit Fractional number */
-	unsigned int	delta;		/* mix of GMT delta and DLS */
-};
-
-/*
- * /dev/nvram ioctls
- *
- * Note that PMAC_NVRAM_GET_OFFSET is still supported, but is
- * definitely obsolete. Do not use it if you can avoid it
- */
-
-#define OBSOLETE_PMAC_NVRAM_GET_OFFSET \
-				_IOWR('p', 0x40, int)
-
-#define IOC_NVRAM_GET_OFFSET	_IOWR('p', 0x42, int)	/* Get NVRAM partition offset */
-#define IOC_NVRAM_SYNC		_IO('p', 0x43)		/* Sync NVRAM image */
-
-#endif /* _ASM_POWERPC_NVRAM_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/ohare.h b/ANDROID_3.4.5/arch/powerpc/include/asm/ohare.h
deleted file mode 100644
index 0d030f9d..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/ohare.h
+++ /dev/null
@@ -1,54 +0,0 @@
-#ifndef _ASM_POWERPC_OHARE_H
-#define _ASM_POWERPC_OHARE_H
-#ifdef __KERNEL__
-/*
- * ohare.h: definitions for using the "O'Hare" I/O controller chip.
- *
- * Copyright (C) 1997 Paul Mackerras.
- *
- * BenH: Changed to match those of heathrow (but not all of them). Please
- *       check if I didn't break anything (especially the media bay).
- */
-
-/* offset from ohare base for feature control register */
-#define OHARE_MBCR	0x34
-#define OHARE_FCR	0x38
-
-/*
- * Bits in feature control register.
- * These were mostly derived by experiment on a powerbook 3400
- * and may differ for other machines.
- */
-#define OH_SCC_RESET		1
-#define OH_BAY_POWER_N		2	/* a guess */
-#define OH_BAY_PCI_ENABLE	4	/* a guess */
-#define OH_BAY_IDE_ENABLE	8
-#define OH_BAY_FLOPPY_ENABLE	0x10
-#define OH_IDE0_ENABLE		0x20
-#define OH_IDE0_RESET_N		0x40	/* a guess */
-#define OH_BAY_DEV_MASK		0x1c
-#define OH_BAY_RESET_N		0x80
-#define OH_IOBUS_ENABLE		0x100	/* IOBUS seems to be IDE */
-#define OH_SCC_ENABLE		0x200
-#define OH_MESH_ENABLE		0x400
-#define OH_FLOPPY_ENABLE	0x800
-#define OH_SCCA_IO		0x4000
-#define OH_SCCB_IO		0x8000
-#define OH_VIA_ENABLE		0x10000	/* Is apparently wrong, to be verified */
-#define OH_IDE1_RESET_N		0x800000
-
-/*
- * Bits to set in the feature control register on PowerBooks.
- */
-#define PBOOK_FEATURES		(OH_IDE_ENABLE | OH_SCC_ENABLE | \
-				 OH_MESH_ENABLE | OH_SCCA_IO | OH_SCCB_IO)
-
-/*
- * A magic value to put into the feature control register of the
- * "ohare" I/O controller on Starmaxes to enable the IDE CD interface.
- * Contributed by Harry Eaton.
- */
-#define STARMAX_FEATURES	0xbeff7a
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_OHARE_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/opal.h b/ANDROID_3.4.5/arch/powerpc/include/asm/opal.h
deleted file mode 100644
index a4b28f16..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/opal.h
+++ /dev/null
@@ -1,566 +0,0 @@
-/*
- * PowerNV OPAL definitions.
- *
- * Copyright 2011 IBM Corp.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef __OPAL_H
-#define __OPAL_H
-
-/****** Takeover interface ********/
-
-/* PAPR H-Call used to querty the HAL existence and/or instanciate
- * it from within pHyp (tech preview only).
- *
- * This is exclusively used in prom_init.c
- */
-
-#ifndef __ASSEMBLY__
-
-struct opal_takeover_args {
-	u64	k_image;		/* r4 */
-	u64	k_size;			/* r5 */
-	u64	k_entry;		/* r6 */
-	u64	k_entry2;		/* r7 */
-	u64	hal_addr;		/* r8 */
-	u64	rd_image;		/* r9 */
-	u64	rd_size;		/* r10 */
-	u64	rd_loc;			/* r11 */
-};
-
-extern long opal_query_takeover(u64 *hal_size, u64 *hal_align);
-
-extern long opal_do_takeover(struct opal_takeover_args *args);
-
-struct rtas_args;
-extern int opal_enter_rtas(struct rtas_args *args,
-			   unsigned long data,
-			   unsigned long entry);
-
-#endif /* __ASSEMBLY__ */
-
-/****** OPAL APIs ******/
-
-/* Return codes */
-#define OPAL_SUCCESS 		0
-#define OPAL_PARAMETER		-1
-#define OPAL_BUSY		-2
-#define OPAL_PARTIAL		-3
-#define OPAL_CONSTRAINED	-4
-#define OPAL_CLOSED		-5
-#define OPAL_HARDWARE		-6
-#define OPAL_UNSUPPORTED	-7
-#define OPAL_PERMISSION		-8
-#define OPAL_NO_MEM		-9
-#define OPAL_RESOURCE		-10
-#define OPAL_INTERNAL_ERROR	-11
-#define OPAL_BUSY_EVENT		-12
-#define OPAL_HARDWARE_FROZEN	-13
-
-/* API Tokens (in r0) */
-#define OPAL_CONSOLE_WRITE			1
-#define OPAL_CONSOLE_READ			2
-#define OPAL_RTC_READ				3
-#define OPAL_RTC_WRITE				4
-#define OPAL_CEC_POWER_DOWN			5
-#define OPAL_CEC_REBOOT				6
-#define OPAL_READ_NVRAM				7
-#define OPAL_WRITE_NVRAM			8
-#define OPAL_HANDLE_INTERRUPT			9
-#define OPAL_POLL_EVENTS			10
-#define OPAL_PCI_SET_HUB_TCE_MEMORY		11
-#define OPAL_PCI_SET_PHB_TCE_MEMORY		12
-#define OPAL_PCI_CONFIG_READ_BYTE		13
-#define OPAL_PCI_CONFIG_READ_HALF_WORD  	14
-#define OPAL_PCI_CONFIG_READ_WORD		15
-#define OPAL_PCI_CONFIG_WRITE_BYTE		16
-#define OPAL_PCI_CONFIG_WRITE_HALF_WORD		17
-#define OPAL_PCI_CONFIG_WRITE_WORD		18
-#define OPAL_SET_XIVE				19
-#define OPAL_GET_XIVE				20
-#define OPAL_GET_COMPLETION_TOKEN_STATUS	21 /* obsolete */
-#define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER	22
-#define OPAL_PCI_EEH_FREEZE_STATUS		23
-#define OPAL_PCI_SHPC				24
-#define OPAL_CONSOLE_WRITE_BUFFER_SPACE		25
-#define OPAL_PCI_EEH_FREEZE_CLEAR		26
-#define OPAL_PCI_PHB_MMIO_ENABLE		27
-#define OPAL_PCI_SET_PHB_MEM_WINDOW		28
-#define OPAL_PCI_MAP_PE_MMIO_WINDOW		29
-#define OPAL_PCI_SET_PHB_TABLE_MEMORY		30
-#define OPAL_PCI_SET_PE				31
-#define OPAL_PCI_SET_PELTV			32
-#define OPAL_PCI_SET_MVE			33
-#define OPAL_PCI_SET_MVE_ENABLE			34
-#define OPAL_PCI_GET_XIVE_REISSUE		35
-#define OPAL_PCI_SET_XIVE_REISSUE		36
-#define OPAL_PCI_SET_XIVE_PE			37
-#define OPAL_GET_XIVE_SOURCE			38
-#define OPAL_GET_MSI_32				39
-#define OPAL_GET_MSI_64				40
-#define OPAL_START_CPU				41
-#define OPAL_QUERY_CPU_STATUS			42
-#define OPAL_WRITE_OPPANEL			43
-#define OPAL_PCI_MAP_PE_DMA_WINDOW		44
-#define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL		45
-#define OPAL_PCI_RESET				49
-#define OPAL_PCI_GET_HUB_DIAG_DATA		50
-#define OPAL_PCI_GET_PHB_DIAG_DATA		51
-#define OPAL_PCI_FENCE_PHB			52
-#define OPAL_PCI_REINIT				53
-#define OPAL_PCI_MASK_PE_ERROR			54
-#define OPAL_SET_SLOT_LED_STATUS		55
-#define OPAL_GET_EPOW_STATUS			56
-#define OPAL_SET_SYSTEM_ATTENTION_LED		57
-
-#ifndef __ASSEMBLY__
-
-/* Other enums */
-enum OpalVendorApiTokens {
-	OPAL_START_VENDOR_API_RANGE = 1000, OPAL_END_VENDOR_API_RANGE = 1999
-};
-enum OpalFreezeState {
-	OPAL_EEH_STOPPED_NOT_FROZEN = 0,
-	OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
-	OPAL_EEH_STOPPED_DMA_FREEZE = 2,
-	OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3,
-	OPAL_EEH_STOPPED_RESET = 4,
-	OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
-	OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
-};
-enum OpalEehFreezeActionToken {
-	OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
-	OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
-	OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3
-};
-enum OpalPciStatusToken {
-	OPAL_EEH_PHB_NO_ERROR = 0,
-	OPAL_EEH_PHB_FATAL = 1,
-	OPAL_EEH_PHB_RECOVERABLE = 2,
-	OPAL_EEH_PHB_BUS_ERROR = 3,
-	OPAL_EEH_PCI_NO_DEVSEL = 4,
-	OPAL_EEH_PCI_TA = 5,
-	OPAL_EEH_PCIEX_UR = 6,
-	OPAL_EEH_PCIEX_CA = 7,
-	OPAL_EEH_PCI_MMIO_ERROR = 8,
-	OPAL_EEH_PCI_DMA_ERROR = 9
-};
-enum OpalShpcAction {
-	OPAL_SHPC_GET_LINK_STATE = 0,
-	OPAL_SHPC_GET_SLOT_STATE = 1
-};
-enum OpalShpcLinkState {
-	OPAL_SHPC_LINK_DOWN = 0,
-	OPAL_SHPC_LINK_UP = 1
-};
-enum OpalMmioWindowType {
-	OPAL_M32_WINDOW_TYPE = 1,
-	OPAL_M64_WINDOW_TYPE = 2,
-	OPAL_IO_WINDOW_TYPE = 3
-};
-enum OpalShpcSlotState {
-	OPAL_SHPC_DEV_NOT_PRESENT = 0,
-	OPAL_SHPC_DEV_PRESENT = 1
-};
-enum OpalExceptionHandler {
-	OPAL_MACHINE_CHECK_HANDLER = 1,
-	OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
-	OPAL_SOFTPATCH_HANDLER = 3
-};
-enum OpalPendingState {
-	OPAL_EVENT_OPAL_INTERNAL = 0x1,
-	OPAL_EVENT_NVRAM = 0x2,
-	OPAL_EVENT_RTC = 0x4,
-	OPAL_EVENT_CONSOLE_OUTPUT = 0x8,
-	OPAL_EVENT_CONSOLE_INPUT = 0x10,
-	OPAL_EVENT_ERROR_LOG_AVAIL = 0x20,
-	OPAL_EVENT_ERROR_LOG = 0x40,
-	OPAL_EVENT_EPOW = 0x80,
-	OPAL_EVENT_LED_STATUS = 0x100
-};
-
-/* Machine check related definitions */
-enum OpalMCE_Version {
-	OpalMCE_V1 = 1,
-};
-
-enum OpalMCE_Severity {
-	OpalMCE_SEV_NO_ERROR = 0,
-	OpalMCE_SEV_WARNING = 1,
-	OpalMCE_SEV_ERROR_SYNC = 2,
-	OpalMCE_SEV_FATAL = 3,
-};
-
-enum OpalMCE_Disposition {
-	OpalMCE_DISPOSITION_RECOVERED = 0,
-	OpalMCE_DISPOSITION_NOT_RECOVERED = 1,
-};
-
-enum OpalMCE_Initiator {
-	OpalMCE_INITIATOR_UNKNOWN = 0,
-	OpalMCE_INITIATOR_CPU = 1,
-};
-
-enum OpalMCE_ErrorType {
-	OpalMCE_ERROR_TYPE_UNKNOWN = 0,
-	OpalMCE_ERROR_TYPE_UE = 1,
-	OpalMCE_ERROR_TYPE_SLB = 2,
-	OpalMCE_ERROR_TYPE_ERAT = 3,
-	OpalMCE_ERROR_TYPE_TLB = 4,
-};
-
-enum OpalMCE_UeErrorType {
-	OpalMCE_UE_ERROR_INDETERMINATE = 0,
-	OpalMCE_UE_ERROR_IFETCH = 1,
-	OpalMCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH = 2,
-	OpalMCE_UE_ERROR_LOAD_STORE = 3,
-	OpalMCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE = 4,
-};
-
-enum OpalMCE_SlbErrorType {
-	OpalMCE_SLB_ERROR_INDETERMINATE = 0,
-	OpalMCE_SLB_ERROR_PARITY = 1,
-	OpalMCE_SLB_ERROR_MULTIHIT = 2,
-};
-
-enum OpalMCE_EratErrorType {
-	OpalMCE_ERAT_ERROR_INDETERMINATE = 0,
-	OpalMCE_ERAT_ERROR_PARITY = 1,
-	OpalMCE_ERAT_ERROR_MULTIHIT = 2,
-};
-
-enum OpalMCE_TlbErrorType {
-	OpalMCE_TLB_ERROR_INDETERMINATE = 0,
-	OpalMCE_TLB_ERROR_PARITY = 1,
-	OpalMCE_TLB_ERROR_MULTIHIT = 2,
-};
-
-enum OpalThreadStatus {
-	OPAL_THREAD_INACTIVE = 0x0,
-	OPAL_THREAD_STARTED = 0x1
-};
-
-enum OpalPciBusCompare {
-	OpalPciBusAny	= 0,	/* Any bus number match */
-	OpalPciBus3Bits	= 2,	/* Match top 3 bits of bus number */
-	OpalPciBus4Bits	= 3,	/* Match top 4 bits of bus number */
-	OpalPciBus5Bits	= 4,	/* Match top 5 bits of bus number */
-	OpalPciBus6Bits	= 5,	/* Match top 6 bits of bus number */
-	OpalPciBus7Bits	= 6,	/* Match top 7 bits of bus number */
-	OpalPciBusAll	= 7,	/* Match bus number exactly */
-};
-
-enum OpalDeviceCompare {
-	OPAL_IGNORE_RID_DEVICE_NUMBER = 0,
-	OPAL_COMPARE_RID_DEVICE_NUMBER = 1
-};
-
-enum OpalFuncCompare {
-	OPAL_IGNORE_RID_FUNCTION_NUMBER = 0,
-	OPAL_COMPARE_RID_FUNCTION_NUMBER = 1
-};
-
-enum OpalPeAction {
-	OPAL_UNMAP_PE = 0,
-	OPAL_MAP_PE = 1
-};
-
-enum OpalPeltvAction {
-	OPAL_REMOVE_PE_FROM_DOMAIN = 0,
-	OPAL_ADD_PE_TO_DOMAIN = 1
-};
-
-enum OpalMveEnableAction {
-	OPAL_DISABLE_MVE = 0,
-	OPAL_ENABLE_MVE = 1
-};
-
-enum OpalPciResetAndReinitScope {
-	OPAL_PHB_COMPLETE = 1, OPAL_PCI_LINK = 2, OPAL_PHB_ERROR = 3,
-	OPAL_PCI_HOT_RESET = 4, OPAL_PCI_FUNDAMENTAL_RESET = 5,
-	OPAL_PCI_IODA_TABLE_RESET = 6,
-};
-
-enum OpalPciResetState {
-	OPAL_DEASSERT_RESET = 0,
-	OPAL_ASSERT_RESET = 1
-};
-
-enum OpalPciMaskAction {
-	OPAL_UNMASK_ERROR_TYPE = 0,
-	OPAL_MASK_ERROR_TYPE = 1
-};
-
-enum OpalSlotLedType {
-	OPAL_SLOT_LED_ID_TYPE = 0,
-	OPAL_SLOT_LED_FAULT_TYPE = 1
-};
-
-enum OpalLedAction {
-	OPAL_TURN_OFF_LED = 0,
-	OPAL_TURN_ON_LED = 1,
-	OPAL_QUERY_LED_STATE_AFTER_BUSY = 2
-};
-
-enum OpalEpowStatus {
-	OPAL_EPOW_NONE = 0,
-	OPAL_EPOW_UPS = 1,
-	OPAL_EPOW_OVER_AMBIENT_TEMP = 2,
-	OPAL_EPOW_OVER_INTERNAL_TEMP = 3
-};
-
-struct opal_machine_check_event {
-	enum OpalMCE_Version	version:8;	/* 0x00 */
-	uint8_t			in_use;		/* 0x01 */
-	enum OpalMCE_Severity	severity:8;	/* 0x02 */
-	enum OpalMCE_Initiator	initiator:8;	/* 0x03 */
-	enum OpalMCE_ErrorType	error_type:8;	/* 0x04 */
-	enum OpalMCE_Disposition disposition:8; /* 0x05 */
-	uint8_t			reserved_1[2];	/* 0x06 */
-	uint64_t		gpr3;		/* 0x08 */
-	uint64_t		srr0;		/* 0x10 */
-	uint64_t		srr1;		/* 0x18 */
-	union {					/* 0x20 */
-		struct {
-			enum OpalMCE_UeErrorType ue_error_type:8;
-			uint8_t		effective_address_provided;
-			uint8_t		physical_address_provided;
-			uint8_t		reserved_1[5];
-			uint64_t	effective_address;
-			uint64_t	physical_address;
-			uint8_t		reserved_2[8];
-		} ue_error;
-
-		struct {
-			enum OpalMCE_SlbErrorType slb_error_type:8;
-			uint8_t		effective_address_provided;
-			uint8_t		reserved_1[6];
-			uint64_t	effective_address;
-			uint8_t		reserved_2[16];
-		} slb_error;
-
-		struct {
-			enum OpalMCE_EratErrorType erat_error_type:8;
-			uint8_t		effective_address_provided;
-			uint8_t		reserved_1[6];
-			uint64_t	effective_address;
-			uint8_t		reserved_2[16];
-		} erat_error;
-
-		struct {
-			enum OpalMCE_TlbErrorType tlb_error_type:8;
-			uint8_t		effective_address_provided;
-			uint8_t		reserved_1[6];
-			uint64_t	effective_address;
-			uint8_t		reserved_2[16];
-		} tlb_error;
-	} u;
-};
-
-/**
- * This structure defines the overlay which will be used to store PHB error
- * data upon request.
- */
-enum {
-	OPAL_P7IOC_NUM_PEST_REGS = 128,
-};
-
-struct OpalIoP7IOCPhbErrorData {
-	uint32_t brdgCtl;
-
-	// P7IOC utl regs
-	uint32_t portStatusReg;
-	uint32_t rootCmplxStatus;
-	uint32_t busAgentStatus;
-
-	// P7IOC cfg regs
-	uint32_t deviceStatus;
-	uint32_t slotStatus;
-	uint32_t linkStatus;
-	uint32_t devCmdStatus;
-	uint32_t devSecStatus;
-
-	// cfg AER regs
-	uint32_t rootErrorStatus;
-	uint32_t uncorrErrorStatus;
-	uint32_t corrErrorStatus;
-	uint32_t tlpHdr1;
-	uint32_t tlpHdr2;
-	uint32_t tlpHdr3;
-	uint32_t tlpHdr4;
-	uint32_t sourceId;
-
-	uint32_t rsv3;
-
-	// Record data about the call to allocate a buffer.
-	uint64_t errorClass;
-	uint64_t correlator;
-
-	//P7IOC MMIO Error Regs
-	uint64_t p7iocPlssr;                // n120
-	uint64_t p7iocCsr;                  // n110
-	uint64_t lemFir;                    // nC00
-	uint64_t lemErrorMask;              // nC18
-	uint64_t lemWOF;                    // nC40
-	uint64_t phbErrorStatus;            // nC80
-	uint64_t phbFirstErrorStatus;       // nC88
-	uint64_t phbErrorLog0;              // nCC0
-	uint64_t phbErrorLog1;              // nCC8
-	uint64_t mmioErrorStatus;           // nD00
-	uint64_t mmioFirstErrorStatus;      // nD08
-	uint64_t mmioErrorLog0;             // nD40
-	uint64_t mmioErrorLog1;             // nD48
-	uint64_t dma0ErrorStatus;           // nD80
-	uint64_t dma0FirstErrorStatus;      // nD88
-	uint64_t dma0ErrorLog0;             // nDC0
-	uint64_t dma0ErrorLog1;             // nDC8
-	uint64_t dma1ErrorStatus;           // nE00
-	uint64_t dma1FirstErrorStatus;      // nE08
-	uint64_t dma1ErrorLog0;             // nE40
-	uint64_t dma1ErrorLog1;             // nE48
-	uint64_t pestA[OPAL_P7IOC_NUM_PEST_REGS];
-	uint64_t pestB[OPAL_P7IOC_NUM_PEST_REGS];
-};
-
-typedef struct oppanel_line {
-	const char * 	line;
-	uint64_t 	line_len;
-} oppanel_line_t;
-
-/* API functions */
-int64_t opal_console_write(int64_t term_number, int64_t *length,
-			   const uint8_t *buffer);
-int64_t opal_console_read(int64_t term_number, int64_t *length,
-			  uint8_t *buffer);
-int64_t opal_console_write_buffer_space(int64_t term_number,
-					int64_t *length);
-int64_t opal_rtc_read(uint32_t *year_month_day,
-		      uint64_t *hour_minute_second_millisecond);
-int64_t opal_rtc_write(uint32_t year_month_day,
-		       uint64_t hour_minute_second_millisecond);
-int64_t opal_cec_power_down(uint64_t request);
-int64_t opal_cec_reboot(void);
-int64_t opal_read_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
-int64_t opal_write_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
-int64_t opal_handle_interrupt(uint64_t isn, uint64_t *outstanding_event_mask);
-int64_t opal_poll_events(uint64_t *outstanding_event_mask);
-int64_t opal_pci_set_hub_tce_memory(uint64_t hub_id, uint64_t tce_mem_addr,
-				    uint64_t tce_mem_size);
-int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, uint64_t tce_mem_addr,
-				    uint64_t tce_mem_size);
-int64_t opal_pci_config_read_byte(uint64_t phb_id, uint64_t bus_dev_func,
-				  uint64_t offset, uint8_t *data);
-int64_t opal_pci_config_read_half_word(uint64_t phb_id, uint64_t bus_dev_func,
-				       uint64_t offset, uint16_t *data);
-int64_t opal_pci_config_read_word(uint64_t phb_id, uint64_t bus_dev_func,
-				  uint64_t offset, uint32_t *data);
-int64_t opal_pci_config_write_byte(uint64_t phb_id, uint64_t bus_dev_func,
-				   uint64_t offset, uint8_t data);
-int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func,
-					uint64_t offset, uint16_t data);
-int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func,
-				   uint64_t offset, uint32_t data);
-int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority);
-int64_t opal_get_xive(uint32_t isn, uint16_t *server, uint8_t *priority);
-int64_t opal_register_exception_handler(uint64_t opal_exception,
-					uint64_t handler_address,
-					uint64_t glue_cache_line);
-int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number,
-				   uint8_t *freeze_state,
-				   uint16_t *pci_error_type,
-				   uint64_t *phb_status);
-int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number,
-				  uint64_t eeh_action_token);
-int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state);
-
-
-
-int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type,
-				 uint16_t window_num, uint16_t enable);
-int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type,
-				    uint16_t window_num,
-				    uint64_t starting_real_address,
-				    uint64_t starting_pci_address,
-				    uint16_t segment_size);
-int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number,
-				    uint16_t window_type, uint16_t window_num,
-				    uint16_t segment_num);
-int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr,
-				      uint64_t ivt_addr, uint64_t ivt_len,
-				      uint64_t reject_array_addr,
-				      uint64_t peltv_addr);
-int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t bus_dev_func,
-			uint8_t bus_compare, uint8_t dev_compare, uint8_t func_compare,
-			uint8_t pe_action);
-int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe,
-			   uint8_t state);
-int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, uint32_t pe_number);
-int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number,
-				uint32_t state);
-int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number,
-				  uint8_t *p_bit, uint8_t *q_bit);
-int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number,
-				  uint8_t p_bit, uint8_t q_bit);
-int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number,
-			     uint32_t xive_num);
-int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num,
-			     int32_t *interrupt_source_number);
-int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num,
-			uint8_t msi_range, uint32_t *msi_address,
-			uint32_t *message_data);
-int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number,
-			uint32_t xive_num, uint8_t msi_range,
-			uint64_t *msi_address, uint32_t *message_data);
-int64_t opal_start_cpu(uint64_t thread_number, uint64_t start_address);
-int64_t opal_query_cpu_status(uint64_t thread_number, uint8_t *thread_status);
-int64_t opal_write_oppanel(oppanel_line_t *lines, uint64_t num_lines);
-int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t window_id,
-				   uint16_t tce_levels, uint64_t tce_table_addr,
-				   uint64_t tce_table_size, uint64_t tce_page_size);
-int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number,
-					uint16_t dma_window_number, uint64_t pci_start_addr,
-					uint64_t pci_mem_size);
-int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, uint8_t assert_state);
-
-int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer, uint64_t diag_buffer_len);
-int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer, uint64_t diag_buffer_len);
-int64_t opal_pci_fence_phb(uint64_t phb_id);
-int64_t opal_pci_reinit(uint64_t phb_id, uint8_t reinit_scope);
-int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action);
-int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
-int64_t opal_get_epow_status(uint64_t *status);
-int64_t opal_set_system_attention_led(uint8_t led_action);
-
-/* Internal functions */
-extern int early_init_dt_scan_opal(unsigned long node, const char *uname, int depth, void *data);
-
-extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
-extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
-
-extern void hvc_opal_init_early(void);
-
-/* Internal functions */
-extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
-				   int depth, void *data);
-
-extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
-extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
-
-extern void hvc_opal_init_early(void);
-
-struct rtc_time;
-extern int opal_set_rtc_time(struct rtc_time *tm);
-extern void opal_get_rtc_time(struct rtc_time *tm);
-extern unsigned long opal_get_boot_time(void);
-extern void opal_nvram_init(void);
-
-extern int opal_machine_check(struct pt_regs *regs);
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* __OPAL_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/oprofile_impl.h b/ANDROID_3.4.5/arch/powerpc/include/asm/oprofile_impl.h
deleted file mode 100644
index 639dc960..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/oprofile_impl.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
- *
- * Based on alpha version.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_POWERPC_OPROFILE_IMPL_H
-#define _ASM_POWERPC_OPROFILE_IMPL_H
-#ifdef __KERNEL__
-
-#define OP_MAX_COUNTER 8
-
-/* Per-counter configuration as set via oprofilefs.  */
-struct op_counter_config {
-	unsigned long enabled;
-	unsigned long event;
-	unsigned long count;
-	/* Classic doesn't support per-counter user/kernel selection */
-	unsigned long kernel;
-	unsigned long user;
-	unsigned long unit_mask;
-};
-
-/* System-wide configuration as set via oprofilefs.  */
-struct op_system_config {
-#ifdef CONFIG_PPC64
-	unsigned long mmcr0;
-	unsigned long mmcr1;
-	unsigned long mmcra;
-#ifdef CONFIG_OPROFILE_CELL
-	/* Register for oprofile user tool to check cell kernel profiling
-	 * suport.
-	 */
-	unsigned long cell_support;
-#endif
-#endif
-	unsigned long enable_kernel;
-	unsigned long enable_user;
-};
-
-/* Per-arch configuration */
-struct op_powerpc_model {
-	int (*reg_setup) (struct op_counter_config *,
-			   struct op_system_config *,
-			   int num_counters);
-	int  (*cpu_setup) (struct op_counter_config *);
-	int  (*start) (struct op_counter_config *);
-	int  (*global_start) (struct op_counter_config *);
-	void (*stop) (void);
-	void (*global_stop) (void);
-	int (*sync_start)(void);
-	int (*sync_stop)(void);
-	void (*handle_interrupt) (struct pt_regs *,
-				  struct op_counter_config *);
-	int num_counters;
-};
-
-extern struct op_powerpc_model op_model_fsl_emb;
-extern struct op_powerpc_model op_model_rs64;
-extern struct op_powerpc_model op_model_power4;
-extern struct op_powerpc_model op_model_7450;
-extern struct op_powerpc_model op_model_cell;
-extern struct op_powerpc_model op_model_pa6t;
-
-
-/* All the classic PPC parts use these */
-static inline unsigned int classic_ctr_read(unsigned int i)
-{
-	switch(i) {
-	case 0:
-		return mfspr(SPRN_PMC1);
-	case 1:
-		return mfspr(SPRN_PMC2);
-	case 2:
-		return mfspr(SPRN_PMC3);
-	case 3:
-		return mfspr(SPRN_PMC4);
-	case 4:
-		return mfspr(SPRN_PMC5);
-	case 5:
-		return mfspr(SPRN_PMC6);
-
-/* No PPC32 chip has more than 6 so far */
-#ifdef CONFIG_PPC64
-	case 6:
-		return mfspr(SPRN_PMC7);
-	case 7:
-		return mfspr(SPRN_PMC8);
-#endif
-	default:
-		return 0;
-	}
-}
-
-static inline void classic_ctr_write(unsigned int i, unsigned int val)
-{
-	switch(i) {
-	case 0:
-		mtspr(SPRN_PMC1, val);
-		break;
-	case 1:
-		mtspr(SPRN_PMC2, val);
-		break;
-	case 2:
-		mtspr(SPRN_PMC3, val);
-		break;
-	case 3:
-		mtspr(SPRN_PMC4, val);
-		break;
-	case 4:
-		mtspr(SPRN_PMC5, val);
-		break;
-	case 5:
-		mtspr(SPRN_PMC6, val);
-		break;
-
-/* No PPC32 chip has more than 6, yet */
-#ifdef CONFIG_PPC64
-	case 6:
-		mtspr(SPRN_PMC7, val);
-		break;
-	case 7:
-		mtspr(SPRN_PMC8, val);
-		break;
-#endif
-	default:
-		break;
-	}
-}
-
-
-extern void op_powerpc_backtrace(struct pt_regs * const regs, unsigned int depth);
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_OPROFILE_IMPL_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/pSeries_reconfig.h b/ANDROID_3.4.5/arch/powerpc/include/asm/pSeries_reconfig.h
deleted file mode 100644
index 23cd6cc3..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/pSeries_reconfig.h
+++ /dev/null
@@ -1,35 +0,0 @@
-#ifndef _PPC64_PSERIES_RECONFIG_H
-#define _PPC64_PSERIES_RECONFIG_H
-#ifdef __KERNEL__
-
-#include <linux/notifier.h>
-
-/*
- * Use this API if your code needs to know about OF device nodes being
- * added or removed on pSeries systems.
- */
-
-#define PSERIES_RECONFIG_ADD		0x0001
-#define PSERIES_RECONFIG_REMOVE		0x0002
-#define PSERIES_DRCONF_MEM_ADD		0x0003
-#define PSERIES_DRCONF_MEM_REMOVE	0x0004
-
-#ifdef CONFIG_PPC_PSERIES
-extern int pSeries_reconfig_notifier_register(struct notifier_block *);
-extern void pSeries_reconfig_notifier_unregister(struct notifier_block *);
-extern int pSeries_reconfig_notify(unsigned long action, void *p);
-/* Not the best place to put this, will be fixed when we move some
- * of the rtas suspend-me stuff to pseries */
-extern void pSeries_coalesce_init(void);
-#else /* !CONFIG_PPC_PSERIES */
-static inline int pSeries_reconfig_notifier_register(struct notifier_block *nb)
-{
-	return 0;
-}
-static inline void pSeries_reconfig_notifier_unregister(struct notifier_block *nb) { }
-static inline void pSeries_coalesce_init(void) { }
-#endif /* CONFIG_PPC_PSERIES */
-
-
-#endif /* __KERNEL__ */
-#endif /* _PPC64_PSERIES_RECONFIG_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/paca.h b/ANDROID_3.4.5/arch/powerpc/include/asm/paca.h
deleted file mode 100644
index daf813fe..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/paca.h
+++ /dev/null
@@ -1,183 +0,0 @@
-/*
- * This control block defines the PACA which defines the processor
- * specific data for each logical processor on the system.
- * There are some pointers defined that are utilized by PLIC.
- *
- * C 2001 PPC 64 Team, IBM Corp
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef _ASM_POWERPC_PACA_H
-#define _ASM_POWERPC_PACA_H
-#ifdef __KERNEL__
-
-#ifdef CONFIG_PPC64
-
-#include <linux/init.h>
-#include <asm/types.h>
-#include <asm/lppaca.h>
-#include <asm/mmu.h>
-#include <asm/page.h>
-#include <asm/exception-64e.h>
-#ifdef CONFIG_KVM_BOOK3S_64_HANDLER
-#include <asm/kvm_book3s_asm.h>
-#endif
-
-register struct paca_struct *local_paca asm("r13");
-
-#if defined(CONFIG_DEBUG_PREEMPT) && defined(CONFIG_SMP)
-extern unsigned int debug_smp_processor_id(void); /* from linux/smp.h */
-/*
- * Add standard checks that preemption cannot occur when using get_paca():
- * otherwise the paca_struct it points to may be the wrong one just after.
- */
-#define get_paca()	((void) debug_smp_processor_id(), local_paca)
-#else
-#define get_paca()	local_paca
-#endif
-
-#define get_lppaca()	(get_paca()->lppaca_ptr)
-#define get_slb_shadow()	(get_paca()->slb_shadow_ptr)
-
-struct task_struct;
-struct opal_machine_check_event;
-
-/*
- * Defines the layout of the paca.
- *
- * This structure is not directly accessed by firmware or the service
- * processor.
- */
-struct paca_struct {
-#ifdef CONFIG_PPC_BOOK3S
-	/*
-	 * Because hw_cpu_id, unlike other paca fields, is accessed
-	 * routinely from other CPUs (from the IRQ code), we stick to
-	 * read-only (after boot) fields in the first cacheline to
-	 * avoid cacheline bouncing.
-	 */
-
-	struct lppaca *lppaca_ptr;	/* Pointer to LpPaca for PLIC */
-#endif /* CONFIG_PPC_BOOK3S */
-	/*
-	 * MAGIC: the spinlock functions in arch/powerpc/lib/locks.c 
-	 * load lock_token and paca_index with a single lwz
-	 * instruction.  They must travel together and be properly
-	 * aligned.
-	 */
-	u16 lock_token;			/* Constant 0x8000, used in locks */
-	u16 paca_index;			/* Logical processor number */
-
-	u64 kernel_toc;			/* Kernel TOC address */
-	u64 kernelbase;			/* Base address of kernel */
-	u64 kernel_msr;			/* MSR while running in kernel */
-#ifdef CONFIG_PPC_STD_MMU_64
-	u64 stab_real;			/* Absolute address of segment table */
-	u64 stab_addr;			/* Virtual address of segment table */
-#endif /* CONFIG_PPC_STD_MMU_64 */
-	void *emergency_sp;		/* pointer to emergency stack */
-	u64 data_offset;		/* per cpu data offset */
-	s16 hw_cpu_id;			/* Physical processor number */
-	u8 cpu_start;			/* At startup, processor spins until */
-					/* this becomes non-zero. */
-	u8 kexec_state;		/* set when kexec down has irqs off */
-#ifdef CONFIG_PPC_STD_MMU_64
-	struct slb_shadow *slb_shadow_ptr;
-	struct dtl_entry *dispatch_log;
-	struct dtl_entry *dispatch_log_end;
-
-	/*
-	 * Now, starting in cacheline 2, the exception save areas
-	 */
-	/* used for most interrupts/exceptions */
-	u64 exgen[11] __attribute__((aligned(0x80)));
-	u64 exmc[11];		/* used for machine checks */
-	u64 exslb[11];		/* used for SLB/segment table misses
- 				 * on the linear mapping */
-	/* SLB related definitions */
-	u16 vmalloc_sllp;
-	u16 slb_cache_ptr;
-	u16 slb_cache[SLB_CACHE_ENTRIES];
-#endif /* CONFIG_PPC_STD_MMU_64 */
-
-#ifdef CONFIG_PPC_BOOK3E
-	u64 exgen[8] __attribute__((aligned(0x80)));
-	/* Keep pgd in the same cacheline as the start of extlb */
-	pgd_t *pgd __attribute__((aligned(0x80))); /* Current PGD */
-	pgd_t *kernel_pgd;		/* Kernel PGD */
-	/* We can have up to 3 levels of reentrancy in the TLB miss handler */
-	u64 extlb[3][EX_TLB_SIZE / sizeof(u64)];
-	u64 exmc[8];		/* used for machine checks */
-	u64 excrit[8];		/* used for crit interrupts */
-	u64 exdbg[8];		/* used for debug interrupts */
-
-	/* Kernel stack pointers for use by special exceptions */
-	void *mc_kstack;
-	void *crit_kstack;
-	void *dbg_kstack;
-#endif /* CONFIG_PPC_BOOK3E */
-
-	mm_context_t context;
-
-	/*
-	 * then miscellaneous read-write fields
-	 */
-	struct task_struct *__current;	/* Pointer to current */
-	u64 kstack;			/* Saved Kernel stack addr */
-	u64 stab_rr;			/* stab/slb round-robin counter */
-	u64 saved_r1;			/* r1 save for RTAS calls or PM */
-	u64 saved_msr;			/* MSR saved here by enter_rtas */
-	u16 trap_save;			/* Used when bad stack is encountered */
-	u8 soft_enabled;		/* irq soft-enable flag */
-	u8 irq_happened;		/* irq happened while soft-disabled */
-	u8 io_sync;			/* writel() needs spin_unlock sync */
-	u8 irq_work_pending;		/* IRQ_WORK interrupt while soft-disable */
-	u8 nap_state_lost;		/* NV GPR values lost in power7_idle */
-
-#ifdef CONFIG_PPC_POWERNV
-	/* Pointer to OPAL machine check event structure set by the
-	 * early exception handler for use by high level C handler
-	 */
-	struct opal_machine_check_event *opal_mc_evt;
-#endif
-
-	/* Stuff for accurate time accounting */
-	u64 user_time;			/* accumulated usermode TB ticks */
-	u64 system_time;		/* accumulated system TB ticks */
-	u64 user_time_scaled;		/* accumulated usermode SPURR ticks */
-	u64 starttime;			/* TB value snapshot */
-	u64 starttime_user;		/* TB value on exit to usermode */
-	u64 startspurr;			/* SPURR value snapshot */
-	u64 utime_sspurr;		/* ->user_time when ->startspurr set */
-	u64 stolen_time;		/* TB ticks taken by hypervisor */
-	u64 dtl_ridx;			/* read index in dispatch log */
-	struct dtl_entry *dtl_curr;	/* pointer corresponding to dtl_ridx */
-
-#ifdef CONFIG_KVM_BOOK3S_HANDLER
-#ifdef CONFIG_KVM_BOOK3S_PR
-	/* We use this to store guest state in */
-	struct kvmppc_book3s_shadow_vcpu shadow_vcpu;
-#endif
-	struct kvmppc_host_state kvm_hstate;
-#endif
-};
-
-extern struct paca_struct *paca;
-extern __initdata struct paca_struct boot_paca;
-extern void initialise_paca(struct paca_struct *new_paca, int cpu);
-extern void setup_paca(struct paca_struct *new_paca);
-extern void allocate_pacas(void);
-extern void free_unused_pacas(void);
-
-#else /* CONFIG_PPC64 */
-
-static inline void allocate_pacas(void) { };
-static inline void free_unused_pacas(void) { };
-
-#endif /* CONFIG_PPC64 */
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_PACA_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/page.h b/ANDROID_3.4.5/arch/powerpc/include/asm/page.h
deleted file mode 100644
index f072e974..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/page.h
+++ /dev/null
@@ -1,386 +0,0 @@
-#ifndef _ASM_POWERPC_PAGE_H
-#define _ASM_POWERPC_PAGE_H
-
-/*
- * Copyright (C) 2001,2005 IBM Corporation.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef __ASSEMBLY__
-#include <linux/types.h>
-#else
-#include <asm/types.h>
-#endif
-#include <asm/asm-compat.h>
-#include <asm/kdump.h>
-
-/*
- * On regular PPC32 page size is 4K (but we support 4K/16K/64K/256K pages
- * on PPC44x). For PPC64 we support either 4K or 64K software
- * page size. When using 64K pages however, whether we are really supporting
- * 64K pages in HW or not is irrelevant to those definitions.
- */
-#if defined(CONFIG_PPC_256K_PAGES)
-#define PAGE_SHIFT		18
-#elif defined(CONFIG_PPC_64K_PAGES)
-#define PAGE_SHIFT		16
-#elif defined(CONFIG_PPC_16K_PAGES)
-#define PAGE_SHIFT		14
-#else
-#define PAGE_SHIFT		12
-#endif
-
-#define PAGE_SIZE		(ASM_CONST(1) << PAGE_SHIFT)
-
-#ifndef __ASSEMBLY__
-#ifdef CONFIG_HUGETLB_PAGE
-extern unsigned int HPAGE_SHIFT;
-#else
-#define HPAGE_SHIFT PAGE_SHIFT
-#endif
-#define HPAGE_SIZE		((1UL) << HPAGE_SHIFT)
-#define HPAGE_MASK		(~(HPAGE_SIZE - 1))
-#define HUGETLB_PAGE_ORDER	(HPAGE_SHIFT - PAGE_SHIFT)
-#define HUGE_MAX_HSTATE		(MMU_PAGE_COUNT-1)
-#endif
-
-/* We do define AT_SYSINFO_EHDR but don't use the gate mechanism */
-#define __HAVE_ARCH_GATE_AREA		1
-
-/*
- * Subtle: (1 << PAGE_SHIFT) is an int, not an unsigned long. So if we
- * assign PAGE_MASK to a larger type it gets extended the way we want
- * (i.e. with 1s in the high bits)
- */
-#define PAGE_MASK      (~((1 << PAGE_SHIFT) - 1))
-
-/*
- * KERNELBASE is the virtual address of the start of the kernel, it's often
- * the same as PAGE_OFFSET, but _might not be_.
- *
- * The kdump dump kernel is one example where KERNELBASE != PAGE_OFFSET.
- *
- * PAGE_OFFSET is the virtual address of the start of lowmem.
- *
- * PHYSICAL_START is the physical address of the start of the kernel.
- *
- * MEMORY_START is the physical address of the start of lowmem.
- *
- * KERNELBASE, PAGE_OFFSET, and PHYSICAL_START are all configurable on
- * ppc32 and based on how they are set we determine MEMORY_START.
- *
- * For the linear mapping the following equation should be true:
- * KERNELBASE - PAGE_OFFSET = PHYSICAL_START - MEMORY_START
- *
- * Also, KERNELBASE >= PAGE_OFFSET and PHYSICAL_START >= MEMORY_START
- *
- * There are two was to determine a physical address from a virtual one:
- * va = pa + PAGE_OFFSET - MEMORY_START
- * va = pa + KERNELBASE - PHYSICAL_START
- *
- * If you want to know something's offset from the start of the kernel you
- * should subtract KERNELBASE.
- *
- * If you want to test if something's a kernel address, use is_kernel_addr().
- */
-
-#define KERNELBASE      ASM_CONST(CONFIG_KERNEL_START)
-#define PAGE_OFFSET	ASM_CONST(CONFIG_PAGE_OFFSET)
-#define LOAD_OFFSET	ASM_CONST((CONFIG_KERNEL_START-CONFIG_PHYSICAL_START))
-
-#if defined(CONFIG_NONSTATIC_KERNEL)
-#ifndef __ASSEMBLY__
-
-extern phys_addr_t memstart_addr;
-extern phys_addr_t kernstart_addr;
-
-#ifdef CONFIG_RELOCATABLE_PPC32
-extern long long virt_phys_offset;
-#endif
-
-#endif /* __ASSEMBLY__ */
-#define PHYSICAL_START	kernstart_addr
-
-#else	/* !CONFIG_NONSTATIC_KERNEL */
-#define PHYSICAL_START	ASM_CONST(CONFIG_PHYSICAL_START)
-#endif
-
-/* See Description below for VIRT_PHYS_OFFSET */
-#ifdef CONFIG_RELOCATABLE_PPC32
-#define VIRT_PHYS_OFFSET virt_phys_offset
-#else
-#define VIRT_PHYS_OFFSET (KERNELBASE - PHYSICAL_START)
-#endif
-
-
-#ifdef CONFIG_PPC64
-#define MEMORY_START	0UL
-#elif defined(CONFIG_NONSTATIC_KERNEL)
-#define MEMORY_START	memstart_addr
-#else
-#define MEMORY_START	(PHYSICAL_START + PAGE_OFFSET - KERNELBASE)
-#endif
-
-#ifdef CONFIG_FLATMEM
-#define ARCH_PFN_OFFSET		((unsigned long)(MEMORY_START >> PAGE_SHIFT))
-#define pfn_valid(pfn)		((pfn) >= ARCH_PFN_OFFSET && (pfn) < max_mapnr)
-#endif
-
-#define virt_to_page(kaddr)	pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
-#define pfn_to_kaddr(pfn)	__va((pfn) << PAGE_SHIFT)
-#define virt_addr_valid(kaddr)	pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
-
-/*
- * On Book-E parts we need __va to parse the device tree and we can't
- * determine MEMORY_START until then.  However we can determine PHYSICAL_START
- * from information at hand (program counter, TLB lookup).
- *
- * On BookE with RELOCATABLE (RELOCATABLE_PPC32)
- *
- *   With RELOCATABLE_PPC32,  we support loading the kernel at any physical 
- *   address without any restriction on the page alignment.
- *
- *   We find the runtime address of _stext and relocate ourselves based on 
- *   the following calculation:
- *
- *  	  virtual_base = ALIGN_DOWN(KERNELBASE,256M) +
- *  				MODULO(_stext.run,256M)
- *   and create the following mapping:
- *
- * 	  ALIGN_DOWN(_stext.run,256M) => ALIGN_DOWN(KERNELBASE,256M)
- *
- *   When we process relocations, we cannot depend on the
- *   existing equation for the __va()/__pa() translations:
- *
- * 	   __va(x) = (x)  - PHYSICAL_START + KERNELBASE
- *
- *   Where:
- *   	 PHYSICAL_START = kernstart_addr = Physical address of _stext
- *  	 KERNELBASE = Compiled virtual address of _stext.
- *
- *   This formula holds true iff, kernel load address is TLB page aligned.
- *
- *   In our case, we need to also account for the shift in the kernel Virtual 
- *   address.
- *
- *   E.g.,
- *
- *   Let the kernel be loaded at 64MB and KERNELBASE be 0xc0000000 (same as PAGE_OFFSET).
- *   In this case, we would be mapping 0 to 0xc0000000, and kernstart_addr = 64M
- *
- *   Now __va(1MB) = (0x100000) - (0x4000000) + 0xc0000000
- *                 = 0xbc100000 , which is wrong.
- *
- *   Rather, it should be : 0xc0000000 + 0x100000 = 0xc0100000
- *      	according to our mapping.
- *
- *   Hence we use the following formula to get the translations right:
- *
- * 	  __va(x) = (x) - [ PHYSICAL_START - Effective KERNELBASE ]
- *
- * 	  Where :
- * 		PHYSICAL_START = dynamic load address.(kernstart_addr variable)
- * 		Effective KERNELBASE = virtual_base =
- * 				     = ALIGN_DOWN(KERNELBASE,256M) +
- * 						MODULO(PHYSICAL_START,256M)
- *
- * 	To make the cost of __va() / __pa() more light weight, we introduce
- * 	a new variable virt_phys_offset, which will hold :
- *
- * 	virt_phys_offset = Effective KERNELBASE - PHYSICAL_START
- * 			 = ALIGN_DOWN(KERNELBASE,256M) - 
- * 			 	ALIGN_DOWN(PHYSICALSTART,256M)
- *
- * 	Hence :
- *
- * 	__va(x) = x - PHYSICAL_START + Effective KERNELBASE
- * 		= x + virt_phys_offset
- *
- * 		and
- * 	__pa(x) = x + PHYSICAL_START - Effective KERNELBASE
- * 		= x - virt_phys_offset
- * 		
- * On non-Book-E PPC64 PAGE_OFFSET and MEMORY_START are constants so use
- * the other definitions for __va & __pa.
- */
-#ifdef CONFIG_BOOKE
-#define __va(x) ((void *)(unsigned long)((phys_addr_t)(x) + VIRT_PHYS_OFFSET))
-#define __pa(x) ((unsigned long)(x) - VIRT_PHYS_OFFSET)
-#else
-#define __va(x) ((void *)(unsigned long)((phys_addr_t)(x) + PAGE_OFFSET - MEMORY_START))
-#define __pa(x) ((unsigned long)(x) - PAGE_OFFSET + MEMORY_START)
-#endif
-
-/*
- * Unfortunately the PLT is in the BSS in the PPC32 ELF ABI,
- * and needs to be executable.  This means the whole heap ends
- * up being executable.
- */
-#define VM_DATA_DEFAULT_FLAGS32	(VM_READ | VM_WRITE | VM_EXEC | \
-				 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
-
-#define VM_DATA_DEFAULT_FLAGS64	(VM_READ | VM_WRITE | \
-				 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
-
-#ifdef __powerpc64__
-#include <asm/page_64.h>
-#else
-#include <asm/page_32.h>
-#endif
-
-/* align addr on a size boundary - adjust address up/down if needed */
-#define _ALIGN_UP(addr,size)	(((addr)+((size)-1))&(~((size)-1)))
-#define _ALIGN_DOWN(addr,size)	((addr)&(~((size)-1)))
-
-/* align addr on a size boundary - adjust address up if needed */
-#define _ALIGN(addr,size)     _ALIGN_UP(addr,size)
-
-/*
- * Don't compare things with KERNELBASE or PAGE_OFFSET to test for
- * "kernelness", use is_kernel_addr() - it should do what you want.
- */
-#ifdef CONFIG_PPC_BOOK3E_64
-#define is_kernel_addr(x)	((x) >= 0x8000000000000000ul)
-#else
-#define is_kernel_addr(x)	((x) >= PAGE_OFFSET)
-#endif
-
-/*
- * Use the top bit of the higher-level page table entries to indicate whether
- * the entries we point to contain hugepages.  This works because we know that
- * the page tables live in kernel space.  If we ever decide to support having
- * page tables at arbitrary addresses, this breaks and will have to change.
- */
-#ifdef CONFIG_PPC64
-#define PD_HUGE 0x8000000000000000
-#else
-#define PD_HUGE 0x80000000
-#endif
-
-/*
- * Some number of bits at the level of the page table that points to
- * a hugepte are used to encode the size.  This masks those bits.
- */
-#define HUGEPD_SHIFT_MASK     0x3f
-
-#ifndef __ASSEMBLY__
-
-#undef STRICT_MM_TYPECHECKS
-
-#ifdef STRICT_MM_TYPECHECKS
-/* These are used to make use of C type-checking. */
-
-/* PTE level */
-typedef struct { pte_basic_t pte; } pte_t;
-#define pte_val(x)	((x).pte)
-#define __pte(x)	((pte_t) { (x) })
-
-/* 64k pages additionally define a bigger "real PTE" type that gathers
- * the "second half" part of the PTE for pseudo 64k pages
- */
-#if defined(CONFIG_PPC_64K_PAGES) && defined(CONFIG_PPC_STD_MMU_64)
-typedef struct { pte_t pte; unsigned long hidx; } real_pte_t;
-#else
-typedef struct { pte_t pte; } real_pte_t;
-#endif
-
-/* PMD level */
-#ifdef CONFIG_PPC64
-typedef struct { unsigned long pmd; } pmd_t;
-#define pmd_val(x)	((x).pmd)
-#define __pmd(x)	((pmd_t) { (x) })
-
-/* PUD level exusts only on 4k pages */
-#ifndef CONFIG_PPC_64K_PAGES
-typedef struct { unsigned long pud; } pud_t;
-#define pud_val(x)	((x).pud)
-#define __pud(x)	((pud_t) { (x) })
-#endif /* !CONFIG_PPC_64K_PAGES */
-#endif /* CONFIG_PPC64 */
-
-/* PGD level */
-typedef struct { unsigned long pgd; } pgd_t;
-#define pgd_val(x)	((x).pgd)
-#define __pgd(x)	((pgd_t) { (x) })
-
-/* Page protection bits */
-typedef struct { unsigned long pgprot; } pgprot_t;
-#define pgprot_val(x)	((x).pgprot)
-#define __pgprot(x)	((pgprot_t) { (x) })
-
-#else
-
-/*
- * .. while these make it easier on the compiler
- */
-
-typedef pte_basic_t pte_t;
-#define pte_val(x)	(x)
-#define __pte(x)	(x)
-
-#if defined(CONFIG_PPC_64K_PAGES) && defined(CONFIG_PPC_STD_MMU_64)
-typedef struct { pte_t pte; unsigned long hidx; } real_pte_t;
-#else
-typedef pte_t real_pte_t;
-#endif
-
-
-#ifdef CONFIG_PPC64
-typedef unsigned long pmd_t;
-#define pmd_val(x)	(x)
-#define __pmd(x)	(x)
-
-#ifndef CONFIG_PPC_64K_PAGES
-typedef unsigned long pud_t;
-#define pud_val(x)	(x)
-#define __pud(x)	(x)
-#endif /* !CONFIG_PPC_64K_PAGES */
-#endif /* CONFIG_PPC64 */
-
-typedef unsigned long pgd_t;
-#define pgd_val(x)	(x)
-#define pgprot_val(x)	(x)
-
-typedef unsigned long pgprot_t;
-#define __pgd(x)	(x)
-#define __pgprot(x)	(x)
-
-#endif
-
-typedef struct { signed long pd; } hugepd_t;
-
-#ifdef CONFIG_HUGETLB_PAGE
-static inline int hugepd_ok(hugepd_t hpd)
-{
-	return (hpd.pd > 0);
-}
-
-#define is_hugepd(pdep)               (hugepd_ok(*((hugepd_t *)(pdep))))
-#else /* CONFIG_HUGETLB_PAGE */
-#define is_hugepd(pdep)			0
-#endif /* CONFIG_HUGETLB_PAGE */
-
-struct page;
-extern void clear_user_page(void *page, unsigned long vaddr, struct page *pg);
-extern void copy_user_page(void *to, void *from, unsigned long vaddr,
-		struct page *p);
-extern int page_is_ram(unsigned long pfn);
-extern int devmem_is_allowed(unsigned long pfn);
-
-#ifdef CONFIG_PPC_SMLPAR
-void arch_free_page(struct page *page, int order);
-#define HAVE_ARCH_FREE_PAGE
-#endif
-
-struct vm_area_struct;
-
-typedef struct page *pgtable_t;
-
-#include <asm-generic/memory_model.h>
-#endif /* __ASSEMBLY__ */
-
-#endif /* _ASM_POWERPC_PAGE_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/page_32.h b/ANDROID_3.4.5/arch/powerpc/include/asm/page_32.h
deleted file mode 100644
index 68d73b2a..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/page_32.h
+++ /dev/null
@@ -1,51 +0,0 @@
-#ifndef _ASM_POWERPC_PAGE_32_H
-#define _ASM_POWERPC_PAGE_32_H
-
-#if defined(CONFIG_PHYSICAL_ALIGN) && (CONFIG_PHYSICAL_START != 0)
-#if (CONFIG_PHYSICAL_START % CONFIG_PHYSICAL_ALIGN) != 0
-#error "CONFIG_PHYSICAL_START must be a multiple of CONFIG_PHYSICAL_ALIGN"
-#endif
-#endif
-
-#define VM_DATA_DEFAULT_FLAGS	VM_DATA_DEFAULT_FLAGS32
-
-#ifdef CONFIG_NOT_COHERENT_CACHE
-#define ARCH_DMA_MINALIGN	L1_CACHE_BYTES
-#endif
-
-#ifdef CONFIG_PTE_64BIT
-#define PTE_FLAGS_OFFSET	4	/* offset of PTE flags, in bytes */
-#else
-#define PTE_FLAGS_OFFSET	0
-#endif
-
-#ifdef CONFIG_PPC_256K_PAGES
-#define PTE_SHIFT	(PAGE_SHIFT - PTE_T_LOG2 - 2)	/* 1/4 of a page */
-#else
-#define PTE_SHIFT	(PAGE_SHIFT - PTE_T_LOG2)	/* full page */
-#endif
-
-#ifndef __ASSEMBLY__
-/*
- * The basic type of a PTE - 64 bits for those CPUs with > 32 bit
- * physical addressing.
- */
-#ifdef CONFIG_PTE_64BIT
-typedef unsigned long long pte_basic_t;
-#else
-typedef unsigned long pte_basic_t;
-#endif
-
-struct page;
-extern void clear_pages(void *page, int order);
-static inline void clear_page(void *page) { clear_pages(page, 0); }
-extern void copy_page(void *to, void *from);
-
-#include <asm-generic/getorder.h>
-
-#define PGD_T_LOG2	(__builtin_ffs(sizeof(pgd_t)) - 1)
-#define PTE_T_LOG2	(__builtin_ffs(sizeof(pte_t)) - 1)
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* _ASM_POWERPC_PAGE_32_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/page_64.h b/ANDROID_3.4.5/arch/powerpc/include/asm/page_64.h
deleted file mode 100644
index fed85e62..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/page_64.h
+++ /dev/null
@@ -1,161 +0,0 @@
-#ifndef _ASM_POWERPC_PAGE_64_H
-#define _ASM_POWERPC_PAGE_64_H
-
-/*
- * Copyright (C) 2001 PPC64 Team, IBM Corp
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-/*
- * We always define HW_PAGE_SHIFT to 12 as use of 64K pages remains Linux
- * specific, every notion of page number shared with the firmware, TCEs,
- * iommu, etc... still uses a page size of 4K.
- */
-#define HW_PAGE_SHIFT		12
-#define HW_PAGE_SIZE		(ASM_CONST(1) << HW_PAGE_SHIFT)
-#define HW_PAGE_MASK		(~(HW_PAGE_SIZE-1))
-
-/*
- * PAGE_FACTOR is the number of bits factor between PAGE_SHIFT and
- * HW_PAGE_SHIFT, that is 4K pages.
- */
-#define PAGE_FACTOR		(PAGE_SHIFT - HW_PAGE_SHIFT)
-
-/* Segment size; normal 256M segments */
-#define SID_SHIFT		28
-#define SID_MASK		ASM_CONST(0xfffffffff)
-#define ESID_MASK		0xfffffffff0000000UL
-#define GET_ESID(x)		(((x) >> SID_SHIFT) & SID_MASK)
-
-/* 1T segments */
-#define SID_SHIFT_1T		40
-#define SID_MASK_1T		0xffffffUL
-#define ESID_MASK_1T		0xffffff0000000000UL
-#define GET_ESID_1T(x)		(((x) >> SID_SHIFT_1T) & SID_MASK_1T)
-
-#ifndef __ASSEMBLY__
-#include <asm/cache.h>
-
-typedef unsigned long pte_basic_t;
-
-static __inline__ void clear_page(void *addr)
-{
-	unsigned long lines, line_size;
-
-	line_size = ppc64_caches.dline_size;
-	lines = ppc64_caches.dlines_per_page;
-
-	__asm__ __volatile__(
-	"mtctr	%1	# clear_page\n\
-1:      dcbz	0,%0\n\
-	add	%0,%0,%3\n\
-	bdnz+	1b"
-        : "=r" (addr)
-        : "r" (lines), "0" (addr), "r" (line_size)
-	: "ctr", "memory");
-}
-
-extern void copy_page(void *to, void *from);
-
-/* Log 2 of page table size */
-extern u64 ppc64_pft_size;
-
-#endif /* __ASSEMBLY__ */
-
-#ifdef CONFIG_PPC_MM_SLICES
-
-#define SLICE_LOW_SHIFT		28
-#define SLICE_HIGH_SHIFT	40
-
-#define SLICE_LOW_TOP		(0x100000000ul)
-#define SLICE_NUM_LOW		(SLICE_LOW_TOP >> SLICE_LOW_SHIFT)
-#define SLICE_NUM_HIGH		(PGTABLE_RANGE >> SLICE_HIGH_SHIFT)
-
-#define GET_LOW_SLICE_INDEX(addr)	((addr) >> SLICE_LOW_SHIFT)
-#define GET_HIGH_SLICE_INDEX(addr)	((addr) >> SLICE_HIGH_SHIFT)
-
-#ifndef __ASSEMBLY__
-
-struct slice_mask {
-	u16 low_slices;
-	u16 high_slices;
-};
-
-struct mm_struct;
-
-extern unsigned long slice_get_unmapped_area(unsigned long addr,
-					     unsigned long len,
-					     unsigned long flags,
-					     unsigned int psize,
-					     int topdown,
-					     int use_cache);
-
-extern unsigned int get_slice_psize(struct mm_struct *mm,
-				    unsigned long addr);
-
-extern void slice_init_context(struct mm_struct *mm, unsigned int psize);
-extern void slice_set_user_psize(struct mm_struct *mm, unsigned int psize);
-extern void slice_set_range_psize(struct mm_struct *mm, unsigned long start,
-				  unsigned long len, unsigned int psize);
-
-#define slice_mm_new_context(mm)	((mm)->context.id == MMU_NO_CONTEXT)
-
-#endif /* __ASSEMBLY__ */
-#else
-#define slice_init()
-#ifdef CONFIG_PPC_STD_MMU_64
-#define get_slice_psize(mm, addr)	((mm)->context.user_psize)
-#define slice_set_user_psize(mm, psize)		\
-do {						\
-	(mm)->context.user_psize = (psize);	\
-	(mm)->context.sllp = SLB_VSID_USER | mmu_psize_defs[(psize)].sllp; \
-} while (0)
-#else /* CONFIG_PPC_STD_MMU_64 */
-#ifdef CONFIG_PPC_64K_PAGES
-#define get_slice_psize(mm, addr)	MMU_PAGE_64K
-#else /* CONFIG_PPC_64K_PAGES */
-#define get_slice_psize(mm, addr)	MMU_PAGE_4K
-#endif /* !CONFIG_PPC_64K_PAGES */
-#define slice_set_user_psize(mm, psize)	do { BUG(); } while(0)
-#endif /* !CONFIG_PPC_STD_MMU_64 */
-
-#define slice_set_range_psize(mm, start, len, psize)	\
-	slice_set_user_psize((mm), (psize))
-#define slice_mm_new_context(mm)	1
-#endif /* CONFIG_PPC_MM_SLICES */
-
-#ifdef CONFIG_HUGETLB_PAGE
-
-#ifdef CONFIG_PPC_MM_SLICES
-#define HAVE_ARCH_HUGETLB_UNMAPPED_AREA
-#endif
-
-#endif /* !CONFIG_HUGETLB_PAGE */
-
-#define VM_DATA_DEFAULT_FLAGS \
-	(is_32bit_task() ? \
-	 VM_DATA_DEFAULT_FLAGS32 : VM_DATA_DEFAULT_FLAGS64)
-
-/*
- * This is the default if a program doesn't have a PT_GNU_STACK
- * program header entry. The PPC64 ELF ABI has a non executable stack
- * stack by default, so in the absence of a PT_GNU_STACK program header
- * we turn execute permission off.
- */
-#define VM_STACK_DEFAULT_FLAGS32	(VM_READ | VM_WRITE | VM_EXEC | \
-					 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
-
-#define VM_STACK_DEFAULT_FLAGS64	(VM_READ | VM_WRITE | \
-					 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
-
-#define VM_STACK_DEFAULT_FLAGS \
-	(is_32bit_task() ? \
-	 VM_STACK_DEFAULT_FLAGS32 : VM_STACK_DEFAULT_FLAGS64)
-
-#include <asm-generic/getorder.h>
-
-#endif /* _ASM_POWERPC_PAGE_64_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/param.h b/ANDROID_3.4.5/arch/powerpc/include/asm/param.h
deleted file mode 100644
index 965d4542..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/param.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/param.h>
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/parport.h b/ANDROID_3.4.5/arch/powerpc/include/asm/parport.h
deleted file mode 100644
index 1ca1102b..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/parport.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * parport.h: platform-specific PC-style parport initialisation
- *
- * Copyright (C) 1999, 2000  Tim Waugh <tim@cyberelk.demon.co.uk>
- *
- * This file should only be included by drivers/parport/parport_pc.c.
- */
-
-#ifndef _ASM_POWERPC_PARPORT_H
-#define _ASM_POWERPC_PARPORT_H
-#ifdef __KERNEL__
-
-#include <asm/prom.h>
-
-static int __devinit parport_pc_find_nonpci_ports (int autoirq, int autodma)
-{
-	struct device_node *np;
-	const u32 *prop;
-	u32 io1, io2;
-	int propsize;
-	int count = 0;
-	int virq;
-
-	for (np = NULL; (np = of_find_compatible_node(np,
-						      "parallel",
-						      "pnpPNP,400")) != NULL;) {
-		prop = of_get_property(np, "reg", &propsize);
-		if (!prop || propsize > 6*sizeof(u32))
-			continue;
-		io1 = prop[1]; io2 = prop[2];
-
-		virq = irq_of_parse_and_map(np, 0);
-		if (virq == NO_IRQ)
-			continue;
-
-		if (parport_pc_probe_port(io1, io2, virq, autodma, NULL, 0)
-				!= NULL)
-			count++;
-	}
-	return count;
-}
-
-#endif /* __KERNEL__ */
-#endif /* !(_ASM_POWERPC_PARPORT_H) */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/pasemi_dma.h b/ANDROID_3.4.5/arch/powerpc/include/asm/pasemi_dma.h
deleted file mode 100644
index eafa5a5f..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/pasemi_dma.h
+++ /dev/null
@@ -1,538 +0,0 @@
-/*
- * Copyright (C) 2006-2008 PA Semi, Inc
- *
- * Hardware register layout and descriptor formats for the on-board
- * DMA engine on PA Semi PWRficient. Used by ethernet, function and security
- * drivers.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-
-#ifndef ASM_PASEMI_DMA_H
-#define ASM_PASEMI_DMA_H
-
-/* status register layout in IOB region, at 0xfb800000 */
-struct pasdma_status {
-	u64 rx_sta[64];		/* RX channel status */
-	u64 tx_sta[20];		/* TX channel status */
-};
-
-
-/* All these registers live in the PCI configuration space for the DMA PCI
- * device. Use the normal PCI config access functions for them.
- */
-enum {
-	PAS_DMA_CAP_TXCH  = 0x44,	/* Transmit Channel Info      */
-	PAS_DMA_CAP_RXCH  = 0x48,	/* Transmit Channel Info      */
-	PAS_DMA_CAP_IFI	  = 0x4c,	/* Interface Info	      */
-	PAS_DMA_COM_TXCMD = 0x100,	/* Transmit Command Register  */
-	PAS_DMA_COM_TXSTA = 0x104,	/* Transmit Status Register   */
-	PAS_DMA_COM_RXCMD = 0x108,	/* Receive Command Register   */
-	PAS_DMA_COM_RXSTA = 0x10c,	/* Receive Status Register    */
-	PAS_DMA_COM_CFG   = 0x114,	/* Common config reg	      */
-	PAS_DMA_TXF_SFLG0 = 0x140,	/* Set flags                  */
-	PAS_DMA_TXF_SFLG1 = 0x144,	/* Set flags                  */
-	PAS_DMA_TXF_CFLG0 = 0x148,	/* Set flags                  */
-	PAS_DMA_TXF_CFLG1 = 0x14c,	/* Set flags                  */
-};
-
-
-#define PAS_DMA_CAP_TXCH_TCHN_M	0x00ff0000 /* # of TX channels */
-#define PAS_DMA_CAP_TXCH_TCHN_S	16
-
-#define PAS_DMA_CAP_RXCH_RCHN_M	0x00ff0000 /* # of RX channels */
-#define PAS_DMA_CAP_RXCH_RCHN_S	16
-
-#define PAS_DMA_CAP_IFI_IOFF_M	0xff000000 /* Cfg reg for intf pointers */
-#define PAS_DMA_CAP_IFI_IOFF_S	24
-#define PAS_DMA_CAP_IFI_NIN_M	0x00ff0000 /* # of interfaces */
-#define PAS_DMA_CAP_IFI_NIN_S	16
-
-#define PAS_DMA_COM_TXCMD_EN	0x00000001 /* enable */
-#define PAS_DMA_COM_TXSTA_ACT	0x00000001 /* active */
-#define PAS_DMA_COM_RXCMD_EN	0x00000001 /* enable */
-#define PAS_DMA_COM_RXSTA_ACT	0x00000001 /* active */
-
-
-/* Per-interface and per-channel registers */
-#define _PAS_DMA_RXINT_STRIDE		0x20
-#define PAS_DMA_RXINT_RCMDSTA(i)	(0x200+(i)*_PAS_DMA_RXINT_STRIDE)
-#define    PAS_DMA_RXINT_RCMDSTA_EN	0x00000001
-#define    PAS_DMA_RXINT_RCMDSTA_ST	0x00000002
-#define    PAS_DMA_RXINT_RCMDSTA_MBT	0x00000008
-#define    PAS_DMA_RXINT_RCMDSTA_MDR	0x00000010
-#define    PAS_DMA_RXINT_RCMDSTA_MOO	0x00000020
-#define    PAS_DMA_RXINT_RCMDSTA_MBP	0x00000040
-#define    PAS_DMA_RXINT_RCMDSTA_BT	0x00000800
-#define    PAS_DMA_RXINT_RCMDSTA_DR	0x00001000
-#define    PAS_DMA_RXINT_RCMDSTA_OO	0x00002000
-#define    PAS_DMA_RXINT_RCMDSTA_BP	0x00004000
-#define    PAS_DMA_RXINT_RCMDSTA_TB	0x00008000
-#define    PAS_DMA_RXINT_RCMDSTA_ACT	0x00010000
-#define    PAS_DMA_RXINT_RCMDSTA_DROPS_M	0xfffe0000
-#define    PAS_DMA_RXINT_RCMDSTA_DROPS_S	17
-#define PAS_DMA_RXINT_CFG(i)		(0x204+(i)*_PAS_DMA_RXINT_STRIDE)
-#define    PAS_DMA_RXINT_CFG_RBP	0x80000000
-#define    PAS_DMA_RXINT_CFG_ITRR	0x40000000
-#define    PAS_DMA_RXINT_CFG_DHL_M	0x07000000
-#define    PAS_DMA_RXINT_CFG_DHL_S	24
-#define    PAS_DMA_RXINT_CFG_DHL(x)	(((x) << PAS_DMA_RXINT_CFG_DHL_S) & \
-					 PAS_DMA_RXINT_CFG_DHL_M)
-#define    PAS_DMA_RXINT_CFG_ITR	0x00400000
-#define    PAS_DMA_RXINT_CFG_LW		0x00200000
-#define    PAS_DMA_RXINT_CFG_L2		0x00100000
-#define    PAS_DMA_RXINT_CFG_HEN	0x00080000
-#define    PAS_DMA_RXINT_CFG_WIF	0x00000002
-#define    PAS_DMA_RXINT_CFG_WIL	0x00000001
-
-#define PAS_DMA_RXINT_INCR(i)		(0x210+(i)*_PAS_DMA_RXINT_STRIDE)
-#define    PAS_DMA_RXINT_INCR_INCR_M	0x0000ffff
-#define    PAS_DMA_RXINT_INCR_INCR_S	0
-#define    PAS_DMA_RXINT_INCR_INCR(x)	((x) & 0x0000ffff)
-#define PAS_DMA_RXINT_BASEL(i)		(0x218+(i)*_PAS_DMA_RXINT_STRIDE)
-#define    PAS_DMA_RXINT_BASEL_BRBL(x)	((x) & ~0x3f)
-#define PAS_DMA_RXINT_BASEU(i)		(0x21c+(i)*_PAS_DMA_RXINT_STRIDE)
-#define    PAS_DMA_RXINT_BASEU_BRBH(x)	((x) & 0xfff)
-#define    PAS_DMA_RXINT_BASEU_SIZ_M	0x3fff0000	/* # of cache lines worth of buffer ring */
-#define    PAS_DMA_RXINT_BASEU_SIZ_S	16		/* 0 = 16K */
-#define    PAS_DMA_RXINT_BASEU_SIZ(x)	(((x) << PAS_DMA_RXINT_BASEU_SIZ_S) & \
-					 PAS_DMA_RXINT_BASEU_SIZ_M)
-
-
-#define _PAS_DMA_TXCHAN_STRIDE	0x20    /* Size per channel		*/
-#define _PAS_DMA_TXCHAN_TCMDSTA	0x300	/* Command / Status		*/
-#define _PAS_DMA_TXCHAN_CFG	0x304	/* Configuration		*/
-#define _PAS_DMA_TXCHAN_DSCRBU	0x308	/* Descriptor BU Allocation	*/
-#define _PAS_DMA_TXCHAN_INCR	0x310	/* Descriptor increment		*/
-#define _PAS_DMA_TXCHAN_CNT	0x314	/* Descriptor count/offset	*/
-#define _PAS_DMA_TXCHAN_BASEL	0x318	/* Descriptor ring base (low)	*/
-#define _PAS_DMA_TXCHAN_BASEU	0x31c	/*			(high)	*/
-#define PAS_DMA_TXCHAN_TCMDSTA(c) (0x300+(c)*_PAS_DMA_TXCHAN_STRIDE)
-#define    PAS_DMA_TXCHAN_TCMDSTA_EN	0x00000001	/* Enabled */
-#define    PAS_DMA_TXCHAN_TCMDSTA_ST	0x00000002	/* Stop interface */
-#define    PAS_DMA_TXCHAN_TCMDSTA_ACT	0x00010000	/* Active */
-#define    PAS_DMA_TXCHAN_TCMDSTA_SZ	0x00000800
-#define    PAS_DMA_TXCHAN_TCMDSTA_DB	0x00000400
-#define    PAS_DMA_TXCHAN_TCMDSTA_DE	0x00000200
-#define    PAS_DMA_TXCHAN_TCMDSTA_DA	0x00000100
-#define PAS_DMA_TXCHAN_CFG(c)     (0x304+(c)*_PAS_DMA_TXCHAN_STRIDE)
-#define    PAS_DMA_TXCHAN_CFG_TY_IFACE	0x00000000	/* Type = interface */
-#define    PAS_DMA_TXCHAN_CFG_TY_COPY	0x00000001	/* Type = copy only */
-#define    PAS_DMA_TXCHAN_CFG_TY_FUNC	0x00000002	/* Type = function */
-#define    PAS_DMA_TXCHAN_CFG_TY_XOR	0x00000003	/* Type = xor only */
-#define    PAS_DMA_TXCHAN_CFG_TATTR_M	0x0000003c
-#define    PAS_DMA_TXCHAN_CFG_TATTR_S	2
-#define    PAS_DMA_TXCHAN_CFG_TATTR(x)	(((x) << PAS_DMA_TXCHAN_CFG_TATTR_S) & \
-					 PAS_DMA_TXCHAN_CFG_TATTR_M)
-#define    PAS_DMA_TXCHAN_CFG_LPDQ	0x00000800
-#define    PAS_DMA_TXCHAN_CFG_LPSQ	0x00000400
-#define    PAS_DMA_TXCHAN_CFG_WT_M	0x000003c0
-#define    PAS_DMA_TXCHAN_CFG_WT_S	6
-#define    PAS_DMA_TXCHAN_CFG_WT(x)	(((x) << PAS_DMA_TXCHAN_CFG_WT_S) & \
-					 PAS_DMA_TXCHAN_CFG_WT_M)
-#define    PAS_DMA_TXCHAN_CFG_TRD	0x00010000	/* translate data */
-#define    PAS_DMA_TXCHAN_CFG_TRR	0x00008000	/* translate rings */
-#define    PAS_DMA_TXCHAN_CFG_UP	0x00004000	/* update tx descr when sent */
-#define    PAS_DMA_TXCHAN_CFG_CL	0x00002000	/* Clean last line */
-#define    PAS_DMA_TXCHAN_CFG_CF	0x00001000	/* Clean first line */
-#define PAS_DMA_TXCHAN_INCR(c)    (0x310+(c)*_PAS_DMA_TXCHAN_STRIDE)
-#define PAS_DMA_TXCHAN_BASEL(c)   (0x318+(c)*_PAS_DMA_TXCHAN_STRIDE)
-#define    PAS_DMA_TXCHAN_BASEL_BRBL_M	0xffffffc0
-#define    PAS_DMA_TXCHAN_BASEL_BRBL_S	0
-#define    PAS_DMA_TXCHAN_BASEL_BRBL(x)	(((x) << PAS_DMA_TXCHAN_BASEL_BRBL_S) & \
-					 PAS_DMA_TXCHAN_BASEL_BRBL_M)
-#define PAS_DMA_TXCHAN_BASEU(c)   (0x31c+(c)*_PAS_DMA_TXCHAN_STRIDE)
-#define    PAS_DMA_TXCHAN_BASEU_BRBH_M	0x00000fff
-#define    PAS_DMA_TXCHAN_BASEU_BRBH_S	0
-#define    PAS_DMA_TXCHAN_BASEU_BRBH(x)	(((x) << PAS_DMA_TXCHAN_BASEU_BRBH_S) & \
-					 PAS_DMA_TXCHAN_BASEU_BRBH_M)
-/* # of cache lines worth of buffer ring */
-#define    PAS_DMA_TXCHAN_BASEU_SIZ_M	0x3fff0000
-#define    PAS_DMA_TXCHAN_BASEU_SIZ_S	16		/* 0 = 16K */
-#define    PAS_DMA_TXCHAN_BASEU_SIZ(x)	(((x) << PAS_DMA_TXCHAN_BASEU_SIZ_S) & \
-					 PAS_DMA_TXCHAN_BASEU_SIZ_M)
-
-#define _PAS_DMA_RXCHAN_STRIDE	0x20    /* Size per channel		*/
-#define _PAS_DMA_RXCHAN_CCMDSTA	0x800	/* Command / Status		*/
-#define _PAS_DMA_RXCHAN_CFG	0x804	/* Configuration		*/
-#define _PAS_DMA_RXCHAN_INCR	0x810	/* Descriptor increment		*/
-#define _PAS_DMA_RXCHAN_CNT	0x814	/* Descriptor count/offset	*/
-#define _PAS_DMA_RXCHAN_BASEL	0x818	/* Descriptor ring base (low)	*/
-#define _PAS_DMA_RXCHAN_BASEU	0x81c	/*			(high)	*/
-#define PAS_DMA_RXCHAN_CCMDSTA(c) (0x800+(c)*_PAS_DMA_RXCHAN_STRIDE)
-#define    PAS_DMA_RXCHAN_CCMDSTA_EN	0x00000001	/* Enabled */
-#define    PAS_DMA_RXCHAN_CCMDSTA_ST	0x00000002	/* Stop interface */
-#define    PAS_DMA_RXCHAN_CCMDSTA_ACT	0x00010000	/* Active */
-#define    PAS_DMA_RXCHAN_CCMDSTA_DU	0x00020000
-#define    PAS_DMA_RXCHAN_CCMDSTA_OD	0x00002000
-#define    PAS_DMA_RXCHAN_CCMDSTA_FD	0x00001000
-#define    PAS_DMA_RXCHAN_CCMDSTA_DT	0x00000800
-#define PAS_DMA_RXCHAN_CFG(c)     (0x804+(c)*_PAS_DMA_RXCHAN_STRIDE)
-#define    PAS_DMA_RXCHAN_CFG_CTR	0x00000400
-#define    PAS_DMA_RXCHAN_CFG_HBU_M	0x00000380
-#define    PAS_DMA_RXCHAN_CFG_HBU_S	7
-#define    PAS_DMA_RXCHAN_CFG_HBU(x)	(((x) << PAS_DMA_RXCHAN_CFG_HBU_S) & \
-					 PAS_DMA_RXCHAN_CFG_HBU_M)
-#define PAS_DMA_RXCHAN_INCR(c)    (0x810+(c)*_PAS_DMA_RXCHAN_STRIDE)
-#define PAS_DMA_RXCHAN_BASEL(c)   (0x818+(c)*_PAS_DMA_RXCHAN_STRIDE)
-#define    PAS_DMA_RXCHAN_BASEL_BRBL_M	0xffffffc0
-#define    PAS_DMA_RXCHAN_BASEL_BRBL_S	0
-#define    PAS_DMA_RXCHAN_BASEL_BRBL(x)	(((x) << PAS_DMA_RXCHAN_BASEL_BRBL_S) & \
-					 PAS_DMA_RXCHAN_BASEL_BRBL_M)
-#define PAS_DMA_RXCHAN_BASEU(c)   (0x81c+(c)*_PAS_DMA_RXCHAN_STRIDE)
-#define    PAS_DMA_RXCHAN_BASEU_BRBH_M	0x00000fff
-#define    PAS_DMA_RXCHAN_BASEU_BRBH_S	0
-#define    PAS_DMA_RXCHAN_BASEU_BRBH(x)	(((x) << PAS_DMA_RXCHAN_BASEU_BRBH_S) & \
-					 PAS_DMA_RXCHAN_BASEU_BRBH_M)
-/* # of cache lines worth of buffer ring */
-#define    PAS_DMA_RXCHAN_BASEU_SIZ_M	0x3fff0000
-#define    PAS_DMA_RXCHAN_BASEU_SIZ_S	16		/* 0 = 16K */
-#define    PAS_DMA_RXCHAN_BASEU_SIZ(x)	(((x) << PAS_DMA_RXCHAN_BASEU_SIZ_S) & \
-					 PAS_DMA_RXCHAN_BASEU_SIZ_M)
-
-#define    PAS_STATUS_PCNT_M		0x000000000000ffffull
-#define    PAS_STATUS_PCNT_S		0
-#define    PAS_STATUS_DCNT_M		0x00000000ffff0000ull
-#define    PAS_STATUS_DCNT_S		16
-#define    PAS_STATUS_BPCNT_M		0x0000ffff00000000ull
-#define    PAS_STATUS_BPCNT_S		32
-#define    PAS_STATUS_CAUSE_M		0xf000000000000000ull
-#define    PAS_STATUS_TIMER		0x1000000000000000ull
-#define    PAS_STATUS_ERROR		0x2000000000000000ull
-#define    PAS_STATUS_SOFT		0x4000000000000000ull
-#define    PAS_STATUS_INT		0x8000000000000000ull
-
-#define PAS_IOB_COM_PKTHDRCNT		0x120
-#define    PAS_IOB_COM_PKTHDRCNT_PKTHDR1_M	0x0fff0000
-#define    PAS_IOB_COM_PKTHDRCNT_PKTHDR1_S	16
-#define    PAS_IOB_COM_PKTHDRCNT_PKTHDR0_M	0x00000fff
-#define    PAS_IOB_COM_PKTHDRCNT_PKTHDR0_S	0
-
-#define PAS_IOB_DMA_RXCH_CFG(i)		(0x1100 + (i)*4)
-#define    PAS_IOB_DMA_RXCH_CFG_CNTTH_M		0x00000fff
-#define    PAS_IOB_DMA_RXCH_CFG_CNTTH_S		0
-#define    PAS_IOB_DMA_RXCH_CFG_CNTTH(x)	(((x) << PAS_IOB_DMA_RXCH_CFG_CNTTH_S) & \
-						 PAS_IOB_DMA_RXCH_CFG_CNTTH_M)
-#define PAS_IOB_DMA_TXCH_CFG(i)		(0x1200 + (i)*4)
-#define    PAS_IOB_DMA_TXCH_CFG_CNTTH_M		0x00000fff
-#define    PAS_IOB_DMA_TXCH_CFG_CNTTH_S		0
-#define    PAS_IOB_DMA_TXCH_CFG_CNTTH(x)	(((x) << PAS_IOB_DMA_TXCH_CFG_CNTTH_S) & \
-						 PAS_IOB_DMA_TXCH_CFG_CNTTH_M)
-#define PAS_IOB_DMA_RXCH_STAT(i)	(0x1300 + (i)*4)
-#define    PAS_IOB_DMA_RXCH_STAT_INTGEN	0x00001000
-#define    PAS_IOB_DMA_RXCH_STAT_CNTDEL_M	0x00000fff
-#define    PAS_IOB_DMA_RXCH_STAT_CNTDEL_S	0
-#define    PAS_IOB_DMA_RXCH_STAT_CNTDEL(x)	(((x) << PAS_IOB_DMA_RXCH_STAT_CNTDEL_S) &\
-						 PAS_IOB_DMA_RXCH_STAT_CNTDEL_M)
-#define PAS_IOB_DMA_TXCH_STAT(i)	(0x1400 + (i)*4)
-#define    PAS_IOB_DMA_TXCH_STAT_INTGEN	0x00001000
-#define    PAS_IOB_DMA_TXCH_STAT_CNTDEL_M	0x00000fff
-#define    PAS_IOB_DMA_TXCH_STAT_CNTDEL_S	0
-#define    PAS_IOB_DMA_TXCH_STAT_CNTDEL(x)	(((x) << PAS_IOB_DMA_TXCH_STAT_CNTDEL_S) &\
-						 PAS_IOB_DMA_TXCH_STAT_CNTDEL_M)
-#define PAS_IOB_DMA_RXCH_RESET(i)	(0x1500 + (i)*4)
-#define    PAS_IOB_DMA_RXCH_RESET_PCNT_M	0xffff0000
-#define    PAS_IOB_DMA_RXCH_RESET_PCNT_S	16
-#define    PAS_IOB_DMA_RXCH_RESET_PCNT(x)	(((x) << PAS_IOB_DMA_RXCH_RESET_PCNT_S) & \
-						 PAS_IOB_DMA_RXCH_RESET_PCNT_M)
-#define    PAS_IOB_DMA_RXCH_RESET_PCNTRST	0x00000020
-#define    PAS_IOB_DMA_RXCH_RESET_DCNTRST	0x00000010
-#define    PAS_IOB_DMA_RXCH_RESET_TINTC		0x00000008
-#define    PAS_IOB_DMA_RXCH_RESET_DINTC		0x00000004
-#define    PAS_IOB_DMA_RXCH_RESET_SINTC		0x00000002
-#define    PAS_IOB_DMA_RXCH_RESET_PINTC		0x00000001
-#define PAS_IOB_DMA_TXCH_RESET(i)	(0x1600 + (i)*4)
-#define    PAS_IOB_DMA_TXCH_RESET_PCNT_M	0xffff0000
-#define    PAS_IOB_DMA_TXCH_RESET_PCNT_S	16
-#define    PAS_IOB_DMA_TXCH_RESET_PCNT(x)	(((x) << PAS_IOB_DMA_TXCH_RESET_PCNT_S) & \
-						 PAS_IOB_DMA_TXCH_RESET_PCNT_M)
-#define    PAS_IOB_DMA_TXCH_RESET_PCNTRST	0x00000020
-#define    PAS_IOB_DMA_TXCH_RESET_DCNTRST	0x00000010
-#define    PAS_IOB_DMA_TXCH_RESET_TINTC		0x00000008
-#define    PAS_IOB_DMA_TXCH_RESET_DINTC		0x00000004
-#define    PAS_IOB_DMA_TXCH_RESET_SINTC		0x00000002
-#define    PAS_IOB_DMA_TXCH_RESET_PINTC		0x00000001
-
-#define PAS_IOB_DMA_COM_TIMEOUTCFG		0x1700
-#define    PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M	0x00ffffff
-#define    PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S	0
-#define    PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(x)	(((x) << PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S) & \
-						 PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M)
-
-/* Transmit descriptor fields */
-#define	XCT_MACTX_T		0x8000000000000000ull
-#define	XCT_MACTX_ST		0x4000000000000000ull
-#define XCT_MACTX_NORES		0x0000000000000000ull
-#define XCT_MACTX_8BRES		0x1000000000000000ull
-#define XCT_MACTX_24BRES	0x2000000000000000ull
-#define XCT_MACTX_40BRES	0x3000000000000000ull
-#define XCT_MACTX_I		0x0800000000000000ull
-#define XCT_MACTX_O		0x0400000000000000ull
-#define XCT_MACTX_E		0x0200000000000000ull
-#define XCT_MACTX_VLAN_M	0x0180000000000000ull
-#define XCT_MACTX_VLAN_NOP	0x0000000000000000ull
-#define XCT_MACTX_VLAN_REMOVE	0x0080000000000000ull
-#define XCT_MACTX_VLAN_INSERT   0x0100000000000000ull
-#define XCT_MACTX_VLAN_REPLACE  0x0180000000000000ull
-#define XCT_MACTX_CRC_M		0x0060000000000000ull
-#define XCT_MACTX_CRC_NOP	0x0000000000000000ull
-#define XCT_MACTX_CRC_INSERT	0x0020000000000000ull
-#define XCT_MACTX_CRC_PAD	0x0040000000000000ull
-#define XCT_MACTX_CRC_REPLACE	0x0060000000000000ull
-#define XCT_MACTX_SS		0x0010000000000000ull
-#define XCT_MACTX_LLEN_M	0x00007fff00000000ull
-#define XCT_MACTX_LLEN_S	32ull
-#define XCT_MACTX_LLEN(x)	((((long)(x)) << XCT_MACTX_LLEN_S) & \
-				 XCT_MACTX_LLEN_M)
-#define XCT_MACTX_IPH_M		0x00000000f8000000ull
-#define XCT_MACTX_IPH_S		27ull
-#define XCT_MACTX_IPH(x)	((((long)(x)) << XCT_MACTX_IPH_S) & \
-				 XCT_MACTX_IPH_M)
-#define XCT_MACTX_IPO_M		0x0000000007c00000ull
-#define XCT_MACTX_IPO_S		22ull
-#define XCT_MACTX_IPO(x)	((((long)(x)) << XCT_MACTX_IPO_S) & \
-				 XCT_MACTX_IPO_M)
-#define XCT_MACTX_CSUM_M	0x0000000000000060ull
-#define XCT_MACTX_CSUM_NOP	0x0000000000000000ull
-#define XCT_MACTX_CSUM_TCP	0x0000000000000040ull
-#define XCT_MACTX_CSUM_UDP	0x0000000000000060ull
-#define XCT_MACTX_V6		0x0000000000000010ull
-#define XCT_MACTX_C		0x0000000000000004ull
-#define XCT_MACTX_AL2		0x0000000000000002ull
-
-/* Receive descriptor fields */
-#define	XCT_MACRX_T		0x8000000000000000ull
-#define	XCT_MACRX_ST		0x4000000000000000ull
-#define XCT_MACRX_RR_M		0x3000000000000000ull
-#define XCT_MACRX_RR_NORES	0x0000000000000000ull
-#define XCT_MACRX_RR_8BRES	0x1000000000000000ull
-#define XCT_MACRX_O		0x0400000000000000ull
-#define XCT_MACRX_E		0x0200000000000000ull
-#define XCT_MACRX_FF		0x0100000000000000ull
-#define XCT_MACRX_PF		0x0080000000000000ull
-#define XCT_MACRX_OB		0x0040000000000000ull
-#define XCT_MACRX_OD		0x0020000000000000ull
-#define XCT_MACRX_FS		0x0010000000000000ull
-#define XCT_MACRX_NB_M		0x000fc00000000000ull
-#define XCT_MACRX_NB_S		46ULL
-#define XCT_MACRX_NB(x)		((((long)(x)) << XCT_MACRX_NB_S) & \
-				 XCT_MACRX_NB_M)
-#define XCT_MACRX_LLEN_M	0x00003fff00000000ull
-#define XCT_MACRX_LLEN_S	32ULL
-#define XCT_MACRX_LLEN(x)	((((long)(x)) << XCT_MACRX_LLEN_S) & \
-				 XCT_MACRX_LLEN_M)
-#define XCT_MACRX_CRC		0x0000000080000000ull
-#define XCT_MACRX_LEN_M		0x0000000060000000ull
-#define XCT_MACRX_LEN_TOOSHORT	0x0000000020000000ull
-#define XCT_MACRX_LEN_BELOWMIN	0x0000000040000000ull
-#define XCT_MACRX_LEN_TRUNC	0x0000000060000000ull
-#define XCT_MACRX_CAST_M	0x0000000018000000ull
-#define XCT_MACRX_CAST_UNI	0x0000000000000000ull
-#define XCT_MACRX_CAST_MULTI	0x0000000008000000ull
-#define XCT_MACRX_CAST_BROAD	0x0000000010000000ull
-#define XCT_MACRX_CAST_PAUSE	0x0000000018000000ull
-#define XCT_MACRX_VLC_M		0x0000000006000000ull
-#define XCT_MACRX_FM		0x0000000001000000ull
-#define XCT_MACRX_HTY_M		0x0000000000c00000ull
-#define XCT_MACRX_HTY_IPV4_OK	0x0000000000000000ull
-#define XCT_MACRX_HTY_IPV6 	0x0000000000400000ull
-#define XCT_MACRX_HTY_IPV4_BAD	0x0000000000800000ull
-#define XCT_MACRX_HTY_NONIP	0x0000000000c00000ull
-#define XCT_MACRX_IPP_M		0x00000000003f0000ull
-#define XCT_MACRX_IPP_S		16
-#define XCT_MACRX_CSUM_M	0x000000000000ffffull
-#define XCT_MACRX_CSUM_S	0
-
-#define XCT_PTR_T		0x8000000000000000ull
-#define XCT_PTR_LEN_M		0x7ffff00000000000ull
-#define XCT_PTR_LEN_S		44
-#define XCT_PTR_LEN(x)		((((long)(x)) << XCT_PTR_LEN_S) & \
-				 XCT_PTR_LEN_M)
-#define XCT_PTR_ADDR_M		0x00000fffffffffffull
-#define XCT_PTR_ADDR_S		0
-#define XCT_PTR_ADDR(x)		((((long)(x)) << XCT_PTR_ADDR_S) & \
-				 XCT_PTR_ADDR_M)
-
-/* Receive interface 8byte result fields */
-#define XCT_RXRES_8B_L4O_M	0xff00000000000000ull
-#define XCT_RXRES_8B_L4O_S	56
-#define XCT_RXRES_8B_RULE_M	0x00ffff0000000000ull
-#define XCT_RXRES_8B_RULE_S	40
-#define XCT_RXRES_8B_EVAL_M	0x000000ffff000000ull
-#define XCT_RXRES_8B_EVAL_S	24
-#define XCT_RXRES_8B_HTYPE_M	0x0000000000f00000ull
-#define XCT_RXRES_8B_HASH_M	0x00000000000fffffull
-#define XCT_RXRES_8B_HASH_S	0
-
-/* Receive interface buffer fields */
-#define XCT_RXB_LEN_M		0x0ffff00000000000ull
-#define XCT_RXB_LEN_S		44
-#define XCT_RXB_LEN(x)		((((long)(x)) << XCT_RXB_LEN_S) & \
-				 XCT_RXB_LEN_M)
-#define XCT_RXB_ADDR_M		0x00000fffffffffffull
-#define XCT_RXB_ADDR_S		0
-#define XCT_RXB_ADDR(x)		((((long)(x)) << XCT_RXB_ADDR_S) & \
-				 XCT_RXB_ADDR_M)
-
-/* Copy descriptor fields */
-#define XCT_COPY_T		0x8000000000000000ull
-#define XCT_COPY_ST		0x4000000000000000ull
-#define XCT_COPY_RR_M		0x3000000000000000ull
-#define XCT_COPY_RR_NORES	0x0000000000000000ull
-#define XCT_COPY_RR_8BRES	0x1000000000000000ull
-#define XCT_COPY_RR_24BRES	0x2000000000000000ull
-#define XCT_COPY_RR_40BRES	0x3000000000000000ull
-#define XCT_COPY_I		0x0800000000000000ull
-#define XCT_COPY_O		0x0400000000000000ull
-#define XCT_COPY_E		0x0200000000000000ull
-#define XCT_COPY_STY_ZERO	0x01c0000000000000ull
-#define XCT_COPY_DTY_PREF	0x0038000000000000ull
-#define XCT_COPY_LLEN_M		0x0007ffff00000000ull
-#define XCT_COPY_LLEN_S		32
-#define XCT_COPY_LLEN(x)	((((long)(x)) << XCT_COPY_LLEN_S) & \
-				 XCT_COPY_LLEN_M)
-#define XCT_COPY_SE		0x0000000000000001ull
-
-/* Function descriptor fields */
-#define XCT_FUN_T		0x8000000000000000ull
-#define XCT_FUN_ST		0x4000000000000000ull
-#define XCT_FUN_RR_M		0x3000000000000000ull
-#define XCT_FUN_RR_NORES	0x0000000000000000ull
-#define XCT_FUN_RR_8BRES	0x1000000000000000ull
-#define XCT_FUN_RR_24BRES	0x2000000000000000ull
-#define XCT_FUN_RR_40BRES	0x3000000000000000ull
-#define XCT_FUN_I		0x0800000000000000ull
-#define XCT_FUN_O		0x0400000000000000ull
-#define XCT_FUN_E		0x0200000000000000ull
-#define XCT_FUN_FUN_M		0x01c0000000000000ull
-#define XCT_FUN_FUN_S		54
-#define XCT_FUN_FUN(x)		((((long)(x)) << XCT_FUN_FUN_S) & XCT_FUN_FUN_M)
-#define XCT_FUN_CRM_M		0x0038000000000000ull
-#define XCT_FUN_CRM_NOP		0x0000000000000000ull
-#define XCT_FUN_CRM_SIG		0x0008000000000000ull
-#define XCT_FUN_LLEN_M		0x0007ffff00000000ull
-#define XCT_FUN_LLEN_S		32
-#define XCT_FUN_LLEN(x)		((((long)(x)) << XCT_FUN_LLEN_S) & XCT_FUN_LLEN_M)
-#define XCT_FUN_SHL_M		0x00000000f8000000ull
-#define XCT_FUN_SHL_S		27
-#define XCT_FUN_SHL(x)		((((long)(x)) << XCT_FUN_SHL_S) & XCT_FUN_SHL_M)
-#define XCT_FUN_CHL_M		0x0000000007c00000ull
-#define XCT_FUN_HSZ_M		0x00000000003c0000ull
-#define XCT_FUN_ALG_M		0x0000000000038000ull
-#define XCT_FUN_HP		0x0000000000004000ull
-#define XCT_FUN_BCM_M		0x0000000000003800ull
-#define XCT_FUN_BCP_M		0x0000000000000600ull
-#define XCT_FUN_SIG_M		0x00000000000001f0ull
-#define XCT_FUN_SIG_TCP4	0x0000000000000140ull
-#define XCT_FUN_SIG_TCP6	0x0000000000000150ull
-#define XCT_FUN_SIG_UDP4	0x0000000000000160ull
-#define XCT_FUN_SIG_UDP6	0x0000000000000170ull
-#define XCT_FUN_A		0x0000000000000008ull
-#define XCT_FUN_C		0x0000000000000004ull
-#define XCT_FUN_AL2		0x0000000000000002ull
-#define XCT_FUN_SE		0x0000000000000001ull
-
-/* Function descriptor 8byte result fields */
-#define XCT_FUNRES_8B_CS_M	0x0000ffff00000000ull
-#define XCT_FUNRES_8B_CS_S	32
-#define XCT_FUNRES_8B_CRC_M	0x00000000ffffffffull
-#define XCT_FUNRES_8B_CRC_S	0
-
-/* Control descriptor fields */
-#define CTRL_CMD_T		0x8000000000000000ull
-#define CTRL_CMD_META_EVT	0x2000000000000000ull
-#define CTRL_CMD_O		0x0400000000000000ull
-#define CTRL_CMD_ETYPE_M	0x0038000000000000ull
-#define CTRL_CMD_ETYPE_EXT	0x0000000000000000ull
-#define CTRL_CMD_ETYPE_WSET	0x0020000000000000ull
-#define CTRL_CMD_ETYPE_WCLR	0x0028000000000000ull
-#define CTRL_CMD_ETYPE_SET	0x0030000000000000ull
-#define CTRL_CMD_ETYPE_CLR	0x0038000000000000ull
-#define CTRL_CMD_REG_M		0x000000000000007full
-#define CTRL_CMD_REG_S		0
-#define CTRL_CMD_REG(x)		((((long)(x)) << CTRL_CMD_REG_S) & \
-				 CTRL_CMD_REG_M)
-
-
-
-/* Prototypes for the shared DMA functions in the platform code. */
-
-/* DMA TX Channel type. Right now only limitations used are event types 0/1,
- * for event-triggered DMA transactions.
- */
-
-enum pasemi_dmachan_type {
-	RXCHAN = 0,		/* Any RX chan */
-	TXCHAN = 1,		/* Any TX chan */
-	TXCHAN_EVT0 = 0x1001,	/* TX chan in event class 0 (chan 0-9) */
-	TXCHAN_EVT1 = 0x2001,	/* TX chan in event class 1 (chan 10-19) */
-};
-
-struct pasemi_dmachan {
-	int		 chno;		/* Channel number */
-	enum pasemi_dmachan_type chan_type;	/* TX / RX */
-	u64		*status;	/* Ptr to cacheable status */
-	int		 irq;		/* IRQ used by channel */
-	unsigned int	 ring_size;	/* size of allocated ring */
-	dma_addr_t	 ring_dma;	/* DMA address for ring */
-	u64		*ring_virt;	/* Virt address for ring */
-	void		*priv;		/* Ptr to start of client struct */
-};
-
-/* Read/write the different registers in the I/O Bridge, Ethernet
- * and DMA Controller
- */
-extern unsigned int pasemi_read_iob_reg(unsigned int reg);
-extern void pasemi_write_iob_reg(unsigned int reg, unsigned int val);
-
-extern unsigned int pasemi_read_mac_reg(int intf, unsigned int reg);
-extern void pasemi_write_mac_reg(int intf, unsigned int reg, unsigned int val);
-
-extern unsigned int pasemi_read_dma_reg(unsigned int reg);
-extern void pasemi_write_dma_reg(unsigned int reg, unsigned int val);
-
-/* Channel management routines */
-
-extern void *pasemi_dma_alloc_chan(enum pasemi_dmachan_type type,
-				   int total_size, int offset);
-extern void pasemi_dma_free_chan(struct pasemi_dmachan *chan);
-
-extern void pasemi_dma_start_chan(const struct pasemi_dmachan *chan,
-				  const u32 cmdsta);
-extern int pasemi_dma_stop_chan(const struct pasemi_dmachan *chan);
-
-/* Common routines to allocate rings and buffers */
-
-extern int pasemi_dma_alloc_ring(struct pasemi_dmachan *chan, int ring_size);
-extern void pasemi_dma_free_ring(struct pasemi_dmachan *chan);
-
-extern void *pasemi_dma_alloc_buf(struct pasemi_dmachan *chan, int size,
-				  dma_addr_t *handle);
-extern void pasemi_dma_free_buf(struct pasemi_dmachan *chan, int size,
-				dma_addr_t *handle);
-
-/* Routines to allocate flags (events) for channel synchronization */
-extern int  pasemi_dma_alloc_flag(void);
-extern void pasemi_dma_free_flag(int flag);
-extern void pasemi_dma_set_flag(int flag);
-extern void pasemi_dma_clear_flag(int flag);
-
-/* Routines to allocate function engines */
-extern int  pasemi_dma_alloc_fun(void);
-extern void pasemi_dma_free_fun(int fun);
-
-/* Initialize the library, must be called before any other functions */
-extern int pasemi_dma_init(void);
-
-#endif /* ASM_PASEMI_DMA_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/pci-bridge.h b/ANDROID_3.4.5/arch/powerpc/include/asm/pci-bridge.h
deleted file mode 100644
index ac39e6a3..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/pci-bridge.h
+++ /dev/null
@@ -1,240 +0,0 @@
-#ifndef _ASM_POWERPC_PCI_BRIDGE_H
-#define _ASM_POWERPC_PCI_BRIDGE_H
-#ifdef __KERNEL__
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#include <linux/pci.h>
-#include <linux/list.h>
-#include <linux/ioport.h>
-#include <asm-generic/pci-bridge.h>
-
-struct device_node;
-
-/*
- * Structure of a PCI controller (host bridge)
- */
-struct pci_controller {
-	struct pci_bus *bus;
-	char is_dynamic;
-#ifdef CONFIG_PPC64
-	int node;
-#endif
-	struct device_node *dn;
-	struct list_head list_node;
-	struct device *parent;
-
-	int first_busno;
-	int last_busno;
-	int self_busno;
-
-	void __iomem *io_base_virt;
-#ifdef CONFIG_PPC64
-	void *io_base_alloc;
-#endif
-	resource_size_t io_base_phys;
-	resource_size_t pci_io_size;
-
-	/* Some machines (PReP) have a non 1:1 mapping of
-	 * the PCI memory space in the CPU bus space
-	 */
-	resource_size_t pci_mem_offset;
-
-	/* Some machines have a special region to forward the ISA
-	 * "memory" cycles such as VGA memory regions. Left to 0
-	 * if unsupported
-	 */
-	resource_size_t	isa_mem_phys;
-	resource_size_t	isa_mem_size;
-
-	struct pci_ops *ops;
-	unsigned int __iomem *cfg_addr;
-	void __iomem *cfg_data;
-
-	/*
-	 * Used for variants of PCI indirect handling and possible quirks:
-	 *  SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
-	 *  EXT_REG - provides access to PCI-e extended registers
-	 *  SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
-	 *   on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
-	 *   to determine which bus number to match on when generating type0
-	 *   config cycles
-	 *  NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
-	 *   hanging if we don't have link and try to do config cycles to
-	 *   anything but the PHB.  Only allow talking to the PHB if this is
-	 *   set.
-	 *  BIG_ENDIAN - cfg_addr is a big endian register
-	 *  BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
-	 *   the PLB4.  Effectively disable MRM commands by setting this.
-	 */
-#define PPC_INDIRECT_TYPE_SET_CFG_TYPE		0x00000001
-#define PPC_INDIRECT_TYPE_EXT_REG		0x00000002
-#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS	0x00000004
-#define PPC_INDIRECT_TYPE_NO_PCIE_LINK		0x00000008
-#define PPC_INDIRECT_TYPE_BIG_ENDIAN		0x00000010
-#define PPC_INDIRECT_TYPE_BROKEN_MRM		0x00000020
-	u32 indirect_type;
-	/* Currently, we limit ourselves to 1 IO range and 3 mem
-	 * ranges since the common pci_bus structure can't handle more
-	 */
-	struct resource	io_resource;
-	struct resource mem_resources[3];
-	int global_number;		/* PCI domain number */
-
-	resource_size_t dma_window_base_cur;
-	resource_size_t dma_window_size;
-
-#ifdef CONFIG_PPC64
-	unsigned long buid;
-
-	void *private_data;
-#endif	/* CONFIG_PPC64 */
-};
-
-/* These are used for config access before all the PCI probing
-   has been done. */
-extern int early_read_config_byte(struct pci_controller *hose, int bus,
-			int dev_fn, int where, u8 *val);
-extern int early_read_config_word(struct pci_controller *hose, int bus,
-			int dev_fn, int where, u16 *val);
-extern int early_read_config_dword(struct pci_controller *hose, int bus,
-			int dev_fn, int where, u32 *val);
-extern int early_write_config_byte(struct pci_controller *hose, int bus,
-			int dev_fn, int where, u8 val);
-extern int early_write_config_word(struct pci_controller *hose, int bus,
-			int dev_fn, int where, u16 val);
-extern int early_write_config_dword(struct pci_controller *hose, int bus,
-			int dev_fn, int where, u32 val);
-
-extern int early_find_capability(struct pci_controller *hose, int bus,
-				 int dev_fn, int cap);
-
-extern void setup_indirect_pci(struct pci_controller* hose,
-			       resource_size_t cfg_addr,
-			       resource_size_t cfg_data, u32 flags);
-
-static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
-{
-	return bus->sysdata;
-}
-
-#ifndef CONFIG_PPC64
-
-extern int pci_device_from_OF_node(struct device_node *node,
-				   u8 *bus, u8 *devfn);
-extern void pci_create_OF_bus_map(void);
-
-static inline int isa_vaddr_is_ioport(void __iomem *address)
-{
-	/* No specific ISA handling on ppc32 at this stage, it
-	 * all goes through PCI
-	 */
-	return 0;
-}
-
-#else	/* CONFIG_PPC64 */
-
-/*
- * PCI stuff, for nodes representing PCI devices, pointed to
- * by device_node->data.
- */
-struct iommu_table;
-
-struct pci_dn {
-	int	busno;			/* pci bus number */
-	int	devfn;			/* pci device and function number */
-
-	struct  pci_controller *phb;	/* for pci devices */
-	struct	iommu_table *iommu_table;	/* for phb's or bridges */
-	struct	device_node *node;	/* back-pointer to the device_node */
-
-	int	pci_ext_config_space;	/* for pci devices */
-
-	struct	pci_dev *pcidev;	/* back-pointer to the pci device */
-#ifdef CONFIG_EEH
-	struct eeh_dev *edev;		/* eeh device */
-#endif
-#define IODA_INVALID_PE		(-1)
-#ifdef CONFIG_PPC_POWERNV
-	int	pe_number;
-#endif
-};
-
-/* Get the pointer to a device_node's pci_dn */
-#define PCI_DN(dn)	((struct pci_dn *) (dn)->data)
-
-extern void * update_dn_pci_info(struct device_node *dn, void *data);
-
-static inline int pci_device_from_OF_node(struct device_node *np,
-					  u8 *bus, u8 *devfn)
-{
-	if (!PCI_DN(np))
-		return -ENODEV;
-	*bus = PCI_DN(np)->busno;
-	*devfn = PCI_DN(np)->devfn;
-	return 0;
-}
-
-#if defined(CONFIG_EEH)
-static inline struct eeh_dev *of_node_to_eeh_dev(struct device_node *dn)
-{
-	return PCI_DN(dn)->edev;
-}
-#endif
-
-/** Find the bus corresponding to the indicated device node */
-extern struct pci_bus *pcibios_find_pci_bus(struct device_node *dn);
-
-/** Remove all of the PCI devices under this bus */
-extern void pcibios_remove_pci_devices(struct pci_bus *bus);
-
-/** Discover new pci devices under this bus, and add them */
-extern void pcibios_add_pci_devices(struct pci_bus *bus);
-
-
-extern void isa_bridge_find_early(struct pci_controller *hose);
-
-static inline int isa_vaddr_is_ioport(void __iomem *address)
-{
-	/* Check if address hits the reserved legacy IO range */
-	unsigned long ea = (unsigned long)address;
-	return ea >= ISA_IO_BASE && ea < ISA_IO_END;
-}
-
-extern int pcibios_unmap_io_space(struct pci_bus *bus);
-extern int pcibios_map_io_space(struct pci_bus *bus);
-
-#ifdef CONFIG_NUMA
-#define PHB_SET_NODE(PHB, NODE)		((PHB)->node = (NODE))
-#else
-#define PHB_SET_NODE(PHB, NODE)		((PHB)->node = -1)
-#endif
-
-#endif	/* CONFIG_PPC64 */
-
-/* Get the PCI host controller for an OF device */
-extern struct pci_controller *pci_find_hose_for_OF_device(
-			struct device_node* node);
-
-/* Fill up host controller resources from the OF node */
-extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
-			struct device_node *dev, int primary);
-
-/* Allocate & free a PCI host bridge structure */
-extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
-extern void pcibios_free_controller(struct pci_controller *phb);
-
-#ifdef CONFIG_PCI
-extern int pcibios_vaddr_is_ioport(void __iomem *address);
-#else
-static inline int pcibios_vaddr_is_ioport(void __iomem *address)
-{
-	return 0;
-}
-#endif	/* CONFIG_PCI */
-
-#endif	/* __KERNEL__ */
-#endif	/* _ASM_POWERPC_PCI_BRIDGE_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/pci.h b/ANDROID_3.4.5/arch/powerpc/include/asm/pci.h
deleted file mode 100644
index 6653f274..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/pci.h
+++ /dev/null
@@ -1,192 +0,0 @@
-#ifndef __ASM_POWERPC_PCI_H
-#define __ASM_POWERPC_PCI_H
-#ifdef __KERNEL__
-
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/types.h>
-#include <linux/slab.h>
-#include <linux/string.h>
-#include <linux/dma-mapping.h>
-
-#include <asm/machdep.h>
-#include <asm/scatterlist.h>
-#include <asm/io.h>
-#include <asm/prom.h>
-#include <asm/pci-bridge.h>
-
-#include <asm-generic/pci-dma-compat.h>
-
-/* Return values for ppc_md.pci_probe_mode function */
-#define PCI_PROBE_NONE		-1	/* Don't look at this bus at all */
-#define PCI_PROBE_NORMAL	0	/* Do normal PCI probing */
-#define PCI_PROBE_DEVTREE	1	/* Instantiate from device tree */
-
-#define PCIBIOS_MIN_IO		0x1000
-#define PCIBIOS_MIN_MEM		0x10000000
-
-struct pci_dev;
-
-/* Values for the `which' argument to sys_pciconfig_iobase syscall.  */
-#define IOBASE_BRIDGE_NUMBER	0
-#define IOBASE_MEMORY		1
-#define IOBASE_IO		2
-#define IOBASE_ISA_IO		3
-#define IOBASE_ISA_MEM		4
-
-/*
- * Set this to 1 if you want the kernel to re-assign all PCI
- * bus numbers (don't do that on ppc64 yet !)
- */
-#define pcibios_assign_all_busses() \
-	(pci_has_flag(PCI_REASSIGN_ALL_BUS))
-
-static inline void pcibios_penalize_isa_irq(int irq, int active)
-{
-	/* We don't do dynamic PCI IRQ allocation */
-}
-
-#define HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ
-static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
-{
-	if (ppc_md.pci_get_legacy_ide_irq)
-		return ppc_md.pci_get_legacy_ide_irq(dev, channel);
-	return channel ? 15 : 14;
-}
-
-#ifdef CONFIG_PCI
-extern void set_pci_dma_ops(struct dma_map_ops *dma_ops);
-extern struct dma_map_ops *get_pci_dma_ops(void);
-#else	/* CONFIG_PCI */
-#define set_pci_dma_ops(d)
-#define get_pci_dma_ops()	NULL
-#endif
-
-#ifdef CONFIG_PPC64
-
-/*
- * We want to avoid touching the cacheline size or MWI bit.
- * pSeries firmware sets the cacheline size (which is not the cpu cacheline
- * size in all cases) and hardware treats MWI the same as memory write.
- */
-#define PCI_DISABLE_MWI
-
-#ifdef CONFIG_PCI
-static inline void pci_dma_burst_advice(struct pci_dev *pdev,
-					enum pci_dma_burst_strategy *strat,
-					unsigned long *strategy_parameter)
-{
-	unsigned long cacheline_size;
-	u8 byte;
-
-	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
-	if (byte == 0)
-		cacheline_size = 1024;
-	else
-		cacheline_size = (int) byte * 4;
-
-	*strat = PCI_DMA_BURST_MULTIPLE;
-	*strategy_parameter = cacheline_size;
-}
-#endif
-
-#else /* 32-bit */
-
-#ifdef CONFIG_PCI
-static inline void pci_dma_burst_advice(struct pci_dev *pdev,
-					enum pci_dma_burst_strategy *strat,
-					unsigned long *strategy_parameter)
-{
-	*strat = PCI_DMA_BURST_INFINITY;
-	*strategy_parameter = ~0UL;
-}
-#endif
-#endif /* CONFIG_PPC64 */
-
-extern int pci_domain_nr(struct pci_bus *bus);
-
-/* Decide whether to display the domain number in /proc */
-extern int pci_proc_domain(struct pci_bus *bus);
-
-/* MSI arch hooks */
-#define arch_setup_msi_irqs arch_setup_msi_irqs
-#define arch_teardown_msi_irqs arch_teardown_msi_irqs
-#define arch_msi_check_device arch_msi_check_device
-
-struct vm_area_struct;
-/* Map a range of PCI memory or I/O space for a device into user space */
-int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma,
-			enum pci_mmap_state mmap_state, int write_combine);
-
-/* Tell drivers/pci/proc.c that we have pci_mmap_page_range() */
-#define HAVE_PCI_MMAP	1
-
-extern int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val,
-			   size_t count);
-extern int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val,
-			   size_t count);
-extern int pci_mmap_legacy_page_range(struct pci_bus *bus,
-				      struct vm_area_struct *vma,
-				      enum pci_mmap_state mmap_state);
-
-#define HAVE_PCI_LEGACY	1
-
-#ifdef CONFIG_PPC64
-
-/* The PCI address space does not equal the physical memory address
- * space (we have an IOMMU).  The IDE and SCSI device layers use
- * this boolean for bounce buffer decisions.
- */
-#define PCI_DMA_BUS_IS_PHYS	(0)
-
-#else /* 32-bit */
-
-/* The PCI address space does equal the physical memory
- * address space (no IOMMU).  The IDE and SCSI device layers use
- * this boolean for bounce buffer decisions.
- */
-#define PCI_DMA_BUS_IS_PHYS     (1)
-
-#endif /* CONFIG_PPC64 */
-
-extern void pcibios_claim_one_bus(struct pci_bus *b);
-
-extern void pcibios_finish_adding_to_bus(struct pci_bus *bus);
-
-extern void pcibios_resource_survey(void);
-
-extern struct pci_controller *init_phb_dynamic(struct device_node *dn);
-extern int remove_phb_dynamic(struct pci_controller *phb);
-
-extern struct pci_dev *of_create_pci_dev(struct device_node *node,
-					struct pci_bus *bus, int devfn);
-
-extern void of_scan_pci_bridge(struct pci_dev *dev);
-
-extern void of_scan_bus(struct device_node *node, struct pci_bus *bus);
-extern void of_rescan_bus(struct device_node *node, struct pci_bus *bus);
-
-struct file;
-extern pgprot_t	pci_phys_mem_access_prot(struct file *file,
-					 unsigned long pfn,
-					 unsigned long size,
-					 pgprot_t prot);
-
-#define HAVE_ARCH_PCI_RESOURCE_TO_USER
-extern void pci_resource_to_user(const struct pci_dev *dev, int bar,
-				 const struct resource *rsrc,
-				 resource_size_t *start, resource_size_t *end);
-
-extern resource_size_t pcibios_io_space_offset(struct pci_controller *hose);
-extern void pcibios_setup_bus_devices(struct pci_bus *bus);
-extern void pcibios_setup_bus_self(struct pci_bus *bus);
-extern void pcibios_setup_phb_io_space(struct pci_controller *hose);
-extern void pcibios_scan_phb(struct pci_controller *hose);
-
-#endif	/* __KERNEL__ */
-#endif /* __ASM_POWERPC_PCI_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/percpu.h b/ANDROID_3.4.5/arch/powerpc/include/asm/percpu.h
deleted file mode 100644
index 2cedefdd..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/percpu.h
+++ /dev/null
@@ -1,21 +0,0 @@
-#ifndef _ASM_POWERPC_PERCPU_H_
-#define _ASM_POWERPC_PERCPU_H_
-#ifdef __powerpc64__
-
-/*
- * Same as asm-generic/percpu.h, except that we store the per cpu offset
- * in the paca. Based on the x86-64 implementation.
- */
-
-#ifdef CONFIG_SMP
-
-#include <asm/paca.h>
-
-#define __my_cpu_offset local_paca->data_offset
-
-#endif /* CONFIG_SMP */
-#endif /* __powerpc64__ */
-
-#include <asm-generic/percpu.h>
-
-#endif /* _ASM_POWERPC_PERCPU_H_ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/perf_event.h b/ANDROID_3.4.5/arch/powerpc/include/asm/perf_event.h
deleted file mode 100644
index 5c16b891..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/perf_event.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Performance event support - hardware-specific disambiguation
- *
- * For now this is a compile-time decision, but eventually it should be
- * runtime.  This would allow multiplatform perf event support for e300 (fsl
- * embedded perf counters) plus server/classic, and would accommodate
- * devices other than the core which provide their own performance counters.
- *
- * Copyright 2010 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifdef CONFIG_PPC_PERF_CTRS
-#include <asm/perf_event_server.h>
-#endif
-
-#ifdef CONFIG_FSL_EMB_PERF_EVENT
-#include <asm/perf_event_fsl_emb.h>
-#endif
-
-#ifdef CONFIG_PERF_EVENTS
-#include <asm/ptrace.h>
-#include <asm/reg.h>
-
-#define perf_arch_fetch_caller_regs(regs, __ip)			\
-	do {							\
-		(regs)->nip = __ip;				\
-		(regs)->gpr[1] = *(unsigned long *)__get_SP();	\
-		asm volatile("mfmsr %0" : "=r" ((regs)->msr));	\
-	} while (0)
-#endif
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/perf_event_fsl_emb.h b/ANDROID_3.4.5/arch/powerpc/include/asm/perf_event_fsl_emb.h
deleted file mode 100644
index 718a9fa9..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/perf_event_fsl_emb.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * Performance event support - Freescale embedded specific definitions.
- *
- * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
- * Copyright 2010 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/types.h>
-#include <asm/hw_irq.h>
-
-#define MAX_HWEVENTS 4
-
-/* event flags */
-#define FSL_EMB_EVENT_VALID      1
-#define FSL_EMB_EVENT_RESTRICTED 2
-
-/* upper half of event flags is PMLCb */
-#define FSL_EMB_EVENT_THRESHMUL  0x0000070000000000ULL
-#define FSL_EMB_EVENT_THRESH     0x0000003f00000000ULL
-
-struct fsl_emb_pmu {
-	const char	*name;
-	int		n_counter; /* total number of counters */
-
-	/*
-	 * The number of contiguous counters starting at zero that
-	 * can hold restricted events, or zero if there are no
-	 * restricted events.
-	 *
-	 * This isn't a very flexible method of expressing constraints,
-	 * but it's very simple and is adequate for existing chips.
-	 */
-	int		n_restricted;
-
-	/* Returns event flags and PMLCb (FSL_EMB_EVENT_*) */
-	u64		(*xlate_event)(u64 event_id);
-
-	int		n_generic;
-	int		*generic_events;
-	int		(*cache_events)[PERF_COUNT_HW_CACHE_MAX]
-			       [PERF_COUNT_HW_CACHE_OP_MAX]
-			       [PERF_COUNT_HW_CACHE_RESULT_MAX];
-};
-
-int register_fsl_emb_pmu(struct fsl_emb_pmu *);
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/perf_event_server.h b/ANDROID_3.4.5/arch/powerpc/include/asm/perf_event_server.h
deleted file mode 100644
index 078019b5..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/perf_event_server.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * Performance event support - PowerPC classic/server specific definitions.
- *
- * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/types.h>
-#include <asm/hw_irq.h>
-
-#define MAX_HWEVENTS		8
-#define MAX_EVENT_ALTERNATIVES	8
-#define MAX_LIMITED_HWCOUNTERS	2
-
-/*
- * This struct provides the constants and functions needed to
- * describe the PMU on a particular POWER-family CPU.
- */
-struct power_pmu {
-	const char	*name;
-	int		n_counter;
-	int		max_alternatives;
-	unsigned long	add_fields;
-	unsigned long	test_adder;
-	int		(*compute_mmcr)(u64 events[], int n_ev,
-				unsigned int hwc[], unsigned long mmcr[]);
-	int		(*get_constraint)(u64 event_id, unsigned long *mskp,
-				unsigned long *valp);
-	int		(*get_alternatives)(u64 event_id, unsigned int flags,
-				u64 alt[]);
-	void		(*disable_pmc)(unsigned int pmc, unsigned long mmcr[]);
-	int		(*limited_pmc_event)(u64 event_id);
-	u32		flags;
-	int		n_generic;
-	int		*generic_events;
-	int		(*cache_events)[PERF_COUNT_HW_CACHE_MAX]
-			       [PERF_COUNT_HW_CACHE_OP_MAX]
-			       [PERF_COUNT_HW_CACHE_RESULT_MAX];
-};
-
-/*
- * Values for power_pmu.flags
- */
-#define PPMU_LIMITED_PMC5_6	1	/* PMC5/6 have limited function */
-#define PPMU_ALT_SIPR		2	/* uses alternate posn for SIPR/HV */
-#define PPMU_NO_SIPR		4	/* no SIPR/HV in MMCRA at all */
-#define PPMU_NO_CONT_SAMPLING	8	/* no continuous sampling */
-
-/*
- * Values for flags to get_alternatives()
- */
-#define PPMU_LIMITED_PMC_OK	1	/* can put this on a limited PMC */
-#define PPMU_LIMITED_PMC_REQD	2	/* have to put this on a limited PMC */
-#define PPMU_ONLY_COUNT_RUN	4	/* only counting in run state */
-
-extern int register_power_pmu(struct power_pmu *);
-
-struct pt_regs;
-extern unsigned long perf_misc_flags(struct pt_regs *regs);
-extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
-
-/*
- * Only override the default definitions in include/linux/perf_event.h
- * if we have hardware PMU support.
- */
-#ifdef CONFIG_PPC_PERF_CTRS
-#define perf_misc_flags(regs)	perf_misc_flags(regs)
-#endif
-
-/*
- * The power_pmu.get_constraint function returns a 32/64-bit value and
- * a 32/64-bit mask that express the constraints between this event_id and
- * other events.
- *
- * The value and mask are divided up into (non-overlapping) bitfields
- * of three different types:
- *
- * Select field: this expresses the constraint that some set of bits
- * in MMCR* needs to be set to a specific value for this event_id.  For a
- * select field, the mask contains 1s in every bit of the field, and
- * the value contains a unique value for each possible setting of the
- * MMCR* bits.  The constraint checking code will ensure that two events
- * that set the same field in their masks have the same value in their
- * value dwords.
- *
- * Add field: this expresses the constraint that there can be at most
- * N events in a particular class.  A field of k bits can be used for
- * N <= 2^(k-1) - 1.  The mask has the most significant bit of the field
- * set (and the other bits 0), and the value has only the least significant
- * bit of the field set.  In addition, the 'add_fields' and 'test_adder'
- * in the struct power_pmu for this processor come into play.  The
- * add_fields value contains 1 in the LSB of the field, and the
- * test_adder contains 2^(k-1) - 1 - N in the field.
- *
- * NAND field: this expresses the constraint that you may not have events
- * in all of a set of classes.  (For example, on PPC970, you can't select
- * events from the FPU, ISU and IDU simultaneously, although any two are
- * possible.)  For N classes, the field is N+1 bits wide, and each class
- * is assigned one bit from the least-significant N bits.  The mask has
- * only the most-significant bit set, and the value has only the bit
- * for the event_id's class set.  The test_adder has the least significant
- * bit set in the field.
- *
- * If an event_id is not subject to the constraint expressed by a particular
- * field, then it will have 0 in both the mask and value for that field.
- */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/pgalloc-32.h b/ANDROID_3.4.5/arch/powerpc/include/asm/pgalloc-32.h
deleted file mode 100644
index 580cf73b..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/pgalloc-32.h
+++ /dev/null
@@ -1,48 +0,0 @@
-#ifndef _ASM_POWERPC_PGALLOC_32_H
-#define _ASM_POWERPC_PGALLOC_32_H
-
-#include <linux/threads.h>
-
-/* For 32-bit, all levels of page tables are just drawn from get_free_page() */
-#define MAX_PGTABLE_INDEX_SIZE	0
-
-extern void __bad_pte(pmd_t *pmd);
-
-extern pgd_t *pgd_alloc(struct mm_struct *mm);
-extern void pgd_free(struct mm_struct *mm, pgd_t *pgd);
-
-/*
- * We don't have any real pmd's, and this code never triggers because
- * the pgd will always be present..
- */
-/* #define pmd_alloc_one(mm,address)       ({ BUG(); ((pmd_t *)2); }) */
-#define pmd_free(mm, x) 		do { } while (0)
-#define __pmd_free_tlb(tlb,x,a)		do { } while (0)
-/* #define pgd_populate(mm, pmd, pte)      BUG() */
-
-#ifndef CONFIG_BOOKE
-#define pmd_populate_kernel(mm, pmd, pte)	\
-		(pmd_val(*(pmd)) = __pa(pte) | _PMD_PRESENT)
-#define pmd_populate(mm, pmd, pte)	\
-		(pmd_val(*(pmd)) = (page_to_pfn(pte) << PAGE_SHIFT) | _PMD_PRESENT)
-#define pmd_pgtable(pmd) pmd_page(pmd)
-#else
-#define pmd_populate_kernel(mm, pmd, pte)	\
-		(pmd_val(*(pmd)) = (unsigned long)pte | _PMD_PRESENT)
-#define pmd_populate(mm, pmd, pte)	\
-		(pmd_val(*(pmd)) = (unsigned long)lowmem_page_address(pte) | _PMD_PRESENT)
-#define pmd_pgtable(pmd) pmd_page(pmd)
-#endif
-
-extern pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr);
-extern pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long addr);
-
-static inline void pgtable_free(void *table, unsigned index_size)
-{
-	BUG_ON(index_size); /* 32-bit doesn't use this */
-	free_page((unsigned long)table);
-}
-
-#define check_pgt_cache()	do { } while (0)
-
-#endif /* _ASM_POWERPC_PGALLOC_32_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/pgalloc-64.h b/ANDROID_3.4.5/arch/powerpc/include/asm/pgalloc-64.h
deleted file mode 100644
index 292725ce..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/pgalloc-64.h
+++ /dev/null
@@ -1,143 +0,0 @@
-#ifndef _ASM_POWERPC_PGALLOC_64_H
-#define _ASM_POWERPC_PGALLOC_64_H
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/slab.h>
-#include <linux/cpumask.h>
-#include <linux/percpu.h>
-
-struct vmemmap_backing {
-	struct vmemmap_backing *list;
-	unsigned long phys;
-	unsigned long virt_addr;
-};
-
-/*
- * Functions that deal with pagetables that could be at any level of
- * the table need to be passed an "index_size" so they know how to
- * handle allocation.  For PTE pages (which are linked to a struct
- * page for now, and drawn from the main get_free_pages() pool), the
- * allocation size will be (2^index_size * sizeof(pointer)) and
- * allocations are drawn from the kmem_cache in PGT_CACHE(index_size).
- *
- * The maximum index size needs to be big enough to allow any
- * pagetable sizes we need, but small enough to fit in the low bits of
- * any page table pointer.  In other words all pagetables, even tiny
- * ones, must be aligned to allow at least enough low 0 bits to
- * contain this value.  This value is also used as a mask, so it must
- * be one less than a power of two.
- */
-#define MAX_PGTABLE_INDEX_SIZE	0xf
-
-extern struct kmem_cache *pgtable_cache[];
-#define PGT_CACHE(shift) (pgtable_cache[(shift)-1])
-
-static inline pgd_t *pgd_alloc(struct mm_struct *mm)
-{
-	return kmem_cache_alloc(PGT_CACHE(PGD_INDEX_SIZE), GFP_KERNEL);
-}
-
-static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
-{
-	kmem_cache_free(PGT_CACHE(PGD_INDEX_SIZE), pgd);
-}
-
-#ifndef CONFIG_PPC_64K_PAGES
-
-#define pgd_populate(MM, PGD, PUD)	pgd_set(PGD, PUD)
-
-static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long addr)
-{
-	return kmem_cache_alloc(PGT_CACHE(PUD_INDEX_SIZE),
-				GFP_KERNEL|__GFP_REPEAT);
-}
-
-static inline void pud_free(struct mm_struct *mm, pud_t *pud)
-{
-	kmem_cache_free(PGT_CACHE(PUD_INDEX_SIZE), pud);
-}
-
-static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
-{
-	pud_set(pud, (unsigned long)pmd);
-}
-
-#define pmd_populate(mm, pmd, pte_page) \
-	pmd_populate_kernel(mm, pmd, page_address(pte_page))
-#define pmd_populate_kernel(mm, pmd, pte) pmd_set(pmd, (unsigned long)(pte))
-#define pmd_pgtable(pmd) pmd_page(pmd)
-
-
-#else /* CONFIG_PPC_64K_PAGES */
-
-#define pud_populate(mm, pud, pmd)	pud_set(pud, (unsigned long)pmd)
-
-static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd,
-				       pte_t *pte)
-{
-	pmd_set(pmd, (unsigned long)pte);
-}
-
-#define pmd_populate(mm, pmd, pte_page) \
-	pmd_populate_kernel(mm, pmd, page_address(pte_page))
-#define pmd_pgtable(pmd) pmd_page(pmd)
-
-#endif /* CONFIG_PPC_64K_PAGES */
-
-static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
-{
-	return kmem_cache_alloc(PGT_CACHE(PMD_INDEX_SIZE),
-				GFP_KERNEL|__GFP_REPEAT);
-}
-
-static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd)
-{
-	kmem_cache_free(PGT_CACHE(PMD_INDEX_SIZE), pmd);
-}
-
-static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
-					  unsigned long address)
-{
-        return (pte_t *)__get_free_page(GFP_KERNEL | __GFP_REPEAT | __GFP_ZERO);
-}
-
-static inline pgtable_t pte_alloc_one(struct mm_struct *mm,
-					unsigned long address)
-{
-	struct page *page;
-	pte_t *pte;
-
-	pte = pte_alloc_one_kernel(mm, address);
-	if (!pte)
-		return NULL;
-	page = virt_to_page(pte);
-	pgtable_page_ctor(page);
-	return page;
-}
-
-static inline void pgtable_free(void *table, unsigned index_size)
-{
-	if (!index_size)
-		free_page((unsigned long)table);
-	else {
-		BUG_ON(index_size > MAX_PGTABLE_INDEX_SIZE);
-		kmem_cache_free(PGT_CACHE(index_size), table);
-	}
-}
-
-#define __pmd_free_tlb(tlb, pmd, addr)		      \
-	pgtable_free_tlb(tlb, pmd, PMD_INDEX_SIZE)
-#ifndef CONFIG_PPC_64K_PAGES
-#define __pud_free_tlb(tlb, pud, addr)		      \
-	pgtable_free_tlb(tlb, pud, PUD_INDEX_SIZE)
-
-#endif /* CONFIG_PPC_64K_PAGES */
-
-#define check_pgt_cache()	do { } while (0)
-
-#endif /* _ASM_POWERPC_PGALLOC_64_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/pgalloc.h b/ANDROID_3.4.5/arch/powerpc/include/asm/pgalloc.h
deleted file mode 100644
index bf301ac6..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/pgalloc.h
+++ /dev/null
@@ -1,68 +0,0 @@
-#ifndef _ASM_POWERPC_PGALLOC_H
-#define _ASM_POWERPC_PGALLOC_H
-#ifdef __KERNEL__
-
-#include <linux/mm.h>
-
-#ifdef CONFIG_PPC_BOOK3E
-extern void tlb_flush_pgtable(struct mmu_gather *tlb, unsigned long address);
-#else /* CONFIG_PPC_BOOK3E */
-static inline void tlb_flush_pgtable(struct mmu_gather *tlb,
-				     unsigned long address)
-{
-}
-#endif /* !CONFIG_PPC_BOOK3E */
-
-static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
-{
-	free_page((unsigned long)pte);
-}
-
-static inline void pte_free(struct mm_struct *mm, pgtable_t ptepage)
-{
-	pgtable_page_dtor(ptepage);
-	__free_page(ptepage);
-}
-
-#ifdef CONFIG_PPC64
-#include <asm/pgalloc-64.h>
-#else
-#include <asm/pgalloc-32.h>
-#endif
-
-#ifdef CONFIG_SMP
-struct mmu_gather;
-extern void tlb_remove_table(struct mmu_gather *, void *);
-
-static inline void pgtable_free_tlb(struct mmu_gather *tlb, void *table, int shift)
-{
-	unsigned long pgf = (unsigned long)table;
-	BUG_ON(shift > MAX_PGTABLE_INDEX_SIZE);
-	pgf |= shift;
-	tlb_remove_table(tlb, (void *)pgf);
-}
-
-static inline void __tlb_remove_table(void *_table)
-{
-	void *table = (void *)((unsigned long)_table & ~MAX_PGTABLE_INDEX_SIZE);
-	unsigned shift = (unsigned long)_table & MAX_PGTABLE_INDEX_SIZE;
-
-	pgtable_free(table, shift);
-}
-#else /* CONFIG_SMP */
-static inline void pgtable_free_tlb(struct mmu_gather *tlb, void *table, unsigned shift)
-{
-	pgtable_free(table, shift);
-}
-#endif /* !CONFIG_SMP */
-
-static inline void __pte_free_tlb(struct mmu_gather *tlb, struct page *ptepage,
-				  unsigned long address)
-{
-	tlb_flush_pgtable(tlb, address);
-	pgtable_page_dtor(ptepage);
-	pgtable_free_tlb(tlb, page_address(ptepage), 0);
-}
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_PGALLOC_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/pgtable-ppc32.h b/ANDROID_3.4.5/arch/powerpc/include/asm/pgtable-ppc32.h
deleted file mode 100644
index 47edde8c..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/pgtable-ppc32.h
+++ /dev/null
@@ -1,341 +0,0 @@
-#ifndef _ASM_POWERPC_PGTABLE_PPC32_H
-#define _ASM_POWERPC_PGTABLE_PPC32_H
-
-#include <asm-generic/pgtable-nopmd.h>
-
-#ifndef __ASSEMBLY__
-#include <linux/sched.h>
-#include <linux/threads.h>
-#include <asm/io.h>			/* For sub-arch specific PPC_PIN_SIZE */
-
-extern unsigned long va_to_phys(unsigned long address);
-extern pte_t *va_to_pte(unsigned long address);
-extern unsigned long ioremap_bot;
-
-#ifdef CONFIG_44x
-extern int icache_44x_need_flush;
-#endif
-
-#endif /* __ASSEMBLY__ */
-
-/*
- * The normal case is that PTEs are 32-bits and we have a 1-page
- * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages.  -- paulus
- *
- * For any >32-bit physical address platform, we can use the following
- * two level page table layout where the pgdir is 8KB and the MS 13 bits
- * are an index to the second level table.  The combined pgdir/pmd first
- * level has 2048 entries and the second level has 512 64-bit PTE entries.
- * -Matt
- */
-/* PGDIR_SHIFT determines what a top-level page table entry can map */
-#define PGDIR_SHIFT	(PAGE_SHIFT + PTE_SHIFT)
-#define PGDIR_SIZE	(1UL << PGDIR_SHIFT)
-#define PGDIR_MASK	(~(PGDIR_SIZE-1))
-
-/*
- * entries per page directory level: our page-table tree is two-level, so
- * we don't really have any PMD directory.
- */
-#ifndef __ASSEMBLY__
-#define PTE_TABLE_SIZE	(sizeof(pte_t) << PTE_SHIFT)
-#define PGD_TABLE_SIZE	(sizeof(pgd_t) << (32 - PGDIR_SHIFT))
-#endif	/* __ASSEMBLY__ */
-
-#define PTRS_PER_PTE	(1 << PTE_SHIFT)
-#define PTRS_PER_PMD	1
-#define PTRS_PER_PGD	(1 << (32 - PGDIR_SHIFT))
-
-#define USER_PTRS_PER_PGD	(TASK_SIZE / PGDIR_SIZE)
-#define FIRST_USER_ADDRESS	0
-
-#define pte_ERROR(e) \
-	printk("%s:%d: bad pte %llx.\n", __FILE__, __LINE__, \
-		(unsigned long long)pte_val(e))
-#define pgd_ERROR(e) \
-	printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
-
-/*
- * This is the bottom of the PKMAP area with HIGHMEM or an arbitrary
- * value (for now) on others, from where we can start layout kernel
- * virtual space that goes below PKMAP and FIXMAP
- */
-#ifdef CONFIG_HIGHMEM
-#define KVIRT_TOP	PKMAP_BASE
-#else
-#define KVIRT_TOP	(0xfe000000UL)	/* for now, could be FIXMAP_BASE ? */
-#endif
-
-/*
- * ioremap_bot starts at that address. Early ioremaps move down from there,
- * until mem_init() at which point this becomes the top of the vmalloc
- * and ioremap space
- */
-#ifdef CONFIG_NOT_COHERENT_CACHE
-#define IOREMAP_TOP	((KVIRT_TOP - CONFIG_CONSISTENT_SIZE) & PAGE_MASK)
-#else
-#define IOREMAP_TOP	KVIRT_TOP
-#endif
-
-/*
- * Just any arbitrary offset to the start of the vmalloc VM area: the
- * current 16MB value just means that there will be a 64MB "hole" after the
- * physical memory until the kernel virtual memory starts.  That means that
- * any out-of-bounds memory accesses will hopefully be caught.
- * The vmalloc() routines leaves a hole of 4kB between each vmalloced
- * area for the same reason. ;)
- *
- * We no longer map larger than phys RAM with the BATs so we don't have
- * to worry about the VMALLOC_OFFSET causing problems.  We do have to worry
- * about clashes between our early calls to ioremap() that start growing down
- * from ioremap_base being run into the VM area allocations (growing upwards
- * from VMALLOC_START).  For this reason we have ioremap_bot to check when
- * we actually run into our mappings setup in the early boot with the VM
- * system.  This really does become a problem for machines with good amounts
- * of RAM.  -- Cort
- */
-#define VMALLOC_OFFSET (0x1000000) /* 16M */
-#ifdef PPC_PIN_SIZE
-#define VMALLOC_START (((_ALIGN((long)high_memory, PPC_PIN_SIZE) + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
-#else
-#define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
-#endif
-#define VMALLOC_END	ioremap_bot
-
-/*
- * Bits in a linux-style PTE.  These match the bits in the
- * (hardware-defined) PowerPC PTE as closely as possible.
- */
-
-#if defined(CONFIG_40x)
-#include <asm/pte-40x.h>
-#elif defined(CONFIG_44x)
-#include <asm/pte-44x.h>
-#elif defined(CONFIG_FSL_BOOKE) && defined(CONFIG_PTE_64BIT)
-#include <asm/pte-book3e.h>
-#elif defined(CONFIG_FSL_BOOKE)
-#include <asm/pte-fsl-booke.h>
-#elif defined(CONFIG_8xx)
-#include <asm/pte-8xx.h>
-#else /* CONFIG_6xx */
-#include <asm/pte-hash32.h>
-#endif
-
-/* And here we include common definitions */
-#include <asm/pte-common.h>
-
-#ifndef __ASSEMBLY__
-
-#define pte_clear(mm, addr, ptep) \
-	do { pte_update(ptep, ~_PAGE_HASHPTE, 0); } while (0)
-
-#define pmd_none(pmd)		(!pmd_val(pmd))
-#define	pmd_bad(pmd)		(pmd_val(pmd) & _PMD_BAD)
-#define	pmd_present(pmd)	(pmd_val(pmd) & _PMD_PRESENT_MASK)
-#define	pmd_clear(pmdp)		do { pmd_val(*(pmdp)) = 0; } while (0)
-
-/*
- * When flushing the tlb entry for a page, we also need to flush the hash
- * table entry.  flush_hash_pages is assembler (for speed) in hashtable.S.
- */
-extern int flush_hash_pages(unsigned context, unsigned long va,
-			    unsigned long pmdval, int count);
-
-/* Add an HPTE to the hash table */
-extern void add_hash_page(unsigned context, unsigned long va,
-			  unsigned long pmdval);
-
-/* Flush an entry from the TLB/hash table */
-extern void flush_hash_entry(struct mm_struct *mm, pte_t *ptep,
-			     unsigned long address);
-
-/*
- * PTE updates. This function is called whenever an existing
- * valid PTE is updated. This does -not- include set_pte_at()
- * which nowadays only sets a new PTE.
- *
- * Depending on the type of MMU, we may need to use atomic updates
- * and the PTE may be either 32 or 64 bit wide. In the later case,
- * when using atomic updates, only the low part of the PTE is
- * accessed atomically.
- *
- * In addition, on 44x, we also maintain a global flag indicating
- * that an executable user mapping was modified, which is needed
- * to properly flush the virtually tagged instruction cache of
- * those implementations.
- */
-#ifndef CONFIG_PTE_64BIT
-static inline unsigned long pte_update(pte_t *p,
-				       unsigned long clr,
-				       unsigned long set)
-{
-#ifdef PTE_ATOMIC_UPDATES
-	unsigned long old, tmp;
-
-	__asm__ __volatile__("\
-1:	lwarx	%0,0,%3\n\
-	andc	%1,%0,%4\n\
-	or	%1,%1,%5\n"
-	PPC405_ERR77(0,%3)
-"	stwcx.	%1,0,%3\n\
-	bne-	1b"
-	: "=&r" (old), "=&r" (tmp), "=m" (*p)
-	: "r" (p), "r" (clr), "r" (set), "m" (*p)
-	: "cc" );
-#else /* PTE_ATOMIC_UPDATES */
-	unsigned long old = pte_val(*p);
-	*p = __pte((old & ~clr) | set);
-#endif /* !PTE_ATOMIC_UPDATES */
-
-#ifdef CONFIG_44x
-	if ((old & _PAGE_USER) && (old & _PAGE_EXEC))
-		icache_44x_need_flush = 1;
-#endif
-	return old;
-}
-#else /* CONFIG_PTE_64BIT */
-static inline unsigned long long pte_update(pte_t *p,
-					    unsigned long clr,
-					    unsigned long set)
-{
-#ifdef PTE_ATOMIC_UPDATES
-	unsigned long long old;
-	unsigned long tmp;
-
-	__asm__ __volatile__("\
-1:	lwarx	%L0,0,%4\n\
-	lwzx	%0,0,%3\n\
-	andc	%1,%L0,%5\n\
-	or	%1,%1,%6\n"
-	PPC405_ERR77(0,%3)
-"	stwcx.	%1,0,%4\n\
-	bne-	1b"
-	: "=&r" (old), "=&r" (tmp), "=m" (*p)
-	: "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p)
-	: "cc" );
-#else /* PTE_ATOMIC_UPDATES */
-	unsigned long long old = pte_val(*p);
-	*p = __pte((old & ~(unsigned long long)clr) | set);
-#endif /* !PTE_ATOMIC_UPDATES */
-
-#ifdef CONFIG_44x
-	if ((old & _PAGE_USER) && (old & _PAGE_EXEC))
-		icache_44x_need_flush = 1;
-#endif
-	return old;
-}
-#endif /* CONFIG_PTE_64BIT */
-
-/*
- * 2.6 calls this without flushing the TLB entry; this is wrong
- * for our hash-based implementation, we fix that up here.
- */
-#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
-static inline int __ptep_test_and_clear_young(unsigned int context, unsigned long addr, pte_t *ptep)
-{
-	unsigned long old;
-	old = pte_update(ptep, _PAGE_ACCESSED, 0);
-#if _PAGE_HASHPTE != 0
-	if (old & _PAGE_HASHPTE) {
-		unsigned long ptephys = __pa(ptep) & PAGE_MASK;
-		flush_hash_pages(context, addr, ptephys, 1);
-	}
-#endif
-	return (old & _PAGE_ACCESSED) != 0;
-}
-#define ptep_test_and_clear_young(__vma, __addr, __ptep) \
-	__ptep_test_and_clear_young((__vma)->vm_mm->context.id, __addr, __ptep)
-
-#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
-static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
-				       pte_t *ptep)
-{
-	return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0));
-}
-
-#define __HAVE_ARCH_PTEP_SET_WRPROTECT
-static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
-				      pte_t *ptep)
-{
-	pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), 0);
-}
-static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
-					   unsigned long addr, pte_t *ptep)
-{
-	ptep_set_wrprotect(mm, addr, ptep);
-}
-
-
-static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry)
-{
-	unsigned long bits = pte_val(entry) &
-		(_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC);
-	pte_update(ptep, 0, bits);
-}
-
-#define __HAVE_ARCH_PTE_SAME
-#define pte_same(A,B)	(((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)
-
-/*
- * Note that on Book E processors, the pmd contains the kernel virtual
- * (lowmem) address of the pte page.  The physical address is less useful
- * because everything runs with translation enabled (even the TLB miss
- * handler).  On everything else the pmd contains the physical address
- * of the pte page.  -- paulus
- */
-#ifndef CONFIG_BOOKE
-#define pmd_page_vaddr(pmd)	\
-	((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
-#define pmd_page(pmd)		\
-	pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)
-#else
-#define pmd_page_vaddr(pmd)	\
-	((unsigned long) (pmd_val(pmd) & PAGE_MASK))
-#define pmd_page(pmd)		\
-	pfn_to_page((__pa(pmd_val(pmd)) >> PAGE_SHIFT))
-#endif
-
-/* to find an entry in a kernel page-table-directory */
-#define pgd_offset_k(address) pgd_offset(&init_mm, address)
-
-/* to find an entry in a page-table-directory */
-#define pgd_index(address)	 ((address) >> PGDIR_SHIFT)
-#define pgd_offset(mm, address)	 ((mm)->pgd + pgd_index(address))
-
-/* Find an entry in the third-level page table.. */
-#define pte_index(address)		\
-	(((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
-#define pte_offset_kernel(dir, addr)	\
-	((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(addr))
-#define pte_offset_map(dir, addr)		\
-	((pte_t *) kmap_atomic(pmd_page(*(dir))) + pte_index(addr))
-#define pte_unmap(pte)		kunmap_atomic(pte)
-
-/*
- * Encode and decode a swap entry.
- * Note that the bits we use in a PTE for representing a swap entry
- * must not include the _PAGE_PRESENT bit, the _PAGE_FILE bit, or the
- *_PAGE_HASHPTE bit (if used).  -- paulus
- */
-#define __swp_type(entry)		((entry).val & 0x1f)
-#define __swp_offset(entry)		((entry).val >> 5)
-#define __swp_entry(type, offset)	((swp_entry_t) { (type) | ((offset) << 5) })
-#define __pte_to_swp_entry(pte)		((swp_entry_t) { pte_val(pte) >> 3 })
-#define __swp_entry_to_pte(x)		((pte_t) { (x).val << 3 })
-
-/* Encode and decode a nonlinear file mapping entry */
-#define PTE_FILE_MAX_BITS	29
-#define pte_to_pgoff(pte)	(pte_val(pte) >> 3)
-#define pgoff_to_pte(off)	((pte_t) { ((off) << 3) | _PAGE_FILE })
-
-/*
- * No page table caches to initialise
- */
-#define pgtable_cache_init()	do { } while (0)
-
-extern int get_pteptr(struct mm_struct *mm, unsigned long addr, pte_t **ptep,
-		      pmd_t **pmdp);
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* _ASM_POWERPC_PGTABLE_PPC32_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/pgtable-ppc64-4k.h b/ANDROID_3.4.5/arch/powerpc/include/asm/pgtable-ppc64-4k.h
deleted file mode 100644
index 6eefdcff..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/pgtable-ppc64-4k.h
+++ /dev/null
@@ -1,74 +0,0 @@
-#ifndef _ASM_POWERPC_PGTABLE_PPC64_4K_H
-#define _ASM_POWERPC_PGTABLE_PPC64_4K_H
-/*
- * Entries per page directory level.  The PTE level must use a 64b record
- * for each page table entry.  The PMD and PGD level use a 32b record for
- * each entry by assuming that each entry is page aligned.
- */
-#define PTE_INDEX_SIZE  9
-#define PMD_INDEX_SIZE  7
-#define PUD_INDEX_SIZE  7
-#define PGD_INDEX_SIZE  9
-
-#ifndef __ASSEMBLY__
-#define PTE_TABLE_SIZE	(sizeof(pte_t) << PTE_INDEX_SIZE)
-#define PMD_TABLE_SIZE	(sizeof(pmd_t) << PMD_INDEX_SIZE)
-#define PUD_TABLE_SIZE	(sizeof(pud_t) << PUD_INDEX_SIZE)
-#define PGD_TABLE_SIZE	(sizeof(pgd_t) << PGD_INDEX_SIZE)
-#endif	/* __ASSEMBLY__ */
-
-#define PTRS_PER_PTE	(1 << PTE_INDEX_SIZE)
-#define PTRS_PER_PMD	(1 << PMD_INDEX_SIZE)
-#define PTRS_PER_PUD	(1 << PMD_INDEX_SIZE)
-#define PTRS_PER_PGD	(1 << PGD_INDEX_SIZE)
-
-/* PMD_SHIFT determines what a second-level page table entry can map */
-#define PMD_SHIFT	(PAGE_SHIFT + PTE_INDEX_SIZE)
-#define PMD_SIZE	(1UL << PMD_SHIFT)
-#define PMD_MASK	(~(PMD_SIZE-1))
-
-/* With 4k base page size, hugepage PTEs go at the PMD level */
-#define MIN_HUGEPTE_SHIFT	PMD_SHIFT
-
-/* PUD_SHIFT determines what a third-level page table entry can map */
-#define PUD_SHIFT	(PMD_SHIFT + PMD_INDEX_SIZE)
-#define PUD_SIZE	(1UL << PUD_SHIFT)
-#define PUD_MASK	(~(PUD_SIZE-1))
-
-/* PGDIR_SHIFT determines what a fourth-level page table entry can map */
-#define PGDIR_SHIFT	(PUD_SHIFT + PUD_INDEX_SIZE)
-#define PGDIR_SIZE	(1UL << PGDIR_SHIFT)
-#define PGDIR_MASK	(~(PGDIR_SIZE-1))
-
-/* Bits to mask out from a PMD to get to the PTE page */
-#define PMD_MASKED_BITS		0
-/* Bits to mask out from a PUD to get to the PMD page */
-#define PUD_MASKED_BITS		0
-/* Bits to mask out from a PGD to get to the PUD page */
-#define PGD_MASKED_BITS		0
-
-
-/*
- * 4-level page tables related bits
- */
-
-#define pgd_none(pgd)		(!pgd_val(pgd))
-#define pgd_bad(pgd)		(pgd_val(pgd) == 0)
-#define pgd_present(pgd)	(pgd_val(pgd) != 0)
-#define pgd_clear(pgdp)		(pgd_val(*(pgdp)) = 0)
-#define pgd_page_vaddr(pgd)	(pgd_val(pgd) & ~PGD_MASKED_BITS)
-#define pgd_page(pgd)		virt_to_page(pgd_page_vaddr(pgd))
-
-#define pud_offset(pgdp, addr)	\
-  (((pud_t *) pgd_page_vaddr(*(pgdp))) + \
-    (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)))
-
-#define pud_ERROR(e) \
-	printk("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e))
-
-/*
- * On all 4K setups, remap_4k_pfn() equates to remap_pfn_range() */
-#define remap_4k_pfn(vma, addr, pfn, prot)	\
-	remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, (prot))
-
-#endif /* _ASM_POWERPC_PGTABLE_PPC64_4K_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/pgtable-ppc64-64k.h b/ANDROID_3.4.5/arch/powerpc/include/asm/pgtable-ppc64-64k.h
deleted file mode 100644
index 90533ddc..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/pgtable-ppc64-64k.h
+++ /dev/null
@@ -1,40 +0,0 @@
-#ifndef _ASM_POWERPC_PGTABLE_PPC64_64K_H
-#define _ASM_POWERPC_PGTABLE_PPC64_64K_H
-
-#include <asm-generic/pgtable-nopud.h>
-
-
-#define PTE_INDEX_SIZE  12
-#define PMD_INDEX_SIZE  12
-#define PUD_INDEX_SIZE	0
-#define PGD_INDEX_SIZE  4
-
-#ifndef __ASSEMBLY__
-#define PTE_TABLE_SIZE	(sizeof(real_pte_t) << PTE_INDEX_SIZE)
-#define PMD_TABLE_SIZE	(sizeof(pmd_t) << PMD_INDEX_SIZE)
-#define PGD_TABLE_SIZE	(sizeof(pgd_t) << PGD_INDEX_SIZE)
-#endif	/* __ASSEMBLY__ */
-
-#define PTRS_PER_PTE	(1 << PTE_INDEX_SIZE)
-#define PTRS_PER_PMD	(1 << PMD_INDEX_SIZE)
-#define PTRS_PER_PGD	(1 << PGD_INDEX_SIZE)
-
-/* With 4k base page size, hugepage PTEs go at the PMD level */
-#define MIN_HUGEPTE_SHIFT	PAGE_SHIFT
-
-/* PMD_SHIFT determines what a second-level page table entry can map */
-#define PMD_SHIFT	(PAGE_SHIFT + PTE_INDEX_SIZE)
-#define PMD_SIZE	(1UL << PMD_SHIFT)
-#define PMD_MASK	(~(PMD_SIZE-1))
-
-/* PGDIR_SHIFT determines what a third-level page table entry can map */
-#define PGDIR_SHIFT	(PMD_SHIFT + PMD_INDEX_SIZE)
-#define PGDIR_SIZE	(1UL << PGDIR_SHIFT)
-#define PGDIR_MASK	(~(PGDIR_SIZE-1))
-
-/* Bits to mask out from a PMD to get to the PTE page */
-#define PMD_MASKED_BITS		0x1ff
-/* Bits to mask out from a PGD/PUD to get to the PMD page */
-#define PUD_MASKED_BITS		0x1ff
-
-#endif /* _ASM_POWERPC_PGTABLE_PPC64_64K_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/pgtable-ppc64.h b/ANDROID_3.4.5/arch/powerpc/include/asm/pgtable-ppc64.h
deleted file mode 100644
index c4205616..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/pgtable-ppc64.h
+++ /dev/null
@@ -1,395 +0,0 @@
-#ifndef _ASM_POWERPC_PGTABLE_PPC64_H_
-#define _ASM_POWERPC_PGTABLE_PPC64_H_
-/*
- * This file contains the functions and defines necessary to modify and use
- * the ppc64 hashed page table.
- */
-
-#ifdef CONFIG_PPC_64K_PAGES
-#include <asm/pgtable-ppc64-64k.h>
-#else
-#include <asm/pgtable-ppc64-4k.h>
-#endif
-
-#define FIRST_USER_ADDRESS	0
-
-/*
- * Size of EA range mapped by our pagetables.
- */
-#define PGTABLE_EADDR_SIZE (PTE_INDEX_SIZE + PMD_INDEX_SIZE + \
-                	    PUD_INDEX_SIZE + PGD_INDEX_SIZE + PAGE_SHIFT)
-#define PGTABLE_RANGE (ASM_CONST(1) << PGTABLE_EADDR_SIZE)
-
-
-/* Some sanity checking */
-#if TASK_SIZE_USER64 > PGTABLE_RANGE
-#error TASK_SIZE_USER64 exceeds pagetable range
-#endif
-
-#ifdef CONFIG_PPC_STD_MMU_64
-#if TASK_SIZE_USER64 > (1UL << (USER_ESID_BITS + SID_SHIFT))
-#error TASK_SIZE_USER64 exceeds user VSID range
-#endif
-#endif
-
-/*
- * Define the address range of the kernel non-linear virtual area
- */
-
-#ifdef CONFIG_PPC_BOOK3E
-#define KERN_VIRT_START ASM_CONST(0x8000000000000000)
-#else
-#define KERN_VIRT_START ASM_CONST(0xD000000000000000)
-#endif
-#define KERN_VIRT_SIZE	PGTABLE_RANGE
-
-/*
- * The vmalloc space starts at the beginning of that region, and
- * occupies half of it on hash CPUs and a quarter of it on Book3E
- * (we keep a quarter for the virtual memmap)
- */
-#define VMALLOC_START	KERN_VIRT_START
-#ifdef CONFIG_PPC_BOOK3E
-#define VMALLOC_SIZE	(KERN_VIRT_SIZE >> 2)
-#else
-#define VMALLOC_SIZE	(KERN_VIRT_SIZE >> 1)
-#endif
-#define VMALLOC_END	(VMALLOC_START + VMALLOC_SIZE)
-
-/*
- * The second half of the kernel virtual space is used for IO mappings,
- * it's itself carved into the PIO region (ISA and PHB IO space) and
- * the ioremap space
- *
- *  ISA_IO_BASE = KERN_IO_START, 64K reserved area
- *  PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces
- * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE
- */
-#define KERN_IO_START	(KERN_VIRT_START + (KERN_VIRT_SIZE >> 1))
-#define FULL_IO_SIZE	0x80000000ul
-#define  ISA_IO_BASE	(KERN_IO_START)
-#define  ISA_IO_END	(KERN_IO_START + 0x10000ul)
-#define  PHB_IO_BASE	(ISA_IO_END)
-#define  PHB_IO_END	(KERN_IO_START + FULL_IO_SIZE)
-#define IOREMAP_BASE	(PHB_IO_END)
-#define IOREMAP_END	(KERN_VIRT_START + KERN_VIRT_SIZE)
-
-
-/*
- * Region IDs
- */
-#define REGION_SHIFT		60UL
-#define REGION_MASK		(0xfUL << REGION_SHIFT)
-#define REGION_ID(ea)		(((unsigned long)(ea)) >> REGION_SHIFT)
-
-#define VMALLOC_REGION_ID	(REGION_ID(VMALLOC_START))
-#define KERNEL_REGION_ID	(REGION_ID(PAGE_OFFSET))
-#define VMEMMAP_REGION_ID	(0xfUL)	/* Server only */
-#define USER_REGION_ID		(0UL)
-
-/*
- * Defines the address of the vmemap area, in its own region on
- * hash table CPUs and after the vmalloc space on Book3E
- */
-#ifdef CONFIG_PPC_BOOK3E
-#define VMEMMAP_BASE		VMALLOC_END
-#define VMEMMAP_END		KERN_IO_START
-#else
-#define VMEMMAP_BASE		(VMEMMAP_REGION_ID << REGION_SHIFT)
-#endif
-#define vmemmap			((struct page *)VMEMMAP_BASE)
-
-
-/*
- * Include the PTE bits definitions
- */
-#ifdef CONFIG_PPC_BOOK3S
-#include <asm/pte-hash64.h>
-#else
-#include <asm/pte-book3e.h>
-#endif
-#include <asm/pte-common.h>
-
-#ifdef CONFIG_PPC_MM_SLICES
-#define HAVE_ARCH_UNMAPPED_AREA
-#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
-#endif /* CONFIG_PPC_MM_SLICES */
-
-#ifndef __ASSEMBLY__
-
-#include <linux/stddef.h>
-#include <asm/tlbflush.h>
-
-/*
- * This is the default implementation of various PTE accessors, it's
- * used in all cases except Book3S with 64K pages where we have a
- * concept of sub-pages
- */
-#ifndef __real_pte
-
-#ifdef STRICT_MM_TYPECHECKS
-#define __real_pte(e,p)		((real_pte_t){(e)})
-#define __rpte_to_pte(r)	((r).pte)
-#else
-#define __real_pte(e,p)		(e)
-#define __rpte_to_pte(r)	(__pte(r))
-#endif
-#define __rpte_to_hidx(r,index)	(pte_val(__rpte_to_pte(r)) >> 12)
-
-#define pte_iterate_hashed_subpages(rpte, psize, va, index, shift)       \
-	do {							         \
-		index = 0;					         \
-		shift = mmu_psize_defs[psize].shift;		         \
-
-#define pte_iterate_hashed_end() } while(0)
-
-#ifdef CONFIG_PPC_HAS_HASH_64K
-#define pte_pagesize_index(mm, addr, pte)	get_slice_psize(mm, addr)
-#else
-#define pte_pagesize_index(mm, addr, pte)	MMU_PAGE_4K
-#endif
-
-#endif /* __real_pte */
-
-
-/* pte_clear moved to later in this file */
-
-#define PMD_BAD_BITS		(PTE_TABLE_SIZE-1)
-#define PUD_BAD_BITS		(PMD_TABLE_SIZE-1)
-
-#define pmd_set(pmdp, pmdval) 	(pmd_val(*(pmdp)) = (pmdval))
-#define pmd_none(pmd)		(!pmd_val(pmd))
-#define	pmd_bad(pmd)		(!is_kernel_addr(pmd_val(pmd)) \
-				 || (pmd_val(pmd) & PMD_BAD_BITS))
-#define	pmd_present(pmd)	(pmd_val(pmd) != 0)
-#define	pmd_clear(pmdp)		(pmd_val(*(pmdp)) = 0)
-#define pmd_page_vaddr(pmd)	(pmd_val(pmd) & ~PMD_MASKED_BITS)
-#define pmd_page(pmd)		virt_to_page(pmd_page_vaddr(pmd))
-
-#define pud_set(pudp, pudval)	(pud_val(*(pudp)) = (pudval))
-#define pud_none(pud)		(!pud_val(pud))
-#define	pud_bad(pud)		(!is_kernel_addr(pud_val(pud)) \
-				 || (pud_val(pud) & PUD_BAD_BITS))
-#define pud_present(pud)	(pud_val(pud) != 0)
-#define pud_clear(pudp)		(pud_val(*(pudp)) = 0)
-#define pud_page_vaddr(pud)	(pud_val(pud) & ~PUD_MASKED_BITS)
-#define pud_page(pud)		virt_to_page(pud_page_vaddr(pud))
-
-#define pgd_set(pgdp, pudp)	({pgd_val(*(pgdp)) = (unsigned long)(pudp);})
-
-/*
- * Find an entry in a page-table-directory.  We combine the address region
- * (the high order N bits) and the pgd portion of the address.
- */
-/* to avoid overflow in free_pgtables we don't use PTRS_PER_PGD here */
-#define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & 0x1ff)
-
-#define pgd_offset(mm, address)	 ((mm)->pgd + pgd_index(address))
-
-#define pmd_offset(pudp,addr) \
-  (((pmd_t *) pud_page_vaddr(*(pudp))) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)))
-
-#define pte_offset_kernel(dir,addr) \
-  (((pte_t *) pmd_page_vaddr(*(dir))) + (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
-
-#define pte_offset_map(dir,addr)	pte_offset_kernel((dir), (addr))
-#define pte_unmap(pte)			do { } while(0)
-
-/* to find an entry in a kernel page-table-directory */
-/* This now only contains the vmalloc pages */
-#define pgd_offset_k(address) pgd_offset(&init_mm, address)
-
-
-/* Atomic PTE updates */
-static inline unsigned long pte_update(struct mm_struct *mm,
-				       unsigned long addr,
-				       pte_t *ptep, unsigned long clr,
-				       int huge)
-{
-#ifdef PTE_ATOMIC_UPDATES
-	unsigned long old, tmp;
-
-	__asm__ __volatile__(
-	"1:	ldarx	%0,0,%3		# pte_update\n\
-	andi.	%1,%0,%6\n\
-	bne-	1b \n\
-	andc	%1,%0,%4 \n\
-	stdcx.	%1,0,%3 \n\
-	bne-	1b"
-	: "=&r" (old), "=&r" (tmp), "=m" (*ptep)
-	: "r" (ptep), "r" (clr), "m" (*ptep), "i" (_PAGE_BUSY)
-	: "cc" );
-#else
-	unsigned long old = pte_val(*ptep);
-	*ptep = __pte(old & ~clr);
-#endif
-	/* huge pages use the old page table lock */
-	if (!huge)
-		assert_pte_locked(mm, addr);
-
-#ifdef CONFIG_PPC_STD_MMU_64
-	if (old & _PAGE_HASHPTE)
-		hpte_need_flush(mm, addr, ptep, old, huge);
-#endif
-
-	return old;
-}
-
-static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
-					      unsigned long addr, pte_t *ptep)
-{
-	unsigned long old;
-
-       	if ((pte_val(*ptep) & (_PAGE_ACCESSED | _PAGE_HASHPTE)) == 0)
-		return 0;
-	old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0);
-	return (old & _PAGE_ACCESSED) != 0;
-}
-#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
-#define ptep_test_and_clear_young(__vma, __addr, __ptep)		   \
-({									   \
-	int __r;							   \
-	__r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \
-	__r;								   \
-})
-
-#define __HAVE_ARCH_PTEP_SET_WRPROTECT
-static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
-				      pte_t *ptep)
-{
-
-	if ((pte_val(*ptep) & _PAGE_RW) == 0)
-		return;
-
-	pte_update(mm, addr, ptep, _PAGE_RW, 0);
-}
-
-static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
-					   unsigned long addr, pte_t *ptep)
-{
-	if ((pte_val(*ptep) & _PAGE_RW) == 0)
-		return;
-
-	pte_update(mm, addr, ptep, _PAGE_RW, 1);
-}
-
-/*
- * We currently remove entries from the hashtable regardless of whether
- * the entry was young or dirty. The generic routines only flush if the
- * entry was young or dirty which is not good enough.
- *
- * We should be more intelligent about this but for the moment we override
- * these functions and force a tlb flush unconditionally
- */
-#define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
-#define ptep_clear_flush_young(__vma, __address, __ptep)		\
-({									\
-	int __young = __ptep_test_and_clear_young((__vma)->vm_mm, __address, \
-						  __ptep);		\
-	__young;							\
-})
-
-#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
-static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
-				       unsigned long addr, pte_t *ptep)
-{
-	unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0);
-	return __pte(old);
-}
-
-static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
-			     pte_t * ptep)
-{
-	pte_update(mm, addr, ptep, ~0UL, 0);
-}
-
-
-/* Set the dirty and/or accessed bits atomically in a linux PTE, this
- * function doesn't need to flush the hash entry
- */
-static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry)
-{
-	unsigned long bits = pte_val(entry) &
-		(_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC);
-
-#ifdef PTE_ATOMIC_UPDATES
-	unsigned long old, tmp;
-
-	__asm__ __volatile__(
-	"1:	ldarx	%0,0,%4\n\
-		andi.	%1,%0,%6\n\
-		bne-	1b \n\
-		or	%0,%3,%0\n\
-		stdcx.	%0,0,%4\n\
-		bne-	1b"
-	:"=&r" (old), "=&r" (tmp), "=m" (*ptep)
-	:"r" (bits), "r" (ptep), "m" (*ptep), "i" (_PAGE_BUSY)
-	:"cc");
-#else
-	unsigned long old = pte_val(*ptep);
-	*ptep = __pte(old | bits);
-#endif
-}
-
-#define __HAVE_ARCH_PTE_SAME
-#define pte_same(A,B)	(((pte_val(A) ^ pte_val(B)) & ~_PAGE_HPTEFLAGS) == 0)
-
-#define pte_ERROR(e) \
-	printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
-#define pmd_ERROR(e) \
-	printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
-#define pgd_ERROR(e) \
-	printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
-
-/* Encode and de-code a swap entry */
-#define __swp_type(entry)	(((entry).val >> 1) & 0x3f)
-#define __swp_offset(entry)	((entry).val >> 8)
-#define __swp_entry(type, offset) ((swp_entry_t){((type)<< 1)|((offset)<<8)})
-#define __pte_to_swp_entry(pte)	((swp_entry_t){pte_val(pte) >> PTE_RPN_SHIFT})
-#define __swp_entry_to_pte(x)	((pte_t) { (x).val << PTE_RPN_SHIFT })
-#define pte_to_pgoff(pte)	(pte_val(pte) >> PTE_RPN_SHIFT)
-#define pgoff_to_pte(off)	((pte_t) {((off) << PTE_RPN_SHIFT)|_PAGE_FILE})
-#define PTE_FILE_MAX_BITS	(BITS_PER_LONG - PTE_RPN_SHIFT)
-
-void pgtable_cache_add(unsigned shift, void (*ctor)(void *));
-void pgtable_cache_init(void);
-
-/*
- * find_linux_pte returns the address of a linux pte for a given
- * effective address and directory.  If not found, it returns zero.
- */
-static inline pte_t *find_linux_pte(pgd_t *pgdir, unsigned long ea)
-{
-	pgd_t *pg;
-	pud_t *pu;
-	pmd_t *pm;
-	pte_t *pt = NULL;
-
-	pg = pgdir + pgd_index(ea);
-	if (!pgd_none(*pg)) {
-		pu = pud_offset(pg, ea);
-		if (!pud_none(*pu)) {
-			pm = pmd_offset(pu, ea);
-			if (pmd_present(*pm))
-				pt = pte_offset_kernel(pm, ea);
-		}
-	}
-	return pt;
-}
-
-#ifdef CONFIG_HUGETLB_PAGE
-pte_t *find_linux_pte_or_hugepte(pgd_t *pgdir, unsigned long ea,
-				 unsigned *shift);
-#else
-static inline pte_t *find_linux_pte_or_hugepte(pgd_t *pgdir, unsigned long ea,
-					       unsigned *shift)
-{
-	if (shift)
-		*shift = 0;
-	return find_linux_pte(pgdir, ea);
-}
-#endif /* !CONFIG_HUGETLB_PAGE */
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* _ASM_POWERPC_PGTABLE_PPC64_H_ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/pgtable.h b/ANDROID_3.4.5/arch/powerpc/include/asm/pgtable.h
deleted file mode 100644
index 2e0e4110..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/pgtable.h
+++ /dev/null
@@ -1,224 +0,0 @@
-#ifndef _ASM_POWERPC_PGTABLE_H
-#define _ASM_POWERPC_PGTABLE_H
-#ifdef __KERNEL__
-
-#ifndef __ASSEMBLY__
-#include <asm/processor.h>		/* For TASK_SIZE */
-#include <asm/mmu.h>
-#include <asm/page.h>
-
-struct mm_struct;
-
-#ifdef CONFIG_DEBUG_VM
-extern void assert_pte_locked(struct mm_struct *mm, unsigned long addr);
-#else /* CONFIG_DEBUG_VM */
-static inline void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
-{
-}
-#endif /* !CONFIG_DEBUG_VM */
-
-#endif /* !__ASSEMBLY__ */
-
-#if defined(CONFIG_PPC64)
-#  include <asm/pgtable-ppc64.h>
-#else
-#  include <asm/pgtable-ppc32.h>
-#endif
-
-#ifndef __ASSEMBLY__
-
-/* Generic accessors to PTE bits */
-static inline int pte_write(pte_t pte)		{ return pte_val(pte) & _PAGE_RW; }
-static inline int pte_dirty(pte_t pte)		{ return pte_val(pte) & _PAGE_DIRTY; }
-static inline int pte_young(pte_t pte)		{ return pte_val(pte) & _PAGE_ACCESSED; }
-static inline int pte_file(pte_t pte)		{ return pte_val(pte) & _PAGE_FILE; }
-static inline int pte_special(pte_t pte)	{ return pte_val(pte) & _PAGE_SPECIAL; }
-static inline int pte_present(pte_t pte)	{ return pte_val(pte) & _PAGE_PRESENT; }
-static inline int pte_none(pte_t pte)		{ return (pte_val(pte) & ~_PTE_NONE_MASK) == 0; }
-static inline pgprot_t pte_pgprot(pte_t pte)	{ return __pgprot(pte_val(pte) & PAGE_PROT_BITS); }
-
-/* Conversion functions: convert a page and protection to a page entry,
- * and a page entry and page directory to the page they refer to.
- *
- * Even if PTEs can be unsigned long long, a PFN is always an unsigned
- * long for now.
- */
-static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) {
-	return __pte(((pte_basic_t)(pfn) << PTE_RPN_SHIFT) |
-		     pgprot_val(pgprot)); }
-static inline unsigned long pte_pfn(pte_t pte)	{
-	return pte_val(pte) >> PTE_RPN_SHIFT; }
-
-/* Keep these as a macros to avoid include dependency mess */
-#define pte_page(x)		pfn_to_page(pte_pfn(x))
-#define mk_pte(page, pgprot)	pfn_pte(page_to_pfn(page), (pgprot))
-
-/* Generic modifiers for PTE bits */
-static inline pte_t pte_wrprotect(pte_t pte) {
-	pte_val(pte) &= ~(_PAGE_RW | _PAGE_HWWRITE); return pte; }
-static inline pte_t pte_mkclean(pte_t pte) {
-	pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HWWRITE); return pte; }
-static inline pte_t pte_mkold(pte_t pte) {
-	pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
-static inline pte_t pte_mkwrite(pte_t pte) {
-	pte_val(pte) |= _PAGE_RW; return pte; }
-static inline pte_t pte_mkdirty(pte_t pte) {
-	pte_val(pte) |= _PAGE_DIRTY; return pte; }
-static inline pte_t pte_mkyoung(pte_t pte) {
-	pte_val(pte) |= _PAGE_ACCESSED; return pte; }
-static inline pte_t pte_mkspecial(pte_t pte) {
-	pte_val(pte) |= _PAGE_SPECIAL; return pte; }
-static inline pte_t pte_mkhuge(pte_t pte) {
-	return pte; }
-static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
-{
-	pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot);
-	return pte;
-}
-
-
-/* Insert a PTE, top-level function is out of line. It uses an inline
- * low level function in the respective pgtable-* files
- */
-extern void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
-		       pte_t pte);
-
-/* This low level function performs the actual PTE insertion
- * Setting the PTE depends on the MMU type and other factors. It's
- * an horrible mess that I'm not going to try to clean up now but
- * I'm keeping it in one place rather than spread around
- */
-static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
-				pte_t *ptep, pte_t pte, int percpu)
-{
-#if defined(CONFIG_PPC_STD_MMU_32) && defined(CONFIG_SMP) && !defined(CONFIG_PTE_64BIT)
-	/* First case is 32-bit Hash MMU in SMP mode with 32-bit PTEs. We use the
-	 * helper pte_update() which does an atomic update. We need to do that
-	 * because a concurrent invalidation can clear _PAGE_HASHPTE. If it's a
-	 * per-CPU PTE such as a kmap_atomic, we do a simple update preserving
-	 * the hash bits instead (ie, same as the non-SMP case)
-	 */
-	if (percpu)
-		*ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
-			      | (pte_val(pte) & ~_PAGE_HASHPTE));
-	else
-		pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte));
-
-#elif defined(CONFIG_PPC32) && defined(CONFIG_PTE_64BIT)
-	/* Second case is 32-bit with 64-bit PTE.  In this case, we
-	 * can just store as long as we do the two halves in the right order
-	 * with a barrier in between. This is possible because we take care,
-	 * in the hash code, to pre-invalidate if the PTE was already hashed,
-	 * which synchronizes us with any concurrent invalidation.
-	 * In the percpu case, we also fallback to the simple update preserving
-	 * the hash bits
-	 */
-	if (percpu) {
-		*ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
-			      | (pte_val(pte) & ~_PAGE_HASHPTE));
-		return;
-	}
-#if _PAGE_HASHPTE != 0
-	if (pte_val(*ptep) & _PAGE_HASHPTE)
-		flush_hash_entry(mm, ptep, addr);
-#endif
-	__asm__ __volatile__("\
-		stw%U0%X0 %2,%0\n\
-		eieio\n\
-		stw%U0%X0 %L2,%1"
-	: "=m" (*ptep), "=m" (*((unsigned char *)ptep+4))
-	: "r" (pte) : "memory");
-
-#elif defined(CONFIG_PPC_STD_MMU_32)
-	/* Third case is 32-bit hash table in UP mode, we need to preserve
-	 * the _PAGE_HASHPTE bit since we may not have invalidated the previous
-	 * translation in the hash yet (done in a subsequent flush_tlb_xxx())
-	 * and see we need to keep track that this PTE needs invalidating
-	 */
-	*ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
-		      | (pte_val(pte) & ~_PAGE_HASHPTE));
-
-#else
-	/* Anything else just stores the PTE normally. That covers all 64-bit
-	 * cases, and 32-bit non-hash with 32-bit PTEs.
-	 */
-	*ptep = pte;
-#endif
-}
-
-
-#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
-extern int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address,
-				 pte_t *ptep, pte_t entry, int dirty);
-
-/*
- * Macro to mark a page protection value as "uncacheable".
- */
-
-#define _PAGE_CACHE_CTL	(_PAGE_COHERENT | _PAGE_GUARDED | _PAGE_NO_CACHE | \
-			 _PAGE_WRITETHRU)
-
-#define pgprot_noncached(prot)	  (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
-				            _PAGE_NO_CACHE | _PAGE_GUARDED))
-
-#define pgprot_noncached_wc(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
-				            _PAGE_NO_CACHE))
-
-#define pgprot_cached(prot)       (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
-				            _PAGE_COHERENT))
-
-#define pgprot_cached_wthru(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
-				            _PAGE_COHERENT | _PAGE_WRITETHRU))
-
-#define pgprot_cached_noncoherent(prot) \
-		(__pgprot(pgprot_val(prot) & ~_PAGE_CACHE_CTL))
-
-#define pgprot_writecombine pgprot_noncached_wc
-
-struct file;
-extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
-				     unsigned long size, pgprot_t vma_prot);
-#define __HAVE_PHYS_MEM_ACCESS_PROT
-
-/*
- * ZERO_PAGE is a global shared page that is always zero: used
- * for zero-mapped memory areas etc..
- */
-extern unsigned long empty_zero_page[];
-#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
-
-extern pgd_t swapper_pg_dir[];
-
-extern void paging_init(void);
-
-/*
- * kern_addr_valid is intended to indicate whether an address is a valid
- * kernel address.  Most 32-bit archs define it as always true (like this)
- * but most 64-bit archs actually perform a test.  What should we do here?
- */
-#define kern_addr_valid(addr)	(1)
-
-#define io_remap_pfn_range(vma, vaddr, pfn, size, prot)		\
-		remap_pfn_range(vma, vaddr, pfn, size, prot)
-
-#include <asm-generic/pgtable.h>
-
-
-/*
- * This gets called at the end of handling a page fault, when
- * the kernel has put a new PTE into the page table for the process.
- * We use it to ensure coherency between the i-cache and d-cache
- * for the page which has just been mapped in.
- * On machines which use an MMU hash table, we use this to put a
- * corresponding HPTE into the hash table ahead of time, instead of
- * waiting for the inevitable extra hash-table miss exception.
- */
-extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *);
-
-extern int gup_hugepd(hugepd_t *hugepd, unsigned pdshift, unsigned long addr,
-		      unsigned long end, int write, struct page **pages, int *nr);
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_PGTABLE_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/pmac_feature.h b/ANDROID_3.4.5/arch/powerpc/include/asm/pmac_feature.h
deleted file mode 100644
index 10902c93..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/pmac_feature.h
+++ /dev/null
@@ -1,405 +0,0 @@
-/*
- * Definition of platform feature hooks for PowerMacs
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1998 Paul Mackerras &
- *                    Ben. Herrenschmidt.
- *
- *
- * Note: I removed media-bay details from the feature stuff, I believe it's
- *       not worth it, the media-bay driver can directly use the mac-io
- *       ASIC registers.
- *
- * Implementation note: Currently, none of these functions will block.
- * However, they may internally protect themselves with a spinlock
- * for way too long. Be prepared for at least some of these to block
- * in the future.
- *
- * Unless specifically defined, the result code is assumed to be an
- * error when negative, 0 is the default success result. Some functions
- * may return additional positive result values.
- *
- * To keep implementation simple, all feature calls are assumed to have
- * the prototype parameters (struct device_node* node, int value).
- * When either is not used, pass 0.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_POWERPC_PMAC_FEATURE_H
-#define __ASM_POWERPC_PMAC_FEATURE_H
-
-#include <asm/macio.h>
-#include <asm/machdep.h>
-
-/*
- * Known Mac motherboard models
- *
- * Please, report any error here to benh@kernel.crashing.org, thanks !
- *
- * Note that I don't fully maintain this list for Core99 & MacRISC2
- * and I'm considering removing all NewWorld entries from it and
- * entirely rely on the model string.
- */
-
-/* PowerSurge are the first generation of PCI Pmacs. This include
- * all of the Grand-Central based machines. We currently don't
- * differenciate most of them.
- */
-#define PMAC_TYPE_PSURGE		0x10	/* PowerSurge */
-#define PMAC_TYPE_ANS			0x11	/* Apple Network Server */
-
-/* Here is the infamous serie of OHare based machines
- */
-#define PMAC_TYPE_COMET			0x20	/* Believed to be PowerBook 2400 */
-#define PMAC_TYPE_HOOPER		0x21	/* Believed to be PowerBook 3400 */
-#define PMAC_TYPE_KANGA			0x22	/* PowerBook 3500 (first G3) */
-#define PMAC_TYPE_ALCHEMY		0x23	/* Alchemy motherboard base */
-#define PMAC_TYPE_GAZELLE		0x24	/* Spartacus, some 5xxx/6xxx */
-#define PMAC_TYPE_UNKNOWN_OHARE		0x2f	/* Unknown, but OHare based */
-
-/* Here are the Heathrow based machines
- * FIXME: Differenciate wallstreet,mainstreet,wallstreetII
- */
-#define PMAC_TYPE_GOSSAMER		0x30	/* Gossamer motherboard */
-#define PMAC_TYPE_SILK			0x31	/* Desktop PowerMac G3 */
-#define PMAC_TYPE_WALLSTREET		0x32	/* Wallstreet/Mainstreet PowerBook*/
-#define PMAC_TYPE_UNKNOWN_HEATHROW	0x3f	/* Unknown but heathrow based */
-
-/* Here are newworld machines based on Paddington (heathrow derivative)
- */
-#define PMAC_TYPE_101_PBOOK		0x40	/* 101 PowerBook (aka Lombard) */
-#define PMAC_TYPE_ORIG_IMAC		0x41	/* First generation iMac */
-#define PMAC_TYPE_YOSEMITE		0x42	/* B&W G3 */
-#define PMAC_TYPE_YIKES			0x43	/* Yikes G4 (PCI graphics) */
-#define PMAC_TYPE_UNKNOWN_PADDINGTON	0x4f	/* Unknown but paddington based */
-
-/* Core99 machines based on UniNorth 1.0 and 1.5
- *
- * Note: A single entry here may cover several actual models according
- * to the device-tree. (Sawtooth is most tower G4s, FW_IMAC is most
- * FireWire based iMacs, etc...). Those machines are too similar to be
- * distinguished here, when they need to be differencied, use the
- * device-tree "model" or "compatible" property.
- */
-#define PMAC_TYPE_ORIG_IBOOK		0x40	/* First iBook model (no firewire) */
-#define PMAC_TYPE_SAWTOOTH		0x41	/* Desktop G4s */
-#define PMAC_TYPE_FW_IMAC		0x42	/* FireWire iMacs (except Pangea based) */
-#define PMAC_TYPE_FW_IBOOK		0x43	/* FireWire iBooks (except iBook2) */
-#define PMAC_TYPE_CUBE			0x44	/* Cube PowerMac */
-#define PMAC_TYPE_QUICKSILVER		0x45	/* QuickSilver G4s */
-#define PMAC_TYPE_PISMO			0x46	/* Pismo PowerBook */
-#define PMAC_TYPE_TITANIUM		0x47	/* Titanium PowerBook */
-#define PMAC_TYPE_TITANIUM2		0x48	/* Titanium II PowerBook (no L3, M6) */
-#define PMAC_TYPE_TITANIUM3		0x49	/* Titanium III PowerBook (with L3 & M7) */
-#define PMAC_TYPE_TITANIUM4		0x50	/* Titanium IV PowerBook (with L3 & M9) */
-#define PMAC_TYPE_EMAC			0x50	/* eMac */
-#define PMAC_TYPE_UNKNOWN_CORE99	0x5f
-
-/* MacRisc2 with UniNorth 2.0 */
-#define PMAC_TYPE_RACKMAC		0x80	/* XServe */
-#define PMAC_TYPE_WINDTUNNEL		0x81
-
-/* MacRISC2 machines based on the Pangea chipset
- */
-#define PMAC_TYPE_PANGEA_IMAC		0x100	/* Flower Power iMac */
-#define PMAC_TYPE_IBOOK2		0x101	/* iBook2 (polycarbonate) */
-#define PMAC_TYPE_FLAT_PANEL_IMAC	0x102	/* Flat panel iMac */
-#define PMAC_TYPE_UNKNOWN_PANGEA	0x10f
-
-/* MacRISC2 machines based on the Intrepid chipset
- */
-#define PMAC_TYPE_UNKNOWN_INTREPID	0x11f	/* Generic */
-
-/* MacRISC4 / G5 machines. We don't have per-machine selection here anymore,
- * but rather machine families
- */
-#define PMAC_TYPE_POWERMAC_G5		0x150	/* U3 & U3H based */
-#define PMAC_TYPE_POWERMAC_G5_U3L	0x151	/* U3L based desktop */
-#define PMAC_TYPE_IMAC_G5		0x152	/* iMac G5 */
-#define PMAC_TYPE_XSERVE_G5		0x153	/* Xserve G5 */
-#define PMAC_TYPE_UNKNOWN_K2		0x19f	/* Any other K2 based */
-#define PMAC_TYPE_UNKNOWN_SHASTA       	0x19e	/* Any other Shasta based */
-
-/*
- * Motherboard flags
- */
-
-#define PMAC_MB_CAN_SLEEP		0x00000001
-#define PMAC_MB_HAS_FW_POWER		0x00000002
-#define PMAC_MB_OLD_CORE99		0x00000004
-#define PMAC_MB_MOBILE			0x00000008
-#define PMAC_MB_MAY_SLEEP		0x00000010
-
-/*
- * Feature calls supported on pmac
- *
- */
-
-/*
- * Use this inline wrapper
- */
-struct device_node;
-
-static inline long pmac_call_feature(int selector, struct device_node* node,
-					long param, long value)
-{
-	if (!ppc_md.feature_call || !machine_is(powermac))
-		return -ENODEV;
-	return ppc_md.feature_call(selector, node, param, value);
-}
-
-/* PMAC_FTR_SERIAL_ENABLE	(struct device_node* node, int param, int value)
- * enable/disable an SCC side. Pass the node corresponding to the
- * channel side as a parameter.
- * param is the type of port
- * if param is ored with PMAC_SCC_FLAG_XMON, then the SCC is locked enabled
- * for use by xmon.
- */
-#define PMAC_FTR_SCC_ENABLE		PMAC_FTR_DEF(0)
-	#define PMAC_SCC_ASYNC		0
-	#define PMAC_SCC_IRDA		1
-	#define PMAC_SCC_I2S1		2
-	#define PMAC_SCC_FLAG_XMON	0x00001000
-
-/* PMAC_FTR_MODEM_ENABLE	(struct device_node* node, 0, int value)
- * enable/disable the internal modem.
- */
-#define PMAC_FTR_MODEM_ENABLE		PMAC_FTR_DEF(1)
-
-/* PMAC_FTR_SWIM3_ENABLE	(struct device_node* node, 0,int value)
- * enable/disable the swim3 (floppy) cell of a mac-io ASIC
- */
-#define PMAC_FTR_SWIM3_ENABLE		PMAC_FTR_DEF(2)
-
-/* PMAC_FTR_MESH_ENABLE		(struct device_node* node, 0, int value)
- * enable/disable the mesh (scsi) cell of a mac-io ASIC
- */
-#define PMAC_FTR_MESH_ENABLE		PMAC_FTR_DEF(3)
-
-/* PMAC_FTR_IDE_ENABLE		(struct device_node* node, int busID, int value)
- * enable/disable an IDE port of a mac-io ASIC
- * pass the busID parameter
- */
-#define PMAC_FTR_IDE_ENABLE		PMAC_FTR_DEF(4)
-
-/* PMAC_FTR_IDE_RESET		(struct device_node* node, int busID, int value)
- * assert(1)/release(0) an IDE reset line (mac-io IDE only)
- */
-#define PMAC_FTR_IDE_RESET		PMAC_FTR_DEF(5)
-
-/* PMAC_FTR_BMAC_ENABLE		(struct device_node* node, 0, int value)
- * enable/disable the bmac (ethernet) cell of a mac-io ASIC, also drive
- * it's reset line
- */
-#define PMAC_FTR_BMAC_ENABLE		PMAC_FTR_DEF(6)
-
-/* PMAC_FTR_GMAC_ENABLE		(struct device_node* node, 0, int value)
- * enable/disable the gmac (ethernet) cell of an uninorth ASIC. This
- * control the cell's clock.
- */
-#define PMAC_FTR_GMAC_ENABLE		PMAC_FTR_DEF(7)
-
-/* PMAC_FTR_GMAC_PHY_RESET	(struct device_node* node, 0, 0)
- * Perform a HW reset of the PHY connected to a gmac controller.
- * Pass the gmac device node, not the PHY node.
- */
-#define PMAC_FTR_GMAC_PHY_RESET		PMAC_FTR_DEF(8)
-
-/* PMAC_FTR_SOUND_CHIP_ENABLE	(struct device_node* node, 0, int value)
- * enable/disable the sound chip, whatever it is and provided it can
- * acually be controlled
- */
-#define PMAC_FTR_SOUND_CHIP_ENABLE	PMAC_FTR_DEF(9)
-
-/* -- add various tweaks related to sound routing -- */
-
-/* PMAC_FTR_AIRPORT_ENABLE	(struct device_node* node, 0, int value)
- * enable/disable the airport card
- */
-#define PMAC_FTR_AIRPORT_ENABLE		PMAC_FTR_DEF(10)
-
-/* PMAC_FTR_RESET_CPU		(NULL, int cpu_nr, 0)
- * toggle the reset line of a CPU on an uninorth-based SMP machine
- */
-#define PMAC_FTR_RESET_CPU		PMAC_FTR_DEF(11)
-
-/* PMAC_FTR_USB_ENABLE		(struct device_node* node, 0, int value)
- * enable/disable an USB cell, along with the power of the USB "pad"
- * on keylargo based machines
- */
-#define PMAC_FTR_USB_ENABLE		PMAC_FTR_DEF(12)
-
-/* PMAC_FTR_1394_ENABLE		(struct device_node* node, 0, int value)
- * enable/disable the firewire cell of an uninorth ASIC.
- */
-#define PMAC_FTR_1394_ENABLE		PMAC_FTR_DEF(13)
-
-/* PMAC_FTR_1394_CABLE_POWER	(struct device_node* node, 0, int value)
- * enable/disable the firewire cable power supply of the uninorth
- * firewire cell
- */
-#define PMAC_FTR_1394_CABLE_POWER	PMAC_FTR_DEF(14)
-
-/* PMAC_FTR_SLEEP_STATE		(struct device_node* node, 0, int value)
- * set the sleep state of the motherboard.
- *
- * Pass -1 as value to query for sleep capability
- * Pass 1 to set IOs to sleep
- * Pass 0 to set IOs to wake
- */
-#define PMAC_FTR_SLEEP_STATE		PMAC_FTR_DEF(15)
-
-/* PMAC_FTR_GET_MB_INFO		(NULL, selector, 0)
- *
- * returns some motherboard infos.
- * selector: 0  - model id
- *           1  - model flags (capabilities)
- *           2  - model name (cast to const char *)
- */
-#define PMAC_FTR_GET_MB_INFO		PMAC_FTR_DEF(16)
-#define   PMAC_MB_INFO_MODEL	0
-#define   PMAC_MB_INFO_FLAGS	1
-#define   PMAC_MB_INFO_NAME	2
-
-/* PMAC_FTR_READ_GPIO		(NULL, int index, 0)
- *
- * read a GPIO from a mac-io controller of type KeyLargo or Pangea.
- * the value returned is a byte (positive), or a negative error code
- */
-#define PMAC_FTR_READ_GPIO		PMAC_FTR_DEF(17)
-
-/* PMAC_FTR_WRITE_GPIO		(NULL, int index, int value)
- *
- * write a GPIO of a mac-io controller of type KeyLargo or Pangea.
- */
-#define PMAC_FTR_WRITE_GPIO		PMAC_FTR_DEF(18)
-
-/* PMAC_FTR_ENABLE_MPIC
- *
- * Enable the MPIC cell
- */
-#define PMAC_FTR_ENABLE_MPIC		PMAC_FTR_DEF(19)
-
-/* PMAC_FTR_AACK_DELAY_ENABLE	(NULL, int enable, 0)
- *
- * Enable/disable the AACK delay on the northbridge for systems using DFS
- */
-#define PMAC_FTR_AACK_DELAY_ENABLE     	PMAC_FTR_DEF(20)
-
-/* PMAC_FTR_DEVICE_CAN_WAKE
- *
- * Used by video drivers to inform system that they can actually perform
- * wakeup from sleep
- */
-#define PMAC_FTR_DEVICE_CAN_WAKE	PMAC_FTR_DEF(22)
-
-
-/* Don't use those directly, they are for the sake of pmac_setup.c */
-extern long pmac_do_feature_call(unsigned int selector, ...);
-extern void pmac_feature_init(void);
-
-/* Video suspend tweak */
-extern void pmac_set_early_video_resume(void (*proc)(void *data), void *data);
-extern void pmac_call_early_video_resume(void);
-
-#define PMAC_FTR_DEF(x) ((0x6660000) | (x))
-
-/* The AGP driver registers itself here */
-extern void pmac_register_agp_pm(struct pci_dev *bridge,
-				 int (*suspend)(struct pci_dev *bridge),
-				 int (*resume)(struct pci_dev *bridge));
-
-/* Those are meant to be used by video drivers to deal with AGP
- * suspend resume properly
- */
-extern void pmac_suspend_agp_for_card(struct pci_dev *dev);
-extern void pmac_resume_agp_for_card(struct pci_dev *dev);
-
-/*
- * The part below is for use by macio_asic.c only, do not rely
- * on the data structures or constants below in a normal driver
- *
- */
-
-#define MAX_MACIO_CHIPS		2
-
-enum {
-	macio_unknown = 0,
-	macio_grand_central,
-	macio_ohare,
-	macio_ohareII,
-	macio_heathrow,
-	macio_gatwick,
-	macio_paddington,
-	macio_keylargo,
-	macio_pangea,
-	macio_intrepid,
-	macio_keylargo2,
-	macio_shasta,
-};
-
-struct macio_chip
-{
-	struct device_node	*of_node;
-	int			type;
-	const char		*name;
-	int			rev;
-	volatile u32		__iomem *base;
-	unsigned long		flags;
-
-	/* For use by macio_asic PCI driver */
-	struct macio_bus	lbus;
-};
-
-extern struct macio_chip macio_chips[MAX_MACIO_CHIPS];
-
-#define MACIO_FLAG_SCCA_ON	0x00000001
-#define MACIO_FLAG_SCCB_ON	0x00000002
-#define MACIO_FLAG_SCC_LOCKED	0x00000004
-#define MACIO_FLAG_AIRPORT_ON	0x00000010
-#define MACIO_FLAG_FW_SUPPORTED	0x00000020
-
-extern struct macio_chip* macio_find(struct device_node* child, int type);
-
-#define MACIO_FCR32(macio, r)	((macio)->base + ((r) >> 2))
-#define MACIO_FCR8(macio, r)	(((volatile u8 __iomem *)((macio)->base)) + (r))
-
-#define MACIO_IN32(r)		(in_le32(MACIO_FCR32(macio,r)))
-#define MACIO_OUT32(r,v)	(out_le32(MACIO_FCR32(macio,r), (v)))
-#define MACIO_BIS(r,v)		(MACIO_OUT32((r), MACIO_IN32(r) | (v)))
-#define MACIO_BIC(r,v)		(MACIO_OUT32((r), MACIO_IN32(r) & ~(v)))
-#define MACIO_IN8(r)		(in_8(MACIO_FCR8(macio,r)))
-#define MACIO_OUT8(r,v)		(out_8(MACIO_FCR8(macio,r), (v)))
-
-/*
- * Those are exported by pmac feature for internal use by arch code
- * only like the platform function callbacks, do not use directly in drivers
- */
-extern raw_spinlock_t feature_lock;
-extern struct device_node *uninorth_node;
-extern u32 __iomem *uninorth_base;
-
-/*
- * Uninorth reg. access. Note that Uni-N regs are big endian
- */
-
-#define UN_REG(r)	(uninorth_base + ((r) >> 2))
-#define UN_IN(r)	(in_be32(UN_REG(r)))
-#define UN_OUT(r,v)	(out_be32(UN_REG(r), (v)))
-#define UN_BIS(r,v)	(UN_OUT((r), UN_IN(r) | (v)))
-#define UN_BIC(r,v)	(UN_OUT((r), UN_IN(r) & ~(v)))
-
-/* Uninorth variant:
- *
- * 0 = not uninorth
- * 1 = U1.x or U2.x
- * 3 = U3
- * 4 = U4
- */
-extern int pmac_get_uninorth_variant(void);
-
-#endif /* __ASM_POWERPC_PMAC_FEATURE_H */
-#endif /* __KERNEL__ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/pmac_low_i2c.h b/ANDROID_3.4.5/arch/powerpc/include/asm/pmac_low_i2c.h
deleted file mode 100644
index 01d71826..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/pmac_low_i2c.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/* 
- *  include/asm-ppc/pmac_low_i2c.h
- *
- *  Copyright (C) 2003 Ben. Herrenschmidt (benh@kernel.crashing.org)
- *
- *  This program is free software; you can redistribute it and/or
- *  modify it under the terms of the GNU General Public License
- *  as published by the Free Software Foundation; either version
- *  2 of the License, or (at your option) any later version.
- *
- */
-#ifndef __PMAC_LOW_I2C_H__
-#define __PMAC_LOW_I2C_H__
-#ifdef __KERNEL__
-
-/* i2c mode (based on the platform functions format) */
-enum {
-	pmac_i2c_mode_dumb	= 1,
-	pmac_i2c_mode_std	= 2,
-	pmac_i2c_mode_stdsub	= 3,
-	pmac_i2c_mode_combined	= 4,
-};
-
-/* RW bit in address */
-enum {
-	pmac_i2c_read		= 0x01,
-	pmac_i2c_write		= 0x00
-};
-
-/* i2c bus type */
-enum {
-	pmac_i2c_bus_keywest	= 0,
-	pmac_i2c_bus_pmu	= 1,
-	pmac_i2c_bus_smu	= 2,
-};
-
-/* i2c bus features */
-enum {
-	/* can_largesub : supports >1 byte subaddresses (SMU only) */
-	pmac_i2c_can_largesub	= 0x00000001u,
-
-	/* multibus : device node holds multiple busses, bus number is
-	 * encoded in bits 0xff00 of "reg" of a given device
-	 */
-	pmac_i2c_multibus	= 0x00000002u,
-};
-
-/* i2c busses in the system */
-struct pmac_i2c_bus;
-struct i2c_adapter;
-
-/* Init, called early during boot */
-extern int pmac_i2c_init(void);
-
-/* Lookup an i2c bus for a device-node. The node can be either the bus
- * node itself or a device below it. In the case of a multibus, the bus
- * node itself is the controller node, else, it's a child of the controller
- * node
- */
-extern struct pmac_i2c_bus *pmac_i2c_find_bus(struct device_node *node);
-
-/* Get the address for an i2c device. This strips the bus number if
- * necessary. The 7 bits address is returned 1 bit right shifted so that the
- * direction can be directly ored in
- */
-extern u8 pmac_i2c_get_dev_addr(struct device_node *device);
-
-/* Get infos about a bus */
-extern struct device_node *pmac_i2c_get_controller(struct pmac_i2c_bus *bus);
-extern struct device_node *pmac_i2c_get_bus_node(struct pmac_i2c_bus *bus);
-extern int pmac_i2c_get_type(struct pmac_i2c_bus *bus);
-extern int pmac_i2c_get_flags(struct pmac_i2c_bus *bus);
-extern int pmac_i2c_get_channel(struct pmac_i2c_bus *bus);
-
-/* i2c layer adapter helpers */
-extern struct i2c_adapter *pmac_i2c_get_adapter(struct pmac_i2c_bus *bus);
-extern struct pmac_i2c_bus *pmac_i2c_adapter_to_bus(struct i2c_adapter *adapter);
-
-/* March a device or bus with an i2c adapter structure, to be used by drivers
- * to match device-tree nodes with i2c adapters during adapter discovery
- * callbacks
- */
-extern int pmac_i2c_match_adapter(struct device_node *dev,
-				  struct i2c_adapter *adapter);
-
-
-/* (legacy) Locking functions exposed to i2c-keywest */
-extern int pmac_low_i2c_lock(struct device_node *np);
-extern int pmac_low_i2c_unlock(struct device_node *np);
-
-/* Access functions for platform code */
-extern int pmac_i2c_open(struct pmac_i2c_bus *bus, int polled);
-extern void pmac_i2c_close(struct pmac_i2c_bus *bus);
-extern int pmac_i2c_setmode(struct pmac_i2c_bus *bus, int mode);
-extern int pmac_i2c_xfer(struct pmac_i2c_bus *bus, u8 addrdir, int subsize,
-			 u32 subaddr, u8 *data,  int len);
-
-/* Suspend/resume code called by via-pmu directly for now */
-extern void pmac_pfunc_i2c_suspend(void);
-extern void pmac_pfunc_i2c_resume(void);
-
-#endif /* __KERNEL__ */
-#endif /* __PMAC_LOW_I2C_H__ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/pmac_pfunc.h b/ANDROID_3.4.5/arch/powerpc/include/asm/pmac_pfunc.h
deleted file mode 100644
index 1330d6a5..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/pmac_pfunc.h
+++ /dev/null
@@ -1,252 +0,0 @@
-#ifndef __PMAC_PFUNC_H__
-#define __PMAC_PFUNC_H__
-
-#include <linux/types.h>
-#include <linux/list.h>
-
-/* Flags in command lists */
-#define PMF_FLAGS_ON_INIT		0x80000000u
-#define PMF_FLGAS_ON_TERM		0x40000000u
-#define PMF_FLAGS_ON_SLEEP		0x20000000u
-#define PMF_FLAGS_ON_WAKE		0x10000000u
-#define PMF_FLAGS_ON_DEMAND		0x08000000u
-#define PMF_FLAGS_INT_GEN		0x04000000u
-#define PMF_FLAGS_HIGH_SPEED		0x02000000u
-#define PMF_FLAGS_LOW_SPEED		0x01000000u
-#define PMF_FLAGS_SIDE_EFFECTS		0x00800000u
-
-/*
- * Arguments to a platform function call.
- *
- * NOTE: By convention, pointer arguments point to an u32
- */
-struct pmf_args {
-	union {
-		u32 v;
-		u32 *p;
-	} u[4];
-	unsigned int count;
-};
-
-/*
- * A driver capable of interpreting commands provides a handlers
- * structure filled with whatever handlers are implemented by this
- * driver. Non implemented handlers are left NULL.
- *
- * PMF_STD_ARGS are the same arguments that are passed to the parser
- * and that gets passed back to the various handlers.
- *
- * Interpreting a given function always start with a begin() call which
- * returns an instance data to be passed around subsequent calls, and
- * ends with an end() call. This allows the low level driver to implement
- * locking policy or per-function instance data.
- *
- * For interrupt capable functions, irq_enable() is called when a client
- * registers, and irq_disable() is called when the last client unregisters
- * Note that irq_enable & irq_disable are called within a semaphore held
- * by the core, thus you should not try to register yourself to some other
- * pmf interrupt during those calls.
- */
-
-#define PMF_STD_ARGS	struct pmf_function *func, void *instdata, \
-		        struct pmf_args *args
-
-struct pmf_function;
-
-struct pmf_handlers {
-	void * (*begin)(struct pmf_function *func, struct pmf_args *args);
-	void (*end)(struct pmf_function *func, void *instdata);
-
-	int (*irq_enable)(struct pmf_function *func);
-	int (*irq_disable)(struct pmf_function *func);
-
-	int (*write_gpio)(PMF_STD_ARGS, u8 value, u8 mask);
-	int (*read_gpio)(PMF_STD_ARGS, u8 mask, int rshift, u8 xor);
-
-	int (*write_reg32)(PMF_STD_ARGS, u32 offset, u32 value, u32 mask);
-	int (*read_reg32)(PMF_STD_ARGS, u32 offset);
-	int (*write_reg16)(PMF_STD_ARGS, u32 offset, u16 value, u16 mask);
-	int (*read_reg16)(PMF_STD_ARGS, u32 offset);
-	int (*write_reg8)(PMF_STD_ARGS, u32 offset, u8 value, u8 mask);
-	int (*read_reg8)(PMF_STD_ARGS, u32 offset);
-
-	int (*delay)(PMF_STD_ARGS, u32 duration);
-
-	int (*wait_reg32)(PMF_STD_ARGS, u32 offset, u32 value, u32 mask);
-	int (*wait_reg16)(PMF_STD_ARGS, u32 offset, u16 value, u16 mask);
-	int (*wait_reg8)(PMF_STD_ARGS, u32 offset, u8 value, u8 mask);
-
-	int (*read_i2c)(PMF_STD_ARGS, u32 len);
-	int (*write_i2c)(PMF_STD_ARGS, u32 len, const u8 *data);
-	int (*rmw_i2c)(PMF_STD_ARGS, u32 masklen, u32 valuelen, u32 totallen,
-		       const u8 *maskdata, const u8 *valuedata);
-
-	int (*read_cfg)(PMF_STD_ARGS, u32 offset, u32 len);
-	int (*write_cfg)(PMF_STD_ARGS, u32 offset, u32 len, const u8 *data);
-	int (*rmw_cfg)(PMF_STD_ARGS, u32 offset, u32 masklen, u32 valuelen,
-		       u32 totallen, const u8 *maskdata, const u8 *valuedata);
-
-	int (*read_i2c_sub)(PMF_STD_ARGS, u8 subaddr, u32 len);
-	int (*write_i2c_sub)(PMF_STD_ARGS, u8 subaddr, u32 len, const u8 *data);
-	int (*set_i2c_mode)(PMF_STD_ARGS, int mode);
-	int (*rmw_i2c_sub)(PMF_STD_ARGS, u8 subaddr, u32 masklen, u32 valuelen,
-			   u32 totallen, const u8 *maskdata,
-			   const u8 *valuedata);
-
-	int (*read_reg32_msrx)(PMF_STD_ARGS, u32 offset, u32 mask, u32 shift,
-			       u32 xor);
-	int (*read_reg16_msrx)(PMF_STD_ARGS, u32 offset, u32 mask, u32 shift,
-			       u32 xor);
-	int (*read_reg8_msrx)(PMF_STD_ARGS, u32 offset, u32 mask, u32 shift,
-			      u32 xor);
-
-	int (*write_reg32_slm)(PMF_STD_ARGS, u32 offset, u32 shift, u32 mask);
-	int (*write_reg16_slm)(PMF_STD_ARGS, u32 offset, u32 shift, u32 mask);
-	int (*write_reg8_slm)(PMF_STD_ARGS, u32 offset, u32 shift, u32 mask);
-
-	int (*mask_and_compare)(PMF_STD_ARGS, u32 len, const u8 *maskdata,
-				const u8 *valuedata);
-
-	struct module *owner;
-};
-
-
-/*
- * Drivers who expose platform functions register at init time, this
- * causes the platform functions for that device node to be parsed in
- * advance and associated with the device. The data structures are
- * partially public so a driver can walk the list of platform functions
- * and eventually inspect the flags
- */
-struct pmf_device;
-
-struct pmf_function {
-	/* All functions for a given driver are linked */
-	struct list_head	link;
-
-	/* Function node & driver data */
-	struct device_node	*node;
-	void			*driver_data;
-
-	/* For internal use by core */
-	struct pmf_device	*dev;
-
-	/* The name is the "xxx" in "platform-do-xxx", this is how
-	 * platform functions are identified by this code. Some functions
-	 * only operate for a given target, in which case the phandle is
-	 * here (or 0 if the filter doesn't apply)
-	 */
-	const char		*name;
-	u32			phandle;
-
-	/* The flags for that function. You can have several functions
-	 * with the same name and different flag
-	 */
-	u32			flags;
-
-	/* The actual tokenized function blob */
-	const void		*data;
-	unsigned int		length;
-
-	/* Interrupt clients */
-	struct list_head	irq_clients;
-
-	/* Refcounting */
-	struct kref		ref;
-};
-
-/*
- * For platform functions that are interrupts, one can register
- * irq_client structures. You canNOT use the same structure twice
- * as it contains a link member. Also, the callback is called with
- * a spinlock held, you must not call back into any of the pmf_* functions
- * from within that callback
- */
-struct pmf_irq_client {
-	void			(*handler)(void *data);
-	void			*data;
-	struct module		*owner;
-	struct list_head	link;
-	struct pmf_function	*func;
-};
-
-
-/*
- * Register/Unregister a function-capable driver and its handlers
- */
-extern int pmf_register_driver(struct device_node *np,
-			      struct pmf_handlers *handlers,
-			      void *driverdata);
-
-extern void pmf_unregister_driver(struct device_node *np);
-
-
-/*
- * Register/Unregister interrupt clients
- */
-extern int pmf_register_irq_client(struct device_node *np,
-				   const char *name,
-				   struct pmf_irq_client *client);
-
-extern void pmf_unregister_irq_client(struct pmf_irq_client *client);
-
-/*
- * Called by the handlers when an irq happens
- */
-extern void pmf_do_irq(struct pmf_function *func);
-
-
-/*
- * Low level call to platform functions.
- *
- * The phandle can filter on the target object for functions that have
- * multiple targets, the flags allow you to restrict the call to a given
- * combination of flags.
- *
- * The args array contains as many arguments as is required by the function,
- * this is dependent on the function you are calling, unfortunately Apple
- * mechanism provides no way to encode that so you have to get it right at
- * the call site. Some functions require no args, in which case, you can
- * pass NULL.
- *
- * You can also pass NULL to the name. This will match any function that has
- * the appropriate combination of flags & phandle or you can pass 0 to the
- * phandle to match any
- */
-extern int pmf_do_functions(struct device_node *np, const char *name,
-			    u32 phandle, u32 flags, struct pmf_args *args);
-
-
-
-/*
- * High level call to a platform function.
- *
- * This one looks for the platform-xxx first so you should call it to the
- * actual target if any. It will fallback to platform-do-xxx if it can't
- * find one. It will also exclusively target functions that have
- * the "OnDemand" flag.
- */
-
-extern int pmf_call_function(struct device_node *target, const char *name,
-			     struct pmf_args *args);
-
-
-/*
- * For low latency interrupt usage, you can lookup for on-demand functions
- * using the functions below
- */
-
-extern struct pmf_function *pmf_find_function(struct device_node *target,
-					      const char *name);
-
-extern struct pmf_function * pmf_get_function(struct pmf_function *func);
-extern void pmf_put_function(struct pmf_function *func);
-
-extern int pmf_call_one(struct pmf_function *func, struct pmf_args *args);
-
-
-/* Suspend/resume code called by via-pmu directly for now */
-extern void pmac_pfunc_base_suspend(void);
-extern void pmac_pfunc_base_resume(void);
-
-#endif /* __PMAC_PFUNC_H__ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/pmc.h b/ANDROID_3.4.5/arch/powerpc/include/asm/pmc.h
deleted file mode 100644
index 5a9ede49..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/pmc.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * pmc.h
- * Copyright (C) 2004  David Gibson, IBM Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-#ifndef _POWERPC_PMC_H
-#define _POWERPC_PMC_H
-#ifdef __KERNEL__
-
-#include <asm/ptrace.h>
-
-typedef void (*perf_irq_t)(struct pt_regs *);
-extern perf_irq_t perf_irq;
-
-int reserve_pmc_hardware(perf_irq_t new_perf_irq);
-void release_pmc_hardware(void);
-void ppc_enable_pmcs(void);
-
-#ifdef CONFIG_PPC_BOOK3S_64
-#include <asm/lppaca.h>
-
-static inline void ppc_set_pmu_inuse(int inuse)
-{
-	get_lppaca()->pmcregs_in_use = inuse;
-}
-
-extern void power4_enable_pmcs(void);
-
-#else /* CONFIG_PPC64 */
-
-static inline void ppc_set_pmu_inuse(int inuse) { }
-
-#endif
-
-#endif /* __KERNEL__ */
-#endif /* _POWERPC_PMC_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/pmi.h b/ANDROID_3.4.5/arch/powerpc/include/asm/pmi.h
deleted file mode 100644
index b4e91fbf..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/pmi.h
+++ /dev/null
@@ -1,66 +0,0 @@
-#ifndef _POWERPC_PMI_H
-#define _POWERPC_PMI_H
-
-/*
- * Definitions for talking with PMI device on PowerPC
- *
- * PMI (Platform Management Interrupt) is a way to communicate
- * with the BMC (Baseboard Management Controller) via interrupts.
- * Unlike IPMI it is bidirectional and has a low latency.
- *
- * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
- *
- * Author: Christian Krafft <krafft@de.ibm.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifdef __KERNEL__
-
-#define PMI_TYPE_FREQ_CHANGE	0x01
-#define PMI_TYPE_POWER_BUTTON	0x02
-#define PMI_READ_TYPE		0
-#define PMI_READ_DATA0		1
-#define PMI_READ_DATA1		2
-#define PMI_READ_DATA2		3
-#define PMI_WRITE_TYPE		4
-#define PMI_WRITE_DATA0		5
-#define PMI_WRITE_DATA1		6
-#define PMI_WRITE_DATA2		7
-
-#define PMI_ACK			0x80
-
-#define PMI_TIMEOUT		100
-
-typedef struct {
-	u8	type;
-	u8	data0;
-	u8	data1;
-	u8	data2;
-} pmi_message_t;
-
-struct pmi_handler {
-	struct list_head node;
-	u8 type;
-	void (*handle_pmi_message) (pmi_message_t);
-};
-
-int pmi_register_handler(struct pmi_handler *);
-void pmi_unregister_handler(struct pmi_handler *);
-
-int pmi_send_message(pmi_message_t);
-
-#endif /* __KERNEL__ */
-#endif /* _POWERPC_PMI_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/poll.h b/ANDROID_3.4.5/arch/powerpc/include/asm/poll.h
deleted file mode 100644
index c98509d3..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/poll.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/poll.h>
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/posix_types.h b/ANDROID_3.4.5/arch/powerpc/include/asm/posix_types.h
deleted file mode 100644
index f1393252..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/posix_types.h
+++ /dev/null
@@ -1,28 +0,0 @@
-#ifndef _ASM_POWERPC_POSIX_TYPES_H
-#define _ASM_POWERPC_POSIX_TYPES_H
-
-/*
- * This file is generally used by user-level software, so you need to
- * be a little careful about namespace pollution etc.  Also, we cannot
- * assume GCC is being used.
- */
-
-#ifdef __powerpc64__
-typedef unsigned long	__kernel_old_dev_t;
-#define __kernel_old_dev_t __kernel_old_dev_t
-#else
-typedef unsigned int	__kernel_size_t;
-typedef int		__kernel_ssize_t;
-typedef long		__kernel_ptrdiff_t;
-#define __kernel_size_t __kernel_size_t
-
-typedef unsigned short	__kernel_nlink_t;
-#define __kernel_nlink_t __kernel_nlink_t
-
-typedef short		__kernel_ipc_pid_t;
-#define __kernel_ipc_pid_t __kernel_ipc_pid_t
-#endif
-
-#include <asm-generic/posix_types.h>
-
-#endif /* _ASM_POWERPC_POSIX_TYPES_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/ppc-opcode.h b/ANDROID_3.4.5/arch/powerpc/include/asm/ppc-opcode.h
deleted file mode 100644
index d81f9943..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/ppc-opcode.h
+++ /dev/null
@@ -1,206 +0,0 @@
-/*
- * Copyright 2009 Freescale Semicondutor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- *
- * provides masks and opcode images for use by code generation, emulation
- * and for instructions that older assemblers might not know about
- */
-#ifndef _ASM_POWERPC_PPC_OPCODE_H
-#define _ASM_POWERPC_PPC_OPCODE_H
-
-#include <linux/stringify.h>
-#include <asm/asm-compat.h>
-
-/* sorted alphabetically */
-#define PPC_INST_DCBA			0x7c0005ec
-#define PPC_INST_DCBA_MASK		0xfc0007fe
-#define PPC_INST_DCBAL			0x7c2005ec
-#define PPC_INST_DCBZL			0x7c2007ec
-#define PPC_INST_ISEL			0x7c00001e
-#define PPC_INST_ISEL_MASK		0xfc00003e
-#define PPC_INST_LDARX			0x7c0000a8
-#define PPC_INST_LSWI			0x7c0004aa
-#define PPC_INST_LSWX			0x7c00042a
-#define PPC_INST_LWARX			0x7c000028
-#define PPC_INST_LWSYNC			0x7c2004ac
-#define PPC_INST_LXVD2X			0x7c000698
-#define PPC_INST_MCRXR			0x7c000400
-#define PPC_INST_MCRXR_MASK		0xfc0007fe
-#define PPC_INST_MFSPR_PVR		0x7c1f42a6
-#define PPC_INST_MFSPR_PVR_MASK		0xfc1fffff
-#define PPC_INST_MSGSND			0x7c00019c
-#define PPC_INST_NOP			0x60000000
-#define PPC_INST_POPCNTB		0x7c0000f4
-#define PPC_INST_POPCNTB_MASK		0xfc0007fe
-#define PPC_INST_POPCNTD		0x7c0003f4
-#define PPC_INST_POPCNTW		0x7c0002f4
-#define PPC_INST_RFCI			0x4c000066
-#define PPC_INST_RFDI			0x4c00004e
-#define PPC_INST_RFMCI			0x4c00004c
-#define PPC_INST_MFSPR_DSCR		0x7c1102a6
-#define PPC_INST_MFSPR_DSCR_MASK	0xfc1fffff
-#define PPC_INST_MTSPR_DSCR		0x7c1103a6
-#define PPC_INST_MTSPR_DSCR_MASK	0xfc1fffff
-#define PPC_INST_SLBFEE			0x7c0007a7
-
-#define PPC_INST_STRING			0x7c00042a
-#define PPC_INST_STRING_MASK		0xfc0007fe
-#define PPC_INST_STRING_GEN_MASK	0xfc00067e
-
-#define PPC_INST_STSWI			0x7c0005aa
-#define PPC_INST_STSWX			0x7c00052a
-#define PPC_INST_STXVD2X		0x7c000798
-#define PPC_INST_TLBIE			0x7c000264
-#define PPC_INST_TLBILX			0x7c000024
-#define PPC_INST_WAIT			0x7c00007c
-#define PPC_INST_TLBIVAX		0x7c000624
-#define PPC_INST_TLBSRX_DOT		0x7c0006a5
-#define PPC_INST_XXLOR			0xf0000510
-
-#define PPC_INST_NAP			0x4c000364
-#define PPC_INST_SLEEP			0x4c0003a4
-
-/* A2 specific instructions */
-#define PPC_INST_ERATWE			0x7c0001a6
-#define PPC_INST_ERATRE			0x7c000166
-#define PPC_INST_ERATILX		0x7c000066
-#define PPC_INST_ERATIVAX		0x7c000666
-#define PPC_INST_ERATSX			0x7c000126
-#define PPC_INST_ERATSX_DOT		0x7c000127
-
-/* Misc instructions for BPF compiler */
-#define PPC_INST_LD			0xe8000000
-#define PPC_INST_LHZ			0xa0000000
-#define PPC_INST_LWZ			0x80000000
-#define PPC_INST_STD			0xf8000000
-#define PPC_INST_STDU			0xf8000001
-#define PPC_INST_MFLR			0x7c0802a6
-#define PPC_INST_MTLR			0x7c0803a6
-#define PPC_INST_CMPWI			0x2c000000
-#define PPC_INST_CMPDI			0x2c200000
-#define PPC_INST_CMPLW			0x7c000040
-#define PPC_INST_CMPLWI			0x28000000
-#define PPC_INST_ADDI			0x38000000
-#define PPC_INST_ADDIS			0x3c000000
-#define PPC_INST_ADD			0x7c000214
-#define PPC_INST_SUB			0x7c000050
-#define PPC_INST_BLR			0x4e800020
-#define PPC_INST_BLRL			0x4e800021
-#define PPC_INST_MULLW			0x7c0001d6
-#define PPC_INST_MULHWU			0x7c000016
-#define PPC_INST_MULLI			0x1c000000
-#define PPC_INST_DIVWU			0x7c0003d6
-#define PPC_INST_RLWINM			0x54000000
-#define PPC_INST_RLDICR			0x78000004
-#define PPC_INST_SLW			0x7c000030
-#define PPC_INST_SRW			0x7c000430
-#define PPC_INST_AND			0x7c000038
-#define PPC_INST_ANDDOT			0x7c000039
-#define PPC_INST_OR			0x7c000378
-#define PPC_INST_ANDI			0x70000000
-#define PPC_INST_ORI			0x60000000
-#define PPC_INST_ORIS			0x64000000
-#define PPC_INST_NEG			0x7c0000d0
-#define PPC_INST_BRANCH			0x48000000
-#define PPC_INST_BRANCH_COND		0x40800000
-
-/* macros to insert fields into opcodes */
-#define __PPC_RA(a)	(((a) & 0x1f) << 16)
-#define __PPC_RB(b)	(((b) & 0x1f) << 11)
-#define __PPC_RS(s)	(((s) & 0x1f) << 21)
-#define __PPC_RT(s)	__PPC_RS(s)
-#define __PPC_XA(a)	((((a) & 0x1f) << 16) | (((a) & 0x20) >> 3))
-#define __PPC_XB(b)	((((b) & 0x1f) << 11) | (((b) & 0x20) >> 4))
-#define __PPC_XS(s)	((((s) & 0x1f) << 21) | (((s) & 0x20) >> 5))
-#define __PPC_XT(s)	__PPC_XS(s)
-#define __PPC_T_TLB(t)	(((t) & 0x3) << 21)
-#define __PPC_WC(w)	(((w) & 0x3) << 21)
-#define __PPC_WS(w)	(((w) & 0x1f) << 11)
-#define __PPC_SH(s)	__PPC_WS(s)
-#define __PPC_MB(s)	(((s) & 0x1f) << 6)
-#define __PPC_ME(s)	(((s) & 0x1f) << 1)
-#define __PPC_BI(s)	(((s) & 0x1f) << 16)
-
-/*
- * Only use the larx hint bit on 64bit CPUs. e500v1/v2 based CPUs will treat a
- * larx with EH set as an illegal instruction.
- */
-#ifdef CONFIG_PPC64
-#define __PPC_EH(eh)	(((eh) & 0x1) << 0)
-#else
-#define __PPC_EH(eh)	0
-#endif
-
-/* Deal with instructions that older assemblers aren't aware of */
-#define	PPC_DCBAL(a, b)		stringify_in_c(.long PPC_INST_DCBAL | \
-					__PPC_RA(a) | __PPC_RB(b))
-#define	PPC_DCBZL(a, b)		stringify_in_c(.long PPC_INST_DCBZL | \
-					__PPC_RA(a) | __PPC_RB(b))
-#define PPC_LDARX(t, a, b, eh)	stringify_in_c(.long PPC_INST_LDARX | \
-					__PPC_RT(t) | __PPC_RA(a) | \
-					__PPC_RB(b) | __PPC_EH(eh))
-#define PPC_LWARX(t, a, b, eh)	stringify_in_c(.long PPC_INST_LWARX | \
-					__PPC_RT(t) | __PPC_RA(a) | \
-					__PPC_RB(b) | __PPC_EH(eh))
-#define PPC_MSGSND(b)		stringify_in_c(.long PPC_INST_MSGSND | \
-					__PPC_RB(b))
-#define PPC_POPCNTB(a, s)	stringify_in_c(.long PPC_INST_POPCNTB | \
-					__PPC_RA(a) | __PPC_RS(s))
-#define PPC_POPCNTD(a, s)	stringify_in_c(.long PPC_INST_POPCNTD | \
-					__PPC_RA(a) | __PPC_RS(s))
-#define PPC_POPCNTW(a, s)	stringify_in_c(.long PPC_INST_POPCNTW | \
-					__PPC_RA(a) | __PPC_RS(s))
-#define PPC_RFCI		stringify_in_c(.long PPC_INST_RFCI)
-#define PPC_RFDI		stringify_in_c(.long PPC_INST_RFDI)
-#define PPC_RFMCI		stringify_in_c(.long PPC_INST_RFMCI)
-#define PPC_TLBILX(t, a, b)	stringify_in_c(.long PPC_INST_TLBILX | \
-					__PPC_T_TLB(t) | __PPC_RA(a) | __PPC_RB(b))
-#define PPC_TLBILX_ALL(a, b)	PPC_TLBILX(0, a, b)
-#define PPC_TLBILX_PID(a, b)	PPC_TLBILX(1, a, b)
-#define PPC_TLBILX_VA(a, b)	PPC_TLBILX(3, a, b)
-#define PPC_WAIT(w)		stringify_in_c(.long PPC_INST_WAIT | \
-					__PPC_WC(w))
-#define PPC_TLBIE(lp,a) 	stringify_in_c(.long PPC_INST_TLBIE | \
-					       __PPC_RB(a) | __PPC_RS(lp))
-#define PPC_TLBSRX_DOT(a,b)	stringify_in_c(.long PPC_INST_TLBSRX_DOT | \
-					__PPC_RA(a) | __PPC_RB(b))
-#define PPC_TLBIVAX(a,b)	stringify_in_c(.long PPC_INST_TLBIVAX | \
-					__PPC_RA(a) | __PPC_RB(b))
-
-#define PPC_ERATWE(s, a, w)	stringify_in_c(.long PPC_INST_ERATWE | \
-					__PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
-#define PPC_ERATRE(s, a, w)	stringify_in_c(.long PPC_INST_ERATRE | \
-					__PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
-#define PPC_ERATILX(t, a, b)	stringify_in_c(.long PPC_INST_ERATILX | \
-					__PPC_T_TLB(t) | __PPC_RA(a) | \
-					__PPC_RB(b))
-#define PPC_ERATIVAX(s, a, b)	stringify_in_c(.long PPC_INST_ERATIVAX | \
-					__PPC_RS(s) | __PPC_RA(a) | __PPC_RB(b))
-#define PPC_ERATSX(t, a, w)	stringify_in_c(.long PPC_INST_ERATSX | \
-					__PPC_RS(t) | __PPC_RA(a) | __PPC_RB(b))
-#define PPC_ERATSX_DOT(t, a, w)	stringify_in_c(.long PPC_INST_ERATSX_DOT | \
-					__PPC_RS(t) | __PPC_RA(a) | __PPC_RB(b))
-#define PPC_SLBFEE_DOT(t, b)	stringify_in_c(.long PPC_INST_SLBFEE | \
-					__PPC_RT(t) | __PPC_RB(b))
-
-/*
- * Define what the VSX XX1 form instructions will look like, then add
- * the 128 bit load store instructions based on that.
- */
-#define VSX_XX1(s, a, b)	(__PPC_XS(s) | __PPC_RA(a) | __PPC_RB(b))
-#define VSX_XX3(t, a, b)	(__PPC_XT(t) | __PPC_XA(a) | __PPC_XB(b))
-#define STXVD2X(s, a, b)	stringify_in_c(.long PPC_INST_STXVD2X | \
-					       VSX_XX1((s), (a), (b)))
-#define LXVD2X(s, a, b)		stringify_in_c(.long PPC_INST_LXVD2X | \
-					       VSX_XX1((s), (a), (b)))
-#define XXLOR(t, a, b)		stringify_in_c(.long PPC_INST_XXLOR | \
-					       VSX_XX3((t), (a), (b)))
-
-#define PPC_NAP			stringify_in_c(.long PPC_INST_NAP)
-#define PPC_SLEEP		stringify_in_c(.long PPC_INST_SLEEP)
-
-#endif /* _ASM_POWERPC_PPC_OPCODE_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/ppc-pci.h b/ANDROID_3.4.5/arch/powerpc/include/asm/ppc-pci.h
deleted file mode 100644
index 80fa704d..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/ppc-pci.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * c 2001 PPC 64 Team, IBM Corp
- *
- *      This program is free software; you can redistribute it and/or
- *      modify it under the terms of the GNU General Public License
- *      as published by the Free Software Foundation; either version
- *      2 of the License, or (at your option) any later version.
- */
-#ifndef _ASM_POWERPC_PPC_PCI_H
-#define _ASM_POWERPC_PPC_PCI_H
-#ifdef __KERNEL__
-
-#ifdef CONFIG_PCI
-
-#include <linux/pci.h>
-#include <asm/pci-bridge.h>
-
-extern unsigned long isa_io_base;
-
-extern void pci_setup_phb_io(struct pci_controller *hose, int primary);
-extern void pci_setup_phb_io_dynamic(struct pci_controller *hose, int primary);
-
-
-extern struct list_head hose_list;
-
-extern void find_and_init_phbs(void);
-
-extern struct pci_dev *isa_bridge_pcidev;	/* may be NULL if no ISA bus */
-
-/** Bus Unit ID macros; get low and hi 32-bits of the 64-bit BUID */
-#define BUID_HI(buid) upper_32_bits(buid)
-#define BUID_LO(buid) lower_32_bits(buid)
-
-/* PCI device_node operations */
-struct device_node;
-typedef void *(*traverse_func)(struct device_node *me, void *data);
-void *traverse_pci_devices(struct device_node *start, traverse_func pre,
-		void *data);
-
-extern void pci_devs_phb_init(void);
-extern void pci_devs_phb_init_dynamic(struct pci_controller *phb);
-
-/* From rtas_pci.h */
-extern void init_pci_config_tokens (void);
-extern unsigned long get_phb_buid (struct device_node *);
-extern int rtas_setup_phb(struct pci_controller *phb);
-
-#ifdef CONFIG_EEH
-
-void pci_addr_cache_build(void);
-void pci_addr_cache_insert_device(struct pci_dev *dev);
-void pci_addr_cache_remove_device(struct pci_dev *dev);
-struct pci_dev *pci_addr_cache_get_device(unsigned long addr);
-void eeh_slot_error_detail(struct eeh_dev *edev, int severity);
-int eeh_pci_enable(struct eeh_dev *edev, int function);
-int eeh_reset_pe(struct eeh_dev *);
-void eeh_restore_bars(struct eeh_dev *);
-int rtas_write_config(struct pci_dn *, int where, int size, u32 val);
-int rtas_read_config(struct pci_dn *, int where, int size, u32 *val);
-void eeh_mark_slot(struct device_node *dn, int mode_flag);
-void eeh_clear_slot(struct device_node *dn, int mode_flag);
-struct device_node *eeh_find_device_pe(struct device_node *dn);
-
-void eeh_sysfs_add_device(struct pci_dev *pdev);
-void eeh_sysfs_remove_device(struct pci_dev *pdev);
-
-static inline const char *eeh_pci_name(struct pci_dev *pdev) 
-{ 
-	return pdev ? pci_name(pdev) : "<null>";
-} 
-
-static inline const char *eeh_driver_name(struct pci_dev *pdev)
-{
-	return (pdev && pdev->driver) ? pdev->driver->name : "<null>";
-}
-
-#endif /* CONFIG_EEH */
-
-#else /* CONFIG_PCI */
-static inline void find_and_init_phbs(void) { }
-static inline void init_pci_config_tokens(void) { }
-#endif /* !CONFIG_PCI */
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_PPC_PCI_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/ppc4xx.h b/ANDROID_3.4.5/arch/powerpc/include/asm/ppc4xx.h
deleted file mode 100644
index 033039a8..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/ppc4xx.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * PPC4xx Prototypes and definitions
- *
- * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
- *
- * This is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-
-#ifndef __ASM_POWERPC_PPC4xx_H__
-#define __ASM_POWERPC_PPC4xx_H__
-
-extern void ppc4xx_reset_system(char *cmd);
-
-#endif /* __ASM_POWERPC_PPC4xx_H__ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/ppc_asm.h b/ANDROID_3.4.5/arch/powerpc/include/asm/ppc_asm.h
deleted file mode 100644
index 50f73aa2..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/ppc_asm.h
+++ /dev/null
@@ -1,701 +0,0 @@
-/*
- * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
- */
-#ifndef _ASM_POWERPC_PPC_ASM_H
-#define _ASM_POWERPC_PPC_ASM_H
-
-#include <linux/init.h>
-#include <linux/stringify.h>
-#include <asm/asm-compat.h>
-#include <asm/processor.h>
-#include <asm/ppc-opcode.h>
-#include <asm/firmware.h>
-
-#ifndef __ASSEMBLY__
-#error __FILE__ should only be used in assembler files
-#else
-
-#define SZL			(BITS_PER_LONG/8)
-
-/*
- * Stuff for accurate CPU time accounting.
- * These macros handle transitions between user and system state
- * in exception entry and exit and accumulate time to the
- * user_time and system_time fields in the paca.
- */
-
-#ifndef CONFIG_VIRT_CPU_ACCOUNTING
-#define ACCOUNT_CPU_USER_ENTRY(ra, rb)
-#define ACCOUNT_CPU_USER_EXIT(ra, rb)
-#define ACCOUNT_STOLEN_TIME
-#else
-#define ACCOUNT_CPU_USER_ENTRY(ra, rb)					\
-	beq	2f;			/* if from kernel mode */	\
-	MFTB(ra);			/* get timebase */		\
-	ld	rb,PACA_STARTTIME_USER(r13);				\
-	std	ra,PACA_STARTTIME(r13);					\
-	subf	rb,rb,ra;		/* subtract start value */	\
-	ld	ra,PACA_USER_TIME(r13);					\
-	add	ra,ra,rb;		/* add on to user time */	\
-	std	ra,PACA_USER_TIME(r13);					\
-2:
-
-#define ACCOUNT_CPU_USER_EXIT(ra, rb)					\
-	MFTB(ra);			/* get timebase */		\
-	ld	rb,PACA_STARTTIME(r13);					\
-	std	ra,PACA_STARTTIME_USER(r13);				\
-	subf	rb,rb,ra;		/* subtract start value */	\
-	ld	ra,PACA_SYSTEM_TIME(r13);				\
-	add	ra,ra,rb;		/* add on to system time */	\
-	std	ra,PACA_SYSTEM_TIME(r13)
-
-#ifdef CONFIG_PPC_SPLPAR
-#define ACCOUNT_STOLEN_TIME						\
-BEGIN_FW_FTR_SECTION;							\
-	beq	33f;							\
-	/* from user - see if there are any DTL entries to process */	\
-	ld	r10,PACALPPACAPTR(r13);	/* get ptr to VPA */		\
-	ld	r11,PACA_DTL_RIDX(r13);	/* get log read index */	\
-	ld	r10,LPPACA_DTLIDX(r10);	/* get log write index */	\
-	cmpd	cr1,r11,r10;						\
-	beq+	cr1,33f;						\
-	bl	.accumulate_stolen_time;				\
-	ld	r12,_MSR(r1);						\
-	andi.	r10,r12,MSR_PR;		/* Restore cr0 (coming from user) */ \
-33:									\
-END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
-
-#else  /* CONFIG_PPC_SPLPAR */
-#define ACCOUNT_STOLEN_TIME
-
-#endif /* CONFIG_PPC_SPLPAR */
-
-#endif /* CONFIG_VIRT_CPU_ACCOUNTING */
-
-/*
- * Macros for storing registers into and loading registers from
- * exception frames.
- */
-#ifdef __powerpc64__
-#define SAVE_GPR(n, base)	std	n,GPR0+8*(n)(base)
-#define REST_GPR(n, base)	ld	n,GPR0+8*(n)(base)
-#define SAVE_NVGPRS(base)	SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
-#define REST_NVGPRS(base)	REST_8GPRS(14, base); REST_10GPRS(22, base)
-#else
-#define SAVE_GPR(n, base)	stw	n,GPR0+4*(n)(base)
-#define REST_GPR(n, base)	lwz	n,GPR0+4*(n)(base)
-#define SAVE_NVGPRS(base)	SAVE_GPR(13, base); SAVE_8GPRS(14, base); \
-				SAVE_10GPRS(22, base)
-#define REST_NVGPRS(base)	REST_GPR(13, base); REST_8GPRS(14, base); \
-				REST_10GPRS(22, base)
-#endif
-
-#define SAVE_2GPRS(n, base)	SAVE_GPR(n, base); SAVE_GPR(n+1, base)
-#define SAVE_4GPRS(n, base)	SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
-#define SAVE_8GPRS(n, base)	SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
-#define SAVE_10GPRS(n, base)	SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
-#define REST_2GPRS(n, base)	REST_GPR(n, base); REST_GPR(n+1, base)
-#define REST_4GPRS(n, base)	REST_2GPRS(n, base); REST_2GPRS(n+2, base)
-#define REST_8GPRS(n, base)	REST_4GPRS(n, base); REST_4GPRS(n+4, base)
-#define REST_10GPRS(n, base)	REST_8GPRS(n, base); REST_2GPRS(n+8, base)
-
-#define SAVE_FPR(n, base)	stfd	n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base)
-#define SAVE_2FPRS(n, base)	SAVE_FPR(n, base); SAVE_FPR(n+1, base)
-#define SAVE_4FPRS(n, base)	SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
-#define SAVE_8FPRS(n, base)	SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
-#define SAVE_16FPRS(n, base)	SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
-#define SAVE_32FPRS(n, base)	SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
-#define REST_FPR(n, base)	lfd	n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base)
-#define REST_2FPRS(n, base)	REST_FPR(n, base); REST_FPR(n+1, base)
-#define REST_4FPRS(n, base)	REST_2FPRS(n, base); REST_2FPRS(n+2, base)
-#define REST_8FPRS(n, base)	REST_4FPRS(n, base); REST_4FPRS(n+4, base)
-#define REST_16FPRS(n, base)	REST_8FPRS(n, base); REST_8FPRS(n+8, base)
-#define REST_32FPRS(n, base)	REST_16FPRS(n, base); REST_16FPRS(n+16, base)
-
-#define SAVE_VR(n,b,base)	li b,THREAD_VR0+(16*(n));  stvx n,base,b
-#define SAVE_2VRS(n,b,base)	SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
-#define SAVE_4VRS(n,b,base)	SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
-#define SAVE_8VRS(n,b,base)	SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
-#define SAVE_16VRS(n,b,base)	SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
-#define SAVE_32VRS(n,b,base)	SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
-#define REST_VR(n,b,base)	li b,THREAD_VR0+(16*(n)); lvx n,base,b
-#define REST_2VRS(n,b,base)	REST_VR(n,b,base); REST_VR(n+1,b,base)
-#define REST_4VRS(n,b,base)	REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
-#define REST_8VRS(n,b,base)	REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
-#define REST_16VRS(n,b,base)	REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
-#define REST_32VRS(n,b,base)	REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
-
-/* Save the lower 32 VSRs in the thread VSR region */
-#define SAVE_VSR(n,b,base)	li b,THREAD_VSR0+(16*(n));  STXVD2X(n,base,b)
-#define SAVE_2VSRS(n,b,base)	SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base)
-#define SAVE_4VSRS(n,b,base)	SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base)
-#define SAVE_8VSRS(n,b,base)	SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base)
-#define SAVE_16VSRS(n,b,base)	SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base)
-#define SAVE_32VSRS(n,b,base)	SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base)
-#define REST_VSR(n,b,base)	li b,THREAD_VSR0+(16*(n)); LXVD2X(n,base,b)
-#define REST_2VSRS(n,b,base)	REST_VSR(n,b,base); REST_VSR(n+1,b,base)
-#define REST_4VSRS(n,b,base)	REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base)
-#define REST_8VSRS(n,b,base)	REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base)
-#define REST_16VSRS(n,b,base)	REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base)
-#define REST_32VSRS(n,b,base)	REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base)
-/* Save the upper 32 VSRs (32-63) in the thread VSX region (0-31) */
-#define SAVE_VSRU(n,b,base)	li b,THREAD_VR0+(16*(n));  STXVD2X(n+32,base,b)
-#define SAVE_2VSRSU(n,b,base)	SAVE_VSRU(n,b,base); SAVE_VSRU(n+1,b,base)
-#define SAVE_4VSRSU(n,b,base)	SAVE_2VSRSU(n,b,base); SAVE_2VSRSU(n+2,b,base)
-#define SAVE_8VSRSU(n,b,base)	SAVE_4VSRSU(n,b,base); SAVE_4VSRSU(n+4,b,base)
-#define SAVE_16VSRSU(n,b,base)	SAVE_8VSRSU(n,b,base); SAVE_8VSRSU(n+8,b,base)
-#define SAVE_32VSRSU(n,b,base)	SAVE_16VSRSU(n,b,base); SAVE_16VSRSU(n+16,b,base)
-#define REST_VSRU(n,b,base)	li b,THREAD_VR0+(16*(n)); LXVD2X(n+32,base,b)
-#define REST_2VSRSU(n,b,base)	REST_VSRU(n,b,base); REST_VSRU(n+1,b,base)
-#define REST_4VSRSU(n,b,base)	REST_2VSRSU(n,b,base); REST_2VSRSU(n+2,b,base)
-#define REST_8VSRSU(n,b,base)	REST_4VSRSU(n,b,base); REST_4VSRSU(n+4,b,base)
-#define REST_16VSRSU(n,b,base)	REST_8VSRSU(n,b,base); REST_8VSRSU(n+8,b,base)
-#define REST_32VSRSU(n,b,base)	REST_16VSRSU(n,b,base); REST_16VSRSU(n+16,b,base)
-
-/*
- * b = base register for addressing, o = base offset from register of 1st EVR
- * n = first EVR, s = scratch
- */
-#define SAVE_EVR(n,s,b,o)	evmergehi s,s,n; stw s,o+4*(n)(b)
-#define SAVE_2EVRS(n,s,b,o)	SAVE_EVR(n,s,b,o); SAVE_EVR(n+1,s,b,o)
-#define SAVE_4EVRS(n,s,b,o)	SAVE_2EVRS(n,s,b,o); SAVE_2EVRS(n+2,s,b,o)
-#define SAVE_8EVRS(n,s,b,o)	SAVE_4EVRS(n,s,b,o); SAVE_4EVRS(n+4,s,b,o)
-#define SAVE_16EVRS(n,s,b,o)	SAVE_8EVRS(n,s,b,o); SAVE_8EVRS(n+8,s,b,o)
-#define SAVE_32EVRS(n,s,b,o)	SAVE_16EVRS(n,s,b,o); SAVE_16EVRS(n+16,s,b,o)
-#define REST_EVR(n,s,b,o)	lwz s,o+4*(n)(b); evmergelo n,s,n
-#define REST_2EVRS(n,s,b,o)	REST_EVR(n,s,b,o); REST_EVR(n+1,s,b,o)
-#define REST_4EVRS(n,s,b,o)	REST_2EVRS(n,s,b,o); REST_2EVRS(n+2,s,b,o)
-#define REST_8EVRS(n,s,b,o)	REST_4EVRS(n,s,b,o); REST_4EVRS(n+4,s,b,o)
-#define REST_16EVRS(n,s,b,o)	REST_8EVRS(n,s,b,o); REST_8EVRS(n+8,s,b,o)
-#define REST_32EVRS(n,s,b,o)	REST_16EVRS(n,s,b,o); REST_16EVRS(n+16,s,b,o)
-
-/* Macros to adjust thread priority for hardware multithreading */
-#define HMT_VERY_LOW	or	31,31,31	# very low priority
-#define HMT_LOW		or	1,1,1
-#define HMT_MEDIUM_LOW  or	6,6,6		# medium low priority
-#define HMT_MEDIUM	or	2,2,2
-#define HMT_MEDIUM_HIGH or	5,5,5		# medium high priority
-#define HMT_HIGH	or	3,3,3
-#define HMT_EXTRA_HIGH	or	7,7,7		# power7 only
-
-#ifdef __KERNEL__
-#ifdef CONFIG_PPC64
-
-#define XGLUE(a,b) a##b
-#define GLUE(a,b) XGLUE(a,b)
-
-#define _GLOBAL(name) \
-	.section ".text"; \
-	.align 2 ; \
-	.globl name; \
-	.globl GLUE(.,name); \
-	.section ".opd","aw"; \
-name: \
-	.quad GLUE(.,name); \
-	.quad .TOC.@tocbase; \
-	.quad 0; \
-	.previous; \
-	.type GLUE(.,name),@function; \
-GLUE(.,name):
-
-#define _INIT_GLOBAL(name) \
-	__REF; \
-	.align 2 ; \
-	.globl name; \
-	.globl GLUE(.,name); \
-	.section ".opd","aw"; \
-name: \
-	.quad GLUE(.,name); \
-	.quad .TOC.@tocbase; \
-	.quad 0; \
-	.previous; \
-	.type GLUE(.,name),@function; \
-GLUE(.,name):
-
-#define _KPROBE(name) \
-	.section ".kprobes.text","a"; \
-	.align 2 ; \
-	.globl name; \
-	.globl GLUE(.,name); \
-	.section ".opd","aw"; \
-name: \
-	.quad GLUE(.,name); \
-	.quad .TOC.@tocbase; \
-	.quad 0; \
-	.previous; \
-	.type GLUE(.,name),@function; \
-GLUE(.,name):
-
-#define _STATIC(name) \
-	.section ".text"; \
-	.align 2 ; \
-	.section ".opd","aw"; \
-name: \
-	.quad GLUE(.,name); \
-	.quad .TOC.@tocbase; \
-	.quad 0; \
-	.previous; \
-	.type GLUE(.,name),@function; \
-GLUE(.,name):
-
-#define _INIT_STATIC(name) \
-	__REF; \
-	.align 2 ; \
-	.section ".opd","aw"; \
-name: \
-	.quad GLUE(.,name); \
-	.quad .TOC.@tocbase; \
-	.quad 0; \
-	.previous; \
-	.type GLUE(.,name),@function; \
-GLUE(.,name):
-
-#else /* 32-bit */
-
-#define _ENTRY(n)	\
-	.globl n;	\
-n:
-
-#define _GLOBAL(n)	\
-	.text;		\
-	.stabs __stringify(n:F-1),N_FUN,0,0,n;\
-	.globl n;	\
-n:
-
-#define _KPROBE(n)	\
-	.section ".kprobes.text","a";	\
-	.globl	n;	\
-n:
-
-#endif
-
-/* 
- * LOAD_REG_IMMEDIATE(rn, expr)
- *   Loads the value of the constant expression 'expr' into register 'rn'
- *   using immediate instructions only.  Use this when it's important not
- *   to reference other data (i.e. on ppc64 when the TOC pointer is not
- *   valid) and when 'expr' is a constant or absolute address.
- *
- * LOAD_REG_ADDR(rn, name)
- *   Loads the address of label 'name' into register 'rn'.  Use this when
- *   you don't particularly need immediate instructions only, but you need
- *   the whole address in one register (e.g. it's a structure address and
- *   you want to access various offsets within it).  On ppc32 this is
- *   identical to LOAD_REG_IMMEDIATE.
- *
- * LOAD_REG_ADDRBASE(rn, name)
- * ADDROFF(name)
- *   LOAD_REG_ADDRBASE loads part of the address of label 'name' into
- *   register 'rn'.  ADDROFF(name) returns the remainder of the address as
- *   a constant expression.  ADDROFF(name) is a signed expression < 16 bits
- *   in size, so is suitable for use directly as an offset in load and store
- *   instructions.  Use this when loading/storing a single word or less as:
- *      LOAD_REG_ADDRBASE(rX, name)
- *      ld	rY,ADDROFF(name)(rX)
- */
-#ifdef __powerpc64__
-#define LOAD_REG_IMMEDIATE(reg,expr)		\
-	lis     (reg),(expr)@highest;		\
-	ori     (reg),(reg),(expr)@higher;	\
-	rldicr  (reg),(reg),32,31;		\
-	oris    (reg),(reg),(expr)@h;		\
-	ori     (reg),(reg),(expr)@l;
-
-#define LOAD_REG_ADDR(reg,name)			\
-	ld	(reg),name@got(r2)
-
-#define LOAD_REG_ADDRBASE(reg,name)	LOAD_REG_ADDR(reg,name)
-#define ADDROFF(name)			0
-
-/* offsets for stack frame layout */
-#define LRSAVE	16
-
-#else /* 32-bit */
-
-#define LOAD_REG_IMMEDIATE(reg,expr)		\
-	lis	(reg),(expr)@ha;		\
-	addi	(reg),(reg),(expr)@l;
-
-#define LOAD_REG_ADDR(reg,name)		LOAD_REG_IMMEDIATE(reg, name)
-
-#define LOAD_REG_ADDRBASE(reg, name)	lis	(reg),name@ha
-#define ADDROFF(name)			name@l
-
-/* offsets for stack frame layout */
-#define LRSAVE	4
-
-#endif
-
-/* various errata or part fixups */
-#ifdef CONFIG_PPC601_SYNC_FIX
-#define SYNC				\
-BEGIN_FTR_SECTION			\
-	sync;				\
-	isync;				\
-END_FTR_SECTION_IFSET(CPU_FTR_601)
-#define SYNC_601			\
-BEGIN_FTR_SECTION			\
-	sync;				\
-END_FTR_SECTION_IFSET(CPU_FTR_601)
-#define ISYNC_601			\
-BEGIN_FTR_SECTION			\
-	isync;				\
-END_FTR_SECTION_IFSET(CPU_FTR_601)
-#else
-#define	SYNC
-#define SYNC_601
-#define ISYNC_601
-#endif
-
-#ifdef CONFIG_PPC_CELL
-#define MFTB(dest)			\
-90:	mftb  dest;			\
-BEGIN_FTR_SECTION_NESTED(96);		\
-	cmpwi dest,0;			\
-	beq-  90b;			\
-END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96)
-#else
-#define MFTB(dest)			mftb dest
-#endif
-
-#ifndef CONFIG_SMP
-#define TLBSYNC
-#else /* CONFIG_SMP */
-/* tlbsync is not implemented on 601 */
-#define TLBSYNC				\
-BEGIN_FTR_SECTION			\
-	tlbsync;			\
-	sync;				\
-END_FTR_SECTION_IFCLR(CPU_FTR_601)
-#endif
-
-	
-/*
- * This instruction is not implemented on the PPC 603 or 601; however, on
- * the 403GCX and 405GP tlbia IS defined and tlbie is not.
- * All of these instructions exist in the 8xx, they have magical powers,
- * and they must be used.
- */
-
-#if !defined(CONFIG_4xx) && !defined(CONFIG_8xx)
-#define tlbia					\
-	li	r4,1024;			\
-	mtctr	r4;				\
-	lis	r4,KERNELBASE@h;		\
-0:	tlbie	r4;				\
-	addi	r4,r4,0x1000;			\
-	bdnz	0b
-#endif
-
-
-#ifdef CONFIG_IBM440EP_ERR42
-#define PPC440EP_ERR42 isync
-#else
-#define PPC440EP_ERR42
-#endif
-
-/*
- * toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them
- * keep the address intact to be compatible with code shared with
- * 32-bit classic.
- *
- * On the other hand, I find it useful to have them behave as expected
- * by their name (ie always do the addition) on 64-bit BookE
- */
-#if defined(CONFIG_BOOKE) && !defined(CONFIG_PPC64)
-#define toreal(rd)
-#define fromreal(rd)
-
-/*
- * We use addis to ensure compatibility with the "classic" ppc versions of
- * these macros, which use rs = 0 to get the tophys offset in rd, rather than
- * converting the address in r0, and so this version has to do that too
- * (i.e. set register rd to 0 when rs == 0).
- */
-#define tophys(rd,rs)				\
-	addis	rd,rs,0
-
-#define tovirt(rd,rs)				\
-	addis	rd,rs,0
-
-#elif defined(CONFIG_PPC64)
-#define toreal(rd)		/* we can access c000... in real mode */
-#define fromreal(rd)
-
-#define tophys(rd,rs)                           \
-	clrldi	rd,rs,2
-
-#define tovirt(rd,rs)                           \
-	rotldi	rd,rs,16;			\
-	ori	rd,rd,((KERNELBASE>>48)&0xFFFF);\
-	rotldi	rd,rd,48
-#else
-/*
- * On APUS (Amiga PowerPC cpu upgrade board), we don't know the
- * physical base address of RAM at compile time.
- */
-#define toreal(rd)	tophys(rd,rd)
-#define fromreal(rd)	tovirt(rd,rd)
-
-#define tophys(rd,rs)				\
-0:	addis	rd,rs,-PAGE_OFFSET@h;		\
-	.section ".vtop_fixup","aw";		\
-	.align  1;				\
-	.long   0b;				\
-	.previous
-
-#define tovirt(rd,rs)				\
-0:	addis	rd,rs,PAGE_OFFSET@h;		\
-	.section ".ptov_fixup","aw";		\
-	.align  1;				\
-	.long   0b;				\
-	.previous
-#endif
-
-#ifdef CONFIG_PPC_BOOK3S_64
-#define RFI		rfid
-#define MTMSRD(r)	mtmsrd	r
-#else
-#define FIX_SRR1(ra, rb)
-#ifndef CONFIG_40x
-#define	RFI		rfi
-#else
-#define RFI		rfi; b .	/* Prevent prefetch past rfi */
-#endif
-#define MTMSRD(r)	mtmsr	r
-#define CLR_TOP32(r)
-#endif
-
-#endif /* __KERNEL__ */
-
-/* The boring bits... */
-
-/* Condition Register Bit Fields */
-
-#define	cr0	0
-#define	cr1	1
-#define	cr2	2
-#define	cr3	3
-#define	cr4	4
-#define	cr5	5
-#define	cr6	6
-#define	cr7	7
-
-
-/* General Purpose Registers (GPRs) */
-
-#define	r0	0
-#define	r1	1
-#define	r2	2
-#define	r3	3
-#define	r4	4
-#define	r5	5
-#define	r6	6
-#define	r7	7
-#define	r8	8
-#define	r9	9
-#define	r10	10
-#define	r11	11
-#define	r12	12
-#define	r13	13
-#define	r14	14
-#define	r15	15
-#define	r16	16
-#define	r17	17
-#define	r18	18
-#define	r19	19
-#define	r20	20
-#define	r21	21
-#define	r22	22
-#define	r23	23
-#define	r24	24
-#define	r25	25
-#define	r26	26
-#define	r27	27
-#define	r28	28
-#define	r29	29
-#define	r30	30
-#define	r31	31
-
-
-/* Floating Point Registers (FPRs) */
-
-#define	fr0	0
-#define	fr1	1
-#define	fr2	2
-#define	fr3	3
-#define	fr4	4
-#define	fr5	5
-#define	fr6	6
-#define	fr7	7
-#define	fr8	8
-#define	fr9	9
-#define	fr10	10
-#define	fr11	11
-#define	fr12	12
-#define	fr13	13
-#define	fr14	14
-#define	fr15	15
-#define	fr16	16
-#define	fr17	17
-#define	fr18	18
-#define	fr19	19
-#define	fr20	20
-#define	fr21	21
-#define	fr22	22
-#define	fr23	23
-#define	fr24	24
-#define	fr25	25
-#define	fr26	26
-#define	fr27	27
-#define	fr28	28
-#define	fr29	29
-#define	fr30	30
-#define	fr31	31
-
-/* AltiVec Registers (VPRs) */
-
-#define	vr0	0
-#define	vr1	1
-#define	vr2	2
-#define	vr3	3
-#define	vr4	4
-#define	vr5	5
-#define	vr6	6
-#define	vr7	7
-#define	vr8	8
-#define	vr9	9
-#define	vr10	10
-#define	vr11	11
-#define	vr12	12
-#define	vr13	13
-#define	vr14	14
-#define	vr15	15
-#define	vr16	16
-#define	vr17	17
-#define	vr18	18
-#define	vr19	19
-#define	vr20	20
-#define	vr21	21
-#define	vr22	22
-#define	vr23	23
-#define	vr24	24
-#define	vr25	25
-#define	vr26	26
-#define	vr27	27
-#define	vr28	28
-#define	vr29	29
-#define	vr30	30
-#define	vr31	31
-
-/* VSX Registers (VSRs) */
-
-#define	vsr0	0
-#define	vsr1	1
-#define	vsr2	2
-#define	vsr3	3
-#define	vsr4	4
-#define	vsr5	5
-#define	vsr6	6
-#define	vsr7	7
-#define	vsr8	8
-#define	vsr9	9
-#define	vsr10	10
-#define	vsr11	11
-#define	vsr12	12
-#define	vsr13	13
-#define	vsr14	14
-#define	vsr15	15
-#define	vsr16	16
-#define	vsr17	17
-#define	vsr18	18
-#define	vsr19	19
-#define	vsr20	20
-#define	vsr21	21
-#define	vsr22	22
-#define	vsr23	23
-#define	vsr24	24
-#define	vsr25	25
-#define	vsr26	26
-#define	vsr27	27
-#define	vsr28	28
-#define	vsr29	29
-#define	vsr30	30
-#define	vsr31	31
-#define	vsr32	32
-#define	vsr33	33
-#define	vsr34	34
-#define	vsr35	35
-#define	vsr36	36
-#define	vsr37	37
-#define	vsr38	38
-#define	vsr39	39
-#define	vsr40	40
-#define	vsr41	41
-#define	vsr42	42
-#define	vsr43	43
-#define	vsr44	44
-#define	vsr45	45
-#define	vsr46	46
-#define	vsr47	47
-#define	vsr48	48
-#define	vsr49	49
-#define	vsr50	50
-#define	vsr51	51
-#define	vsr52	52
-#define	vsr53	53
-#define	vsr54	54
-#define	vsr55	55
-#define	vsr56	56
-#define	vsr57	57
-#define	vsr58	58
-#define	vsr59	59
-#define	vsr60	60
-#define	vsr61	61
-#define	vsr62	62
-#define	vsr63	63
-
-/* SPE Registers (EVPRs) */
-
-#define	evr0	0
-#define	evr1	1
-#define	evr2	2
-#define	evr3	3
-#define	evr4	4
-#define	evr5	5
-#define	evr6	6
-#define	evr7	7
-#define	evr8	8
-#define	evr9	9
-#define	evr10	10
-#define	evr11	11
-#define	evr12	12
-#define	evr13	13
-#define	evr14	14
-#define	evr15	15
-#define	evr16	16
-#define	evr17	17
-#define	evr18	18
-#define	evr19	19
-#define	evr20	20
-#define	evr21	21
-#define	evr22	22
-#define	evr23	23
-#define	evr24	24
-#define	evr25	25
-#define	evr26	26
-#define	evr27	27
-#define	evr28	28
-#define	evr29	29
-#define	evr30	30
-#define	evr31	31
-
-/* some stab codes */
-#define N_FUN	36
-#define N_RSYM	64
-#define N_SLINE	68
-#define N_SO	100
-
-#endif /*  __ASSEMBLY__ */
-
-#endif /* _ASM_POWERPC_PPC_ASM_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/processor.h b/ANDROID_3.4.5/arch/powerpc/include/asm/processor.h
deleted file mode 100644
index 8e2d0371..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/processor.h
+++ /dev/null
@@ -1,420 +0,0 @@
-#ifndef _ASM_POWERPC_PROCESSOR_H
-#define _ASM_POWERPC_PROCESSOR_H
-
-/*
- * Copyright (C) 2001 PPC 64 Team, IBM Corp
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <asm/reg.h>
-
-#ifdef CONFIG_VSX
-#define TS_FPRWIDTH 2
-#else
-#define TS_FPRWIDTH 1
-#endif
-
-#ifndef __ASSEMBLY__
-#include <linux/compiler.h>
-#include <linux/cache.h>
-#include <asm/ptrace.h>
-#include <asm/types.h>
-
-/* We do _not_ want to define new machine types at all, those must die
- * in favor of using the device-tree
- * -- BenH.
- */
-
-/* PREP sub-platform types see residual.h for these */
-#define _PREP_Motorola	0x01	/* motorola prep */
-#define _PREP_Firm	0x02	/* firmworks prep */
-#define _PREP_IBM	0x00	/* ibm prep */
-#define _PREP_Bull	0x03	/* bull prep */
-
-/* CHRP sub-platform types. These are arbitrary */
-#define _CHRP_Motorola	0x04	/* motorola chrp, the cobra */
-#define _CHRP_IBM	0x05	/* IBM chrp, the longtrail and longtrail 2 */
-#define _CHRP_Pegasos	0x06	/* Genesi/bplan's Pegasos and Pegasos2 */
-#define _CHRP_briq	0x07	/* TotalImpact's briQ */
-
-#if defined(__KERNEL__) && defined(CONFIG_PPC32)
-
-extern int _chrp_type;
-
-#ifdef CONFIG_PPC_PREP
-
-/* what kind of prep workstation we are */
-extern int _prep_type;
-
-#endif /* CONFIG_PPC_PREP */
-
-#endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */
-
-/*
- * Default implementation of macro that returns current
- * instruction pointer ("program counter").
- */
-#define current_text_addr() ({ __label__ _l; _l: &&_l;})
-
-/* Macros for adjusting thread priority (hardware multi-threading) */
-#define HMT_very_low()   asm volatile("or 31,31,31   # very low priority")
-#define HMT_low()	 asm volatile("or 1,1,1	     # low priority")
-#define HMT_medium_low() asm volatile("or 6,6,6      # medium low priority")
-#define HMT_medium()	 asm volatile("or 2,2,2	     # medium priority")
-#define HMT_medium_high() asm volatile("or 5,5,5      # medium high priority")
-#define HMT_high()	 asm volatile("or 3,3,3	     # high priority")
-
-#ifdef __KERNEL__
-
-struct task_struct;
-void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp);
-void release_thread(struct task_struct *);
-
-/* Prepare to copy thread state - unlazy all lazy status */
-extern void prepare_to_copy(struct task_struct *tsk);
-
-/* Create a new kernel thread. */
-extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
-
-/* Lazy FPU handling on uni-processor */
-extern struct task_struct *last_task_used_math;
-extern struct task_struct *last_task_used_altivec;
-extern struct task_struct *last_task_used_vsx;
-extern struct task_struct *last_task_used_spe;
-
-#ifdef CONFIG_PPC32
-
-#if CONFIG_TASK_SIZE > CONFIG_KERNEL_START
-#error User TASK_SIZE overlaps with KERNEL_START address
-#endif
-#define TASK_SIZE	(CONFIG_TASK_SIZE)
-
-/* This decides where the kernel will search for a free chunk of vm
- * space during mmap's.
- */
-#define TASK_UNMAPPED_BASE	(TASK_SIZE / 8 * 3)
-#endif
-
-#ifdef CONFIG_PPC64
-/* 64-bit user address space is 44-bits (16TB user VM) */
-#define TASK_SIZE_USER64 (0x0000100000000000UL)
-
-/* 
- * 32-bit user address space is 4GB - 1 page 
- * (this 1 page is needed so referencing of 0xFFFFFFFF generates EFAULT
- */
-#define TASK_SIZE_USER32 (0x0000000100000000UL - (1*PAGE_SIZE))
-
-#define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \
-		TASK_SIZE_USER32 : TASK_SIZE_USER64)
-#define TASK_SIZE	  TASK_SIZE_OF(current)
-
-/* This decides where the kernel will search for a free chunk of vm
- * space during mmap's.
- */
-#define TASK_UNMAPPED_BASE_USER32 (PAGE_ALIGN(TASK_SIZE_USER32 / 4))
-#define TASK_UNMAPPED_BASE_USER64 (PAGE_ALIGN(TASK_SIZE_USER64 / 4))
-
-#define TASK_UNMAPPED_BASE ((is_32bit_task()) ? \
-		TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 )
-#endif
-
-#ifdef __powerpc64__
-
-#define STACK_TOP_USER64 TASK_SIZE_USER64
-#define STACK_TOP_USER32 TASK_SIZE_USER32
-
-#define STACK_TOP (is_32bit_task() ? \
-		   STACK_TOP_USER32 : STACK_TOP_USER64)
-
-#define STACK_TOP_MAX STACK_TOP_USER64
-
-#else /* __powerpc64__ */
-
-#define STACK_TOP TASK_SIZE
-#define STACK_TOP_MAX	STACK_TOP
-
-#endif /* __powerpc64__ */
-
-typedef struct {
-	unsigned long seg;
-} mm_segment_t;
-
-#define TS_FPROFFSET 0
-#define TS_VSRLOWOFFSET 1
-#define TS_FPR(i) fpr[i][TS_FPROFFSET]
-
-struct thread_struct {
-	unsigned long	ksp;		/* Kernel stack pointer */
-	unsigned long	ksp_limit;	/* if ksp <= ksp_limit stack overflow */
-
-#ifdef CONFIG_PPC64
-	unsigned long	ksp_vsid;
-#endif
-	struct pt_regs	*regs;		/* Pointer to saved register state */
-	mm_segment_t	fs;		/* for get_fs() validation */
-#ifdef CONFIG_BOOKE
-	/* BookE base exception scratch space; align on cacheline */
-	unsigned long	normsave[8] ____cacheline_aligned;
-#endif
-#ifdef CONFIG_PPC32
-	void		*pgdir;		/* root of page-table tree */
-#endif
-#ifdef CONFIG_PPC_ADV_DEBUG_REGS
-	/*
-	 * The following help to manage the use of Debug Control Registers
-	 * om the BookE platforms.
-	 */
-	unsigned long	dbcr0;
-	unsigned long	dbcr1;
-#ifdef CONFIG_BOOKE
-	unsigned long	dbcr2;
-#endif
-	/*
-	 * The stored value of the DBSR register will be the value at the
-	 * last debug interrupt. This register can only be read from the
-	 * user (will never be written to) and has value while helping to
-	 * describe the reason for the last debug trap.  Torez
-	 */
-	unsigned long	dbsr;
-	/*
-	 * The following will contain addresses used by debug applications
-	 * to help trace and trap on particular address locations.
-	 * The bits in the Debug Control Registers above help define which
-	 * of the following registers will contain valid data and/or addresses.
-	 */
-	unsigned long	iac1;
-	unsigned long	iac2;
-#if CONFIG_PPC_ADV_DEBUG_IACS > 2
-	unsigned long	iac3;
-	unsigned long	iac4;
-#endif
-	unsigned long	dac1;
-	unsigned long	dac2;
-#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
-	unsigned long	dvc1;
-	unsigned long	dvc2;
-#endif
-#endif
-	/* FP and VSX 0-31 register set */
-	double		fpr[32][TS_FPRWIDTH];
-	struct {
-
-		unsigned int pad;
-		unsigned int val;	/* Floating point status */
-	} fpscr;
-	int		fpexc_mode;	/* floating-point exception mode */
-	unsigned int	align_ctl;	/* alignment handling control */
-#ifdef CONFIG_PPC64
-	unsigned long	start_tb;	/* Start purr when proc switched in */
-	unsigned long	accum_tb;	/* Total accumilated purr for process */
-#ifdef CONFIG_HAVE_HW_BREAKPOINT
-	struct perf_event *ptrace_bps[HBP_NUM];
-	/*
-	 * Helps identify source of single-step exception and subsequent
-	 * hw-breakpoint enablement
-	 */
-	struct perf_event *last_hit_ubp;
-#endif /* CONFIG_HAVE_HW_BREAKPOINT */
-#endif
-	unsigned long	dabr;		/* Data address breakpoint register */
-#ifdef CONFIG_ALTIVEC
-	/* Complete AltiVec register set */
-	vector128	vr[32] __attribute__((aligned(16)));
-	/* AltiVec status */
-	vector128	vscr __attribute__((aligned(16)));
-	unsigned long	vrsave;
-	int		used_vr;	/* set if process has used altivec */
-#endif /* CONFIG_ALTIVEC */
-#ifdef CONFIG_VSX
-	/* VSR status */
-	int		used_vsr;	/* set if process has used altivec */
-#endif /* CONFIG_VSX */
-#ifdef CONFIG_SPE
-	unsigned long	evr[32];	/* upper 32-bits of SPE regs */
-	u64		acc;		/* Accumulator */
-	unsigned long	spefscr;	/* SPE & eFP status */
-	int		used_spe;	/* set if process has used spe */
-#endif /* CONFIG_SPE */
-#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
-	void*		kvm_shadow_vcpu; /* KVM internal data */
-#endif /* CONFIG_KVM_BOOK3S_32_HANDLER */
-#ifdef CONFIG_PPC64
-	unsigned long	dscr;
-	int		dscr_inherit;
-#endif
-};
-
-#define ARCH_MIN_TASKALIGN 16
-
-#define INIT_SP		(sizeof(init_stack) + (unsigned long) &init_stack)
-#define INIT_SP_LIMIT \
-	(_ALIGN_UP(sizeof(init_thread_info), 16) + (unsigned long) &init_stack)
-
-#ifdef CONFIG_SPE
-#define SPEFSCR_INIT .spefscr = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE,
-#else
-#define SPEFSCR_INIT
-#endif
-
-#ifdef CONFIG_PPC32
-#define INIT_THREAD { \
-	.ksp = INIT_SP, \
-	.ksp_limit = INIT_SP_LIMIT, \
-	.fs = KERNEL_DS, \
-	.pgdir = swapper_pg_dir, \
-	.fpexc_mode = MSR_FE0 | MSR_FE1, \
-	SPEFSCR_INIT \
-}
-#else
-#define INIT_THREAD  { \
-	.ksp = INIT_SP, \
-	.ksp_limit = INIT_SP_LIMIT, \
-	.regs = (struct pt_regs *)INIT_SP - 1, /* XXX bogus, I think */ \
-	.fs = KERNEL_DS, \
-	.fpr = {{0}}, \
-	.fpscr = { .val = 0, }, \
-	.fpexc_mode = 0, \
-}
-#endif
-
-/*
- * Return saved PC of a blocked thread. For now, this is the "user" PC
- */
-#define thread_saved_pc(tsk)    \
-        ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
-
-#define task_pt_regs(tsk)	((struct pt_regs *)(tsk)->thread.regs)
-
-unsigned long get_wchan(struct task_struct *p);
-
-#define KSTK_EIP(tsk)  ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
-#define KSTK_ESP(tsk)  ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)
-
-/* Get/set floating-point exception mode */
-#define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
-#define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))
-
-extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
-extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);
-
-#define GET_ENDIAN(tsk, adr) get_endian((tsk), (adr))
-#define SET_ENDIAN(tsk, val) set_endian((tsk), (val))
-
-extern int get_endian(struct task_struct *tsk, unsigned long adr);
-extern int set_endian(struct task_struct *tsk, unsigned int val);
-
-#define GET_UNALIGN_CTL(tsk, adr)	get_unalign_ctl((tsk), (adr))
-#define SET_UNALIGN_CTL(tsk, val)	set_unalign_ctl((tsk), (val))
-
-extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr);
-extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);
-
-static inline unsigned int __unpack_fe01(unsigned long msr_bits)
-{
-	return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8);
-}
-
-static inline unsigned long __pack_fe01(unsigned int fpmode)
-{
-	return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1);
-}
-
-#ifdef CONFIG_PPC64
-#define cpu_relax()	do { HMT_low(); HMT_medium(); barrier(); } while (0)
-#else
-#define cpu_relax()	barrier()
-#endif
-
-/* Check that a certain kernel stack pointer is valid in task_struct p */
-int validate_sp(unsigned long sp, struct task_struct *p,
-                       unsigned long nbytes);
-
-/*
- * Prefetch macros.
- */
-#define ARCH_HAS_PREFETCH
-#define ARCH_HAS_PREFETCHW
-#define ARCH_HAS_SPINLOCK_PREFETCH
-
-static inline void prefetch(const void *x)
-{
-	if (unlikely(!x))
-		return;
-
-	__asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
-}
-
-static inline void prefetchw(const void *x)
-{
-	if (unlikely(!x))
-		return;
-
-	__asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
-}
-
-#define spin_lock_prefetch(x)	prefetchw(x)
-
-#ifdef CONFIG_PPC64
-#define HAVE_ARCH_PICK_MMAP_LAYOUT
-#endif
-
-#ifdef CONFIG_PPC64
-static inline unsigned long get_clean_sp(struct pt_regs *regs, int is_32)
-{
-	unsigned long sp;
-
-	if (is_32)
-		sp = regs->gpr[1] & 0x0ffffffffUL;
-	else
-		sp = regs->gpr[1];
-
-	return sp;
-}
-#else
-static inline unsigned long get_clean_sp(struct pt_regs *regs, int is_32)
-{
-	return regs->gpr[1];
-}
-#endif
-
-extern unsigned long cpuidle_disable;
-enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};
-
-extern int powersave_nap;	/* set if nap mode can be used in idle loop */
-void cpu_idle_wait(void);
-
-#ifdef CONFIG_PSERIES_IDLE
-extern void update_smt_snooze_delay(int snooze);
-extern int pseries_notify_cpuidle_add_cpu(int cpu);
-#else
-static inline void update_smt_snooze_delay(int snooze) {}
-static inline int pseries_notify_cpuidle_add_cpu(int cpu) { return 0; }
-#endif
-
-extern void flush_instruction_cache(void);
-extern void hard_reset_now(void);
-extern void poweroff_now(void);
-extern int fix_alignment(struct pt_regs *);
-extern void cvt_fd(float *from, double *to);
-extern void cvt_df(double *from, float *to);
-extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
-
-#ifdef CONFIG_PPC64
-/*
- * We handle most unaligned accesses in hardware. On the other hand 
- * unaligned DMA can be very expensive on some ppc64 IO chips (it does
- * powers of 2 writes until it reaches sufficient alignment).
- *
- * Based on this we disable the IP header alignment in network drivers.
- */
-#define NET_IP_ALIGN	0
-#endif
-
-#endif /* __KERNEL__ */
-#endif /* __ASSEMBLY__ */
-#endif /* _ASM_POWERPC_PROCESSOR_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/prom.h b/ANDROID_3.4.5/arch/powerpc/include/asm/prom.h
deleted file mode 100644
index b5c91901..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/prom.h
+++ /dev/null
@@ -1,71 +0,0 @@
-#include <linux/of.h>	/* linux/of.h gets to determine #include ordering */
-#ifndef _POWERPC_PROM_H
-#define _POWERPC_PROM_H
-#ifdef __KERNEL__
-
-/*
- * Definitions for talking to the Open Firmware PROM on
- * Power Macintosh computers.
- *
- * Copyright (C) 1996-2005 Paul Mackerras.
- *
- * Updates for PPC64 by Peter Bergner & David Engebretsen, IBM Corp.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#include <linux/types.h>
-#include <asm/irq.h>
-#include <linux/atomic.h>
-
-#define HAVE_ARCH_DEVTREE_FIXUPS
-
-/*
- * OF address retreival & translation
- */
-
-/* Translate a DMA address from device space to CPU space */
-extern u64 of_translate_dma_address(struct device_node *dev,
-				    const __be32 *in_addr);
-
-#ifdef CONFIG_PCI
-extern unsigned long pci_address_to_pio(phys_addr_t address);
-#define pci_address_to_pio pci_address_to_pio
-#endif	/* CONFIG_PCI */
-
-/* Parse the ibm,dma-window property of an OF node into the busno, phys and
- * size parameters.
- */
-void of_parse_dma_window(struct device_node *dn, const void *dma_window_prop,
-		unsigned long *busno, unsigned long *phys, unsigned long *size);
-
-extern void kdump_move_device_tree(void);
-
-/* CPU OF node matching */
-struct device_node *of_get_cpu_node(int cpu, unsigned int *thread);
-
-/* cache lookup */
-struct device_node *of_find_next_cache_node(struct device_node *np);
-
-#ifdef CONFIG_NUMA
-extern int of_node_to_nid(struct device_node *device);
-#else
-static inline int of_node_to_nid(struct device_node *device) { return 0; }
-#endif
-#define of_node_to_nid of_node_to_nid
-
-extern void of_instantiate_rtc(void);
-
-/* These includes are put at the bottom because they may contain things
- * that are overridden by this file.  Ideally they shouldn't be included
- * by this file, but there are a bunch of .c files that currently depend
- * on it.  Eventually they will be cleaned up. */
-#include <linux/of_fdt.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/platform_device.h>
-
-#endif /* __KERNEL__ */
-#endif /* _POWERPC_PROM_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/ps3.h b/ANDROID_3.4.5/arch/powerpc/include/asm/ps3.h
deleted file mode 100644
index 7f065e17..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/ps3.h
+++ /dev/null
@@ -1,530 +0,0 @@
-/*
- *  PS3 platform declarations.
- *
- *  Copyright (C) 2006 Sony Computer Entertainment Inc.
- *  Copyright 2006 Sony Corp.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; version 2 of the License.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#if !defined(_ASM_POWERPC_PS3_H)
-#define _ASM_POWERPC_PS3_H
-
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/device.h>
-#include "cell-pmu.h"
-
-union ps3_firmware_version {
-	u64 raw;
-	struct {
-		u16 pad;
-		u16 major;
-		u16 minor;
-		u16 rev;
-	};
-};
-
-void ps3_get_firmware_version(union ps3_firmware_version *v);
-int ps3_compare_firmware_version(u16 major, u16 minor, u16 rev);
-
-/* 'Other OS' area */
-
-enum ps3_param_av_multi_out {
-	PS3_PARAM_AV_MULTI_OUT_NTSC = 0,
-	PS3_PARAM_AV_MULTI_OUT_PAL_RGB = 1,
-	PS3_PARAM_AV_MULTI_OUT_PAL_YCBCR = 2,
-	PS3_PARAM_AV_MULTI_OUT_SECAM = 3,
-};
-
-enum ps3_param_av_multi_out ps3_os_area_get_av_multi_out(void);
-
-extern u64 ps3_os_area_get_rtc_diff(void);
-extern void ps3_os_area_set_rtc_diff(u64 rtc_diff);
-
-struct ps3_os_area_flash_ops {
-	ssize_t (*read)(void *buf, size_t count, loff_t pos);
-	ssize_t (*write)(const void *buf, size_t count, loff_t pos);
-};
-
-extern void ps3_os_area_flash_register(const struct ps3_os_area_flash_ops *ops);
-
-/* dma routines */
-
-enum ps3_dma_page_size {
-	PS3_DMA_4K = 12U,
-	PS3_DMA_64K = 16U,
-	PS3_DMA_1M = 20U,
-	PS3_DMA_16M = 24U,
-};
-
-enum ps3_dma_region_type {
-	PS3_DMA_OTHER = 0,
-	PS3_DMA_INTERNAL = 2,
-};
-
-struct ps3_dma_region_ops;
-
-/**
- * struct ps3_dma_region - A per device dma state variables structure
- * @did: The HV device id.
- * @page_size: The ioc pagesize.
- * @region_type: The HV region type.
- * @bus_addr: The 'translated' bus address of the region.
- * @len: The length in bytes of the region.
- * @offset: The offset from the start of memory of the region.
- * @ioid: The IOID of the device who owns this region
- * @chunk_list: Opaque variable used by the ioc page manager.
- * @region_ops: struct ps3_dma_region_ops - dma region operations
- */
-
-struct ps3_dma_region {
-	struct ps3_system_bus_device *dev;
-	/* device variables */
-	const struct ps3_dma_region_ops *region_ops;
-	unsigned char ioid;
-	enum ps3_dma_page_size page_size;
-	enum ps3_dma_region_type region_type;
-	unsigned long len;
-	unsigned long offset;
-
-	/* driver variables  (set by ps3_dma_region_create) */
-	unsigned long bus_addr;
-	struct {
-		spinlock_t lock;
-		struct list_head head;
-	} chunk_list;
-};
-
-struct ps3_dma_region_ops {
-	int (*create)(struct ps3_dma_region *);
-	int (*free)(struct ps3_dma_region *);
-	int (*map)(struct ps3_dma_region *,
-		   unsigned long virt_addr,
-		   unsigned long len,
-		   dma_addr_t *bus_addr,
-		   u64 iopte_pp);
-	int (*unmap)(struct ps3_dma_region *,
-		     dma_addr_t bus_addr,
-		     unsigned long len);
-};
-/**
- * struct ps3_dma_region_init - Helper to initialize structure variables
- *
- * Helper to properly initialize variables prior to calling
- * ps3_system_bus_device_register.
- */
-
-struct ps3_system_bus_device;
-
-int ps3_dma_region_init(struct ps3_system_bus_device *dev,
-	struct ps3_dma_region *r, enum ps3_dma_page_size page_size,
-	enum ps3_dma_region_type region_type, void *addr, unsigned long len);
-int ps3_dma_region_create(struct ps3_dma_region *r);
-int ps3_dma_region_free(struct ps3_dma_region *r);
-int ps3_dma_map(struct ps3_dma_region *r, unsigned long virt_addr,
-	unsigned long len, dma_addr_t *bus_addr,
-	u64 iopte_pp);
-int ps3_dma_unmap(struct ps3_dma_region *r, dma_addr_t bus_addr,
-	unsigned long len);
-
-/* mmio routines */
-
-enum ps3_mmio_page_size {
-	PS3_MMIO_4K = 12U,
-	PS3_MMIO_64K = 16U
-};
-
-struct ps3_mmio_region_ops;
-/**
- * struct ps3_mmio_region - a per device mmio state variables structure
- *
- * Current systems can be supported with a single region per device.
- */
-
-struct ps3_mmio_region {
-	struct ps3_system_bus_device *dev;
-	const struct ps3_mmio_region_ops *mmio_ops;
-	unsigned long bus_addr;
-	unsigned long len;
-	enum ps3_mmio_page_size page_size;
-	unsigned long lpar_addr;
-};
-
-struct ps3_mmio_region_ops {
-	int (*create)(struct ps3_mmio_region *);
-	int (*free)(struct ps3_mmio_region *);
-};
-/**
- * struct ps3_mmio_region_init - Helper to initialize structure variables
- *
- * Helper to properly initialize variables prior to calling
- * ps3_system_bus_device_register.
- */
-
-int ps3_mmio_region_init(struct ps3_system_bus_device *dev,
-	struct ps3_mmio_region *r, unsigned long bus_addr, unsigned long len,
-	enum ps3_mmio_page_size page_size);
-int ps3_mmio_region_create(struct ps3_mmio_region *r);
-int ps3_free_mmio_region(struct ps3_mmio_region *r);
-unsigned long ps3_mm_phys_to_lpar(unsigned long phys_addr);
-
-/* inrerrupt routines */
-
-enum ps3_cpu_binding {
-	PS3_BINDING_CPU_ANY = -1,
-	PS3_BINDING_CPU_0 = 0,
-	PS3_BINDING_CPU_1 = 1,
-};
-
-int ps3_irq_plug_setup(enum ps3_cpu_binding cpu, unsigned long outlet,
-	unsigned int *virq);
-int ps3_irq_plug_destroy(unsigned int virq);
-int ps3_event_receive_port_setup(enum ps3_cpu_binding cpu, unsigned int *virq);
-int ps3_event_receive_port_destroy(unsigned int virq);
-int ps3_send_event_locally(unsigned int virq);
-
-int ps3_io_irq_setup(enum ps3_cpu_binding cpu, unsigned int interrupt_id,
-	unsigned int *virq);
-int ps3_io_irq_destroy(unsigned int virq);
-int ps3_vuart_irq_setup(enum ps3_cpu_binding cpu, void* virt_addr_bmp,
-	unsigned int *virq);
-int ps3_vuart_irq_destroy(unsigned int virq);
-int ps3_spe_irq_setup(enum ps3_cpu_binding cpu, unsigned long spe_id,
-	unsigned int class, unsigned int *virq);
-int ps3_spe_irq_destroy(unsigned int virq);
-
-int ps3_sb_event_receive_port_setup(struct ps3_system_bus_device *dev,
-	enum ps3_cpu_binding cpu, unsigned int *virq);
-int ps3_sb_event_receive_port_destroy(struct ps3_system_bus_device *dev,
-	unsigned int virq);
-
-/* lv1 result codes */
-
-enum lv1_result {
-	LV1_SUCCESS                     = 0,
-	/* not used                       -1 */
-	LV1_RESOURCE_SHORTAGE           = -2,
-	LV1_NO_PRIVILEGE                = -3,
-	LV1_DENIED_BY_POLICY            = -4,
-	LV1_ACCESS_VIOLATION            = -5,
-	LV1_NO_ENTRY                    = -6,
-	LV1_DUPLICATE_ENTRY             = -7,
-	LV1_TYPE_MISMATCH               = -8,
-	LV1_BUSY                        = -9,
-	LV1_EMPTY                       = -10,
-	LV1_WRONG_STATE                 = -11,
-	/* not used                       -12 */
-	LV1_NO_MATCH                    = -13,
-	LV1_ALREADY_CONNECTED           = -14,
-	LV1_UNSUPPORTED_PARAMETER_VALUE = -15,
-	LV1_CONDITION_NOT_SATISFIED     = -16,
-	LV1_ILLEGAL_PARAMETER_VALUE     = -17,
-	LV1_BAD_OPTION                  = -18,
-	LV1_IMPLEMENTATION_LIMITATION   = -19,
-	LV1_NOT_IMPLEMENTED             = -20,
-	LV1_INVALID_CLASS_ID            = -21,
-	LV1_CONSTRAINT_NOT_SATISFIED    = -22,
-	LV1_ALIGNMENT_ERROR             = -23,
-	LV1_HARDWARE_ERROR              = -24,
-	LV1_INVALID_DATA_FORMAT         = -25,
-	LV1_INVALID_OPERATION           = -26,
-	LV1_INTERNAL_ERROR              = -32768,
-};
-
-static inline const char* ps3_result(int result)
-{
-#if defined(DEBUG)
-	switch (result) {
-	case LV1_SUCCESS:
-		return "LV1_SUCCESS (0)";
-	case -1:
-		return "** unknown result ** (-1)";
-	case LV1_RESOURCE_SHORTAGE:
-		return "LV1_RESOURCE_SHORTAGE (-2)";
-	case LV1_NO_PRIVILEGE:
-		return "LV1_NO_PRIVILEGE (-3)";
-	case LV1_DENIED_BY_POLICY:
-		return "LV1_DENIED_BY_POLICY (-4)";
-	case LV1_ACCESS_VIOLATION:
-		return "LV1_ACCESS_VIOLATION (-5)";
-	case LV1_NO_ENTRY:
-		return "LV1_NO_ENTRY (-6)";
-	case LV1_DUPLICATE_ENTRY:
-		return "LV1_DUPLICATE_ENTRY (-7)";
-	case LV1_TYPE_MISMATCH:
-		return "LV1_TYPE_MISMATCH (-8)";
-	case LV1_BUSY:
-		return "LV1_BUSY (-9)";
-	case LV1_EMPTY:
-		return "LV1_EMPTY (-10)";
-	case LV1_WRONG_STATE:
-		return "LV1_WRONG_STATE (-11)";
-	case -12:
-		return "** unknown result ** (-12)";
-	case LV1_NO_MATCH:
-		return "LV1_NO_MATCH (-13)";
-	case LV1_ALREADY_CONNECTED:
-		return "LV1_ALREADY_CONNECTED (-14)";
-	case LV1_UNSUPPORTED_PARAMETER_VALUE:
-		return "LV1_UNSUPPORTED_PARAMETER_VALUE (-15)";
-	case LV1_CONDITION_NOT_SATISFIED:
-		return "LV1_CONDITION_NOT_SATISFIED (-16)";
-	case LV1_ILLEGAL_PARAMETER_VALUE:
-		return "LV1_ILLEGAL_PARAMETER_VALUE (-17)";
-	case LV1_BAD_OPTION:
-		return "LV1_BAD_OPTION (-18)";
-	case LV1_IMPLEMENTATION_LIMITATION:
-		return "LV1_IMPLEMENTATION_LIMITATION (-19)";
-	case LV1_NOT_IMPLEMENTED:
-		return "LV1_NOT_IMPLEMENTED (-20)";
-	case LV1_INVALID_CLASS_ID:
-		return "LV1_INVALID_CLASS_ID (-21)";
-	case LV1_CONSTRAINT_NOT_SATISFIED:
-		return "LV1_CONSTRAINT_NOT_SATISFIED (-22)";
-	case LV1_ALIGNMENT_ERROR:
-		return "LV1_ALIGNMENT_ERROR (-23)";
-	case LV1_HARDWARE_ERROR:
-		return "LV1_HARDWARE_ERROR (-24)";
-	case LV1_INVALID_DATA_FORMAT:
-		return "LV1_INVALID_DATA_FORMAT (-25)";
-	case LV1_INVALID_OPERATION:
-		return "LV1_INVALID_OPERATION (-26)";
-	case LV1_INTERNAL_ERROR:
-		return "LV1_INTERNAL_ERROR (-32768)";
-	default:
-		BUG();
-		return "** unknown result **";
-	};
-#else
-	return "";
-#endif
-}
-
-/* system bus routines */
-
-enum ps3_match_id {
-	PS3_MATCH_ID_EHCI		= 1,
-	PS3_MATCH_ID_OHCI		= 2,
-	PS3_MATCH_ID_GELIC		= 3,
-	PS3_MATCH_ID_AV_SETTINGS	= 4,
-	PS3_MATCH_ID_SYSTEM_MANAGER	= 5,
-	PS3_MATCH_ID_STOR_DISK		= 6,
-	PS3_MATCH_ID_STOR_ROM		= 7,
-	PS3_MATCH_ID_STOR_FLASH		= 8,
-	PS3_MATCH_ID_SOUND		= 9,
-	PS3_MATCH_ID_GPU		= 10,
-	PS3_MATCH_ID_LPM		= 11,
-};
-
-enum ps3_match_sub_id {
-	PS3_MATCH_SUB_ID_GPU_FB		= 1,
-	PS3_MATCH_SUB_ID_GPU_RAMDISK	= 2,
-};
-
-#define PS3_MODULE_ALIAS_EHCI		"ps3:1:0"
-#define PS3_MODULE_ALIAS_OHCI		"ps3:2:0"
-#define PS3_MODULE_ALIAS_GELIC		"ps3:3:0"
-#define PS3_MODULE_ALIAS_AV_SETTINGS	"ps3:4:0"
-#define PS3_MODULE_ALIAS_SYSTEM_MANAGER	"ps3:5:0"
-#define PS3_MODULE_ALIAS_STOR_DISK	"ps3:6:0"
-#define PS3_MODULE_ALIAS_STOR_ROM	"ps3:7:0"
-#define PS3_MODULE_ALIAS_STOR_FLASH	"ps3:8:0"
-#define PS3_MODULE_ALIAS_SOUND		"ps3:9:0"
-#define PS3_MODULE_ALIAS_GPU_FB		"ps3:10:1"
-#define PS3_MODULE_ALIAS_GPU_RAMDISK	"ps3:10:2"
-#define PS3_MODULE_ALIAS_LPM		"ps3:11:0"
-
-enum ps3_system_bus_device_type {
-	PS3_DEVICE_TYPE_IOC0 = 1,
-	PS3_DEVICE_TYPE_SB,
-	PS3_DEVICE_TYPE_VUART,
-	PS3_DEVICE_TYPE_LPM,
-};
-
-/**
- * struct ps3_system_bus_device - a device on the system bus
- */
-
-struct ps3_system_bus_device {
-	enum ps3_match_id match_id;
-	enum ps3_match_sub_id match_sub_id;
-	enum ps3_system_bus_device_type dev_type;
-
-	u64 bus_id;                       /* SB */
-	u64 dev_id;                       /* SB */
-	unsigned int interrupt_id;        /* SB */
-	struct ps3_dma_region *d_region;  /* SB, IOC0 */
-	struct ps3_mmio_region *m_region; /* SB, IOC0*/
-	unsigned int port_number;         /* VUART */
-	struct {                          /* LPM */
-		u64 node_id;
-		u64 pu_id;
-		u64 rights;
-	} lpm;
-
-/*	struct iommu_table *iommu_table; -- waiting for BenH's cleanups */
-	struct device core;
-	void *driver_priv; /* private driver variables */
-};
-
-int ps3_open_hv_device(struct ps3_system_bus_device *dev);
-int ps3_close_hv_device(struct ps3_system_bus_device *dev);
-
-/**
- * struct ps3_system_bus_driver - a driver for a device on the system bus
- */
-
-struct ps3_system_bus_driver {
-	enum ps3_match_id match_id;
-	enum ps3_match_sub_id match_sub_id;
-	struct device_driver core;
-	int (*probe)(struct ps3_system_bus_device *);
-	int (*remove)(struct ps3_system_bus_device *);
-	int (*shutdown)(struct ps3_system_bus_device *);
-/*	int (*suspend)(struct ps3_system_bus_device *, pm_message_t); */
-/*	int (*resume)(struct ps3_system_bus_device *); */
-};
-
-int ps3_system_bus_device_register(struct ps3_system_bus_device *dev);
-int ps3_system_bus_driver_register(struct ps3_system_bus_driver *drv);
-void ps3_system_bus_driver_unregister(struct ps3_system_bus_driver *drv);
-
-static inline struct ps3_system_bus_driver *ps3_drv_to_system_bus_drv(
-	struct device_driver *_drv)
-{
-	return container_of(_drv, struct ps3_system_bus_driver, core);
-}
-static inline struct ps3_system_bus_device *ps3_dev_to_system_bus_dev(
-	struct device *_dev)
-{
-	return container_of(_dev, struct ps3_system_bus_device, core);
-}
-static inline struct ps3_system_bus_driver *
-	ps3_system_bus_dev_to_system_bus_drv(struct ps3_system_bus_device *_dev)
-{
-	BUG_ON(!_dev);
-	BUG_ON(!_dev->core.driver);
-	return ps3_drv_to_system_bus_drv(_dev->core.driver);
-}
-
-/**
- * ps3_system_bus_set_drvdata -
- * @dev: device structure
- * @data: Data to set
- */
-
-static inline void ps3_system_bus_set_drvdata(
-	struct ps3_system_bus_device *dev, void *data)
-{
-	dev_set_drvdata(&dev->core, data);
-}
-static inline void *ps3_system_bus_get_drvdata(
-	struct ps3_system_bus_device *dev)
-{
-	return dev_get_drvdata(&dev->core);
-}
-
-/* These two need global scope for get_dma_ops(). */
-
-extern struct bus_type ps3_system_bus_type;
-
-/* system manager */
-
-struct ps3_sys_manager_ops {
-	struct ps3_system_bus_device *dev;
-	void (*power_off)(struct ps3_system_bus_device *dev);
-	void (*restart)(struct ps3_system_bus_device *dev);
-};
-
-void ps3_sys_manager_register_ops(const struct ps3_sys_manager_ops *ops);
-void __noreturn ps3_sys_manager_power_off(void);
-void __noreturn ps3_sys_manager_restart(void);
-void __noreturn ps3_sys_manager_halt(void);
-int ps3_sys_manager_get_wol(void);
-void ps3_sys_manager_set_wol(int state);
-
-struct ps3_prealloc {
-    const char *name;
-    void *address;
-    unsigned long size;
-    unsigned long align;
-};
-
-extern struct ps3_prealloc ps3fb_videomemory;
-extern struct ps3_prealloc ps3flash_bounce_buffer;
-
-/* logical performance monitor */
-
-/**
- * enum ps3_lpm_rights - Rigths granted by the system policy module.
- *
- * @PS3_LPM_RIGHTS_USE_LPM: The right to use the lpm.
- * @PS3_LPM_RIGHTS_USE_TB: The right to use the internal trace buffer.
- */
-
-enum ps3_lpm_rights {
-	PS3_LPM_RIGHTS_USE_LPM = 0x001,
-	PS3_LPM_RIGHTS_USE_TB = 0x100,
-};
-
-/**
- * enum ps3_lpm_tb_type - Type of trace buffer lv1 should use.
- *
- * @PS3_LPM_TB_TYPE_NONE: Do not use a trace buffer.
- * @PS3_LPM_RIGHTS_USE_TB: Use the lv1 internal trace buffer.  Must have
- *  rights @PS3_LPM_RIGHTS_USE_TB.
- */
-
-enum ps3_lpm_tb_type {
-	PS3_LPM_TB_TYPE_NONE = 0,
-	PS3_LPM_TB_TYPE_INTERNAL = 1,
-};
-
-int ps3_lpm_open(enum ps3_lpm_tb_type tb_type, void *tb_cache,
-	u64 tb_cache_size);
-int ps3_lpm_close(void);
-int ps3_lpm_copy_tb(unsigned long offset, void *buf, unsigned long count,
-	unsigned long *bytes_copied);
-int ps3_lpm_copy_tb_to_user(unsigned long offset, void __user *buf,
-	unsigned long count, unsigned long *bytes_copied);
-void ps3_set_bookmark(u64 bookmark);
-void ps3_set_pm_bookmark(u64 tag, u64 incident, u64 th_id);
-int ps3_set_signal(u64 rtas_signal_group, u8 signal_bit, u16 sub_unit,
-	u8 bus_word);
-
-u32 ps3_read_phys_ctr(u32 cpu, u32 phys_ctr);
-void ps3_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val);
-u32 ps3_read_ctr(u32 cpu, u32 ctr);
-void ps3_write_ctr(u32 cpu, u32 ctr, u32 val);
-
-u32 ps3_read_pm07_control(u32 cpu, u32 ctr);
-void ps3_write_pm07_control(u32 cpu, u32 ctr, u32 val);
-u32 ps3_read_pm(u32 cpu, enum pm_reg_name reg);
-void ps3_write_pm(u32 cpu, enum pm_reg_name reg, u32 val);
-
-u32 ps3_get_ctr_size(u32 cpu, u32 phys_ctr);
-void ps3_set_ctr_size(u32 cpu, u32 phys_ctr, u32 ctr_size);
-
-void ps3_enable_pm(u32 cpu);
-void ps3_disable_pm(u32 cpu);
-void ps3_enable_pm_interrupts(u32 cpu, u32 thread, u32 mask);
-void ps3_disable_pm_interrupts(u32 cpu);
-
-u32 ps3_get_and_clear_pm_interrupts(u32 cpu);
-void ps3_sync_irq(int node);
-u32 ps3_get_hw_thread_id(int cpu);
-u64 ps3_get_spe_id(void *arg);
-
-#endif
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/ps3av.h b/ANDROID_3.4.5/arch/powerpc/include/asm/ps3av.h
deleted file mode 100644
index 0427b0b5..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/ps3av.h
+++ /dev/null
@@ -1,743 +0,0 @@
-/*
- *  PS3 AV backend support.
- *
- *  Copyright (C) 2007 Sony Computer Entertainment Inc.
- *  Copyright 2007 Sony Corp.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; version 2 of the License.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#ifndef _ASM_POWERPC_PS3AV_H_
-#define _ASM_POWERPC_PS3AV_H_
-
-/** command for ioctl() **/
-#define PS3AV_VERSION 0x205	/* version of ps3av command */
-
-#define PS3AV_CID_AV_INIT              0x00000001
-#define PS3AV_CID_AV_FIN               0x00000002
-#define PS3AV_CID_AV_GET_HW_CONF       0x00000003
-#define PS3AV_CID_AV_GET_MONITOR_INFO  0x00000004
-#define PS3AV_CID_AV_ENABLE_EVENT      0x00000006
-#define PS3AV_CID_AV_DISABLE_EVENT     0x00000007
-#define PS3AV_CID_AV_TV_MUTE           0x0000000a
-
-#define PS3AV_CID_AV_VIDEO_CS          0x00010001
-#define PS3AV_CID_AV_VIDEO_MUTE        0x00010002
-#define PS3AV_CID_AV_VIDEO_DISABLE_SIG 0x00010003
-#define PS3AV_CID_AV_AUDIO_PARAM       0x00020001
-#define PS3AV_CID_AV_AUDIO_MUTE        0x00020002
-#define PS3AV_CID_AV_HDMI_MODE         0x00040001
-
-#define PS3AV_CID_VIDEO_INIT           0x01000001
-#define PS3AV_CID_VIDEO_MODE           0x01000002
-#define PS3AV_CID_VIDEO_FORMAT         0x01000004
-#define PS3AV_CID_VIDEO_PITCH          0x01000005
-
-#define PS3AV_CID_AUDIO_INIT           0x02000001
-#define PS3AV_CID_AUDIO_MODE           0x02000002
-#define PS3AV_CID_AUDIO_MUTE           0x02000003
-#define PS3AV_CID_AUDIO_ACTIVE         0x02000004
-#define PS3AV_CID_AUDIO_INACTIVE       0x02000005
-#define PS3AV_CID_AUDIO_SPDIF_BIT      0x02000006
-#define PS3AV_CID_AUDIO_CTRL           0x02000007
-
-#define PS3AV_CID_EVENT_UNPLUGGED      0x10000001
-#define PS3AV_CID_EVENT_PLUGGED        0x10000002
-#define PS3AV_CID_EVENT_HDCP_DONE      0x10000003
-#define PS3AV_CID_EVENT_HDCP_FAIL      0x10000004
-#define PS3AV_CID_EVENT_HDCP_AUTH      0x10000005
-#define PS3AV_CID_EVENT_HDCP_ERROR     0x10000006
-
-#define PS3AV_CID_AVB_PARAM            0x04000001
-
-/* max backend ports */
-#define PS3AV_HDMI_MAX                 2	/* HDMI_0 HDMI_1 */
-#define PS3AV_AVMULTI_MAX              1	/* AVMULTI_0 */
-#define PS3AV_AV_PORT_MAX              (PS3AV_HDMI_MAX + PS3AV_AVMULTI_MAX)
-#define PS3AV_OPT_PORT_MAX             1	/* SPDIF0 */
-#define PS3AV_HEAD_MAX                 2	/* HEAD_A HEAD_B */
-
-/* num of pkt for PS3AV_CID_AVB_PARAM */
-#define PS3AV_AVB_NUM_VIDEO            PS3AV_HEAD_MAX
-#define PS3AV_AVB_NUM_AUDIO            0	/* not supported */
-#define PS3AV_AVB_NUM_AV_VIDEO         PS3AV_AV_PORT_MAX
-#define PS3AV_AVB_NUM_AV_AUDIO         PS3AV_HDMI_MAX
-
-#define PS3AV_MUTE_PORT_MAX            1	/* num of ports in mute pkt */
-
-/* event_bit */
-#define PS3AV_CMD_EVENT_BIT_UNPLUGGED			(1 << 0)
-#define PS3AV_CMD_EVENT_BIT_PLUGGED			(1 << 1)
-#define PS3AV_CMD_EVENT_BIT_HDCP_DONE			(1 << 2)
-#define PS3AV_CMD_EVENT_BIT_HDCP_FAIL			(1 << 3)
-#define PS3AV_CMD_EVENT_BIT_HDCP_REAUTH			(1 << 4)
-#define PS3AV_CMD_EVENT_BIT_HDCP_TOPOLOGY		(1 << 5)
-
-/* common params */
-/* mute */
-#define PS3AV_CMD_MUTE_OFF				0x0000
-#define PS3AV_CMD_MUTE_ON				0x0001
-/* avport */
-#define PS3AV_CMD_AVPORT_HDMI_0				0x0000
-#define PS3AV_CMD_AVPORT_HDMI_1				0x0001
-#define PS3AV_CMD_AVPORT_AVMULTI_0			0x0010
-#define PS3AV_CMD_AVPORT_SPDIF_0			0x0020
-#define PS3AV_CMD_AVPORT_SPDIF_1			0x0021
-
-/* for av backend */
-/* av_mclk */
-#define PS3AV_CMD_AV_MCLK_128				0x0000
-#define PS3AV_CMD_AV_MCLK_256				0x0001
-#define PS3AV_CMD_AV_MCLK_512				0x0003
-/* av_inputlen */
-#define PS3AV_CMD_AV_INPUTLEN_16			0x02
-#define PS3AV_CMD_AV_INPUTLEN_20			0x0a
-#define PS3AV_CMD_AV_INPUTLEN_24			0x0b
-/* alayout */
-#define PS3AV_CMD_AV_LAYOUT_32				(1 << 0)
-#define PS3AV_CMD_AV_LAYOUT_44				(1 << 1)
-#define PS3AV_CMD_AV_LAYOUT_48				(1 << 2)
-#define PS3AV_CMD_AV_LAYOUT_88				(1 << 3)
-#define PS3AV_CMD_AV_LAYOUT_96				(1 << 4)
-#define PS3AV_CMD_AV_LAYOUT_176				(1 << 5)
-#define PS3AV_CMD_AV_LAYOUT_192				(1 << 6)
-/* hdmi_mode */
-#define PS3AV_CMD_AV_HDMI_MODE_NORMAL			0xff
-#define PS3AV_CMD_AV_HDMI_HDCP_OFF			0x01
-#define PS3AV_CMD_AV_HDMI_EDID_PASS			0x80
-#define PS3AV_CMD_AV_HDMI_DVI				0x40
-
-/* for video module */
-/* video_head */
-#define PS3AV_CMD_VIDEO_HEAD_A				0x0000
-#define PS3AV_CMD_VIDEO_HEAD_B				0x0001
-/* video_cs_out video_cs_in */
-#define PS3AV_CMD_VIDEO_CS_NONE				0x0000
-#define PS3AV_CMD_VIDEO_CS_RGB_8			0x0001
-#define PS3AV_CMD_VIDEO_CS_YUV444_8			0x0002
-#define PS3AV_CMD_VIDEO_CS_YUV422_8			0x0003
-#define PS3AV_CMD_VIDEO_CS_XVYCC_8			0x0004
-#define PS3AV_CMD_VIDEO_CS_RGB_10			0x0005
-#define PS3AV_CMD_VIDEO_CS_YUV444_10			0x0006
-#define PS3AV_CMD_VIDEO_CS_YUV422_10			0x0007
-#define PS3AV_CMD_VIDEO_CS_XVYCC_10			0x0008
-#define PS3AV_CMD_VIDEO_CS_RGB_12			0x0009
-#define PS3AV_CMD_VIDEO_CS_YUV444_12			0x000a
-#define PS3AV_CMD_VIDEO_CS_YUV422_12			0x000b
-#define PS3AV_CMD_VIDEO_CS_XVYCC_12			0x000c
-/* video_vid */
-#define PS3AV_CMD_VIDEO_VID_NONE			0x0000
-#define PS3AV_CMD_VIDEO_VID_480I			0x0001
-#define PS3AV_CMD_VIDEO_VID_576I			0x0003
-#define PS3AV_CMD_VIDEO_VID_480P			0x0005
-#define PS3AV_CMD_VIDEO_VID_576P			0x0006
-#define PS3AV_CMD_VIDEO_VID_1080I_60HZ			0x0007
-#define PS3AV_CMD_VIDEO_VID_1080I_50HZ			0x0008
-#define PS3AV_CMD_VIDEO_VID_720P_60HZ			0x0009
-#define PS3AV_CMD_VIDEO_VID_720P_50HZ			0x000a
-#define PS3AV_CMD_VIDEO_VID_1080P_60HZ			0x000b
-#define PS3AV_CMD_VIDEO_VID_1080P_50HZ			0x000c
-#define PS3AV_CMD_VIDEO_VID_WXGA			0x000d
-#define PS3AV_CMD_VIDEO_VID_SXGA			0x000e
-#define PS3AV_CMD_VIDEO_VID_WUXGA			0x000f
-#define PS3AV_CMD_VIDEO_VID_480I_A			0x0010
-/* video_format */
-#define PS3AV_CMD_VIDEO_FORMAT_BLACK			0x0000
-#define PS3AV_CMD_VIDEO_FORMAT_ARGB_8BIT		0x0007
-/* video_order */
-#define PS3AV_CMD_VIDEO_ORDER_RGB			0x0000
-#define PS3AV_CMD_VIDEO_ORDER_BGR			0x0001
-/* video_fmt */
-#define PS3AV_CMD_VIDEO_FMT_X8R8G8B8			0x0000
-/* video_out_format */
-#define PS3AV_CMD_VIDEO_OUT_FORMAT_RGB_12BIT		0x0000
-/* video_cl_cnv */
-#define PS3AV_CMD_VIDEO_CL_CNV_ENABLE_LUT		0x0000
-#define PS3AV_CMD_VIDEO_CL_CNV_DISABLE_LUT		0x0010
-/* video_sync */
-#define PS3AV_CMD_VIDEO_SYNC_VSYNC			0x0001
-#define PS3AV_CMD_VIDEO_SYNC_CSYNC			0x0004
-#define PS3AV_CMD_VIDEO_SYNC_HSYNC			0x0010
-
-/* for audio module */
-/* num_of_ch */
-#define PS3AV_CMD_AUDIO_NUM_OF_CH_2			0x0000
-#define PS3AV_CMD_AUDIO_NUM_OF_CH_3			0x0001
-#define PS3AV_CMD_AUDIO_NUM_OF_CH_4			0x0002
-#define PS3AV_CMD_AUDIO_NUM_OF_CH_5			0x0003
-#define PS3AV_CMD_AUDIO_NUM_OF_CH_6			0x0004
-#define PS3AV_CMD_AUDIO_NUM_OF_CH_7			0x0005
-#define PS3AV_CMD_AUDIO_NUM_OF_CH_8			0x0006
-/* audio_fs */
-#define PS3AV_CMD_AUDIO_FS_32K				0x0001
-#define PS3AV_CMD_AUDIO_FS_44K				0x0002
-#define PS3AV_CMD_AUDIO_FS_48K				0x0003
-#define PS3AV_CMD_AUDIO_FS_88K				0x0004
-#define PS3AV_CMD_AUDIO_FS_96K				0x0005
-#define PS3AV_CMD_AUDIO_FS_176K				0x0006
-#define PS3AV_CMD_AUDIO_FS_192K				0x0007
-/* audio_word_bits */
-#define PS3AV_CMD_AUDIO_WORD_BITS_16			0x0001
-#define PS3AV_CMD_AUDIO_WORD_BITS_20			0x0002
-#define PS3AV_CMD_AUDIO_WORD_BITS_24			0x0003
-/* audio_format */
-#define PS3AV_CMD_AUDIO_FORMAT_PCM			0x0001
-#define PS3AV_CMD_AUDIO_FORMAT_BITSTREAM		0x00ff
-/* audio_source */
-#define PS3AV_CMD_AUDIO_SOURCE_SERIAL			0x0000
-#define PS3AV_CMD_AUDIO_SOURCE_SPDIF			0x0001
-/* audio_swap */
-#define PS3AV_CMD_AUDIO_SWAP_0				0x0000
-#define PS3AV_CMD_AUDIO_SWAP_1				0x0000
-/* audio_map */
-#define PS3AV_CMD_AUDIO_MAP_OUTPUT_0			0x0000
-#define PS3AV_CMD_AUDIO_MAP_OUTPUT_1			0x0001
-#define PS3AV_CMD_AUDIO_MAP_OUTPUT_2			0x0002
-#define PS3AV_CMD_AUDIO_MAP_OUTPUT_3			0x0003
-/* audio_layout */
-#define PS3AV_CMD_AUDIO_LAYOUT_2CH			0x0000
-#define PS3AV_CMD_AUDIO_LAYOUT_6CH			0x000b	/* LREClr */
-#define PS3AV_CMD_AUDIO_LAYOUT_8CH			0x001f	/* LREClrXY */
-/* audio_downmix */
-#define PS3AV_CMD_AUDIO_DOWNMIX_PERMITTED		0x0000
-#define PS3AV_CMD_AUDIO_DOWNMIX_PROHIBITED		0x0001
-
-/* audio_port */
-#define PS3AV_CMD_AUDIO_PORT_HDMI_0			( 1 << 0 )
-#define PS3AV_CMD_AUDIO_PORT_HDMI_1			( 1 << 1 )
-#define PS3AV_CMD_AUDIO_PORT_AVMULTI_0			( 1 << 10 )
-#define PS3AV_CMD_AUDIO_PORT_SPDIF_0			( 1 << 20 )
-#define PS3AV_CMD_AUDIO_PORT_SPDIF_1			( 1 << 21 )
-
-/* audio_ctrl_id */
-#define PS3AV_CMD_AUDIO_CTRL_ID_DAC_RESET		0x0000
-#define PS3AV_CMD_AUDIO_CTRL_ID_DAC_DE_EMPHASIS		0x0001
-#define PS3AV_CMD_AUDIO_CTRL_ID_AVCLK			0x0002
-/* audio_ctrl_data[0] reset */
-#define PS3AV_CMD_AUDIO_CTRL_RESET_NEGATE		0x0000
-#define PS3AV_CMD_AUDIO_CTRL_RESET_ASSERT		0x0001
-/* audio_ctrl_data[0] de-emphasis */
-#define PS3AV_CMD_AUDIO_CTRL_DE_EMPHASIS_OFF		0x0000
-#define PS3AV_CMD_AUDIO_CTRL_DE_EMPHASIS_ON		0x0001
-/* audio_ctrl_data[0] avclk */
-#define PS3AV_CMD_AUDIO_CTRL_AVCLK_22			0x0000
-#define PS3AV_CMD_AUDIO_CTRL_AVCLK_18			0x0001
-
-/* av_vid */
-/* do not use these params directly, use vid_video2av */
-#define PS3AV_CMD_AV_VID_480I				0x0000
-#define PS3AV_CMD_AV_VID_480P				0x0001
-#define PS3AV_CMD_AV_VID_720P_60HZ			0x0002
-#define PS3AV_CMD_AV_VID_1080I_60HZ			0x0003
-#define PS3AV_CMD_AV_VID_1080P_60HZ			0x0004
-#define PS3AV_CMD_AV_VID_576I				0x0005
-#define PS3AV_CMD_AV_VID_576P				0x0006
-#define PS3AV_CMD_AV_VID_720P_50HZ			0x0007
-#define PS3AV_CMD_AV_VID_1080I_50HZ			0x0008
-#define PS3AV_CMD_AV_VID_1080P_50HZ			0x0009
-#define PS3AV_CMD_AV_VID_WXGA				0x000a
-#define PS3AV_CMD_AV_VID_SXGA				0x000b
-#define PS3AV_CMD_AV_VID_WUXGA				0x000c
-/* av_cs_out av_cs_in */
-/* use cs_video2av() */
-#define PS3AV_CMD_AV_CS_RGB_8				0x0000
-#define PS3AV_CMD_AV_CS_YUV444_8			0x0001
-#define PS3AV_CMD_AV_CS_YUV422_8			0x0002
-#define PS3AV_CMD_AV_CS_XVYCC_8				0x0003
-#define PS3AV_CMD_AV_CS_RGB_10				0x0004
-#define PS3AV_CMD_AV_CS_YUV444_10			0x0005
-#define PS3AV_CMD_AV_CS_YUV422_10			0x0006
-#define PS3AV_CMD_AV_CS_XVYCC_10			0x0007
-#define PS3AV_CMD_AV_CS_RGB_12				0x0008
-#define PS3AV_CMD_AV_CS_YUV444_12			0x0009
-#define PS3AV_CMD_AV_CS_YUV422_12			0x000a
-#define PS3AV_CMD_AV_CS_XVYCC_12			0x000b
-#define PS3AV_CMD_AV_CS_8				0x0000
-#define PS3AV_CMD_AV_CS_10				0x0001
-#define PS3AV_CMD_AV_CS_12				0x0002
-/* dither */
-#define PS3AV_CMD_AV_DITHER_OFF				0x0000
-#define PS3AV_CMD_AV_DITHER_ON				0x0001
-#define PS3AV_CMD_AV_DITHER_8BIT			0x0000
-#define PS3AV_CMD_AV_DITHER_10BIT			0x0002
-#define PS3AV_CMD_AV_DITHER_12BIT			0x0004
-/* super_white */
-#define PS3AV_CMD_AV_SUPER_WHITE_OFF			0x0000
-#define PS3AV_CMD_AV_SUPER_WHITE_ON			0x0001
-/* aspect */
-#define PS3AV_CMD_AV_ASPECT_16_9			0x0000
-#define PS3AV_CMD_AV_ASPECT_4_3				0x0001
-/* video_cs_cnv() */
-#define PS3AV_CMD_VIDEO_CS_RGB				0x0001
-#define PS3AV_CMD_VIDEO_CS_YUV422			0x0002
-#define PS3AV_CMD_VIDEO_CS_YUV444			0x0003
-
-/* for broadcast automode */
-#define PS3AV_RESBIT_720x480P			0x0003	/* 0x0001 | 0x0002 */
-#define PS3AV_RESBIT_720x576P			0x0003	/* 0x0001 | 0x0002 */
-#define PS3AV_RESBIT_1280x720P			0x0004
-#define PS3AV_RESBIT_1920x1080I			0x0008
-#define PS3AV_RESBIT_1920x1080P			0x4000
-#define PS3AV_RES_MASK_60			(PS3AV_RESBIT_720x480P \
-						| PS3AV_RESBIT_1280x720P \
-						| PS3AV_RESBIT_1920x1080I \
-						| PS3AV_RESBIT_1920x1080P)
-#define PS3AV_RES_MASK_50			(PS3AV_RESBIT_720x576P \
-						| PS3AV_RESBIT_1280x720P \
-						| PS3AV_RESBIT_1920x1080I \
-						| PS3AV_RESBIT_1920x1080P)
-
-/* for VESA automode */
-#define PS3AV_RESBIT_VGA			0x0001
-#define PS3AV_RESBIT_WXGA			0x0002
-#define PS3AV_RESBIT_SXGA			0x0004
-#define PS3AV_RESBIT_WUXGA			0x0008
-#define PS3AV_RES_MASK_VESA			(PS3AV_RESBIT_WXGA |\
-						 PS3AV_RESBIT_SXGA |\
-						 PS3AV_RESBIT_WUXGA)
-
-#define PS3AV_MONITOR_TYPE_HDMI			1	/* HDMI */
-#define PS3AV_MONITOR_TYPE_DVI			2	/* DVI */
-
-
-/* for video mode */
-enum ps3av_mode_num {
-	PS3AV_MODE_AUTO				= 0,
-	PS3AV_MODE_480I				= 1,
-	PS3AV_MODE_480P				= 2,
-	PS3AV_MODE_720P60			= 3,
-	PS3AV_MODE_1080I60			= 4,
-	PS3AV_MODE_1080P60			= 5,
-	PS3AV_MODE_576I				= 6,
-	PS3AV_MODE_576P				= 7,
-	PS3AV_MODE_720P50			= 8,
-	PS3AV_MODE_1080I50			= 9,
-	PS3AV_MODE_1080P50			= 10,
-	PS3AV_MODE_WXGA				= 11,
-	PS3AV_MODE_SXGA				= 12,
-	PS3AV_MODE_WUXGA			= 13,
-};
-
-#define PS3AV_MODE_MASK				0x000F
-#define PS3AV_MODE_HDCP_OFF			0x1000	/* Retail PS3 product doesn't support this */
-#define PS3AV_MODE_DITHER			0x0800
-#define PS3AV_MODE_COLOR			0x0400
-#define PS3AV_MODE_WHITE			0x0200
-#define PS3AV_MODE_FULL				0x0080
-#define PS3AV_MODE_DVI				0x0040
-#define PS3AV_MODE_RGB				0x0020
-
-
-#define PS3AV_DEFAULT_HDMI_MODE_ID_REG_60	PS3AV_MODE_480P
-#define PS3AV_DEFAULT_AVMULTI_MODE_ID_REG_60	PS3AV_MODE_480I
-#define PS3AV_DEFAULT_HDMI_MODE_ID_REG_50	PS3AV_MODE_576P
-#define PS3AV_DEFAULT_AVMULTI_MODE_ID_REG_50	PS3AV_MODE_576I
-
-#define PS3AV_REGION_60				0x01
-#define PS3AV_REGION_50				0x02
-#define PS3AV_REGION_RGB			0x10
-
-#define get_status(buf)				(((__u32 *)buf)[2])
-#define PS3AV_HDR_SIZE				4	/* version + size */
-
-
-/** command packet structure **/
-struct ps3av_send_hdr {
-	u16 version;
-	u16 size;		/* size of command packet */
-	u32 cid;		/* command id */
-};
-
-struct ps3av_reply_hdr {
-	u16 version;
-	u16 size;
-	u32 cid;
-	u32 status;
-};
-
-/* backend: initialization */
-struct ps3av_pkt_av_init {
-	struct ps3av_send_hdr send_hdr;
-	u32 event_bit;
-};
-
-/* backend: finalize */
-struct ps3av_pkt_av_fin {
-	struct ps3av_send_hdr send_hdr;
-	/* recv */
-	u32 reserved;
-};
-
-/* backend: get port */
-struct ps3av_pkt_av_get_hw_conf {
-	struct ps3av_send_hdr send_hdr;
-	/* recv */
-	u32 status;
-	u16 num_of_hdmi;	/* out: number of hdmi */
-	u16 num_of_avmulti;	/* out: number of avmulti */
-	u16 num_of_spdif;	/* out: number of hdmi */
-	u16 reserved;
-};
-
-/* backend: get monitor info */
-struct ps3av_info_resolution {
-	u32 res_bits;
-	u32 native;
-};
-
-struct ps3av_info_cs {
-	u8 rgb;
-	u8 yuv444;
-	u8 yuv422;
-	u8 reserved;
-};
-
-struct ps3av_info_color {
-	u16 red_x;
-	u16 red_y;
-	u16 green_x;
-	u16 green_y;
-	u16 blue_x;
-	u16 blue_y;
-	u16 white_x;
-	u16 white_y;
-	u32 gamma;
-};
-
-struct ps3av_info_audio {
-	u8 type;
-	u8 max_num_of_ch;
-	u8 fs;
-	u8 sbit;
-};
-
-struct ps3av_info_monitor {
-	u8 avport;
-	u8 monitor_id[10];
-	u8 monitor_type;
-	u8 monitor_name[16];
-	struct ps3av_info_resolution res_60;
-	struct ps3av_info_resolution res_50;
-	struct ps3av_info_resolution res_other;
-	struct ps3av_info_resolution res_vesa;
-	struct ps3av_info_cs cs;
-	struct ps3av_info_color color;
-	u8 supported_ai;
-	u8 speaker_info;
-	u8 num_of_audio_block;
-	struct ps3av_info_audio audio[0];	/* 0 or more audio blocks */
-	u8 reserved[169];
-} __attribute__ ((packed));
-
-struct ps3av_pkt_av_get_monitor_info {
-	struct ps3av_send_hdr send_hdr;
-	u16 avport;		/* in: avport */
-	u16 reserved;
-	/* recv */
-	struct ps3av_info_monitor info;	/* out: monitor info */
-};
-
-/* backend: enable/disable event */
-struct ps3av_pkt_av_event {
-	struct ps3av_send_hdr send_hdr;
-	u32 event_bit;		/* in */
-};
-
-/* backend: video cs param */
-struct ps3av_pkt_av_video_cs {
-	struct ps3av_send_hdr send_hdr;
-	u16 avport;		/* in: avport */
-	u16 av_vid;		/* in: video resolution */
-	u16 av_cs_out;		/* in: output color space */
-	u16 av_cs_in;		/* in: input color space */
-	u8 dither;		/* in: dither bit length */
-	u8 bitlen_out;		/* in: bit length */
-	u8 super_white;		/* in: super white */
-	u8 aspect;		/* in: aspect ratio */
-};
-
-/* backend: video mute */
-struct ps3av_av_mute {
-	u16 avport;		/* in: avport */
-	u16 mute;		/* in: mute on/off */
-};
-
-struct ps3av_pkt_av_video_mute {
-	struct ps3av_send_hdr send_hdr;
-	struct ps3av_av_mute mute[PS3AV_MUTE_PORT_MAX];
-};
-
-/* backend: video disable signal */
-struct ps3av_pkt_av_video_disable_sig {
-	struct ps3av_send_hdr send_hdr;
-	u16 avport;		/* in: avport */
-	u16 reserved;
-};
-
-/* backend: audio param */
-struct ps3av_audio_info_frame {
-	struct pb1_bit {
-		u8 ct:4;
-		u8 rsv:1;
-		u8 cc:3;
-	} pb1;
-	struct pb2_bit {
-		u8 rsv:3;
-		u8 sf:3;
-		u8 ss:2;
-	} pb2;
-	u8 pb3;
-	u8 pb4;
-	struct pb5_bit {
-		u8 dm:1;
-		u8 lsv:4;
-		u8 rsv:3;
-	} pb5;
-};
-
-struct ps3av_pkt_av_audio_param {
-	struct ps3av_send_hdr send_hdr;
-	u16 avport;		/* in: avport */
-	u16 reserved;
-	u8 mclk;		/* in: audio mclk */
-	u8 ns[3];		/* in: audio ns val */
-	u8 enable;		/* in: audio enable */
-	u8 swaplr;		/* in: audio swap */
-	u8 fifomap;		/* in: audio fifomap */
-	u8 inputctrl;		/* in: audio input ctrl */
-	u8 inputlen;		/* in: sample bit size */
-	u8 layout;		/* in: speaker layout param */
-	struct ps3av_audio_info_frame info;	/* in: info */
-	u8 chstat[5];		/* in: ch stat */
-};
-
-/* backend: audio_mute */
-struct ps3av_pkt_av_audio_mute {
-	struct ps3av_send_hdr send_hdr;
-	struct ps3av_av_mute mute[PS3AV_MUTE_PORT_MAX];
-};
-
-/* backend: hdmi_mode */
-struct ps3av_pkt_av_hdmi_mode {
-	struct ps3av_send_hdr send_hdr;
-	u8 mode;		/* in: hdmi_mode */
-	u8 reserved0;
-	u8 reserved1;
-	u8 reserved2;
-};
-
-/* backend: tv_mute */
-struct ps3av_pkt_av_tv_mute {
-	struct ps3av_send_hdr send_hdr;
-	u16 avport;		/* in: avport HDMI only */
-	u16 mute;		/* in: mute */
-};
-
-/* video: initialize */
-struct ps3av_pkt_video_init {
-	struct ps3av_send_hdr send_hdr;
-	/* recv */
-	u32 reserved;
-};
-
-/* video: mode setting */
-struct ps3av_pkt_video_mode {
-	struct ps3av_send_hdr send_hdr;
-	u32 video_head;		/* in: head */
-	u32 reserved;
-	u32 video_vid;		/* in: video resolution */
-	u16 reserved1;
-	u16 width;		/* in: width in pixel */
-	u16 reserved2;
-	u16 height;		/* in: height in pixel */
-	u32 pitch;		/* in: line size in byte */
-	u32 video_out_format;	/* in: out format */
-	u32 video_format;	/* in: input frame buffer format */
-	u8 reserved3;
-	u8 video_cl_cnv;	/* in: color conversion */
-	u16 video_order;	/* in: input RGB order */
-	u32 reserved4;
-};
-
-/* video: format */
-struct ps3av_pkt_video_format {
-	struct ps3av_send_hdr send_hdr;
-	u32 video_head;		/* in: head */
-	u32 video_format;	/* in: frame buffer format */
-	u8 reserved;
-	u8 video_cl_cnv;	/* in: color conversion */
-	u16 video_order;	/* in: input RGB order */
-};
-
-/* video: pitch */
-struct ps3av_pkt_video_pitch {
-	u16 version;
-	u16 size;		/* size of command packet */
-	u32 cid;		/* command id */
-	u32 video_head;		/* in: head */
-	u32 pitch;		/* in: line size in byte */
-};
-
-/* audio: initialize */
-struct ps3av_pkt_audio_init {
-	struct ps3av_send_hdr send_hdr;
-	/* recv */
-	u32 reserved;
-};
-
-/* audio: mode setting */
-struct ps3av_pkt_audio_mode {
-	struct ps3av_send_hdr send_hdr;
-	u8 avport;		/* in: avport */
-	u8 reserved0[3];
-	u32 mask;		/* in: mask */
-	u32 audio_num_of_ch;	/* in: number of ch */
-	u32 audio_fs;		/* in: sampling freq */
-	u32 audio_word_bits;	/* in: sample bit size */
-	u32 audio_format;	/* in: audio output format */
-	u32 audio_source;	/* in: audio source */
-	u8 audio_enable[4];	/* in: audio enable */
-	u8 audio_swap[4];	/* in: audio swap */
-	u8 audio_map[4];	/* in: audio map */
-	u32 audio_layout;	/* in: speaker layout */
-	u32 audio_downmix;	/* in: audio downmix permission */
-	u32 audio_downmix_level;
-	u8 audio_cs_info[8];	/* in: IEC channel status */
-};
-
-/* audio: mute */
-struct ps3av_audio_mute {
-	u8 avport;		/* in: opt_port optical */
-	u8 reserved[3];
-	u32 mute;		/* in: mute */
-};
-
-struct ps3av_pkt_audio_mute {
-	struct ps3av_send_hdr send_hdr;
-	struct ps3av_audio_mute mute[PS3AV_OPT_PORT_MAX];
-};
-
-/* audio: active/inactive */
-struct ps3av_pkt_audio_active {
-	struct ps3av_send_hdr send_hdr;
-	u32 audio_port;		/* in: audio active/inactive port */
-};
-
-/* audio: SPDIF user bit */
-struct ps3av_pkt_audio_spdif_bit {
-	u16 version;
-	u16 size;		/* size of command packet */
-	u32 cid;		/* command id */
-	u8 avport;		/* in: avport SPDIF only */
-	u8 reserved[3];
-	u32 audio_port;		/* in: SPDIF only */
-	u32 spdif_bit_data[12];	/* in: user bit data */
-};
-
-/* audio: audio control */
-struct ps3av_pkt_audio_ctrl {
-	u16 version;
-	u16 size;		/* size of command packet */
-	u32 cid;		/* command id */
-	u32 audio_ctrl_id;	/* in: control id */
-	u32 audio_ctrl_data[4];	/* in: control data */
-};
-
-/* avb:param */
-#define PS3AV_PKT_AVB_PARAM_MAX_BUF_SIZE	\
-	(PS3AV_AVB_NUM_VIDEO*sizeof(struct ps3av_pkt_video_mode) + \
-	 PS3AV_AVB_NUM_AUDIO*sizeof(struct ps3av_pkt_audio_mode) + \
-	 PS3AV_AVB_NUM_AV_VIDEO*sizeof(struct ps3av_pkt_av_video_cs) + \
-	 PS3AV_AVB_NUM_AV_AUDIO*sizeof(struct ps3av_pkt_av_audio_param))
-
-struct ps3av_pkt_avb_param {
-	struct ps3av_send_hdr send_hdr;
-	u16 num_of_video_pkt;
-	u16 num_of_audio_pkt;
-	u16 num_of_av_video_pkt;
-	u16 num_of_av_audio_pkt;
-	/*
-	 * The actual buffer layout depends on the fields above:
-	 *
-	 * struct ps3av_pkt_video_mode video[num_of_video_pkt];
-	 * struct ps3av_pkt_audio_mode audio[num_of_audio_pkt];
-	 * struct ps3av_pkt_av_video_cs av_video[num_of_av_video_pkt];
-	 * struct ps3av_pkt_av_audio_param av_audio[num_of_av_audio_pkt];
-	 */
-	u8 buf[PS3AV_PKT_AVB_PARAM_MAX_BUF_SIZE];
-};
-
-/* channel status */
-extern u8 ps3av_mode_cs_info[];
-
-/** command status **/
-#define PS3AV_STATUS_SUCCESS			0x0000	/* success */
-#define PS3AV_STATUS_RECEIVE_VUART_ERROR	0x0001	/* receive vuart error */
-#define PS3AV_STATUS_SYSCON_COMMUNICATE_FAIL	0x0002	/* syscon communication error */
-#define PS3AV_STATUS_INVALID_COMMAND		0x0003	/* obsolete invalid CID */
-#define PS3AV_STATUS_INVALID_PORT		0x0004	/* invalid port number */
-#define PS3AV_STATUS_INVALID_VID		0x0005	/* invalid video format */
-#define PS3AV_STATUS_INVALID_COLOR_SPACE	0x0006	/* invalid video colose space */
-#define PS3AV_STATUS_INVALID_FS			0x0007	/* invalid audio sampling freq */
-#define PS3AV_STATUS_INVALID_AUDIO_CH		0x0008	/* invalid audio channel number */
-#define PS3AV_STATUS_UNSUPPORTED_VERSION	0x0009	/* version mismatch  */
-#define PS3AV_STATUS_INVALID_SAMPLE_SIZE	0x000a	/* invalid audio sample bit size */
-#define PS3AV_STATUS_FAILURE			0x000b	/* other failures */
-#define PS3AV_STATUS_UNSUPPORTED_COMMAND	0x000c	/* unsupported cid */
-#define PS3AV_STATUS_BUFFER_OVERFLOW		0x000d	/* write buffer overflow */
-#define PS3AV_STATUS_INVALID_VIDEO_PARAM	0x000e	/* invalid video param */
-#define PS3AV_STATUS_NO_SEL			0x000f	/* not exist selector */
-#define PS3AV_STATUS_INVALID_AV_PARAM		0x0010	/* invalid backend param */
-#define PS3AV_STATUS_INVALID_AUDIO_PARAM	0x0011	/* invalid audio param */
-#define PS3AV_STATUS_UNSUPPORTED_HDMI_MODE	0x0012	/* unsupported hdmi mode */
-#define PS3AV_STATUS_NO_SYNC_HEAD		0x0013	/* sync head failed */
-
-extern void ps3av_set_hdr(u32, u16, struct ps3av_send_hdr *);
-extern int ps3av_do_pkt(u32, u16, size_t, struct ps3av_send_hdr *);
-
-extern int ps3av_cmd_init(void);
-extern int ps3av_cmd_fin(void);
-extern int ps3av_cmd_av_video_mute(int, u32 *, u32);
-extern int ps3av_cmd_av_video_disable_sig(u32);
-extern int ps3av_cmd_av_tv_mute(u32, u32);
-extern int ps3av_cmd_enable_event(void);
-extern int ps3av_cmd_av_hdmi_mode(u8);
-extern u32 ps3av_cmd_set_av_video_cs(void *, u32, int, int, int, u32);
-extern u32 ps3av_cmd_set_video_mode(void *, u32, int, int, u32);
-extern int ps3av_cmd_video_format_black(u32, u32, u32);
-extern int ps3av_cmd_av_audio_mute(int, u32 *, u32);
-extern u32 ps3av_cmd_set_av_audio_param(void *, u32,
-					const struct ps3av_pkt_audio_mode *,
-					u32);
-extern void ps3av_cmd_set_audio_mode(struct ps3av_pkt_audio_mode *, u32, u32,
-				     u32, u32, u32, u32);
-extern int ps3av_cmd_audio_mode(struct ps3av_pkt_audio_mode *);
-extern int ps3av_cmd_audio_mute(int, u32 *, u32);
-extern int ps3av_cmd_audio_active(int, u32);
-extern int ps3av_cmd_avb_param(struct ps3av_pkt_avb_param *, u32);
-extern int ps3av_cmd_av_get_hw_conf(struct ps3av_pkt_av_get_hw_conf *);
-extern int ps3av_cmd_video_get_monitor_info(struct ps3av_pkt_av_get_monitor_info *,
-					    u32);
-
-extern int ps3av_set_video_mode(int);
-extern int ps3av_set_audio_mode(u32, u32, u32, u32, u32);
-extern int ps3av_get_auto_mode(void);
-extern int ps3av_get_mode(void);
-extern int ps3av_video_mode2res(u32, u32 *, u32 *);
-extern int ps3av_video_mute(int);
-extern int ps3av_audio_mute(int);
-extern int ps3av_audio_mute_analog(int);
-extern int ps3av_dev_open(void);
-extern int ps3av_dev_close(void);
-#endif	/* _ASM_POWERPC_PS3AV_H_ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/ps3fb.h b/ANDROID_3.4.5/arch/powerpc/include/asm/ps3fb.h
deleted file mode 100644
index e7233a84..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/ps3fb.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Copyright (C) 2006 Sony Computer Entertainment Inc.
- * Copyright 2006, 2007 Sony Corporation
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published
- * by the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#ifndef _ASM_POWERPC_PS3FB_H_
-#define _ASM_POWERPC_PS3FB_H_
-
-#include <linux/types.h>
-#include <linux/ioctl.h>
-
-/* ioctl */
-#define PS3FB_IOCTL_SETMODE       _IOW('r',  1, int) /* set video mode */
-#define PS3FB_IOCTL_GETMODE       _IOR('r',  2, int) /* get video mode */
-#define PS3FB_IOCTL_SCREENINFO    _IOR('r',  3, int) /* get screen info */
-#define PS3FB_IOCTL_ON            _IO('r', 4)        /* use IOCTL_FSEL */
-#define PS3FB_IOCTL_OFF           _IO('r', 5)        /* return to normal-flip */
-#define PS3FB_IOCTL_FSEL          _IOW('r', 6, int)  /* blit and flip request */
-
-#ifndef FBIO_WAITFORVSYNC
-#define FBIO_WAITFORVSYNC         _IOW('F', 0x20, __u32) /* wait for vsync */
-#endif
-
-struct ps3fb_ioctl_res {
-	__u32 xres; /* frame buffer x_size */
-	__u32 yres; /* frame buffer y_size */
-	__u32 xoff; /* margine x  */
-	__u32 yoff; /* margine y */
-	__u32 num_frames; /* num of frame buffers */
-};
-
-#endif /* _ASM_POWERPC_PS3FB_H_ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/ps3gpu.h b/ANDROID_3.4.5/arch/powerpc/include/asm/ps3gpu.h
deleted file mode 100644
index b2b89591..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/ps3gpu.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- *  PS3 GPU declarations.
- *
- *  Copyright 2009 Sony Corporation
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; version 2 of the License.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program.
- *  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef _ASM_POWERPC_PS3GPU_H
-#define _ASM_POWERPC_PS3GPU_H
-
-#include <linux/mutex.h>
-
-#include <asm/lv1call.h>
-
-
-#define L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_SYNC	0x101
-#define L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_FLIP	0x102
-
-#define L1GPU_CONTEXT_ATTRIBUTE_FB_SETUP	0x600
-#define L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT		0x601
-#define L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT_SYNC	0x602
-#define L1GPU_CONTEXT_ATTRIBUTE_FB_CLOSE	0x603
-
-#define L1GPU_FB_BLIT_WAIT_FOR_COMPLETION	(1ULL << 32)
-
-#define L1GPU_DISPLAY_SYNC_HSYNC		1
-#define L1GPU_DISPLAY_SYNC_VSYNC		2
-
-
-/* mutex synchronizing GPU accesses and video mode changes */
-extern struct mutex ps3_gpu_mutex;
-
-
-static inline int lv1_gpu_display_sync(u64 context_handle, u64 head,
-				       u64 ddr_offset)
-{
-	return lv1_gpu_context_attribute(context_handle,
-					 L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_SYNC,
-					 head, ddr_offset, 0, 0);
-}
-
-static inline int lv1_gpu_display_flip(u64 context_handle, u64 head,
-				       u64 ddr_offset)
-{
-	return lv1_gpu_context_attribute(context_handle,
-					 L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_FLIP,
-					 head, ddr_offset, 0, 0);
-}
-
-static inline int lv1_gpu_fb_setup(u64 context_handle, u64 xdr_lpar,
-				   u64 xdr_size, u64 ioif_offset)
-{
-	return lv1_gpu_context_attribute(context_handle,
-					 L1GPU_CONTEXT_ATTRIBUTE_FB_SETUP,
-					 xdr_lpar, xdr_size, ioif_offset, 0);
-}
-
-static inline int lv1_gpu_fb_blit(u64 context_handle, u64 ddr_offset,
-				  u64 ioif_offset, u64 sync_width, u64 pitch)
-{
-	return lv1_gpu_context_attribute(context_handle,
-					 L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT,
-					 ddr_offset, ioif_offset, sync_width,
-					 pitch);
-}
-
-static inline int lv1_gpu_fb_close(u64 context_handle)
-{
-	return lv1_gpu_context_attribute(context_handle,
-					 L1GPU_CONTEXT_ATTRIBUTE_FB_CLOSE, 0,
-					 0, 0, 0);
-}
-
-#endif /* _ASM_POWERPC_PS3GPU_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/ps3stor.h b/ANDROID_3.4.5/arch/powerpc/include/asm/ps3stor.h
deleted file mode 100644
index 6fcaf714..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/ps3stor.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * PS3 Storage Devices
- *
- * Copyright (C) 2007 Sony Computer Entertainment Inc.
- * Copyright 2007 Sony Corp.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published
- * by the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#ifndef _ASM_POWERPC_PS3STOR_H_
-#define _ASM_POWERPC_PS3STOR_H_
-
-#include <linux/interrupt.h>
-
-#include <asm/ps3.h>
-
-
-struct ps3_storage_region {
-	unsigned int id;
-	u64 start;
-	u64 size;
-};
-
-struct ps3_storage_device {
-	struct ps3_system_bus_device sbd;
-
-	struct ps3_dma_region dma_region;
-	unsigned int irq;
-	u64 blk_size;
-
-	u64 tag;
-	u64 lv1_status;
-	struct completion done;
-
-	unsigned long bounce_size;
-	void *bounce_buf;
-	u64 bounce_lpar;
-	dma_addr_t bounce_dma;
-
-	unsigned int num_regions;
-	unsigned long accessible_regions;
-	unsigned int region_idx;		/* first accessible region */
-	struct ps3_storage_region regions[0];	/* Must be last */
-};
-
-static inline struct ps3_storage_device *to_ps3_storage_device(struct device *dev)
-{
-	return container_of(dev, struct ps3_storage_device, sbd.core);
-}
-
-extern int ps3stor_setup(struct ps3_storage_device *dev,
-			 irq_handler_t handler);
-extern void ps3stor_teardown(struct ps3_storage_device *dev);
-extern u64 ps3stor_read_write_sectors(struct ps3_storage_device *dev, u64 lpar,
-				      u64 start_sector, u64 sectors,
-				      int write);
-extern u64 ps3stor_send_command(struct ps3_storage_device *dev, u64 cmd,
-				u64 arg1, u64 arg2, u64 arg3, u64 arg4);
-
-#endif /* _ASM_POWERPC_PS3STOR_H_ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/pte-40x.h b/ANDROID_3.4.5/arch/powerpc/include/asm/pte-40x.h
deleted file mode 100644
index ec0b0b0d..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/pte-40x.h
+++ /dev/null
@@ -1,65 +0,0 @@
-#ifndef _ASM_POWERPC_PTE_40x_H
-#define _ASM_POWERPC_PTE_40x_H
-#ifdef __KERNEL__
-
-/*
- * At present, all PowerPC 400-class processors share a similar TLB
- * architecture. The instruction and data sides share a unified,
- * 64-entry, fully-associative TLB which is maintained totally under
- * software control. In addition, the instruction side has a
- * hardware-managed, 4-entry, fully-associative TLB which serves as a
- * first level to the shared TLB. These two TLBs are known as the UTLB
- * and ITLB, respectively (see "mmu.h" for definitions).
- *
- * There are several potential gotchas here.  The 40x hardware TLBLO
- * field looks like this:
- *
- * 0  1  2  3  4  ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31
- * RPN.....................  0  0 EX WR ZSEL.......  W  I  M  G
- *
- * Where possible we make the Linux PTE bits match up with this
- *
- * - bits 20 and 21 must be cleared, because we use 4k pages (40x can
- *   support down to 1k pages), this is done in the TLBMiss exception
- *   handler.
- * - We use only zones 0 (for kernel pages) and 1 (for user pages)
- *   of the 16 available.  Bit 24-26 of the TLB are cleared in the TLB
- *   miss handler.  Bit 27 is PAGE_USER, thus selecting the correct
- *   zone.
- * - PRESENT *must* be in the bottom two bits because swap cache
- *   entries use the top 30 bits.  Because 40x doesn't support SMP
- *   anyway, M is irrelevant so we borrow it for PAGE_PRESENT.  Bit 30
- *   is cleared in the TLB miss handler before the TLB entry is loaded.
- * - All other bits of the PTE are loaded into TLBLO without
- *   modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for
- *   software PTE bits.  We actually use use bits 21, 24, 25, and
- *   30 respectively for the software bits: ACCESSED, DIRTY, RW, and
- *   PRESENT.
- */
-
-#define	_PAGE_GUARDED	0x001	/* G: page is guarded from prefetch */
-#define _PAGE_FILE	0x001	/* when !present: nonlinear file mapping */
-#define _PAGE_PRESENT	0x002	/* software: PTE contains a translation */
-#define	_PAGE_NO_CACHE	0x004	/* I: caching is inhibited */
-#define	_PAGE_WRITETHRU	0x008	/* W: caching is write-through */
-#define	_PAGE_USER	0x010	/* matches one of the zone permission bits */
-#define	_PAGE_SPECIAL	0x020	/* software: Special page */
-#define	_PAGE_RW	0x040	/* software: Writes permitted */
-#define	_PAGE_DIRTY	0x080	/* software: dirty page */
-#define _PAGE_HWWRITE	0x100	/* hardware: Dirty & RW, set in exception */
-#define _PAGE_EXEC	0x200	/* hardware: EX permission */
-#define _PAGE_ACCESSED	0x400	/* software: R: page referenced */
-
-#define _PMD_PRESENT	0x400	/* PMD points to page of PTEs */
-#define _PMD_BAD	0x802
-#define _PMD_SIZE	0x0e0	/* size field, != 0 for large-page PMD entry */
-#define _PMD_SIZE_4M	0x0c0
-#define _PMD_SIZE_16M	0x0e0
-
-#define PMD_PAGE_SIZE(pmdval)	(1024 << (((pmdval) & _PMD_SIZE) >> 4))
-
-/* Until my rework is finished, 40x still needs atomic PTE updates */
-#define PTE_ATOMIC_UPDATES	1
-
-#endif /* __KERNEL__ */
-#endif /*  _ASM_POWERPC_PTE_40x_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/pte-44x.h b/ANDROID_3.4.5/arch/powerpc/include/asm/pte-44x.h
deleted file mode 100644
index 4192b9ba..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/pte-44x.h
+++ /dev/null
@@ -1,102 +0,0 @@
-#ifndef _ASM_POWERPC_PTE_44x_H
-#define _ASM_POWERPC_PTE_44x_H
-#ifdef __KERNEL__
-
-/*
- * Definitions for PPC440
- *
- * Because of the 3 word TLB entries to support 36-bit addressing,
- * the attribute are difficult to map in such a fashion that they
- * are easily loaded during exception processing.  I decided to
- * organize the entry so the ERPN is the only portion in the
- * upper word of the PTE and the attribute bits below are packed
- * in as sensibly as they can be in the area below a 4KB page size
- * oriented RPN.  This at least makes it easy to load the RPN and
- * ERPN fields in the TLB. -Matt
- *
- * This isn't entirely true anymore, at least some bits are now
- * easier to move into the TLB from the PTE. -BenH.
- *
- * Note that these bits preclude future use of a page size
- * less than 4KB.
- *
- *
- * PPC 440 core has following TLB attribute fields;
- *
- *   TLB1:
- *   0  1  2  3  4  ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
- *   RPN.................................  -  -  -  -  -  - ERPN.......
- *
- *   TLB2:
- *   0  1  2  3  4  ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
- *   -  -  -  -  -    - U0 U1 U2 U3 W  I  M  G  E   - UX UW UR SX SW SR
- *
- * Newer 440 cores (440x6 as used on AMCC 460EX/460GT) have additional
- * TLB2 storage attibute fields. Those are:
- *
- *   TLB2:
- *   0...10    11   12   13   14   15   16...31
- *   no change WL1  IL1I IL1D IL2I IL2D no change
- *
- * There are some constrains and options, to decide mapping software bits
- * into TLB entry.
- *
- *   - PRESENT *must* be in the bottom three bits because swap cache
- *     entries use the top 29 bits for TLB2.
- *
- *   - FILE *must* be in the bottom three bits because swap cache
- *     entries use the top 29 bits for TLB2.
- *
- *   - CACHE COHERENT bit (M) has no effect on original PPC440 cores,
- *     because it doesn't support SMP. However, some later 460 variants
- *     have -some- form of SMP support and so I keep the bit there for
- *     future use
- *
- * With the PPC 44x Linux implementation, the 0-11th LSBs of the PTE are used
- * for memory protection related functions (see PTE structure in
- * include/asm-ppc/mmu.h).  The _PAGE_XXX definitions in this file map to the
- * above bits.  Note that the bit values are CPU specific, not architecture
- * specific.
- *
- * The kernel PTE entry holds an arch-dependent swp_entry structure under
- * certain situations. In other words, in such situations some portion of
- * the PTE bits are used as a swp_entry. In the PPC implementation, the
- * 3-24th LSB are shared with swp_entry, however the 0-2nd three LSB still
- * hold protection values. That means the three protection bits are
- * reserved for both PTE and SWAP entry at the most significant three
- * LSBs.
- *
- * There are three protection bits available for SWAP entry:
- *	_PAGE_PRESENT
- *	_PAGE_FILE
- *	_PAGE_HASHPTE (if HW has)
- *
- * So those three bits have to be inside of 0-2nd LSB of PTE.
- *
- */
-
-#define _PAGE_PRESENT	0x00000001		/* S: PTE valid */
-#define _PAGE_RW	0x00000002		/* S: Write permission */
-#define _PAGE_FILE	0x00000004		/* S: nonlinear file mapping */
-#define _PAGE_EXEC	0x00000004		/* H: Execute permission */
-#define _PAGE_ACCESSED	0x00000008		/* S: Page referenced */
-#define _PAGE_DIRTY	0x00000010		/* S: Page dirty */
-#define _PAGE_SPECIAL	0x00000020		/* S: Special page */
-#define _PAGE_USER	0x00000040		/* S: User page */
-#define _PAGE_ENDIAN	0x00000080		/* H: E bit */
-#define _PAGE_GUARDED	0x00000100		/* H: G bit */
-#define _PAGE_COHERENT	0x00000200		/* H: M bit */
-#define _PAGE_NO_CACHE	0x00000400		/* H: I bit */
-#define _PAGE_WRITETHRU	0x00000800		/* H: W bit */
-
-/* TODO: Add large page lowmem mapping support */
-#define _PMD_PRESENT	0
-#define _PMD_PRESENT_MASK (PAGE_MASK)
-#define _PMD_BAD	(~PAGE_MASK)
-
-/* ERPN in a PTE never gets cleared, ignore it */
-#define _PTE_NONE_MASK	0xffffffff00000000ULL
-
-
-#endif /* __KERNEL__ */
-#endif /*  _ASM_POWERPC_PTE_44x_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/pte-8xx.h b/ANDROID_3.4.5/arch/powerpc/include/asm/pte-8xx.h
deleted file mode 100644
index d44826e4..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/pte-8xx.h
+++ /dev/null
@@ -1,67 +0,0 @@
-#ifndef _ASM_POWERPC_PTE_8xx_H
-#define _ASM_POWERPC_PTE_8xx_H
-#ifdef __KERNEL__
-
-/*
- * The PowerPC MPC8xx uses a TLB with hardware assisted, software tablewalk.
- * We also use the two level tables, but we can put the real bits in them
- * needed for the TLB and tablewalk.  These definitions require Mx_CTR.PPM = 0,
- * Mx_CTR.PPCS = 0, and MD_CTR.TWAM = 1.  The level 2 descriptor has
- * additional page protection (when Mx_CTR.PPCS = 1) that allows TLB hit
- * based upon user/super access.  The TLB does not have accessed nor write
- * protect.  We assume that if the TLB get loaded with an entry it is
- * accessed, and overload the changed bit for write protect.  We use
- * two bits in the software pte that are supposed to be set to zero in
- * the TLB entry (24 and 25) for these indicators.  Although the level 1
- * descriptor contains the guarded and writethrough/copyback bits, we can
- * set these at the page level since they get copied from the Mx_TWC
- * register when the TLB entry is loaded.  We will use bit 27 for guard, since
- * that is where it exists in the MD_TWC, and bit 26 for writethrough.
- * These will get masked from the level 2 descriptor at TLB load time, and
- * copied to the MD_TWC before it gets loaded.
- * Large page sizes added.  We currently support two sizes, 4K and 8M.
- * This also allows a TLB hander optimization because we can directly
- * load the PMD into MD_TWC.  The 8M pages are only used for kernel
- * mapping of well known areas.  The PMD (PGD) entries contain control
- * flags in addition to the address, so care must be taken that the
- * software no longer assumes these are only pointers.
- */
-
-/* Definitions for 8xx embedded chips. */
-#define _PAGE_PRESENT	0x0001	/* Page is valid */
-#define _PAGE_FILE	0x0002	/* when !present: nonlinear file mapping */
-#define _PAGE_NO_CACHE	0x0002	/* I: cache inhibit */
-#define _PAGE_SHARED	0x0004	/* No ASID (context) compare */
-#define _PAGE_SPECIAL	0x0008	/* SW entry, forced to 0 by the TLB miss */
-#define _PAGE_DIRTY	0x0100	/* C: page changed */
-
-/* These 4 software bits must be masked out when the entry is loaded
- * into the TLB, 1 SW bit left(0x0080).
- */
-#define _PAGE_GUARDED	0x0010	/* software: guarded access */
-#define _PAGE_ACCESSED	0x0020	/* software: page referenced */
-#define _PAGE_WRITETHRU	0x0040	/* software: caching is write through */
-
-/* Setting any bits in the nibble with the follow two controls will
- * require a TLB exception handler change.  It is assumed unused bits
- * are always zero.
- */
-#define _PAGE_RW	0x0400	/* lsb PP bits, inverted in HW */
-#define _PAGE_USER	0x0800	/* msb PP bits */
-
-#define _PMD_PRESENT	0x0001
-#define _PMD_BAD	0x0ff0
-#define _PMD_PAGE_MASK	0x000c
-#define _PMD_PAGE_8M	0x000c
-
-#define _PTE_NONE_MASK _PAGE_ACCESSED
-
-/* Until my rework is finished, 8xx still needs atomic PTE updates */
-#define PTE_ATOMIC_UPDATES	1
-
-/* We need to add _PAGE_SHARED to kernel pages */
-#define _PAGE_KERNEL_RO	(_PAGE_SHARED)
-#define _PAGE_KERNEL_RW	(_PAGE_DIRTY | _PAGE_RW | _PAGE_HWWRITE)
-
-#endif /* __KERNEL__ */
-#endif /*  _ASM_POWERPC_PTE_8xx_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/pte-book3e.h b/ANDROID_3.4.5/arch/powerpc/include/asm/pte-book3e.h
deleted file mode 100644
index 0156702b..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/pte-book3e.h
+++ /dev/null
@@ -1,87 +0,0 @@
-#ifndef _ASM_POWERPC_PTE_BOOK3E_H
-#define _ASM_POWERPC_PTE_BOOK3E_H
-#ifdef __KERNEL__
-
-/* PTE bit definitions for processors compliant to the Book3E
- * architecture 2.06 or later. The position of the PTE bits
- * matches the HW definition of the optional Embedded Page Table
- * category.
- */
-
-/* Architected bits */
-#define _PAGE_PRESENT	0x000001 /* software: pte contains a translation */
-#define _PAGE_FILE	0x000002 /* (!present only) software: pte holds file offset */
-#define _PAGE_SW1	0x000002
-#define _PAGE_BAP_SR	0x000004
-#define _PAGE_BAP_UR	0x000008
-#define _PAGE_BAP_SW	0x000010
-#define _PAGE_BAP_UW	0x000020
-#define _PAGE_BAP_SX	0x000040
-#define _PAGE_BAP_UX	0x000080
-#define _PAGE_PSIZE_MSK	0x000f00
-#define _PAGE_PSIZE_4K	0x000200
-#define _PAGE_PSIZE_8K	0x000300
-#define _PAGE_PSIZE_16K	0x000400
-#define _PAGE_PSIZE_32K	0x000500
-#define _PAGE_PSIZE_64K	0x000600
-#define _PAGE_PSIZE_128K	0x000700
-#define _PAGE_PSIZE_256K	0x000800
-#define _PAGE_PSIZE_512K	0x000900
-#define _PAGE_PSIZE_1M	0x000a00
-#define _PAGE_PSIZE_2M	0x000b00
-#define _PAGE_PSIZE_4M	0x000c00
-#define _PAGE_PSIZE_8M	0x000d00
-#define _PAGE_PSIZE_16M	0x000e00
-#define _PAGE_PSIZE_32M	0x000f00
-#define _PAGE_DIRTY	0x001000 /* C: page changed */
-#define _PAGE_SW0	0x002000
-#define _PAGE_U3	0x004000
-#define _PAGE_U2	0x008000
-#define _PAGE_U1	0x010000
-#define _PAGE_U0	0x020000
-#define _PAGE_ACCESSED	0x040000
-#define _PAGE_LENDIAN	0x080000
-#define _PAGE_GUARDED	0x100000
-#define _PAGE_COHERENT	0x200000 /* M: enforce memory coherence */
-#define _PAGE_NO_CACHE	0x400000 /* I: cache inhibit */
-#define _PAGE_WRITETHRU	0x800000 /* W: cache write-through */
-
-/* "Higher level" linux bit combinations */
-#define _PAGE_EXEC		_PAGE_BAP_UX /* .. and was cache cleaned */
-#define _PAGE_RW		(_PAGE_BAP_SW | _PAGE_BAP_UW) /* User write permission */
-#define _PAGE_KERNEL_RW		(_PAGE_BAP_SW | _PAGE_BAP_SR | _PAGE_DIRTY)
-#define _PAGE_KERNEL_RO		(_PAGE_BAP_SR)
-#define _PAGE_KERNEL_RWX	(_PAGE_BAP_SW | _PAGE_BAP_SR | _PAGE_DIRTY | _PAGE_BAP_SX)
-#define _PAGE_KERNEL_ROX	(_PAGE_BAP_SR | _PAGE_BAP_SX)
-#define _PAGE_USER		(_PAGE_BAP_UR | _PAGE_BAP_SR) /* Can be read */
-
-#define _PAGE_HASHPTE	0
-#define _PAGE_BUSY	0
-
-#define _PAGE_SPECIAL	_PAGE_SW0
-
-/* Flags to be preserved on PTE modifications */
-#define _PAGE_HPTEFLAGS	_PAGE_BUSY
-
-/* Base page size */
-#ifdef CONFIG_PPC_64K_PAGES
-#define _PAGE_PSIZE	_PAGE_PSIZE_64K
-#define PTE_RPN_SHIFT	(28)
-#else
-#define _PAGE_PSIZE	_PAGE_PSIZE_4K
-#define	PTE_RPN_SHIFT	(24)
-#endif
-
-#define PTE_WIMGE_SHIFT (19)
-#define PTE_BAP_SHIFT	(2)
-
-/* On 32-bit, we never clear the top part of the PTE */
-#ifdef CONFIG_PPC32
-#define _PTE_NONE_MASK	0xffffffff00000000ULL
-#define _PMD_PRESENT	0
-#define _PMD_PRESENT_MASK (PAGE_MASK)
-#define _PMD_BAD	(~PAGE_MASK)
-#endif
-
-#endif /* __KERNEL__ */
-#endif /*  _ASM_POWERPC_PTE_FSL_BOOKE_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/pte-common.h b/ANDROID_3.4.5/arch/powerpc/include/asm/pte-common.h
deleted file mode 100644
index 8d1569c2..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/pte-common.h
+++ /dev/null
@@ -1,187 +0,0 @@
-/* Included from asm/pgtable-*.h only ! */
-
-/*
- * Some bits are only used on some cpu families... Make sure that all
- * the undefined gets a sensible default
- */
-#ifndef _PAGE_HASHPTE
-#define _PAGE_HASHPTE	0
-#endif
-#ifndef _PAGE_SHARED
-#define _PAGE_SHARED	0
-#endif
-#ifndef _PAGE_HWWRITE
-#define _PAGE_HWWRITE	0
-#endif
-#ifndef _PAGE_EXEC
-#define _PAGE_EXEC	0
-#endif
-#ifndef _PAGE_ENDIAN
-#define _PAGE_ENDIAN	0
-#endif
-#ifndef _PAGE_COHERENT
-#define _PAGE_COHERENT	0
-#endif
-#ifndef _PAGE_WRITETHRU
-#define _PAGE_WRITETHRU	0
-#endif
-#ifndef _PAGE_4K_PFN
-#define _PAGE_4K_PFN		0
-#endif
-#ifndef _PAGE_SAO
-#define _PAGE_SAO	0
-#endif
-#ifndef _PAGE_PSIZE
-#define _PAGE_PSIZE		0
-#endif
-#ifndef _PMD_PRESENT_MASK
-#define _PMD_PRESENT_MASK	_PMD_PRESENT
-#endif
-#ifndef _PMD_SIZE
-#define _PMD_SIZE	0
-#define PMD_PAGE_SIZE(pmd)	bad_call_to_PMD_PAGE_SIZE()
-#endif
-#ifndef _PAGE_KERNEL_RO
-#define _PAGE_KERNEL_RO		0
-#endif
-#ifndef _PAGE_KERNEL_ROX
-#define _PAGE_KERNEL_ROX	(_PAGE_EXEC)
-#endif
-#ifndef _PAGE_KERNEL_RW
-#define _PAGE_KERNEL_RW		(_PAGE_DIRTY | _PAGE_RW | _PAGE_HWWRITE)
-#endif
-#ifndef _PAGE_KERNEL_RWX
-#define _PAGE_KERNEL_RWX	(_PAGE_DIRTY | _PAGE_RW | _PAGE_HWWRITE | _PAGE_EXEC)
-#endif
-#ifndef _PAGE_HPTEFLAGS
-#define _PAGE_HPTEFLAGS _PAGE_HASHPTE
-#endif
-#ifndef _PTE_NONE_MASK
-#define _PTE_NONE_MASK	_PAGE_HPTEFLAGS
-#endif
-
-/* Make sure we get a link error if PMD_PAGE_SIZE is ever called on a
- * kernel without large page PMD support
- */
-#ifndef __ASSEMBLY__
-extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
-#endif /* __ASSEMBLY__ */
-
-/* Location of the PFN in the PTE. Most 32-bit platforms use the same
- * as _PAGE_SHIFT here (ie, naturally aligned).
- * Platform who don't just pre-define the value so we don't override it here
- */
-#ifndef PTE_RPN_SHIFT
-#define PTE_RPN_SHIFT	(PAGE_SHIFT)
-#endif
-
-/* The mask convered by the RPN must be a ULL on 32-bit platforms with
- * 64-bit PTEs
- */
-#if defined(CONFIG_PPC32) && defined(CONFIG_PTE_64BIT)
-#define PTE_RPN_MAX	(1ULL << (64 - PTE_RPN_SHIFT))
-#define PTE_RPN_MASK	(~((1ULL<<PTE_RPN_SHIFT)-1))
-#else
-#define PTE_RPN_MAX	(1UL << (32 - PTE_RPN_SHIFT))
-#define PTE_RPN_MASK	(~((1UL<<PTE_RPN_SHIFT)-1))
-#endif
-
-/* _PAGE_CHG_MASK masks of bits that are to be preserved across
- * pgprot changes
- */
-#define _PAGE_CHG_MASK	(PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
-                         _PAGE_ACCESSED | _PAGE_SPECIAL)
-
-/* Mask of bits returned by pte_pgprot() */
-#define PAGE_PROT_BITS	(_PAGE_GUARDED | _PAGE_COHERENT | _PAGE_NO_CACHE | \
-			 _PAGE_WRITETHRU | _PAGE_ENDIAN | _PAGE_4K_PFN | \
-			 _PAGE_USER | _PAGE_ACCESSED | \
-			 _PAGE_RW | _PAGE_HWWRITE | _PAGE_DIRTY | _PAGE_EXEC)
-
-/*
- * We define 2 sets of base prot bits, one for basic pages (ie,
- * cacheable kernel and user pages) and one for non cacheable
- * pages. We always set _PAGE_COHERENT when SMP is enabled or
- * the processor might need it for DMA coherency.
- */
-#define _PAGE_BASE_NC	(_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE)
-#if defined(CONFIG_SMP) || defined(CONFIG_PPC_STD_MMU)
-#define _PAGE_BASE	(_PAGE_BASE_NC | _PAGE_COHERENT)
-#else
-#define _PAGE_BASE	(_PAGE_BASE_NC)
-#endif
-
-/* Permission masks used to generate the __P and __S table,
- *
- * Note:__pgprot is defined in arch/powerpc/include/asm/page.h
- *
- * Write permissions imply read permissions for now (we could make write-only
- * pages on BookE but we don't bother for now). Execute permission control is
- * possible on platforms that define _PAGE_EXEC
- *
- * Note due to the way vm flags are laid out, the bits are XWR
- */
-#define PAGE_NONE	__pgprot(_PAGE_BASE)
-#define PAGE_SHARED	__pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
-#define PAGE_SHARED_X	__pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC)
-#define PAGE_COPY	__pgprot(_PAGE_BASE | _PAGE_USER)
-#define PAGE_COPY_X	__pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
-#define PAGE_READONLY	__pgprot(_PAGE_BASE | _PAGE_USER)
-#define PAGE_READONLY_X	__pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
-
-#define __P000	PAGE_NONE
-#define __P001	PAGE_READONLY
-#define __P010	PAGE_COPY
-#define __P011	PAGE_COPY
-#define __P100	PAGE_READONLY_X
-#define __P101	PAGE_READONLY_X
-#define __P110	PAGE_COPY_X
-#define __P111	PAGE_COPY_X
-
-#define __S000	PAGE_NONE
-#define __S001	PAGE_READONLY
-#define __S010	PAGE_SHARED
-#define __S011	PAGE_SHARED
-#define __S100	PAGE_READONLY_X
-#define __S101	PAGE_READONLY_X
-#define __S110	PAGE_SHARED_X
-#define __S111	PAGE_SHARED_X
-
-/* Permission masks used for kernel mappings */
-#define PAGE_KERNEL	__pgprot(_PAGE_BASE | _PAGE_KERNEL_RW)
-#define PAGE_KERNEL_NC	__pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
-				 _PAGE_NO_CACHE)
-#define PAGE_KERNEL_NCG	__pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
-				 _PAGE_NO_CACHE | _PAGE_GUARDED)
-#define PAGE_KERNEL_X	__pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX)
-#define PAGE_KERNEL_RO	__pgprot(_PAGE_BASE | _PAGE_KERNEL_RO)
-#define PAGE_KERNEL_ROX	__pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX)
-
-/* Protection used for kernel text. We want the debuggers to be able to
- * set breakpoints anywhere, so don't write protect the kernel text
- * on platforms where such control is possible.
- */
-#if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) ||\
-	defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE)
-#define PAGE_KERNEL_TEXT	PAGE_KERNEL_X
-#else
-#define PAGE_KERNEL_TEXT	PAGE_KERNEL_ROX
-#endif
-
-/* Make modules code happy. We don't set RO yet */
-#define PAGE_KERNEL_EXEC	PAGE_KERNEL_X
-
-/*
- * Don't just check for any non zero bits in __PAGE_USER, since for book3e
- * and PTE_64BIT, PAGE_KERNEL_X contains _PAGE_BAP_SR which is also in
- * _PAGE_USER.  Need to explicitly match _PAGE_BAP_UR bit in that case too.
- */
-#define pte_user(val)		((val & _PAGE_USER) == _PAGE_USER)
-
-/* Advertise special mapping type for AGP */
-#define PAGE_AGP		(PAGE_KERNEL_NC)
-#define HAVE_PAGE_AGP
-
-/* Advertise support for _PAGE_SPECIAL */
-#define __HAVE_ARCH_PTE_SPECIAL
-
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/pte-fsl-booke.h b/ANDROID_3.4.5/arch/powerpc/include/asm/pte-fsl-booke.h
deleted file mode 100644
index 2c12be5f..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/pte-fsl-booke.h
+++ /dev/null
@@ -1,41 +0,0 @@
-#ifndef _ASM_POWERPC_PTE_FSL_BOOKE_H
-#define _ASM_POWERPC_PTE_FSL_BOOKE_H
-#ifdef __KERNEL__
-
-/* PTE bit definitions for Freescale BookE SW loaded TLB MMU based
- * processors
- *
-   MMU Assist Register 3:
-
-   32 33 34 35 36  ... 50 51 52 53 54 55 56 57 58 59 60 61 62 63
-   RPN......................  0  0 U0 U1 U2 U3 UX SX UW SW UR SR
-
-   - PRESENT *must* be in the bottom three bits because swap cache
-     entries use the top 29 bits.
-
-   - FILE *must* be in the bottom three bits because swap cache
-     entries use the top 29 bits.
-*/
-
-/* Definitions for FSL Book-E Cores */
-#define _PAGE_PRESENT	0x00001	/* S: PTE contains a translation */
-#define _PAGE_USER	0x00002	/* S: User page (maps to UR) */
-#define _PAGE_FILE	0x00002	/* S: when !present: nonlinear file mapping */
-#define _PAGE_RW	0x00004	/* S: Write permission (SW) */
-#define _PAGE_DIRTY	0x00008	/* S: Page dirty */
-#define _PAGE_EXEC	0x00010	/* H: SX permission */
-#define _PAGE_ACCESSED	0x00020	/* S: Page referenced */
-
-#define _PAGE_ENDIAN	0x00040	/* H: E bit */
-#define _PAGE_GUARDED	0x00080	/* H: G bit */
-#define _PAGE_COHERENT	0x00100	/* H: M bit */
-#define _PAGE_NO_CACHE	0x00200	/* H: I bit */
-#define _PAGE_WRITETHRU	0x00400	/* H: W bit */
-#define _PAGE_SPECIAL	0x00800 /* S: Special page */
-
-#define _PMD_PRESENT	0
-#define _PMD_PRESENT_MASK (PAGE_MASK)
-#define _PMD_BAD	(~PAGE_MASK)
-
-#endif /* __KERNEL__ */
-#endif /*  _ASM_POWERPC_PTE_FSL_BOOKE_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/pte-hash32.h b/ANDROID_3.4.5/arch/powerpc/include/asm/pte-hash32.h
deleted file mode 100644
index 4aad4132..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/pte-hash32.h
+++ /dev/null
@@ -1,47 +0,0 @@
-#ifndef _ASM_POWERPC_PTE_HASH32_H
-#define _ASM_POWERPC_PTE_HASH32_H
-#ifdef __KERNEL__
-
-/*
- * The "classic" 32-bit implementation of the PowerPC MMU uses a hash
- * table containing PTEs, together with a set of 16 segment registers,
- * to define the virtual to physical address mapping.
- *
- * We use the hash table as an extended TLB, i.e. a cache of currently
- * active mappings.  We maintain a two-level page table tree, much
- * like that used by the i386, for the sake of the Linux memory
- * management code.  Low-level assembler code in hash_low_32.S
- * (procedure hash_page) is responsible for extracting ptes from the
- * tree and putting them into the hash table when necessary, and
- * updating the accessed and modified bits in the page table tree.
- */
-
-#define _PAGE_PRESENT	0x001	/* software: pte contains a translation */
-#define _PAGE_HASHPTE	0x002	/* hash_page has made an HPTE for this pte */
-#define _PAGE_FILE	0x004	/* when !present: nonlinear file mapping */
-#define _PAGE_USER	0x004	/* usermode access allowed */
-#define _PAGE_GUARDED	0x008	/* G: prohibit speculative access */
-#define _PAGE_COHERENT	0x010	/* M: enforce memory coherence (SMP systems) */
-#define _PAGE_NO_CACHE	0x020	/* I: cache inhibit */
-#define _PAGE_WRITETHRU	0x040	/* W: cache write-through */
-#define _PAGE_DIRTY	0x080	/* C: page changed */
-#define _PAGE_ACCESSED	0x100	/* R: page referenced */
-#define _PAGE_RW	0x400	/* software: user write access allowed */
-#define _PAGE_SPECIAL	0x800	/* software: Special page */
-
-#ifdef CONFIG_PTE_64BIT
-/* We never clear the high word of the pte */
-#define _PTE_NONE_MASK	(0xffffffff00000000ULL | _PAGE_HASHPTE)
-#else
-#define _PTE_NONE_MASK	_PAGE_HASHPTE
-#endif
-
-#define _PMD_PRESENT	0
-#define _PMD_PRESENT_MASK (PAGE_MASK)
-#define _PMD_BAD	(~PAGE_MASK)
-
-/* Hash table based platforms need atomic updates of the linux PTE */
-#define PTE_ATOMIC_UPDATES	1
-
-#endif /* __KERNEL__ */
-#endif /*  _ASM_POWERPC_PTE_HASH32_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/pte-hash64-4k.h b/ANDROID_3.4.5/arch/powerpc/include/asm/pte-hash64-4k.h
deleted file mode 100644
index c134e809..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/pte-hash64-4k.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* To be include by pgtable-hash64.h only */
-
-/* PTE bits */
-#define _PAGE_HASHPTE	0x0400 /* software: pte has an associated HPTE */
-#define _PAGE_SECONDARY 0x8000 /* software: HPTE is in secondary group */
-#define _PAGE_GROUP_IX  0x7000 /* software: HPTE index within group */
-#define _PAGE_F_SECOND  _PAGE_SECONDARY
-#define _PAGE_F_GIX     _PAGE_GROUP_IX
-#define _PAGE_SPECIAL	0x10000 /* software: special page */
-
-/* PTE flags to conserve for HPTE identification */
-#define _PAGE_HPTEFLAGS (_PAGE_BUSY | _PAGE_HASHPTE | \
-			 _PAGE_SECONDARY | _PAGE_GROUP_IX)
-
-/* shift to put page number into pte */
-#define PTE_RPN_SHIFT	(17)
-
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/pte-hash64-64k.h b/ANDROID_3.4.5/arch/powerpc/include/asm/pte-hash64-64k.h
deleted file mode 100644
index 59247e81..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/pte-hash64-64k.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/* To be include by pgtable-hash64.h only */
-
-/* Additional PTE bits (don't change without checking asm in hash_low.S) */
-#define _PAGE_SPECIAL	0x00000400 /* software: special page */
-#define _PAGE_HPTE_SUB	0x0ffff000 /* combo only: sub pages HPTE bits */
-#define _PAGE_HPTE_SUB0	0x08000000 /* combo only: first sub page */
-#define _PAGE_COMBO	0x10000000 /* this is a combo 4k page */
-#define _PAGE_4K_PFN	0x20000000 /* PFN is for a single 4k page */
-
-/* For 64K page, we don't have a separate _PAGE_HASHPTE bit. Instead,
- * we set that to be the whole sub-bits mask. The C code will only
- * test this, so a multi-bit mask will work. For combo pages, this
- * is equivalent as effectively, the old _PAGE_HASHPTE was an OR of
- * all the sub bits. For real 64k pages, we now have the assembly set
- * _PAGE_HPTE_SUB0 in addition to setting the HIDX bits which overlap
- * that mask. This is fine as long as the HIDX bits are never set on
- * a PTE that isn't hashed, which is the case today.
- *
- * A little nit is for the huge page C code, which does the hashing
- * in C, we need to provide which bit to use.
- */
-#define _PAGE_HASHPTE	_PAGE_HPTE_SUB
-
-/* Note the full page bits must be in the same location as for normal
- * 4k pages as the same assembly will be used to insert 64K pages
- * wether the kernel has CONFIG_PPC_64K_PAGES or not
- */
-#define _PAGE_F_SECOND  0x00008000 /* full page: hidx bits */
-#define _PAGE_F_GIX     0x00007000 /* full page: hidx bits */
-
-/* PTE flags to conserve for HPTE identification */
-#define _PAGE_HPTEFLAGS (_PAGE_BUSY | _PAGE_HASHPTE | _PAGE_COMBO)
-
-/* Shift to put page number into pte.
- *
- * That gives us a max RPN of 34 bits, which means a max of 50 bits
- * of addressable physical space, or 46 bits for the special 4k PFNs.
- */
-#define PTE_RPN_SHIFT	(30)
-
-#ifndef __ASSEMBLY__
-
-/*
- * With 64K pages on hash table, we have a special PTE format that
- * uses a second "half" of the page table to encode sub-page information
- * in order to deal with 64K made of 4K HW pages. Thus we override the
- * generic accessors and iterators here
- */
-#define __real_pte(e,p) 	((real_pte_t) { \
-			(e), ((e) & _PAGE_COMBO) ? \
-				(pte_val(*((p) + PTRS_PER_PTE))) : 0 })
-#define __rpte_to_hidx(r,index)	((pte_val((r).pte) & _PAGE_COMBO) ? \
-        (((r).hidx >> ((index)<<2)) & 0xf) : ((pte_val((r).pte) >> 12) & 0xf))
-#define __rpte_to_pte(r)	((r).pte)
-#define __rpte_sub_valid(rpte, index) \
-	(pte_val(rpte.pte) & (_PAGE_HPTE_SUB0 >> (index)))
-
-/* Trick: we set __end to va + 64k, which happens works for
- * a 16M page as well as we want only one iteration
- */
-#define pte_iterate_hashed_subpages(rpte, psize, va, index, shift)	    \
-        do {                                                                \
-                unsigned long __end = va + PAGE_SIZE;                       \
-                unsigned __split = (psize == MMU_PAGE_4K ||                 \
-				    psize == MMU_PAGE_64K_AP);              \
-                shift = mmu_psize_defs[psize].shift;                        \
-		for (index = 0; va < __end; index++, va += (1L << shift)) { \
-		        if (!__split || __rpte_sub_valid(rpte, index)) do { \
-
-#define pte_iterate_hashed_end() } while(0); } } while(0)
-
-#define pte_pagesize_index(mm, addr, pte)	\
-	(((pte) & _PAGE_COMBO)? MMU_PAGE_4K: MMU_PAGE_64K)
-
-#define remap_4k_pfn(vma, addr, pfn, prot)				\
-	remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE,		\
-			__pgprot(pgprot_val((prot)) | _PAGE_4K_PFN))
-
-#endif	/* __ASSEMBLY__ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/pte-hash64.h b/ANDROID_3.4.5/arch/powerpc/include/asm/pte-hash64.h
deleted file mode 100644
index 0419eeb5..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/pte-hash64.h
+++ /dev/null
@@ -1,54 +0,0 @@
-#ifndef _ASM_POWERPC_PTE_HASH64_H
-#define _ASM_POWERPC_PTE_HASH64_H
-#ifdef __KERNEL__
-
-/*
- * Common bits between 4K and 64K pages in a linux-style PTE.
- * These match the bits in the (hardware-defined) PowerPC PTE as closely
- * as possible. Additional bits may be defined in pgtable-hash64-*.h
- *
- * Note: We only support user read/write permissions. Supervisor always
- * have full read/write to pages above PAGE_OFFSET (pages below that
- * always use the user access permissions).
- *
- * We could create separate kernel read-only if we used the 3 PP bits
- * combinations that newer processors provide but we currently don't.
- */
-#define _PAGE_PRESENT		0x0001 /* software: pte contains a translation */
-#define _PAGE_USER		0x0002 /* matches one of the PP bits */
-#define _PAGE_FILE		0x0002 /* (!present only) software: pte holds file offset */
-#define _PAGE_EXEC		0x0004 /* No execute on POWER4 and newer (we invert) */
-#define _PAGE_GUARDED		0x0008
-#define _PAGE_COHERENT		0x0010 /* M: enforce memory coherence (SMP systems) */
-#define _PAGE_NO_CACHE		0x0020 /* I: cache inhibit */
-#define _PAGE_WRITETHRU		0x0040 /* W: cache write-through */
-#define _PAGE_DIRTY		0x0080 /* C: page changed */
-#define _PAGE_ACCESSED		0x0100 /* R: page referenced */
-#define _PAGE_RW		0x0200 /* software: user write access allowed */
-#define _PAGE_BUSY		0x0800 /* software: PTE & hash are busy */
-
-/* No separate kernel read-only */
-#define _PAGE_KERNEL_RW		(_PAGE_RW | _PAGE_DIRTY) /* user access blocked by key */
-#define _PAGE_KERNEL_RO		 _PAGE_KERNEL_RW
-
-/* Strong Access Ordering */
-#define _PAGE_SAO		(_PAGE_WRITETHRU | _PAGE_NO_CACHE | _PAGE_COHERENT)
-
-/* No page size encoding in the linux PTE */
-#define _PAGE_PSIZE		0
-
-/* PTEIDX nibble */
-#define _PTEIDX_SECONDARY	0x8
-#define _PTEIDX_GROUP_IX	0x7
-
-/* Hash table based platforms need atomic updates of the linux PTE */
-#define PTE_ATOMIC_UPDATES	1
-
-#ifdef CONFIG_PPC_64K_PAGES
-#include <asm/pte-hash64-64k.h>
-#else
-#include <asm/pte-hash64-4k.h>
-#endif
-
-#endif /* __KERNEL__ */
-#endif /*  _ASM_POWERPC_PTE_HASH64_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/ptrace.h b/ANDROID_3.4.5/arch/powerpc/include/asm/ptrace.h
deleted file mode 100644
index 84cc7840..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/ptrace.h
+++ /dev/null
@@ -1,444 +0,0 @@
-#ifndef _ASM_POWERPC_PTRACE_H
-#define _ASM_POWERPC_PTRACE_H
-
-/*
- * Copyright (C) 2001 PPC64 Team, IBM Corp
- *
- * This struct defines the way the registers are stored on the
- * kernel stack during a system call or other kernel entry.
- *
- * this should only contain volatile regs
- * since we can keep non-volatile in the thread_struct
- * should set this up when only volatiles are saved
- * by intr code.
- *
- * Since this is going on the stack, *CARE MUST BE TAKEN* to insure
- * that the overall structure is a multiple of 16 bytes in length.
- *
- * Note that the offsets of the fields in this struct correspond with
- * the PT_* values below.  This simplifies arch/powerpc/kernel/ptrace.c.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/types.h>
-
-#ifndef __ASSEMBLY__
-
-struct pt_regs {
-	unsigned long gpr[32];
-	unsigned long nip;
-	unsigned long msr;
-	unsigned long orig_gpr3;	/* Used for restarting system calls */
-	unsigned long ctr;
-	unsigned long link;
-	unsigned long xer;
-	unsigned long ccr;
-#ifdef __powerpc64__
-	unsigned long softe;		/* Soft enabled/disabled */
-#else
-	unsigned long mq;		/* 601 only (not used at present) */
-					/* Used on APUS to hold IPL value. */
-#endif
-	unsigned long trap;		/* Reason for being here */
-	/* N.B. for critical exceptions on 4xx, the dar and dsisr
-	   fields are overloaded to hold srr0 and srr1. */
-	unsigned long dar;		/* Fault registers */
-	unsigned long dsisr;		/* on 4xx/Book-E used for ESR */
-	unsigned long result;		/* Result of a system call */
-};
-
-#endif /* __ASSEMBLY__ */
-
-#ifdef __KERNEL__
-
-#ifdef __powerpc64__
-
-#define STACK_FRAME_OVERHEAD	112	/* size of minimum stack frame */
-#define STACK_FRAME_LR_SAVE	2	/* Location of LR in stack frame */
-#define STACK_FRAME_REGS_MARKER	ASM_CONST(0x7265677368657265)
-#define STACK_INT_FRAME_SIZE	(sizeof(struct pt_regs) + \
-					STACK_FRAME_OVERHEAD + 288)
-#define STACK_FRAME_MARKER	12
-
-/* Size of dummy stack frame allocated when calling signal handler. */
-#define __SIGNAL_FRAMESIZE	128
-#define __SIGNAL_FRAMESIZE32	64
-
-#else /* __powerpc64__ */
-
-#define STACK_FRAME_OVERHEAD	16	/* size of minimum stack frame */
-#define STACK_FRAME_LR_SAVE	1	/* Location of LR in stack frame */
-#define STACK_FRAME_REGS_MARKER	ASM_CONST(0x72656773)
-#define STACK_INT_FRAME_SIZE	(sizeof(struct pt_regs) + STACK_FRAME_OVERHEAD)
-#define STACK_FRAME_MARKER	2
-
-/* Size of stack frame allocated when calling signal handler. */
-#define __SIGNAL_FRAMESIZE	64
-
-#endif /* __powerpc64__ */
-
-#ifndef __ASSEMBLY__
-
-#define GET_IP(regs)		((regs)->nip)
-#define GET_USP(regs)		((regs)->gpr[1])
-#define GET_FP(regs)		(0)
-#define SET_FP(regs, val)
-
-#ifdef CONFIG_SMP
-extern unsigned long profile_pc(struct pt_regs *regs);
-#define profile_pc profile_pc
-#endif
-
-#include <asm-generic/ptrace.h>
-
-#define kernel_stack_pointer(regs) ((regs)->gpr[1])
-static inline int is_syscall_success(struct pt_regs *regs)
-{
-	return !(regs->ccr & 0x10000000);
-}
-
-static inline long regs_return_value(struct pt_regs *regs)
-{
-	if (is_syscall_success(regs))
-		return regs->gpr[3];
-	else
-		return -regs->gpr[3];
-}
-
-#ifdef __powerpc64__
-#define user_mode(regs) ((((regs)->msr) >> MSR_PR_LG) & 0x1)
-#else
-#define user_mode(regs) (((regs)->msr & MSR_PR) != 0)
-#endif
-
-#define force_successful_syscall_return()   \
-	do { \
-		set_thread_flag(TIF_NOERROR); \
-	} while(0)
-
-struct task_struct;
-extern unsigned long ptrace_get_reg(struct task_struct *task, int regno);
-extern int ptrace_put_reg(struct task_struct *task, int regno,
-			  unsigned long data);
-
-/*
- * We use the least-significant bit of the trap field to indicate
- * whether we have saved the full set of registers, or only a
- * partial set.  A 1 there means the partial set.
- * On 4xx we use the next bit to indicate whether the exception
- * is a critical exception (1 means it is).
- */
-#define FULL_REGS(regs)		(((regs)->trap & 1) == 0)
-#ifndef __powerpc64__
-#define IS_CRITICAL_EXC(regs)	(((regs)->trap & 2) != 0)
-#define IS_MCHECK_EXC(regs)	(((regs)->trap & 4) != 0)
-#define IS_DEBUG_EXC(regs)	(((regs)->trap & 8) != 0)
-#endif /* ! __powerpc64__ */
-#define TRAP(regs)		((regs)->trap & ~0xF)
-#ifdef __powerpc64__
-#define NV_REG_POISON		0xdeadbeefdeadbeefUL
-#define CHECK_FULL_REGS(regs)	BUG_ON(regs->trap & 1)
-#else
-#define NV_REG_POISON		0xdeadbeef
-#define CHECK_FULL_REGS(regs)						      \
-do {									      \
-	if ((regs)->trap & 1)						      \
-		printk(KERN_CRIT "%s: partial register set\n", __func__); \
-} while (0)
-#endif /* __powerpc64__ */
-
-#define arch_has_single_step()	(1)
-#define arch_has_block_step()	(!cpu_has_feature(CPU_FTR_601))
-#define ARCH_HAS_USER_SINGLE_STEP_INFO
-
-/*
- * kprobe-based event tracer support
- */
-
-#include <linux/stddef.h>
-#include <linux/thread_info.h>
-extern int regs_query_register_offset(const char *name);
-extern const char *regs_query_register_name(unsigned int offset);
-#define MAX_REG_OFFSET (offsetof(struct pt_regs, dsisr))
-
-/**
- * regs_get_register() - get register value from its offset
- * @regs:	   pt_regs from which register value is gotten
- * @offset:    offset number of the register.
- *
- * regs_get_register returns the value of a register whose offset from @regs.
- * The @offset is the offset of the register in struct pt_regs.
- * If @offset is bigger than MAX_REG_OFFSET, this returns 0.
- */
-static inline unsigned long regs_get_register(struct pt_regs *regs,
-						unsigned int offset)
-{
-	if (unlikely(offset > MAX_REG_OFFSET))
-		return 0;
-	return *(unsigned long *)((unsigned long)regs + offset);
-}
-
-/**
- * regs_within_kernel_stack() - check the address in the stack
- * @regs:      pt_regs which contains kernel stack pointer.
- * @addr:      address which is checked.
- *
- * regs_within_kernel_stack() checks @addr is within the kernel stack page(s).
- * If @addr is within the kernel stack, it returns true. If not, returns false.
- */
-
-static inline bool regs_within_kernel_stack(struct pt_regs *regs,
-						unsigned long addr)
-{
-	return ((addr & ~(THREAD_SIZE - 1))  ==
-		(kernel_stack_pointer(regs) & ~(THREAD_SIZE - 1)));
-}
-
-/**
- * regs_get_kernel_stack_nth() - get Nth entry of the stack
- * @regs:	pt_regs which contains kernel stack pointer.
- * @n:		stack entry number.
- *
- * regs_get_kernel_stack_nth() returns @n th entry of the kernel stack which
- * is specified by @regs. If the @n th entry is NOT in the kernel stack,
- * this returns 0.
- */
-static inline unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs,
-						      unsigned int n)
-{
-	unsigned long *addr = (unsigned long *)kernel_stack_pointer(regs);
-	addr += n;
-	if (regs_within_kernel_stack(regs, (unsigned long)addr))
-		return *addr;
-	else
-		return 0;
-}
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* __KERNEL__ */
-
-/*
- * Offsets used by 'ptrace' system call interface.
- * These can't be changed without breaking binary compatibility
- * with MkLinux, etc.
- */
-#define PT_R0	0
-#define PT_R1	1
-#define PT_R2	2
-#define PT_R3	3
-#define PT_R4	4
-#define PT_R5	5
-#define PT_R6	6
-#define PT_R7	7
-#define PT_R8	8
-#define PT_R9	9
-#define PT_R10	10
-#define PT_R11	11
-#define PT_R12	12
-#define PT_R13	13
-#define PT_R14	14
-#define PT_R15	15
-#define PT_R16	16
-#define PT_R17	17
-#define PT_R18	18
-#define PT_R19	19
-#define PT_R20	20
-#define PT_R21	21
-#define PT_R22	22
-#define PT_R23	23
-#define PT_R24	24
-#define PT_R25	25
-#define PT_R26	26
-#define PT_R27	27
-#define PT_R28	28
-#define PT_R29	29
-#define PT_R30	30
-#define PT_R31	31
-
-#define PT_NIP	32
-#define PT_MSR	33
-#define PT_ORIG_R3 34
-#define PT_CTR	35
-#define PT_LNK	36
-#define PT_XER	37
-#define PT_CCR	38
-#ifndef __powerpc64__
-#define PT_MQ	39
-#else
-#define PT_SOFTE 39
-#endif
-#define PT_TRAP	40
-#define PT_DAR	41
-#define PT_DSISR 42
-#define PT_RESULT 43
-#define PT_REGS_COUNT 44
-
-#define PT_FPR0	48	/* each FP reg occupies 2 slots in this space */
-
-#ifndef __powerpc64__
-
-#define PT_FPR31 (PT_FPR0 + 2*31)
-#define PT_FPSCR (PT_FPR0 + 2*32 + 1)
-
-#else /* __powerpc64__ */
-
-#define PT_FPSCR (PT_FPR0 + 32)	/* each FP reg occupies 1 slot in 64-bit space */
-
-#ifdef __KERNEL__
-#define PT_FPSCR32 (PT_FPR0 + 2*32 + 1)	/* each FP reg occupies 2 32-bit userspace slots */
-#endif
-
-#define PT_VR0 82	/* each Vector reg occupies 2 slots in 64-bit */
-#define PT_VSCR (PT_VR0 + 32*2 + 1)
-#define PT_VRSAVE (PT_VR0 + 33*2)
-
-#ifdef __KERNEL__
-#define PT_VR0_32 164	/* each Vector reg occupies 4 slots in 32-bit */
-#define PT_VSCR_32 (PT_VR0 + 32*4 + 3)
-#define PT_VRSAVE_32 (PT_VR0 + 33*4)
-#endif
-
-/*
- * Only store first 32 VSRs here. The second 32 VSRs in VR0-31
- */
-#define PT_VSR0 150	/* each VSR reg occupies 2 slots in 64-bit */
-#define PT_VSR31 (PT_VSR0 + 2*31)
-#ifdef __KERNEL__
-#define PT_VSR0_32 300 	/* each VSR reg occupies 4 slots in 32-bit */
-#endif
-#endif /* __powerpc64__ */
-
-/*
- * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go.
- * The transfer totals 34 quadword.  Quadwords 0-31 contain the
- * corresponding vector registers.  Quadword 32 contains the vscr as the
- * last word (offset 12) within that quadword.  Quadword 33 contains the
- * vrsave as the first word (offset 0) within the quadword.
- *
- * This definition of the VMX state is compatible with the current PPC32
- * ptrace interface.  This allows signal handling and ptrace to use the same
- * structures.  This also simplifies the implementation of a bi-arch
- * (combined (32- and 64-bit) gdb.
- */
-#define PTRACE_GETVRREGS	18
-#define PTRACE_SETVRREGS	19
-
-/* Get/set all the upper 32-bits of the SPE registers, accumulator, and
- * spefscr, in one go */
-#define PTRACE_GETEVRREGS	20
-#define PTRACE_SETEVRREGS	21
-
-/* Get the first 32 128bit VSX registers */
-#define PTRACE_GETVSRREGS	27
-#define PTRACE_SETVSRREGS	28
-
-/*
- * Get or set a debug register. The first 16 are DABR registers and the
- * second 16 are IABR registers.
- */
-#define PTRACE_GET_DEBUGREG	25
-#define PTRACE_SET_DEBUGREG	26
-
-/* (new) PTRACE requests using the same numbers as x86 and the same
- * argument ordering. Additionally, they support more registers too
- */
-#define PTRACE_GETREGS            12
-#define PTRACE_SETREGS            13
-#define PTRACE_GETFPREGS          14
-#define PTRACE_SETFPREGS          15
-#define PTRACE_GETREGS64	  22
-#define PTRACE_SETREGS64	  23
-
-/* (old) PTRACE requests with inverted arguments */
-#define PPC_PTRACE_GETREGS	0x99	/* Get GPRs 0 - 31 */
-#define PPC_PTRACE_SETREGS	0x98	/* Set GPRs 0 - 31 */
-#define PPC_PTRACE_GETFPREGS	0x97	/* Get FPRs 0 - 31 */
-#define PPC_PTRACE_SETFPREGS	0x96	/* Set FPRs 0 - 31 */
-
-/* Calls to trace a 64bit program from a 32bit program */
-#define PPC_PTRACE_PEEKTEXT_3264 0x95
-#define PPC_PTRACE_PEEKDATA_3264 0x94
-#define PPC_PTRACE_POKETEXT_3264 0x93
-#define PPC_PTRACE_POKEDATA_3264 0x92
-#define PPC_PTRACE_PEEKUSR_3264  0x91
-#define PPC_PTRACE_POKEUSR_3264  0x90
-
-#define PTRACE_SINGLEBLOCK	0x100	/* resume execution until next branch */
-
-#define PPC_PTRACE_GETHWDBGINFO	0x89
-#define PPC_PTRACE_SETHWDEBUG	0x88
-#define PPC_PTRACE_DELHWDEBUG	0x87
-
-#ifndef __ASSEMBLY__
-
-struct ppc_debug_info {
-	__u32 version;			/* Only version 1 exists to date */
-	__u32 num_instruction_bps;
-	__u32 num_data_bps;
-	__u32 num_condition_regs;
-	__u32 data_bp_alignment;
-	__u32 sizeof_condition;		/* size of the DVC register */
-	__u64 features;
-};
-
-#endif /* __ASSEMBLY__ */
-
-/*
- * features will have bits indication whether there is support for:
- */
-#define PPC_DEBUG_FEATURE_INSN_BP_RANGE		0x0000000000000001
-#define PPC_DEBUG_FEATURE_INSN_BP_MASK		0x0000000000000002
-#define PPC_DEBUG_FEATURE_DATA_BP_RANGE		0x0000000000000004
-#define PPC_DEBUG_FEATURE_DATA_BP_MASK		0x0000000000000008
-
-#ifndef __ASSEMBLY__
-
-struct ppc_hw_breakpoint {
-	__u32 version;		/* currently, version must be 1 */
-	__u32 trigger_type;	/* only some combinations allowed */
-	__u32 addr_mode;	/* address match mode */
-	__u32 condition_mode;	/* break/watchpoint condition flags */
-	__u64 addr;		/* break/watchpoint address */
-	__u64 addr2;		/* range end or mask */
-	__u64 condition_value;	/* contents of the DVC register */
-};
-
-#endif /* __ASSEMBLY__ */
-
-/*
- * Trigger Type
- */
-#define PPC_BREAKPOINT_TRIGGER_EXECUTE	0x00000001
-#define PPC_BREAKPOINT_TRIGGER_READ	0x00000002
-#define PPC_BREAKPOINT_TRIGGER_WRITE	0x00000004
-#define PPC_BREAKPOINT_TRIGGER_RW	\
-	(PPC_BREAKPOINT_TRIGGER_READ | PPC_BREAKPOINT_TRIGGER_WRITE)
-
-/*
- * Address Mode
- */
-#define PPC_BREAKPOINT_MODE_EXACT		0x00000000
-#define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE	0x00000001
-#define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE	0x00000002
-#define PPC_BREAKPOINT_MODE_MASK		0x00000003
-
-/*
- * Condition Mode
- */
-#define PPC_BREAKPOINT_CONDITION_MODE	0x00000003
-#define PPC_BREAKPOINT_CONDITION_NONE	0x00000000
-#define PPC_BREAKPOINT_CONDITION_AND	0x00000001
-#define PPC_BREAKPOINT_CONDITION_EXACT	PPC_BREAKPOINT_CONDITION_AND
-#define PPC_BREAKPOINT_CONDITION_OR	0x00000002
-#define PPC_BREAKPOINT_CONDITION_AND_OR	0x00000003
-#define PPC_BREAKPOINT_CONDITION_BE_ALL	0x00ff0000
-#define PPC_BREAKPOINT_CONDITION_BE_SHIFT	16
-#define PPC_BREAKPOINT_CONDITION_BE(n)	\
-	(1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT))
-
-#endif /* _ASM_POWERPC_PTRACE_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/qe.h b/ANDROID_3.4.5/arch/powerpc/include/asm/qe.h
deleted file mode 100644
index 5e0b6d51..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/qe.h
+++ /dev/null
@@ -1,739 +0,0 @@
-/*
- * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
- *
- * Authors: 	Shlomi Gridish <gridish@freescale.com>
- * 		Li Yang <leoli@freescale.com>
- *
- * Description:
- * QUICC Engine (QE) external definitions and structure.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-#ifndef _ASM_POWERPC_QE_H
-#define _ASM_POWERPC_QE_H
-#ifdef __KERNEL__
-
-#include <linux/spinlock.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <asm/cpm.h>
-#include <asm/immap_qe.h>
-
-#define QE_NUM_OF_SNUM	256	/* There are 256 serial number in QE */
-#define QE_NUM_OF_BRGS	16
-#define QE_NUM_OF_PORTS	1024
-
-/* Memory partitions
-*/
-#define MEM_PART_SYSTEM		0
-#define MEM_PART_SECONDARY	1
-#define MEM_PART_MURAM		2
-
-/* Clocks and BRGs */
-enum qe_clock {
-	QE_CLK_NONE = 0,
-	QE_BRG1,		/* Baud Rate Generator 1 */
-	QE_BRG2,		/* Baud Rate Generator 2 */
-	QE_BRG3,		/* Baud Rate Generator 3 */
-	QE_BRG4,		/* Baud Rate Generator 4 */
-	QE_BRG5,		/* Baud Rate Generator 5 */
-	QE_BRG6,		/* Baud Rate Generator 6 */
-	QE_BRG7,		/* Baud Rate Generator 7 */
-	QE_BRG8,		/* Baud Rate Generator 8 */
-	QE_BRG9,		/* Baud Rate Generator 9 */
-	QE_BRG10,		/* Baud Rate Generator 10 */
-	QE_BRG11,		/* Baud Rate Generator 11 */
-	QE_BRG12,		/* Baud Rate Generator 12 */
-	QE_BRG13,		/* Baud Rate Generator 13 */
-	QE_BRG14,		/* Baud Rate Generator 14 */
-	QE_BRG15,		/* Baud Rate Generator 15 */
-	QE_BRG16,		/* Baud Rate Generator 16 */
-	QE_CLK1,		/* Clock 1 */
-	QE_CLK2,		/* Clock 2 */
-	QE_CLK3,		/* Clock 3 */
-	QE_CLK4,		/* Clock 4 */
-	QE_CLK5,		/* Clock 5 */
-	QE_CLK6,		/* Clock 6 */
-	QE_CLK7,		/* Clock 7 */
-	QE_CLK8,		/* Clock 8 */
-	QE_CLK9,		/* Clock 9 */
-	QE_CLK10,		/* Clock 10 */
-	QE_CLK11,		/* Clock 11 */
-	QE_CLK12,		/* Clock 12 */
-	QE_CLK13,		/* Clock 13 */
-	QE_CLK14,		/* Clock 14 */
-	QE_CLK15,		/* Clock 15 */
-	QE_CLK16,		/* Clock 16 */
-	QE_CLK17,		/* Clock 17 */
-	QE_CLK18,		/* Clock 18 */
-	QE_CLK19,		/* Clock 19 */
-	QE_CLK20,		/* Clock 20 */
-	QE_CLK21,		/* Clock 21 */
-	QE_CLK22,		/* Clock 22 */
-	QE_CLK23,		/* Clock 23 */
-	QE_CLK24,		/* Clock 24 */
-	QE_CLK_DUMMY
-};
-
-static inline bool qe_clock_is_brg(enum qe_clock clk)
-{
-	return clk >= QE_BRG1 && clk <= QE_BRG16;
-}
-
-extern spinlock_t cmxgcr_lock;
-
-/* Export QE common operations */
-#ifdef CONFIG_QUICC_ENGINE
-extern void qe_reset(void);
-#else
-static inline void qe_reset(void) {}
-#endif
-
-/* QE PIO */
-#define QE_PIO_PINS 32
-
-struct qe_pio_regs {
-	__be32	cpodr;		/* Open drain register */
-	__be32	cpdata;		/* Data register */
-	__be32	cpdir1;		/* Direction register */
-	__be32	cpdir2;		/* Direction register */
-	__be32	cppar1;		/* Pin assignment register */
-	__be32	cppar2;		/* Pin assignment register */
-#ifdef CONFIG_PPC_85xx
-	u8	pad[8];
-#endif
-};
-
-#define QE_PIO_DIR_IN	2
-#define QE_PIO_DIR_OUT	1
-extern void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin,
-				int dir, int open_drain, int assignment,
-				int has_irq);
-#ifdef CONFIG_QUICC_ENGINE
-extern int par_io_init(struct device_node *np);
-extern int par_io_of_config(struct device_node *np);
-extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
-			     int assignment, int has_irq);
-extern int par_io_data_set(u8 port, u8 pin, u8 val);
-#else
-static inline int par_io_init(struct device_node *np) { return -ENOSYS; }
-static inline int par_io_of_config(struct device_node *np) { return -ENOSYS; }
-static inline int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
-		int assignment, int has_irq) { return -ENOSYS; }
-static inline int par_io_data_set(u8 port, u8 pin, u8 val) { return -ENOSYS; }
-#endif /* CONFIG_QUICC_ENGINE */
-
-/*
- * Pin multiplexing functions.
- */
-struct qe_pin;
-#ifdef CONFIG_QE_GPIO
-extern struct qe_pin *qe_pin_request(struct device_node *np, int index);
-extern void qe_pin_free(struct qe_pin *qe_pin);
-extern void qe_pin_set_gpio(struct qe_pin *qe_pin);
-extern void qe_pin_set_dedicated(struct qe_pin *pin);
-#else
-static inline struct qe_pin *qe_pin_request(struct device_node *np, int index)
-{
-	return ERR_PTR(-ENOSYS);
-}
-static inline void qe_pin_free(struct qe_pin *qe_pin) {}
-static inline void qe_pin_set_gpio(struct qe_pin *qe_pin) {}
-static inline void qe_pin_set_dedicated(struct qe_pin *pin) {}
-#endif /* CONFIG_QE_GPIO */
-
-#ifdef CONFIG_QUICC_ENGINE
-int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input);
-#else
-static inline int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol,
-			       u32 cmd_input)
-{
-	return -ENOSYS;
-}
-#endif /* CONFIG_QUICC_ENGINE */
-
-/* QE internal API */
-enum qe_clock qe_clock_source(const char *source);
-unsigned int qe_get_brg_clk(void);
-int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier);
-int qe_get_snum(void);
-void qe_put_snum(u8 snum);
-unsigned int qe_get_num_of_risc(void);
-unsigned int qe_get_num_of_snums(void);
-
-static inline int qe_alive_during_sleep(void)
-{
-	/*
-	 * MPC8568E reference manual says:
-	 *
-	 * "...power down sequence waits for all I/O interfaces to become idle.
-	 *  In some applications this may happen eventually without actively
-	 *  shutting down interfaces, but most likely, software will have to
-	 *  take steps to shut down the eTSEC, QUICC Engine Block, and PCI
-	 *  interfaces before issuing the command (either the write to the core
-	 *  MSR[WE] as described above or writing to POWMGTCSR) to put the
-	 *  device into sleep state."
-	 *
-	 * MPC8569E reference manual has a similar paragraph.
-	 */
-#ifdef CONFIG_PPC_85xx
-	return 0;
-#else
-	return 1;
-#endif
-}
-
-/* we actually use cpm_muram implementation, define this for convenience */
-#define qe_muram_init cpm_muram_init
-#define qe_muram_alloc cpm_muram_alloc
-#define qe_muram_alloc_fixed cpm_muram_alloc_fixed
-#define qe_muram_free cpm_muram_free
-#define qe_muram_addr cpm_muram_addr
-#define qe_muram_offset cpm_muram_offset
-
-/* Structure that defines QE firmware binary files.
- *
- * See Documentation/powerpc/qe_firmware.txt for a description of these
- * fields.
- */
-struct qe_firmware {
-	struct qe_header {
-		__be32 length;  /* Length of the entire structure, in bytes */
-		u8 magic[3];    /* Set to { 'Q', 'E', 'F' } */
-		u8 version;     /* Version of this layout. First ver is '1' */
-	} header;
-	u8 id[62];      /* Null-terminated identifier string */
-	u8 split;	/* 0 = shared I-RAM, 1 = split I-RAM */
-	u8 count;       /* Number of microcode[] structures */
-	struct {
-		__be16 model;   	/* The SOC model  */
-		u8 major;       	/* The SOC revision major */
-		u8 minor;       	/* The SOC revision minor */
-	} __attribute__ ((packed)) soc;
-	u8 padding[4];			/* Reserved, for alignment */
-	__be64 extended_modes;		/* Extended modes */
-	__be32 vtraps[8];		/* Virtual trap addresses */
-	u8 reserved[4];			/* Reserved, for future expansion */
-	struct qe_microcode {
-		u8 id[32];      	/* Null-terminated identifier */
-		__be32 traps[16];       /* Trap addresses, 0 == ignore */
-		__be32 eccr;    	/* The value for the ECCR register */
-		__be32 iram_offset;     /* Offset into I-RAM for the code */
-		__be32 count;   	/* Number of 32-bit words of the code */
-		__be32 code_offset;     /* Offset of the actual microcode */
-		u8 major;       	/* The microcode version major */
-		u8 minor;       	/* The microcode version minor */
-		u8 revision;		/* The microcode version revision */
-		u8 padding;		/* Reserved, for alignment */
-		u8 reserved[4];		/* Reserved, for future expansion */
-	} __attribute__ ((packed)) microcode[1];
-	/* All microcode binaries should be located here */
-	/* CRC32 should be located here, after the microcode binaries */
-} __attribute__ ((packed));
-
-struct qe_firmware_info {
-	char id[64];		/* Firmware name */
-	u32 vtraps[8];		/* Virtual trap addresses */
-	u64 extended_modes;	/* Extended modes */
-};
-
-#ifdef CONFIG_QUICC_ENGINE
-/* Upload a firmware to the QE */
-int qe_upload_firmware(const struct qe_firmware *firmware);
-#else
-static inline int qe_upload_firmware(const struct qe_firmware *firmware)
-{
-	return -ENOSYS;
-}
-#endif /* CONFIG_QUICC_ENGINE */
-
-/* Obtain information on the uploaded firmware */
-struct qe_firmware_info *qe_get_firmware_info(void);
-
-/* QE USB */
-int qe_usb_clock_set(enum qe_clock clk, int rate);
-
-/* Buffer descriptors */
-struct qe_bd {
-	__be16 status;
-	__be16 length;
-	__be32 buf;
-} __attribute__ ((packed));
-
-#define BD_STATUS_MASK	0xffff0000
-#define BD_LENGTH_MASK	0x0000ffff
-
-/* Alignment */
-#define QE_INTR_TABLE_ALIGN	16	/* ??? */
-#define QE_ALIGNMENT_OF_BD	8
-#define QE_ALIGNMENT_OF_PRAM	64
-
-/* RISC allocation */
-#define QE_RISC_ALLOCATION_RISC1	0x1  /* RISC 1 */
-#define QE_RISC_ALLOCATION_RISC2	0x2  /* RISC 2 */
-#define QE_RISC_ALLOCATION_RISC3	0x4  /* RISC 3 */
-#define QE_RISC_ALLOCATION_RISC4	0x8  /* RISC 4 */
-#define QE_RISC_ALLOCATION_RISC1_AND_RISC2	(QE_RISC_ALLOCATION_RISC1 | \
-						 QE_RISC_ALLOCATION_RISC2)
-#define QE_RISC_ALLOCATION_FOUR_RISCS	(QE_RISC_ALLOCATION_RISC1 | \
-					 QE_RISC_ALLOCATION_RISC2 | \
-					 QE_RISC_ALLOCATION_RISC3 | \
-					 QE_RISC_ALLOCATION_RISC4)
-
-/* QE extended filtering Table Lookup Key Size */
-enum qe_fltr_tbl_lookup_key_size {
-	QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES
-		= 0x3f,		/* LookupKey parsed by the Generate LookupKey
-				   CMD is truncated to 8 bytes */
-	QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES
-		= 0x5f,		/* LookupKey parsed by the Generate LookupKey
-				   CMD is truncated to 16 bytes */
-};
-
-/* QE FLTR extended filtering Largest External Table Lookup Key Size */
-enum qe_fltr_largest_external_tbl_lookup_key_size {
-	QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE
-		= 0x0,/* not used */
-	QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES
-		= QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES,	/* 8 bytes */
-	QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES
-		= QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES,	/* 16 bytes */
-};
-
-/* structure representing QE parameter RAM */
-struct qe_timer_tables {
-	u16 tm_base;		/* QE timer table base adr */
-	u16 tm_ptr;		/* QE timer table pointer */
-	u16 r_tmr;		/* QE timer mode register */
-	u16 r_tmv;		/* QE timer valid register */
-	u32 tm_cmd;		/* QE timer cmd register */
-	u32 tm_cnt;		/* QE timer internal cnt */
-} __attribute__ ((packed));
-
-#define QE_FLTR_TAD_SIZE	8
-
-/* QE extended filtering Termination Action Descriptor (TAD) */
-struct qe_fltr_tad {
-	u8 serialized[QE_FLTR_TAD_SIZE];
-} __attribute__ ((packed));
-
-/* Communication Direction */
-enum comm_dir {
-	COMM_DIR_NONE = 0,
-	COMM_DIR_RX = 1,
-	COMM_DIR_TX = 2,
-	COMM_DIR_RX_AND_TX = 3
-};
-
-/* QE CMXUCR Registers.
- * There are two UCCs represented in each of the four CMXUCR registers.
- * These values are for the UCC in the LSBs
- */
-#define QE_CMXUCR_MII_ENET_MNG		0x00007000
-#define QE_CMXUCR_MII_ENET_MNG_SHIFT	12
-#define QE_CMXUCR_GRANT			0x00008000
-#define QE_CMXUCR_TSA			0x00004000
-#define QE_CMXUCR_BKPT			0x00000100
-#define QE_CMXUCR_TX_CLK_SRC_MASK	0x0000000F
-
-/* QE CMXGCR Registers.
-*/
-#define QE_CMXGCR_MII_ENET_MNG		0x00007000
-#define QE_CMXGCR_MII_ENET_MNG_SHIFT	12
-#define QE_CMXGCR_USBCS			0x0000000f
-#define QE_CMXGCR_USBCS_CLK3		0x1
-#define QE_CMXGCR_USBCS_CLK5		0x2
-#define QE_CMXGCR_USBCS_CLK7		0x3
-#define QE_CMXGCR_USBCS_CLK9		0x4
-#define QE_CMXGCR_USBCS_CLK13		0x5
-#define QE_CMXGCR_USBCS_CLK17		0x6
-#define QE_CMXGCR_USBCS_CLK19		0x7
-#define QE_CMXGCR_USBCS_CLK21		0x8
-#define QE_CMXGCR_USBCS_BRG9		0x9
-#define QE_CMXGCR_USBCS_BRG10		0xa
-
-/* QE CECR Commands.
-*/
-#define QE_CR_FLG			0x00010000
-#define QE_RESET			0x80000000
-#define QE_INIT_TX_RX			0x00000000
-#define QE_INIT_RX			0x00000001
-#define QE_INIT_TX			0x00000002
-#define QE_ENTER_HUNT_MODE		0x00000003
-#define QE_STOP_TX			0x00000004
-#define QE_GRACEFUL_STOP_TX		0x00000005
-#define QE_RESTART_TX			0x00000006
-#define QE_CLOSE_RX_BD			0x00000007
-#define QE_SWITCH_COMMAND		0x00000007
-#define QE_SET_GROUP_ADDRESS		0x00000008
-#define QE_START_IDMA			0x00000009
-#define QE_MCC_STOP_RX			0x00000009
-#define QE_ATM_TRANSMIT			0x0000000a
-#define QE_HPAC_CLEAR_ALL		0x0000000b
-#define QE_GRACEFUL_STOP_RX		0x0000001a
-#define QE_RESTART_RX			0x0000001b
-#define QE_HPAC_SET_PRIORITY		0x0000010b
-#define QE_HPAC_STOP_TX			0x0000020b
-#define QE_HPAC_STOP_RX			0x0000030b
-#define QE_HPAC_GRACEFUL_STOP_TX	0x0000040b
-#define QE_HPAC_GRACEFUL_STOP_RX	0x0000050b
-#define QE_HPAC_START_TX		0x0000060b
-#define QE_HPAC_START_RX		0x0000070b
-#define QE_USB_STOP_TX			0x0000000a
-#define QE_USB_RESTART_TX		0x0000000c
-#define QE_QMC_STOP_TX			0x0000000c
-#define QE_QMC_STOP_RX			0x0000000d
-#define QE_SS7_SU_FIL_RESET		0x0000000e
-/* jonathbr added from here down for 83xx */
-#define QE_RESET_BCS			0x0000000a
-#define QE_MCC_INIT_TX_RX_16		0x00000003
-#define QE_MCC_STOP_TX			0x00000004
-#define QE_MCC_INIT_TX_1		0x00000005
-#define QE_MCC_INIT_RX_1		0x00000006
-#define QE_MCC_RESET			0x00000007
-#define QE_SET_TIMER			0x00000008
-#define QE_RANDOM_NUMBER		0x0000000c
-#define QE_ATM_MULTI_THREAD_INIT	0x00000011
-#define QE_ASSIGN_PAGE			0x00000012
-#define QE_ADD_REMOVE_HASH_ENTRY	0x00000013
-#define QE_START_FLOW_CONTROL		0x00000014
-#define QE_STOP_FLOW_CONTROL		0x00000015
-#define QE_ASSIGN_PAGE_TO_DEVICE	0x00000016
-
-#define QE_ASSIGN_RISC			0x00000010
-#define QE_CR_MCN_NORMAL_SHIFT		6
-#define QE_CR_MCN_USB_SHIFT		4
-#define QE_CR_MCN_RISC_ASSIGN_SHIFT	8
-#define QE_CR_SNUM_SHIFT		17
-
-/* QE CECR Sub Block - sub block of QE command.
-*/
-#define QE_CR_SUBBLOCK_INVALID		0x00000000
-#define QE_CR_SUBBLOCK_USB		0x03200000
-#define QE_CR_SUBBLOCK_UCCFAST1		0x02000000
-#define QE_CR_SUBBLOCK_UCCFAST2		0x02200000
-#define QE_CR_SUBBLOCK_UCCFAST3		0x02400000
-#define QE_CR_SUBBLOCK_UCCFAST4		0x02600000
-#define QE_CR_SUBBLOCK_UCCFAST5		0x02800000
-#define QE_CR_SUBBLOCK_UCCFAST6		0x02a00000
-#define QE_CR_SUBBLOCK_UCCFAST7		0x02c00000
-#define QE_CR_SUBBLOCK_UCCFAST8		0x02e00000
-#define QE_CR_SUBBLOCK_UCCSLOW1		0x00000000
-#define QE_CR_SUBBLOCK_UCCSLOW2		0x00200000
-#define QE_CR_SUBBLOCK_UCCSLOW3		0x00400000
-#define QE_CR_SUBBLOCK_UCCSLOW4		0x00600000
-#define QE_CR_SUBBLOCK_UCCSLOW5		0x00800000
-#define QE_CR_SUBBLOCK_UCCSLOW6		0x00a00000
-#define QE_CR_SUBBLOCK_UCCSLOW7		0x00c00000
-#define QE_CR_SUBBLOCK_UCCSLOW8		0x00e00000
-#define QE_CR_SUBBLOCK_MCC1		0x03800000
-#define QE_CR_SUBBLOCK_MCC2		0x03a00000
-#define QE_CR_SUBBLOCK_MCC3		0x03000000
-#define QE_CR_SUBBLOCK_IDMA1		0x02800000
-#define QE_CR_SUBBLOCK_IDMA2		0x02a00000
-#define QE_CR_SUBBLOCK_IDMA3		0x02c00000
-#define QE_CR_SUBBLOCK_IDMA4		0x02e00000
-#define QE_CR_SUBBLOCK_HPAC		0x01e00000
-#define QE_CR_SUBBLOCK_SPI1		0x01400000
-#define QE_CR_SUBBLOCK_SPI2		0x01600000
-#define QE_CR_SUBBLOCK_RAND		0x01c00000
-#define QE_CR_SUBBLOCK_TIMER		0x01e00000
-#define QE_CR_SUBBLOCK_GENERAL		0x03c00000
-
-/* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command */
-#define QE_CR_PROTOCOL_UNSPECIFIED	0x00	/* For all other protocols */
-#define QE_CR_PROTOCOL_HDLC_TRANSPARENT	0x00
-#define QE_CR_PROTOCOL_QMC		0x02
-#define QE_CR_PROTOCOL_UART		0x04
-#define QE_CR_PROTOCOL_ATM_POS		0x0A
-#define QE_CR_PROTOCOL_ETHERNET		0x0C
-#define QE_CR_PROTOCOL_L2_SWITCH	0x0D
-
-/* BRG configuration register */
-#define QE_BRGC_ENABLE		0x00010000
-#define QE_BRGC_DIVISOR_SHIFT	1
-#define QE_BRGC_DIVISOR_MAX	0xFFF
-#define QE_BRGC_DIV16		1
-
-/* QE Timers registers */
-#define QE_GTCFR1_PCAS	0x80
-#define QE_GTCFR1_STP2	0x20
-#define QE_GTCFR1_RST2	0x10
-#define QE_GTCFR1_GM2	0x08
-#define QE_GTCFR1_GM1	0x04
-#define QE_GTCFR1_STP1	0x02
-#define QE_GTCFR1_RST1	0x01
-
-/* SDMA registers */
-#define QE_SDSR_BER1	0x02000000
-#define QE_SDSR_BER2	0x01000000
-
-#define QE_SDMR_GLB_1_MSK	0x80000000
-#define QE_SDMR_ADR_SEL		0x20000000
-#define QE_SDMR_BER1_MSK	0x02000000
-#define QE_SDMR_BER2_MSK	0x01000000
-#define QE_SDMR_EB1_MSK		0x00800000
-#define QE_SDMR_ER1_MSK		0x00080000
-#define QE_SDMR_ER2_MSK		0x00040000
-#define QE_SDMR_CEN_MASK	0x0000E000
-#define QE_SDMR_SBER_1		0x00000200
-#define QE_SDMR_SBER_2		0x00000200
-#define QE_SDMR_EB1_PR_MASK	0x000000C0
-#define QE_SDMR_ER1_PR		0x00000008
-
-#define QE_SDMR_CEN_SHIFT	13
-#define QE_SDMR_EB1_PR_SHIFT	6
-
-#define QE_SDTM_MSNUM_SHIFT	24
-
-#define QE_SDEBCR_BA_MASK	0x01FFFFFF
-
-/* Communication Processor */
-#define QE_CP_CERCR_MEE		0x8000	/* Multi-user RAM ECC enable */
-#define QE_CP_CERCR_IEE		0x4000	/* Instruction RAM ECC enable */
-#define QE_CP_CERCR_CIR		0x0800	/* Common instruction RAM */
-
-/* I-RAM */
-#define QE_IRAM_IADD_AIE	0x80000000	/* Auto Increment Enable */
-#define QE_IRAM_IADD_BADDR	0x00080000	/* Base Address */
-
-/* UPC */
-#define UPGCR_PROTOCOL	0x80000000	/* protocol ul2 or pl2 */
-#define UPGCR_TMS	0x40000000	/* Transmit master/slave mode */
-#define UPGCR_RMS	0x20000000	/* Receive master/slave mode */
-#define UPGCR_ADDR	0x10000000	/* Master MPHY Addr multiplexing */
-#define UPGCR_DIAG	0x01000000	/* Diagnostic mode */
-
-/* UCC GUEMR register */
-#define UCC_GUEMR_MODE_MASK_RX	0x02
-#define UCC_GUEMR_MODE_FAST_RX	0x02
-#define UCC_GUEMR_MODE_SLOW_RX	0x00
-#define UCC_GUEMR_MODE_MASK_TX	0x01
-#define UCC_GUEMR_MODE_FAST_TX	0x01
-#define UCC_GUEMR_MODE_SLOW_TX	0x00
-#define UCC_GUEMR_MODE_MASK (UCC_GUEMR_MODE_MASK_RX | UCC_GUEMR_MODE_MASK_TX)
-#define UCC_GUEMR_SET_RESERVED3	0x10	/* Bit 3 in the guemr is reserved but
-					   must be set 1 */
-
-/* structure representing UCC SLOW parameter RAM */
-struct ucc_slow_pram {
-	__be16 rbase;		/* RX BD base address */
-	__be16 tbase;		/* TX BD base address */
-	u8 rbmr;		/* RX bus mode register (same as CPM's RFCR) */
-	u8 tbmr;		/* TX bus mode register (same as CPM's TFCR) */
-	__be16 mrblr;		/* Rx buffer length */
-	__be32 rstate;		/* Rx internal state */
-	__be32 rptr;		/* Rx internal data pointer */
-	__be16 rbptr;		/* rb BD Pointer */
-	__be16 rcount;		/* Rx internal byte count */
-	__be32 rtemp;		/* Rx temp */
-	__be32 tstate;		/* Tx internal state */
-	__be32 tptr;		/* Tx internal data pointer */
-	__be16 tbptr;		/* Tx BD pointer */
-	__be16 tcount;		/* Tx byte count */
-	__be32 ttemp;		/* Tx temp */
-	__be32 rcrc;		/* temp receive CRC */
-	__be32 tcrc;		/* temp transmit CRC */
-} __attribute__ ((packed));
-
-/* General UCC SLOW Mode Register (GUMRH & GUMRL) */
-#define UCC_SLOW_GUMR_H_SAM_QMC		0x00000000
-#define UCC_SLOW_GUMR_H_SAM_SATM	0x00008000
-#define UCC_SLOW_GUMR_H_REVD		0x00002000
-#define UCC_SLOW_GUMR_H_TRX		0x00001000
-#define UCC_SLOW_GUMR_H_TTX		0x00000800
-#define UCC_SLOW_GUMR_H_CDP		0x00000400
-#define UCC_SLOW_GUMR_H_CTSP		0x00000200
-#define UCC_SLOW_GUMR_H_CDS		0x00000100
-#define UCC_SLOW_GUMR_H_CTSS		0x00000080
-#define UCC_SLOW_GUMR_H_TFL		0x00000040
-#define UCC_SLOW_GUMR_H_RFW		0x00000020
-#define UCC_SLOW_GUMR_H_TXSY		0x00000010
-#define UCC_SLOW_GUMR_H_4SYNC		0x00000004
-#define UCC_SLOW_GUMR_H_8SYNC		0x00000008
-#define UCC_SLOW_GUMR_H_16SYNC		0x0000000c
-#define UCC_SLOW_GUMR_H_RTSM		0x00000002
-#define UCC_SLOW_GUMR_H_RSYN		0x00000001
-
-#define UCC_SLOW_GUMR_L_TCI		0x10000000
-#define UCC_SLOW_GUMR_L_RINV		0x02000000
-#define UCC_SLOW_GUMR_L_TINV		0x01000000
-#define UCC_SLOW_GUMR_L_TEND		0x00040000
-#define UCC_SLOW_GUMR_L_TDCR_MASK	0x00030000
-#define UCC_SLOW_GUMR_L_TDCR_32	        0x00030000
-#define UCC_SLOW_GUMR_L_TDCR_16	        0x00020000
-#define UCC_SLOW_GUMR_L_TDCR_8	        0x00010000
-#define UCC_SLOW_GUMR_L_TDCR_1	        0x00000000
-#define UCC_SLOW_GUMR_L_RDCR_MASK	0x0000c000
-#define UCC_SLOW_GUMR_L_RDCR_32		0x0000c000
-#define UCC_SLOW_GUMR_L_RDCR_16	        0x00008000
-#define UCC_SLOW_GUMR_L_RDCR_8	        0x00004000
-#define UCC_SLOW_GUMR_L_RDCR_1		0x00000000
-#define UCC_SLOW_GUMR_L_RENC_NRZI	0x00000800
-#define UCC_SLOW_GUMR_L_RENC_NRZ	0x00000000
-#define UCC_SLOW_GUMR_L_TENC_NRZI	0x00000100
-#define UCC_SLOW_GUMR_L_TENC_NRZ	0x00000000
-#define UCC_SLOW_GUMR_L_DIAG_MASK	0x000000c0
-#define UCC_SLOW_GUMR_L_DIAG_LE	        0x000000c0
-#define UCC_SLOW_GUMR_L_DIAG_ECHO	0x00000080
-#define UCC_SLOW_GUMR_L_DIAG_LOOP	0x00000040
-#define UCC_SLOW_GUMR_L_DIAG_NORM	0x00000000
-#define UCC_SLOW_GUMR_L_ENR		0x00000020
-#define UCC_SLOW_GUMR_L_ENT		0x00000010
-#define UCC_SLOW_GUMR_L_MODE_MASK	0x0000000F
-#define UCC_SLOW_GUMR_L_MODE_BISYNC	0x00000008
-#define UCC_SLOW_GUMR_L_MODE_AHDLC	0x00000006
-#define UCC_SLOW_GUMR_L_MODE_UART	0x00000004
-#define UCC_SLOW_GUMR_L_MODE_QMC	0x00000002
-
-/* General UCC FAST Mode Register */
-#define UCC_FAST_GUMR_TCI	0x20000000
-#define UCC_FAST_GUMR_TRX	0x10000000
-#define UCC_FAST_GUMR_TTX	0x08000000
-#define UCC_FAST_GUMR_CDP	0x04000000
-#define UCC_FAST_GUMR_CTSP	0x02000000
-#define UCC_FAST_GUMR_CDS	0x01000000
-#define UCC_FAST_GUMR_CTSS	0x00800000
-#define UCC_FAST_GUMR_TXSY	0x00020000
-#define UCC_FAST_GUMR_RSYN	0x00010000
-#define UCC_FAST_GUMR_RTSM	0x00002000
-#define UCC_FAST_GUMR_REVD	0x00000400
-#define UCC_FAST_GUMR_ENR	0x00000020
-#define UCC_FAST_GUMR_ENT	0x00000010
-
-/* UART Slow UCC Event Register (UCCE) */
-#define UCC_UART_UCCE_AB	0x0200
-#define UCC_UART_UCCE_IDLE	0x0100
-#define UCC_UART_UCCE_GRA	0x0080
-#define UCC_UART_UCCE_BRKE	0x0040
-#define UCC_UART_UCCE_BRKS	0x0020
-#define UCC_UART_UCCE_CCR	0x0008
-#define UCC_UART_UCCE_BSY	0x0004
-#define UCC_UART_UCCE_TX	0x0002
-#define UCC_UART_UCCE_RX	0x0001
-
-/* HDLC Slow UCC Event Register (UCCE) */
-#define UCC_HDLC_UCCE_GLR	0x1000
-#define UCC_HDLC_UCCE_GLT	0x0800
-#define UCC_HDLC_UCCE_IDLE	0x0100
-#define UCC_HDLC_UCCE_BRKE	0x0040
-#define UCC_HDLC_UCCE_BRKS	0x0020
-#define UCC_HDLC_UCCE_TXE	0x0010
-#define UCC_HDLC_UCCE_RXF	0x0008
-#define UCC_HDLC_UCCE_BSY	0x0004
-#define UCC_HDLC_UCCE_TXB	0x0002
-#define UCC_HDLC_UCCE_RXB	0x0001
-
-/* BISYNC Slow UCC Event Register (UCCE) */
-#define UCC_BISYNC_UCCE_GRA	0x0080
-#define UCC_BISYNC_UCCE_TXE	0x0010
-#define UCC_BISYNC_UCCE_RCH	0x0008
-#define UCC_BISYNC_UCCE_BSY	0x0004
-#define UCC_BISYNC_UCCE_TXB	0x0002
-#define UCC_BISYNC_UCCE_RXB	0x0001
-
-/* Gigabit Ethernet Fast UCC Event Register (UCCE) */
-#define UCC_GETH_UCCE_MPD       0x80000000
-#define UCC_GETH_UCCE_SCAR      0x40000000
-#define UCC_GETH_UCCE_GRA       0x20000000
-#define UCC_GETH_UCCE_CBPR      0x10000000
-#define UCC_GETH_UCCE_BSY       0x08000000
-#define UCC_GETH_UCCE_RXC       0x04000000
-#define UCC_GETH_UCCE_TXC       0x02000000
-#define UCC_GETH_UCCE_TXE       0x01000000
-#define UCC_GETH_UCCE_TXB7      0x00800000
-#define UCC_GETH_UCCE_TXB6      0x00400000
-#define UCC_GETH_UCCE_TXB5      0x00200000
-#define UCC_GETH_UCCE_TXB4      0x00100000
-#define UCC_GETH_UCCE_TXB3      0x00080000
-#define UCC_GETH_UCCE_TXB2      0x00040000
-#define UCC_GETH_UCCE_TXB1      0x00020000
-#define UCC_GETH_UCCE_TXB0      0x00010000
-#define UCC_GETH_UCCE_RXB7      0x00008000
-#define UCC_GETH_UCCE_RXB6      0x00004000
-#define UCC_GETH_UCCE_RXB5      0x00002000
-#define UCC_GETH_UCCE_RXB4      0x00001000
-#define UCC_GETH_UCCE_RXB3      0x00000800
-#define UCC_GETH_UCCE_RXB2      0x00000400
-#define UCC_GETH_UCCE_RXB1      0x00000200
-#define UCC_GETH_UCCE_RXB0      0x00000100
-#define UCC_GETH_UCCE_RXF7      0x00000080
-#define UCC_GETH_UCCE_RXF6      0x00000040
-#define UCC_GETH_UCCE_RXF5      0x00000020
-#define UCC_GETH_UCCE_RXF4      0x00000010
-#define UCC_GETH_UCCE_RXF3      0x00000008
-#define UCC_GETH_UCCE_RXF2      0x00000004
-#define UCC_GETH_UCCE_RXF1      0x00000002
-#define UCC_GETH_UCCE_RXF0      0x00000001
-
-/* UCC Protocol Specific Mode Register (UPSMR), when used for UART */
-#define UCC_UART_UPSMR_FLC		0x8000
-#define UCC_UART_UPSMR_SL		0x4000
-#define UCC_UART_UPSMR_CL_MASK		0x3000
-#define UCC_UART_UPSMR_CL_8		0x3000
-#define UCC_UART_UPSMR_CL_7		0x2000
-#define UCC_UART_UPSMR_CL_6		0x1000
-#define UCC_UART_UPSMR_CL_5		0x0000
-#define UCC_UART_UPSMR_UM_MASK		0x0c00
-#define UCC_UART_UPSMR_UM_NORMAL	0x0000
-#define UCC_UART_UPSMR_UM_MAN_MULTI	0x0400
-#define UCC_UART_UPSMR_UM_AUTO_MULTI	0x0c00
-#define UCC_UART_UPSMR_FRZ		0x0200
-#define UCC_UART_UPSMR_RZS		0x0100
-#define UCC_UART_UPSMR_SYN		0x0080
-#define UCC_UART_UPSMR_DRT		0x0040
-#define UCC_UART_UPSMR_PEN		0x0010
-#define UCC_UART_UPSMR_RPM_MASK		0x000c
-#define UCC_UART_UPSMR_RPM_ODD		0x0000
-#define UCC_UART_UPSMR_RPM_LOW		0x0004
-#define UCC_UART_UPSMR_RPM_EVEN		0x0008
-#define UCC_UART_UPSMR_RPM_HIGH		0x000C
-#define UCC_UART_UPSMR_TPM_MASK		0x0003
-#define UCC_UART_UPSMR_TPM_ODD		0x0000
-#define UCC_UART_UPSMR_TPM_LOW		0x0001
-#define UCC_UART_UPSMR_TPM_EVEN		0x0002
-#define UCC_UART_UPSMR_TPM_HIGH		0x0003
-
-/* UCC Protocol Specific Mode Register (UPSMR), when used for Ethernet */
-#define UCC_GETH_UPSMR_FTFE     0x80000000
-#define UCC_GETH_UPSMR_PTPE     0x40000000
-#define UCC_GETH_UPSMR_ECM      0x04000000
-#define UCC_GETH_UPSMR_HSE      0x02000000
-#define UCC_GETH_UPSMR_PRO      0x00400000
-#define UCC_GETH_UPSMR_CAP      0x00200000
-#define UCC_GETH_UPSMR_RSH      0x00100000
-#define UCC_GETH_UPSMR_RPM      0x00080000
-#define UCC_GETH_UPSMR_R10M     0x00040000
-#define UCC_GETH_UPSMR_RLPB     0x00020000
-#define UCC_GETH_UPSMR_TBIM     0x00010000
-#define UCC_GETH_UPSMR_RES1     0x00002000
-#define UCC_GETH_UPSMR_RMM      0x00001000
-#define UCC_GETH_UPSMR_CAM      0x00000400
-#define UCC_GETH_UPSMR_BRO      0x00000200
-#define UCC_GETH_UPSMR_SMM	0x00000080
-#define UCC_GETH_UPSMR_SGMM	0x00000020
-
-/* UCC Transmit On Demand Register (UTODR) */
-#define UCC_SLOW_TOD	0x8000
-#define UCC_FAST_TOD	0x8000
-
-/* UCC Bus Mode Register masks */
-/* Not to be confused with the Bundle Mode Register */
-#define UCC_BMR_GBL		0x20
-#define UCC_BMR_BO_BE		0x10
-#define UCC_BMR_CETM		0x04
-#define UCC_BMR_DTB		0x02
-#define UCC_BMR_BDB		0x01
-
-/* Function code masks */
-#define FC_GBL				0x20
-#define FC_DTB_LCL			0x02
-#define UCC_FAST_FUNCTION_CODE_GBL	0x20
-#define UCC_FAST_FUNCTION_CODE_DTB_LCL	0x02
-#define UCC_FAST_FUNCTION_CODE_BDB_LCL	0x01
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_QE_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/qe_ic.h b/ANDROID_3.4.5/arch/powerpc/include/asm/qe_ic.h
deleted file mode 100644
index f706164b..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/qe_ic.h
+++ /dev/null
@@ -1,144 +0,0 @@
-/*
- * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
- *
- * Authors: 	Shlomi Gridish <gridish@freescale.com>
- * 		Li Yang <leoli@freescale.com>
- *
- * Description:
- * QE IC external definitions and structure.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-#ifndef _ASM_POWERPC_QE_IC_H
-#define _ASM_POWERPC_QE_IC_H
-
-#include <linux/irq.h>
-
-struct device_node;
-struct qe_ic;
-
-#define NUM_OF_QE_IC_GROUPS	6
-
-/* Flags when we init the QE IC */
-#define QE_IC_SPREADMODE_GRP_W			0x00000001
-#define QE_IC_SPREADMODE_GRP_X			0x00000002
-#define QE_IC_SPREADMODE_GRP_Y			0x00000004
-#define QE_IC_SPREADMODE_GRP_Z			0x00000008
-#define QE_IC_SPREADMODE_GRP_RISCA		0x00000010
-#define QE_IC_SPREADMODE_GRP_RISCB		0x00000020
-
-#define QE_IC_LOW_SIGNAL			0x00000100
-#define QE_IC_HIGH_SIGNAL			0x00000200
-
-#define QE_IC_GRP_W_PRI0_DEST_SIGNAL_HIGH	0x00001000
-#define QE_IC_GRP_W_PRI1_DEST_SIGNAL_HIGH	0x00002000
-#define QE_IC_GRP_X_PRI0_DEST_SIGNAL_HIGH	0x00004000
-#define QE_IC_GRP_X_PRI1_DEST_SIGNAL_HIGH	0x00008000
-#define QE_IC_GRP_Y_PRI0_DEST_SIGNAL_HIGH	0x00010000
-#define QE_IC_GRP_Y_PRI1_DEST_SIGNAL_HIGH	0x00020000
-#define QE_IC_GRP_Z_PRI0_DEST_SIGNAL_HIGH	0x00040000
-#define QE_IC_GRP_Z_PRI1_DEST_SIGNAL_HIGH	0x00080000
-#define QE_IC_GRP_RISCA_PRI0_DEST_SIGNAL_HIGH	0x00100000
-#define QE_IC_GRP_RISCA_PRI1_DEST_SIGNAL_HIGH	0x00200000
-#define QE_IC_GRP_RISCB_PRI0_DEST_SIGNAL_HIGH	0x00400000
-#define QE_IC_GRP_RISCB_PRI1_DEST_SIGNAL_HIGH	0x00800000
-#define QE_IC_GRP_W_DEST_SIGNAL_SHIFT		(12)
-
-/* QE interrupt sources groups */
-enum qe_ic_grp_id {
-	QE_IC_GRP_W = 0,	/* QE interrupt controller group W */
-	QE_IC_GRP_X,		/* QE interrupt controller group X */
-	QE_IC_GRP_Y,		/* QE interrupt controller group Y */
-	QE_IC_GRP_Z,		/* QE interrupt controller group Z */
-	QE_IC_GRP_RISCA,	/* QE interrupt controller RISC group A */
-	QE_IC_GRP_RISCB		/* QE interrupt controller RISC group B */
-};
-
-#ifdef CONFIG_QUICC_ENGINE
-void qe_ic_init(struct device_node *node, unsigned int flags,
-		void (*low_handler)(unsigned int irq, struct irq_desc *desc),
-		void (*high_handler)(unsigned int irq, struct irq_desc *desc));
-unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic);
-unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic);
-#else
-static inline void qe_ic_init(struct device_node *node, unsigned int flags,
-		void (*low_handler)(unsigned int irq, struct irq_desc *desc),
-		void (*high_handler)(unsigned int irq, struct irq_desc *desc))
-{}
-static inline unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
-{ return 0; }
-static inline unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
-{ return 0; }
-#endif /* CONFIG_QUICC_ENGINE */
-
-void qe_ic_set_highest_priority(unsigned int virq, int high);
-int qe_ic_set_priority(unsigned int virq, unsigned int priority);
-int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high);
-
-static inline void qe_ic_cascade_low_ipic(unsigned int irq,
-					  struct irq_desc *desc)
-{
-	struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
-	unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
-
-	if (cascade_irq != NO_IRQ)
-		generic_handle_irq(cascade_irq);
-}
-
-static inline void qe_ic_cascade_high_ipic(unsigned int irq,
-					   struct irq_desc *desc)
-{
-	struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
-	unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
-
-	if (cascade_irq != NO_IRQ)
-		generic_handle_irq(cascade_irq);
-}
-
-static inline void qe_ic_cascade_low_mpic(unsigned int irq,
-					  struct irq_desc *desc)
-{
-	struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
-	unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
-	struct irq_chip *chip = irq_desc_get_chip(desc);
-
-	if (cascade_irq != NO_IRQ)
-		generic_handle_irq(cascade_irq);
-
-	chip->irq_eoi(&desc->irq_data);
-}
-
-static inline void qe_ic_cascade_high_mpic(unsigned int irq,
-					   struct irq_desc *desc)
-{
-	struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
-	unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
-	struct irq_chip *chip = irq_desc_get_chip(desc);
-
-	if (cascade_irq != NO_IRQ)
-		generic_handle_irq(cascade_irq);
-
-	chip->irq_eoi(&desc->irq_data);
-}
-
-static inline void qe_ic_cascade_muxed_mpic(unsigned int irq,
-					    struct irq_desc *desc)
-{
-	struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
-	unsigned int cascade_irq;
-	struct irq_chip *chip = irq_desc_get_chip(desc);
-
-	cascade_irq = qe_ic_get_high_irq(qe_ic);
-	if (cascade_irq == NO_IRQ)
-		cascade_irq = qe_ic_get_low_irq(qe_ic);
-
-	if (cascade_irq != NO_IRQ)
-		generic_handle_irq(cascade_irq);
-
-	chip->irq_eoi(&desc->irq_data);
-}
-
-#endif /* _ASM_POWERPC_QE_IC_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/reg.h b/ANDROID_3.4.5/arch/powerpc/include/asm/reg.h
deleted file mode 100644
index 9d7f0fb6..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/reg.h
+++ /dev/null
@@ -1,1099 +0,0 @@
-/*
- * Contains the definition of registers common to all PowerPC variants.
- * If a register definition has been changed in a different PowerPC
- * variant, we will case it in #ifndef XXX ... #endif, and have the
- * number used in the Programming Environments Manual For 32-Bit
- * Implementations of the PowerPC Architecture (a.k.a. Green Book) here.
- */
-
-#ifndef _ASM_POWERPC_REG_H
-#define _ASM_POWERPC_REG_H
-#ifdef __KERNEL__
-
-#include <linux/stringify.h>
-#include <asm/cputable.h>
-
-/* Pickup Book E specific registers. */
-#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
-#include <asm/reg_booke.h>
-#endif /* CONFIG_BOOKE || CONFIG_40x */
-
-#ifdef CONFIG_FSL_EMB_PERFMON
-#include <asm/reg_fsl_emb.h>
-#endif
-
-#ifdef CONFIG_8xx
-#include <asm/reg_8xx.h>
-#endif /* CONFIG_8xx */
-
-#define MSR_SF_LG	63              /* Enable 64 bit mode */
-#define MSR_ISF_LG	61              /* Interrupt 64b mode valid on 630 */
-#define MSR_HV_LG 	60              /* Hypervisor state */
-#define MSR_VEC_LG	25	        /* Enable AltiVec */
-#define MSR_VSX_LG	23		/* Enable VSX */
-#define MSR_POW_LG	18		/* Enable Power Management */
-#define MSR_WE_LG	18		/* Wait State Enable */
-#define MSR_TGPR_LG	17		/* TLB Update registers in use */
-#define MSR_CE_LG	17		/* Critical Interrupt Enable */
-#define MSR_ILE_LG	16		/* Interrupt Little Endian */
-#define MSR_EE_LG	15		/* External Interrupt Enable */
-#define MSR_PR_LG	14		/* Problem State / Privilege Level */
-#define MSR_FP_LG	13		/* Floating Point enable */
-#define MSR_ME_LG	12		/* Machine Check Enable */
-#define MSR_FE0_LG	11		/* Floating Exception mode 0 */
-#define MSR_SE_LG	10		/* Single Step */
-#define MSR_BE_LG	9		/* Branch Trace */
-#define MSR_DE_LG	9 		/* Debug Exception Enable */
-#define MSR_FE1_LG	8		/* Floating Exception mode 1 */
-#define MSR_IP_LG	6		/* Exception prefix 0x000/0xFFF */
-#define MSR_IR_LG	5 		/* Instruction Relocate */
-#define MSR_DR_LG	4 		/* Data Relocate */
-#define MSR_PE_LG	3		/* Protection Enable */
-#define MSR_PX_LG	2		/* Protection Exclusive Mode */
-#define MSR_PMM_LG	2		/* Performance monitor */
-#define MSR_RI_LG	1		/* Recoverable Exception */
-#define MSR_LE_LG	0 		/* Little Endian */
-
-#ifdef __ASSEMBLY__
-#define __MASK(X)	(1<<(X))
-#else
-#define __MASK(X)	(1UL<<(X))
-#endif
-
-#ifdef CONFIG_PPC64
-#define MSR_SF		__MASK(MSR_SF_LG)	/* Enable 64 bit mode */
-#define MSR_ISF		__MASK(MSR_ISF_LG)	/* Interrupt 64b mode valid on 630 */
-#define MSR_HV 		__MASK(MSR_HV_LG)	/* Hypervisor state */
-#else
-/* so tests for these bits fail on 32-bit */
-#define MSR_SF		0
-#define MSR_ISF		0
-#define MSR_HV		0
-#endif
-
-#define MSR_VEC		__MASK(MSR_VEC_LG)	/* Enable AltiVec */
-#define MSR_VSX		__MASK(MSR_VSX_LG)	/* Enable VSX */
-#define MSR_POW		__MASK(MSR_POW_LG)	/* Enable Power Management */
-#define MSR_WE		__MASK(MSR_WE_LG)	/* Wait State Enable */
-#define MSR_TGPR	__MASK(MSR_TGPR_LG)	/* TLB Update registers in use */
-#define MSR_CE		__MASK(MSR_CE_LG)	/* Critical Interrupt Enable */
-#define MSR_ILE		__MASK(MSR_ILE_LG)	/* Interrupt Little Endian */
-#define MSR_EE		__MASK(MSR_EE_LG)	/* External Interrupt Enable */
-#define MSR_PR		__MASK(MSR_PR_LG)	/* Problem State / Privilege Level */
-#define MSR_FP		__MASK(MSR_FP_LG)	/* Floating Point enable */
-#define MSR_ME		__MASK(MSR_ME_LG)	/* Machine Check Enable */
-#define MSR_FE0		__MASK(MSR_FE0_LG)	/* Floating Exception mode 0 */
-#define MSR_SE		__MASK(MSR_SE_LG)	/* Single Step */
-#define MSR_BE		__MASK(MSR_BE_LG)	/* Branch Trace */
-#define MSR_DE		__MASK(MSR_DE_LG)	/* Debug Exception Enable */
-#define MSR_FE1		__MASK(MSR_FE1_LG)	/* Floating Exception mode 1 */
-#define MSR_IP		__MASK(MSR_IP_LG)	/* Exception prefix 0x000/0xFFF */
-#define MSR_IR		__MASK(MSR_IR_LG)	/* Instruction Relocate */
-#define MSR_DR		__MASK(MSR_DR_LG)	/* Data Relocate */
-#define MSR_PE		__MASK(MSR_PE_LG)	/* Protection Enable */
-#define MSR_PX		__MASK(MSR_PX_LG)	/* Protection Exclusive Mode */
-#ifndef MSR_PMM
-#define MSR_PMM		__MASK(MSR_PMM_LG)	/* Performance monitor */
-#endif
-#define MSR_RI		__MASK(MSR_RI_LG)	/* Recoverable Exception */
-#define MSR_LE		__MASK(MSR_LE_LG)	/* Little Endian */
-
-#if defined(CONFIG_PPC_BOOK3S_64)
-#define MSR_64BIT	MSR_SF
-
-/* Server variant */
-#define MSR_		MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF |MSR_HV
-#define MSR_KERNEL	MSR_ | MSR_64BIT
-#define MSR_USER32	MSR_ | MSR_PR | MSR_EE
-#define MSR_USER64	MSR_USER32 | MSR_64BIT
-#elif defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_8xx)
-/* Default MSR for kernel mode. */
-#define MSR_KERNEL	(MSR_ME|MSR_RI|MSR_IR|MSR_DR)
-#define MSR_USER	(MSR_KERNEL|MSR_PR|MSR_EE)
-#endif
-
-#ifndef MSR_64BIT
-#define MSR_64BIT	0
-#endif
-
-/* Floating Point Status and Control Register (FPSCR) Fields */
-#define FPSCR_FX	0x80000000	/* FPU exception summary */
-#define FPSCR_FEX	0x40000000	/* FPU enabled exception summary */
-#define FPSCR_VX	0x20000000	/* Invalid operation summary */
-#define FPSCR_OX	0x10000000	/* Overflow exception summary */
-#define FPSCR_UX	0x08000000	/* Underflow exception summary */
-#define FPSCR_ZX	0x04000000	/* Zero-divide exception summary */
-#define FPSCR_XX	0x02000000	/* Inexact exception summary */
-#define FPSCR_VXSNAN	0x01000000	/* Invalid op for SNaN */
-#define FPSCR_VXISI	0x00800000	/* Invalid op for Inv - Inv */
-#define FPSCR_VXIDI	0x00400000	/* Invalid op for Inv / Inv */
-#define FPSCR_VXZDZ	0x00200000	/* Invalid op for Zero / Zero */
-#define FPSCR_VXIMZ	0x00100000	/* Invalid op for Inv * Zero */
-#define FPSCR_VXVC	0x00080000	/* Invalid op for Compare */
-#define FPSCR_FR	0x00040000	/* Fraction rounded */
-#define FPSCR_FI	0x00020000	/* Fraction inexact */
-#define FPSCR_FPRF	0x0001f000	/* FPU Result Flags */
-#define FPSCR_FPCC	0x0000f000	/* FPU Condition Codes */
-#define FPSCR_VXSOFT	0x00000400	/* Invalid op for software request */
-#define FPSCR_VXSQRT	0x00000200	/* Invalid op for square root */
-#define FPSCR_VXCVI	0x00000100	/* Invalid op for integer convert */
-#define FPSCR_VE	0x00000080	/* Invalid op exception enable */
-#define FPSCR_OE	0x00000040	/* IEEE overflow exception enable */
-#define FPSCR_UE	0x00000020	/* IEEE underflow exception enable */
-#define FPSCR_ZE	0x00000010	/* IEEE zero divide exception enable */
-#define FPSCR_XE	0x00000008	/* FP inexact exception enable */
-#define FPSCR_NI	0x00000004	/* FPU non IEEE-Mode */
-#define FPSCR_RN	0x00000003	/* FPU rounding control */
-
-/* Bit definitions for SPEFSCR. */
-#define SPEFSCR_SOVH	0x80000000	/* Summary integer overflow high */
-#define SPEFSCR_OVH	0x40000000	/* Integer overflow high */
-#define SPEFSCR_FGH	0x20000000	/* Embedded FP guard bit high */
-#define SPEFSCR_FXH	0x10000000	/* Embedded FP sticky bit high */
-#define SPEFSCR_FINVH	0x08000000	/* Embedded FP invalid operation high */
-#define SPEFSCR_FDBZH	0x04000000	/* Embedded FP div by zero high */
-#define SPEFSCR_FUNFH	0x02000000	/* Embedded FP underflow high */
-#define SPEFSCR_FOVFH	0x01000000	/* Embedded FP overflow high */
-#define SPEFSCR_FINXS	0x00200000	/* Embedded FP inexact sticky */
-#define SPEFSCR_FINVS	0x00100000	/* Embedded FP invalid op. sticky */
-#define SPEFSCR_FDBZS	0x00080000	/* Embedded FP div by zero sticky */
-#define SPEFSCR_FUNFS	0x00040000	/* Embedded FP underflow sticky */
-#define SPEFSCR_FOVFS	0x00020000	/* Embedded FP overflow sticky */
-#define SPEFSCR_MODE	0x00010000	/* Embedded FP mode */
-#define SPEFSCR_SOV	0x00008000	/* Integer summary overflow */
-#define SPEFSCR_OV	0x00004000	/* Integer overflow */
-#define SPEFSCR_FG	0x00002000	/* Embedded FP guard bit */
-#define SPEFSCR_FX	0x00001000	/* Embedded FP sticky bit */
-#define SPEFSCR_FINV	0x00000800	/* Embedded FP invalid operation */
-#define SPEFSCR_FDBZ	0x00000400	/* Embedded FP div by zero */
-#define SPEFSCR_FUNF	0x00000200	/* Embedded FP underflow */
-#define SPEFSCR_FOVF	0x00000100	/* Embedded FP overflow */
-#define SPEFSCR_FINXE	0x00000040	/* Embedded FP inexact enable */
-#define SPEFSCR_FINVE	0x00000020	/* Embedded FP invalid op. enable */
-#define SPEFSCR_FDBZE	0x00000010	/* Embedded FP div by zero enable */
-#define SPEFSCR_FUNFE	0x00000008	/* Embedded FP underflow enable */
-#define SPEFSCR_FOVFE	0x00000004	/* Embedded FP overflow enable */
-#define SPEFSCR_FRMC 	0x00000003	/* Embedded FP rounding mode control */
-
-/* Special Purpose Registers (SPRNs)*/
-
-#ifdef CONFIG_40x
-#define SPRN_PID	0x3B1	/* Process ID */
-#else
-#define SPRN_PID	0x030	/* Process ID */
-#ifdef CONFIG_BOOKE
-#define SPRN_PID0	SPRN_PID/* Process ID Register 0 */
-#endif
-#endif
-
-#define SPRN_CTR	0x009	/* Count Register */
-#define SPRN_DSCR	0x11
-#define SPRN_CFAR	0x1c	/* Come From Address Register */
-#define SPRN_AMR	0x1d	/* Authority Mask Register */
-#define SPRN_UAMOR	0x9d	/* User Authority Mask Override Register */
-#define SPRN_AMOR	0x15d	/* Authority Mask Override Register */
-#define SPRN_ACOP	0x1F	/* Available Coprocessor Register */
-#define SPRN_CTRLF	0x088
-#define SPRN_CTRLT	0x098
-#define   CTRL_CT	0xc0000000	/* current thread */
-#define   CTRL_CT0	0x80000000	/* thread 0 */
-#define   CTRL_CT1	0x40000000	/* thread 1 */
-#define   CTRL_TE	0x00c00000	/* thread enable */
-#define   CTRL_RUNLATCH	0x1
-#define SPRN_DABR	0x3F5	/* Data Address Breakpoint Register */
-#define   DABR_TRANSLATION	(1UL << 2)
-#define   DABR_DATA_WRITE	(1UL << 1)
-#define   DABR_DATA_READ	(1UL << 0)
-#define SPRN_DABR2	0x13D	/* e300 */
-#define SPRN_DABRX	0x3F7	/* Data Address Breakpoint Register Extension */
-#define   DABRX_USER	(1UL << 0)
-#define   DABRX_KERNEL	(1UL << 1)
-#define SPRN_DAR	0x013	/* Data Address Register */
-#define SPRN_DBCR	0x136	/* e300 Data Breakpoint Control Reg */
-#define SPRN_DSISR	0x012	/* Data Storage Interrupt Status Register */
-#define   DSISR_NOHPTE		0x40000000	/* no translation found */
-#define   DSISR_PROTFAULT	0x08000000	/* protection fault */
-#define   DSISR_ISSTORE		0x02000000	/* access was a store */
-#define   DSISR_DABRMATCH	0x00400000	/* hit data breakpoint */
-#define   DSISR_NOSEGMENT	0x00200000	/* STAB/SLB miss */
-#define   DSISR_KEYFAULT	0x00200000	/* Key fault */
-#define SPRN_TBRL	0x10C	/* Time Base Read Lower Register (user, R/O) */
-#define SPRN_TBRU	0x10D	/* Time Base Read Upper Register (user, R/O) */
-#define SPRN_TBWL	0x11C	/* Time Base Lower Register (super, R/W) */
-#define SPRN_TBWU	0x11D	/* Time Base Upper Register (super, R/W) */
-#define SPRN_SPURR	0x134	/* Scaled PURR */
-#define SPRN_HSPRG0	0x130	/* Hypervisor Scratch 0 */
-#define SPRN_HSPRG1	0x131	/* Hypervisor Scratch 1 */
-#define SPRN_HDSISR     0x132
-#define SPRN_HDAR       0x133
-#define SPRN_HDEC	0x136	/* Hypervisor Decrementer */
-#define SPRN_HIOR	0x137	/* 970 Hypervisor interrupt offset */
-#define SPRN_RMOR	0x138	/* Real mode offset register */
-#define SPRN_HRMOR	0x139	/* Real mode offset register */
-#define SPRN_HSRR0	0x13A	/* Hypervisor Save/Restore 0 */
-#define SPRN_HSRR1	0x13B	/* Hypervisor Save/Restore 1 */
-#define SPRN_LPCR	0x13E	/* LPAR Control Register */
-#define   LPCR_VPM0	(1ul << (63-0))
-#define   LPCR_VPM1	(1ul << (63-1))
-#define   LPCR_ISL	(1ul << (63-2))
-#define   LPCR_VC_SH	(63-2)
-#define   LPCR_DPFD_SH	(63-11)
-#define   LPCR_VRMASD	(0x1ful << (63-16))
-#define   LPCR_VRMA_L	(1ul << (63-12))
-#define   LPCR_VRMA_LP0	(1ul << (63-15))
-#define   LPCR_VRMA_LP1	(1ul << (63-16))
-#define   LPCR_VRMASD_SH (63-16)
-#define   LPCR_RMLS    0x1C000000      /* impl dependent rmo limit sel */
-#define	  LPCR_RMLS_SH	(63-37)
-#define   LPCR_ILE     0x02000000      /* !HV irqs set MSR:LE */
-#define   LPCR_PECE	0x00007000	/* powersave exit cause enable */
-#define     LPCR_PECE0	0x00004000	/* ext. exceptions can cause exit */
-#define     LPCR_PECE1	0x00002000	/* decrementer can cause exit */
-#define     LPCR_PECE2	0x00001000	/* machine check etc can cause exit */
-#define   LPCR_MER	0x00000800	/* Mediated External Exception */
-#define   LPCR_LPES    0x0000000c
-#define   LPCR_LPES0   0x00000008      /* LPAR Env selector 0 */
-#define   LPCR_LPES1   0x00000004      /* LPAR Env selector 1 */
-#define   LPCR_LPES_SH	2
-#define   LPCR_RMI     0x00000002      /* real mode is cache inhibit */
-#define   LPCR_HDICE   0x00000001      /* Hyp Decr enable (HV,PR,EE) */
-#define SPRN_LPID	0x13F	/* Logical Partition Identifier */
-#define   LPID_RSVD	0x3ff		/* Reserved LPID for partn switching */
-#define	SPRN_HMER	0x150	/* Hardware m? error recovery */
-#define	SPRN_HMEER	0x151	/* Hardware m? enable error recovery */
-#define	SPRN_HEIR	0x153	/* Hypervisor Emulated Instruction Register */
-#define SPRN_TLBINDEXR	0x154	/* P7 TLB control register */
-#define SPRN_TLBVPNR	0x155	/* P7 TLB control register */
-#define SPRN_TLBRPNR	0x156	/* P7 TLB control register */
-#define SPRN_TLBLPIDR	0x157	/* P7 TLB control register */
-#define SPRN_DBAT0L	0x219	/* Data BAT 0 Lower Register */
-#define SPRN_DBAT0U	0x218	/* Data BAT 0 Upper Register */
-#define SPRN_DBAT1L	0x21B	/* Data BAT 1 Lower Register */
-#define SPRN_DBAT1U	0x21A	/* Data BAT 1 Upper Register */
-#define SPRN_DBAT2L	0x21D	/* Data BAT 2 Lower Register */
-#define SPRN_DBAT2U	0x21C	/* Data BAT 2 Upper Register */
-#define SPRN_DBAT3L	0x21F	/* Data BAT 3 Lower Register */
-#define SPRN_DBAT3U	0x21E	/* Data BAT 3 Upper Register */
-#define SPRN_DBAT4L	0x239	/* Data BAT 4 Lower Register */
-#define SPRN_DBAT4U	0x238	/* Data BAT 4 Upper Register */
-#define SPRN_DBAT5L	0x23B	/* Data BAT 5 Lower Register */
-#define SPRN_DBAT5U	0x23A	/* Data BAT 5 Upper Register */
-#define SPRN_DBAT6L	0x23D	/* Data BAT 6 Lower Register */
-#define SPRN_DBAT6U	0x23C	/* Data BAT 6 Upper Register */
-#define SPRN_DBAT7L	0x23F	/* Data BAT 7 Lower Register */
-#define SPRN_DBAT7U	0x23E	/* Data BAT 7 Upper Register */
-
-#define SPRN_DEC	0x016		/* Decrement Register */
-#define SPRN_DER	0x095		/* Debug Enable Regsiter */
-#define DER_RSTE	0x40000000	/* Reset Interrupt */
-#define DER_CHSTPE	0x20000000	/* Check Stop */
-#define DER_MCIE	0x10000000	/* Machine Check Interrupt */
-#define DER_EXTIE	0x02000000	/* External Interrupt */
-#define DER_ALIE	0x01000000	/* Alignment Interrupt */
-#define DER_PRIE	0x00800000	/* Program Interrupt */
-#define DER_FPUVIE	0x00400000	/* FP Unavailable Interrupt */
-#define DER_DECIE	0x00200000	/* Decrementer Interrupt */
-#define DER_SYSIE	0x00040000	/* System Call Interrupt */
-#define DER_TRE		0x00020000	/* Trace Interrupt */
-#define DER_SEIE	0x00004000	/* FP SW Emulation Interrupt */
-#define DER_ITLBMSE	0x00002000	/* Imp. Spec. Instruction TLB Miss */
-#define DER_ITLBERE	0x00001000	/* Imp. Spec. Instruction TLB Error */
-#define DER_DTLBMSE	0x00000800	/* Imp. Spec. Data TLB Miss */
-#define DER_DTLBERE	0x00000400	/* Imp. Spec. Data TLB Error */
-#define DER_LBRKE	0x00000008	/* Load/Store Breakpoint Interrupt */
-#define DER_IBRKE	0x00000004	/* Instruction Breakpoint Interrupt */
-#define DER_EBRKE	0x00000002	/* External Breakpoint Interrupt */
-#define DER_DPIE	0x00000001	/* Dev. Port Nonmaskable Request */
-#define SPRN_DMISS	0x3D0		/* Data TLB Miss Register */
-#define SPRN_EAR	0x11A		/* External Address Register */
-#define SPRN_HASH1	0x3D2		/* Primary Hash Address Register */
-#define SPRN_HASH2	0x3D3		/* Secondary Hash Address Resgister */
-#define SPRN_HID0	0x3F0		/* Hardware Implementation Register 0 */
-#define HID0_HDICE_SH	(63 - 23)	/* 970 HDEC interrupt enable */
-#define HID0_EMCP	(1<<31)		/* Enable Machine Check pin */
-#define HID0_EBA	(1<<29)		/* Enable Bus Address Parity */
-#define HID0_EBD	(1<<28)		/* Enable Bus Data Parity */
-#define HID0_SBCLK	(1<<27)
-#define HID0_EICE	(1<<26)
-#define HID0_TBEN	(1<<26)		/* Timebase enable - 745x */
-#define HID0_ECLK	(1<<25)
-#define HID0_PAR	(1<<24)
-#define HID0_STEN	(1<<24)		/* Software table search enable - 745x */
-#define HID0_HIGH_BAT	(1<<23)		/* Enable high BATs - 7455 */
-#define HID0_DOZE	(1<<23)
-#define HID0_NAP	(1<<22)
-#define HID0_SLEEP	(1<<21)
-#define HID0_DPM	(1<<20)
-#define HID0_BHTCLR	(1<<18)		/* Clear branch history table - 7450 */
-#define HID0_XAEN	(1<<17)		/* Extended addressing enable - 7450 */
-#define HID0_NHR	(1<<16)		/* Not hard reset (software bit-7450)*/
-#define HID0_ICE	(1<<15)		/* Instruction Cache Enable */
-#define HID0_DCE	(1<<14)		/* Data Cache Enable */
-#define HID0_ILOCK	(1<<13)		/* Instruction Cache Lock */
-#define HID0_DLOCK	(1<<12)		/* Data Cache Lock */
-#define HID0_ICFI	(1<<11)		/* Instr. Cache Flash Invalidate */
-#define HID0_DCI	(1<<10)		/* Data Cache Invalidate */
-#define HID0_SPD	(1<<9)		/* Speculative disable */
-#define HID0_DAPUEN	(1<<8)		/* Debug APU enable */
-#define HID0_SGE	(1<<7)		/* Store Gathering Enable */
-#define HID0_SIED	(1<<7)		/* Serial Instr. Execution [Disable] */
-#define HID0_DCFA	(1<<6)		/* Data Cache Flush Assist */
-#define HID0_LRSTK	(1<<4)		/* Link register stack - 745x */
-#define HID0_BTIC	(1<<5)		/* Branch Target Instr Cache Enable */
-#define HID0_ABE	(1<<3)		/* Address Broadcast Enable */
-#define HID0_FOLD	(1<<3)		/* Branch Folding enable - 745x */
-#define HID0_BHTE	(1<<2)		/* Branch History Table Enable */
-#define HID0_BTCD	(1<<1)		/* Branch target cache disable */
-#define HID0_NOPDST	(1<<1)		/* No-op dst, dstt, etc. instr. */
-#define HID0_NOPTI	(1<<0)		/* No-op dcbt and dcbst instr. */
-
-#define SPRN_HID1	0x3F1		/* Hardware Implementation Register 1 */
-#ifdef CONFIG_6xx
-#define HID1_EMCP	(1<<31)		/* 7450 Machine Check Pin Enable */
-#define HID1_DFS	(1<<22)		/* 7447A Dynamic Frequency Scaling */
-#define HID1_PC0	(1<<16)		/* 7450 PLL_CFG[0] */
-#define HID1_PC1	(1<<15)		/* 7450 PLL_CFG[1] */
-#define HID1_PC2	(1<<14)		/* 7450 PLL_CFG[2] */
-#define HID1_PC3	(1<<13)		/* 7450 PLL_CFG[3] */
-#define HID1_SYNCBE	(1<<11)		/* 7450 ABE for sync, eieio */
-#define HID1_ABE	(1<<10)		/* 7450 Address Broadcast Enable */
-#define HID1_PS		(1<<16)		/* 750FX PLL selection */
-#endif
-#define SPRN_HID2	0x3F8		/* Hardware Implementation Register 2 */
-#define SPRN_HID2_GEKKO	0x398		/* Gekko HID2 Register */
-#define SPRN_IABR	0x3F2	/* Instruction Address Breakpoint Register */
-#define SPRN_IABR2	0x3FA		/* 83xx */
-#define SPRN_IBCR	0x135		/* 83xx Insn Breakpoint Control Reg */
-#define SPRN_HID4	0x3F4		/* 970 HID4 */
-#define  HID4_LPES0	 (1ul << (63-0)) /* LPAR env. sel. bit 0 */
-#define	 HID4_RMLS2_SH	 (63 - 2)	/* Real mode limit bottom 2 bits */
-#define	 HID4_LPID5_SH	 (63 - 6)	/* partition ID bottom 4 bits */
-#define	 HID4_RMOR_SH	 (63 - 22)	/* real mode offset (16 bits) */
-#define  HID4_LPES1	 (1 << (63-57))	/* LPAR env. sel. bit 1 */
-#define  HID4_RMLS0_SH	 (63 - 58)	/* Real mode limit top bit */
-#define	 HID4_LPID1_SH	 0		/* partition ID top 2 bits */
-#define SPRN_HID4_GEKKO	0x3F3		/* Gekko HID4 */
-#define SPRN_HID5	0x3F6		/* 970 HID5 */
-#define SPRN_HID6	0x3F9	/* BE HID 6 */
-#define   HID6_LB	(0x0F<<12) /* Concurrent Large Page Modes */
-#define   HID6_DLP	(1<<20)	/* Disable all large page modes (4K only) */
-#define SPRN_TSC_CELL	0x399	/* Thread switch control on Cell */
-#define   TSC_CELL_DEC_ENABLE_0	0x400000 /* Decrementer Interrupt */
-#define   TSC_CELL_DEC_ENABLE_1	0x200000 /* Decrementer Interrupt */
-#define   TSC_CELL_EE_ENABLE	0x100000 /* External Interrupt */
-#define   TSC_CELL_EE_BOOST	0x080000 /* External Interrupt Boost */
-#define SPRN_TSC 	0x3FD	/* Thread switch control on others */
-#define SPRN_TST 	0x3FC	/* Thread switch timeout on others */
-#if !defined(SPRN_IAC1) && !defined(SPRN_IAC2)
-#define SPRN_IAC1	0x3F4		/* Instruction Address Compare 1 */
-#define SPRN_IAC2	0x3F5		/* Instruction Address Compare 2 */
-#endif
-#define SPRN_IBAT0L	0x211		/* Instruction BAT 0 Lower Register */
-#define SPRN_IBAT0U	0x210		/* Instruction BAT 0 Upper Register */
-#define SPRN_IBAT1L	0x213		/* Instruction BAT 1 Lower Register */
-#define SPRN_IBAT1U	0x212		/* Instruction BAT 1 Upper Register */
-#define SPRN_IBAT2L	0x215		/* Instruction BAT 2 Lower Register */
-#define SPRN_IBAT2U	0x214		/* Instruction BAT 2 Upper Register */
-#define SPRN_IBAT3L	0x217		/* Instruction BAT 3 Lower Register */
-#define SPRN_IBAT3U	0x216		/* Instruction BAT 3 Upper Register */
-#define SPRN_IBAT4L	0x231		/* Instruction BAT 4 Lower Register */
-#define SPRN_IBAT4U	0x230		/* Instruction BAT 4 Upper Register */
-#define SPRN_IBAT5L	0x233		/* Instruction BAT 5 Lower Register */
-#define SPRN_IBAT5U	0x232		/* Instruction BAT 5 Upper Register */
-#define SPRN_IBAT6L	0x235		/* Instruction BAT 6 Lower Register */
-#define SPRN_IBAT6U	0x234		/* Instruction BAT 6 Upper Register */
-#define SPRN_IBAT7L	0x237		/* Instruction BAT 7 Lower Register */
-#define SPRN_IBAT7U	0x236		/* Instruction BAT 7 Upper Register */
-#define SPRN_ICMP	0x3D5		/* Instruction TLB Compare Register */
-#define SPRN_ICTC	0x3FB	/* Instruction Cache Throttling Control Reg */
-#define SPRN_ICTRL	0x3F3	/* 1011 7450 icache and interrupt ctrl */
-#define ICTRL_EICE	0x08000000	/* enable icache parity errs */
-#define ICTRL_EDC	0x04000000	/* enable dcache parity errs */
-#define ICTRL_EICP	0x00000100	/* enable icache par. check */
-#define SPRN_IMISS	0x3D4		/* Instruction TLB Miss Register */
-#define SPRN_IMMR	0x27E		/* Internal Memory Map Register */
-#define SPRN_L2CR	0x3F9		/* Level 2 Cache Control Regsiter */
-#define SPRN_L2CR2	0x3f8
-#define L2CR_L2E		0x80000000	/* L2 enable */
-#define L2CR_L2PE		0x40000000	/* L2 parity enable */
-#define L2CR_L2SIZ_MASK		0x30000000	/* L2 size mask */
-#define L2CR_L2SIZ_256KB	0x10000000	/* L2 size 256KB */
-#define L2CR_L2SIZ_512KB	0x20000000	/* L2 size 512KB */
-#define L2CR_L2SIZ_1MB		0x30000000	/* L2 size 1MB */
-#define L2CR_L2CLK_MASK		0x0e000000	/* L2 clock mask */
-#define L2CR_L2CLK_DISABLED	0x00000000	/* L2 clock disabled */
-#define L2CR_L2CLK_DIV1		0x02000000	/* L2 clock / 1 */
-#define L2CR_L2CLK_DIV1_5	0x04000000	/* L2 clock / 1.5 */
-#define L2CR_L2CLK_DIV2		0x08000000	/* L2 clock / 2 */
-#define L2CR_L2CLK_DIV2_5	0x0a000000	/* L2 clock / 2.5 */
-#define L2CR_L2CLK_DIV3		0x0c000000	/* L2 clock / 3 */
-#define L2CR_L2RAM_MASK		0x01800000	/* L2 RAM type mask */
-#define L2CR_L2RAM_FLOW		0x00000000	/* L2 RAM flow through */
-#define L2CR_L2RAM_PIPE		0x01000000	/* L2 RAM pipelined */
-#define L2CR_L2RAM_PIPE_LW	0x01800000	/* L2 RAM pipelined latewr */
-#define L2CR_L2DO		0x00400000	/* L2 data only */
-#define L2CR_L2I		0x00200000	/* L2 global invalidate */
-#define L2CR_L2CTL		0x00100000	/* L2 RAM control */
-#define L2CR_L2WT		0x00080000	/* L2 write-through */
-#define L2CR_L2TS		0x00040000	/* L2 test support */
-#define L2CR_L2OH_MASK		0x00030000	/* L2 output hold mask */
-#define L2CR_L2OH_0_5		0x00000000	/* L2 output hold 0.5 ns */
-#define L2CR_L2OH_1_0		0x00010000	/* L2 output hold 1.0 ns */
-#define L2CR_L2SL		0x00008000	/* L2 DLL slow */
-#define L2CR_L2DF		0x00004000	/* L2 differential clock */
-#define L2CR_L2BYP		0x00002000	/* L2 DLL bypass */
-#define L2CR_L2IP		0x00000001	/* L2 GI in progress */
-#define L2CR_L2IO_745x		0x00100000	/* L2 instr. only (745x) */
-#define L2CR_L2DO_745x		0x00010000	/* L2 data only (745x) */
-#define L2CR_L2REP_745x		0x00001000	/* L2 repl. algorithm (745x) */
-#define L2CR_L2HWF_745x		0x00000800	/* L2 hardware flush (745x) */
-#define SPRN_L3CR		0x3FA	/* Level 3 Cache Control Regsiter */
-#define L3CR_L3E		0x80000000	/* L3 enable */
-#define L3CR_L3PE		0x40000000	/* L3 data parity enable */
-#define L3CR_L3APE		0x20000000	/* L3 addr parity enable */
-#define L3CR_L3SIZ		0x10000000	/* L3 size */
-#define L3CR_L3CLKEN		0x08000000	/* L3 clock enable */
-#define L3CR_L3RES		0x04000000	/* L3 special reserved bit */
-#define L3CR_L3CLKDIV		0x03800000	/* L3 clock divisor */
-#define L3CR_L3IO		0x00400000	/* L3 instruction only */
-#define L3CR_L3SPO		0x00040000	/* L3 sample point override */
-#define L3CR_L3CKSP		0x00030000	/* L3 clock sample point */
-#define L3CR_L3PSP		0x0000e000	/* L3 P-clock sample point */
-#define L3CR_L3REP		0x00001000	/* L3 replacement algorithm */
-#define L3CR_L3HWF		0x00000800	/* L3 hardware flush */
-#define L3CR_L3I		0x00000400	/* L3 global invalidate */
-#define L3CR_L3RT		0x00000300	/* L3 SRAM type */
-#define L3CR_L3NIRCA		0x00000080	/* L3 non-integer ratio clock adj. */
-#define L3CR_L3DO		0x00000040	/* L3 data only mode */
-#define L3CR_PMEN		0x00000004	/* L3 private memory enable */
-#define L3CR_PMSIZ		0x00000001	/* L3 private memory size */
-
-#define SPRN_MSSCR0	0x3f6	/* Memory Subsystem Control Register 0 */
-#define SPRN_MSSSR0	0x3f7	/* Memory Subsystem Status Register 1 */
-#define SPRN_LDSTCR	0x3f8	/* Load/Store control register */
-#define SPRN_LDSTDB	0x3f4	/* */
-#define SPRN_LR		0x008	/* Link Register */
-#ifndef SPRN_PIR
-#define SPRN_PIR	0x3FF	/* Processor Identification Register */
-#endif
-#define SPRN_PTEHI	0x3D5	/* 981 7450 PTE HI word (S/W TLB load) */
-#define SPRN_PTELO	0x3D6	/* 982 7450 PTE LO word (S/W TLB load) */
-#define SPRN_PURR	0x135	/* Processor Utilization of Resources Reg */
-#define SPRN_PVR	0x11F	/* Processor Version Register */
-#define SPRN_RPA	0x3D6	/* Required Physical Address Register */
-#define SPRN_SDA	0x3BF	/* Sampled Data Address Register */
-#define SPRN_SDR1	0x019	/* MMU Hash Base Register */
-#define SPRN_ASR	0x118   /* Address Space Register */
-#define SPRN_SIA	0x3BB	/* Sampled Instruction Address Register */
-#define SPRN_SPRG0	0x110	/* Special Purpose Register General 0 */
-#define SPRN_SPRG1	0x111	/* Special Purpose Register General 1 */
-#define SPRN_SPRG2	0x112	/* Special Purpose Register General 2 */
-#define SPRN_SPRG3	0x113	/* Special Purpose Register General 3 */
-#define SPRN_SPRG4	0x114	/* Special Purpose Register General 4 */
-#define SPRN_SPRG5	0x115	/* Special Purpose Register General 5 */
-#define SPRN_SPRG6	0x116	/* Special Purpose Register General 6 */
-#define SPRN_SPRG7	0x117	/* Special Purpose Register General 7 */
-#define SPRN_SRR0	0x01A	/* Save/Restore Register 0 */
-#define SPRN_SRR1	0x01B	/* Save/Restore Register 1 */
-#define   SRR1_ISI_NOPT		0x40000000 /* ISI: Not found in hash */
-#define   SRR1_ISI_N_OR_G	0x10000000 /* ISI: Access is no-exec or G */
-#define   SRR1_ISI_PROT		0x08000000 /* ISI: Other protection fault */
-#define   SRR1_WAKEMASK		0x00380000 /* reason for wakeup */
-#define   SRR1_WAKESYSERR	0x00300000 /* System error */
-#define   SRR1_WAKEEE		0x00200000 /* External interrupt */
-#define   SRR1_WAKEMT		0x00280000 /* mtctrl */
-#define	  SRR1_WAKEHMI		0x00280000 /* Hypervisor maintenance */
-#define   SRR1_WAKEDEC		0x00180000 /* Decrementer interrupt */
-#define   SRR1_WAKETHERM	0x00100000 /* Thermal management interrupt */
-#define	  SRR1_WAKERESET	0x00100000 /* System reset */
-#define	  SRR1_WAKESTATE	0x00030000 /* Powersave exit mask [46:47] */
-#define	  SRR1_WS_DEEPEST	0x00030000 /* Some resources not maintained,
-					  * may not be recoverable */
-#define	  SRR1_WS_DEEPER	0x00020000 /* Some resources not maintained */
-#define	  SRR1_WS_DEEP		0x00010000 /* All resources maintained */
-#define   SRR1_PROGFPE		0x00100000 /* Floating Point Enabled */
-#define   SRR1_PROGPRIV		0x00040000 /* Privileged instruction */
-#define   SRR1_PROGTRAP		0x00020000 /* Trap */
-#define   SRR1_PROGADDR		0x00010000 /* SRR0 contains subsequent addr */
-
-#define SPRN_HSRR0	0x13A	/* Save/Restore Register 0 */
-#define SPRN_HSRR1	0x13B	/* Save/Restore Register 1 */
-
-#define SPRN_TBCTL	0x35f	/* PA6T Timebase control register */
-#define   TBCTL_FREEZE		0x0000000000000000ull /* Freeze all tbs */
-#define   TBCTL_RESTART		0x0000000100000000ull /* Restart all tbs */
-#define   TBCTL_UPDATE_UPPER	0x0000000200000000ull /* Set upper 32 bits */
-#define   TBCTL_UPDATE_LOWER	0x0000000300000000ull /* Set lower 32 bits */
-
-#ifndef SPRN_SVR
-#define SPRN_SVR	0x11E	/* System Version Register */
-#endif
-#define SPRN_THRM1	0x3FC		/* Thermal Management Register 1 */
-/* these bits were defined in inverted endian sense originally, ugh, confusing */
-#define THRM1_TIN	(1 << 31)
-#define THRM1_TIV	(1 << 30)
-#define THRM1_THRES(x)	((x&0x7f)<<23)
-#define THRM3_SITV(x)	((x&0x3fff)<<1)
-#define THRM1_TID	(1<<2)
-#define THRM1_TIE	(1<<1)
-#define THRM1_V		(1<<0)
-#define SPRN_THRM2	0x3FD		/* Thermal Management Register 2 */
-#define SPRN_THRM3	0x3FE		/* Thermal Management Register 3 */
-#define THRM3_E		(1<<0)
-#define SPRN_TLBMISS	0x3D4		/* 980 7450 TLB Miss Register */
-#define SPRN_UMMCR0	0x3A8	/* User Monitor Mode Control Register 0 */
-#define SPRN_UMMCR1	0x3AC	/* User Monitor Mode Control Register 0 */
-#define SPRN_UPMC1	0x3A9	/* User Performance Counter Register 1 */
-#define SPRN_UPMC2	0x3AA	/* User Performance Counter Register 2 */
-#define SPRN_UPMC3	0x3AD	/* User Performance Counter Register 3 */
-#define SPRN_UPMC4	0x3AE	/* User Performance Counter Register 4 */
-#define SPRN_USIA	0x3AB	/* User Sampled Instruction Address Register */
-#define SPRN_VRSAVE	0x100	/* Vector Register Save Register */
-#define SPRN_XER	0x001	/* Fixed Point Exception Register */
-
-#define SPRN_MMCR0_GEKKO 0x3B8 /* Gekko Monitor Mode Control Register 0 */
-#define SPRN_MMCR1_GEKKO 0x3BC /* Gekko Monitor Mode Control Register 1 */
-#define SPRN_PMC1_GEKKO  0x3B9 /* Gekko Performance Monitor Control 1 */
-#define SPRN_PMC2_GEKKO  0x3BA /* Gekko Performance Monitor Control 2 */
-#define SPRN_PMC3_GEKKO  0x3BD /* Gekko Performance Monitor Control 3 */
-#define SPRN_PMC4_GEKKO  0x3BE /* Gekko Performance Monitor Control 4 */
-#define SPRN_WPAR_GEKKO  0x399 /* Gekko Write Pipe Address Register */
-
-#define SPRN_SCOMC	0x114	/* SCOM Access Control */
-#define SPRN_SCOMD	0x115	/* SCOM Access DATA */
-
-/* Performance monitor SPRs */
-#ifdef CONFIG_PPC64
-#define SPRN_MMCR0	795
-#define   MMCR0_FC	0x80000000UL /* freeze counters */
-#define   MMCR0_FCS	0x40000000UL /* freeze in supervisor state */
-#define   MMCR0_KERNEL_DISABLE MMCR0_FCS
-#define   MMCR0_FCP	0x20000000UL /* freeze in problem state */
-#define   MMCR0_PROBLEM_DISABLE MMCR0_FCP
-#define   MMCR0_FCM1	0x10000000UL /* freeze counters while MSR mark = 1 */
-#define   MMCR0_FCM0	0x08000000UL /* freeze counters while MSR mark = 0 */
-#define   MMCR0_PMXE	0x04000000UL /* performance monitor exception enable */
-#define   MMCR0_FCECE	0x02000000UL /* freeze ctrs on enabled cond or event */
-#define   MMCR0_TBEE	0x00400000UL /* time base exception enable */
-#define   MMCR0_PMC1CE	0x00008000UL /* PMC1 count enable*/
-#define   MMCR0_PMCjCE	0x00004000UL /* PMCj count enable*/
-#define   MMCR0_TRIGGER	0x00002000UL /* TRIGGER enable */
-#define   MMCR0_PMAO	0x00000080UL /* performance monitor alert has occurred, set to 0 after handling exception */
-#define   MMCR0_SHRFC	0x00000040UL /* SHRre freeze conditions between threads */
-#define   MMCR0_FCTI	0x00000008UL /* freeze counters in tags inactive mode */
-#define   MMCR0_FCTA	0x00000004UL /* freeze counters in tags active mode */
-#define   MMCR0_FCWAIT	0x00000002UL /* freeze counter in WAIT state */
-#define   MMCR0_FCHV	0x00000001UL /* freeze conditions in hypervisor mode */
-#define SPRN_MMCR1	798
-#define SPRN_MMCRA	0x312
-#define   MMCRA_SDSYNC	0x80000000UL /* SDAR synced with SIAR */
-#define   MMCRA_SDAR_DCACHE_MISS 0x40000000UL
-#define   MMCRA_SDAR_ERAT_MISS   0x20000000UL
-#define   MMCRA_SIHV	0x10000000UL /* state of MSR HV when SIAR set */
-#define   MMCRA_SIPR	0x08000000UL /* state of MSR PR when SIAR set */
-#define   MMCRA_SLOT	0x07000000UL /* SLOT bits (37-39) */
-#define   MMCRA_SLOT_SHIFT	24
-#define   MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */
-#define   POWER6_MMCRA_SDSYNC 0x0000080000000000ULL	/* SDAR/SIAR synced */
-#define   POWER6_MMCRA_SIHV   0x0000040000000000ULL
-#define   POWER6_MMCRA_SIPR   0x0000020000000000ULL
-#define   POWER6_MMCRA_THRM	0x00000020UL
-#define   POWER6_MMCRA_OTHER	0x0000000EUL
-#define SPRN_PMC1	787
-#define SPRN_PMC2	788
-#define SPRN_PMC3	789
-#define SPRN_PMC4	790
-#define SPRN_PMC5	791
-#define SPRN_PMC6	792
-#define SPRN_PMC7	793
-#define SPRN_PMC8	794
-#define SPRN_SIAR	780
-#define SPRN_SDAR	781
-
-#define SPRN_PA6T_MMCR0 795
-#define   PA6T_MMCR0_EN0	0x0000000000000001UL
-#define   PA6T_MMCR0_EN1	0x0000000000000002UL
-#define   PA6T_MMCR0_EN2	0x0000000000000004UL
-#define   PA6T_MMCR0_EN3	0x0000000000000008UL
-#define   PA6T_MMCR0_EN4	0x0000000000000010UL
-#define   PA6T_MMCR0_EN5	0x0000000000000020UL
-#define   PA6T_MMCR0_SUPEN	0x0000000000000040UL
-#define   PA6T_MMCR0_PREN	0x0000000000000080UL
-#define   PA6T_MMCR0_HYPEN	0x0000000000000100UL
-#define   PA6T_MMCR0_FCM0	0x0000000000000200UL
-#define   PA6T_MMCR0_FCM1	0x0000000000000400UL
-#define   PA6T_MMCR0_INTGEN	0x0000000000000800UL
-#define   PA6T_MMCR0_INTEN0	0x0000000000001000UL
-#define   PA6T_MMCR0_INTEN1	0x0000000000002000UL
-#define   PA6T_MMCR0_INTEN2	0x0000000000004000UL
-#define   PA6T_MMCR0_INTEN3	0x0000000000008000UL
-#define   PA6T_MMCR0_INTEN4	0x0000000000010000UL
-#define   PA6T_MMCR0_INTEN5	0x0000000000020000UL
-#define   PA6T_MMCR0_DISCNT	0x0000000000040000UL
-#define   PA6T_MMCR0_UOP	0x0000000000080000UL
-#define   PA6T_MMCR0_TRG	0x0000000000100000UL
-#define   PA6T_MMCR0_TRGEN	0x0000000000200000UL
-#define   PA6T_MMCR0_TRGREG	0x0000000001600000UL
-#define   PA6T_MMCR0_SIARLOG	0x0000000002000000UL
-#define   PA6T_MMCR0_SDARLOG	0x0000000004000000UL
-#define   PA6T_MMCR0_PROEN	0x0000000008000000UL
-#define   PA6T_MMCR0_PROLOG	0x0000000010000000UL
-#define   PA6T_MMCR0_DAMEN2	0x0000000020000000UL
-#define   PA6T_MMCR0_DAMEN3	0x0000000040000000UL
-#define   PA6T_MMCR0_DAMEN4	0x0000000080000000UL
-#define   PA6T_MMCR0_DAMEN5	0x0000000100000000UL
-#define   PA6T_MMCR0_DAMSEL2	0x0000000200000000UL
-#define   PA6T_MMCR0_DAMSEL3	0x0000000400000000UL
-#define   PA6T_MMCR0_DAMSEL4	0x0000000800000000UL
-#define   PA6T_MMCR0_DAMSEL5	0x0000001000000000UL
-#define   PA6T_MMCR0_HANDDIS	0x0000002000000000UL
-#define   PA6T_MMCR0_PCTEN	0x0000004000000000UL
-#define   PA6T_MMCR0_SOCEN	0x0000008000000000UL
-#define   PA6T_MMCR0_SOCMOD	0x0000010000000000UL
-
-#define SPRN_PA6T_MMCR1 798
-#define   PA6T_MMCR1_ES2	0x00000000000000ffUL
-#define   PA6T_MMCR1_ES3	0x000000000000ff00UL
-#define   PA6T_MMCR1_ES4	0x0000000000ff0000UL
-#define   PA6T_MMCR1_ES5	0x00000000ff000000UL
-
-#define SPRN_PA6T_UPMC0 771	/* User PerfMon Counter 0 */
-#define SPRN_PA6T_UPMC1 772	/* ... */
-#define SPRN_PA6T_UPMC2 773
-#define SPRN_PA6T_UPMC3 774
-#define SPRN_PA6T_UPMC4 775
-#define SPRN_PA6T_UPMC5 776
-#define SPRN_PA6T_UMMCR0 779	/* User Monitor Mode Control Register 0 */
-#define SPRN_PA6T_SIAR	780	/* Sampled Instruction Address */
-#define SPRN_PA6T_UMMCR1 782	/* User Monitor Mode Control Register 1 */
-#define SPRN_PA6T_SIER	785	/* Sampled Instruction Event Register */
-#define SPRN_PA6T_PMC0	787
-#define SPRN_PA6T_PMC1	788
-#define SPRN_PA6T_PMC2	789
-#define SPRN_PA6T_PMC3	790
-#define SPRN_PA6T_PMC4	791
-#define SPRN_PA6T_PMC5	792
-#define SPRN_PA6T_TSR0	793	/* Timestamp Register 0 */
-#define SPRN_PA6T_TSR1	794	/* Timestamp Register 1 */
-#define SPRN_PA6T_TSR2	799	/* Timestamp Register 2 */
-#define SPRN_PA6T_TSR3	784	/* Timestamp Register 3 */
-
-#define SPRN_PA6T_IER	981	/* Icache Error Register */
-#define SPRN_PA6T_DER	982	/* Dcache Error Register */
-#define SPRN_PA6T_BER	862	/* BIU Error Address Register */
-#define SPRN_PA6T_MER	849	/* MMU Error Register */
-
-#define SPRN_PA6T_IMA0	880	/* Instruction Match Array 0 */
-#define SPRN_PA6T_IMA1	881	/* ... */
-#define SPRN_PA6T_IMA2	882
-#define SPRN_PA6T_IMA3	883
-#define SPRN_PA6T_IMA4	884
-#define SPRN_PA6T_IMA5	885
-#define SPRN_PA6T_IMA6	886
-#define SPRN_PA6T_IMA7	887
-#define SPRN_PA6T_IMA8	888
-#define SPRN_PA6T_IMA9	889
-#define SPRN_PA6T_BTCR	978	/* Breakpoint and Tagging Control Register */
-#define SPRN_PA6T_IMAAT	979	/* Instruction Match Array Action Table */
-#define SPRN_PA6T_PCCR	1019	/* Power Counter Control Register */
-#define SPRN_BKMK	1020	/* Cell Bookmark Register */
-#define SPRN_PA6T_RPCCR	1021	/* Retire PC Trace Control Register */
-
-
-#else /* 32-bit */
-#define SPRN_MMCR0	952	/* Monitor Mode Control Register 0 */
-#define   MMCR0_FC	0x80000000UL /* freeze counters */
-#define   MMCR0_FCS	0x40000000UL /* freeze in supervisor state */
-#define   MMCR0_FCP	0x20000000UL /* freeze in problem state */
-#define   MMCR0_FCM1	0x10000000UL /* freeze counters while MSR mark = 1 */
-#define   MMCR0_FCM0	0x08000000UL /* freeze counters while MSR mark = 0 */
-#define   MMCR0_PMXE	0x04000000UL /* performance monitor exception enable */
-#define   MMCR0_FCECE	0x02000000UL /* freeze ctrs on enabled cond or event */
-#define   MMCR0_TBEE	0x00400000UL /* time base exception enable */
-#define   MMCR0_PMC1CE	0x00008000UL /* PMC1 count enable*/
-#define   MMCR0_PMCnCE	0x00004000UL /* count enable for all but PMC 1*/
-#define   MMCR0_TRIGGER	0x00002000UL /* TRIGGER enable */
-#define   MMCR0_PMC1SEL	0x00001fc0UL /* PMC 1 Event */
-#define   MMCR0_PMC2SEL	0x0000003fUL /* PMC 2 Event */
-
-#define SPRN_MMCR1	956
-#define   MMCR1_PMC3SEL	0xf8000000UL /* PMC 3 Event */
-#define   MMCR1_PMC4SEL	0x07c00000UL /* PMC 4 Event */
-#define   MMCR1_PMC5SEL	0x003e0000UL /* PMC 5 Event */
-#define   MMCR1_PMC6SEL 0x0001f800UL /* PMC 6 Event */
-#define SPRN_MMCR2	944
-#define SPRN_PMC1	953	/* Performance Counter Register 1 */
-#define SPRN_PMC2	954	/* Performance Counter Register 2 */
-#define SPRN_PMC3	957	/* Performance Counter Register 3 */
-#define SPRN_PMC4	958	/* Performance Counter Register 4 */
-#define SPRN_PMC5	945	/* Performance Counter Register 5 */
-#define SPRN_PMC6	946	/* Performance Counter Register 6 */
-
-#define SPRN_SIAR	955	/* Sampled Instruction Address Register */
-
-/* Bit definitions for MMCR0 and PMC1 / PMC2. */
-#define MMCR0_PMC1_CYCLES	(1 << 7)
-#define MMCR0_PMC1_ICACHEMISS	(5 << 7)
-#define MMCR0_PMC1_DTLB		(6 << 7)
-#define MMCR0_PMC2_DCACHEMISS	0x6
-#define MMCR0_PMC2_CYCLES	0x1
-#define MMCR0_PMC2_ITLB		0x7
-#define MMCR0_PMC2_LOADMISSTIME	0x5
-#endif
-
-/*
- * SPRG usage:
- *
- * All 64-bit:
- *	- SPRG1 stores PACA pointer except 64-bit server in
- *        HV mode in which case it is HSPRG0
- *
- * 64-bit server:
- *	- SPRG0 unused (reserved for HV on Power4)
- *	- SPRG2 scratch for exception vectors
- *	- SPRG3 unused (user visible)
- *      - HSPRG0 stores PACA in HV mode
- *      - HSPRG1 scratch for "HV" exceptions
- *
- * 64-bit embedded
- *	- SPRG0 generic exception scratch
- *	- SPRG2 TLB exception stack
- *	- SPRG3 unused (user visible)
- *	- SPRG4 unused (user visible)
- *	- SPRG6 TLB miss scratch (user visible, sorry !)
- *	- SPRG7 critical exception scratch
- *	- SPRG8 machine check exception scratch
- *	- SPRG9 debug exception scratch
- *
- * All 32-bit:
- *	- SPRG3 current thread_info pointer
- *        (virtual on BookE, physical on others)
- *
- * 32-bit classic:
- *	- SPRG0 scratch for exception vectors
- *	- SPRG1 scratch for exception vectors
- *	- SPRG2 indicator that we are in RTAS
- *	- SPRG4 (603 only) pseudo TLB LRU data
- *
- * 32-bit 40x:
- *	- SPRG0 scratch for exception vectors
- *	- SPRG1 scratch for exception vectors
- *	- SPRG2 scratch for exception vectors
- *	- SPRG4 scratch for exception vectors (not 403)
- *	- SPRG5 scratch for exception vectors (not 403)
- *	- SPRG6 scratch for exception vectors (not 403)
- *	- SPRG7 scratch for exception vectors (not 403)
- *
- * 32-bit 440 and FSL BookE:
- *	- SPRG0 scratch for exception vectors
- *	- SPRG1 scratch for exception vectors (*)
- *	- SPRG2 scratch for crit interrupts handler
- *	- SPRG4 scratch for exception vectors
- *	- SPRG5 scratch for exception vectors
- *	- SPRG6 scratch for machine check handler
- *	- SPRG7 scratch for exception vectors
- *	- SPRG9 scratch for debug vectors (e500 only)
- *
- *      Additionally, BookE separates "read" and "write"
- *      of those registers. That allows to use the userspace
- *      readable variant for reads, which can avoid a fault
- *      with KVM type virtualization.
- *
- *      (*) Under KVM, the host SPRG1 is used to point to
- *      the current VCPU data structure
- *
- * 32-bit 8xx:
- *	- SPRG0 scratch for exception vectors
- *	- SPRG1 scratch for exception vectors
- *	- SPRG2 apparently unused but initialized
- *
- */
-#ifdef CONFIG_PPC64
-#define SPRN_SPRG_PACA 		SPRN_SPRG1
-#else
-#define SPRN_SPRG_THREAD 	SPRN_SPRG3
-#endif
-
-#ifdef CONFIG_PPC_BOOK3S_64
-#define SPRN_SPRG_SCRATCH0	SPRN_SPRG2
-#define SPRN_SPRG_HPACA		SPRN_HSPRG0
-#define SPRN_SPRG_HSCRATCH0	SPRN_HSPRG1
-
-#define GET_PACA(rX)					\
-	BEGIN_FTR_SECTION_NESTED(66);			\
-	mfspr	rX,SPRN_SPRG_PACA;			\
-	FTR_SECTION_ELSE_NESTED(66);			\
-	mfspr	rX,SPRN_SPRG_HPACA;			\
-	ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
-
-#define SET_PACA(rX)					\
-	BEGIN_FTR_SECTION_NESTED(66);			\
-	mtspr	SPRN_SPRG_PACA,rX;			\
-	FTR_SECTION_ELSE_NESTED(66);			\
-	mtspr	SPRN_SPRG_HPACA,rX;			\
-	ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
-
-#define GET_SCRATCH0(rX)				\
-	BEGIN_FTR_SECTION_NESTED(66);			\
-	mfspr	rX,SPRN_SPRG_SCRATCH0;			\
-	FTR_SECTION_ELSE_NESTED(66);			\
-	mfspr	rX,SPRN_SPRG_HSCRATCH0;			\
-	ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
-
-#define SET_SCRATCH0(rX)				\
-	BEGIN_FTR_SECTION_NESTED(66);			\
-	mtspr	SPRN_SPRG_SCRATCH0,rX;			\
-	FTR_SECTION_ELSE_NESTED(66);			\
-	mtspr	SPRN_SPRG_HSCRATCH0,rX;			\
-	ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
-
-#else /* CONFIG_PPC_BOOK3S_64 */
-#define GET_SCRATCH0(rX)	mfspr	rX,SPRN_SPRG_SCRATCH0
-#define SET_SCRATCH0(rX)	mtspr	SPRN_SPRG_SCRATCH0,rX
-
-#endif
-
-#ifdef CONFIG_PPC_BOOK3E_64
-#define SPRN_SPRG_MC_SCRATCH	SPRN_SPRG8
-#define SPRN_SPRG_CRIT_SCRATCH	SPRN_SPRG7
-#define SPRN_SPRG_DBG_SCRATCH	SPRN_SPRG9
-#define SPRN_SPRG_TLB_EXFRAME	SPRN_SPRG2
-#define SPRN_SPRG_TLB_SCRATCH	SPRN_SPRG6
-#define SPRN_SPRG_GEN_SCRATCH	SPRN_SPRG0
-
-#define SET_PACA(rX)	mtspr	SPRN_SPRG_PACA,rX
-#define GET_PACA(rX)	mfspr	rX,SPRN_SPRG_PACA
-
-#endif
-
-#ifdef CONFIG_PPC_BOOK3S_32
-#define SPRN_SPRG_SCRATCH0	SPRN_SPRG0
-#define SPRN_SPRG_SCRATCH1	SPRN_SPRG1
-#define SPRN_SPRG_RTAS		SPRN_SPRG2
-#define SPRN_SPRG_603_LRU	SPRN_SPRG4
-#endif
-
-#ifdef CONFIG_40x
-#define SPRN_SPRG_SCRATCH0	SPRN_SPRG0
-#define SPRN_SPRG_SCRATCH1	SPRN_SPRG1
-#define SPRN_SPRG_SCRATCH2	SPRN_SPRG2
-#define SPRN_SPRG_SCRATCH3	SPRN_SPRG4
-#define SPRN_SPRG_SCRATCH4	SPRN_SPRG5
-#define SPRN_SPRG_SCRATCH5	SPRN_SPRG6
-#define SPRN_SPRG_SCRATCH6	SPRN_SPRG7
-#endif
-
-#ifdef CONFIG_BOOKE
-#define SPRN_SPRG_RSCRATCH0	SPRN_SPRG0
-#define SPRN_SPRG_WSCRATCH0	SPRN_SPRG0
-#define SPRN_SPRG_RSCRATCH1	SPRN_SPRG1
-#define SPRN_SPRG_WSCRATCH1	SPRN_SPRG1
-#define SPRN_SPRG_RSCRATCH_CRIT	SPRN_SPRG2
-#define SPRN_SPRG_WSCRATCH_CRIT	SPRN_SPRG2
-#define SPRN_SPRG_RSCRATCH2	SPRN_SPRG4R
-#define SPRN_SPRG_WSCRATCH2	SPRN_SPRG4W
-#define SPRN_SPRG_RSCRATCH3	SPRN_SPRG5R
-#define SPRN_SPRG_WSCRATCH3	SPRN_SPRG5W
-#define SPRN_SPRG_RSCRATCH_MC	SPRN_SPRG1
-#define SPRN_SPRG_WSCRATCH_MC	SPRN_SPRG1
-#define SPRN_SPRG_RSCRATCH4	SPRN_SPRG7R
-#define SPRN_SPRG_WSCRATCH4	SPRN_SPRG7W
-#ifdef CONFIG_E200
-#define SPRN_SPRG_RSCRATCH_DBG	SPRN_SPRG6R
-#define SPRN_SPRG_WSCRATCH_DBG	SPRN_SPRG6W
-#else
-#define SPRN_SPRG_RSCRATCH_DBG	SPRN_SPRG9
-#define SPRN_SPRG_WSCRATCH_DBG	SPRN_SPRG9
-#endif
-#define SPRN_SPRG_RVCPU		SPRN_SPRG1
-#define SPRN_SPRG_WVCPU		SPRN_SPRG1
-#endif
-
-#ifdef CONFIG_8xx
-#define SPRN_SPRG_SCRATCH0	SPRN_SPRG0
-#define SPRN_SPRG_SCRATCH1	SPRN_SPRG1
-#endif
-
-
-
-/*
- * An mtfsf instruction with the L bit set. On CPUs that support this a
- * full 64bits of FPSCR is restored and on other CPUs the L bit is ignored.
- *
- * Until binutils gets the new form of mtfsf, hardwire the instruction.
- */
-#ifdef CONFIG_PPC64
-#define MTFSF_L(REG) \
-	.long (0xfc00058e | ((0xff) << 17) | ((REG) << 11) | (1 << 25))
-#else
-#define MTFSF_L(REG)	mtfsf	0xff, (REG)
-#endif
-
-/* Processor Version Register (PVR) field extraction */
-
-#define PVR_VER(pvr)	(((pvr) >>  16) & 0xFFFF)	/* Version field */
-#define PVR_REV(pvr)	(((pvr) >>   0) & 0xFFFF)	/* Revison field */
-
-#define __is_processor(pv)	(PVR_VER(mfspr(SPRN_PVR)) == (pv))
-
-/*
- * IBM has further subdivided the standard PowerPC 16-bit version and
- * revision subfields of the PVR for the PowerPC 403s into the following:
- */
-
-#define PVR_FAM(pvr)	(((pvr) >> 20) & 0xFFF)	/* Family field */
-#define PVR_MEM(pvr)	(((pvr) >> 16) & 0xF)	/* Member field */
-#define PVR_CORE(pvr)	(((pvr) >> 12) & 0xF)	/* Core field */
-#define PVR_CFG(pvr)	(((pvr) >>  8) & 0xF)	/* Configuration field */
-#define PVR_MAJ(pvr)	(((pvr) >>  4) & 0xF)	/* Major revision field */
-#define PVR_MIN(pvr)	(((pvr) >>  0) & 0xF)	/* Minor revision field */
-
-/* Processor Version Numbers */
-
-#define PVR_403GA	0x00200000
-#define PVR_403GB	0x00200100
-#define PVR_403GC	0x00200200
-#define PVR_403GCX	0x00201400
-#define PVR_405GP	0x40110000
-#define PVR_476		0x11a52000
-#define PVR_476FPE	0x7ff50000
-#define PVR_STB03XXX	0x40310000
-#define PVR_NP405H	0x41410000
-#define PVR_NP405L	0x41610000
-#define PVR_601		0x00010000
-#define PVR_602		0x00050000
-#define PVR_603		0x00030000
-#define PVR_603e	0x00060000
-#define PVR_603ev	0x00070000
-#define PVR_603r	0x00071000
-#define PVR_604		0x00040000
-#define PVR_604e	0x00090000
-#define PVR_604r	0x000A0000
-#define PVR_620		0x00140000
-#define PVR_740		0x00080000
-#define PVR_750		PVR_740
-#define PVR_740P	0x10080000
-#define PVR_750P	PVR_740P
-#define PVR_7400	0x000C0000
-#define PVR_7410	0x800C0000
-#define PVR_7450	0x80000000
-#define PVR_8540	0x80200000
-#define PVR_8560	0x80200000
-#define PVR_VER_E500V1	0x8020
-#define PVR_VER_E500V2	0x8021
-/*
- * For the 8xx processors, all of them report the same PVR family for
- * the PowerPC core. The various versions of these processors must be
- * differentiated by the version number in the Communication Processor
- * Module (CPM).
- */
-#define PVR_821		0x00500000
-#define PVR_823		PVR_821
-#define PVR_850		PVR_821
-#define PVR_860		PVR_821
-#define PVR_8240	0x00810100
-#define PVR_8245	0x80811014
-#define PVR_8260	PVR_8240
-
-/* 476 Simulator seems to currently have the PVR of the 602... */
-#define PVR_476_ISS	0x00052000
-
-/* 64-bit processors */
-/* XXX the prefix should be PVR_, we'll do a global sweep to fix it one day */
-#define PV_NORTHSTAR	0x0033
-#define PV_PULSAR	0x0034
-#define PV_POWER4	0x0035
-#define PV_ICESTAR	0x0036
-#define PV_SSTAR	0x0037
-#define PV_POWER4p	0x0038
-#define PV_970		0x0039
-#define PV_POWER5	0x003A
-#define PV_POWER5p	0x003B
-#define PV_970FX	0x003C
-#define PV_POWER6	0x003E
-#define PV_POWER7	0x003F
-#define PV_630		0x0040
-#define PV_630p	0x0041
-#define PV_970MP	0x0044
-#define PV_970GX	0x0045
-#define PV_BE		0x0070
-#define PV_PA6T		0x0090
-
-/* Macros for setting and retrieving special purpose registers */
-#ifndef __ASSEMBLY__
-#define mfmsr()		({unsigned long rval; \
-			asm volatile("mfmsr %0" : "=r" (rval)); rval;})
-#ifdef CONFIG_PPC_BOOK3S_64
-#define __mtmsrd(v, l)	asm volatile("mtmsrd %0," __stringify(l) \
-				     : : "r" (v) : "memory")
-#define mtmsrd(v)	__mtmsrd((v), 0)
-#define mtmsr(v)	mtmsrd(v)
-#else
-#define mtmsr(v)	asm volatile("mtmsr %0" : \
-				     : "r" ((unsigned long)(v)) \
-				     : "memory")
-#endif
-
-#define mfspr(rn)	({unsigned long rval; \
-			asm volatile("mfspr %0," __stringify(rn) \
-				: "=r" (rval)); rval;})
-#define mtspr(rn, v)	asm volatile("mtspr " __stringify(rn) ",%0" : \
-				     : "r" ((unsigned long)(v)) \
-				     : "memory")
-
-#ifdef __powerpc64__
-#ifdef CONFIG_PPC_CELL
-#define mftb()		({unsigned long rval;				\
-			asm volatile(					\
-				"90:	mftb %0;\n"			\
-				"97:	cmpwi %0,0;\n"			\
-				"	beq- 90b;\n"			\
-				"99:\n"					\
-				".section __ftr_fixup,\"a\"\n"		\
-				".align 3\n"				\
-				"98:\n"					\
-				"	.llong %1\n"			\
-				"	.llong %1\n"			\
-				"	.llong 97b-98b\n"		\
-				"	.llong 99b-98b\n"		\
-				"	.llong 0\n"			\
-				"	.llong 0\n"			\
-				".previous"				\
-			: "=r" (rval) : "i" (CPU_FTR_CELL_TB_BUG)); rval;})
-#else
-#define mftb()		({unsigned long rval;	\
-			asm volatile("mftb %0" : "=r" (rval)); rval;})
-#endif /* !CONFIG_PPC_CELL */
-
-#else /* __powerpc64__ */
-
-#define mftbl()		({unsigned long rval;	\
-			asm volatile("mftbl %0" : "=r" (rval)); rval;})
-#define mftbu()		({unsigned long rval;	\
-			asm volatile("mftbu %0" : "=r" (rval)); rval;})
-#endif /* !__powerpc64__ */
-
-#define mttbl(v)	asm volatile("mttbl %0":: "r"(v))
-#define mttbu(v)	asm volatile("mttbu %0":: "r"(v))
-
-#ifdef CONFIG_PPC32
-#define mfsrin(v)	({unsigned int rval; \
-			asm volatile("mfsrin %0,%1" : "=r" (rval) : "r" (v)); \
-					rval;})
-#endif
-
-#define proc_trap()	asm volatile("trap")
-
-#define __get_SP()	({unsigned long sp; \
-			asm volatile("mr %0,1": "=r" (sp)); sp;})
-
-extern unsigned long scom970_read(unsigned int address);
-extern void scom970_write(unsigned int address, unsigned long value);
-
-struct pt_regs;
-
-extern void ppc_save_regs(struct pt_regs *regs);
-
-#endif /* __ASSEMBLY__ */
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_REG_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/reg_8xx.h b/ANDROID_3.4.5/arch/powerpc/include/asm/reg_8xx.h
deleted file mode 100644
index e8ea346b..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/reg_8xx.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Contains register definitions common to PowerPC 8xx CPUs.  Notice
- */
-#ifndef _ASM_POWERPC_REG_8xx_H
-#define _ASM_POWERPC_REG_8xx_H
-
-/* Cache control on the MPC8xx is provided through some additional
- * special purpose registers.
- */
-#define SPRN_IC_CST	560	/* Instruction cache control/status */
-#define SPRN_IC_ADR	561	/* Address needed for some commands */
-#define SPRN_IC_DAT	562	/* Read-only data register */
-#define SPRN_DC_CST	568	/* Data cache control/status */
-#define SPRN_DC_ADR	569	/* Address needed for some commands */
-#define SPRN_DC_DAT	570	/* Read-only data register */
-
-/* Commands.  Only the first few are available to the instruction cache.
-*/
-#define	IDC_ENABLE	0x02000000	/* Cache enable */
-#define IDC_DISABLE	0x04000000	/* Cache disable */
-#define IDC_LDLCK	0x06000000	/* Load and lock */
-#define IDC_UNLINE	0x08000000	/* Unlock line */
-#define IDC_UNALL	0x0a000000	/* Unlock all */
-#define IDC_INVALL	0x0c000000	/* Invalidate all */
-
-#define DC_FLINE	0x0e000000	/* Flush data cache line */
-#define DC_SFWT		0x01000000	/* Set forced writethrough mode */
-#define DC_CFWT		0x03000000	/* Clear forced writethrough mode */
-#define DC_SLES		0x05000000	/* Set little endian swap mode */
-#define DC_CLES		0x07000000	/* Clear little endian swap mode */
-
-/* Status.
-*/
-#define IDC_ENABLED	0x80000000	/* Cache is enabled */
-#define IDC_CERR1	0x00200000	/* Cache error 1 */
-#define IDC_CERR2	0x00100000	/* Cache error 2 */
-#define IDC_CERR3	0x00080000	/* Cache error 3 */
-
-#define DC_DFWT		0x40000000	/* Data cache is forced write through */
-#define DC_LES		0x20000000	/* Caches are little endian mode */
-
-#endif /* _ASM_POWERPC_REG_8xx_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/reg_a2.h b/ANDROID_3.4.5/arch/powerpc/include/asm/reg_a2.h
deleted file mode 100644
index 3d52a113..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/reg_a2.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- *  Register definitions specific to the A2 core
- *
- *  Copyright (C) 2008 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
- *
- *  This program is free software; you can redistribute it and/or
- *  modify it under the terms of the GNU General Public License
- *  as published by the Free Software Foundation; either version
- *  2 of the License, or (at your option) any later version.
- */
-
-#ifndef __ASM_POWERPC_REG_A2_H__
-#define __ASM_POWERPC_REG_A2_H__
-
-#define SPRN_TENSR	0x1b5
-#define SPRN_TENS	0x1b6	/* Thread ENable Set */
-#define SPRN_TENC	0x1b7	/* Thread ENable Clear */
-
-#define SPRN_A2_CCR0	0x3f0	/* Core Configuration Register 0 */
-#define SPRN_A2_CCR1	0x3f1	/* Core Configuration Register 1 */
-#define SPRN_A2_CCR2	0x3f2	/* Core Configuration Register 2 */
-#define SPRN_MMUCR0	0x3fc	/* MMU Control Register 0 */
-#define SPRN_MMUCR1	0x3fd	/* MMU Control Register 1 */
-#define SPRN_MMUCR2	0x3fe	/* MMU Control Register 2 */
-#define SPRN_MMUCR3	0x3ff	/* MMU Control Register 3 */
-
-#define SPRN_IAR	0x372
-
-#define SPRN_IUCR0	0x3f3
-#define IUCR0_ICBI_ACK	0x1000
-
-#define SPRN_XUCR0	0x3f6	/* Execution Unit Config Register 0 */
-
-#define A2_IERAT_SIZE	16
-#define A2_DERAT_SIZE	32
-
-/* A2 MMUCR0 bits */
-#define MMUCR0_ECL	0x80000000	/* Extended Class for TLB fills */
-#define MMUCR0_TID_NZ	0x40000000	/* TID is non-zero */
-#define MMUCR0_TS	0x10000000	/* Translation space for TLB fills */
-#define MMUCR0_TGS	0x20000000	/* Guest space for TLB fills */
-#define MMUCR0_TLBSEL	0x0c000000	/* TLB or ERAT target for TLB fills */
-#define MMUCR0_TLBSEL_U	0x00000000	/*  TLBSEL = UTLB */
-#define MMUCR0_TLBSEL_I	0x08000000	/*  TLBSEL = I-ERAT */
-#define MMUCR0_TLBSEL_D	0x0c000000	/*  TLBSEL = D-ERAT */
-#define MMUCR0_LOCKSRSH	0x02000000	/* Use TLB lock on tlbsx. */
-#define MMUCR0_TID_MASK	0x000000ff	/* TID field */
-
-/* A2 MMUCR1 bits */
-#define MMUCR1_IRRE		0x80000000	/* I-ERAT round robin enable */
-#define MMUCR1_DRRE		0x40000000	/* D-ERAT round robin enable */
-#define MMUCR1_REE		0x20000000	/* Reference Exception Enable*/
-#define MMUCR1_CEE		0x10000000	/* Change exception enable */
-#define MMUCR1_CSINV_ALL	0x00000000	/* Inval ERAT on all CS evts */
-#define MMUCR1_CSINV_NISYNC	0x04000000	/* Inval ERAT on all ex isync*/
-#define MMUCR1_CSINV_NEVER	0x0c000000	/* Don't inval ERAT on CS */
-#define MMUCR1_ICTID		0x00080000	/* IERAT class field as TID */
-#define MMUCR1_ITTID		0x00040000	/* IERAT thdid field as TID */
-#define MMUCR1_DCTID		0x00020000	/* DERAT class field as TID */
-#define MMUCR1_DTTID		0x00010000	/* DERAT thdid field as TID */
-#define MMUCR1_DCCD		0x00008000	/* DERAT class ignore */
-#define MMUCR1_TLBWE_BINV	0x00004000	/* back invalidate on tlbwe */
-
-/* A2 MMUCR2 bits */
-#define MMUCR2_PSSEL_SHIFT	4
-
-/* A2 MMUCR3 bits */
-#define MMUCR3_THID		0x0000000f	/* Thread ID */
-
-/* *** ERAT TLB bits definitions */
-#define TLB0_EPN_MASK		ASM_CONST(0xfffffffffffff000)
-#define TLB0_CLASS_MASK		ASM_CONST(0x0000000000000c00)
-#define TLB0_CLASS_00		ASM_CONST(0x0000000000000000)
-#define TLB0_CLASS_01		ASM_CONST(0x0000000000000400)
-#define TLB0_CLASS_10		ASM_CONST(0x0000000000000800)
-#define TLB0_CLASS_11		ASM_CONST(0x0000000000000c00)
-#define TLB0_V			ASM_CONST(0x0000000000000200)
-#define TLB0_X			ASM_CONST(0x0000000000000100)
-#define TLB0_SIZE_MASK		ASM_CONST(0x00000000000000f0)
-#define TLB0_SIZE_4K		ASM_CONST(0x0000000000000010)
-#define TLB0_SIZE_64K		ASM_CONST(0x0000000000000030)
-#define TLB0_SIZE_1M		ASM_CONST(0x0000000000000050)
-#define TLB0_SIZE_16M		ASM_CONST(0x0000000000000070)
-#define TLB0_SIZE_1G		ASM_CONST(0x00000000000000a0)
-#define TLB0_THDID_MASK		ASM_CONST(0x000000000000000f)
-#define TLB0_THDID_0		ASM_CONST(0x0000000000000001)
-#define TLB0_THDID_1		ASM_CONST(0x0000000000000002)
-#define TLB0_THDID_2		ASM_CONST(0x0000000000000004)
-#define TLB0_THDID_3		ASM_CONST(0x0000000000000008)
-#define TLB0_THDID_ALL		ASM_CONST(0x000000000000000f)
-
-#define TLB1_RESVATTR		ASM_CONST(0x00f0000000000000)
-#define TLB1_U0			ASM_CONST(0x0008000000000000)
-#define TLB1_U1			ASM_CONST(0x0004000000000000)
-#define TLB1_U2			ASM_CONST(0x0002000000000000)
-#define TLB1_U3			ASM_CONST(0x0001000000000000)
-#define TLB1_R			ASM_CONST(0x0000800000000000)
-#define TLB1_C			ASM_CONST(0x0000400000000000)
-#define TLB1_RPN_MASK		ASM_CONST(0x000003fffffff000)
-#define TLB1_W			ASM_CONST(0x0000000000000800)
-#define TLB1_I			ASM_CONST(0x0000000000000400)
-#define TLB1_M			ASM_CONST(0x0000000000000200)
-#define TLB1_G			ASM_CONST(0x0000000000000100)
-#define TLB1_E			ASM_CONST(0x0000000000000080)
-#define TLB1_VF			ASM_CONST(0x0000000000000040)
-#define TLB1_UX			ASM_CONST(0x0000000000000020)
-#define TLB1_SX			ASM_CONST(0x0000000000000010)
-#define TLB1_UW			ASM_CONST(0x0000000000000008)
-#define TLB1_SW			ASM_CONST(0x0000000000000004)
-#define TLB1_UR			ASM_CONST(0x0000000000000002)
-#define TLB1_SR			ASM_CONST(0x0000000000000001)
-
-#ifdef CONFIG_PPC_EARLY_DEBUG_WSP
-#define WSP_UART_PHYS	0xffc000c000
-/* This needs to be careful chosen to hit a !0 congruence class
- * in the TLB since we bolt it in way 3, which is already occupied
- * by our linear mapping primary bolted entry in CC 0.
- */
-#define WSP_UART_VIRT	0xf000000000001000
-#endif
-
-/* A2 erativax attributes definitions */
-#define ERATIVAX_RS_IS_ALL		0x000
-#define ERATIVAX_RS_IS_TID		0x040
-#define ERATIVAX_RS_IS_CLASS		0x080
-#define ERATIVAX_RS_IS_FULLMATCH	0x0c0
-#define ERATIVAX_CLASS_00		0x000
-#define ERATIVAX_CLASS_01		0x010
-#define ERATIVAX_CLASS_10		0x020
-#define ERATIVAX_CLASS_11		0x030
-#define ERATIVAX_PSIZE_4K		(TLB_PSIZE_4K >> 1)
-#define ERATIVAX_PSIZE_64K		(TLB_PSIZE_64K >> 1)
-#define ERATIVAX_PSIZE_1M		(TLB_PSIZE_1M >> 1)
-#define ERATIVAX_PSIZE_16M		(TLB_PSIZE_16M >> 1)
-#define ERATIVAX_PSIZE_1G		(TLB_PSIZE_1G >> 1)
-
-/* A2 eratilx attributes definitions */
-#define ERATILX_T_ALL			0
-#define ERATILX_T_TID			1
-#define ERATILX_T_TGS			2
-#define ERATILX_T_FULLMATCH		3
-#define ERATILX_T_CLASS0		4
-#define ERATILX_T_CLASS1		5
-#define ERATILX_T_CLASS2		6
-#define ERATILX_T_CLASS3		7
-
-/* XUCR0 bits */
-#define XUCR0_TRACE_UM_T0		0x40000000	/* Thread 0 */
-#define XUCR0_TRACE_UM_T1		0x20000000	/* Thread 1 */
-#define XUCR0_TRACE_UM_T2		0x10000000	/* Thread 2 */
-#define XUCR0_TRACE_UM_T3		0x08000000	/* Thread 3 */
-
-/* A2 CCR0 register */
-#define A2_CCR0_PME_DISABLED		0x00000000
-#define A2_CCR0_PME_SLEEP		0x40000000
-#define A2_CCR0_PME_RVW			0x80000000
-#define A2_CCR0_PME_DISABLED2		0xc0000000
-
-/* A2 CCR2 register */
-#define A2_CCR2_ERAT_ONLY_MODE		0x00000001
-#define A2_CCR2_ENABLE_ICSWX		0x00000002
-#define A2_CCR2_ENABLE_PC		0x20000000
-#define A2_CCR2_ENABLE_TRACE		0x40000000
-
-#endif /* __ASM_POWERPC_REG_A2_H__ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/reg_booke.h b/ANDROID_3.4.5/arch/powerpc/include/asm/reg_booke.h
deleted file mode 100644
index 8a97aa72..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/reg_booke.h
+++ /dev/null
@@ -1,672 +0,0 @@
-/*
- * Contains register definitions common to the Book E PowerPC
- * specification.  Notice that while the IBM-40x series of CPUs
- * are not true Book E PowerPCs, they borrowed a number of features
- * before Book E was finalized, and are included here as well.  Unfortunately,
- * they sometimes used different locations than true Book E CPUs did.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * Copyright 2009-2010 Freescale Semiconductor, Inc.
- */
-#ifdef __KERNEL__
-#ifndef __ASM_POWERPC_REG_BOOKE_H__
-#define __ASM_POWERPC_REG_BOOKE_H__
-
-/* Machine State Register (MSR) Fields */
-#define MSR_GS		(1<<28) /* Guest state */
-#define MSR_UCLE	(1<<26)	/* User-mode cache lock enable */
-#define MSR_SPE		(1<<25)	/* Enable SPE */
-#define MSR_DWE		(1<<10)	/* Debug Wait Enable */
-#define MSR_UBLE	(1<<10)	/* BTB lock enable (e500) */
-#define MSR_IS		MSR_IR	/* Instruction Space */
-#define MSR_DS		MSR_DR	/* Data Space */
-#define MSR_PMM		(1<<2)	/* Performance monitor mark bit */
-#define MSR_CM		(1<<31) /* Computation Mode (0=32-bit, 1=64-bit) */
-
-#if defined(CONFIG_PPC_BOOK3E_64)
-#define MSR_64BIT	MSR_CM
-
-#define MSR_		MSR_ME | MSR_CE
-#define MSR_KERNEL	MSR_ | MSR_64BIT
-#define MSR_USER32	MSR_ | MSR_PR | MSR_EE
-#define MSR_USER64	MSR_USER32 | MSR_64BIT
-#elif defined (CONFIG_40x)
-#define MSR_KERNEL	(MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE)
-#define MSR_USER	(MSR_KERNEL|MSR_PR|MSR_EE)
-#else
-#define MSR_KERNEL	(MSR_ME|MSR_RI|MSR_CE)
-#define MSR_USER	(MSR_KERNEL|MSR_PR|MSR_EE)
-#endif
-
-/* Special Purpose Registers (SPRNs)*/
-#define SPRN_DECAR	0x036	/* Decrementer Auto Reload Register */
-#define SPRN_IVPR	0x03F	/* Interrupt Vector Prefix Register */
-#define SPRN_USPRG0	0x100	/* User Special Purpose Register General 0 */
-#define SPRN_SPRG3R	0x103	/* Special Purpose Register General 3 Read */
-#define SPRN_SPRG4R	0x104	/* Special Purpose Register General 4 Read */
-#define SPRN_SPRG5R	0x105	/* Special Purpose Register General 5 Read */
-#define SPRN_SPRG6R	0x106	/* Special Purpose Register General 6 Read */
-#define SPRN_SPRG7R	0x107	/* Special Purpose Register General 7 Read */
-#define SPRN_SPRG4W	0x114	/* Special Purpose Register General 4 Write */
-#define SPRN_SPRG5W	0x115	/* Special Purpose Register General 5 Write */
-#define SPRN_SPRG6W	0x116	/* Special Purpose Register General 6 Write */
-#define SPRN_SPRG7W	0x117	/* Special Purpose Register General 7 Write */
-#define SPRN_EPCR	0x133	/* Embedded Processor Control Register */
-#define SPRN_DBCR2	0x136	/* Debug Control Register 2 */
-#define SPRN_IAC3	0x13A	/* Instruction Address Compare 3 */
-#define SPRN_IAC4	0x13B	/* Instruction Address Compare 4 */
-#define SPRN_DVC1	0x13E	/* Data Value Compare Register 1 */
-#define SPRN_DVC2	0x13F	/* Data Value Compare Register 2 */
-#define SPRN_MAS8	0x155	/* MMU Assist Register 8 */
-#define SPRN_TLB0PS	0x158	/* TLB 0 Page Size Register */
-#define SPRN_TLB1PS	0x159	/* TLB 1 Page Size Register */
-#define SPRN_MAS5_MAS6	0x15c	/* MMU Assist Register 5 || 6 */
-#define SPRN_MAS8_MAS1	0x15d	/* MMU Assist Register 8 || 1 */
-#define SPRN_EPTCFG	0x15e	/* Embedded Page Table Config */
-#define SPRN_MAS7_MAS3	0x174	/* MMU Assist Register 7 || 3 */
-#define SPRN_MAS0_MAS1	0x175	/* MMU Assist Register 0 || 1 */
-#define SPRN_IVOR0	0x190	/* Interrupt Vector Offset Register 0 */
-#define SPRN_IVOR1	0x191	/* Interrupt Vector Offset Register 1 */
-#define SPRN_IVOR2	0x192	/* Interrupt Vector Offset Register 2 */
-#define SPRN_IVOR3	0x193	/* Interrupt Vector Offset Register 3 */
-#define SPRN_IVOR4	0x194	/* Interrupt Vector Offset Register 4 */
-#define SPRN_IVOR5	0x195	/* Interrupt Vector Offset Register 5 */
-#define SPRN_IVOR6	0x196	/* Interrupt Vector Offset Register 6 */
-#define SPRN_IVOR7	0x197	/* Interrupt Vector Offset Register 7 */
-#define SPRN_IVOR8	0x198	/* Interrupt Vector Offset Register 8 */
-#define SPRN_IVOR9	0x199	/* Interrupt Vector Offset Register 9 */
-#define SPRN_IVOR10	0x19A	/* Interrupt Vector Offset Register 10 */
-#define SPRN_IVOR11	0x19B	/* Interrupt Vector Offset Register 11 */
-#define SPRN_IVOR12	0x19C	/* Interrupt Vector Offset Register 12 */
-#define SPRN_IVOR13	0x19D	/* Interrupt Vector Offset Register 13 */
-#define SPRN_IVOR14	0x19E	/* Interrupt Vector Offset Register 14 */
-#define SPRN_IVOR15	0x19F	/* Interrupt Vector Offset Register 15 */
-#define SPRN_IVOR38	0x1B0	/* Interrupt Vector Offset Register 38 */
-#define SPRN_IVOR39	0x1B1	/* Interrupt Vector Offset Register 39 */
-#define SPRN_IVOR40	0x1B2	/* Interrupt Vector Offset Register 40 */
-#define SPRN_IVOR41	0x1B3	/* Interrupt Vector Offset Register 41 */
-#define SPRN_SPEFSCR	0x200	/* SPE & Embedded FP Status & Control */
-#define SPRN_BBEAR	0x201	/* Branch Buffer Entry Address Register */
-#define SPRN_BBTAR	0x202	/* Branch Buffer Target Address Register */
-#define SPRN_L1CFG0	0x203	/* L1 Cache Configure Register 0 */
-#define SPRN_L1CFG1	0x204	/* L1 Cache Configure Register 1 */
-#define SPRN_ATB	0x20E	/* Alternate Time Base */
-#define SPRN_ATBL	0x20E	/* Alternate Time Base Lower */
-#define SPRN_ATBU	0x20F	/* Alternate Time Base Upper */
-#define SPRN_IVOR32	0x210	/* Interrupt Vector Offset Register 32 */
-#define SPRN_IVOR33	0x211	/* Interrupt Vector Offset Register 33 */
-#define SPRN_IVOR34	0x212	/* Interrupt Vector Offset Register 34 */
-#define SPRN_IVOR35	0x213	/* Interrupt Vector Offset Register 35 */
-#define SPRN_IVOR36	0x214	/* Interrupt Vector Offset Register 36 */
-#define SPRN_IVOR37	0x215	/* Interrupt Vector Offset Register 37 */
-#define SPRN_MCARU	0x239	/* Machine Check Address Register Upper */
-#define SPRN_MCSRR0	0x23A	/* Machine Check Save and Restore Register 0 */
-#define SPRN_MCSRR1	0x23B	/* Machine Check Save and Restore Register 1 */
-#define SPRN_MCSR	0x23C	/* Machine Check Status Register */
-#define SPRN_MCAR	0x23D	/* Machine Check Address Register */
-#define SPRN_DSRR0	0x23E	/* Debug Save and Restore Register 0 */
-#define SPRN_DSRR1	0x23F	/* Debug Save and Restore Register 1 */
-#define SPRN_SPRG8	0x25C	/* Special Purpose Register General 8 */
-#define SPRN_SPRG9	0x25D	/* Special Purpose Register General 9 */
-#define SPRN_L1CSR2	0x25E	/* L1 Cache Control and Status Register 2 */
-#define SPRN_MAS0	0x270	/* MMU Assist Register 0 */
-#define SPRN_MAS1	0x271	/* MMU Assist Register 1 */
-#define SPRN_MAS2	0x272	/* MMU Assist Register 2 */
-#define SPRN_MAS3	0x273	/* MMU Assist Register 3 */
-#define SPRN_MAS4	0x274	/* MMU Assist Register 4 */
-#define SPRN_MAS5	0x153	/* MMU Assist Register 5 */
-#define SPRN_MAS6	0x276	/* MMU Assist Register 6 */
-#define SPRN_PID1	0x279	/* Process ID Register 1 */
-#define SPRN_PID2	0x27A	/* Process ID Register 2 */
-#define SPRN_TLB0CFG	0x2B0	/* TLB 0 Config Register */
-#define SPRN_TLB1CFG	0x2B1	/* TLB 1 Config Register */
-#define SPRN_TLB2CFG	0x2B2	/* TLB 2 Config Register */
-#define SPRN_TLB3CFG	0x2B3	/* TLB 3 Config Register */
-#define SPRN_EPR	0x2BE	/* External Proxy Register */
-#define SPRN_CCR1	0x378	/* Core Configuration Register 1 */
-#define SPRN_ZPR	0x3B0	/* Zone Protection Register (40x) */
-#define SPRN_MAS7	0x3B0	/* MMU Assist Register 7 */
-#define SPRN_MMUCR	0x3B2	/* MMU Control Register */
-#define SPRN_CCR0	0x3B3	/* Core Configuration Register 0 */
-#define SPRN_EPLC	0x3B3	/* External Process ID Load Context */
-#define SPRN_EPSC	0x3B4	/* External Process ID Store Context */
-#define SPRN_SGR	0x3B9	/* Storage Guarded Register */
-#define SPRN_DCWR	0x3BA	/* Data Cache Write-thru Register */
-#define SPRN_SLER	0x3BB	/* Little-endian real mode */
-#define SPRN_SU0R	0x3BC	/* "User 0" real mode (40x) */
-#define SPRN_DCMP	0x3D1	/* Data TLB Compare Register */
-#define SPRN_ICDBDR	0x3D3	/* Instruction Cache Debug Data Register */
-#define SPRN_EVPR	0x3D6	/* Exception Vector Prefix Register */
-#define SPRN_L1CSR0	0x3F2	/* L1 Cache Control and Status Register 0 */
-#define SPRN_L1CSR1	0x3F3	/* L1 Cache Control and Status Register 1 */
-#define SPRN_MMUCSR0	0x3F4	/* MMU Control and Status Register 0 */
-#define SPRN_MMUCFG	0x3F7	/* MMU Configuration Register */
-#define SPRN_PIT	0x3DB	/* Programmable Interval Timer */
-#define SPRN_BUCSR	0x3F5	/* Branch Unit Control and Status */
-#define SPRN_L2CSR0	0x3F9	/* L2 Data Cache Control and Status Register 0 */
-#define SPRN_L2CSR1	0x3FA	/* L2 Data Cache Control and Status Register 1 */
-#define SPRN_DCCR	0x3FA	/* Data Cache Cacheability Register */
-#define SPRN_ICCR	0x3FB	/* Instruction Cache Cacheability Register */
-#define SPRN_SVR	0x3FF	/* System Version Register */
-
-/*
- * SPRs which have conflicting definitions on true Book E versus classic,
- * or IBM 40x.
- */
-#ifdef CONFIG_BOOKE
-#define SPRN_CSRR0	0x03A	/* Critical Save and Restore Register 0 */
-#define SPRN_CSRR1	0x03B	/* Critical Save and Restore Register 1 */
-#define SPRN_DEAR	0x03D	/* Data Error Address Register */
-#define SPRN_ESR	0x03E	/* Exception Syndrome Register */
-#define SPRN_PIR	0x11E	/* Processor Identification Register */
-#define SPRN_DBSR	0x130	/* Debug Status Register */
-#define SPRN_DBCR0	0x134	/* Debug Control Register 0 */
-#define SPRN_DBCR1	0x135	/* Debug Control Register 1 */
-#define SPRN_IAC1	0x138	/* Instruction Address Compare 1 */
-#define SPRN_IAC2	0x139	/* Instruction Address Compare 2 */
-#define SPRN_DAC1	0x13C	/* Data Address Compare 1 */
-#define SPRN_DAC2	0x13D	/* Data Address Compare 2 */
-#define SPRN_TSR	0x150	/* Timer Status Register */
-#define SPRN_TCR	0x154	/* Timer Control Register */
-#endif /* Book E */
-#ifdef CONFIG_40x
-#define SPRN_DBCR1	0x3BD	/* Debug Control Register 1 */		
-#define SPRN_ESR	0x3D4	/* Exception Syndrome Register */
-#define SPRN_DEAR	0x3D5	/* Data Error Address Register */
-#define SPRN_TSR	0x3D8	/* Timer Status Register */
-#define SPRN_TCR	0x3DA	/* Timer Control Register */
-#define SPRN_SRR2	0x3DE	/* Save/Restore Register 2 */
-#define SPRN_SRR3	0x3DF	/* Save/Restore Register 3 */
-#define SPRN_DBSR	0x3F0	/* Debug Status Register */		
-#define SPRN_DBCR0	0x3F2	/* Debug Control Register 0 */
-#define SPRN_DAC1	0x3F6	/* Data Address Compare 1 */
-#define SPRN_DAC2	0x3F7	/* Data Address Compare 2 */
-#define SPRN_CSRR0	SPRN_SRR2 /* Critical Save and Restore Register 0 */
-#define SPRN_CSRR1	SPRN_SRR3 /* Critical Save and Restore Register 1 */
-#endif
-
-#ifdef CONFIG_PPC_ICSWX
-#define SPRN_HACOP	0x15F	/* Hypervisor Available Coprocessor Register */
-#endif
-
-/* Bit definitions for CCR1. */
-#define	CCR1_DPC	0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */
-#define	CCR1_TCS	0x00000080 /* Timer Clock Select */
-
-/* Bit definitions for the MCSR. */
-#define MCSR_MCS	0x80000000 /* Machine Check Summary */
-#define MCSR_IB		0x40000000 /* Instruction PLB Error */
-#define MCSR_DRB	0x20000000 /* Data Read PLB Error */
-#define MCSR_DWB	0x10000000 /* Data Write PLB Error */
-#define MCSR_TLBP	0x08000000 /* TLB Parity Error */
-#define MCSR_ICP	0x04000000 /* I-Cache Parity Error */
-#define MCSR_DCSP	0x02000000 /* D-Cache Search Parity Error */
-#define MCSR_DCFP	0x01000000 /* D-Cache Flush Parity Error */
-#define MCSR_IMPE	0x00800000 /* Imprecise Machine Check Exception */
-
-#define PPC47x_MCSR_GPR	0x01000000 /* GPR parity error */
-#define PPC47x_MCSR_FPR	0x00800000 /* FPR parity error */
-#define PPC47x_MCSR_IPR	0x00400000 /* Imprecise Machine Check Exception */
-
-#ifdef CONFIG_E500
-/* All e500 */
-#define MCSR_MCP 	0x80000000UL /* Machine Check Input Pin */
-#define MCSR_ICPERR 	0x40000000UL /* I-Cache Parity Error */
-
-/* e500v1/v2 */
-#define MCSR_DCP_PERR 	0x20000000UL /* D-Cache Push Parity Error */
-#define MCSR_DCPERR 	0x10000000UL /* D-Cache Parity Error */
-#define MCSR_BUS_IAERR 	0x00000080UL /* Instruction Address Error */
-#define MCSR_BUS_RAERR 	0x00000040UL /* Read Address Error */
-#define MCSR_BUS_WAERR 	0x00000020UL /* Write Address Error */
-#define MCSR_BUS_IBERR 	0x00000010UL /* Instruction Data Error */
-#define MCSR_BUS_RBERR 	0x00000008UL /* Read Data Bus Error */
-#define MCSR_BUS_WBERR 	0x00000004UL /* Write Data Bus Error */
-#define MCSR_BUS_IPERR 	0x00000002UL /* Instruction parity Error */
-#define MCSR_BUS_RPERR 	0x00000001UL /* Read parity Error */
-
-/* e500mc */
-#define MCSR_DCPERR_MC	0x20000000UL /* D-Cache Parity Error */
-#define MCSR_L2MMU_MHIT	0x04000000UL /* Hit on multiple TLB entries */
-#define MCSR_NMI	0x00100000UL /* Non-Maskable Interrupt */
-#define MCSR_MAV	0x00080000UL /* MCAR address valid */
-#define MCSR_MEA	0x00040000UL /* MCAR is effective address */
-#define MCSR_IF		0x00010000UL /* Instruction Fetch */
-#define MCSR_LD		0x00008000UL /* Load */
-#define MCSR_ST		0x00004000UL /* Store */
-#define MCSR_LDG	0x00002000UL /* Guarded Load */
-#define MCSR_TLBSYNC	0x00000002UL /* Multiple tlbsyncs detected */
-#define MCSR_BSL2_ERR	0x00000001UL /* Backside L2 cache error */
-#endif
-
-#ifdef CONFIG_E200
-#define MCSR_MCP 	0x80000000UL /* Machine Check Input Pin */
-#define MCSR_CP_PERR 	0x20000000UL /* Cache Push Parity Error */
-#define MCSR_CPERR 	0x10000000UL /* Cache Parity Error */
-#define MCSR_EXCP_ERR 	0x08000000UL /* ISI, ITLB, or Bus Error on 1st insn
-					fetch for an exception handler */
-#define MCSR_BUS_IRERR 	0x00000010UL /* Read Bus Error on instruction fetch*/
-#define MCSR_BUS_DRERR 	0x00000008UL /* Read Bus Error on data load */
-#define MCSR_BUS_WRERR 	0x00000004UL /* Write Bus Error on buffered
-					store or cache line push */
-#endif
-
-/* Bit definitions for the HID1 */
-#ifdef CONFIG_E500
-/* e500v1/v2 */
-#define HID1_PLL_CFG_MASK 0xfc000000	/* PLL_CFG input pins */
-#define HID1_RFXE	0x00020000	/* Read fault exception enable */
-#define HID1_R1DPE	0x00008000	/* R1 data bus parity enable */
-#define HID1_R2DPE	0x00004000	/* R2 data bus parity enable */
-#define HID1_ASTME	0x00002000	/* Address bus streaming mode enable */
-#define HID1_ABE	0x00001000	/* Address broadcast enable */
-#define HID1_MPXTT	0x00000400	/* MPX re-map transfer type */
-#define HID1_ATS	0x00000080	/* Atomic status */
-#define HID1_MID_MASK	0x0000000f	/* MID input pins */
-#endif
-
-/* Bit definitions for the DBSR. */
-/*
- * DBSR bits which have conflicting definitions on true Book E versus IBM 40x.
- */
-#ifdef CONFIG_BOOKE
-#define DBSR_IC		0x08000000	/* Instruction Completion */
-#define DBSR_BT		0x04000000	/* Branch Taken */
-#define DBSR_IRPT	0x02000000	/* Exception Debug Event */
-#define DBSR_TIE	0x01000000	/* Trap Instruction Event */
-#define DBSR_IAC1	0x00800000	/* Instr Address Compare 1 Event */
-#define DBSR_IAC2	0x00400000	/* Instr Address Compare 2 Event */
-#define DBSR_IAC3	0x00200000	/* Instr Address Compare 3 Event */
-#define DBSR_IAC4	0x00100000	/* Instr Address Compare 4 Event */
-#define DBSR_DAC1R	0x00080000	/* Data Addr Compare 1 Read Event */
-#define DBSR_DAC1W	0x00040000	/* Data Addr Compare 1 Write Event */
-#define DBSR_DAC2R	0x00020000	/* Data Addr Compare 2 Read Event */
-#define DBSR_DAC2W	0x00010000	/* Data Addr Compare 2 Write Event */
-#define DBSR_RET	0x00008000	/* Return Debug Event */
-#define DBSR_CIRPT	0x00000040	/* Critical Interrupt Taken Event */
-#define DBSR_CRET	0x00000020	/* Critical Return Debug Event */
-#define DBSR_IAC12ATS	0x00000002	/* Instr Address Compare 1/2 Toggle */
-#define DBSR_IAC34ATS	0x00000001	/* Instr Address Compare 3/4 Toggle */
-#endif
-#ifdef CONFIG_40x
-#define DBSR_IC		0x80000000	/* Instruction Completion */
-#define DBSR_BT		0x40000000	/* Branch taken */
-#define DBSR_IRPT	0x20000000	/* Exception Debug Event */
-#define DBSR_TIE	0x10000000	/* Trap Instruction debug Event */
-#define DBSR_IAC1	0x04000000	/* Instruction Address Compare 1 Event */
-#define DBSR_IAC2	0x02000000	/* Instruction Address Compare 2 Event */
-#define DBSR_IAC3	0x00080000	/* Instruction Address Compare 3 Event */
-#define DBSR_IAC4	0x00040000	/* Instruction Address Compare 4 Event */
-#define DBSR_DAC1R	0x01000000	/* Data Address Compare 1 Read Event */
-#define DBSR_DAC1W	0x00800000	/* Data Address Compare 1 Write Event */
-#define DBSR_DAC2R	0x00400000	/* Data Address Compare 2 Read Event */
-#define DBSR_DAC2W	0x00200000	/* Data Address Compare 2 Write Event */
-#endif
-
-/* Bit definitions related to the ESR. */
-#define ESR_MCI		0x80000000	/* Machine Check - Instruction */
-#define ESR_IMCP	0x80000000	/* Instr. Machine Check - Protection */
-#define ESR_IMCN	0x40000000	/* Instr. Machine Check - Non-config */
-#define ESR_IMCB	0x20000000	/* Instr. Machine Check - Bus error */
-#define ESR_IMCT	0x10000000	/* Instr. Machine Check - Timeout */
-#define ESR_PIL		0x08000000	/* Program Exception - Illegal */
-#define ESR_PPR		0x04000000	/* Program Exception - Privileged */
-#define ESR_PTR		0x02000000	/* Program Exception - Trap */
-#define ESR_FP		0x01000000	/* Floating Point Operation */
-#define ESR_DST		0x00800000	/* Storage Exception - Data miss */
-#define ESR_DIZ		0x00400000	/* Storage Exception - Zone fault */
-#define ESR_ST		0x00800000	/* Store Operation */
-#define ESR_DLK		0x00200000	/* Data Cache Locking */
-#define ESR_ILK		0x00100000	/* Instr. Cache Locking */
-#define ESR_PUO		0x00040000	/* Unimplemented Operation exception */
-#define ESR_BO		0x00020000	/* Byte Ordering */
-#define ESR_SPV		0x00000080	/* Signal Processing operation */
-
-/* Bit definitions related to the DBCR0. */
-#if defined(CONFIG_40x)
-#define DBCR0_EDM	0x80000000	/* External Debug Mode */
-#define DBCR0_IDM	0x40000000	/* Internal Debug Mode */
-#define DBCR0_RST	0x30000000	/* all the bits in the RST field */
-#define DBCR0_RST_SYSTEM 0x30000000	/* System Reset */
-#define DBCR0_RST_CHIP	0x20000000	/* Chip Reset */
-#define DBCR0_RST_CORE	0x10000000	/* Core Reset */
-#define DBCR0_RST_NONE	0x00000000	/* No Reset */
-#define DBCR0_IC	0x08000000	/* Instruction Completion */
-#define DBCR0_ICMP	DBCR0_IC
-#define DBCR0_BT	0x04000000	/* Branch Taken */
-#define DBCR0_BRT	DBCR0_BT
-#define DBCR0_EDE	0x02000000	/* Exception Debug Event */
-#define DBCR0_IRPT	DBCR0_EDE
-#define DBCR0_TDE	0x01000000	/* TRAP Debug Event */
-#define DBCR0_IA1	0x00800000	/* Instr Addr compare 1 enable */
-#define DBCR0_IAC1	DBCR0_IA1
-#define DBCR0_IA2	0x00400000	/* Instr Addr compare 2 enable */
-#define DBCR0_IAC2	DBCR0_IA2
-#define DBCR0_IA12	0x00200000	/* Instr Addr 1-2 range enable */
-#define DBCR0_IA12X	0x00100000	/* Instr Addr 1-2 range eXclusive */
-#define DBCR0_IA3	0x00080000	/* Instr Addr compare 3 enable */
-#define DBCR0_IAC3	DBCR0_IA3
-#define DBCR0_IA4	0x00040000	/* Instr Addr compare 4 enable */
-#define DBCR0_IAC4	DBCR0_IA4
-#define DBCR0_IA34	0x00020000	/* Instr Addr 3-4 range Enable */
-#define DBCR0_IA34X	0x00010000	/* Instr Addr 3-4 range eXclusive */
-#define DBCR0_IA12T	0x00008000	/* Instr Addr 1-2 range Toggle */
-#define DBCR0_IA34T	0x00004000	/* Instr Addr 3-4 range Toggle */
-#define DBCR0_FT	0x00000001	/* Freeze Timers on debug event */
-
-#define dbcr_iac_range(task)	((task)->thread.dbcr0)
-#define DBCR_IAC12I	DBCR0_IA12			/* Range Inclusive */
-#define DBCR_IAC12X	(DBCR0_IA12 | DBCR0_IA12X)	/* Range Exclusive */
-#define DBCR_IAC12MODE	(DBCR0_IA12 | DBCR0_IA12X)	/* IAC 1-2 Mode Bits */
-#define DBCR_IAC34I	DBCR0_IA34			/* Range Inclusive */
-#define DBCR_IAC34X	(DBCR0_IA34 | DBCR0_IA34X)	/* Range Exclusive */
-#define DBCR_IAC34MODE	(DBCR0_IA34 | DBCR0_IA34X)	/* IAC 3-4 Mode Bits */
-
-/* Bit definitions related to the DBCR1. */
-#define DBCR1_DAC1R	0x80000000	/* DAC1 Read Debug Event */
-#define DBCR1_DAC2R	0x40000000	/* DAC2 Read Debug Event */
-#define DBCR1_DAC1W	0x20000000	/* DAC1 Write Debug Event */
-#define DBCR1_DAC2W	0x10000000	/* DAC2 Write Debug Event */
-
-#define dbcr_dac(task)	((task)->thread.dbcr1)
-#define DBCR_DAC1R	DBCR1_DAC1R
-#define DBCR_DAC1W	DBCR1_DAC1W
-#define DBCR_DAC2R	DBCR1_DAC2R
-#define DBCR_DAC2W	DBCR1_DAC2W
-
-/*
- * Are there any active Debug Events represented in the
- * Debug Control Registers?
- */
-#define DBCR0_ACTIVE_EVENTS	(DBCR0_ICMP | DBCR0_IAC1 | DBCR0_IAC2 | \
-				 DBCR0_IAC3 | DBCR0_IAC4)
-#define DBCR1_ACTIVE_EVENTS	(DBCR1_DAC1R | DBCR1_DAC2R | \
-				 DBCR1_DAC1W | DBCR1_DAC2W)
-#define DBCR_ACTIVE_EVENTS(dbcr0, dbcr1)  (((dbcr0) & DBCR0_ACTIVE_EVENTS) || \
-					   ((dbcr1) & DBCR1_ACTIVE_EVENTS))
-
-#elif defined(CONFIG_BOOKE)
-#define DBCR0_EDM	0x80000000	/* External Debug Mode */
-#define DBCR0_IDM	0x40000000	/* Internal Debug Mode */
-#define DBCR0_RST	0x30000000	/* all the bits in the RST field */
-/* DBCR0_RST_* is 44x specific and not followed in fsl booke */
-#define DBCR0_RST_SYSTEM 0x30000000	/* System Reset */
-#define DBCR0_RST_CHIP	0x20000000	/* Chip Reset */
-#define DBCR0_RST_CORE	0x10000000	/* Core Reset */
-#define DBCR0_RST_NONE	0x00000000	/* No Reset */
-#define DBCR0_ICMP	0x08000000	/* Instruction Completion */
-#define DBCR0_IC	DBCR0_ICMP
-#define DBCR0_BRT	0x04000000	/* Branch Taken */
-#define DBCR0_BT	DBCR0_BRT
-#define DBCR0_IRPT	0x02000000	/* Exception Debug Event */
-#define DBCR0_TDE	0x01000000	/* TRAP Debug Event */
-#define DBCR0_TIE	DBCR0_TDE
-#define DBCR0_IAC1	0x00800000	/* Instr Addr compare 1 enable */
-#define DBCR0_IAC2	0x00400000	/* Instr Addr compare 2 enable */
-#define DBCR0_IAC3	0x00200000	/* Instr Addr compare 3 enable */
-#define DBCR0_IAC4	0x00100000	/* Instr Addr compare 4 enable */
-#define DBCR0_DAC1R	0x00080000	/* DAC 1 Read enable */
-#define DBCR0_DAC1W	0x00040000	/* DAC 1 Write enable */
-#define DBCR0_DAC2R	0x00020000	/* DAC 2 Read enable */
-#define DBCR0_DAC2W	0x00010000	/* DAC 2 Write enable */
-#define DBCR0_RET	0x00008000	/* Return Debug Event */
-#define DBCR0_CIRPT	0x00000040	/* Critical Interrupt Taken Event */
-#define DBCR0_CRET	0x00000020	/* Critical Return Debug Event */
-#define DBCR0_FT	0x00000001	/* Freeze Timers on debug event */
-
-#define dbcr_dac(task)	((task)->thread.dbcr0)
-#define DBCR_DAC1R	DBCR0_DAC1R
-#define DBCR_DAC1W	DBCR0_DAC1W
-#define DBCR_DAC2R	DBCR0_DAC2R
-#define DBCR_DAC2W	DBCR0_DAC2W
-
-/* Bit definitions related to the DBCR1. */
-#define DBCR1_IAC1US	0xC0000000	/* Instr Addr Cmp 1 Sup/User   */
-#define DBCR1_IAC1ER	0x30000000	/* Instr Addr Cmp 1 Eff/Real */
-#define DBCR1_IAC1ER_01	0x10000000	/* reserved */
-#define DBCR1_IAC1ER_10	0x20000000	/* Instr Addr Cmp 1 Eff/Real MSR[IS]=0 */
-#define DBCR1_IAC1ER_11	0x30000000	/* Instr Addr Cmp 1 Eff/Real MSR[IS]=1 */
-#define DBCR1_IAC2US	0x0C000000	/* Instr Addr Cmp 2 Sup/User   */
-#define DBCR1_IAC2ER	0x03000000	/* Instr Addr Cmp 2 Eff/Real */
-#define DBCR1_IAC2ER_01	0x01000000	/* reserved */
-#define DBCR1_IAC2ER_10	0x02000000	/* Instr Addr Cmp 2 Eff/Real MSR[IS]=0 */
-#define DBCR1_IAC2ER_11	0x03000000	/* Instr Addr Cmp 2 Eff/Real MSR[IS]=1 */
-#define DBCR1_IAC12M	0x00800000	/* Instr Addr 1-2 range enable */
-#define DBCR1_IAC12MX	0x00C00000	/* Instr Addr 1-2 range eXclusive */
-#define DBCR1_IAC12AT	0x00010000	/* Instr Addr 1-2 range Toggle */
-#define DBCR1_IAC3US	0x0000C000	/* Instr Addr Cmp 3 Sup/User   */
-#define DBCR1_IAC3ER	0x00003000	/* Instr Addr Cmp 3 Eff/Real */
-#define DBCR1_IAC3ER_01	0x00001000	/* reserved */
-#define DBCR1_IAC3ER_10	0x00002000	/* Instr Addr Cmp 3 Eff/Real MSR[IS]=0 */
-#define DBCR1_IAC3ER_11	0x00003000	/* Instr Addr Cmp 3 Eff/Real MSR[IS]=1 */
-#define DBCR1_IAC4US	0x00000C00	/* Instr Addr Cmp 4 Sup/User   */
-#define DBCR1_IAC4ER	0x00000300	/* Instr Addr Cmp 4 Eff/Real */
-#define DBCR1_IAC4ER_01	0x00000100	/* Instr Addr Cmp 4 Eff/Real MSR[IS]=0 */
-#define DBCR1_IAC4ER_10	0x00000200	/* Instr Addr Cmp 4 Eff/Real MSR[IS]=0 */
-#define DBCR1_IAC4ER_11	0x00000300	/* Instr Addr Cmp 4 Eff/Real MSR[IS]=1 */
-#define DBCR1_IAC34M	0x00000080	/* Instr Addr 3-4 range enable */
-#define DBCR1_IAC34MX	0x000000C0	/* Instr Addr 3-4 range eXclusive */
-#define DBCR1_IAC34AT	0x00000001	/* Instr Addr 3-4 range Toggle */
-
-#define dbcr_iac_range(task)	((task)->thread.dbcr1)
-#define DBCR_IAC12I	DBCR1_IAC12M	/* Range Inclusive */
-#define DBCR_IAC12X	DBCR1_IAC12MX	/* Range Exclusive */
-#define DBCR_IAC12MODE	DBCR1_IAC12MX	/* IAC 1-2 Mode Bits */
-#define DBCR_IAC34I	DBCR1_IAC34M	/* Range Inclusive */
-#define DBCR_IAC34X	DBCR1_IAC34MX	/* Range Exclusive */
-#define DBCR_IAC34MODE	DBCR1_IAC34MX	/* IAC 3-4 Mode Bits */
-
-/* Bit definitions related to the DBCR2. */
-#define DBCR2_DAC1US	0xC0000000	/* Data Addr Cmp 1 Sup/User   */
-#define DBCR2_DAC1ER	0x30000000	/* Data Addr Cmp 1 Eff/Real */
-#define DBCR2_DAC2US	0x0C000000	/* Data Addr Cmp 2 Sup/User   */
-#define DBCR2_DAC2ER	0x03000000	/* Data Addr Cmp 2 Eff/Real */
-#define DBCR2_DAC12M	0x00800000	/* DAC 1-2 range enable */
-#define DBCR2_DAC12MM	0x00400000	/* DAC 1-2 Mask mode*/
-#define DBCR2_DAC12MX	0x00C00000	/* DAC 1-2 range eXclusive */
-#define DBCR2_DAC12MODE	0x00C00000	/* DAC 1-2 Mode Bits */
-#define DBCR2_DAC12A	0x00200000	/* DAC 1-2 Asynchronous */
-#define DBCR2_DVC1M	0x000C0000	/* Data Value Comp 1 Mode */
-#define DBCR2_DVC1M_SHIFT	18	/* # of bits to shift DBCR2_DVC1M */
-#define DBCR2_DVC2M	0x00030000	/* Data Value Comp 2 Mode */
-#define DBCR2_DVC2M_SHIFT	16	/* # of bits to shift DBCR2_DVC2M */
-#define DBCR2_DVC1BE	0x00000F00	/* Data Value Comp 1 Byte */
-#define DBCR2_DVC1BE_SHIFT	8	/* # of bits to shift DBCR2_DVC1BE */
-#define DBCR2_DVC2BE	0x0000000F	/* Data Value Comp 2 Byte */
-#define DBCR2_DVC2BE_SHIFT	0	/* # of bits to shift DBCR2_DVC2BE */
-
-/*
- * Are there any active Debug Events represented in the
- * Debug Control Registers?
- */
-#define DBCR0_ACTIVE_EVENTS  (DBCR0_ICMP | DBCR0_IAC1 | DBCR0_IAC2 | \
-			      DBCR0_IAC3 | DBCR0_IAC4 | DBCR0_DAC1R | \
-			      DBCR0_DAC1W  | DBCR0_DAC2R | DBCR0_DAC2W)
-#define DBCR1_ACTIVE_EVENTS	0
-
-#define DBCR_ACTIVE_EVENTS(dbcr0, dbcr1)  (((dbcr0) & DBCR0_ACTIVE_EVENTS) || \
-					   ((dbcr1) & DBCR1_ACTIVE_EVENTS))
-#endif /* #elif defined(CONFIG_BOOKE) */
-
-/* Bit definitions related to the TCR. */
-#define TCR_WP(x)	(((x)&0x3)<<30)	/* WDT Period */
-#define TCR_WP_MASK	TCR_WP(3)
-#define WP_2_17		0		/* 2^17 clocks */
-#define WP_2_21		1		/* 2^21 clocks */
-#define WP_2_25		2		/* 2^25 clocks */
-#define WP_2_29		3		/* 2^29 clocks */
-#define TCR_WRC(x)	(((x)&0x3)<<28)	/* WDT Reset Control */
-#define TCR_WRC_MASK	TCR_WRC(3)
-#define WRC_NONE	0		/* No reset will occur */
-#define WRC_CORE	1		/* Core reset will occur */
-#define WRC_CHIP	2		/* Chip reset will occur */
-#define WRC_SYSTEM	3		/* System reset will occur */
-#define TCR_WIE		0x08000000	/* WDT Interrupt Enable */
-#define TCR_PIE		0x04000000	/* PIT Interrupt Enable */
-#define TCR_DIE		TCR_PIE		/* DEC Interrupt Enable */
-#define TCR_FP(x)	(((x)&0x3)<<24)	/* FIT Period */
-#define TCR_FP_MASK	TCR_FP(3)
-#define FP_2_9		0		/* 2^9 clocks */
-#define FP_2_13		1		/* 2^13 clocks */
-#define FP_2_17		2		/* 2^17 clocks */
-#define FP_2_21		3		/* 2^21 clocks */
-#define TCR_FIE		0x00800000	/* FIT Interrupt Enable */
-#define TCR_ARE		0x00400000	/* Auto Reload Enable */
-
-/* Bit definitions for the TSR. */
-#define TSR_ENW		0x80000000	/* Enable Next Watchdog */
-#define TSR_WIS		0x40000000	/* WDT Interrupt Status */
-#define TSR_WRS(x)	(((x)&0x3)<<28)	/* WDT Reset Status */
-#define WRS_NONE	0		/* No WDT reset occurred */
-#define WRS_CORE	1		/* WDT forced core reset */
-#define WRS_CHIP	2		/* WDT forced chip reset */
-#define WRS_SYSTEM	3		/* WDT forced system reset */
-#define TSR_PIS		0x08000000	/* PIT Interrupt Status */
-#define TSR_DIS		TSR_PIS		/* DEC Interrupt Status */
-#define TSR_FIS		0x04000000	/* FIT Interrupt Status */
-
-/* Bit definitions for the DCCR. */
-#define DCCR_NOCACHE	0		/* Noncacheable */
-#define DCCR_CACHE	1		/* Cacheable */
-
-/* Bit definitions for DCWR. */
-#define DCWR_COPY	0		/* Copy-back */
-#define DCWR_WRITE	1		/* Write-through */
-
-/* Bit definitions for ICCR. */
-#define ICCR_NOCACHE	0		/* Noncacheable */
-#define ICCR_CACHE	1		/* Cacheable */
-
-/* Bit definitions for L1CSR0. */
-#define L1CSR0_CPE	0x00010000	/* Data Cache Parity Enable */
-#define L1CSR0_CLFC	0x00000100	/* Cache Lock Bits Flash Clear */
-#define L1CSR0_DCFI	0x00000002	/* Data Cache Flash Invalidate */
-#define L1CSR0_CFI	0x00000002	/* Cache Flash Invalidate */
-#define L1CSR0_DCE	0x00000001	/* Data Cache Enable */
-
-/* Bit definitions for L1CSR1. */
-#define L1CSR1_CPE	0x00010000	/* Instruction Cache Parity Enable */
-#define L1CSR1_ICLFR	0x00000100	/* Instr Cache Lock Bits Flash Reset */
-#define L1CSR1_ICFI	0x00000002	/* Instr Cache Flash Invalidate */
-#define L1CSR1_ICE	0x00000001	/* Instr Cache Enable */
-
-/* Bit definitions for L1CSR2. */
-#define L1CSR2_DCWS	0x40000000	/* Data Cache write shadow */
-
-/* Bit definitions for L2CSR0. */
-#define L2CSR0_L2E	0x80000000	/* L2 Cache Enable */
-#define L2CSR0_L2PE	0x40000000	/* L2 Cache Parity/ECC Enable */
-#define L2CSR0_L2WP	0x1c000000	/* L2 I/D Way Partioning */
-#define L2CSR0_L2CM	0x03000000	/* L2 Cache Coherency Mode */
-#define L2CSR0_L2FI	0x00200000	/* L2 Cache Flash Invalidate */
-#define L2CSR0_L2IO	0x00100000	/* L2 Cache Instruction Only */
-#define L2CSR0_L2DO	0x00010000	/* L2 Cache Data Only */
-#define L2CSR0_L2REP	0x00003000	/* L2 Line Replacement Algo */
-#define L2CSR0_L2FL	0x00000800	/* L2 Cache Flush */
-#define L2CSR0_L2LFC	0x00000400	/* L2 Cache Lock Flash Clear */
-#define L2CSR0_L2LOA	0x00000080	/* L2 Cache Lock Overflow Allocate */
-#define L2CSR0_L2LO	0x00000020	/* L2 Cache Lock Overflow */
-
-/* Bit definitions for SGR. */
-#define SGR_NORMAL	0		/* Speculative fetching allowed. */
-#define SGR_GUARDED	1		/* Speculative fetching disallowed. */
-
-/* Bit definitions for EPCR */
-#define SPRN_EPCR_EXTGS		0x80000000	/* External Input interrupt
-						 * directed to Guest state */
-#define SPRN_EPCR_DTLBGS	0x40000000	/* Data TLB Error interrupt
-						 * directed to guest state */
-#define SPRN_EPCR_ITLBGS	0x20000000	/* Instr. TLB error interrupt
-						 * directed to guest state */
-#define SPRN_EPCR_DSIGS		0x10000000	/* Data Storage interrupt
-						 * directed to guest state */
-#define SPRN_EPCR_ISIGS		0x08000000	/* Instr. Storage interrupt
-						 * directed to guest state */
-#define SPRN_EPCR_DUVD		0x04000000	/* Disable Hypervisor Debug */
-#define SPRN_EPCR_ICM		0x02000000	/* Interrupt computation mode
-						 * (copied to MSR:CM on intr) */
-#define SPRN_EPCR_GICM		0x01000000	/* Guest Interrupt Comp. mode */
-#define SPRN_EPCR_DGTMI		0x00800000	/* Disable TLB Guest Management
-						 * instructions */
-#define SPRN_EPCR_DMIUH		0x00400000	/* Disable MAS Interrupt updates
-						 * for hypervisor */
-
-
-/*
- * The IBM-403 is an even more odd special case, as it is much
- * older than the IBM-405 series.  We put these down here incase someone
- * wishes to support these machines again.
- */
-#ifdef CONFIG_403GCX
-/* Special Purpose Registers (SPRNs)*/
-#define SPRN_TBHU	0x3CC	/* Time Base High User-mode */
-#define SPRN_TBLU	0x3CD	/* Time Base Low User-mode */
-#define SPRN_CDBCR	0x3D7	/* Cache Debug Control Register */
-#define SPRN_TBHI	0x3DC	/* Time Base High */
-#define SPRN_TBLO	0x3DD	/* Time Base Low */
-#define SPRN_DBCR	0x3F2	/* Debug Control Regsiter */
-#define SPRN_PBL1	0x3FC	/* Protection Bound Lower 1 */
-#define SPRN_PBL2	0x3FE	/* Protection Bound Lower 2 */
-#define SPRN_PBU1	0x3FD	/* Protection Bound Upper 1 */
-#define SPRN_PBU2	0x3FF	/* Protection Bound Upper 2 */
-
-
-/* Bit definitions for the DBCR. */
-#define DBCR_EDM	DBCR0_EDM
-#define DBCR_IDM	DBCR0_IDM
-#define DBCR_RST(x)	(((x) & 0x3) << 28)
-#define DBCR_RST_NONE	0
-#define DBCR_RST_CORE	1
-#define DBCR_RST_CHIP	2
-#define DBCR_RST_SYSTEM	3
-#define DBCR_IC		DBCR0_IC	/* Instruction Completion Debug Evnt */
-#define DBCR_BT		DBCR0_BT	/* Branch Taken Debug Event */
-#define DBCR_EDE	DBCR0_EDE	/* Exception Debug Event */
-#define DBCR_TDE	DBCR0_TDE	/* TRAP Debug Event */
-#define DBCR_FER	0x00F80000	/* First Events Remaining Mask */
-#define DBCR_FT		0x00040000	/* Freeze Timers on Debug Event */
-#define DBCR_IA1	0x00020000	/* Instr. Addr. Compare 1 Enable */
-#define DBCR_IA2	0x00010000	/* Instr. Addr. Compare 2 Enable */
-#define DBCR_D1R	0x00008000	/* Data Addr. Compare 1 Read Enable */
-#define DBCR_D1W	0x00004000	/* Data Addr. Compare 1 Write Enable */
-#define DBCR_D1S(x)	(((x) & 0x3) << 12)	/* Data Adrr. Compare 1 Size */
-#define DAC_BYTE	0
-#define DAC_HALF	1
-#define DAC_WORD	2
-#define DAC_QUAD	3
-#define DBCR_D2R	0x00000800	/* Data Addr. Compare 2 Read Enable */
-#define DBCR_D2W	0x00000400	/* Data Addr. Compare 2 Write Enable */
-#define DBCR_D2S(x)	(((x) & 0x3) << 8)	/* Data Addr. Compare 2 Size */
-#define DBCR_SBT	0x00000040	/* Second Branch Taken Debug Event */
-#define DBCR_SED	0x00000020	/* Second Exception Debug Event */
-#define DBCR_STD	0x00000010	/* Second Trap Debug Event */
-#define DBCR_SIA	0x00000008	/* Second IAC Enable */
-#define DBCR_SDA	0x00000004	/* Second DAC Enable */
-#define DBCR_JOI	0x00000002	/* JTAG Serial Outbound Int. Enable */
-#define DBCR_JII	0x00000001	/* JTAG Serial Inbound Int. Enable */
-#endif /* 403GCX */
-
-/* Some 476 specific registers */
-#define SPRN_SSPCR		830
-#define SPRN_USPCR		831
-#define SPRN_ISPCR		829
-#define SPRN_MMUBE0		820
-#define MMUBE0_IBE0_SHIFT	24
-#define MMUBE0_IBE1_SHIFT	16
-#define MMUBE0_IBE2_SHIFT	8
-#define MMUBE0_VBE0		0x00000004
-#define MMUBE0_VBE1		0x00000002
-#define MMUBE0_VBE2		0x00000001
-#define SPRN_MMUBE1		821
-#define MMUBE1_IBE3_SHIFT	24
-#define MMUBE1_IBE4_SHIFT	16
-#define MMUBE1_IBE5_SHIFT	8
-#define MMUBE1_VBE3		0x00000004
-#define MMUBE1_VBE4		0x00000002
-#define MMUBE1_VBE5		0x00000001
-
-#endif /* __ASM_POWERPC_REG_BOOKE_H__ */
-#endif /* __KERNEL__ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/reg_fsl_emb.h b/ANDROID_3.4.5/arch/powerpc/include/asm/reg_fsl_emb.h
deleted file mode 100644
index 77bb71cf..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/reg_fsl_emb.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * Contains register definitions for the Freescale Embedded Performance
- * Monitor.
- */
-#ifdef __KERNEL__
-#ifndef __ASM_POWERPC_REG_FSL_EMB_H__
-#define __ASM_POWERPC_REG_FSL_EMB_H__
-
-#ifndef __ASSEMBLY__
-/* Performance Monitor Registers */
-#define mfpmr(rn)	({unsigned int rval; \
-			asm volatile("mfpmr %0," __stringify(rn) \
-				     : "=r" (rval)); rval;})
-#define mtpmr(rn, v)	asm volatile("mtpmr " __stringify(rn) ",%0" : : "r" (v))
-#endif /* __ASSEMBLY__ */
-
-/* Freescale Book E Performance Monitor APU Registers */
-#define PMRN_PMC0	0x010	/* Performance Monitor Counter 0 */
-#define PMRN_PMC1	0x011	/* Performance Monitor Counter 1 */
-#define PMRN_PMC2	0x012	/* Performance Monitor Counter 1 */
-#define PMRN_PMC3	0x013	/* Performance Monitor Counter 1 */
-#define PMRN_PMLCA0	0x090	/* PM Local Control A0 */
-#define PMRN_PMLCA1	0x091	/* PM Local Control A1 */
-#define PMRN_PMLCA2	0x092	/* PM Local Control A2 */
-#define PMRN_PMLCA3	0x093	/* PM Local Control A3 */
-
-#define PMLCA_FC	0x80000000	/* Freeze Counter */
-#define PMLCA_FCS	0x40000000	/* Freeze in Supervisor */
-#define PMLCA_FCU	0x20000000	/* Freeze in User */
-#define PMLCA_FCM1	0x10000000	/* Freeze when PMM==1 */
-#define PMLCA_FCM0	0x08000000	/* Freeze when PMM==0 */
-#define PMLCA_CE	0x04000000	/* Condition Enable */
-
-#define PMLCA_EVENT_MASK 0x00ff0000	/* Event field */
-#define PMLCA_EVENT_SHIFT	16
-
-#define PMRN_PMLCB0	0x110	/* PM Local Control B0 */
-#define PMRN_PMLCB1	0x111	/* PM Local Control B1 */
-#define PMRN_PMLCB2	0x112	/* PM Local Control B2 */
-#define PMRN_PMLCB3	0x113	/* PM Local Control B3 */
-
-#define PMLCB_THRESHMUL_MASK	0x0700	/* Threshold Multiple Field */
-#define PMLCB_THRESHMUL_SHIFT	8
-
-#define PMLCB_THRESHOLD_MASK	0x003f	/* Threshold Field */
-#define PMLCB_THRESHOLD_SHIFT	0
-
-#define PMRN_PMGC0	0x190	/* PM Global Control 0 */
-
-#define PMGC0_FAC	0x80000000	/* Freeze all Counters */
-#define PMGC0_PMIE	0x40000000	/* Interrupt Enable */
-#define PMGC0_FCECE	0x20000000	/* Freeze countes on
-					   Enabled Condition or
-					   Event */
-
-#define PMRN_UPMC0	0x000	/* User Performance Monitor Counter 0 */
-#define PMRN_UPMC1	0x001	/* User Performance Monitor Counter 1 */
-#define PMRN_UPMC2	0x002	/* User Performance Monitor Counter 1 */
-#define PMRN_UPMC3	0x003	/* User Performance Monitor Counter 1 */
-#define PMRN_UPMLCA0	0x080	/* User PM Local Control A0 */
-#define PMRN_UPMLCA1	0x081	/* User PM Local Control A1 */
-#define PMRN_UPMLCA2	0x082	/* User PM Local Control A2 */
-#define PMRN_UPMLCA3	0x083	/* User PM Local Control A3 */
-#define PMRN_UPMLCB0	0x100	/* User PM Local Control B0 */
-#define PMRN_UPMLCB1	0x101	/* User PM Local Control B1 */
-#define PMRN_UPMLCB2	0x102	/* User PM Local Control B2 */
-#define PMRN_UPMLCB3	0x103	/* User PM Local Control B3 */
-#define PMRN_UPMGC0	0x180	/* User PM Global Control 0 */
-
-
-#endif /* __ASM_POWERPC_REG_FSL_EMB_H__ */
-#endif /* __KERNEL__ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/resource.h b/ANDROID_3.4.5/arch/powerpc/include/asm/resource.h
deleted file mode 100644
index 04bc4db8..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/resource.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/resource.h>
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/rheap.h b/ANDROID_3.4.5/arch/powerpc/include/asm/rheap.h
deleted file mode 100644
index 17238176..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/rheap.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * include/asm-ppc/rheap.h
- *
- * Header file for the implementation of a remote heap.
- *
- * Author: Pantelis Antoniou <panto@intracom.gr>
- *
- * 2004 (c) INTRACOM S.A. Greece. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifndef __ASM_PPC_RHEAP_H__
-#define __ASM_PPC_RHEAP_H__
-
-#include <linux/list.h>
-
-typedef struct _rh_block {
-	struct list_head list;
-	unsigned long start;
-	int size;
-	const char *owner;
-} rh_block_t;
-
-typedef struct _rh_info {
-	unsigned int alignment;
-	int max_blocks;
-	int empty_slots;
-	rh_block_t *block;
-	struct list_head empty_list;
-	struct list_head free_list;
-	struct list_head taken_list;
-	unsigned int flags;
-} rh_info_t;
-
-#define RHIF_STATIC_INFO	0x1
-#define RHIF_STATIC_BLOCK	0x2
-
-typedef struct _rh_stats {
-	unsigned long start;
-	int size;
-	const char *owner;
-} rh_stats_t;
-
-#define RHGS_FREE	0
-#define RHGS_TAKEN	1
-
-/* Create a remote heap dynamically */
-extern rh_info_t *rh_create(unsigned int alignment);
-
-/* Destroy a remote heap, created by rh_create() */
-extern void rh_destroy(rh_info_t * info);
-
-/* Initialize in place a remote info block */
-extern void rh_init(rh_info_t * info, unsigned int alignment, int max_blocks,
-		    rh_block_t * block);
-
-/* Attach a free region to manage */
-extern int rh_attach_region(rh_info_t * info, unsigned long start, int size);
-
-/* Detach a free region */
-extern unsigned long rh_detach_region(rh_info_t * info, unsigned long start, int size);
-
-/* Allocate the given size from the remote heap (with alignment) */
-extern unsigned long rh_alloc_align(rh_info_t * info, int size, int alignment,
-		const char *owner);
-
-/* Allocate the given size from the remote heap */
-extern unsigned long rh_alloc(rh_info_t * info, int size, const char *owner);
-
-/* Allocate the given size from the given address */
-extern unsigned long rh_alloc_fixed(rh_info_t * info, unsigned long start, int size,
-			    const char *owner);
-
-/* Free the allocated area */
-extern int rh_free(rh_info_t * info, unsigned long start);
-
-/* Get stats for debugging purposes */
-extern int rh_get_stats(rh_info_t * info, int what, int max_stats,
-			rh_stats_t * stats);
-
-/* Simple dump of remote heap info */
-extern void rh_dump(rh_info_t * info);
-
-/* Set owner of taken block */
-extern int rh_set_owner(rh_info_t * info, unsigned long start, const char *owner);
-
-#endif				/* __ASM_PPC_RHEAP_H__ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/rio.h b/ANDROID_3.4.5/arch/powerpc/include/asm/rio.h
deleted file mode 100644
index b1d2dece..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/rio.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * RapidIO architecture support
- *
- * Copyright 2005 MontaVista Software, Inc.
- * Matt Porter <mporter@kernel.crashing.org>
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-#ifndef ASM_PPC_RIO_H
-#define ASM_PPC_RIO_H
-
-extern void platform_rio_init(void);
-#ifdef CONFIG_FSL_RIO
-extern int fsl_rio_mcheck_exception(struct pt_regs *);
-#else
-static inline int fsl_rio_mcheck_exception(struct pt_regs *regs) {return 0; }
-#endif
-
-#endif				/* ASM_PPC_RIO_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/rtas.h b/ANDROID_3.4.5/arch/powerpc/include/asm/rtas.h
deleted file mode 100644
index 557cff84..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/rtas.h
+++ /dev/null
@@ -1,363 +0,0 @@
-#ifndef _POWERPC_RTAS_H
-#define _POWERPC_RTAS_H
-#ifdef __KERNEL__
-
-#include <linux/spinlock.h>
-#include <asm/page.h>
-
-/*
- * Definitions for talking to the RTAS on CHRP machines.
- *
- * Copyright (C) 2001 Peter Bergner
- * Copyright (C) 2001 PPC 64 Team, IBM Corp
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#define RTAS_UNKNOWN_SERVICE (-1)
-#define RTAS_INSTANTIATE_MAX (1ULL<<30) /* Don't instantiate rtas at/above this value */
-
-/* Buffer size for ppc_rtas system call. */
-#define RTAS_RMOBUF_MAX (64 * 1024)
-
-/* RTAS return status codes */
-#define RTAS_NOT_SUSPENDABLE	-9004
-#define RTAS_BUSY		-2    /* RTAS Busy */
-#define RTAS_EXTENDED_DELAY_MIN	9900
-#define RTAS_EXTENDED_DELAY_MAX	9905
-
-/*
- * In general to call RTAS use rtas_token("string") to lookup
- * an RTAS token for the given string (e.g. "event-scan").
- * To actually perform the call use
- *    ret = rtas_call(token, n_in, n_out, ...)
- * Where n_in is the number of input parameters and
- *       n_out is the number of output parameters
- *
- * If the "string" is invalid on this system, RTAS_UNKNOWN_SERVICE
- * will be returned as a token.  rtas_call() does look for this
- * token and error out gracefully so rtas_call(rtas_token("str"), ...)
- * may be safely used for one-shot calls to RTAS.
- *
- */
-
-typedef u32 rtas_arg_t;
-
-struct rtas_args {
-	u32 token;
-	u32 nargs;
-	u32 nret; 
-	rtas_arg_t args[16];
-	rtas_arg_t *rets;     /* Pointer to return values in args[]. */
-};  
-
-struct rtas_t {
-	unsigned long entry;		/* physical address pointer */
-	unsigned long base;		/* physical address pointer */
-	unsigned long size;
-	arch_spinlock_t lock;
-	struct rtas_args args;
-	struct device_node *dev;	/* virtual address pointer */
-};
-
-struct rtas_suspend_me_data {
-	atomic_t working; /* number of cpus accessing this struct */
-	atomic_t done;
-	int token; /* ibm,suspend-me */
-	atomic_t error;
-	struct completion *complete; /* wait on this until working == 0 */
-};
-
-/* RTAS event classes */
-#define RTAS_INTERNAL_ERROR		0x80000000 /* set bit 0 */
-#define RTAS_EPOW_WARNING		0x40000000 /* set bit 1 */
-#define RTAS_HOTPLUG_EVENTS		0x10000000 /* set bit 3 */
-#define RTAS_IO_EVENTS			0x08000000 /* set bit 4 */
-#define RTAS_EVENT_SCAN_ALL_EVENTS	0xffffffff
-
-/* RTAS event severity */
-#define RTAS_SEVERITY_FATAL		0x5
-#define RTAS_SEVERITY_ERROR		0x4
-#define RTAS_SEVERITY_ERROR_SYNC	0x3
-#define RTAS_SEVERITY_WARNING		0x2
-#define RTAS_SEVERITY_EVENT		0x1
-#define RTAS_SEVERITY_NO_ERROR		0x0
-
-/* RTAS event disposition */
-#define RTAS_DISP_FULLY_RECOVERED	0x0
-#define RTAS_DISP_LIMITED_RECOVERY	0x1
-#define RTAS_DISP_NOT_RECOVERED		0x2
-
-/* RTAS event initiator */
-#define RTAS_INITIATOR_UNKNOWN		0x0
-#define RTAS_INITIATOR_CPU		0x1
-#define RTAS_INITIATOR_PCI		0x2
-#define RTAS_INITIATOR_ISA		0x3
-#define RTAS_INITIATOR_MEMORY		0x4
-#define RTAS_INITIATOR_POWERMGM		0x5
-
-/* RTAS event target */
-#define RTAS_TARGET_UNKNOWN		0x0
-#define RTAS_TARGET_CPU			0x1
-#define RTAS_TARGET_PCI			0x2
-#define RTAS_TARGET_ISA			0x3
-#define RTAS_TARGET_MEMORY		0x4
-#define RTAS_TARGET_POWERMGM		0x5
-
-/* RTAS event type */
-#define RTAS_TYPE_RETRY			0x01
-#define RTAS_TYPE_TCE_ERR		0x02
-#define RTAS_TYPE_INTERN_DEV_FAIL	0x03
-#define RTAS_TYPE_TIMEOUT		0x04
-#define RTAS_TYPE_DATA_PARITY		0x05
-#define RTAS_TYPE_ADDR_PARITY		0x06
-#define RTAS_TYPE_CACHE_PARITY		0x07
-#define RTAS_TYPE_ADDR_INVALID		0x08
-#define RTAS_TYPE_ECC_UNCORR		0x09
-#define RTAS_TYPE_ECC_CORR		0x0a
-#define RTAS_TYPE_EPOW			0x40
-#define RTAS_TYPE_PLATFORM		0xE0
-#define RTAS_TYPE_IO			0xE1
-#define RTAS_TYPE_INFO			0xE2
-#define RTAS_TYPE_DEALLOC		0xE3
-#define RTAS_TYPE_DUMP			0xE4
-/* I don't add PowerMGM events right now, this is a different topic */ 
-#define RTAS_TYPE_PMGM_POWER_SW_ON	0x60
-#define RTAS_TYPE_PMGM_POWER_SW_OFF	0x61
-#define RTAS_TYPE_PMGM_LID_OPEN		0x62
-#define RTAS_TYPE_PMGM_LID_CLOSE	0x63
-#define RTAS_TYPE_PMGM_SLEEP_BTN	0x64
-#define RTAS_TYPE_PMGM_WAKE_BTN		0x65
-#define RTAS_TYPE_PMGM_BATTERY_WARN	0x66
-#define RTAS_TYPE_PMGM_BATTERY_CRIT	0x67
-#define RTAS_TYPE_PMGM_SWITCH_TO_BAT	0x68
-#define RTAS_TYPE_PMGM_SWITCH_TO_AC	0x69
-#define RTAS_TYPE_PMGM_KBD_OR_MOUSE	0x6a
-#define RTAS_TYPE_PMGM_ENCLOS_OPEN	0x6b
-#define RTAS_TYPE_PMGM_ENCLOS_CLOSED	0x6c
-#define RTAS_TYPE_PMGM_RING_INDICATE	0x6d
-#define RTAS_TYPE_PMGM_LAN_ATTENTION	0x6e
-#define RTAS_TYPE_PMGM_TIME_ALARM	0x6f
-#define RTAS_TYPE_PMGM_CONFIG_CHANGE	0x70
-#define RTAS_TYPE_PMGM_SERVICE_PROC	0x71
-
-/* RTAS check-exception vector offset */
-#define RTAS_VECTOR_EXTERNAL_INTERRUPT	0x500
-
-struct rtas_error_log {
-	unsigned long version:8;		/* Architectural version */
-	unsigned long severity:3;		/* Severity level of error */
-	unsigned long disposition:2;		/* Degree of recovery */
-	unsigned long extended:1;		/* extended log present? */
-	unsigned long /* reserved */ :2;	/* Reserved for future use */
-	unsigned long initiator:4;		/* Initiator of event */
-	unsigned long target:4;			/* Target of failed operation */
-	unsigned long type:8;			/* General event or error*/
-	unsigned long extended_log_length:32;	/* length in bytes */
-	unsigned char buffer[1];		/* Start of extended log */
-						/* Variable length.      */
-};
-
-#define RTAS_V6EXT_LOG_FORMAT_EVENT_LOG	14
-
-#define RTAS_V6EXT_COMPANY_ID_IBM	(('I' << 24) | ('B' << 16) | ('M' << 8))
-
-/* RTAS general extended event log, Version 6. The extended log starts
- * from "buffer" field of struct rtas_error_log defined above.
- */
-struct rtas_ext_event_log_v6 {
-	/* Byte 0 */
-	uint32_t log_valid:1;		/* 1:Log valid */
-	uint32_t unrecoverable_error:1;	/* 1:Unrecoverable error */
-	uint32_t recoverable_error:1;	/* 1:recoverable (correctable	*/
-					/*   or successfully retried)	*/
-	uint32_t degraded_operation:1;	/* 1:Unrecoverable err, bypassed*/
-					/*   - degraded operation (e.g.	*/
-					/*   CPU or mem taken off-line)	*/
-	uint32_t predictive_error:1;
-	uint32_t new_log:1;		/* 1:"New" log (Always 1 for	*/
-					/*   data returned from RTAS	*/
-	uint32_t big_endian:1;		/* 1: Big endian */
-	uint32_t :1;			/* reserved */
-	/* Byte 1 */
-	uint32_t :8;			/* reserved */
-	/* Byte 2 */
-	uint32_t powerpc_format:1;	/* Set to 1 (indicating log is	*/
-					/* in PowerPC format		*/
-	uint32_t :3;			/* reserved */
-	uint32_t log_format:4;		/* Log format indicator. Define	*/
-					/* format used for byte 12-2047	*/
-	/* Byte 3 */
-	uint32_t :8;			/* reserved */
-	/* Byte 4-11 */
-	uint8_t reserved[8];		/* reserved */
-	/* Byte 12-15 */
-	uint32_t company_id;		/* Company ID of the company	*/
-					/* that defines the format for	*/
-					/* the vendor specific log type	*/
-	/* Byte 16-end of log */
-	uint8_t vendor_log[1];		/* Start of vendor specific log	*/
-					/* Variable length.		*/
-};
-
-/* pSeries event log format */
-
-/* Two bytes ASCII section IDs */
-#define PSERIES_ELOG_SECT_ID_PRIV_HDR		(('P' << 8) | 'H')
-#define PSERIES_ELOG_SECT_ID_USER_HDR		(('U' << 8) | 'H')
-#define PSERIES_ELOG_SECT_ID_PRIMARY_SRC	(('P' << 8) | 'S')
-#define PSERIES_ELOG_SECT_ID_EXTENDED_UH	(('E' << 8) | 'H')
-#define PSERIES_ELOG_SECT_ID_FAILING_MTMS	(('M' << 8) | 'T')
-#define PSERIES_ELOG_SECT_ID_SECONDARY_SRC	(('S' << 8) | 'S')
-#define PSERIES_ELOG_SECT_ID_DUMP_LOCATOR	(('D' << 8) | 'H')
-#define PSERIES_ELOG_SECT_ID_FW_ERROR		(('S' << 8) | 'W')
-#define PSERIES_ELOG_SECT_ID_IMPACT_PART_ID	(('L' << 8) | 'P')
-#define PSERIES_ELOG_SECT_ID_LOGIC_RESOURCE_ID	(('L' << 8) | 'R')
-#define PSERIES_ELOG_SECT_ID_HMC_ID		(('H' << 8) | 'M')
-#define PSERIES_ELOG_SECT_ID_EPOW		(('E' << 8) | 'P')
-#define PSERIES_ELOG_SECT_ID_IO_EVENT		(('I' << 8) | 'E')
-#define PSERIES_ELOG_SECT_ID_MANUFACT_INFO	(('M' << 8) | 'I')
-#define PSERIES_ELOG_SECT_ID_CALL_HOME		(('C' << 8) | 'H')
-#define PSERIES_ELOG_SECT_ID_USER_DEF		(('U' << 8) | 'D')
-
-/* Vendor specific Platform Event Log Format, Version 6, section header */
-struct pseries_errorlog {
-	uint16_t id;			/* 0x00 2-byte ASCII section ID	*/
-	uint16_t length;		/* 0x02 Section length in bytes	*/
-	uint8_t version;		/* 0x04 Section version		*/
-	uint8_t subtype;		/* 0x05 Section subtype		*/
-	uint16_t creator_component;	/* 0x06 Creator component ID	*/
-	uint8_t data[];			/* 0x08 Start of section data	*/
-};
-
-struct pseries_errorlog *get_pseries_errorlog(struct rtas_error_log *log,
-					      uint16_t section_id);
-
-/*
- * This can be set by the rtas_flash module so that it can get called
- * as the absolutely last thing before the kernel terminates.
- */
-extern void (*rtas_flash_term_hook)(int);
-
-extern struct rtas_t rtas;
-
-extern void enter_rtas(unsigned long);
-extern int rtas_token(const char *service);
-extern int rtas_service_present(const char *service);
-extern int rtas_call(int token, int, int, int *, ...);
-extern void rtas_restart(char *cmd);
-extern void rtas_power_off(void);
-extern void rtas_halt(void);
-extern void rtas_os_term(char *str);
-extern int rtas_get_sensor(int sensor, int index, int *state);
-extern int rtas_get_power_level(int powerdomain, int *level);
-extern int rtas_set_power_level(int powerdomain, int level, int *setlevel);
-extern bool rtas_indicator_present(int token, int *maxindex);
-extern int rtas_set_indicator(int indicator, int index, int new_value);
-extern int rtas_set_indicator_fast(int indicator, int index, int new_value);
-extern void rtas_progress(char *s, unsigned short hex);
-extern void rtas_initialize(void);
-extern int rtas_suspend_cpu(struct rtas_suspend_me_data *data);
-extern int rtas_suspend_last_cpu(struct rtas_suspend_me_data *data);
-extern int rtas_ibm_suspend_me(struct rtas_args *);
-
-struct rtc_time;
-extern unsigned long rtas_get_boot_time(void);
-extern void rtas_get_rtc_time(struct rtc_time *rtc_time);
-extern int rtas_set_rtc_time(struct rtc_time *rtc_time);
-
-extern unsigned int rtas_busy_delay_time(int status);
-extern unsigned int rtas_busy_delay(int status);
-
-extern int early_init_dt_scan_rtas(unsigned long node,
-		const char *uname, int depth, void *data);
-
-extern void pSeries_log_error(char *buf, unsigned int err_type, int fatal);
-
-#ifdef CONFIG_PPC_RTAS_DAEMON
-extern void rtas_cancel_event_scan(void);
-#else
-static inline void rtas_cancel_event_scan(void) { }
-#endif
-
-/* Error types logged.  */
-#define ERR_FLAG_ALREADY_LOGGED	0x0
-#define ERR_FLAG_BOOT		0x1 	/* log was pulled from NVRAM on boot */
-#define ERR_TYPE_RTAS_LOG	0x2	/* from rtas event-scan */
-#define ERR_TYPE_KERNEL_PANIC	0x4	/* from die()/panic() */
-#define ERR_TYPE_KERNEL_PANIC_GZ 0x8	/* ditto, compressed */
-
-/* All the types and not flags */
-#define ERR_TYPE_MASK \
-	(ERR_TYPE_RTAS_LOG | ERR_TYPE_KERNEL_PANIC | ERR_TYPE_KERNEL_PANIC_GZ)
-
-#define RTAS_DEBUG KERN_DEBUG "RTAS: "
- 
-#define RTAS_ERROR_LOG_MAX 2048
-
-/*
- * Return the firmware-specified size of the error log buffer
- *  for all rtas calls that require an error buffer argument.
- *  This includes 'check-exception' and 'rtas-last-error'.
- */
-extern int rtas_get_error_log_max(void);
-
-/* Event Scan Parameters */
-#define EVENT_SCAN_ALL_EVENTS	0xf0000000
-#define SURVEILLANCE_TOKEN	9000
-#define LOG_NUMBER		64		/* must be a power of two */
-#define LOG_NUMBER_MASK		(LOG_NUMBER-1)
-
-/* Some RTAS ops require a data buffer and that buffer must be < 4G.
- * Rather than having a memory allocator, just use this buffer
- * (get the lock first), make the RTAS call.  Copy the data instead
- * of holding the buffer for long.
- */
-
-#define RTAS_DATA_BUF_SIZE 4096
-extern spinlock_t rtas_data_buf_lock;
-extern char rtas_data_buf[RTAS_DATA_BUF_SIZE];
-
-/* RMO buffer reserved for user-space RTAS use */
-extern unsigned long rtas_rmo_buf;
-
-#define GLOBAL_INTERRUPT_QUEUE 9005
-
-/**
- * rtas_config_addr - Format a busno, devfn and reg for RTAS.
- * @busno: The bus number.
- * @devfn: The device and function number as encoded by PCI_DEVFN().
- * @reg: The register number.
- *
- * This function encodes the given busno, devfn and register number as
- * required for RTAS calls that take a "config_addr" parameter.
- * See PAPR requirement 7.3.4-1 for more info.
- */
-static inline u32 rtas_config_addr(int busno, int devfn, int reg)
-{
-	return ((reg & 0xf00) << 20) | ((busno & 0xff) << 16) |
-			(devfn << 8) | (reg & 0xff);
-}
-
-extern void __cpuinit rtas_give_timebase(void);
-extern void __cpuinit rtas_take_timebase(void);
-
-#ifdef CONFIG_PPC_RTAS
-static inline int page_is_rtas_user_buf(unsigned long pfn)
-{
-	unsigned long paddr = (pfn << PAGE_SHIFT);
-	if (paddr >= rtas_rmo_buf && paddr < (rtas_rmo_buf + RTAS_RMOBUF_MAX))
-		return 1;
-	return 0;
-}
-#else
-static inline int page_is_rtas_user_buf(unsigned long pfn) { return 0;}
-#endif
-
-extern int call_rtas(const char *, int, int, unsigned long *, ...);
-
-#endif /* __KERNEL__ */
-#endif /* _POWERPC_RTAS_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/rtc.h b/ANDROID_3.4.5/arch/powerpc/include/asm/rtc.h
deleted file mode 100644
index f5802926..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/rtc.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Real-time clock definitions and interfaces
- *
- * Author: Tom Rini <trini@mvista.com>
- *
- * 2002 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- *
- * Based on:
- * include/asm-m68k/rtc.h
- *
- * Copyright Richard Zidlicky
- * implementation details for genrtc/q40rtc driver
- *
- * And the old drivers/macintosh/rtc.c which was heavily based on:
- * Linux/SPARC Real Time Clock Driver
- * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
- *
- * With additional work by Paul Mackerras and Franz Sirl.
- */
-
-#ifndef __ASM_POWERPC_RTC_H__
-#define __ASM_POWERPC_RTC_H__
-
-#ifdef __KERNEL__
-
-#include <linux/rtc.h>
-
-#include <asm/machdep.h>
-#include <asm/time.h>
-
-#define RTC_PIE 0x40		/* periodic interrupt enable */
-#define RTC_AIE 0x20		/* alarm interrupt enable */
-#define RTC_UIE 0x10		/* update-finished interrupt enable */
-
-/* some dummy definitions */
-#define RTC_BATT_BAD 0x100	/* battery bad */
-#define RTC_SQWE 0x08		/* enable square-wave output */
-#define RTC_DM_BINARY 0x04	/* all time/date values are BCD if clear */
-#define RTC_24H 0x02		/* 24 hour mode - else hours bit 7 means pm */
-#define RTC_DST_EN 0x01	        /* auto switch DST - works f. USA only */
-
-static inline unsigned int get_rtc_time(struct rtc_time *time)
-{
-	if (ppc_md.get_rtc_time)
-		ppc_md.get_rtc_time(time);
-	return RTC_24H;
-}
-
-/* Set the current date and time in the real time clock. */
-static inline int set_rtc_time(struct rtc_time *time)
-{
-	if (ppc_md.set_rtc_time)
-		return ppc_md.set_rtc_time(time);
-	return -EINVAL;
-}
-
-static inline unsigned int get_rtc_ss(void)
-{
-	struct rtc_time h;
-
-	get_rtc_time(&h);
-	return h.tm_sec;
-}
-
-static inline int get_rtc_pll(struct rtc_pll_info *pll)
-{
-	return -EINVAL;
-}
-static inline int set_rtc_pll(struct rtc_pll_info *pll)
-{
-	return -EINVAL;
-}
-
-#endif /* __KERNEL__ */
-#endif /* __ASM_POWERPC_RTC_H__ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/runlatch.h b/ANDROID_3.4.5/arch/powerpc/include/asm/runlatch.h
deleted file mode 100644
index 54e9b963..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/runlatch.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
- */
-#ifndef _ASM_POWERPC_RUNLATCH_H
-#define _ASM_POWERPC_RUNLATCH_H
-
-#ifdef CONFIG_PPC64
-
-extern void __ppc64_runlatch_on(void);
-extern void __ppc64_runlatch_off(void);
-
-/*
- * We manually hard enable-disable, this is called
- * in the idle loop and we don't want to mess up
- * with soft-disable/enable & interrupt replay.
- */
-#define ppc64_runlatch_off()					\
-	do {							\
-		if (cpu_has_feature(CPU_FTR_CTRL) &&		\
-		    test_thread_local_flags(_TLF_RUNLATCH)) {	\
-			unsigned long msr = mfmsr();		\
-			__hard_irq_disable();			\
-			__ppc64_runlatch_off();			\
-			if (msr & MSR_EE)			\
-				__hard_irq_enable();		\
-		}      						\
-	} while (0)
-
-#define ppc64_runlatch_on()					\
-	do {							\
-		if (cpu_has_feature(CPU_FTR_CTRL) &&		\
-		    !test_thread_local_flags(_TLF_RUNLATCH)) {	\
-			unsigned long msr = mfmsr();		\
-			__hard_irq_disable();			\
-			__ppc64_runlatch_on();			\
-			if (msr & MSR_EE)			\
-				__hard_irq_enable();		\
-		}      						\
-	} while (0)
-#else
-#define ppc64_runlatch_on()
-#define ppc64_runlatch_off()
-#endif /* CONFIG_PPC64 */
-
-#endif /* _ASM_POWERPC_RUNLATCH_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/scatterlist.h b/ANDROID_3.4.5/arch/powerpc/include/asm/scatterlist.h
deleted file mode 100644
index de1f620b..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/scatterlist.h
+++ /dev/null
@@ -1,17 +0,0 @@
-#ifndef _ASM_POWERPC_SCATTERLIST_H
-#define _ASM_POWERPC_SCATTERLIST_H
-/*
- * Copyright (C) 2001 PPC64 Team, IBM Corp
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <asm/dma.h>
-#include <asm-generic/scatterlist.h>
-
-#define ARCH_HAS_SG_CHAIN
-
-#endif /* _ASM_POWERPC_SCATTERLIST_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/scom.h b/ANDROID_3.4.5/arch/powerpc/include/asm/scom.h
deleted file mode 100644
index 0cabfd7b..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/scom.h
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * Copyright 2010 Benjamin Herrenschmidt, IBM Corp
- *                <benh@kernel.crashing.org>
- *     and        David Gibson, IBM Corporation.
- *
- *   This program is free software;  you can redistribute it and/or modify
- *   it under the terms of the GNU General Public License as published by
- *   the Free Software Foundation; either version 2 of the License, or
- *   (at your option) any later version.
- *
- *   This program is distributed in the hope that it will be useful,
- *   but WITHOUT ANY WARRANTY;  without even the implied warranty of
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
- *   the GNU General Public License for more details.
- *
- *   You should have received a copy of the GNU General Public License
- *   along with this program;  if not, write to the Free Software
- *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#ifndef _ASM_POWERPC_SCOM_H
-#define _ASM_POWERPC_SCOM_H
-
-#ifdef __KERNEL__
-#ifndef __ASSEMBLY__
-#ifdef CONFIG_PPC_SCOM
-
-/*
- * The SCOM bus is a sideband bus used for accessing various internal
- * registers of the processor or the chipset. The implementation details
- * differ between processors and platforms, and the access method as
- * well.
- *
- * This API allows to "map" ranges of SCOM register numbers associated
- * with a given SCOM controller. The later must be represented by a
- * device node, though some implementations might support NULL if there
- * is no possible ambiguity
- *
- * Then, scom_read/scom_write can be used to accesses registers inside
- * that range. The argument passed is a register number relative to
- * the beginning of the range mapped.
- */
-
-typedef void *scom_map_t;
-
-/* Value for an invalid SCOM map */
-#define SCOM_MAP_INVALID	(NULL)
-
-/* The scom_controller data structure is what the platform passes
- * to the core code in scom_init, it provides the actual implementation
- * of all the SCOM functions
- */
-struct scom_controller {
-	scom_map_t (*map)(struct device_node *ctrl_dev, u64 reg, u64 count);
-	void (*unmap)(scom_map_t map);
-
-	u64 (*read)(scom_map_t map, u32 reg);
-	void (*write)(scom_map_t map, u32 reg, u64 value);
-};
-
-extern const struct scom_controller *scom_controller;
-
-/**
- * scom_init - Initialize the SCOM backend, called by the platform
- * @controller: The platform SCOM controller
- */
-static inline void scom_init(const struct scom_controller *controller)
-{
-	scom_controller = controller;
-}
-
-/**
- * scom_map_ok - Test is a SCOM mapping is successful
- * @map: The result of scom_map to test
- */
-static inline int scom_map_ok(scom_map_t map)
-{
-	return map != SCOM_MAP_INVALID;
-}
-
-/**
- * scom_map - Map a block of SCOM registers
- * @ctrl_dev: Device node of the SCOM controller
- *            some implementations allow NULL here
- * @reg: first SCOM register to map
- * @count: Number of SCOM registers to map
- */
-
-static inline scom_map_t scom_map(struct device_node *ctrl_dev,
-				  u64 reg, u64 count)
-{
-	return scom_controller->map(ctrl_dev, reg, count);
-}
-
-/**
- * scom_find_parent - Find the SCOM controller for a device
- * @dev: OF node of the device
- *
- * This is not meant for general usage, but in combination with
- * scom_map() allows to map registers not represented by the
- * device own scom-reg property. Useful for applying HW workarounds
- * on things not properly represented in the device-tree for example.
- */
-struct device_node *scom_find_parent(struct device_node *dev);
-
-
-/**
- * scom_map_device - Map a device's block of SCOM registers
- * @dev: OF node of the device
- * @index: Register bank index (index in "scom-reg" property)
- *
- * This function will use the device-tree binding for SCOM which
- * is to follow "scom-parent" properties until it finds a node with
- * a "scom-controller" property to find the controller. It will then
- * use the "scom-reg" property which is made of reg/count pairs,
- * each of them having a size defined by the controller's #scom-cells
- * property
- */
-extern scom_map_t scom_map_device(struct device_node *dev, int index);
-
-
-/**
- * scom_unmap - Unmap a block of SCOM registers
- * @map: Result of scom_map is to be unmapped
- */
-static inline void scom_unmap(scom_map_t map)
-{
-	if (scom_map_ok(map))
-		scom_controller->unmap(map);
-}
-
-/**
- * scom_read - Read a SCOM register
- * @map: Result of scom_map
- * @reg: Register index within that map
- */
-static inline u64 scom_read(scom_map_t map, u32 reg)
-{
-	return scom_controller->read(map, reg);
-}
-
-/**
- * scom_write - Write to a SCOM register
- * @map: Result of scom_map
- * @reg: Register index within that map
- * @value: Value to write
- */
-static inline void scom_write(scom_map_t map, u32 reg, u64 value)
-{
-	scom_controller->write(map, reg, value);
-}
-
-#endif /* CONFIG_PPC_SCOM */
-#endif /* __ASSEMBLY__ */
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_SCOM_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/seccomp.h b/ANDROID_3.4.5/arch/powerpc/include/asm/seccomp.h
deleted file mode 100644
index 00c1d913..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/seccomp.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#ifndef _ASM_POWERPC_SECCOMP_H
-#define _ASM_POWERPC_SECCOMP_H
-
-#include <linux/unistd.h>
-
-#define __NR_seccomp_read __NR_read
-#define __NR_seccomp_write __NR_write
-#define __NR_seccomp_exit __NR_exit
-#define __NR_seccomp_sigreturn __NR_rt_sigreturn
-
-#define __NR_seccomp_read_32 __NR_read
-#define __NR_seccomp_write_32 __NR_write
-#define __NR_seccomp_exit_32 __NR_exit
-#define __NR_seccomp_sigreturn_32 __NR_sigreturn
-
-#endif	/* _ASM_POWERPC_SECCOMP_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/sections.h b/ANDROID_3.4.5/arch/powerpc/include/asm/sections.h
deleted file mode 100644
index a0f358d4..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/sections.h
+++ /dev/null
@@ -1,41 +0,0 @@
-#ifndef _ASM_POWERPC_SECTIONS_H
-#define _ASM_POWERPC_SECTIONS_H
-#ifdef __KERNEL__
-
-#include <linux/elf.h>
-#include <linux/uaccess.h>
-#include <asm-generic/sections.h>
-
-#ifdef __powerpc64__
-
-extern char __end_interrupts[];
-
-static inline int in_kernel_text(unsigned long addr)
-{
-	if (addr >= (unsigned long)_stext && addr < (unsigned long)__init_end)
-		return 1;
-
-	return 0;
-}
-
-static inline int overlaps_kernel_text(unsigned long start, unsigned long end)
-{
-	return start < (unsigned long)__init_end &&
-		(unsigned long)_stext < end;
-}
-
-#undef dereference_function_descriptor
-static inline void *dereference_function_descriptor(void *ptr)
-{
-	struct ppc64_opd_entry *desc = ptr;
-	void *p;
-
-	if (!probe_kernel_address(&desc->funcaddr, p))
-		ptr = p;
-	return ptr;
-}
-
-#endif
-
-#endif /* __KERNEL__ */
-#endif	/* _ASM_POWERPC_SECTIONS_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/sembuf.h b/ANDROID_3.4.5/arch/powerpc/include/asm/sembuf.h
deleted file mode 100644
index 99a41938..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/sembuf.h
+++ /dev/null
@@ -1,36 +0,0 @@
-#ifndef _ASM_POWERPC_SEMBUF_H
-#define _ASM_POWERPC_SEMBUF_H
-
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-/*
- * The semid64_ds structure for PPC architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-
-struct semid64_ds {
-	struct ipc64_perm sem_perm;	/* permissions .. see ipc.h */
-#ifndef __powerpc64__
-	unsigned long	__unused1;
-#endif
-	__kernel_time_t	sem_otime;	/* last semop time */
-#ifndef __powerpc64__
-	unsigned long	__unused2;
-#endif
-	__kernel_time_t	sem_ctime;	/* last change time */
-	unsigned long	sem_nsems;	/* no. of semaphores in array */
-	unsigned long	__unused3;
-	unsigned long	__unused4;
-};
-
-#endif	/* _ASM_POWERPC_SEMBUF_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/serial.h b/ANDROID_3.4.5/arch/powerpc/include/asm/serial.h
deleted file mode 100644
index 3e8589b4..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/serial.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef _ASM_POWERPC_SERIAL_H
-#define _ASM_POWERPC_SERIAL_H
-
-/*
- * Serial ports are not listed here, because they are discovered
- * through the device tree.
- */
-
-/* Default baud base if not found in device-tree */
-#define BASE_BAUD ( 1843200 / 16 )
-
-#ifdef CONFIG_PPC_UDBG_16550
-extern void find_legacy_serial_ports(void);
-#else
-#define find_legacy_serial_ports()	do { } while (0)
-#endif
-
-#endif /* _PPC64_SERIAL_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/setjmp.h b/ANDROID_3.4.5/arch/powerpc/include/asm/setjmp.h
deleted file mode 100644
index 279d03a1..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/setjmp.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * Copyright © 2008 Michael Neuling IBM Corporation
- *
- *      This program is free software; you can redistribute it and/or
- *      modify it under the terms of the GNU General Public License
- *      as published by the Free Software Foundation; either version
- *      2 of the License, or (at your option) any later version.
- *
- */
-#ifndef _ASM_POWERPC_SETJMP_H
-#define _ASM_POWERPC_SETJMP_H
-
-#define JMP_BUF_LEN    23
-
-extern long setjmp(long *);
-extern void longjmp(long *, long);
-
-#endif /* _ASM_POWERPC_SETJMP_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/setup.h b/ANDROID_3.4.5/arch/powerpc/include/asm/setup.h
deleted file mode 100644
index d084ce19..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/setup.h
+++ /dev/null
@@ -1,32 +0,0 @@
-#ifndef _ASM_POWERPC_SETUP_H
-#define _ASM_POWERPC_SETUP_H
-
-#include <asm-generic/setup.h>
-
-#ifndef __ASSEMBLY__
-extern void ppc_printk_progress(char *s, unsigned short hex);
-
-extern unsigned int rtas_data;
-extern int mem_init_done;	/* set on boot once kmalloc can be called */
-extern int init_bootmem_done;	/* set once bootmem is available */
-extern phys_addr_t memory_limit;
-extern unsigned long klimit;
-extern void *zalloc_maybe_bootmem(size_t size, gfp_t mask);
-
-extern void via_cuda_init(void);
-extern void read_rtc_time(void);
-extern void pmac_find_display(void);
-
-struct device_node;
-extern void note_scsi_host(struct device_node *, void *);
-
-/* Used in very early kernel initialization. */
-extern unsigned long reloc_offset(void);
-extern unsigned long add_reloc_offset(unsigned long);
-extern void reloc_got2(unsigned long);
-
-#define PTRRELOC(x)	((typeof(x)) add_reloc_offset((unsigned long)(x)))
-
-#endif /* !__ASSEMBLY__ */
-
-#endif	/* _ASM_POWERPC_SETUP_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/sfp-machine.h b/ANDROID_3.4.5/arch/powerpc/include/asm/sfp-machine.h
deleted file mode 100644
index 3a7a67a0..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/sfp-machine.h
+++ /dev/null
@@ -1,377 +0,0 @@
-/* Machine-dependent software floating-point definitions.  PPC version.
-   Copyright (C) 1997 Free Software Foundation, Inc.
-   This file is part of the GNU C Library.
-
-   The GNU C Library is free software; you can redistribute it and/or
-   modify it under the terms of the GNU Library General Public License as
-   published by the Free Software Foundation; either version 2 of the
-   License, or (at your option) any later version.
-
-   The GNU C Library is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-   Library General Public License for more details.
-
-   You should have received a copy of the GNU Library General Public
-   License along with the GNU C Library; see the file COPYING.LIB.  If
-   not, write to the Free Software Foundation, Inc.,
-   59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-   Actually, this is a PPC (32bit) version, written based on the
-   i386, sparc, and sparc64 versions, by me,
-   Peter Maydell (pmaydell@chiark.greenend.org.uk).
-   Comments are by and large also mine, although they may be inaccurate.
-
-   In picking out asm fragments I've gone with the lowest common
-   denominator, which also happens to be the hardware I have :->
-   That is, a SPARC without hardware multiply and divide.
- */
-
-/* basic word size definitions */
-#define _FP_W_TYPE_SIZE		32
-#define _FP_W_TYPE		unsigned int
-#define _FP_WS_TYPE		signed int
-#define _FP_I_TYPE		int
-
-#define __ll_B			((UWtype) 1 << (W_TYPE_SIZE / 2))
-#define __ll_lowpart(t)		((UWtype) (t) & (__ll_B - 1))
-#define __ll_highpart(t)	((UWtype) (t) >> (W_TYPE_SIZE / 2))
-
-/* You can optionally code some things like addition in asm. For
- * example, i386 defines __FP_FRAC_ADD_2 as asm. If you don't
- * then you get a fragment of C code [if you change an #ifdef 0
- * in op-2.h] or a call to add_ssaaaa (see below).
- * Good places to look for asm fragments to use are gcc and glibc.
- * gcc's longlong.h is useful.
- */
-
-/* We need to know how to multiply and divide. If the host word size
- * is >= 2*fracbits you can use FP_MUL_MEAT_n_imm(t,R,X,Y) which
- * codes the multiply with whatever gcc does to 'a * b'.
- * _FP_MUL_MEAT_n_wide(t,R,X,Y,f) is used when you have an asm
- * function that can multiply two 1W values and get a 2W result.
- * Otherwise you're stuck with _FP_MUL_MEAT_n_hard(t,R,X,Y) which
- * does bitshifting to avoid overflow.
- * For division there is FP_DIV_MEAT_n_imm(t,R,X,Y,f) for word size
- * >= 2*fracbits, where f is either _FP_DIV_HELP_imm or
- * _FP_DIV_HELP_ldiv (see op-1.h).
- * _FP_DIV_MEAT_udiv() is if you have asm to do 2W/1W => (1W, 1W).
- * [GCC and glibc have longlong.h which has the asm macro udiv_qrnnd
- * to do this.]
- * In general, 'n' is the number of words required to hold the type,
- * and 't' is either S, D or Q for single/double/quad.
- *           -- PMM
- */
-/* Example: SPARC64:
- * #define _FP_MUL_MEAT_S(R,X,Y)	_FP_MUL_MEAT_1_imm(S,R,X,Y)
- * #define _FP_MUL_MEAT_D(R,X,Y)	_FP_MUL_MEAT_1_wide(D,R,X,Y,umul_ppmm)
- * #define _FP_MUL_MEAT_Q(R,X,Y)	_FP_MUL_MEAT_2_wide(Q,R,X,Y,umul_ppmm)
- *
- * #define _FP_DIV_MEAT_S(R,X,Y)	_FP_DIV_MEAT_1_imm(S,R,X,Y,_FP_DIV_HELP_imm)
- * #define _FP_DIV_MEAT_D(R,X,Y)	_FP_DIV_MEAT_1_udiv(D,R,X,Y)
- * #define _FP_DIV_MEAT_Q(R,X,Y)	_FP_DIV_MEAT_2_udiv_64(Q,R,X,Y)
- *
- * Example: i386:
- * #define _FP_MUL_MEAT_S(R,X,Y)   _FP_MUL_MEAT_1_wide(S,R,X,Y,_i386_mul_32_64)
- * #define _FP_MUL_MEAT_D(R,X,Y)   _FP_MUL_MEAT_2_wide(D,R,X,Y,_i386_mul_32_64)
- *
- * #define _FP_DIV_MEAT_S(R,X,Y)   _FP_DIV_MEAT_1_udiv(S,R,X,Y,_i386_div_64_32)
- * #define _FP_DIV_MEAT_D(R,X,Y)   _FP_DIV_MEAT_2_udiv_64(D,R,X,Y)
- */
-
-#define _FP_MUL_MEAT_S(R,X,Y)   _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_S,R,X,Y,umul_ppmm)
-#define _FP_MUL_MEAT_D(R,X,Y)   _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm)
-
-#define _FP_DIV_MEAT_S(R,X,Y)	_FP_DIV_MEAT_1_udiv_norm(S,R,X,Y)
-#define _FP_DIV_MEAT_D(R,X,Y)	_FP_DIV_MEAT_2_udiv(D,R,X,Y)
-
-/* These macros define what NaN looks like. They're supposed to expand to
- * a comma-separated set of 32bit unsigned ints that encode NaN.
- */
-#define _FP_NANFRAC_S		((_FP_QNANBIT_S << 1) - 1)
-#define _FP_NANFRAC_D		((_FP_QNANBIT_D << 1) - 1), -1
-#define _FP_NANFRAC_Q		((_FP_QNANBIT_Q << 1) - 1), -1, -1, -1
-#define _FP_NANSIGN_S		0
-#define _FP_NANSIGN_D		0
-#define _FP_NANSIGN_Q		0
-
-#define _FP_KEEPNANFRACP 1
-
-#ifdef FP_EX_BOOKE_E500_SPE
-#define FP_EX_INEXACT		(1 << 21)
-#define FP_EX_INVALID		(1 << 20)
-#define FP_EX_DIVZERO		(1 << 19)
-#define FP_EX_UNDERFLOW		(1 << 18)
-#define FP_EX_OVERFLOW		(1 << 17)
-#define FP_INHIBIT_RESULTS	0
-
-#define __FPU_FPSCR	(current->thread.spefscr)
-#define __FPU_ENABLED_EXC		\
-({					\
-	(__FPU_FPSCR >> 2) & 0x1f;	\
-})
-#else
-/* Exception flags.  We use the bit positions of the appropriate bits
-   in the FPSCR, which also correspond to the FE_* bits.  This makes
-   everything easier ;-).  */
-#define FP_EX_INVALID         (1 << (31 - 2))
-#define FP_EX_INVALID_SNAN	EFLAG_VXSNAN
-#define FP_EX_INVALID_ISI	EFLAG_VXISI
-#define FP_EX_INVALID_IDI	EFLAG_VXIDI
-#define FP_EX_INVALID_ZDZ	EFLAG_VXZDZ
-#define FP_EX_INVALID_IMZ	EFLAG_VXIMZ
-#define FP_EX_OVERFLOW        (1 << (31 - 3))
-#define FP_EX_UNDERFLOW       (1 << (31 - 4))
-#define FP_EX_DIVZERO         (1 << (31 - 5))
-#define FP_EX_INEXACT         (1 << (31 - 6))
-
-#define __FPU_FPSCR	(current->thread.fpscr.val)
-
-/* We only actually write to the destination register
- * if exceptions signalled (if any) will not trap.
- */
-#define __FPU_ENABLED_EXC \
-({						\
-	(__FPU_FPSCR >> 3) & 0x1f;	\
-})
-
-#endif
-
-/*
- * If one NaN is signaling and the other is not,
- * we choose that one, otherwise we choose X.
- */
-#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP)			\
-  do {								\
-    if ((_FP_FRAC_HIGH_RAW_##fs(Y) & _FP_QNANBIT_##fs)		\
-	&& !(_FP_FRAC_HIGH_RAW_##fs(X) & _FP_QNANBIT_##fs))	\
-      {								\
-	R##_s = X##_s;						\
-	_FP_FRAC_COPY_##wc(R,X);				\
-      }								\
-    else							\
-      {								\
-	R##_s = Y##_s;						\
-	_FP_FRAC_COPY_##wc(R,Y);				\
-      }								\
-    R##_c = FP_CLS_NAN;						\
-  } while (0)
-
-
-#include <linux/kernel.h>
-#include <linux/sched.h>
-
-#define __FPU_TRAP_P(bits) \
-	((__FPU_ENABLED_EXC & (bits)) != 0)
-
-#define __FP_PACK_S(val,X)			\
-({  int __exc = _FP_PACK_CANONICAL(S,1,X);	\
-    if(!__exc || !__FPU_TRAP_P(__exc))		\
-        _FP_PACK_RAW_1_P(S,val,X);		\
-    __exc;					\
-})
-
-#define __FP_PACK_D(val,X)			\
-   do {									\
-	_FP_PACK_CANONICAL(D, 2, X);					\
-	if (!FP_CUR_EXCEPTIONS || !__FPU_TRAP_P(FP_CUR_EXCEPTIONS))	\
-		_FP_PACK_RAW_2_P(D, val, X);				\
-   } while (0)
-
-#define __FP_PACK_DS(val,X)							\
-   do {										\
-	   FP_DECL_S(__X);							\
-	   FP_CONV(S, D, 1, 2, __X, X);						\
-	   _FP_PACK_CANONICAL(S, 1, __X);					\
-	   if (!FP_CUR_EXCEPTIONS || !__FPU_TRAP_P(FP_CUR_EXCEPTIONS)) {	\
-		   _FP_UNPACK_CANONICAL(S, 1, __X);				\
-		   FP_CONV(D, S, 2, 1, X, __X);					\
-		   _FP_PACK_CANONICAL(D, 2, X);					\
-		   if (!FP_CUR_EXCEPTIONS || !__FPU_TRAP_P(FP_CUR_EXCEPTIONS))	\
-		   _FP_PACK_RAW_2_P(D, val, X);					\
-	   }									\
-   } while (0)
-
-/* Obtain the current rounding mode. */
-#define FP_ROUNDMODE			\
-({					\
-	__FPU_FPSCR & 0x3;		\
-})
-
-/* the asm fragments go here: all these are taken from glibc-2.0.5's
- * stdlib/longlong.h
- */
-
-#include <linux/types.h>
-#include <asm/byteorder.h>
-
-/* add_ssaaaa is used in op-2.h and should be equivalent to
- * #define add_ssaaaa(sh,sl,ah,al,bh,bl) (sh = ah+bh+ (( sl = al+bl) < al))
- * add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1,
- * high_addend_2, low_addend_2) adds two UWtype integers, composed by
- * HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and LOW_ADDEND_2
- * respectively.  The result is placed in HIGH_SUM and LOW_SUM.  Overflow
- * (i.e. carry out) is not stored anywhere, and is lost.
- */
-#define add_ssaaaa(sh, sl, ah, al, bh, bl)				\
-  do {									\
-    if (__builtin_constant_p (bh) && (bh) == 0)				\
-      __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2"		\
-	     : "=r" ((USItype)(sh)),					\
-	       "=&r" ((USItype)(sl))					\
-	     : "%r" ((USItype)(ah)),					\
-	       "%r" ((USItype)(al)),					\
-	       "rI" ((USItype)(bl)));					\
-    else if (__builtin_constant_p (bh) && (bh) ==~(USItype) 0)		\
-      __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2"		\
-	     : "=r" ((USItype)(sh)),					\
-	       "=&r" ((USItype)(sl))					\
-	     : "%r" ((USItype)(ah)),					\
-	       "%r" ((USItype)(al)),					\
-	       "rI" ((USItype)(bl)));					\
-    else								\
-      __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3"		\
-	     : "=r" ((USItype)(sh)),					\
-	       "=&r" ((USItype)(sl))					\
-	     : "%r" ((USItype)(ah)),					\
-	       "r" ((USItype)(bh)),					\
-	       "%r" ((USItype)(al)),					\
-	       "rI" ((USItype)(bl)));					\
-  } while (0)
-
-/* sub_ddmmss is used in op-2.h and udivmodti4.c and should be equivalent to
- * #define sub_ddmmss(sh, sl, ah, al, bh, bl) (sh = ah-bh - ((sl = al-bl) > al))
- * sub_ddmmss(high_difference, low_difference, high_minuend, low_minuend,
- * high_subtrahend, low_subtrahend) subtracts two two-word UWtype integers,
- * composed by HIGH_MINUEND_1 and LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and
- * LOW_SUBTRAHEND_2 respectively.  The result is placed in HIGH_DIFFERENCE
- * and LOW_DIFFERENCE.  Overflow (i.e. carry out) is not stored anywhere,
- * and is lost.
- */
-#define sub_ddmmss(sh, sl, ah, al, bh, bl)				\
-  do {									\
-    if (__builtin_constant_p (ah) && (ah) == 0)				\
-      __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2"	\
-	       : "=r" ((USItype)(sh)),					\
-		 "=&r" ((USItype)(sl))					\
-	       : "r" ((USItype)(bh)),					\
-		 "rI" ((USItype)(al)),					\
-		 "r" ((USItype)(bl)));					\
-    else if (__builtin_constant_p (ah) && (ah) ==~(USItype) 0)		\
-      __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2"	\
-	       : "=r" ((USItype)(sh)),					\
-		 "=&r" ((USItype)(sl))					\
-	       : "r" ((USItype)(bh)),					\
-		 "rI" ((USItype)(al)),					\
-		 "r" ((USItype)(bl)));					\
-    else if (__builtin_constant_p (bh) && (bh) == 0)			\
-      __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2"		\
-	       : "=r" ((USItype)(sh)),					\
-		 "=&r" ((USItype)(sl))					\
-	       : "r" ((USItype)(ah)),					\
-		 "rI" ((USItype)(al)),					\
-		 "r" ((USItype)(bl)));					\
-    else if (__builtin_constant_p (bh) && (bh) ==~(USItype) 0)		\
-      __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2"		\
-	       : "=r" ((USItype)(sh)),					\
-		 "=&r" ((USItype)(sl))					\
-	       : "r" ((USItype)(ah)),					\
-		 "rI" ((USItype)(al)),					\
-		 "r" ((USItype)(bl)));					\
-    else								\
-      __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2"	\
-	       : "=r" ((USItype)(sh)),					\
-		 "=&r" ((USItype)(sl))					\
-	       : "r" ((USItype)(ah)),					\
-		 "r" ((USItype)(bh)),					\
-		 "rI" ((USItype)(al)),					\
-		 "r" ((USItype)(bl)));					\
-  } while (0)
-
-/* asm fragments for mul and div */
-
-/* umul_ppmm(high_prod, low_prod, multipler, multiplicand) multiplies two
- * UWtype integers MULTIPLER and MULTIPLICAND, and generates a two UWtype
- * word product in HIGH_PROD and LOW_PROD.
- */
-#define umul_ppmm(ph, pl, m0, m1)					\
-  do {									\
-    USItype __m0 = (m0), __m1 = (m1);					\
-    __asm__ ("mulhwu %0,%1,%2"						\
-	     : "=r" ((USItype)(ph))					\
-	     : "%r" (__m0),						\
-               "r" (__m1));						\
-    (pl) = __m0 * __m1;							\
-  } while (0)
-
-/* udiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
- * denominator) divides a UDWtype, composed by the UWtype integers
- * HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and places the quotient
- * in QUOTIENT and the remainder in REMAINDER.  HIGH_NUMERATOR must be less
- * than DENOMINATOR for correct operation.  If, in addition, the most
- * significant bit of DENOMINATOR must be 1, then the pre-processor symbol
- * UDIV_NEEDS_NORMALIZATION is defined to 1.
- */
-#define udiv_qrnnd(q, r, n1, n0, d)					\
-  do {									\
-    UWtype __d1, __d0, __q1, __q0, __r1, __r0, __m;			\
-    __d1 = __ll_highpart (d);						\
-    __d0 = __ll_lowpart (d);						\
-									\
-    __r1 = (n1) % __d1;							\
-    __q1 = (n1) / __d1;							\
-    __m = (UWtype) __q1 * __d0;						\
-    __r1 = __r1 * __ll_B | __ll_highpart (n0);				\
-    if (__r1 < __m)							\
-      {									\
-	__q1--, __r1 += (d);						\
-	if (__r1 >= (d)) /* we didn't get carry when adding to __r1 */	\
-	  if (__r1 < __m)						\
-	    __q1--, __r1 += (d);					\
-      }									\
-    __r1 -= __m;							\
-									\
-    __r0 = __r1 % __d1;							\
-    __q0 = __r1 / __d1;							\
-    __m = (UWtype) __q0 * __d0;						\
-    __r0 = __r0 * __ll_B | __ll_lowpart (n0);				\
-    if (__r0 < __m)							\
-      {									\
-	__q0--, __r0 += (d);						\
-	if (__r0 >= (d))						\
-	  if (__r0 < __m)						\
-	    __q0--, __r0 += (d);					\
-      }									\
-    __r0 -= __m;							\
-									\
-    (q) = (UWtype) __q1 * __ll_B | __q0;				\
-    (r) = __r0;								\
-  } while (0)
-
-#define UDIV_NEEDS_NORMALIZATION 1
-
-#define abort()								\
-	return 0
-
-#ifdef __BIG_ENDIAN
-#define __BYTE_ORDER __BIG_ENDIAN
-#else
-#define __BYTE_ORDER __LITTLE_ENDIAN
-#endif
-
-/* Exception flags. */
-#define EFLAG_INVALID		(1 << (31 - 2))
-#define EFLAG_OVERFLOW		(1 << (31 - 3))
-#define EFLAG_UNDERFLOW		(1 << (31 - 4))
-#define EFLAG_DIVZERO		(1 << (31 - 5))
-#define EFLAG_INEXACT		(1 << (31 - 6))
-
-#define EFLAG_VXSNAN		(1 << (31 - 7))
-#define EFLAG_VXISI		(1 << (31 - 8))
-#define EFLAG_VXIDI		(1 << (31 - 9))
-#define EFLAG_VXZDZ		(1 << (31 - 10))
-#define EFLAG_VXIMZ		(1 << (31 - 11))
-#define EFLAG_VXVC		(1 << (31 - 12))
-#define EFLAG_VXSOFT		(1 << (31 - 21))
-#define EFLAG_VXSQRT		(1 << (31 - 22))
-#define EFLAG_VXCVI		(1 << (31 - 23))
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/shmbuf.h b/ANDROID_3.4.5/arch/powerpc/include/asm/shmbuf.h
deleted file mode 100644
index 8efa3969..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/shmbuf.h
+++ /dev/null
@@ -1,59 +0,0 @@
-#ifndef _ASM_POWERPC_SHMBUF_H
-#define _ASM_POWERPC_SHMBUF_H
-
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-/*
- * The shmid64_ds structure for PPC architecture.
- *
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-
-struct shmid64_ds {
-	struct ipc64_perm	shm_perm;	/* operation perms */
-#ifndef __powerpc64__
-	unsigned long		__unused1;
-#endif
-	__kernel_time_t		shm_atime;	/* last attach time */
-#ifndef __powerpc64__
-	unsigned long		__unused2;
-#endif
-	__kernel_time_t		shm_dtime;	/* last detach time */
-#ifndef __powerpc64__
-	unsigned long		__unused3;
-#endif
-	__kernel_time_t		shm_ctime;	/* last change time */
-#ifndef __powerpc64__
-	unsigned long		__unused4;
-#endif
-	size_t			shm_segsz;	/* size of segment (bytes) */
-	__kernel_pid_t		shm_cpid;	/* pid of creator */
-	__kernel_pid_t		shm_lpid;	/* pid of last operator */
-	unsigned long		shm_nattch;	/* no. of current attaches */
-	unsigned long		__unused5;
-	unsigned long		__unused6;
-};
-
-struct shminfo64 {
-	unsigned long	shmmax;
-	unsigned long	shmmin;
-	unsigned long	shmmni;
-	unsigned long	shmseg;
-	unsigned long	shmall;
-	unsigned long	__unused1;
-	unsigned long	__unused2;
-	unsigned long	__unused3;
-	unsigned long	__unused4;
-};
-
-#endif	/* _ASM_POWERPC_SHMBUF_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/shmparam.h b/ANDROID_3.4.5/arch/powerpc/include/asm/shmparam.h
deleted file mode 100644
index 5cda42a6..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/shmparam.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_POWERPC_SHMPARAM_H
-#define _ASM_POWERPC_SHMPARAM_H
-
-#define	SHMLBA PAGE_SIZE		 /* attach addr a multiple of this */
-
-#endif	/* _ASM_POWERPC_SHMPARAM_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/sigcontext.h b/ANDROID_3.4.5/arch/powerpc/include/asm/sigcontext.h
deleted file mode 100644
index 9c1f24fd..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/sigcontext.h
+++ /dev/null
@@ -1,87 +0,0 @@
-#ifndef _ASM_POWERPC_SIGCONTEXT_H
-#define _ASM_POWERPC_SIGCONTEXT_H
-
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#include <linux/compiler.h>
-#include <asm/ptrace.h>
-#ifdef __powerpc64__
-#include <asm/elf.h>
-#endif
-
-struct sigcontext {
-	unsigned long	_unused[4];
-	int		signal;
-#ifdef __powerpc64__
-	int		_pad0;
-#endif
-	unsigned long	handler;
-	unsigned long	oldmask;
-	struct pt_regs	__user *regs;
-#ifdef __powerpc64__
-	elf_gregset_t	gp_regs;
-	elf_fpregset_t	fp_regs;
-/*
- * To maintain compatibility with current implementations the sigcontext is
- * extended by appending a pointer (v_regs) to a quadword type (elf_vrreg_t)
- * followed by an unstructured (vmx_reserve) field of 69 doublewords.  This
- * allows the array of vector registers to be quadword aligned independent of
- * the alignment of the containing sigcontext or ucontext. It is the
- * responsibility of the code setting the sigcontext to set this pointer to
- * either NULL (if this processor does not support the VMX feature) or the
- * address of the first quadword within the allocated (vmx_reserve) area.
- *
- * The pointer (v_regs) of vector type (elf_vrreg_t) is type compatible with
- * an array of 34 quadword entries (elf_vrregset_t).  The entries with
- * indexes 0-31 contain the corresponding vector registers.  The entry with
- * index 32 contains the vscr as the last word (offset 12) within the
- * quadword.  This allows the vscr to be stored as either a quadword (since
- * it must be copied via a vector register to/from storage) or as a word.
- * The entry with index 33 contains the vrsave as the first word (offset 0)
- * within the quadword.
- *
- * Part of the VSX data is stored here also by extending vmx_restore
- * by an additional 32 double words.  Architecturally the layout of
- * the VSR registers and how they overlap on top of the legacy FPR and
- * VR registers is shown below:
- *
- *                    VSR doubleword 0               VSR doubleword 1
- *           ----------------------------------------------------------------
- *   VSR[0]  |             FPR[0]            |                              |
- *           ----------------------------------------------------------------
- *   VSR[1]  |             FPR[1]            |                              |
- *           ----------------------------------------------------------------
- *           |              ...              |                              |
- *           |              ...              |                              |
- *           ----------------------------------------------------------------
- *   VSR[30] |             FPR[30]           |                              |
- *           ----------------------------------------------------------------
- *   VSR[31] |             FPR[31]           |                              |
- *           ----------------------------------------------------------------
- *   VSR[32] |                             VR[0]                            |
- *           ----------------------------------------------------------------
- *   VSR[33] |                             VR[1]                            |
- *           ----------------------------------------------------------------
- *           |                              ...                             |
- *           |                              ...                             |
- *           ----------------------------------------------------------------
- *   VSR[62] |                             VR[30]                           |
- *           ----------------------------------------------------------------
- *   VSR[63] |                             VR[31]                           |
- *           ----------------------------------------------------------------
- *
- * FPR/VSR 0-31 doubleword 0 is stored in fp_regs, and VMX/VSR 32-63
- * is stored at the start of vmx_reserve.  vmx_reserve is extended for
- * backwards compatility to store VSR 0-31 doubleword 1 after the VMX
- * registers and vscr/vrsave.
- */
-	elf_vrreg_t	__user *v_regs;
-	long		vmx_reserve[ELF_NVRREG+ELF_NVRREG+32+1];
-#endif
-};
-
-#endif /* _ASM_POWERPC_SIGCONTEXT_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/siginfo.h b/ANDROID_3.4.5/arch/powerpc/include/asm/siginfo.h
deleted file mode 100644
index 49495b05..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/siginfo.h
+++ /dev/null
@@ -1,21 +0,0 @@
-#ifndef _ASM_POWERPC_SIGINFO_H
-#define _ASM_POWERPC_SIGINFO_H
-
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifdef __powerpc64__
-#    define __ARCH_SI_PREAMBLE_SIZE	(4 * sizeof(int))
-#    define SI_PAD_SIZE32		((SI_MAX_SIZE/sizeof(int)) - 3)
-#endif
-
-#include <asm-generic/siginfo.h>
-
-#undef NSIGTRAP
-#define NSIGTRAP	4
-
-#endif	/* _ASM_POWERPC_SIGINFO_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/signal.h b/ANDROID_3.4.5/arch/powerpc/include/asm/signal.h
deleted file mode 100644
index 3eb13be1..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/signal.h
+++ /dev/null
@@ -1,149 +0,0 @@
-#ifndef _ASM_POWERPC_SIGNAL_H
-#define _ASM_POWERPC_SIGNAL_H
-
-#include <linux/types.h>
-
-#define _NSIG		64
-#ifdef __powerpc64__
-#define _NSIG_BPW	64
-#else
-#define _NSIG_BPW	32
-#endif
-#define _NSIG_WORDS	(_NSIG / _NSIG_BPW)
-
-typedef unsigned long old_sigset_t;		/* at least 32 bits */
-
-typedef struct {
-	unsigned long sig[_NSIG_WORDS];
-} sigset_t;
-
-#define SIGHUP		 1
-#define SIGINT		 2
-#define SIGQUIT		 3
-#define SIGILL		 4
-#define SIGTRAP		 5
-#define SIGABRT		 6
-#define SIGIOT		 6
-#define SIGBUS		 7
-#define SIGFPE		 8
-#define SIGKILL		 9
-#define SIGUSR1		10
-#define SIGSEGV		11
-#define SIGUSR2		12
-#define SIGPIPE		13
-#define SIGALRM		14
-#define SIGTERM		15
-#define SIGSTKFLT	16
-#define SIGCHLD		17
-#define SIGCONT		18
-#define SIGSTOP		19
-#define SIGTSTP		20
-#define SIGTTIN		21
-#define SIGTTOU		22
-#define SIGURG		23
-#define SIGXCPU		24
-#define SIGXFSZ		25
-#define SIGVTALRM	26
-#define SIGPROF		27
-#define SIGWINCH	28
-#define SIGIO		29
-#define SIGPOLL		SIGIO
-/*
-#define SIGLOST		29
-*/
-#define SIGPWR		30
-#define SIGSYS		31
-#define	SIGUNUSED	31
-
-/* These should not be considered constants from userland.  */
-#define SIGRTMIN	32
-#define SIGRTMAX	_NSIG
-
-/*
- * SA_FLAGS values:
- *
- * SA_ONSTACK is not currently supported, but will allow sigaltstack(2).
- * SA_RESTART flag to get restarting signals (which were the default long ago)
- * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
- * SA_RESETHAND clears the handler when the signal is delivered.
- * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
- * SA_NODEFER prevents the current signal from being masked in the handler.
- *
- * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
- * Unix names RESETHAND and NODEFER respectively.
- */
-#define SA_NOCLDSTOP	0x00000001U
-#define SA_NOCLDWAIT	0x00000002U
-#define SA_SIGINFO	0x00000004U
-#define SA_ONSTACK	0x08000000U
-#define SA_RESTART	0x10000000U
-#define SA_NODEFER	0x40000000U
-#define SA_RESETHAND	0x80000000U
-
-#define SA_NOMASK	SA_NODEFER
-#define SA_ONESHOT	SA_RESETHAND
-
-#define SA_RESTORER	0x04000000U
-
-/*
- * sigaltstack controls
- */
-#define SS_ONSTACK	1
-#define SS_DISABLE	2
-
-#define MINSIGSTKSZ	2048
-#define SIGSTKSZ	8192
-
-#include <asm-generic/signal-defs.h>
-
-struct old_sigaction {
-	__sighandler_t sa_handler;
-	old_sigset_t sa_mask;
-	unsigned long sa_flags;
-	__sigrestore_t sa_restorer;
-};
-
-struct sigaction {
-	__sighandler_t sa_handler;
-	unsigned long sa_flags;
-	__sigrestore_t sa_restorer;
-	sigset_t sa_mask;		/* mask last for extensibility */
-};
-
-struct k_sigaction {
-	struct sigaction sa;
-};
-
-typedef struct sigaltstack {
-	void __user *ss_sp;
-	int ss_flags;
-	size_t ss_size;
-} stack_t;
-
-#ifdef __KERNEL__
-struct pt_regs;
-#define ptrace_signal_deliver(regs, cookie) do { } while (0)
-#endif /* __KERNEL__ */
-
-#ifndef __powerpc64__
-/*
- * These are parameters to dbg_sigreturn syscall.  They enable or
- * disable certain debugging things that can be done from signal
- * handlers.  The dbg_sigreturn syscall *must* be called from a
- * SA_SIGINFO signal so the ucontext can be passed to it.  It takes an
- * array of struct sig_dbg_op, which has the debug operations to
- * perform before returning from the signal.
- */
-struct sig_dbg_op {
-	int dbg_type;
-	unsigned long dbg_value;
-};
-
-/* Enable or disable single-stepping.  The value sets the state. */
-#define SIG_DBG_SINGLE_STEPPING		1
-
-/* Enable or disable branch tracing.  The value sets the state. */
-#define SIG_DBG_BRANCH_TRACING		2
-#endif /* ! __powerpc64__ */
-
-#endif /* _ASM_POWERPC_SIGNAL_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/smp.h b/ANDROID_3.4.5/arch/powerpc/include/asm/smp.h
deleted file mode 100644
index ebc24dc5..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/smp.h
+++ /dev/null
@@ -1,196 +0,0 @@
-/* 
- * smp.h: PowerPC-specific SMP code.
- *
- * Original was a copy of sparc smp.h.  Now heavily modified
- * for PPC.
- *
- * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
- * Copyright (C) 1996-2001 Cort Dougan <cort@fsmlabs.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_POWERPC_SMP_H
-#define _ASM_POWERPC_SMP_H
-#ifdef __KERNEL__
-
-#include <linux/threads.h>
-#include <linux/cpumask.h>
-#include <linux/kernel.h>
-#include <linux/irqreturn.h>
-
-#ifndef __ASSEMBLY__
-
-#ifdef CONFIG_PPC64
-#include <asm/paca.h>
-#endif
-#include <asm/percpu.h>
-
-extern int boot_cpuid;
-extern int spinning_secondaries;
-
-extern void cpu_die(void);
-
-#ifdef CONFIG_SMP
-
-struct smp_ops_t {
-	void  (*message_pass)(int cpu, int msg);
-#ifdef CONFIG_PPC_SMP_MUXED_IPI
-	void  (*cause_ipi)(int cpu, unsigned long data);
-#endif
-	int   (*probe)(void);
-	int   (*kick_cpu)(int nr);
-	void  (*setup_cpu)(int nr);
-	void  (*bringup_done)(void);
-	void  (*take_timebase)(void);
-	void  (*give_timebase)(void);
-	int   (*cpu_disable)(void);
-	void  (*cpu_die)(unsigned int nr);
-	int   (*cpu_bootable)(unsigned int nr);
-};
-
-extern void smp_send_debugger_break(void);
-extern void start_secondary_resume(void);
-extern void __devinit smp_generic_give_timebase(void);
-extern void __devinit smp_generic_take_timebase(void);
-
-DECLARE_PER_CPU(unsigned int, cpu_pvr);
-
-#ifdef CONFIG_HOTPLUG_CPU
-extern void migrate_irqs(void);
-int generic_cpu_disable(void);
-void generic_cpu_die(unsigned int cpu);
-void generic_mach_cpu_die(void);
-void generic_set_cpu_dead(unsigned int cpu);
-int generic_check_cpu_restart(unsigned int cpu);
-#endif
-
-#ifdef CONFIG_PPC64
-#define raw_smp_processor_id()	(local_paca->paca_index)
-#define hard_smp_processor_id() (get_paca()->hw_cpu_id)
-#else
-/* 32-bit */
-extern int smp_hw_index[];
-
-#define raw_smp_processor_id()	(current_thread_info()->cpu)
-#define hard_smp_processor_id() 	(smp_hw_index[smp_processor_id()])
-
-static inline int get_hard_smp_processor_id(int cpu)
-{
-	return smp_hw_index[cpu];
-}
-
-static inline void set_hard_smp_processor_id(int cpu, int phys)
-{
-	smp_hw_index[cpu] = phys;
-}
-#endif
-
-DECLARE_PER_CPU(cpumask_var_t, cpu_sibling_map);
-DECLARE_PER_CPU(cpumask_var_t, cpu_core_map);
-
-static inline struct cpumask *cpu_sibling_mask(int cpu)
-{
-	return per_cpu(cpu_sibling_map, cpu);
-}
-
-static inline struct cpumask *cpu_core_mask(int cpu)
-{
-	return per_cpu(cpu_core_map, cpu);
-}
-
-extern int cpu_to_core_id(int cpu);
-
-/* Since OpenPIC has only 4 IPIs, we use slightly different message numbers.
- *
- * Make sure this matches openpic_request_IPIs in open_pic.c, or what shows up
- * in /proc/interrupts will be wrong!!! --Troy */
-#define PPC_MSG_CALL_FUNCTION   0
-#define PPC_MSG_RESCHEDULE      1
-#define PPC_MSG_CALL_FUNC_SINGLE	2
-#define PPC_MSG_DEBUGGER_BREAK  3
-
-/* for irq controllers that have dedicated ipis per message (4) */
-extern int smp_request_message_ipi(int virq, int message);
-extern const char *smp_ipi_name[];
-
-/* for irq controllers with only a single ipi */
-extern void smp_muxed_ipi_set_data(int cpu, unsigned long data);
-extern void smp_muxed_ipi_message_pass(int cpu, int msg);
-extern irqreturn_t smp_ipi_demux(void);
-
-void smp_init_pSeries(void);
-void smp_init_cell(void);
-void smp_init_celleb(void);
-void smp_setup_cpu_maps(void);
-
-extern int __cpu_disable(void);
-extern void __cpu_die(unsigned int cpu);
-
-#else
-/* for UP */
-#define hard_smp_processor_id()		get_hard_smp_processor_id(0)
-#define smp_setup_cpu_maps()
-
-#endif /* CONFIG_SMP */
-
-#ifdef CONFIG_PPC64
-static inline int get_hard_smp_processor_id(int cpu)
-{
-	return paca[cpu].hw_cpu_id;
-}
-
-static inline void set_hard_smp_processor_id(int cpu, int phys)
-{
-	paca[cpu].hw_cpu_id = phys;
-}
-
-extern void smp_release_cpus(void);
-
-#else
-/* 32-bit */
-#ifndef CONFIG_SMP
-extern int boot_cpuid_phys;
-static inline int get_hard_smp_processor_id(int cpu)
-{
-	return boot_cpuid_phys;
-}
-
-static inline void set_hard_smp_processor_id(int cpu, int phys)
-{
-	boot_cpuid_phys = phys;
-}
-#endif /* !CONFIG_SMP */
-#endif /* !CONFIG_PPC64 */
-
-extern int smt_enabled_at_boot;
-
-extern int smp_mpic_probe(void);
-extern void smp_mpic_setup_cpu(int cpu);
-extern int smp_generic_kick_cpu(int nr);
-
-extern void smp_generic_give_timebase(void);
-extern void smp_generic_take_timebase(void);
-
-extern struct smp_ops_t *smp_ops;
-
-extern void arch_send_call_function_single_ipi(int cpu);
-extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
-
-/* Definitions relative to the secondary CPU spin loop
- * and entry point. Not all of them exist on both 32 and
- * 64-bit but defining them all here doesn't harm
- */
-extern void generic_secondary_smp_init(void);
-extern void generic_secondary_thread_init(void);
-extern unsigned long __secondary_hold_spinloop;
-extern unsigned long __secondary_hold_acknowledge;
-extern char __secondary_hold;
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_SMP_H) */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/smu.h b/ANDROID_3.4.5/arch/powerpc/include/asm/smu.h
deleted file mode 100644
index ae20ce1a..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/smu.h
+++ /dev/null
@@ -1,700 +0,0 @@
-#ifndef _SMU_H
-#define _SMU_H
-
-/*
- * Definitions for talking to the SMU chip in newer G5 PowerMacs
- */
-#ifdef __KERNEL__
-#include <linux/list.h>
-#endif
-#include <linux/types.h>
-
-/*
- * Known SMU commands
- *
- * Most of what is below comes from looking at the Open Firmware driver,
- * though this is still incomplete and could use better documentation here
- * or there...
- */
-
-
-/*
- * Partition info commands
- *
- * These commands are used to retrieve the sdb-partition-XX datas from
- * the SMU. The length is always 2. First byte is the subcommand code
- * and second byte is the partition ID.
- *
- * The reply is 6 bytes:
- *
- *  - 0..1 : partition address
- *  - 2    : a byte containing the partition ID
- *  - 3    : length (maybe other bits are rest of header ?)
- *
- * The data must then be obtained with calls to another command:
- * SMU_CMD_MISC_ee_GET_DATABLOCK_REC (described below).
- */
-#define SMU_CMD_PARTITION_COMMAND		0x3e
-#define   SMU_CMD_PARTITION_LATEST		0x01
-#define   SMU_CMD_PARTITION_BASE		0x02
-#define   SMU_CMD_PARTITION_UPDATE		0x03
-
-
-/*
- * Fan control
- *
- * This is a "mux" for fan control commands. The command seem to
- * act differently based on the number of arguments. With 1 byte
- * of argument, this seem to be queries for fans status, setpoint,
- * etc..., while with 0xe arguments, we will set the fans speeds.
- *
- * Queries (1 byte arg):
- * ---------------------
- *
- * arg=0x01: read RPM fans status
- * arg=0x02: read RPM fans setpoint
- * arg=0x11: read PWM fans status
- * arg=0x12: read PWM fans setpoint
- *
- * the "status" queries return the current speed while the "setpoint" ones
- * return the programmed/target speed. It _seems_ that the result is a bit
- * mask in the first byte of active/available fans, followed by 6 words (16
- * bits) containing the requested speed.
- *
- * Setpoint (14 bytes arg):
- * ------------------------
- *
- * first arg byte is 0 for RPM fans and 0x10 for PWM. Second arg byte is the
- * mask of fans affected by the command. Followed by 6 words containing the
- * setpoint value for selected fans in the mask (or 0 if mask value is 0)
- */
-#define SMU_CMD_FAN_COMMAND			0x4a
-
-
-/*
- * Battery access
- *
- * Same command number as the PMU, could it be same syntax ?
- */
-#define SMU_CMD_BATTERY_COMMAND			0x6f
-#define   SMU_CMD_GET_BATTERY_INFO		0x00
-
-/*
- * Real time clock control
- *
- * This is a "mux", first data byte contains the "sub" command.
- * The "RTC" part of the SMU controls the date, time, powerup
- * timer, but also a PRAM
- *
- * Dates are in BCD format on 7 bytes:
- * [sec] [min] [hour] [weekday] [month day] [month] [year]
- * with month being 1 based and year minus 100
- */
-#define SMU_CMD_RTC_COMMAND			0x8e
-#define   SMU_CMD_RTC_SET_PWRUP_TIMER		0x00 /* i: 7 bytes date */
-#define   SMU_CMD_RTC_GET_PWRUP_TIMER		0x01 /* o: 7 bytes date */
-#define   SMU_CMD_RTC_STOP_PWRUP_TIMER		0x02
-#define   SMU_CMD_RTC_SET_PRAM_BYTE_ACC		0x20 /* i: 1 byte (address?) */
-#define   SMU_CMD_RTC_SET_PRAM_AUTOINC		0x21 /* i: 1 byte (data?) */
-#define   SMU_CMD_RTC_SET_PRAM_LO_BYTES 	0x22 /* i: 10 bytes */
-#define   SMU_CMD_RTC_SET_PRAM_HI_BYTES 	0x23 /* i: 10 bytes */
-#define   SMU_CMD_RTC_GET_PRAM_BYTE		0x28 /* i: 1 bytes (address?) */
-#define   SMU_CMD_RTC_GET_PRAM_LO_BYTES 	0x29 /* o: 10 bytes */
-#define   SMU_CMD_RTC_GET_PRAM_HI_BYTES 	0x2a /* o: 10 bytes */
-#define	  SMU_CMD_RTC_SET_DATETIME		0x80 /* i: 7 bytes date */
-#define   SMU_CMD_RTC_GET_DATETIME		0x81 /* o: 7 bytes date */
-
- /*
-  * i2c commands
-  *
-  * To issue an i2c command, first is to send a parameter block to the
-  * the SMU. This is a command of type 0x9a with 9 bytes of header
-  * eventually followed by data for a write:
-  *
-  * 0: bus number (from device-tree usually, SMU has lots of busses !)
-  * 1: transfer type/format (see below)
-  * 2: device address. For combined and combined4 type transfers, this
-  *    is the "write" version of the address (bit 0x01 cleared)
-  * 3: subaddress length (0..3)
-  * 4: subaddress byte 0 (or only byte for subaddress length 1)
-  * 5: subaddress byte 1
-  * 6: subaddress byte 2
-  * 7: combined address (device address for combined mode data phase)
-  * 8: data length
-  *
-  * The transfer types are the same good old Apple ones it seems,
-  * that is:
-  *   - 0x00: Simple transfer
-  *   - 0x01: Subaddress transfer (addr write + data tx, no restart)
-  *   - 0x02: Combined transfer (addr write + restart + data tx)
-  *
-  * This is then followed by actual data for a write.
-  *
-  * At this point, the OF driver seems to have a limitation on transfer
-  * sizes of 0xd bytes on reads and 0x5 bytes on writes. I do not know
-  * wether this is just an OF limit due to some temporary buffer size
-  * or if this is an SMU imposed limit. This driver has the same limitation
-  * for now as I use a 0x10 bytes temporary buffer as well
-  *
-  * Once that is completed, a response is expected from the SMU. This is
-  * obtained via a command of type 0x9a with a length of 1 byte containing
-  * 0 as the data byte. OF also fills the rest of the data buffer with 0xff's
-  * though I can't tell yet if this is actually necessary. Once this command
-  * is complete, at this point, all I can tell is what OF does. OF tests
-  * byte 0 of the reply:
-  *   - on read, 0xfe or 0xfc : bus is busy, wait (see below) or nak ?
-  *   - on read, 0x00 or 0x01 : reply is in buffer (after the byte 0)
-  *   - on write, < 0 -> failure (immediate exit)
-  *   - else, OF just exists (without error, weird)
-  *
-  * So on read, there is this wait-for-busy thing when getting a 0xfc or
-  * 0xfe result. OF does a loop of up to 64 retries, waiting 20ms and
-  * doing the above again until either the retries expire or the result
-  * is no longer 0xfe or 0xfc
-  *
-  * The Darwin I2C driver is less subtle though. On any non-success status
-  * from the response command, it waits 5ms and tries again up to 20 times,
-  * it doesn't differenciate between fatal errors or "busy" status.
-  *
-  * This driver provides an asynchronous paramblock based i2c command
-  * interface to be used either directly by low level code or by a higher
-  * level driver interfacing to the linux i2c layer. The current
-  * implementation of this relies on working timers & timer interrupts
-  * though, so be careful of calling context for now. This may be "fixed"
-  * in the future by adding a polling facility.
-  */
-#define SMU_CMD_I2C_COMMAND			0x9a
-          /* transfer types */
-#define   SMU_I2C_TRANSFER_SIMPLE	0x00
-#define   SMU_I2C_TRANSFER_STDSUB	0x01
-#define   SMU_I2C_TRANSFER_COMBINED	0x02
-
-/*
- * Power supply control
- *
- * The "sub" command is an ASCII string in the data, the
- * data length is that of the string.
- *
- * The VSLEW command can be used to get or set the voltage slewing.
- *  - length 5 (only "VSLEW") : it returns "DONE" and 3 bytes of
- *    reply at data offset 6, 7 and 8.
- *  - length 8 ("VSLEWxyz") has 3 additional bytes appended, and is
- *    used to set the voltage slewing point. The SMU replies with "DONE"
- * I yet have to figure out their exact meaning of those 3 bytes in
- * both cases. They seem to be:
- *  x = processor mask
- *  y = op. point index
- *  z = processor freq. step index
- * I haven't yet decyphered result codes
- *
- */
-#define SMU_CMD_POWER_COMMAND			0xaa
-#define   SMU_CMD_POWER_RESTART		       	"RESTART"
-#define   SMU_CMD_POWER_SHUTDOWN		"SHUTDOWN"
-#define   SMU_CMD_POWER_VOLTAGE_SLEW		"VSLEW"
-
-/*
- * Read ADC sensors
- *
- * This command takes one byte of parameter: the sensor ID (or "reg"
- * value in the device-tree) and returns a 16 bits value
- */
-#define SMU_CMD_READ_ADC			0xd8
-
-
-/* Misc commands
- *
- * This command seem to be a grab bag of various things
- *
- * Parameters:
- *   1: subcommand
- */
-#define SMU_CMD_MISC_df_COMMAND			0xdf
-
-/*
- * Sets "system ready" status
- *
- * I did not yet understand how it exactly works or what it does.
- *
- * Guessing from OF code, 0x02 activates the display backlight. Apple uses/used
- * the same codebase for all OF versions. On PowerBooks, this command would
- * enable the backlight. For the G5s, it only activates the front LED. However,
- * don't take this for granted.
- *
- * Parameters:
- *   2: status [0x00, 0x01 or 0x02]
- */
-#define   SMU_CMD_MISC_df_SET_DISPLAY_LIT	0x02
-
-/*
- * Sets mode of power switch.
- *
- * What this actually does is not yet known. Maybe it enables some interrupt.
- *
- * Parameters:
- *   2: enable power switch? [0x00 or 0x01]
- *   3 (optional): enable nmi? [0x00 or 0x01]
- *
- * Returns:
- *   If parameter 2 is 0x00 and parameter 3 is not specified, returns wether
- *   NMI is enabled. Otherwise unknown.
- */
-#define   SMU_CMD_MISC_df_NMI_OPTION		0x04
-
-/* Sets LED dimm offset.
- *
- * The front LED dimms itself during sleep. Its brightness (or, well, the PWM
- * frequency) depends on current time. Therefore, the SMU needs to know the
- * timezone.
- *
- * Parameters:
- *   2-8: unknown (BCD coding)
- */
-#define   SMU_CMD_MISC_df_DIMM_OFFSET		0x99
-
-
-/*
- * Version info commands
- *
- * Parameters:
- *   1 (optional): Specifies version part to retrieve
- *
- * Returns:
- *   Version value
- */
-#define SMU_CMD_VERSION_COMMAND			0xea
-#define   SMU_VERSION_RUNNING			0x00
-#define   SMU_VERSION_BASE			0x01
-#define   SMU_VERSION_UPDATE			0x02
-
-
-/*
- * Switches
- *
- * These are switches whose status seems to be known to the SMU.
- *
- * Parameters:
- *   none
- *
- * Result:
- *   Switch bits (ORed, see below)
- */
-#define SMU_CMD_SWITCHES			0xdc
-
-/* Switches bits */
-#define SMU_SWITCH_CASE_CLOSED			0x01
-#define SMU_SWITCH_AC_POWER			0x04
-#define SMU_SWITCH_POWER_SWITCH			0x08
-
-
-/*
- * Misc commands
- *
- * This command seem to be a grab bag of various things
- *
- * SMU_CMD_MISC_ee_GET_DATABLOCK_REC is used, among others, to
- * transfer blocks of data from the SMU. So far, I've decrypted it's
- * usage to retrieve partition data. In order to do that, you have to
- * break your transfer in "chunks" since that command cannot transfer
- * more than a chunk at a time. The chunk size used by OF is 0xe bytes,
- * but it seems that the darwin driver will let you do 0x1e bytes if
- * your "PMU" version is >= 0x30. You can get the "PMU" version apparently
- * either in the last 16 bits of property "smu-version-pmu" or as the 16
- * bytes at offset 1 of "smu-version-info"
- *
- * For each chunk, the command takes 7 bytes of arguments:
- *  byte 0: subcommand code (0x02)
- *  byte 1: 0x04 (always, I don't know what it means, maybe the address
- *                space to use or some other nicety. It's hard coded in OF)
- *  byte 2..5: SMU address of the chunk (big endian 32 bits)
- *  byte 6: size to transfer (up to max chunk size)
- *
- * The data is returned directly
- */
-#define SMU_CMD_MISC_ee_COMMAND			0xee
-#define   SMU_CMD_MISC_ee_GET_DATABLOCK_REC	0x02
-
-/* Retrieves currently used watts.
- *
- * Parameters:
- *   1: 0x03 (Meaning unknown)
- */
-#define   SMU_CMD_MISC_ee_GET_WATTS		0x03
-
-#define   SMU_CMD_MISC_ee_LEDS_CTRL		0x04 /* i: 00 (00,01) [00] */
-#define   SMU_CMD_MISC_ee_GET_DATA		0x05 /* i: 00 , o: ?? */
-
-
-/*
- * Power related commands
- *
- * Parameters:
- *   1: subcommand
- */
-#define SMU_CMD_POWER_EVENTS_COMMAND		0x8f
-
-/* SMU_POWER_EVENTS subcommands */
-enum {
-	SMU_PWR_GET_POWERUP_EVENTS      = 0x00,
-	SMU_PWR_SET_POWERUP_EVENTS      = 0x01,
-	SMU_PWR_CLR_POWERUP_EVENTS      = 0x02,
-	SMU_PWR_GET_WAKEUP_EVENTS       = 0x03,
-	SMU_PWR_SET_WAKEUP_EVENTS       = 0x04,
-	SMU_PWR_CLR_WAKEUP_EVENTS       = 0x05,
-
-	/*
-	 * Get last shutdown cause
-	 *
-	 * Returns:
-	 *   1 byte (signed char): Last shutdown cause. Exact meaning unknown.
-	 */
-	SMU_PWR_LAST_SHUTDOWN_CAUSE	= 0x07,
-
-	/*
-	 * Sets or gets server ID. Meaning or use is unknown.
-	 *
-	 * Parameters:
-	 *   2 (optional): Set server ID (1 byte)
-	 *
-	 * Returns:
-	 *   1 byte (server ID?)
-	 */
-	SMU_PWR_SERVER_ID		= 0x08,
-};
-
-/* Power events wakeup bits */
-enum {
-	SMU_PWR_WAKEUP_KEY              = 0x01, /* Wake on key press */
-	SMU_PWR_WAKEUP_AC_INSERT        = 0x02, /* Wake on AC adapter plug */
-	SMU_PWR_WAKEUP_AC_CHANGE        = 0x04,
-	SMU_PWR_WAKEUP_LID_OPEN         = 0x08,
-	SMU_PWR_WAKEUP_RING             = 0x10,
-};
-
-
-/*
- * - Kernel side interface -
- */
-
-#ifdef __KERNEL__
-
-/*
- * Asynchronous SMU commands
- *
- * Fill up this structure and submit it via smu_queue_command(),
- * and get notified by the optional done() callback, or because
- * status becomes != 1
- */
-
-struct smu_cmd;
-
-struct smu_cmd
-{
-	/* public */
-	u8			cmd;		/* command */
-	int			data_len;	/* data len */
-	int			reply_len;	/* reply len */
-	void			*data_buf;	/* data buffer */
-	void			*reply_buf;	/* reply buffer */
-	int			status;		/* command status */
-	void			(*done)(struct smu_cmd *cmd, void *misc);
-	void			*misc;
-
-	/* private */
-	struct list_head	link;
-};
-
-/*
- * Queues an SMU command, all fields have to be initialized
- */
-extern int smu_queue_cmd(struct smu_cmd *cmd);
-
-/*
- * Simple command wrapper. This structure embeds a small buffer
- * to ease sending simple SMU commands from the stack
- */
-struct smu_simple_cmd
-{
-	struct smu_cmd	cmd;
-	u8	       	buffer[16];
-};
-
-/*
- * Queues a simple command. All fields will be initialized by that
- * function
- */
-extern int smu_queue_simple(struct smu_simple_cmd *scmd, u8 command,
-			    unsigned int data_len,
-			    void (*done)(struct smu_cmd *cmd, void *misc),
-			    void *misc,
-			    ...);
-
-/*
- * Completion helper. Pass it to smu_queue_simple or as 'done'
- * member to smu_queue_cmd, it will call complete() on the struct
- * completion passed in the "misc" argument
- */
-extern void smu_done_complete(struct smu_cmd *cmd, void *misc);
-
-/*
- * Synchronous helpers. Will spin-wait for completion of a command
- */
-extern void smu_spinwait_cmd(struct smu_cmd *cmd);
-
-static inline void smu_spinwait_simple(struct smu_simple_cmd *scmd)
-{
-	smu_spinwait_cmd(&scmd->cmd);
-}
-
-/*
- * Poll routine to call if blocked with irqs off
- */
-extern void smu_poll(void);
-
-
-/*
- * Init routine, presence check....
- */
-extern int smu_init(void);
-extern int smu_present(void);
-struct platform_device;
-extern struct platform_device *smu_get_ofdev(void);
-
-
-/*
- * Common command wrappers
- */
-extern void smu_shutdown(void);
-extern void smu_restart(void);
-struct rtc_time;
-extern int smu_get_rtc_time(struct rtc_time *time, int spinwait);
-extern int smu_set_rtc_time(struct rtc_time *time, int spinwait);
-
-/*
- * SMU command buffer absolute address, exported by pmac_setup,
- * this is allocated very early during boot.
- */
-extern unsigned long smu_cmdbuf_abs;
-
-
-/*
- * Kenrel asynchronous i2c interface
- */
-
-#define SMU_I2C_READ_MAX	0x1d
-#define SMU_I2C_WRITE_MAX	0x15
-
-/* SMU i2c header, exactly matches i2c header on wire */
-struct smu_i2c_param
-{
-	u8	bus;		/* SMU bus ID (from device tree) */
-	u8	type;		/* i2c transfer type */
-	u8	devaddr;	/* device address (includes direction) */
-	u8	sublen;		/* subaddress length */
-	u8	subaddr[3];	/* subaddress */
-	u8	caddr;		/* combined address, filled by SMU driver */
-	u8	datalen;	/* length of transfer */
-	u8	data[SMU_I2C_READ_MAX];	/* data */
-};
-
-struct smu_i2c_cmd
-{
-	/* public */
-	struct smu_i2c_param	info;
-	void			(*done)(struct smu_i2c_cmd *cmd, void *misc);
-	void			*misc;
-	int			status; /* 1 = pending, 0 = ok, <0 = fail */
-
-	/* private */
-	struct smu_cmd		scmd;
-	int			read;
-	int			stage;
-	int			retries;
-	u8			pdata[32];
-	struct list_head	link;
-};
-
-/*
- * Call this to queue an i2c command to the SMU. You must fill info,
- * including info.data for a write, done and misc.
- * For now, no polling interface is provided so you have to use completion
- * callback.
- */
-extern int smu_queue_i2c(struct smu_i2c_cmd *cmd);
-
-
-#endif /* __KERNEL__ */
-
-
-/*
- * - SMU "sdb" partitions informations -
- */
-
-
-/*
- * Partition header format
- */
-struct smu_sdbp_header {
-	__u8	id;
-	__u8	len;
-	__u8	version;
-	__u8	flags;
-};
-
-
- /*
- * demangle 16 and 32 bits integer in some SMU partitions
- * (currently, afaik, this concerns only the FVT partition
- * (0x12)
- */
-#define SMU_U16_MIX(x)	le16_to_cpu(x)
-#define SMU_U32_MIX(x)  ((((x) & 0xff00ff00u) >> 8)|(((x) & 0x00ff00ffu) << 8))
-
-
-/* This is the definition of the SMU sdb-partition-0x12 table (called
- * CPU F/V/T operating points in Darwin). The definition for all those
- * SMU tables should be moved to some separate file
- */
-#define SMU_SDB_FVT_ID			0x12
-
-struct smu_sdbp_fvt {
-	__u32	sysclk;			/* Base SysClk frequency in Hz for
-					 * this operating point. Value need to
-					 * be unmixed with SMU_U32_MIX()
-					 */
-	__u8	pad;
-	__u8	maxtemp;		/* Max temp. supported by this
-					 * operating point
-					 */
-
-	__u16	volts[3];		/* CPU core voltage for the 3
-					 * PowerTune modes, a mode with
-					 * 0V = not supported. Value need
-					 * to be unmixed with SMU_U16_MIX()
-					 */
-};
-
-/* This partition contains voltage & current sensor calibration
- * informations
- */
-#define SMU_SDB_CPUVCP_ID		0x21
-
-struct smu_sdbp_cpuvcp {
-	__u16	volt_scale;		/* u4.12 fixed point */
-	__s16	volt_offset;		/* s4.12 fixed point */
-	__u16	curr_scale;		/* u4.12 fixed point */
-	__s16	curr_offset;		/* s4.12 fixed point */
-	__s32	power_quads[3];		/* s4.28 fixed point */
-};
-
-/* This partition contains CPU thermal diode calibration
- */
-#define SMU_SDB_CPUDIODE_ID		0x18
-
-struct smu_sdbp_cpudiode {
-	__u16	m_value;		/* u1.15 fixed point */
-	__s16	b_value;		/* s10.6 fixed point */
-
-};
-
-/* This partition contains Slots power calibration
- */
-#define SMU_SDB_SLOTSPOW_ID		0x78
-
-struct smu_sdbp_slotspow {
-	__u16	pow_scale;		/* u4.12 fixed point */
-	__s16	pow_offset;		/* s4.12 fixed point */
-};
-
-/* This partition contains machine specific version information about
- * the sensor/control layout
- */
-#define SMU_SDB_SENSORTREE_ID		0x25
-
-struct smu_sdbp_sensortree {
-	__u8	model_id;
-	__u8	unknown[3];
-};
-
-/* This partition contains CPU thermal control PID informations. So far
- * only single CPU machines have been seen with an SMU, so we assume this
- * carries only informations for those
- */
-#define SMU_SDB_CPUPIDDATA_ID		0x17
-
-struct smu_sdbp_cpupiddata {
-	__u8	unknown1;
-	__u8	target_temp_delta;
-	__u8	unknown2;
-	__u8	history_len;
-	__s16	power_adj;
-	__u16	max_power;
-	__s32	gp,gr,gd;
-};
-
-
-/* Other partitions without known structures */
-#define SMU_SDB_DEBUG_SWITCHES_ID	0x05
-
-#ifdef __KERNEL__
-/*
- * This returns the pointer to an SMU "sdb" partition data or NULL
- * if not found. The data format is described below
- */
-extern const struct smu_sdbp_header *smu_get_sdb_partition(int id,
-					unsigned int *size);
-
-/* Get "sdb" partition data from an SMU satellite */
-extern struct smu_sdbp_header *smu_sat_get_sdb_partition(unsigned int sat_id,
-					int id, unsigned int *size);
-
-
-#endif /* __KERNEL__ */
-
-
-/*
- * - Userland interface -
- */
-
-/*
- * A given instance of the device can be configured for 2 different
- * things at the moment:
- *
- *  - sending SMU commands (default at open() time)
- *  - receiving SMU events (not yet implemented)
- *
- * Commands are written with write() of a command block. They can be
- * "driver" commands (for example to switch to event reception mode)
- * or real SMU commands. They are made of a header followed by command
- * data if any.
- *
- * For SMU commands (not for driver commands), you can then read() back
- * a reply. The reader will be blocked or not depending on how the device
- * file is opened. poll() isn't implemented yet. The reply will consist
- * of a header as well, followed by the reply data if any. You should
- * always provide a buffer large enough for the maximum reply data, I
- * recommand one page.
- *
- * It is illegal to send SMU commands through a file descriptor configured
- * for events reception
- *
- */
-struct smu_user_cmd_hdr
-{
-	__u32		cmdtype;
-#define SMU_CMDTYPE_SMU			0	/* SMU command */
-#define SMU_CMDTYPE_WANTS_EVENTS	1	/* switch fd to events mode */
-#define SMU_CMDTYPE_GET_PARTITION	2	/* retrieve an sdb partition */
-
-	__u8		cmd;			/* SMU command byte */
-	__u8		pad[3];			/* padding */
-	__u32		data_len;		/* Length of data following */
-};
-
-struct smu_user_reply_hdr
-{
-	__u32		status;			/* Command status */
-	__u32		reply_len;		/* Length of data follwing */
-};
-
-#endif /*  _SMU_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/socket.h b/ANDROID_3.4.5/arch/powerpc/include/asm/socket.h
deleted file mode 100644
index 3d5179bb..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/socket.h
+++ /dev/null
@@ -1,79 +0,0 @@
-#ifndef _ASM_POWERPC_SOCKET_H
-#define _ASM_POWERPC_SOCKET_H
-
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <asm/sockios.h>
-
-/* For setsockopt(2) */
-#define SOL_SOCKET	1
-
-#define SO_DEBUG	1
-#define SO_REUSEADDR	2
-#define SO_TYPE		3
-#define SO_ERROR	4
-#define SO_DONTROUTE	5
-#define SO_BROADCAST	6
-#define SO_SNDBUF	7
-#define SO_RCVBUF	8
-#define SO_SNDBUFFORCE	32
-#define SO_RCVBUFFORCE	33
-#define SO_KEEPALIVE	9
-#define SO_OOBINLINE	10
-#define SO_NO_CHECK	11
-#define SO_PRIORITY	12
-#define SO_LINGER	13
-#define SO_BSDCOMPAT	14
-/* To add :#define SO_REUSEPORT 15 */
-#define SO_RCVLOWAT	16
-#define SO_SNDLOWAT	17
-#define SO_RCVTIMEO	18
-#define SO_SNDTIMEO	19
-#define SO_PASSCRED	20
-#define SO_PEERCRED	21
-
-/* Security levels - as per NRL IPv6 - don't actually do anything */
-#define SO_SECURITY_AUTHENTICATION		22
-#define SO_SECURITY_ENCRYPTION_TRANSPORT	23
-#define SO_SECURITY_ENCRYPTION_NETWORK		24
-
-#define SO_BINDTODEVICE	25
-
-/* Socket filtering */
-#define SO_ATTACH_FILTER	26
-#define SO_DETACH_FILTER	27
-
-#define SO_PEERNAME		28
-#define SO_TIMESTAMP		29
-#define SCM_TIMESTAMP		SO_TIMESTAMP
-
-#define SO_ACCEPTCONN		30
-
-#define SO_PEERSEC		31
-#define SO_PASSSEC		34
-#define SO_TIMESTAMPNS		35
-#define SCM_TIMESTAMPNS		SO_TIMESTAMPNS
-
-#define SO_MARK			36
-
-#define SO_TIMESTAMPING		37
-#define SCM_TIMESTAMPING	SO_TIMESTAMPING
-
-#define SO_PROTOCOL		38
-#define SO_DOMAIN		39
-
-#define SO_RXQ_OVFL             40
-
-#define SO_WIFI_STATUS		41
-#define SCM_WIFI_STATUS		SO_WIFI_STATUS
-#define SO_PEEK_OFF		42
-
-/* Instruct lower device to use last 4-bytes of skb data as FCS */
-#define SO_NOFCS		43
-
-#endif	/* _ASM_POWERPC_SOCKET_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/sockios.h b/ANDROID_3.4.5/arch/powerpc/include/asm/sockios.h
deleted file mode 100644
index 55cef767..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/sockios.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef _ASM_POWERPC_SOCKIOS_H
-#define _ASM_POWERPC_SOCKIOS_H
-
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-/* Socket-level I/O control calls. */
-#define FIOSETOWN 	0x8901
-#define SIOCSPGRP	0x8902
-#define FIOGETOWN	0x8903
-#define SIOCGPGRP	0x8904
-#define SIOCATMARK	0x8905
-#define SIOCGSTAMP	0x8906		/* Get stamp (timeval) */
-#define SIOCGSTAMPNS	0x8907		/* Get stamp (timespec) */
-
-#endif	/* _ASM_POWERPC_SOCKIOS_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/sparsemem.h b/ANDROID_3.4.5/arch/powerpc/include/asm/sparsemem.h
deleted file mode 100644
index 0c5fa314..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/sparsemem.h
+++ /dev/null
@@ -1,32 +0,0 @@
-#ifndef _ASM_POWERPC_SPARSEMEM_H
-#define _ASM_POWERPC_SPARSEMEM_H 1
-#ifdef __KERNEL__
-
-#ifdef CONFIG_SPARSEMEM
-/*
- * SECTION_SIZE_BITS		2^N: how big each section will be
- * MAX_PHYSADDR_BITS		2^N: how much physical address space we have
- * MAX_PHYSMEM_BITS		2^N: how much memory we can have in that space
- */
-#define SECTION_SIZE_BITS       24
-
-#define MAX_PHYSADDR_BITS       44
-#define MAX_PHYSMEM_BITS        44
-
-#endif /* CONFIG_SPARSEMEM */
-
-#ifdef CONFIG_MEMORY_HOTPLUG
-extern int create_section_mapping(unsigned long start, unsigned long end);
-extern int remove_section_mapping(unsigned long start, unsigned long end);
-#ifdef CONFIG_NUMA
-extern int hot_add_scn_to_nid(unsigned long scn_addr);
-#else
-static inline int hot_add_scn_to_nid(unsigned long scn_addr)
-{
-	return 0;
-}
-#endif /* CONFIG_NUMA */
-#endif /* CONFIG_MEMORY_HOTPLUG */
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_SPARSEMEM_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/spinlock.h b/ANDROID_3.4.5/arch/powerpc/include/asm/spinlock.h
deleted file mode 100644
index 7124fc06..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/spinlock.h
+++ /dev/null
@@ -1,299 +0,0 @@
-#ifndef __ASM_SPINLOCK_H
-#define __ASM_SPINLOCK_H
-#ifdef __KERNEL__
-
-/*
- * Simple spin lock operations.  
- *
- * Copyright (C) 2001-2004 Paul Mackerras <paulus@au.ibm.com>, IBM
- * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
- * Copyright (C) 2002 Dave Engebretsen <engebret@us.ibm.com>, IBM
- *	Rework to support virtual processors
- *
- * Type of int is used as a full 64b word is not necessary.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- *
- * (the type definitions are in asm/spinlock_types.h)
- */
-#include <linux/irqflags.h>
-#ifdef CONFIG_PPC64
-#include <asm/paca.h>
-#include <asm/hvcall.h>
-#endif
-#include <asm/asm-compat.h>
-#include <asm/synch.h>
-#include <asm/ppc-opcode.h>
-
-#define arch_spin_is_locked(x)		((x)->slock != 0)
-
-#ifdef CONFIG_PPC64
-/* use 0x800000yy when locked, where yy == CPU number */
-#define LOCK_TOKEN	(*(u32 *)(&get_paca()->lock_token))
-#else
-#define LOCK_TOKEN	1
-#endif
-
-#if defined(CONFIG_PPC64) && defined(CONFIG_SMP)
-#define CLEAR_IO_SYNC	(get_paca()->io_sync = 0)
-#define SYNC_IO		do {						\
-				if (unlikely(get_paca()->io_sync)) {	\
-					mb();				\
-					get_paca()->io_sync = 0;	\
-				}					\
-			} while (0)
-#else
-#define CLEAR_IO_SYNC
-#define SYNC_IO
-#endif
-
-/*
- * This returns the old value in the lock, so we succeeded
- * in getting the lock if the return value is 0.
- */
-static inline unsigned long __arch_spin_trylock(arch_spinlock_t *lock)
-{
-	unsigned long tmp, token;
-
-	token = LOCK_TOKEN;
-	__asm__ __volatile__(
-"1:	" PPC_LWARX(%0,0,%2,1) "\n\
-	cmpwi		0,%0,0\n\
-	bne-		2f\n\
-	stwcx.		%1,0,%2\n\
-	bne-		1b\n"
-	PPC_ACQUIRE_BARRIER
-"2:"
-	: "=&r" (tmp)
-	: "r" (token), "r" (&lock->slock)
-	: "cr0", "memory");
-
-	return tmp;
-}
-
-static inline int arch_spin_trylock(arch_spinlock_t *lock)
-{
-	CLEAR_IO_SYNC;
-	return __arch_spin_trylock(lock) == 0;
-}
-
-/*
- * On a system with shared processors (that is, where a physical
- * processor is multiplexed between several virtual processors),
- * there is no point spinning on a lock if the holder of the lock
- * isn't currently scheduled on a physical processor.  Instead
- * we detect this situation and ask the hypervisor to give the
- * rest of our timeslice to the lock holder.
- *
- * So that we can tell which virtual processor is holding a lock,
- * we put 0x80000000 | smp_processor_id() in the lock when it is
- * held.  Conveniently, we have a word in the paca that holds this
- * value.
- */
-
-#if defined(CONFIG_PPC_SPLPAR)
-/* We only yield to the hypervisor if we are in shared processor mode */
-#define SHARED_PROCESSOR (get_lppaca()->shared_proc)
-extern void __spin_yield(arch_spinlock_t *lock);
-extern void __rw_yield(arch_rwlock_t *lock);
-#else /* SPLPAR */
-#define __spin_yield(x)	barrier()
-#define __rw_yield(x)	barrier()
-#define SHARED_PROCESSOR	0
-#endif
-
-static inline void arch_spin_lock(arch_spinlock_t *lock)
-{
-	CLEAR_IO_SYNC;
-	while (1) {
-		if (likely(__arch_spin_trylock(lock) == 0))
-			break;
-		do {
-			HMT_low();
-			if (SHARED_PROCESSOR)
-				__spin_yield(lock);
-		} while (unlikely(lock->slock != 0));
-		HMT_medium();
-	}
-}
-
-static inline
-void arch_spin_lock_flags(arch_spinlock_t *lock, unsigned long flags)
-{
-	unsigned long flags_dis;
-
-	CLEAR_IO_SYNC;
-	while (1) {
-		if (likely(__arch_spin_trylock(lock) == 0))
-			break;
-		local_save_flags(flags_dis);
-		local_irq_restore(flags);
-		do {
-			HMT_low();
-			if (SHARED_PROCESSOR)
-				__spin_yield(lock);
-		} while (unlikely(lock->slock != 0));
-		HMT_medium();
-		local_irq_restore(flags_dis);
-	}
-}
-
-static inline void arch_spin_unlock(arch_spinlock_t *lock)
-{
-	SYNC_IO;
-	__asm__ __volatile__("# arch_spin_unlock\n\t"
-				PPC_RELEASE_BARRIER: : :"memory");
-	lock->slock = 0;
-}
-
-#ifdef CONFIG_PPC64
-extern void arch_spin_unlock_wait(arch_spinlock_t *lock);
-#else
-#define arch_spin_unlock_wait(lock) \
-	do { while (arch_spin_is_locked(lock)) cpu_relax(); } while (0)
-#endif
-
-/*
- * Read-write spinlocks, allowing multiple readers
- * but only one writer.
- *
- * NOTE! it is quite common to have readers in interrupts
- * but no interrupt writers. For those circumstances we
- * can "mix" irq-safe locks - any writer needs to get a
- * irq-safe write-lock, but readers can get non-irqsafe
- * read-locks.
- */
-
-#define arch_read_can_lock(rw)		((rw)->lock >= 0)
-#define arch_write_can_lock(rw)	(!(rw)->lock)
-
-#ifdef CONFIG_PPC64
-#define __DO_SIGN_EXTEND	"extsw	%0,%0\n"
-#define WRLOCK_TOKEN		LOCK_TOKEN	/* it's negative */
-#else
-#define __DO_SIGN_EXTEND
-#define WRLOCK_TOKEN		(-1)
-#endif
-
-/*
- * This returns the old value in the lock + 1,
- * so we got a read lock if the return value is > 0.
- */
-static inline long __arch_read_trylock(arch_rwlock_t *rw)
-{
-	long tmp;
-
-	__asm__ __volatile__(
-"1:	" PPC_LWARX(%0,0,%1,1) "\n"
-	__DO_SIGN_EXTEND
-"	addic.		%0,%0,1\n\
-	ble-		2f\n"
-	PPC405_ERR77(0,%1)
-"	stwcx.		%0,0,%1\n\
-	bne-		1b\n"
-	PPC_ACQUIRE_BARRIER
-"2:"	: "=&r" (tmp)
-	: "r" (&rw->lock)
-	: "cr0", "xer", "memory");
-
-	return tmp;
-}
-
-/*
- * This returns the old value in the lock,
- * so we got the write lock if the return value is 0.
- */
-static inline long __arch_write_trylock(arch_rwlock_t *rw)
-{
-	long tmp, token;
-
-	token = WRLOCK_TOKEN;
-	__asm__ __volatile__(
-"1:	" PPC_LWARX(%0,0,%2,1) "\n\
-	cmpwi		0,%0,0\n\
-	bne-		2f\n"
-	PPC405_ERR77(0,%1)
-"	stwcx.		%1,0,%2\n\
-	bne-		1b\n"
-	PPC_ACQUIRE_BARRIER
-"2:"	: "=&r" (tmp)
-	: "r" (token), "r" (&rw->lock)
-	: "cr0", "memory");
-
-	return tmp;
-}
-
-static inline void arch_read_lock(arch_rwlock_t *rw)
-{
-	while (1) {
-		if (likely(__arch_read_trylock(rw) > 0))
-			break;
-		do {
-			HMT_low();
-			if (SHARED_PROCESSOR)
-				__rw_yield(rw);
-		} while (unlikely(rw->lock < 0));
-		HMT_medium();
-	}
-}
-
-static inline void arch_write_lock(arch_rwlock_t *rw)
-{
-	while (1) {
-		if (likely(__arch_write_trylock(rw) == 0))
-			break;
-		do {
-			HMT_low();
-			if (SHARED_PROCESSOR)
-				__rw_yield(rw);
-		} while (unlikely(rw->lock != 0));
-		HMT_medium();
-	}
-}
-
-static inline int arch_read_trylock(arch_rwlock_t *rw)
-{
-	return __arch_read_trylock(rw) > 0;
-}
-
-static inline int arch_write_trylock(arch_rwlock_t *rw)
-{
-	return __arch_write_trylock(rw) == 0;
-}
-
-static inline void arch_read_unlock(arch_rwlock_t *rw)
-{
-	long tmp;
-
-	__asm__ __volatile__(
-	"# read_unlock\n\t"
-	PPC_RELEASE_BARRIER
-"1:	lwarx		%0,0,%1\n\
-	addic		%0,%0,-1\n"
-	PPC405_ERR77(0,%1)
-"	stwcx.		%0,0,%1\n\
-	bne-		1b"
-	: "=&r"(tmp)
-	: "r"(&rw->lock)
-	: "cr0", "xer", "memory");
-}
-
-static inline void arch_write_unlock(arch_rwlock_t *rw)
-{
-	__asm__ __volatile__("# write_unlock\n\t"
-				PPC_RELEASE_BARRIER: : :"memory");
-	rw->lock = 0;
-}
-
-#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
-#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
-
-#define arch_spin_relax(lock)	__spin_yield(lock)
-#define arch_read_relax(lock)	__rw_yield(lock)
-#define arch_write_relax(lock)	__rw_yield(lock)
-
-#endif /* __KERNEL__ */
-#endif /* __ASM_SPINLOCK_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/spinlock_types.h b/ANDROID_3.4.5/arch/powerpc/include/asm/spinlock_types.h
deleted file mode 100644
index 2351adc4..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/spinlock_types.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef _ASM_POWERPC_SPINLOCK_TYPES_H
-#define _ASM_POWERPC_SPINLOCK_TYPES_H
-
-#ifndef __LINUX_SPINLOCK_TYPES_H
-# error "please don't include this file directly"
-#endif
-
-typedef struct {
-	volatile unsigned int slock;
-} arch_spinlock_t;
-
-#define __ARCH_SPIN_LOCK_UNLOCKED	{ 0 }
-
-typedef struct {
-	volatile signed int lock;
-} arch_rwlock_t;
-
-#define __ARCH_RW_LOCK_UNLOCKED		{ 0 }
-
-#endif
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/spu.h b/ANDROID_3.4.5/arch/powerpc/include/asm/spu.h
deleted file mode 100644
index 93f280e2..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/spu.h
+++ /dev/null
@@ -1,725 +0,0 @@
-/*
- * SPU core / file system interface and HW structures
- *
- * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
- *
- * Author: Arnd Bergmann <arndb@de.ibm.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef _SPU_H
-#define _SPU_H
-#ifdef __KERNEL__
-
-#include <linux/workqueue.h>
-#include <linux/device.h>
-#include <linux/mutex.h>
-
-#define LS_SIZE (256 * 1024)
-#define LS_ADDR_MASK (LS_SIZE - 1)
-
-#define MFC_PUT_CMD             0x20
-#define MFC_PUTS_CMD            0x28
-#define MFC_PUTR_CMD            0x30
-#define MFC_PUTF_CMD            0x22
-#define MFC_PUTB_CMD            0x21
-#define MFC_PUTFS_CMD           0x2A
-#define MFC_PUTBS_CMD           0x29
-#define MFC_PUTRF_CMD           0x32
-#define MFC_PUTRB_CMD           0x31
-#define MFC_PUTL_CMD            0x24
-#define MFC_PUTRL_CMD           0x34
-#define MFC_PUTLF_CMD           0x26
-#define MFC_PUTLB_CMD           0x25
-#define MFC_PUTRLF_CMD          0x36
-#define MFC_PUTRLB_CMD          0x35
-
-#define MFC_GET_CMD             0x40
-#define MFC_GETS_CMD            0x48
-#define MFC_GETF_CMD            0x42
-#define MFC_GETB_CMD            0x41
-#define MFC_GETFS_CMD           0x4A
-#define MFC_GETBS_CMD           0x49
-#define MFC_GETL_CMD            0x44
-#define MFC_GETLF_CMD           0x46
-#define MFC_GETLB_CMD           0x45
-
-#define MFC_SDCRT_CMD           0x80
-#define MFC_SDCRTST_CMD         0x81
-#define MFC_SDCRZ_CMD           0x89
-#define MFC_SDCRS_CMD           0x8D
-#define MFC_SDCRF_CMD           0x8F
-
-#define MFC_GETLLAR_CMD         0xD0
-#define MFC_PUTLLC_CMD          0xB4
-#define MFC_PUTLLUC_CMD         0xB0
-#define MFC_PUTQLLUC_CMD        0xB8
-#define MFC_SNDSIG_CMD          0xA0
-#define MFC_SNDSIGB_CMD         0xA1
-#define MFC_SNDSIGF_CMD         0xA2
-#define MFC_BARRIER_CMD         0xC0
-#define MFC_EIEIO_CMD           0xC8
-#define MFC_SYNC_CMD            0xCC
-
-#define MFC_MIN_DMA_SIZE_SHIFT  4       /* 16 bytes */
-#define MFC_MAX_DMA_SIZE_SHIFT  14      /* 16384 bytes */
-#define MFC_MIN_DMA_SIZE        (1 << MFC_MIN_DMA_SIZE_SHIFT)
-#define MFC_MAX_DMA_SIZE        (1 << MFC_MAX_DMA_SIZE_SHIFT)
-#define MFC_MIN_DMA_SIZE_MASK   (MFC_MIN_DMA_SIZE - 1)
-#define MFC_MAX_DMA_SIZE_MASK   (MFC_MAX_DMA_SIZE - 1)
-#define MFC_MIN_DMA_LIST_SIZE   0x0008  /*   8 bytes */
-#define MFC_MAX_DMA_LIST_SIZE   0x4000  /* 16K bytes */
-
-#define MFC_TAGID_TO_TAGMASK(tag_id)  (1 << (tag_id & 0x1F))
-
-/* Events for Channels 0-2 */
-#define MFC_DMA_TAG_STATUS_UPDATE_EVENT     0x00000001
-#define MFC_DMA_TAG_CMD_STALL_NOTIFY_EVENT  0x00000002
-#define MFC_DMA_QUEUE_AVAILABLE_EVENT       0x00000008
-#define MFC_SPU_MAILBOX_WRITTEN_EVENT       0x00000010
-#define MFC_DECREMENTER_EVENT               0x00000020
-#define MFC_PU_INT_MAILBOX_AVAILABLE_EVENT  0x00000040
-#define MFC_PU_MAILBOX_AVAILABLE_EVENT      0x00000080
-#define MFC_SIGNAL_2_EVENT                  0x00000100
-#define MFC_SIGNAL_1_EVENT                  0x00000200
-#define MFC_LLR_LOST_EVENT                  0x00000400
-#define MFC_PRIV_ATTN_EVENT                 0x00000800
-#define MFC_MULTI_SRC_EVENT                 0x00001000
-
-/* Flag indicating progress during context switch. */
-#define SPU_CONTEXT_SWITCH_PENDING	0UL
-#define SPU_CONTEXT_FAULT_PENDING	1UL
-
-struct spu_context;
-struct spu_runqueue;
-struct spu_lscsa;
-struct device_node;
-
-enum spu_utilization_state {
-	SPU_UTIL_USER,
-	SPU_UTIL_SYSTEM,
-	SPU_UTIL_IOWAIT,
-	SPU_UTIL_IDLE_LOADED,
-	SPU_UTIL_MAX
-};
-
-struct spu {
-	const char *name;
-	unsigned long local_store_phys;
-	u8 *local_store;
-	unsigned long problem_phys;
-	struct spu_problem __iomem *problem;
-	struct spu_priv2 __iomem *priv2;
-	struct list_head cbe_list;
-	struct list_head full_list;
-	enum { SPU_FREE, SPU_USED } alloc_state;
-	int number;
-	unsigned int irqs[3];
-	u32 node;
-	unsigned long flags;
-	u64 class_0_pending;
-	u64 class_0_dar;
-	u64 class_1_dar;
-	u64 class_1_dsisr;
-	size_t ls_size;
-	unsigned int slb_replace;
-	struct mm_struct *mm;
-	struct spu_context *ctx;
-	struct spu_runqueue *rq;
-	unsigned long long timestamp;
-	pid_t pid;
-	pid_t tgid;
-	spinlock_t register_lock;
-
-	void (* wbox_callback)(struct spu *spu);
-	void (* ibox_callback)(struct spu *spu);
-	void (* stop_callback)(struct spu *spu, int irq);
-	void (* mfc_callback)(struct spu *spu);
-
-	char irq_c0[8];
-	char irq_c1[8];
-	char irq_c2[8];
-
-	u64 spe_id;
-
-	void* pdata; /* platform private data */
-
-	/* of based platforms only */
-	struct device_node *devnode;
-
-	/* native only */
-	struct spu_priv1 __iomem *priv1;
-
-	/* beat only */
-	u64 shadow_int_mask_RW[3];
-
-	struct device dev;
-
-	int has_mem_affinity;
-	struct list_head aff_list;
-
-	struct {
-		/* protected by interrupt reentrancy */
-		enum spu_utilization_state util_state;
-		unsigned long long tstamp;
-		unsigned long long times[SPU_UTIL_MAX];
-		unsigned long long vol_ctx_switch;
-		unsigned long long invol_ctx_switch;
-		unsigned long long min_flt;
-		unsigned long long maj_flt;
-		unsigned long long hash_flt;
-		unsigned long long slb_flt;
-		unsigned long long class2_intr;
-		unsigned long long libassist;
-	} stats;
-};
-
-struct cbe_spu_info {
-	struct mutex list_mutex;
-	struct list_head spus;
-	int n_spus;
-	int nr_active;
-	atomic_t busy_spus;
-	atomic_t reserved_spus;
-};
-
-extern struct cbe_spu_info cbe_spu_info[];
-
-void spu_init_channels(struct spu *spu);
-void spu_irq_setaffinity(struct spu *spu, int cpu);
-
-void spu_setup_kernel_slbs(struct spu *spu, struct spu_lscsa *lscsa,
-		void *code, int code_size);
-
-extern void spu_invalidate_slbs(struct spu *spu);
-extern void spu_associate_mm(struct spu *spu, struct mm_struct *mm);
-int spu_64k_pages_available(void);
-
-/* Calls from the memory management to the SPU */
-struct mm_struct;
-extern void spu_flush_all_slbs(struct mm_struct *mm);
-
-/* This interface allows a profiler (e.g., OProfile) to store a ref
- * to spu context information that it creates.	This caching technique
- * avoids the need to recreate this information after a save/restore operation.
- *
- * Assumes the caller has already incremented the ref count to
- * profile_info; then spu_context_destroy must call kref_put
- * on prof_info_kref.
- */
-void spu_set_profile_private_kref(struct spu_context *ctx,
-				  struct kref *prof_info_kref,
-				  void ( * prof_info_release) (struct kref *kref));
-
-void *spu_get_profile_private_kref(struct spu_context *ctx);
-
-/* system callbacks from the SPU */
-struct spu_syscall_block {
-	u64 nr_ret;
-	u64 parm[6];
-};
-extern long spu_sys_callback(struct spu_syscall_block *s);
-
-/* syscalls implemented in spufs */
-struct file;
-struct spufs_calls {
-	long (*create_thread)(const char __user *name,
-					unsigned int flags, umode_t mode,
-					struct file *neighbor);
-	long (*spu_run)(struct file *filp, __u32 __user *unpc,
-						__u32 __user *ustatus);
-	int (*coredump_extra_notes_size)(void);
-	int (*coredump_extra_notes_write)(struct file *file, loff_t *foffset);
-	void (*notify_spus_active)(void);
-	struct module *owner;
-};
-
-/* return status from spu_run, same as in libspe */
-#define SPE_EVENT_DMA_ALIGNMENT		0x0008	/*A DMA alignment error */
-#define SPE_EVENT_SPE_ERROR		0x0010	/*An illegal instruction error*/
-#define SPE_EVENT_SPE_DATA_SEGMENT	0x0020	/*A DMA segmentation error    */
-#define SPE_EVENT_SPE_DATA_STORAGE	0x0040	/*A DMA storage error */
-#define SPE_EVENT_INVALID_DMA		0x0800	/* Invalid MFC DMA */
-
-/*
- * Flags for sys_spu_create.
- */
-#define SPU_CREATE_EVENTS_ENABLED	0x0001
-#define SPU_CREATE_GANG			0x0002
-#define SPU_CREATE_NOSCHED		0x0004
-#define SPU_CREATE_ISOLATE		0x0008
-#define SPU_CREATE_AFFINITY_SPU		0x0010
-#define SPU_CREATE_AFFINITY_MEM		0x0020
-
-#define SPU_CREATE_FLAG_ALL		0x003f /* mask of all valid flags */
-
-
-int register_spu_syscalls(struct spufs_calls *calls);
-void unregister_spu_syscalls(struct spufs_calls *calls);
-
-int spu_add_dev_attr(struct device_attribute *attr);
-void spu_remove_dev_attr(struct device_attribute *attr);
-
-int spu_add_dev_attr_group(struct attribute_group *attrs);
-void spu_remove_dev_attr_group(struct attribute_group *attrs);
-
-int spu_handle_mm_fault(struct mm_struct *mm, unsigned long ea,
-		unsigned long dsisr, unsigned *flt);
-
-/*
- * Notifier blocks:
- *
- * oprofile can get notified when a context switch is performed
- * on an spe. The notifer function that gets called is passed
- * a pointer to the SPU structure as well as the object-id that
- * identifies the binary running on that SPU now.
- *
- * For a context save, the object-id that is passed is zero,
- * identifying that the kernel will run from that moment on.
- *
- * For a context restore, the object-id is the value written
- * to object-id spufs file from user space and the notifer
- * function can assume that spu->ctx is valid.
- */
-struct notifier_block;
-int spu_switch_event_register(struct notifier_block * n);
-int spu_switch_event_unregister(struct notifier_block * n);
-
-extern void notify_spus_active(void);
-extern void do_notify_spus_active(void);
-
-/*
- * This defines the Local Store, Problem Area and Privilege Area of an SPU.
- */
-
-union mfc_tag_size_class_cmd {
-	struct {
-		u16 mfc_size;
-		u16 mfc_tag;
-		u8  pad;
-		u8  mfc_rclassid;
-		u16 mfc_cmd;
-	} u;
-	struct {
-		u32 mfc_size_tag32;
-		u32 mfc_class_cmd32;
-	} by32;
-	u64 all64;
-};
-
-struct mfc_cq_sr {
-	u64 mfc_cq_data0_RW;
-	u64 mfc_cq_data1_RW;
-	u64 mfc_cq_data2_RW;
-	u64 mfc_cq_data3_RW;
-};
-
-struct spu_problem {
-#define MS_SYNC_PENDING         1L
-	u64 spc_mssync_RW;					/* 0x0000 */
-	u8  pad_0x0008_0x3000[0x3000 - 0x0008];
-
-	/* DMA Area */
-	u8  pad_0x3000_0x3004[0x4];				/* 0x3000 */
-	u32 mfc_lsa_W;						/* 0x3004 */
-	u64 mfc_ea_W;						/* 0x3008 */
-	union mfc_tag_size_class_cmd mfc_union_W;			/* 0x3010 */
-	u8  pad_0x3018_0x3104[0xec];				/* 0x3018 */
-	u32 dma_qstatus_R;					/* 0x3104 */
-	u8  pad_0x3108_0x3204[0xfc];				/* 0x3108 */
-	u32 dma_querytype_RW;					/* 0x3204 */
-	u8  pad_0x3208_0x321c[0x14];				/* 0x3208 */
-	u32 dma_querymask_RW;					/* 0x321c */
-	u8  pad_0x3220_0x322c[0xc];				/* 0x3220 */
-	u32 dma_tagstatus_R;					/* 0x322c */
-#define DMA_TAGSTATUS_INTR_ANY	1u
-#define DMA_TAGSTATUS_INTR_ALL	2u
-	u8  pad_0x3230_0x4000[0x4000 - 0x3230]; 		/* 0x3230 */
-
-	/* SPU Control Area */
-	u8  pad_0x4000_0x4004[0x4];				/* 0x4000 */
-	u32 pu_mb_R;						/* 0x4004 */
-	u8  pad_0x4008_0x400c[0x4];				/* 0x4008 */
-	u32 spu_mb_W;						/* 0x400c */
-	u8  pad_0x4010_0x4014[0x4];				/* 0x4010 */
-	u32 mb_stat_R;						/* 0x4014 */
-	u8  pad_0x4018_0x401c[0x4];				/* 0x4018 */
-	u32 spu_runcntl_RW;					/* 0x401c */
-#define SPU_RUNCNTL_STOP	0L
-#define SPU_RUNCNTL_RUNNABLE	1L
-#define SPU_RUNCNTL_ISOLATE	2L
-	u8  pad_0x4020_0x4024[0x4];				/* 0x4020 */
-	u32 spu_status_R;					/* 0x4024 */
-#define SPU_STOP_STATUS_SHIFT           16
-#define SPU_STATUS_STOPPED		0x0
-#define SPU_STATUS_RUNNING		0x1
-#define SPU_STATUS_STOPPED_BY_STOP	0x2
-#define SPU_STATUS_STOPPED_BY_HALT	0x4
-#define SPU_STATUS_WAITING_FOR_CHANNEL	0x8
-#define SPU_STATUS_SINGLE_STEP		0x10
-#define SPU_STATUS_INVALID_INSTR        0x20
-#define SPU_STATUS_INVALID_CH           0x40
-#define SPU_STATUS_ISOLATED_STATE       0x80
-#define SPU_STATUS_ISOLATED_LOAD_STATUS 0x200
-#define SPU_STATUS_ISOLATED_EXIT_STATUS 0x400
-	u8  pad_0x4028_0x402c[0x4];				/* 0x4028 */
-	u32 spu_spe_R;						/* 0x402c */
-	u8  pad_0x4030_0x4034[0x4];				/* 0x4030 */
-	u32 spu_npc_RW;						/* 0x4034 */
-	u8  pad_0x4038_0x14000[0x14000 - 0x4038];		/* 0x4038 */
-
-	/* Signal Notification Area */
-	u8  pad_0x14000_0x1400c[0xc];				/* 0x14000 */
-	u32 signal_notify1;					/* 0x1400c */
-	u8  pad_0x14010_0x1c00c[0x7ffc];			/* 0x14010 */
-	u32 signal_notify2;					/* 0x1c00c */
-} __attribute__ ((aligned(0x20000)));
-
-/* SPU Privilege 2 State Area */
-struct spu_priv2 {
-	/* MFC Registers */
-	u8  pad_0x0000_0x1100[0x1100 - 0x0000]; 		/* 0x0000 */
-
-	/* SLB Management Registers */
-	u8  pad_0x1100_0x1108[0x8];				/* 0x1100 */
-	u64 slb_index_W;					/* 0x1108 */
-#define SLB_INDEX_MASK				0x7L
-	u64 slb_esid_RW;					/* 0x1110 */
-	u64 slb_vsid_RW;					/* 0x1118 */
-#define SLB_VSID_SUPERVISOR_STATE	(0x1ull << 11)
-#define SLB_VSID_SUPERVISOR_STATE_MASK	(0x1ull << 11)
-#define SLB_VSID_PROBLEM_STATE		(0x1ull << 10)
-#define SLB_VSID_PROBLEM_STATE_MASK	(0x1ull << 10)
-#define SLB_VSID_EXECUTE_SEGMENT	(0x1ull << 9)
-#define SLB_VSID_NO_EXECUTE_SEGMENT	(0x1ull << 9)
-#define SLB_VSID_EXECUTE_SEGMENT_MASK	(0x1ull << 9)
-#define SLB_VSID_4K_PAGE		(0x0 << 8)
-#define SLB_VSID_LARGE_PAGE		(0x1ull << 8)
-#define SLB_VSID_PAGE_SIZE_MASK		(0x1ull << 8)
-#define SLB_VSID_CLASS_MASK		(0x1ull << 7)
-#define SLB_VSID_VIRTUAL_PAGE_SIZE_MASK	(0x1ull << 6)
-	u64 slb_invalidate_entry_W;				/* 0x1120 */
-	u64 slb_invalidate_all_W;				/* 0x1128 */
-	u8  pad_0x1130_0x2000[0x2000 - 0x1130]; 		/* 0x1130 */
-
-	/* Context Save / Restore Area */
-	struct mfc_cq_sr spuq[16];				/* 0x2000 */
-	struct mfc_cq_sr puq[8];				/* 0x2200 */
-	u8  pad_0x2300_0x3000[0x3000 - 0x2300]; 		/* 0x2300 */
-
-	/* MFC Control */
-	u64 mfc_control_RW;					/* 0x3000 */
-#define MFC_CNTL_RESUME_DMA_QUEUE		(0ull << 0)
-#define MFC_CNTL_SUSPEND_DMA_QUEUE		(1ull << 0)
-#define MFC_CNTL_SUSPEND_DMA_QUEUE_MASK		(1ull << 0)
-#define MFC_CNTL_SUSPEND_MASK			(1ull << 4)
-#define MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION	(0ull << 8)
-#define MFC_CNTL_SUSPEND_IN_PROGRESS		(1ull << 8)
-#define MFC_CNTL_SUSPEND_COMPLETE		(3ull << 8)
-#define MFC_CNTL_SUSPEND_DMA_STATUS_MASK	(3ull << 8)
-#define MFC_CNTL_DMA_QUEUES_EMPTY		(1ull << 14)
-#define MFC_CNTL_DMA_QUEUES_EMPTY_MASK		(1ull << 14)
-#define MFC_CNTL_PURGE_DMA_REQUEST		(1ull << 15)
-#define MFC_CNTL_PURGE_DMA_IN_PROGRESS		(1ull << 24)
-#define MFC_CNTL_PURGE_DMA_COMPLETE		(3ull << 24)
-#define MFC_CNTL_PURGE_DMA_STATUS_MASK		(3ull << 24)
-#define MFC_CNTL_RESTART_DMA_COMMAND		(1ull << 32)
-#define MFC_CNTL_DMA_COMMAND_REISSUE_PENDING	(1ull << 32)
-#define MFC_CNTL_DMA_COMMAND_REISSUE_STATUS_MASK (1ull << 32)
-#define MFC_CNTL_MFC_PRIVILEGE_STATE		(2ull << 33)
-#define MFC_CNTL_MFC_PROBLEM_STATE		(3ull << 33)
-#define MFC_CNTL_MFC_KEY_PROTECTION_STATE_MASK	(3ull << 33)
-#define MFC_CNTL_DECREMENTER_HALTED		(1ull << 35)
-#define MFC_CNTL_DECREMENTER_RUNNING		(1ull << 40)
-#define MFC_CNTL_DECREMENTER_STATUS_MASK	(1ull << 40)
-	u8  pad_0x3008_0x4000[0x4000 - 0x3008]; 		/* 0x3008 */
-
-	/* Interrupt Mailbox */
-	u64 puint_mb_R;						/* 0x4000 */
-	u8  pad_0x4008_0x4040[0x4040 - 0x4008]; 		/* 0x4008 */
-
-	/* SPU Control */
-	u64 spu_privcntl_RW;					/* 0x4040 */
-#define SPU_PRIVCNTL_MODE_NORMAL		(0x0ull << 0)
-#define SPU_PRIVCNTL_MODE_SINGLE_STEP		(0x1ull << 0)
-#define SPU_PRIVCNTL_MODE_MASK			(0x1ull << 0)
-#define SPU_PRIVCNTL_NO_ATTENTION_EVENT		(0x0ull << 1)
-#define SPU_PRIVCNTL_ATTENTION_EVENT		(0x1ull << 1)
-#define SPU_PRIVCNTL_ATTENTION_EVENT_MASK	(0x1ull << 1)
-#define SPU_PRIVCNT_LOAD_REQUEST_NORMAL		(0x0ull << 2)
-#define SPU_PRIVCNT_LOAD_REQUEST_ENABLE_MASK	(0x1ull << 2)
-	u8  pad_0x4048_0x4058[0x10];				/* 0x4048 */
-	u64 spu_lslr_RW;					/* 0x4058 */
-	u64 spu_chnlcntptr_RW;					/* 0x4060 */
-	u64 spu_chnlcnt_RW;					/* 0x4068 */
-	u64 spu_chnldata_RW;					/* 0x4070 */
-	u64 spu_cfg_RW;						/* 0x4078 */
-	u8  pad_0x4080_0x5000[0x5000 - 0x4080]; 		/* 0x4080 */
-
-	/* PV2_ImplRegs: Implementation-specific privileged-state 2 regs */
-	u64 spu_pm_trace_tag_status_RW;				/* 0x5000 */
-	u64 spu_tag_status_query_RW;				/* 0x5008 */
-#define TAG_STATUS_QUERY_CONDITION_BITS (0x3ull << 32)
-#define TAG_STATUS_QUERY_MASK_BITS (0xffffffffull)
-	u64 spu_cmd_buf1_RW;					/* 0x5010 */
-#define SPU_COMMAND_BUFFER_1_LSA_BITS (0x7ffffull << 32)
-#define SPU_COMMAND_BUFFER_1_EAH_BITS (0xffffffffull)
-	u64 spu_cmd_buf2_RW;					/* 0x5018 */
-#define SPU_COMMAND_BUFFER_2_EAL_BITS ((0xffffffffull) << 32)
-#define SPU_COMMAND_BUFFER_2_TS_BITS (0xffffull << 16)
-#define SPU_COMMAND_BUFFER_2_TAG_BITS (0x3full)
-	u64 spu_atomic_status_RW;				/* 0x5020 */
-} __attribute__ ((aligned(0x20000)));
-
-/* SPU Privilege 1 State Area */
-struct spu_priv1 {
-	/* Control and Configuration Area */
-	u64 mfc_sr1_RW;						/* 0x000 */
-#define MFC_STATE1_LOCAL_STORAGE_DECODE_MASK	0x01ull
-#define MFC_STATE1_BUS_TLBIE_MASK		0x02ull
-#define MFC_STATE1_REAL_MODE_OFFSET_ENABLE_MASK	0x04ull
-#define MFC_STATE1_PROBLEM_STATE_MASK		0x08ull
-#define MFC_STATE1_RELOCATE_MASK		0x10ull
-#define MFC_STATE1_MASTER_RUN_CONTROL_MASK	0x20ull
-#define MFC_STATE1_TABLE_SEARCH_MASK		0x40ull
-	u64 mfc_lpid_RW;					/* 0x008 */
-	u64 spu_idr_RW;						/* 0x010 */
-	u64 mfc_vr_RO;						/* 0x018 */
-#define MFC_VERSION_BITS		(0xffff << 16)
-#define MFC_REVISION_BITS		(0xffff)
-#define MFC_GET_VERSION_BITS(vr)	(((vr) & MFC_VERSION_BITS) >> 16)
-#define MFC_GET_REVISION_BITS(vr)	((vr) & MFC_REVISION_BITS)
-	u64 spu_vr_RO;						/* 0x020 */
-#define SPU_VERSION_BITS		(0xffff << 16)
-#define SPU_REVISION_BITS		(0xffff)
-#define SPU_GET_VERSION_BITS(vr)	(vr & SPU_VERSION_BITS) >> 16
-#define SPU_GET_REVISION_BITS(vr)	(vr & SPU_REVISION_BITS)
-	u8  pad_0x28_0x100[0x100 - 0x28];			/* 0x28 */
-
-	/* Interrupt Area */
-	u64 int_mask_RW[3];					/* 0x100 */
-#define CLASS0_ENABLE_DMA_ALIGNMENT_INTR		0x1L
-#define CLASS0_ENABLE_INVALID_DMA_COMMAND_INTR		0x2L
-#define CLASS0_ENABLE_SPU_ERROR_INTR			0x4L
-#define CLASS0_ENABLE_MFC_FIR_INTR			0x8L
-#define CLASS1_ENABLE_SEGMENT_FAULT_INTR		0x1L
-#define CLASS1_ENABLE_STORAGE_FAULT_INTR		0x2L
-#define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_GET_INTR	0x4L
-#define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_PUT_INTR	0x8L
-#define CLASS2_ENABLE_MAILBOX_INTR			0x1L
-#define CLASS2_ENABLE_SPU_STOP_INTR			0x2L
-#define CLASS2_ENABLE_SPU_HALT_INTR			0x4L
-#define CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR	0x8L
-#define CLASS2_ENABLE_MAILBOX_THRESHOLD_INTR		0x10L
-	u8  pad_0x118_0x140[0x28];				/* 0x118 */
-	u64 int_stat_RW[3];					/* 0x140 */
-#define CLASS0_DMA_ALIGNMENT_INTR			0x1L
-#define CLASS0_INVALID_DMA_COMMAND_INTR			0x2L
-#define CLASS0_SPU_ERROR_INTR				0x4L
-#define CLASS0_INTR_MASK				0x7L
-#define CLASS1_SEGMENT_FAULT_INTR			0x1L
-#define CLASS1_STORAGE_FAULT_INTR			0x2L
-#define CLASS1_LS_COMPARE_SUSPEND_ON_GET_INTR		0x4L
-#define CLASS1_LS_COMPARE_SUSPEND_ON_PUT_INTR		0x8L
-#define CLASS1_INTR_MASK				0xfL
-#define CLASS2_MAILBOX_INTR				0x1L
-#define CLASS2_SPU_STOP_INTR				0x2L
-#define CLASS2_SPU_HALT_INTR				0x4L
-#define CLASS2_SPU_DMA_TAG_GROUP_COMPLETE_INTR		0x8L
-#define CLASS2_MAILBOX_THRESHOLD_INTR			0x10L
-#define CLASS2_INTR_MASK				0x1fL
-	u8  pad_0x158_0x180[0x28];				/* 0x158 */
-	u64 int_route_RW;					/* 0x180 */
-
-	/* Interrupt Routing */
-	u8  pad_0x188_0x200[0x200 - 0x188];			/* 0x188 */
-
-	/* Atomic Unit Control Area */
-	u64 mfc_atomic_flush_RW;				/* 0x200 */
-#define mfc_atomic_flush_enable			0x1L
-	u8  pad_0x208_0x280[0x78];				/* 0x208 */
-	u64 resource_allocation_groupID_RW;			/* 0x280 */
-	u64 resource_allocation_enable_RW; 			/* 0x288 */
-	u8  pad_0x290_0x3c8[0x3c8 - 0x290];			/* 0x290 */
-
-	/* SPU_Cache_ImplRegs: Implementation-dependent cache registers */
-
-	u64 smf_sbi_signal_sel;					/* 0x3c8 */
-#define smf_sbi_mask_lsb	56
-#define smf_sbi_shift		(63 - smf_sbi_mask_lsb)
-#define smf_sbi_mask		(0x301LL << smf_sbi_shift)
-#define smf_sbi_bus0_bits	(0x001LL << smf_sbi_shift)
-#define smf_sbi_bus2_bits	(0x100LL << smf_sbi_shift)
-#define smf_sbi2_bus0_bits	(0x201LL << smf_sbi_shift)
-#define smf_sbi2_bus2_bits	(0x300LL << smf_sbi_shift)
-	u64 smf_ato_signal_sel;					/* 0x3d0 */
-#define smf_ato_mask_lsb	35
-#define smf_ato_shift		(63 - smf_ato_mask_lsb)
-#define smf_ato_mask		(0x3LL << smf_ato_shift)
-#define smf_ato_bus0_bits	(0x2LL << smf_ato_shift)
-#define smf_ato_bus2_bits	(0x1LL << smf_ato_shift)
-	u8  pad_0x3d8_0x400[0x400 - 0x3d8];			/* 0x3d8 */
-
-	/* TLB Management Registers */
-	u64 mfc_sdr_RW;						/* 0x400 */
-	u8  pad_0x408_0x500[0xf8];				/* 0x408 */
-	u64 tlb_index_hint_RO;					/* 0x500 */
-	u64 tlb_index_W;					/* 0x508 */
-	u64 tlb_vpn_RW;						/* 0x510 */
-	u64 tlb_rpn_RW;						/* 0x518 */
-	u8  pad_0x520_0x540[0x20];				/* 0x520 */
-	u64 tlb_invalidate_entry_W;				/* 0x540 */
-	u64 tlb_invalidate_all_W;				/* 0x548 */
-	u8  pad_0x550_0x580[0x580 - 0x550];			/* 0x550 */
-
-	/* SPU_MMU_ImplRegs: Implementation-dependent MMU registers */
-	u64 smm_hid;						/* 0x580 */
-#define PAGE_SIZE_MASK		0xf000000000000000ull
-#define PAGE_SIZE_16MB_64KB	0x2000000000000000ull
-	u8  pad_0x588_0x600[0x600 - 0x588];			/* 0x588 */
-
-	/* MFC Status/Control Area */
-	u64 mfc_accr_RW;					/* 0x600 */
-#define MFC_ACCR_EA_ACCESS_GET		(1 << 0)
-#define MFC_ACCR_EA_ACCESS_PUT		(1 << 1)
-#define MFC_ACCR_LS_ACCESS_GET		(1 << 3)
-#define MFC_ACCR_LS_ACCESS_PUT		(1 << 4)
-	u8  pad_0x608_0x610[0x8];				/* 0x608 */
-	u64 mfc_dsisr_RW;					/* 0x610 */
-#define MFC_DSISR_PTE_NOT_FOUND		(1 << 30)
-#define MFC_DSISR_ACCESS_DENIED		(1 << 27)
-#define MFC_DSISR_ATOMIC		(1 << 26)
-#define MFC_DSISR_ACCESS_PUT		(1 << 25)
-#define MFC_DSISR_ADDR_MATCH		(1 << 22)
-#define MFC_DSISR_LS			(1 << 17)
-#define MFC_DSISR_L			(1 << 16)
-#define MFC_DSISR_ADDRESS_OVERFLOW	(1 << 0)
-	u8  pad_0x618_0x620[0x8];				/* 0x618 */
-	u64 mfc_dar_RW;						/* 0x620 */
-	u8  pad_0x628_0x700[0x700 - 0x628];			/* 0x628 */
-
-	/* Replacement Management Table (RMT) Area */
-	u64 rmt_index_RW;					/* 0x700 */
-	u8  pad_0x708_0x710[0x8];				/* 0x708 */
-	u64 rmt_data1_RW;					/* 0x710 */
-	u8  pad_0x718_0x800[0x800 - 0x718];			/* 0x718 */
-
-	/* Control/Configuration Registers */
-	u64 mfc_dsir_R;						/* 0x800 */
-#define MFC_DSIR_Q			(1 << 31)
-#define MFC_DSIR_SPU_QUEUE		MFC_DSIR_Q
-	u64 mfc_lsacr_RW;					/* 0x808 */
-#define MFC_LSACR_COMPARE_MASK		((~0ull) << 32)
-#define MFC_LSACR_COMPARE_ADDR		((~0ull) >> 32)
-	u64 mfc_lscrr_R;					/* 0x810 */
-#define MFC_LSCRR_Q			(1 << 31)
-#define MFC_LSCRR_SPU_QUEUE		MFC_LSCRR_Q
-#define MFC_LSCRR_QI_SHIFT		32
-#define MFC_LSCRR_QI_MASK		((~0ull) << MFC_LSCRR_QI_SHIFT)
-	u8  pad_0x818_0x820[0x8];				/* 0x818 */
-	u64 mfc_tclass_id_RW;					/* 0x820 */
-#define MFC_TCLASS_ID_ENABLE		(1L << 0L)
-#define MFC_TCLASS_SLOT2_ENABLE		(1L << 5L)
-#define MFC_TCLASS_SLOT1_ENABLE		(1L << 6L)
-#define MFC_TCLASS_SLOT0_ENABLE		(1L << 7L)
-#define MFC_TCLASS_QUOTA_2_SHIFT	8L
-#define MFC_TCLASS_QUOTA_1_SHIFT	16L
-#define MFC_TCLASS_QUOTA_0_SHIFT	24L
-#define MFC_TCLASS_QUOTA_2_MASK		(0x1FL << MFC_TCLASS_QUOTA_2_SHIFT)
-#define MFC_TCLASS_QUOTA_1_MASK		(0x1FL << MFC_TCLASS_QUOTA_1_SHIFT)
-#define MFC_TCLASS_QUOTA_0_MASK		(0x1FL << MFC_TCLASS_QUOTA_0_SHIFT)
-	u8  pad_0x828_0x900[0x900 - 0x828];			/* 0x828 */
-
-	/* Real Mode Support Registers */
-	u64 mfc_rm_boundary;					/* 0x900 */
-	u8  pad_0x908_0x938[0x30];				/* 0x908 */
-	u64 smf_dma_signal_sel;					/* 0x938 */
-#define mfc_dma1_mask_lsb	41
-#define mfc_dma1_shift		(63 - mfc_dma1_mask_lsb)
-#define mfc_dma1_mask		(0x3LL << mfc_dma1_shift)
-#define mfc_dma1_bits		(0x1LL << mfc_dma1_shift)
-#define mfc_dma2_mask_lsb	43
-#define mfc_dma2_shift		(63 - mfc_dma2_mask_lsb)
-#define mfc_dma2_mask		(0x3LL << mfc_dma2_shift)
-#define mfc_dma2_bits		(0x1LL << mfc_dma2_shift)
-	u8  pad_0x940_0xa38[0xf8];				/* 0x940 */
-	u64 smm_signal_sel;					/* 0xa38 */
-#define smm_sig_mask_lsb	12
-#define smm_sig_shift		(63 - smm_sig_mask_lsb)
-#define smm_sig_mask		(0x3LL << smm_sig_shift)
-#define smm_sig_bus0_bits	(0x2LL << smm_sig_shift)
-#define smm_sig_bus2_bits	(0x1LL << smm_sig_shift)
-	u8  pad_0xa40_0xc00[0xc00 - 0xa40];			/* 0xa40 */
-
-	/* DMA Command Error Area */
-	u64 mfc_cer_R;						/* 0xc00 */
-#define MFC_CER_Q		(1 << 31)
-#define MFC_CER_SPU_QUEUE	MFC_CER_Q
-	u8  pad_0xc08_0x1000[0x1000 - 0xc08];			/* 0xc08 */
-
-	/* PV1_ImplRegs: Implementation-dependent privileged-state 1 regs */
-	/* DMA Command Error Area */
-	u64 spu_ecc_cntl_RW;					/* 0x1000 */
-#define SPU_ECC_CNTL_E			(1ull << 0ull)
-#define SPU_ECC_CNTL_ENABLE		SPU_ECC_CNTL_E
-#define SPU_ECC_CNTL_DISABLE		(~SPU_ECC_CNTL_E & 1L)
-#define SPU_ECC_CNTL_S			(1ull << 1ull)
-#define SPU_ECC_STOP_AFTER_ERROR	SPU_ECC_CNTL_S
-#define SPU_ECC_CONTINUE_AFTER_ERROR	(~SPU_ECC_CNTL_S & 2L)
-#define SPU_ECC_CNTL_B			(1ull << 2ull)
-#define SPU_ECC_BACKGROUND_ENABLE	SPU_ECC_CNTL_B
-#define SPU_ECC_BACKGROUND_DISABLE	(~SPU_ECC_CNTL_B & 4L)
-#define SPU_ECC_CNTL_I_SHIFT		3ull
-#define SPU_ECC_CNTL_I_MASK		(3ull << SPU_ECC_CNTL_I_SHIFT)
-#define SPU_ECC_WRITE_ALWAYS		(~SPU_ECC_CNTL_I & 12L)
-#define SPU_ECC_WRITE_CORRECTABLE	(1ull << SPU_ECC_CNTL_I_SHIFT)
-#define SPU_ECC_WRITE_UNCORRECTABLE	(3ull << SPU_ECC_CNTL_I_SHIFT)
-#define SPU_ECC_CNTL_D			(1ull << 5ull)
-#define SPU_ECC_DETECTION_ENABLE	SPU_ECC_CNTL_D
-#define SPU_ECC_DETECTION_DISABLE	(~SPU_ECC_CNTL_D & 32L)
-	u64 spu_ecc_stat_RW;					/* 0x1008 */
-#define SPU_ECC_CORRECTED_ERROR		(1ull << 0ul)
-#define SPU_ECC_UNCORRECTED_ERROR	(1ull << 1ul)
-#define SPU_ECC_SCRUB_COMPLETE		(1ull << 2ul)
-#define SPU_ECC_SCRUB_IN_PROGRESS	(1ull << 3ul)
-#define SPU_ECC_INSTRUCTION_ERROR	(1ull << 4ul)
-#define SPU_ECC_DATA_ERROR		(1ull << 5ul)
-#define SPU_ECC_DMA_ERROR		(1ull << 6ul)
-#define SPU_ECC_STATUS_CNT_MASK		(256ull << 8)
-	u64 spu_ecc_addr_RW;					/* 0x1010 */
-	u64 spu_err_mask_RW;					/* 0x1018 */
-#define SPU_ERR_ILLEGAL_INSTR		(1ull << 0ul)
-#define SPU_ERR_ILLEGAL_CHANNEL		(1ull << 1ul)
-	u8  pad_0x1020_0x1028[0x1028 - 0x1020];			/* 0x1020 */
-
-	/* SPU Debug-Trace Bus (DTB) Selection Registers */
-	u64 spu_trig0_sel;					/* 0x1028 */
-	u64 spu_trig1_sel;					/* 0x1030 */
-	u64 spu_trig2_sel;					/* 0x1038 */
-	u64 spu_trig3_sel;					/* 0x1040 */
-	u64 spu_trace_sel;					/* 0x1048 */
-#define spu_trace_sel_mask		0x1f1fLL
-#define spu_trace_sel_bus0_bits		0x1000LL
-#define spu_trace_sel_bus2_bits		0x0010LL
-	u64 spu_event0_sel;					/* 0x1050 */
-	u64 spu_event1_sel;					/* 0x1058 */
-	u64 spu_event2_sel;					/* 0x1060 */
-	u64 spu_event3_sel;					/* 0x1068 */
-	u64 spu_trace_cntl;					/* 0x1070 */
-} __attribute__ ((aligned(0x2000)));
-
-#endif /* __KERNEL__ */
-#endif
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/spu_csa.h b/ANDROID_3.4.5/arch/powerpc/include/asm/spu_csa.h
deleted file mode 100644
index a40fd491..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/spu_csa.h
+++ /dev/null
@@ -1,266 +0,0 @@
-/*
- * spu_csa.h: Definitions for SPU context save area (CSA).
- *
- * (C) Copyright IBM 2005
- *
- * Author: Mark Nutter <mnutter@us.ibm.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef _SPU_CSA_H_
-#define _SPU_CSA_H_
-#ifdef __KERNEL__
-
-/*
- * Total number of 128-bit registers.
- */
-#define NR_SPU_GPRS         	128
-#define NR_SPU_SPRS         	9
-#define NR_SPU_REGS_PAD	    	7
-#define NR_SPU_SPILL_REGS   	144	/* GPRS + SPRS + PAD */
-#define SIZEOF_SPU_SPILL_REGS	NR_SPU_SPILL_REGS * 16
-
-#define SPU_SAVE_COMPLETE      	0x3FFB
-#define SPU_RESTORE_COMPLETE   	0x3FFC
-
-/*
- * Definitions for various 'stopped' status conditions,
- * to be recreated during context restore.
- */
-#define SPU_STOPPED_STATUS_P    1
-#define SPU_STOPPED_STATUS_I    2
-#define SPU_STOPPED_STATUS_H    3
-#define SPU_STOPPED_STATUS_S    4
-#define SPU_STOPPED_STATUS_S_I  5
-#define SPU_STOPPED_STATUS_S_P  6
-#define SPU_STOPPED_STATUS_P_H  7
-#define SPU_STOPPED_STATUS_P_I  8
-#define SPU_STOPPED_STATUS_R    9
-
-/*
- * Definitions for software decrementer status flag.
- */
-#define SPU_DECR_STATUS_RUNNING 0x1
-#define SPU_DECR_STATUS_WRAPPED 0x2
-
-#ifndef  __ASSEMBLY__
-/**
- * spu_reg128 - generic 128-bit register definition.
- */
-struct spu_reg128 {
-	u32 slot[4];
-};
-
-/**
- * struct spu_lscsa - Local Store Context Save Area.
- * @gprs: Array of saved registers.
- * @fpcr: Saved floating point status control register.
- * @decr: Saved decrementer value.
- * @decr_status: Indicates software decrementer status flags.
- * @ppu_mb: Saved PPU mailbox data.
- * @ppuint_mb: Saved PPU interrupting mailbox data.
- * @tag_mask: Saved tag group mask.
- * @event_mask: Saved event mask.
- * @srr0: Saved SRR0.
- * @stopped_status: Conditions to be recreated by restore.
- * @ls: Saved contents of Local Storage Area.
- *
- * The LSCSA represents state that is primarily saved and
- * restored by SPU-side code.
- */
-struct spu_lscsa {
-	struct spu_reg128 gprs[128];
-	struct spu_reg128 fpcr;
-	struct spu_reg128 decr;
-	struct spu_reg128 decr_status;
-	struct spu_reg128 ppu_mb;
-	struct spu_reg128 ppuint_mb;
-	struct spu_reg128 tag_mask;
-	struct spu_reg128 event_mask;
-	struct spu_reg128 srr0;
-	struct spu_reg128 stopped_status;
-
-	/*
-	 * 'ls' must be page-aligned on all configurations.
-	 * Since we don't want to rely on having the spu-gcc
-	 * installed to build the kernel and this structure
-	 * is used in the SPU-side code, make it 64k-page
-	 * aligned for now.
-	 */
-	unsigned char ls[LS_SIZE] __attribute__((aligned(65536)));
-};
-
-#ifndef __SPU__
-/*
- * struct spu_problem_collapsed - condensed problem state area, w/o pads.
- */
-struct spu_problem_collapsed {
-	u64 spc_mssync_RW;
-	u32 mfc_lsa_W;
-	u32 unused_pad0;
-	u64 mfc_ea_W;
-	union mfc_tag_size_class_cmd mfc_union_W;
-	u32 dma_qstatus_R;
-	u32 dma_querytype_RW;
-	u32 dma_querymask_RW;
-	u32 dma_tagstatus_R;
-	u32 pu_mb_R;
-	u32 spu_mb_W;
-	u32 mb_stat_R;
-	u32 spu_runcntl_RW;
-	u32 spu_status_R;
-	u32 spu_spc_R;
-	u32 spu_npc_RW;
-	u32 signal_notify1;
-	u32 signal_notify2;
-	u32 unused_pad1;
-};
-
-/*
- * struct spu_priv1_collapsed - condensed privileged 1 area, w/o pads.
- */
-struct spu_priv1_collapsed {
-	u64 mfc_sr1_RW;
-	u64 mfc_lpid_RW;
-	u64 spu_idr_RW;
-	u64 mfc_vr_RO;
-	u64 spu_vr_RO;
-	u64 int_mask_class0_RW;
-	u64 int_mask_class1_RW;
-	u64 int_mask_class2_RW;
-	u64 int_stat_class0_RW;
-	u64 int_stat_class1_RW;
-	u64 int_stat_class2_RW;
-	u64 int_route_RW;
-	u64 mfc_atomic_flush_RW;
-	u64 resource_allocation_groupID_RW;
-	u64 resource_allocation_enable_RW;
-	u64 mfc_fir_R;
-	u64 mfc_fir_status_or_W;
-	u64 mfc_fir_status_and_W;
-	u64 mfc_fir_mask_R;
-	u64 mfc_fir_mask_or_W;
-	u64 mfc_fir_mask_and_W;
-	u64 mfc_fir_chkstp_enable_RW;
-	u64 smf_sbi_signal_sel;
-	u64 smf_ato_signal_sel;
-	u64 tlb_index_hint_RO;
-	u64 tlb_index_W;
-	u64 tlb_vpn_RW;
-	u64 tlb_rpn_RW;
-	u64 tlb_invalidate_entry_W;
-	u64 tlb_invalidate_all_W;
-	u64 smm_hid;
-	u64 mfc_accr_RW;
-	u64 mfc_dsisr_RW;
-	u64 mfc_dar_RW;
-	u64 rmt_index_RW;
-	u64 rmt_data1_RW;
-	u64 mfc_dsir_R;
-	u64 mfc_lsacr_RW;
-	u64 mfc_lscrr_R;
-	u64 mfc_tclass_id_RW;
-	u64 mfc_rm_boundary;
-	u64 smf_dma_signal_sel;
-	u64 smm_signal_sel;
-	u64 mfc_cer_R;
-	u64 pu_ecc_cntl_RW;
-	u64 pu_ecc_stat_RW;
-	u64 spu_ecc_addr_RW;
-	u64 spu_err_mask_RW;
-	u64 spu_trig0_sel;
-	u64 spu_trig1_sel;
-	u64 spu_trig2_sel;
-	u64 spu_trig3_sel;
-	u64 spu_trace_sel;
-	u64 spu_event0_sel;
-	u64 spu_event1_sel;
-	u64 spu_event2_sel;
-	u64 spu_event3_sel;
-	u64 spu_trace_cntl;
-};
-
-/*
- * struct spu_priv2_collapsed - condensed privileged 2 area, w/o pads.
- */
-struct spu_priv2_collapsed {
-	u64 slb_index_W;
-	u64 slb_esid_RW;
-	u64 slb_vsid_RW;
-	u64 slb_invalidate_entry_W;
-	u64 slb_invalidate_all_W;
-	struct mfc_cq_sr spuq[16];
-	struct mfc_cq_sr puq[8];
-	u64 mfc_control_RW;
-	u64 puint_mb_R;
-	u64 spu_privcntl_RW;
-	u64 spu_lslr_RW;
-	u64 spu_chnlcntptr_RW;
-	u64 spu_chnlcnt_RW;
-	u64 spu_chnldata_RW;
-	u64 spu_cfg_RW;
-	u64 spu_tag_status_query_RW;
-	u64 spu_cmd_buf1_RW;
-	u64 spu_cmd_buf2_RW;
-	u64 spu_atomic_status_RW;
-};
-
-/**
- * struct spu_state
- * @lscsa: Local Store Context Save Area.
- * @prob: Collapsed Problem State Area, w/o pads.
- * @priv1: Collapsed Privileged 1 Area, w/o pads.
- * @priv2: Collapsed Privileged 2 Area, w/o pads.
- * @spu_chnlcnt_RW: Array of saved channel counts.
- * @spu_chnldata_RW: Array of saved channel data.
- * @suspend_time: Time stamp when decrementer disabled.
- *
- * Structure representing the whole of the SPU
- * context save area (CSA).  This struct contains
- * all of the state necessary to suspend and then
- * later optionally resume execution of an SPU
- * context.
- *
- * The @lscsa region is by far the largest, and is
- * allocated separately so that it may either be
- * pinned or mapped to/from application memory, as
- * appropriate for the OS environment.
- */
-struct spu_state {
-	struct spu_lscsa *lscsa;
-#ifdef CONFIG_SPU_FS_64K_LS
-	int		use_big_pages;
-	/* One struct page per 64k page */
-#define SPU_LSCSA_NUM_BIG_PAGES	(sizeof(struct spu_lscsa) / 0x10000)
-	struct page	*lscsa_pages[SPU_LSCSA_NUM_BIG_PAGES];
-#endif
-	struct spu_problem_collapsed prob;
-	struct spu_priv1_collapsed priv1;
-	struct spu_priv2_collapsed priv2;
-	u64 spu_chnlcnt_RW[32];
-	u64 spu_chnldata_RW[32];
-	u32 spu_mailbox_data[4];
-	u32 pu_mailbox_data[1];
-	u64 class_0_dar, class_0_pending;
-	u64 class_1_dar, class_1_dsisr;
-	unsigned long suspend_time;
-	spinlock_t register_lock;
-};
-
-#endif /* !__SPU__ */
-#endif /* __KERNEL__ */
-#endif /* !__ASSEMBLY__ */
-#endif /* _SPU_CSA_H_ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/spu_info.h b/ANDROID_3.4.5/arch/powerpc/include/asm/spu_info.h
deleted file mode 100644
index 1286c823..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/spu_info.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * SPU info structures
- *
- * (C) Copyright 2006 IBM Corp.
- *
- * Author: Dwayne Grant McConnell <decimal@us.ibm.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef _SPU_INFO_H
-#define _SPU_INFO_H
-
-#include <linux/types.h>
-
-#ifdef __KERNEL__
-#include <asm/spu.h>
-#else
-struct mfc_cq_sr {
-	__u64 mfc_cq_data0_RW;
-	__u64 mfc_cq_data1_RW;
-	__u64 mfc_cq_data2_RW;
-	__u64 mfc_cq_data3_RW;
-};
-#endif /* __KERNEL__ */
-
-struct spu_dma_info {
-	__u64 dma_info_type;
-	__u64 dma_info_mask;
-	__u64 dma_info_status;
-	__u64 dma_info_stall_and_notify;
-	__u64 dma_info_atomic_command_status;
-	struct mfc_cq_sr dma_info_command_data[16];
-};
-
-struct spu_proxydma_info {
-	__u64 proxydma_info_type;
-	__u64 proxydma_info_mask;
-	__u64 proxydma_info_status;
-	struct mfc_cq_sr proxydma_info_command_data[8];
-};
-
-#endif
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/spu_priv1.h b/ANDROID_3.4.5/arch/powerpc/include/asm/spu_priv1.h
deleted file mode 100644
index d8f5c60f..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/spu_priv1.h
+++ /dev/null
@@ -1,236 +0,0 @@
-/*
- * Defines an spu hypervisor abstraction layer.
- *
- *  Copyright 2006 Sony Corp.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; version 2 of the License.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#if !defined(_SPU_PRIV1_H)
-#define _SPU_PRIV1_H
-#if defined(__KERNEL__)
-
-#include <linux/types.h>
-
-struct spu;
-struct spu_context;
-
-/* access to priv1 registers */
-
-struct spu_priv1_ops {
-	void (*int_mask_and) (struct spu *spu, int class, u64 mask);
-	void (*int_mask_or) (struct spu *spu, int class, u64 mask);
-	void (*int_mask_set) (struct spu *spu, int class, u64 mask);
-	u64 (*int_mask_get) (struct spu *spu, int class);
-	void (*int_stat_clear) (struct spu *spu, int class, u64 stat);
-	u64 (*int_stat_get) (struct spu *spu, int class);
-	void (*cpu_affinity_set) (struct spu *spu, int cpu);
-	u64 (*mfc_dar_get) (struct spu *spu);
-	u64 (*mfc_dsisr_get) (struct spu *spu);
-	void (*mfc_dsisr_set) (struct spu *spu, u64 dsisr);
-	void (*mfc_sdr_setup) (struct spu *spu);
-	void (*mfc_sr1_set) (struct spu *spu, u64 sr1);
-	u64 (*mfc_sr1_get) (struct spu *spu);
-	void (*mfc_tclass_id_set) (struct spu *spu, u64 tclass_id);
-	u64 (*mfc_tclass_id_get) (struct spu *spu);
-	void (*tlb_invalidate) (struct spu *spu);
-	void (*resource_allocation_groupID_set) (struct spu *spu, u64 id);
-	u64 (*resource_allocation_groupID_get) (struct spu *spu);
-	void (*resource_allocation_enable_set) (struct spu *spu, u64 enable);
-	u64 (*resource_allocation_enable_get) (struct spu *spu);
-};
-
-extern const struct spu_priv1_ops* spu_priv1_ops;
-
-static inline void
-spu_int_mask_and (struct spu *spu, int class, u64 mask)
-{
-	spu_priv1_ops->int_mask_and(spu, class, mask);
-}
-
-static inline void
-spu_int_mask_or (struct spu *spu, int class, u64 mask)
-{
-	spu_priv1_ops->int_mask_or(spu, class, mask);
-}
-
-static inline void
-spu_int_mask_set (struct spu *spu, int class, u64 mask)
-{
-	spu_priv1_ops->int_mask_set(spu, class, mask);
-}
-
-static inline u64
-spu_int_mask_get (struct spu *spu, int class)
-{
-	return spu_priv1_ops->int_mask_get(spu, class);
-}
-
-static inline void
-spu_int_stat_clear (struct spu *spu, int class, u64 stat)
-{
-	spu_priv1_ops->int_stat_clear(spu, class, stat);
-}
-
-static inline u64
-spu_int_stat_get (struct spu *spu, int class)
-{
-	return spu_priv1_ops->int_stat_get (spu, class);
-}
-
-static inline void
-spu_cpu_affinity_set (struct spu *spu, int cpu)
-{
-	spu_priv1_ops->cpu_affinity_set(spu, cpu);
-}
-
-static inline u64
-spu_mfc_dar_get (struct spu *spu)
-{
-	return spu_priv1_ops->mfc_dar_get(spu);
-}
-
-static inline u64
-spu_mfc_dsisr_get (struct spu *spu)
-{
-	return spu_priv1_ops->mfc_dsisr_get(spu);
-}
-
-static inline void
-spu_mfc_dsisr_set (struct spu *spu, u64 dsisr)
-{
-	spu_priv1_ops->mfc_dsisr_set(spu, dsisr);
-}
-
-static inline void
-spu_mfc_sdr_setup (struct spu *spu)
-{
-	spu_priv1_ops->mfc_sdr_setup(spu);
-}
-
-static inline void
-spu_mfc_sr1_set (struct spu *spu, u64 sr1)
-{
-	spu_priv1_ops->mfc_sr1_set(spu, sr1);
-}
-
-static inline u64
-spu_mfc_sr1_get (struct spu *spu)
-{
-	return spu_priv1_ops->mfc_sr1_get(spu);
-}
-
-static inline void
-spu_mfc_tclass_id_set (struct spu *spu, u64 tclass_id)
-{
-	spu_priv1_ops->mfc_tclass_id_set(spu, tclass_id);
-}
-
-static inline u64
-spu_mfc_tclass_id_get (struct spu *spu)
-{
-	return spu_priv1_ops->mfc_tclass_id_get(spu);
-}
-
-static inline void
-spu_tlb_invalidate (struct spu *spu)
-{
-	spu_priv1_ops->tlb_invalidate(spu);
-}
-
-static inline void
-spu_resource_allocation_groupID_set (struct spu *spu, u64 id)
-{
-	spu_priv1_ops->resource_allocation_groupID_set(spu, id);
-}
-
-static inline u64
-spu_resource_allocation_groupID_get (struct spu *spu)
-{
-	return spu_priv1_ops->resource_allocation_groupID_get(spu);
-}
-
-static inline void
-spu_resource_allocation_enable_set (struct spu *spu, u64 enable)
-{
-	spu_priv1_ops->resource_allocation_enable_set(spu, enable);
-}
-
-static inline u64
-spu_resource_allocation_enable_get (struct spu *spu)
-{
-	return spu_priv1_ops->resource_allocation_enable_get(spu);
-}
-
-/* spu management abstraction */
-
-struct spu_management_ops {
-	int (*enumerate_spus)(int (*fn)(void *data));
-	int (*create_spu)(struct spu *spu, void *data);
-	int (*destroy_spu)(struct spu *spu);
-	void (*enable_spu)(struct spu_context *ctx);
-	void (*disable_spu)(struct spu_context *ctx);
-	int (*init_affinity)(void);
-};
-
-extern const struct spu_management_ops* spu_management_ops;
-
-static inline int
-spu_enumerate_spus (int (*fn)(void *data))
-{
-	return spu_management_ops->enumerate_spus(fn);
-}
-
-static inline int
-spu_create_spu (struct spu *spu, void *data)
-{
-	return spu_management_ops->create_spu(spu, data);
-}
-
-static inline int
-spu_destroy_spu (struct spu *spu)
-{
-	return spu_management_ops->destroy_spu(spu);
-}
-
-static inline int
-spu_init_affinity (void)
-{
-	return spu_management_ops->init_affinity();
-}
-
-static inline void
-spu_enable_spu (struct spu_context *ctx)
-{
-	spu_management_ops->enable_spu(ctx);
-}
-
-static inline void
-spu_disable_spu (struct spu_context *ctx)
-{
-	spu_management_ops->disable_spu(ctx);
-}
-
-/*
- * The declarations following are put here for convenience
- * and only intended to be used by the platform setup code.
- */
-
-extern const struct spu_priv1_ops spu_priv1_mmio_ops;
-extern const struct spu_priv1_ops spu_priv1_beat_ops;
-
-extern const struct spu_management_ops spu_management_of_ops;
-
-#endif /* __KERNEL__ */
-#endif
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/sstep.h b/ANDROID_3.4.5/arch/powerpc/include/asm/sstep.h
deleted file mode 100644
index f593b0f9..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/sstep.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-struct pt_regs;
-
-/*
- * We don't allow single-stepping an mtmsrd that would clear
- * MSR_RI, since that would make the exception unrecoverable.
- * Since we need to single-step to proceed from a breakpoint,
- * we don't allow putting a breakpoint on an mtmsrd instruction.
- * Similarly we don't allow breakpoints on rfid instructions.
- * These macros tell us if an instruction is a mtmsrd or rfid.
- * Note that IS_MTMSRD returns true for both an mtmsr (32-bit)
- * and an mtmsrd (64-bit).
- */
-#define IS_MTMSRD(instr)	(((instr) & 0xfc0007be) == 0x7c000124)
-#define IS_RFID(instr)		(((instr) & 0xfc0007fe) == 0x4c000024)
-#define IS_RFI(instr)		(((instr) & 0xfc0007fe) == 0x4c000064)
-
-/* Emulate instructions that cause a transfer of control. */
-extern int emulate_step(struct pt_regs *regs, unsigned int instr);
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/stat.h b/ANDROID_3.4.5/arch/powerpc/include/asm/stat.h
deleted file mode 100644
index e4edc510..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/stat.h
+++ /dev/null
@@ -1,81 +0,0 @@
-#ifndef _ASM_POWERPC_STAT_H
-#define _ASM_POWERPC_STAT_H
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#include <linux/types.h>
-
-#define STAT_HAVE_NSEC 1
-
-#ifndef __powerpc64__
-struct __old_kernel_stat {
-	unsigned short st_dev;
-	unsigned short st_ino;
-	unsigned short st_mode;
-	unsigned short st_nlink;
-	unsigned short st_uid;
-	unsigned short st_gid;
-	unsigned short st_rdev;
-	unsigned long  st_size;
-	unsigned long  st_atime;
-	unsigned long  st_mtime;
-	unsigned long  st_ctime;
-};
-#endif /* !__powerpc64__ */
-
-struct stat {
-	unsigned long	st_dev;
-	ino_t		st_ino;
-#ifdef __powerpc64__
-	nlink_t		st_nlink;
-	mode_t		st_mode;
-#else
-	mode_t		st_mode;
-	nlink_t		st_nlink;
-#endif
-	uid_t		st_uid;
-	gid_t		st_gid;
-	unsigned long	st_rdev;
-	off_t		st_size;
-	unsigned long	st_blksize;
-	unsigned long	st_blocks;
-	unsigned long	st_atime;
-	unsigned long	st_atime_nsec;
-	unsigned long	st_mtime;
-	unsigned long	st_mtime_nsec;
-	unsigned long	st_ctime;
-	unsigned long	st_ctime_nsec;
-	unsigned long	__unused4;
-	unsigned long	__unused5;
-#ifdef __powerpc64__
-	unsigned long	__unused6;
-#endif
-};
-
-/* This matches struct stat64 in glibc2.1. Only used for 32 bit. */
-struct stat64 {
-	unsigned long long st_dev;		/* Device.  */
-	unsigned long long st_ino;		/* File serial number.  */
-	unsigned int	st_mode;	/* File mode.  */
-	unsigned int	st_nlink;	/* Link count.  */
-	unsigned int	st_uid;		/* User ID of the file's owner.  */
-	unsigned int	st_gid;		/* Group ID of the file's group. */
-	unsigned long long st_rdev;	/* Device number, if device.  */
-	unsigned short	__pad2;
-	long long	st_size;	/* Size of file, in bytes.  */
-	int		st_blksize;	/* Optimal block size for I/O.  */
-	long long	st_blocks;	/* Number 512-byte blocks allocated. */
-	int		st_atime;	/* Time of last access.  */
-	unsigned int	st_atime_nsec;
-	int		st_mtime;	/* Time of last modification.  */
-	unsigned int	st_mtime_nsec;
-	int		st_ctime;	/* Time of last status change.  */
-	unsigned int	st_ctime_nsec;
-	unsigned int	__unused4;
-	unsigned int	__unused5;
-};
-
-#endif /* _ASM_POWERPC_STAT_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/statfs.h b/ANDROID_3.4.5/arch/powerpc/include/asm/statfs.h
deleted file mode 100644
index 52448345..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/statfs.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_POWERPC_STATFS_H
-#define _ASM_POWERPC_STATFS_H
-
-#include <asm-generic/statfs.h>
-
-#endif
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/string.h b/ANDROID_3.4.5/arch/powerpc/include/asm/string.h
deleted file mode 100644
index e40010ab..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/string.h
+++ /dev/null
@@ -1,32 +0,0 @@
-#ifndef _ASM_POWERPC_STRING_H
-#define _ASM_POWERPC_STRING_H
-
-#ifdef __KERNEL__
-
-#define __HAVE_ARCH_STRCPY
-#define __HAVE_ARCH_STRNCPY
-#define __HAVE_ARCH_STRLEN
-#define __HAVE_ARCH_STRCMP
-#define __HAVE_ARCH_STRNCMP
-#define __HAVE_ARCH_STRCAT
-#define __HAVE_ARCH_MEMSET
-#define __HAVE_ARCH_MEMCPY
-#define __HAVE_ARCH_MEMMOVE
-#define __HAVE_ARCH_MEMCMP
-#define __HAVE_ARCH_MEMCHR
-
-extern char * strcpy(char *,const char *);
-extern char * strncpy(char *,const char *, __kernel_size_t);
-extern __kernel_size_t strlen(const char *);
-extern int strcmp(const char *,const char *);
-extern int strncmp(const char *, const char *, __kernel_size_t);
-extern char * strcat(char *, const char *);
-extern void * memset(void *,int,__kernel_size_t);
-extern void * memcpy(void *,const void *,__kernel_size_t);
-extern void * memmove(void *,const void *,__kernel_size_t);
-extern int memcmp(const void *,const void *,__kernel_size_t);
-extern void * memchr(const void *,int,__kernel_size_t);
-
-#endif /* __KERNEL__ */
-
-#endif	/* _ASM_POWERPC_STRING_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/swab.h b/ANDROID_3.4.5/arch/powerpc/include/asm/swab.h
deleted file mode 100644
index c581e3ef..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/swab.h
+++ /dev/null
@@ -1,90 +0,0 @@
-#ifndef _ASM_POWERPC_SWAB_H
-#define _ASM_POWERPC_SWAB_H
-
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/types.h>
-#include <linux/compiler.h>
-
-#ifdef __GNUC__
-
-#ifndef __powerpc64__
-#define __SWAB_64_THRU_32__
-#endif /* __powerpc64__ */
-
-#ifdef __KERNEL__
-
-static __inline__ __u16 ld_le16(const volatile __u16 *addr)
-{
-	__u16 val;
-
-	__asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr));
-	return val;
-}
-#define __arch_swab16p ld_le16
-
-static __inline__ void st_le16(volatile __u16 *addr, const __u16 val)
-{
-	__asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr));
-}
-
-static inline void __arch_swab16s(__u16 *addr)
-{
-	st_le16(addr, *addr);
-}
-#define __arch_swab16s __arch_swab16s
-
-static __inline__ __u32 ld_le32(const volatile __u32 *addr)
-{
-	__u32 val;
-
-	__asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr));
-	return val;
-}
-#define __arch_swab32p ld_le32
-
-static __inline__ void st_le32(volatile __u32 *addr, const __u32 val)
-{
-	__asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr));
-}
-
-static inline void __arch_swab32s(__u32 *addr)
-{
-	st_le32(addr, *addr);
-}
-#define __arch_swab32s __arch_swab32s
-
-static inline __attribute_const__ __u16 __arch_swab16(__u16 value)
-{
-	__u16 result;
-
-	__asm__("rlwimi %0,%1,8,16,23"
-	    : "=r" (result)
-	    : "r" (value), "0" (value >> 8));
-	return result;
-}
-#define __arch_swab16 __arch_swab16
-
-static inline __attribute_const__ __u32 __arch_swab32(__u32 value)
-{
-	__u32 result;
-
-	__asm__("rlwimi %0,%1,24,16,23\n\t"
-	    "rlwimi %0,%1,8,8,15\n\t"
-	    "rlwimi %0,%1,24,0,7"
-	    : "=r" (result)
-	    : "r" (value), "0" (value >> 24));
-	return result;
-}
-#define __arch_swab32 __arch_swab32
-
-#endif /* __KERNEL__ */
-
-#endif /* __GNUC__ */
-
-#endif /* _ASM_POWERPC_SWAB_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/swiotlb.h b/ANDROID_3.4.5/arch/powerpc/include/asm/swiotlb.h
deleted file mode 100644
index 8979d4cd..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/swiotlb.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Copyright (C) 2009 Becky Bruce, Freescale Semiconductor
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- */
-
-#ifndef __ASM_SWIOTLB_H
-#define __ASM_SWIOTLB_H
-
-#include <linux/swiotlb.h>
-
-extern struct dma_map_ops swiotlb_dma_ops;
-
-static inline void dma_mark_clean(void *addr, size_t size) {}
-
-extern unsigned int ppc_swiotlb_enable;
-int __init swiotlb_setup_bus_notifier(void);
-
-extern void pci_dma_dev_setup_swiotlb(struct pci_dev *pdev);
-
-#endif /* __ASM_SWIOTLB_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/switch_to.h b/ANDROID_3.4.5/arch/powerpc/include/asm/switch_to.h
deleted file mode 100644
index caf82d0a..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/switch_to.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
- */
-#ifndef _ASM_POWERPC_SWITCH_TO_H
-#define _ASM_POWERPC_SWITCH_TO_H
-
-struct thread_struct;
-struct task_struct;
-struct pt_regs;
-
-extern struct task_struct *__switch_to(struct task_struct *,
-	struct task_struct *);
-#define switch_to(prev, next, last)	((last) = __switch_to((prev), (next)))
-
-struct thread_struct;
-extern struct task_struct *_switch(struct thread_struct *prev,
-				   struct thread_struct *next);
-
-extern void giveup_fpu(struct task_struct *);
-extern void disable_kernel_fp(void);
-extern void enable_kernel_fp(void);
-extern void flush_fp_to_thread(struct task_struct *);
-extern void enable_kernel_altivec(void);
-extern void giveup_altivec(struct task_struct *);
-extern void load_up_altivec(struct task_struct *);
-extern int emulate_altivec(struct pt_regs *);
-extern void __giveup_vsx(struct task_struct *);
-extern void giveup_vsx(struct task_struct *);
-extern void enable_kernel_spe(void);
-extern void giveup_spe(struct task_struct *);
-extern void load_up_spe(struct task_struct *);
-
-#ifndef CONFIG_SMP
-extern void discard_lazy_cpu_state(void);
-#else
-static inline void discard_lazy_cpu_state(void)
-{
-}
-#endif
-
-#ifdef CONFIG_ALTIVEC
-extern void flush_altivec_to_thread(struct task_struct *);
-#else
-static inline void flush_altivec_to_thread(struct task_struct *t)
-{
-}
-#endif
-
-#ifdef CONFIG_VSX
-extern void flush_vsx_to_thread(struct task_struct *);
-#else
-static inline void flush_vsx_to_thread(struct task_struct *t)
-{
-}
-#endif
-
-#ifdef CONFIG_SPE
-extern void flush_spe_to_thread(struct task_struct *);
-#else
-static inline void flush_spe_to_thread(struct task_struct *t)
-{
-}
-#endif
-
-#endif /* _ASM_POWERPC_SWITCH_TO_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/synch.h b/ANDROID_3.4.5/arch/powerpc/include/asm/synch.h
deleted file mode 100644
index e682a714..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/synch.h
+++ /dev/null
@@ -1,57 +0,0 @@
-#ifndef _ASM_POWERPC_SYNCH_H 
-#define _ASM_POWERPC_SYNCH_H 
-#ifdef __KERNEL__
-
-#include <linux/stringify.h>
-#include <asm/feature-fixups.h>
-
-#if defined(__powerpc64__) || defined(CONFIG_PPC_E500MC)
-#define __SUBARCH_HAS_LWSYNC
-#endif
-
-#ifndef __ASSEMBLY__
-extern unsigned int __start___lwsync_fixup, __stop___lwsync_fixup;
-extern void do_lwsync_fixups(unsigned long value, void *fixup_start,
-			     void *fixup_end);
-extern void do_final_fixups(void);
-
-static inline void eieio(void)
-{
-	__asm__ __volatile__ ("eieio" : : : "memory");
-}
-
-static inline void isync(void)
-{
-	__asm__ __volatile__ ("isync" : : : "memory");
-}
-#endif /* __ASSEMBLY__ */
-
-#if defined(__powerpc64__)
-#    define LWSYNC	lwsync
-#elif defined(CONFIG_E500)
-#    define LWSYNC					\
-	START_LWSYNC_SECTION(96);			\
-	sync;						\
-	MAKE_LWSYNC_SECTION_ENTRY(96, __lwsync_fixup);
-#else
-#    define LWSYNC	sync
-#endif
-
-#ifdef CONFIG_SMP
-#define __PPC_ACQUIRE_BARRIER				\
-	START_LWSYNC_SECTION(97);			\
-	isync;						\
-	MAKE_LWSYNC_SECTION_ENTRY(97, __lwsync_fixup);
-#define PPC_ACQUIRE_BARRIER	 "\n" stringify_in_c(__PPC_ACQUIRE_BARRIER)
-#define PPC_RELEASE_BARRIER	 stringify_in_c(LWSYNC) "\n"
-#define PPC_ATOMIC_ENTRY_BARRIER "\n" stringify_in_c(LWSYNC) "\n"
-#define PPC_ATOMIC_EXIT_BARRIER	 "\n" stringify_in_c(sync) "\n"
-#else
-#define PPC_ACQUIRE_BARRIER
-#define PPC_RELEASE_BARRIER
-#define PPC_ATOMIC_ENTRY_BARRIER
-#define PPC_ATOMIC_EXIT_BARRIER
-#endif
-
-#endif /* __KERNEL__ */
-#endif	/* _ASM_POWERPC_SYNCH_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/syscall.h b/ANDROID_3.4.5/arch/powerpc/include/asm/syscall.h
deleted file mode 100644
index b54b2add..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/syscall.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * Access to user system call parameters and results
- *
- * Copyright (C) 2008 Red Hat, Inc.  All rights reserved.
- *
- * This copyrighted material is made available to anyone wishing to use,
- * modify, copy, or redistribute it subject to the terms and conditions
- * of the GNU General Public License v.2.
- *
- * See asm-generic/syscall.h for descriptions of what we must do here.
- */
-
-#ifndef _ASM_SYSCALL_H
-#define _ASM_SYSCALL_H	1
-
-#include <linux/sched.h>
-
-/* ftrace syscalls requires exporting the sys_call_table */
-#ifdef CONFIG_FTRACE_SYSCALLS
-extern const unsigned long *sys_call_table;
-#endif /* CONFIG_FTRACE_SYSCALLS */
-
-static inline long syscall_get_nr(struct task_struct *task,
-				  struct pt_regs *regs)
-{
-	return TRAP(regs) == 0xc00 ? regs->gpr[0] : -1L;
-}
-
-static inline void syscall_rollback(struct task_struct *task,
-				    struct pt_regs *regs)
-{
-	regs->gpr[3] = regs->orig_gpr3;
-}
-
-static inline long syscall_get_error(struct task_struct *task,
-				     struct pt_regs *regs)
-{
-	return (regs->ccr & 0x10000000) ? -regs->gpr[3] : 0;
-}
-
-static inline long syscall_get_return_value(struct task_struct *task,
-					    struct pt_regs *regs)
-{
-	return regs->gpr[3];
-}
-
-static inline void syscall_set_return_value(struct task_struct *task,
-					    struct pt_regs *regs,
-					    int error, long val)
-{
-	if (error) {
-		regs->ccr |= 0x10000000L;
-		regs->gpr[3] = -error;
-	} else {
-		regs->ccr &= ~0x10000000L;
-		regs->gpr[3] = val;
-	}
-}
-
-static inline void syscall_get_arguments(struct task_struct *task,
-					 struct pt_regs *regs,
-					 unsigned int i, unsigned int n,
-					 unsigned long *args)
-{
-	BUG_ON(i + n > 6);
-#ifdef CONFIG_PPC64
-	if (test_tsk_thread_flag(task, TIF_32BIT)) {
-		/*
-		 * Zero-extend 32-bit argument values.  The high bits are
-		 * garbage ignored by the actual syscall dispatch.
-		 */
-		while (n-- > 0)
-			args[n] = (u32) regs->gpr[3 + i + n];
-		return;
-	}
-#endif
-	memcpy(args, &regs->gpr[3 + i], n * sizeof(args[0]));
-}
-
-static inline void syscall_set_arguments(struct task_struct *task,
-					 struct pt_regs *regs,
-					 unsigned int i, unsigned int n,
-					 const unsigned long *args)
-{
-	BUG_ON(i + n > 6);
-	memcpy(&regs->gpr[3 + i], args, n * sizeof(args[0]));
-}
-
-#endif	/* _ASM_SYSCALL_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/syscalls.h b/ANDROID_3.4.5/arch/powerpc/include/asm/syscalls.h
deleted file mode 100644
index 4084e567..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/syscalls.h
+++ /dev/null
@@ -1,48 +0,0 @@
-#ifndef __ASM_POWERPC_SYSCALLS_H
-#define __ASM_POWERPC_SYSCALLS_H
-#ifdef __KERNEL__
-
-#include <linux/compiler.h>
-#include <linux/linkage.h>
-#include <linux/types.h>
-#include <asm/signal.h>
-
-struct pt_regs;
-struct rtas_args;
-struct sigaction;
-
-asmlinkage unsigned long sys_mmap(unsigned long addr, size_t len,
-		unsigned long prot, unsigned long flags,
-		unsigned long fd, off_t offset);
-asmlinkage unsigned long sys_mmap2(unsigned long addr, size_t len,
-		unsigned long prot, unsigned long flags,
-		unsigned long fd, unsigned long pgoff);
-asmlinkage int sys_execve(unsigned long a0, unsigned long a1,
-		unsigned long a2, unsigned long a3, unsigned long a4,
-		unsigned long a5, struct pt_regs *regs);
-asmlinkage int sys_clone(unsigned long clone_flags, unsigned long usp,
-		int __user *parent_tidp, void __user *child_threadptr,
-		int __user *child_tidp, int p6, struct pt_regs *regs);
-asmlinkage int sys_fork(unsigned long p1, unsigned long p2,
-		unsigned long p3, unsigned long p4, unsigned long p5,
-		unsigned long p6, struct pt_regs *regs);
-asmlinkage int sys_vfork(unsigned long p1, unsigned long p2,
-		unsigned long p3, unsigned long p4, unsigned long p5,
-		unsigned long p6, struct pt_regs *regs);
-asmlinkage long sys_pipe(int __user *fildes);
-asmlinkage long sys_pipe2(int __user *fildes, int flags);
-asmlinkage long sys_rt_sigaction(int sig,
-		const struct sigaction __user *act,
-		struct sigaction __user *oact, size_t sigsetsize);
-asmlinkage long ppc64_personality(unsigned long personality);
-asmlinkage int ppc_rtas(struct rtas_args __user *uargs);
-asmlinkage time_t sys64_time(time_t __user * tloc);
-
-asmlinkage long sys_rt_sigsuspend(sigset_t __user *unewset,
-		size_t sigsetsize);
-asmlinkage long sys_sigaltstack(const stack_t __user *uss,
-		stack_t __user *uoss, unsigned long r5, unsigned long r6,
-		unsigned long r7, unsigned long r8, struct pt_regs *regs);
-
-#endif /* __KERNEL__ */
-#endif /* __ASM_POWERPC_SYSCALLS_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/systbl.h b/ANDROID_3.4.5/arch/powerpc/include/asm/systbl.h
deleted file mode 100644
index 559ae1ee..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/systbl.h
+++ /dev/null
@@ -1,358 +0,0 @@
-/*
- * List of powerpc syscalls. For the meaning of the _SPU suffix see
- * arch/powerpc/platforms/cell/spu_callbacks.c
- */
-
-SYSCALL(restart_syscall)
-SYSCALL(exit)
-PPC_SYS(fork)
-SYSCALL_SPU(read)
-SYSCALL_SPU(write)
-COMPAT_SYS_SPU(open)
-SYSCALL_SPU(close)
-COMPAT_SYS_SPU(waitpid)
-COMPAT_SYS_SPU(creat)
-SYSCALL_SPU(link)
-SYSCALL_SPU(unlink)
-COMPAT_SYS(execve)
-SYSCALL_SPU(chdir)
-COMPAT_SYS_SPU(time)
-SYSCALL_SPU(mknod)
-SYSCALL_SPU(chmod)
-SYSCALL_SPU(lchown)
-SYSCALL(ni_syscall)
-OLDSYS(stat)
-SYSX_SPU(sys_lseek,ppc32_lseek,sys_lseek)
-SYSCALL_SPU(getpid)
-COMPAT_SYS(mount)
-SYSX(sys_ni_syscall,sys_oldumount,sys_oldumount)
-SYSCALL_SPU(setuid)
-SYSCALL_SPU(getuid)
-COMPAT_SYS_SPU(stime)
-COMPAT_SYS(ptrace)
-SYSCALL_SPU(alarm)
-OLDSYS(fstat)
-SYSCALL(pause)
-COMPAT_SYS(utime)
-SYSCALL(ni_syscall)
-SYSCALL(ni_syscall)
-COMPAT_SYS_SPU(access)
-COMPAT_SYS_SPU(nice)
-SYSCALL(ni_syscall)
-SYSCALL_SPU(sync)
-COMPAT_SYS_SPU(kill)
-SYSCALL_SPU(rename)
-COMPAT_SYS_SPU(mkdir)
-SYSCALL_SPU(rmdir)
-SYSCALL_SPU(dup)
-SYSCALL_SPU(pipe)
-COMPAT_SYS_SPU(times)
-SYSCALL(ni_syscall)
-SYSCALL_SPU(brk)
-SYSCALL_SPU(setgid)
-SYSCALL_SPU(getgid)
-SYSCALL(signal)
-SYSCALL_SPU(geteuid)
-SYSCALL_SPU(getegid)
-SYSCALL(acct)
-SYSCALL(umount)
-SYSCALL(ni_syscall)
-COMPAT_SYS_SPU(ioctl)
-COMPAT_SYS_SPU(fcntl)
-SYSCALL(ni_syscall)
-COMPAT_SYS_SPU(setpgid)
-SYSCALL(ni_syscall)
-SYSX(sys_ni_syscall,sys_olduname, sys_olduname)
-COMPAT_SYS_SPU(umask)
-SYSCALL_SPU(chroot)
-COMPAT_SYS(ustat)
-SYSCALL_SPU(dup2)
-SYSCALL_SPU(getppid)
-SYSCALL_SPU(getpgrp)
-SYSCALL_SPU(setsid)
-SYS32ONLY(sigaction)
-SYSCALL_SPU(sgetmask)
-COMPAT_SYS_SPU(ssetmask)
-SYSCALL_SPU(setreuid)
-SYSCALL_SPU(setregid)
-SYS32ONLY(sigsuspend)
-COMPAT_SYS(sigpending)
-COMPAT_SYS_SPU(sethostname)
-COMPAT_SYS_SPU(setrlimit)
-COMPAT_SYS(old_getrlimit)
-COMPAT_SYS_SPU(getrusage)
-COMPAT_SYS_SPU(gettimeofday)
-COMPAT_SYS_SPU(settimeofday)
-COMPAT_SYS_SPU(getgroups)
-COMPAT_SYS_SPU(setgroups)
-SYSX(sys_ni_syscall,sys_ni_syscall,ppc_select)
-SYSCALL_SPU(symlink)
-OLDSYS(lstat)
-COMPAT_SYS_SPU(readlink)
-SYSCALL(uselib)
-SYSCALL(swapon)
-SYSCALL(reboot)
-SYSX(sys_ni_syscall,compat_sys_old_readdir,sys_old_readdir)
-SYSCALL_SPU(mmap)
-SYSCALL_SPU(munmap)
-COMPAT_SYS_SPU(truncate)
-COMPAT_SYS_SPU(ftruncate)
-SYSCALL_SPU(fchmod)
-SYSCALL_SPU(fchown)
-COMPAT_SYS_SPU(getpriority)
-COMPAT_SYS_SPU(setpriority)
-SYSCALL(ni_syscall)
-COMPAT_SYS(statfs)
-COMPAT_SYS(fstatfs)
-SYSCALL(ni_syscall)
-COMPAT_SYS_SPU(socketcall)
-COMPAT_SYS_SPU(syslog)
-COMPAT_SYS_SPU(setitimer)
-COMPAT_SYS_SPU(getitimer)
-COMPAT_SYS_SPU(newstat)
-COMPAT_SYS_SPU(newlstat)
-COMPAT_SYS_SPU(newfstat)
-SYSX(sys_ni_syscall,sys_uname,sys_uname)
-SYSCALL(ni_syscall)
-SYSCALL_SPU(vhangup)
-SYSCALL(ni_syscall)
-SYSCALL(ni_syscall)
-COMPAT_SYS_SPU(wait4)
-SYSCALL(swapoff)
-COMPAT_SYS_SPU(sysinfo)
-COMPAT_SYS(ipc)
-SYSCALL_SPU(fsync)
-SYS32ONLY(sigreturn)
-PPC_SYS(clone)
-COMPAT_SYS_SPU(setdomainname)
-SYSCALL_SPU(newuname)
-SYSCALL(ni_syscall)
-COMPAT_SYS_SPU(adjtimex)
-SYSCALL_SPU(mprotect)
-SYSX(sys_ni_syscall,compat_sys_sigprocmask,sys_sigprocmask)
-SYSCALL(ni_syscall)
-SYSCALL(init_module)
-SYSCALL(delete_module)
-SYSCALL(ni_syscall)
-SYSCALL(quotactl)
-COMPAT_SYS_SPU(getpgid)
-SYSCALL_SPU(fchdir)
-SYSCALL_SPU(bdflush)
-COMPAT_SYS(sysfs)
-SYSX_SPU(ppc64_personality,ppc64_personality,sys_personality)
-SYSCALL(ni_syscall)
-SYSCALL_SPU(setfsuid)
-SYSCALL_SPU(setfsgid)
-SYSCALL_SPU(llseek)
-COMPAT_SYS_SPU(getdents)
-SYSX_SPU(sys_select,ppc32_select,sys_select)
-SYSCALL_SPU(flock)
-SYSCALL_SPU(msync)
-COMPAT_SYS_SPU(readv)
-COMPAT_SYS_SPU(writev)
-COMPAT_SYS_SPU(getsid)
-SYSCALL_SPU(fdatasync)
-COMPAT_SYS(sysctl)
-SYSCALL_SPU(mlock)
-SYSCALL_SPU(munlock)
-SYSCALL_SPU(mlockall)
-SYSCALL_SPU(munlockall)
-COMPAT_SYS_SPU(sched_setparam)
-COMPAT_SYS_SPU(sched_getparam)
-COMPAT_SYS_SPU(sched_setscheduler)
-COMPAT_SYS_SPU(sched_getscheduler)
-SYSCALL_SPU(sched_yield)
-COMPAT_SYS_SPU(sched_get_priority_max)
-COMPAT_SYS_SPU(sched_get_priority_min)
-COMPAT_SYS_SPU(sched_rr_get_interval)
-COMPAT_SYS_SPU(nanosleep)
-SYSCALL_SPU(mremap)
-SYSCALL_SPU(setresuid)
-SYSCALL_SPU(getresuid)
-SYSCALL(ni_syscall)
-SYSCALL_SPU(poll)
-SYSCALL(ni_syscall)
-SYSCALL_SPU(setresgid)
-SYSCALL_SPU(getresgid)
-COMPAT_SYS_SPU(prctl)
-COMPAT_SYS(rt_sigreturn)
-COMPAT_SYS(rt_sigaction)
-COMPAT_SYS(rt_sigprocmask)
-COMPAT_SYS(rt_sigpending)
-COMPAT_SYS(rt_sigtimedwait)
-COMPAT_SYS(rt_sigqueueinfo)
-COMPAT_SYS(rt_sigsuspend)
-COMPAT_SYS_SPU(pread64)
-COMPAT_SYS_SPU(pwrite64)
-SYSCALL_SPU(chown)
-SYSCALL_SPU(getcwd)
-SYSCALL_SPU(capget)
-SYSCALL_SPU(capset)
-COMPAT_SYS(sigaltstack)
-SYSX_SPU(sys_sendfile64,compat_sys_sendfile,sys_sendfile)
-SYSCALL(ni_syscall)
-SYSCALL(ni_syscall)
-PPC_SYS(vfork)
-COMPAT_SYS_SPU(getrlimit)
-COMPAT_SYS_SPU(readahead)
-SYS32ONLY(mmap2)
-SYS32ONLY(truncate64)
-SYS32ONLY(ftruncate64)
-SYSX(sys_ni_syscall,sys_stat64,sys_stat64)
-SYSX(sys_ni_syscall,sys_lstat64,sys_lstat64)
-SYSX(sys_ni_syscall,sys_fstat64,sys_fstat64)
-SYSCALL(pciconfig_read)
-SYSCALL(pciconfig_write)
-SYSCALL(pciconfig_iobase)
-SYSCALL(ni_syscall)
-SYSCALL_SPU(getdents64)
-SYSCALL_SPU(pivot_root)
-SYSX(sys_ni_syscall,compat_sys_fcntl64,sys_fcntl64)
-SYSCALL_SPU(madvise)
-SYSCALL_SPU(mincore)
-SYSCALL_SPU(gettid)
-SYSCALL_SPU(tkill)
-SYSCALL_SPU(setxattr)
-SYSCALL_SPU(lsetxattr)
-SYSCALL_SPU(fsetxattr)
-SYSCALL_SPU(getxattr)
-SYSCALL_SPU(lgetxattr)
-SYSCALL_SPU(fgetxattr)
-SYSCALL_SPU(listxattr)
-SYSCALL_SPU(llistxattr)
-SYSCALL_SPU(flistxattr)
-SYSCALL_SPU(removexattr)
-SYSCALL_SPU(lremovexattr)
-SYSCALL_SPU(fremovexattr)
-COMPAT_SYS_SPU(futex)
-COMPAT_SYS_SPU(sched_setaffinity)
-COMPAT_SYS_SPU(sched_getaffinity)
-SYSCALL(ni_syscall)
-SYSCALL(ni_syscall)
-SYS32ONLY(sendfile64)
-COMPAT_SYS_SPU(io_setup)
-SYSCALL_SPU(io_destroy)
-COMPAT_SYS_SPU(io_getevents)
-COMPAT_SYS_SPU(io_submit)
-SYSCALL_SPU(io_cancel)
-SYSCALL(set_tid_address)
-SYSX_SPU(sys_fadvise64,ppc32_fadvise64,sys_fadvise64)
-SYSCALL(exit_group)
-SYSX(sys_lookup_dcookie,ppc32_lookup_dcookie,sys_lookup_dcookie)
-SYSCALL_SPU(epoll_create)
-SYSCALL_SPU(epoll_ctl)
-SYSCALL_SPU(epoll_wait)
-SYSCALL_SPU(remap_file_pages)
-SYSX_SPU(sys_timer_create,compat_sys_timer_create,sys_timer_create)
-COMPAT_SYS_SPU(timer_settime)
-COMPAT_SYS_SPU(timer_gettime)
-SYSCALL_SPU(timer_getoverrun)
-SYSCALL_SPU(timer_delete)
-COMPAT_SYS_SPU(clock_settime)
-COMPAT_SYS_SPU(clock_gettime)
-COMPAT_SYS_SPU(clock_getres)
-COMPAT_SYS_SPU(clock_nanosleep)
-SYSX(ppc64_swapcontext,ppc32_swapcontext,ppc_swapcontext)
-COMPAT_SYS_SPU(tgkill)
-COMPAT_SYS_SPU(utimes)
-COMPAT_SYS_SPU(statfs64)
-COMPAT_SYS_SPU(fstatfs64)
-SYSX(sys_ni_syscall, ppc_fadvise64_64, ppc_fadvise64_64)
-PPC_SYS_SPU(rtas)
-OLDSYS(debug_setcontext)
-SYSCALL(ni_syscall)
-COMPAT_SYS(migrate_pages)
-COMPAT_SYS(mbind)
-COMPAT_SYS(get_mempolicy)
-COMPAT_SYS(set_mempolicy)
-COMPAT_SYS(mq_open)
-SYSCALL(mq_unlink)
-COMPAT_SYS(mq_timedsend)
-COMPAT_SYS(mq_timedreceive)
-COMPAT_SYS(mq_notify)
-COMPAT_SYS(mq_getsetattr)
-COMPAT_SYS(kexec_load)
-COMPAT_SYS(add_key)
-COMPAT_SYS(request_key)
-COMPAT_SYS(keyctl)
-COMPAT_SYS(waitid)
-COMPAT_SYS(ioprio_set)
-COMPAT_SYS(ioprio_get)
-SYSCALL(inotify_init)
-SYSCALL(inotify_add_watch)
-SYSCALL(inotify_rm_watch)
-SYSCALL(spu_run)
-SYSCALL(spu_create)
-COMPAT_SYS(pselect6)
-COMPAT_SYS(ppoll)
-SYSCALL_SPU(unshare)
-SYSCALL_SPU(splice)
-SYSCALL_SPU(tee)
-COMPAT_SYS_SPU(vmsplice)
-COMPAT_SYS_SPU(openat)
-SYSCALL_SPU(mkdirat)
-SYSCALL_SPU(mknodat)
-SYSCALL_SPU(fchownat)
-COMPAT_SYS_SPU(futimesat)
-SYSX_SPU(sys_newfstatat, sys_fstatat64, sys_fstatat64)
-SYSCALL_SPU(unlinkat)
-SYSCALL_SPU(renameat)
-SYSCALL_SPU(linkat)
-SYSCALL_SPU(symlinkat)
-SYSCALL_SPU(readlinkat)
-SYSCALL_SPU(fchmodat)
-SYSCALL_SPU(faccessat)
-COMPAT_SYS_SPU(get_robust_list)
-COMPAT_SYS_SPU(set_robust_list)
-COMPAT_SYS_SPU(move_pages)
-SYSCALL_SPU(getcpu)
-COMPAT_SYS(epoll_pwait)
-COMPAT_SYS_SPU(utimensat)
-COMPAT_SYS_SPU(signalfd)
-SYSCALL_SPU(timerfd_create)
-SYSCALL_SPU(eventfd)
-COMPAT_SYS_SPU(sync_file_range2)
-COMPAT_SYS(fallocate)
-SYSCALL(subpage_prot)
-COMPAT_SYS_SPU(timerfd_settime)
-COMPAT_SYS_SPU(timerfd_gettime)
-COMPAT_SYS_SPU(signalfd4)
-SYSCALL_SPU(eventfd2)
-SYSCALL_SPU(epoll_create1)
-SYSCALL_SPU(dup3)
-SYSCALL_SPU(pipe2)
-SYSCALL(inotify_init1)
-SYSCALL_SPU(perf_event_open)
-COMPAT_SYS_SPU(preadv)
-COMPAT_SYS_SPU(pwritev)
-COMPAT_SYS(rt_tgsigqueueinfo)
-SYSCALL(fanotify_init)
-COMPAT_SYS(fanotify_mark)
-SYSCALL_SPU(prlimit64)
-SYSCALL_SPU(socket)
-SYSCALL_SPU(bind)
-SYSCALL_SPU(connect)
-SYSCALL_SPU(listen)
-SYSCALL_SPU(accept)
-SYSCALL_SPU(getsockname)
-SYSCALL_SPU(getpeername)
-SYSCALL_SPU(socketpair)
-SYSCALL_SPU(send)
-SYSCALL_SPU(sendto)
-COMPAT_SYS_SPU(recv)
-COMPAT_SYS_SPU(recvfrom)
-SYSCALL_SPU(shutdown)
-COMPAT_SYS_SPU(setsockopt)
-COMPAT_SYS_SPU(getsockopt)
-COMPAT_SYS_SPU(sendmsg)
-COMPAT_SYS_SPU(recvmsg)
-COMPAT_SYS_SPU(recvmmsg)
-SYSCALL_SPU(accept4)
-SYSCALL_SPU(name_to_handle_at)
-COMPAT_SYS_SPU(open_by_handle_at)
-COMPAT_SYS_SPU(clock_adjtime)
-SYSCALL_SPU(syncfs)
-COMPAT_SYS_SPU(sendmmsg)
-SYSCALL_SPU(setns)
-COMPAT_SYS(process_vm_readv)
-COMPAT_SYS(process_vm_writev)
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/tce.h b/ANDROID_3.4.5/arch/powerpc/include/asm/tce.h
deleted file mode 100644
index 743f36b3..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/tce.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
- * Rewrite, cleanup:
- * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-
-#ifndef _ASM_POWERPC_TCE_H
-#define _ASM_POWERPC_TCE_H
-#ifdef __KERNEL__
-
-#include <asm/iommu.h>
-
-/*
- * Tces come in two formats, one for the virtual bus and a different
- * format for PCI.  PCI TCEs can have hardware or software maintianed
- * coherency.
- */
-#define TCE_VB			0
-#define TCE_PCI			1
-#define TCE_PCI_SWINV_CREATE	2
-#define TCE_PCI_SWINV_FREE	4
-#define TCE_PCI_SWINV_PAIR	8
-
-/* TCE page size is 4096 bytes (1 << 12) */
-
-#define TCE_SHIFT	12
-#define TCE_PAGE_SIZE	(1 << TCE_SHIFT)
-
-#define TCE_ENTRY_SIZE		8		/* each TCE is 64 bits */
-
-#define TCE_RPN_MASK		0xfffffffffful  /* 40-bit RPN (4K pages) */
-#define TCE_RPN_SHIFT		12
-#define TCE_VALID		0x800		/* TCE valid */
-#define TCE_ALLIO		0x400		/* TCE valid for all lpars */
-#define TCE_PCI_WRITE		0x2		/* write from PCI allowed */
-#define TCE_PCI_READ		0x1		/* read from PCI allowed */
-#define TCE_VB_WRITE		0x1		/* write from VB allowed */
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_TCE_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/termbits.h b/ANDROID_3.4.5/arch/powerpc/include/asm/termbits.h
deleted file mode 100644
index 549d700e..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/termbits.h
+++ /dev/null
@@ -1,210 +0,0 @@
-#ifndef _ASM_POWERPC_TERMBITS_H
-#define _ASM_POWERPC_TERMBITS_H
-
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-typedef unsigned char	cc_t;
-typedef unsigned int	speed_t;
-typedef unsigned int	tcflag_t;
-
-/*
- * termios type and macro definitions.  Be careful about adding stuff
- * to this file since it's used in GNU libc and there are strict rules
- * concerning namespace pollution.
- */
-
-#define NCCS 19
-struct termios {
-	tcflag_t c_iflag;		/* input mode flags */
-	tcflag_t c_oflag;		/* output mode flags */
-	tcflag_t c_cflag;		/* control mode flags */
-	tcflag_t c_lflag;		/* local mode flags */
-	cc_t c_cc[NCCS];		/* control characters */
-	cc_t c_line;			/* line discipline (== c_cc[19]) */
-	speed_t c_ispeed;		/* input speed */
-	speed_t c_ospeed;		/* output speed */
-};
-
-/* For PowerPC the termios and ktermios are the same */
-
-struct ktermios {
-	tcflag_t c_iflag;		/* input mode flags */
-	tcflag_t c_oflag;		/* output mode flags */
-	tcflag_t c_cflag;		/* control mode flags */
-	tcflag_t c_lflag;		/* local mode flags */
-	cc_t c_cc[NCCS];		/* control characters */
-	cc_t c_line;			/* line discipline (== c_cc[19]) */
-	speed_t c_ispeed;		/* input speed */
-	speed_t c_ospeed;		/* output speed */
-};
-
-/* c_cc characters */
-#define VINTR 	         0
-#define VQUIT 	         1
-#define VERASE 	         2
-#define VKILL	         3
-#define VEOF	         4
-#define VMIN	         5
-#define VEOL	         6
-#define VTIME	         7
-#define VEOL2	         8
-#define VSWTC	         9
-#define VWERASE 	10
-#define VREPRINT	11
-#define VSUSP 		12
-#define VSTART		13
-#define VSTOP		14
-#define VLNEXT		15
-#define VDISCARD	16
-
-/* c_iflag bits */
-#define IGNBRK	0000001
-#define BRKINT	0000002
-#define IGNPAR	0000004
-#define PARMRK	0000010
-#define INPCK	0000020
-#define ISTRIP	0000040
-#define INLCR	0000100
-#define IGNCR	0000200
-#define ICRNL	0000400
-#define IXON	0001000
-#define IXOFF	0002000
-#define IXANY	0004000
-#define IUCLC	0010000
-#define IMAXBEL	0020000
-#define	IUTF8	0040000
-
-/* c_oflag bits */
-#define OPOST	0000001
-#define ONLCR	0000002
-#define OLCUC	0000004
-
-#define OCRNL	0000010
-#define ONOCR	0000020
-#define ONLRET	0000040
-
-#define OFILL	00000100
-#define OFDEL	00000200
-#define NLDLY	00001400
-#define   NL0	00000000
-#define   NL1	00000400
-#define   NL2	00001000
-#define   NL3	00001400
-#define TABDLY	00006000
-#define   TAB0	00000000
-#define   TAB1	00002000
-#define   TAB2	00004000
-#define   TAB3	00006000
-#define   XTABS	00006000	/* required by POSIX to == TAB3 */
-#define CRDLY	00030000
-#define   CR0	00000000
-#define   CR1	00010000
-#define   CR2	00020000
-#define   CR3	00030000
-#define FFDLY	00040000
-#define   FF0	00000000
-#define   FF1	00040000
-#define BSDLY	00100000
-#define   BS0	00000000
-#define   BS1	00100000
-#define VTDLY	00200000
-#define   VT0	00000000
-#define   VT1	00200000
-
-/* c_cflag bit meaning */
-#define CBAUD	0000377
-#define  B0	0000000		/* hang up */
-#define  B50	0000001
-#define  B75	0000002
-#define  B110	0000003
-#define  B134	0000004
-#define  B150	0000005
-#define  B200	0000006
-#define  B300	0000007
-#define  B600	0000010
-#define  B1200	0000011
-#define  B1800	0000012
-#define  B2400	0000013
-#define  B4800	0000014
-#define  B9600	0000015
-#define  B19200	0000016
-#define  B38400	0000017
-#define  EXTA   B19200
-#define  EXTB   B38400
-#define  CBAUDEX 0000000
-#define  B57600   00020
-#define  B115200  00021
-#define  B230400  00022
-#define  B460800  00023
-#define  B500000  00024
-#define  B576000  00025
-#define  B921600  00026
-#define B1000000  00027
-#define B1152000  00030
-#define B1500000  00031
-#define B2000000  00032
-#define B2500000  00033
-#define B3000000  00034
-#define B3500000  00035
-#define B4000000  00036
-#define   BOTHER  00037
-
-#define CIBAUD	077600000
-#define IBSHIFT	16		/* Shift from CBAUD to CIBAUD */
-
-#define CSIZE	00001400
-#define   CS5	00000000
-#define   CS6	00000400
-#define   CS7	00001000
-#define   CS8	00001400
-
-#define CSTOPB	00002000
-#define CREAD	00004000
-#define PARENB	00010000
-#define PARODD	00020000
-#define HUPCL	00040000
-
-#define CLOCAL	00100000
-#define CMSPAR	  010000000000		/* mark or space (stick) parity */
-#define CRTSCTS	  020000000000		/* flow control */
-
-/* c_lflag bits */
-#define ISIG	0x00000080
-#define ICANON	0x00000100
-#define XCASE	0x00004000
-#define ECHO	0x00000008
-#define ECHOE	0x00000002
-#define ECHOK	0x00000004
-#define ECHONL	0x00000010
-#define NOFLSH	0x80000000
-#define TOSTOP	0x00400000
-#define ECHOCTL	0x00000040
-#define ECHOPRT	0x00000020
-#define ECHOKE	0x00000001
-#define FLUSHO	0x00800000
-#define PENDIN	0x20000000
-#define IEXTEN	0x00000400
-#define EXTPROC	0x10000000
-
-/* Values for the ACTION argument to `tcflow'.  */
-#define	TCOOFF		0
-#define	TCOON		1
-#define	TCIOFF		2
-#define	TCION		3
-
-/* Values for the QUEUE_SELECTOR argument to `tcflush'.  */
-#define	TCIFLUSH	0
-#define	TCOFLUSH	1
-#define	TCIOFLUSH	2
-
-/* Values for the OPTIONAL_ACTIONS argument to `tcsetattr'.  */
-#define	TCSANOW		0
-#define	TCSADRAIN	1
-#define	TCSAFLUSH	2
-
-#endif	/* _ASM_POWERPC_TERMBITS_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/termios.h b/ANDROID_3.4.5/arch/powerpc/include/asm/termios.h
deleted file mode 100644
index a24f4870..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/termios.h
+++ /dev/null
@@ -1,85 +0,0 @@
-#ifndef _ASM_POWERPC_TERMIOS_H
-#define _ASM_POWERPC_TERMIOS_H
-
-/*
- * Liberally adapted from alpha/termios.h.  In particular, the c_cc[]
- * fields have been reordered so that termio & termios share the
- * common subset in the same order (for brain dead programs that don't
- * know or care about the differences).
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <asm/ioctls.h>
-#include <asm/termbits.h>
-
-struct sgttyb {
-	char	sg_ispeed;
-	char	sg_ospeed;
-	char	sg_erase;
-	char	sg_kill;
-	short	sg_flags;
-};
-
-struct tchars {
-	char	t_intrc;
-	char	t_quitc;
-	char	t_startc;
-	char	t_stopc;
-	char	t_eofc;
-	char	t_brkc;
-};
-
-struct ltchars {
-	char	t_suspc;
-	char	t_dsuspc;
-	char	t_rprntc;
-	char	t_flushc;
-	char	t_werasc;
-	char	t_lnextc;
-};
-
-struct winsize {
-	unsigned short ws_row;
-	unsigned short ws_col;
-	unsigned short ws_xpixel;
-	unsigned short ws_ypixel;
-};
-
-#define NCC 10
-struct termio {
-	unsigned short c_iflag;		/* input mode flags */
-	unsigned short c_oflag;		/* output mode flags */
-	unsigned short c_cflag;		/* control mode flags */
-	unsigned short c_lflag;		/* local mode flags */
-	unsigned char c_line;		/* line discipline */
-	unsigned char c_cc[NCC];	/* control characters */
-};
-
-/* c_cc characters */
-#define _VINTR	0
-#define _VQUIT	1
-#define _VERASE	2
-#define _VKILL	3
-#define _VEOF	4
-#define _VMIN	5
-#define _VEOL	6
-#define _VTIME	7
-#define _VEOL2	8
-#define _VSWTC	9
-
-#ifdef __KERNEL__
-/*                   ^C  ^\ del  ^U  ^D   1   0   0   0   0  ^W  ^R  ^Z  ^Q  ^S  ^V  ^U  */
-#define INIT_C_CC "\003\034\177\025\004\001\000\000\000\000\027\022\032\021\023\026\025" 
-#endif
-
-#ifdef __KERNEL__
-
-#include <asm-generic/termios-base.h>
-
-#endif	/* __KERNEL__ */
-
-#endif	/* _ASM_POWERPC_TERMIOS_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/thread_info.h b/ANDROID_3.4.5/arch/powerpc/include/asm/thread_info.h
deleted file mode 100644
index 4a741c7e..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/thread_info.h
+++ /dev/null
@@ -1,176 +0,0 @@
-/* thread_info.h: PowerPC low-level thread information
- * adapted from the i386 version by Paul Mackerras
- *
- * Copyright (C) 2002  David Howells (dhowells@redhat.com)
- * - Incorporating suggestions made by Linus Torvalds and Dave Miller
- */
-
-#ifndef _ASM_POWERPC_THREAD_INFO_H
-#define _ASM_POWERPC_THREAD_INFO_H
-
-#ifdef __KERNEL__
-
-/* We have 8k stacks on ppc32 and 16k on ppc64 */
-
-#if defined(CONFIG_PPC64)
-#define THREAD_SHIFT		14
-#elif defined(CONFIG_PPC_256K_PAGES)
-#define THREAD_SHIFT		15
-#else
-#define THREAD_SHIFT		13
-#endif
-
-#define THREAD_SIZE		(1 << THREAD_SHIFT)
-
-#ifndef __ASSEMBLY__
-#include <linux/cache.h>
-#include <asm/processor.h>
-#include <asm/page.h>
-#include <linux/stringify.h>
-
-/*
- * low level task data.
- */
-struct thread_info {
-	struct task_struct *task;		/* main task structure */
-	struct exec_domain *exec_domain;	/* execution domain */
-	int		cpu;			/* cpu we're on */
-	int		preempt_count;		/* 0 => preemptable,
-						   <0 => BUG */
-	struct restart_block restart_block;
-	unsigned long	local_flags;		/* private flags for thread */
-
-	/* low level flags - has atomic operations done on it */
-	unsigned long	flags ____cacheline_aligned_in_smp;
-};
-
-/*
- * macros/functions for gaining access to the thread information structure
- */
-#define INIT_THREAD_INFO(tsk)			\
-{						\
-	.task =		&tsk,			\
-	.exec_domain =	&default_exec_domain,	\
-	.cpu =		0,			\
-	.preempt_count = INIT_PREEMPT_COUNT,	\
-	.restart_block = {			\
-		.fn = do_no_restart_syscall,	\
-	},					\
-	.flags =	0,			\
-}
-
-#define init_thread_info	(init_thread_union.thread_info)
-#define init_stack		(init_thread_union.stack)
-
-/* thread information allocation */
-
-#if THREAD_SHIFT >= PAGE_SHIFT
-
-#define THREAD_SIZE_ORDER	(THREAD_SHIFT - PAGE_SHIFT)
-
-#else /* THREAD_SHIFT < PAGE_SHIFT */
-
-#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
-
-extern struct thread_info *alloc_thread_info_node(struct task_struct *tsk, int node);
-extern void free_thread_info(struct thread_info *ti);
-
-#endif /* THREAD_SHIFT < PAGE_SHIFT */
-
-/* how to get the thread information struct from C */
-static inline struct thread_info *current_thread_info(void)
-{
-	register unsigned long sp asm("r1");
-
-	/* gcc4, at least, is smart enough to turn this into a single
-	 * rlwinm for ppc32 and clrrdi for ppc64 */
-	return (struct thread_info *)(sp & ~(THREAD_SIZE-1));
-}
-
-#endif /* __ASSEMBLY__ */
-
-#define PREEMPT_ACTIVE		0x10000000
-
-/*
- * thread information flag bit numbers
- */
-#define TIF_SYSCALL_TRACE	0	/* syscall trace active */
-#define TIF_SIGPENDING		1	/* signal pending */
-#define TIF_NEED_RESCHED	2	/* rescheduling necessary */
-#define TIF_POLLING_NRFLAG	3	/* true if poll_idle() is polling
-					   TIF_NEED_RESCHED */
-#define TIF_32BIT		4	/* 32 bit binary */
-#define TIF_PERFMON_WORK	5	/* work for pfm_handle_work() */
-#define TIF_PERFMON_CTXSW	6	/* perfmon needs ctxsw calls */
-#define TIF_SYSCALL_AUDIT	7	/* syscall auditing active */
-#define TIF_SINGLESTEP		8	/* singlestepping active */
-#define TIF_MEMDIE		9	/* is terminating due to OOM killer */
-#define TIF_SECCOMP		10	/* secure computing */
-#define TIF_RESTOREALL		11	/* Restore all regs (implies NOERROR) */
-#define TIF_NOERROR		12	/* Force successful syscall return */
-#define TIF_NOTIFY_RESUME	13	/* callback before returning to user */
-#define TIF_SYSCALL_TRACEPOINT	15	/* syscall tracepoint instrumentation */
-
-/* as above, but as bit values */
-#define _TIF_SYSCALL_TRACE	(1<<TIF_SYSCALL_TRACE)
-#define _TIF_SIGPENDING		(1<<TIF_SIGPENDING)
-#define _TIF_NEED_RESCHED	(1<<TIF_NEED_RESCHED)
-#define _TIF_POLLING_NRFLAG	(1<<TIF_POLLING_NRFLAG)
-#define _TIF_32BIT		(1<<TIF_32BIT)
-#define _TIF_PERFMON_WORK	(1<<TIF_PERFMON_WORK)
-#define _TIF_PERFMON_CTXSW	(1<<TIF_PERFMON_CTXSW)
-#define _TIF_SYSCALL_AUDIT	(1<<TIF_SYSCALL_AUDIT)
-#define _TIF_SINGLESTEP		(1<<TIF_SINGLESTEP)
-#define _TIF_SECCOMP		(1<<TIF_SECCOMP)
-#define _TIF_RESTOREALL		(1<<TIF_RESTOREALL)
-#define _TIF_NOERROR		(1<<TIF_NOERROR)
-#define _TIF_NOTIFY_RESUME	(1<<TIF_NOTIFY_RESUME)
-#define _TIF_SYSCALL_TRACEPOINT	(1<<TIF_SYSCALL_TRACEPOINT)
-#define _TIF_RUNLATCH		(1<<TIF_RUNLATCH)
-#define _TIF_SYSCALL_T_OR_A	(_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | \
-				 _TIF_SECCOMP | _TIF_SYSCALL_TRACEPOINT)
-
-#define _TIF_USER_WORK_MASK	(_TIF_SIGPENDING | _TIF_NEED_RESCHED | \
-				 _TIF_NOTIFY_RESUME)
-#define _TIF_PERSYSCALL_MASK	(_TIF_RESTOREALL|_TIF_NOERROR)
-
-/* Bits in local_flags */
-/* Don't move TLF_NAPPING without adjusting the code in entry_32.S */
-#define TLF_NAPPING		0	/* idle thread enabled NAP mode */
-#define TLF_SLEEPING		1	/* suspend code enabled SLEEP mode */
-#define TLF_RESTORE_SIGMASK	2	/* Restore signal mask in do_signal */
-#define TLF_LAZY_MMU		3	/* tlb_batch is active */
-#define TLF_RUNLATCH		4	/* Is the runlatch enabled? */
-
-#define _TLF_NAPPING		(1 << TLF_NAPPING)
-#define _TLF_SLEEPING		(1 << TLF_SLEEPING)
-#define _TLF_RESTORE_SIGMASK	(1 << TLF_RESTORE_SIGMASK)
-#define _TLF_LAZY_MMU		(1 << TLF_LAZY_MMU)
-#define _TLF_RUNLATCH		(1 << TLF_RUNLATCH)
-
-#ifndef __ASSEMBLY__
-#define HAVE_SET_RESTORE_SIGMASK	1
-static inline void set_restore_sigmask(void)
-{
-	struct thread_info *ti = current_thread_info();
-	ti->local_flags |= _TLF_RESTORE_SIGMASK;
-	set_bit(TIF_SIGPENDING, &ti->flags);
-}
-
-static inline bool test_thread_local_flags(unsigned int flags)
-{
-	struct thread_info *ti = current_thread_info();
-	return (ti->local_flags & flags) != 0;
-}
-
-#ifdef CONFIG_PPC64
-#define is_32bit_task()	(test_thread_flag(TIF_32BIT))
-#else
-#define is_32bit_task()	(1)
-#endif
-
-#endif	/* !__ASSEMBLY__ */
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_POWERPC_THREAD_INFO_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/time.h b/ANDROID_3.4.5/arch/powerpc/include/asm/time.h
deleted file mode 100644
index 2136f58a..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/time.h
+++ /dev/null
@@ -1,210 +0,0 @@
-/*
- * Common time prototypes and such for all ppc machines.
- *
- * Written by Cort Dougan (cort@cs.nmt.edu) to merge
- * Paul Mackerras' version and mine for PReP and Pmac.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef __POWERPC_TIME_H
-#define __POWERPC_TIME_H
-
-#ifdef __KERNEL__
-#include <linux/types.h>
-#include <linux/percpu.h>
-
-#include <asm/processor.h>
-
-/* time.c */
-extern unsigned long tb_ticks_per_jiffy;
-extern unsigned long tb_ticks_per_usec;
-extern unsigned long tb_ticks_per_sec;
-
-struct rtc_time;
-extern void to_tm(int tim, struct rtc_time * tm);
-extern void GregorianDay(struct rtc_time *tm);
-
-extern void generic_calibrate_decr(void);
-
-extern void set_dec_cpu6(unsigned int val);
-
-/* Some sane defaults: 125 MHz timebase, 1GHz processor */
-extern unsigned long ppc_proc_freq;
-#define DEFAULT_PROC_FREQ	(DEFAULT_TB_FREQ * 8)
-extern unsigned long ppc_tb_freq;
-#define DEFAULT_TB_FREQ		125000000UL
-
-struct div_result {
-	u64 result_high;
-	u64 result_low;
-};
-
-/* Accessor functions for the timebase (RTC on 601) registers. */
-/* If one day CONFIG_POWER is added just define __USE_RTC as 1 */
-#ifdef CONFIG_6xx
-#define __USE_RTC()	(!cpu_has_feature(CPU_FTR_USE_TB))
-#else
-#define __USE_RTC()	0
-#endif
-
-#ifdef CONFIG_PPC64
-
-/* For compatibility, get_tbl() is defined as get_tb() on ppc64 */
-#define get_tbl		get_tb
-
-#else
-
-static inline unsigned long get_tbl(void)
-{
-#if defined(CONFIG_403GCX)
-	unsigned long tbl;
-	asm volatile("mfspr %0, 0x3dd" : "=r" (tbl));
-	return tbl;
-#else
-	return mftbl();
-#endif
-}
-
-static inline unsigned int get_tbu(void)
-{
-#ifdef CONFIG_403GCX
-	unsigned int tbu;
-	asm volatile("mfspr %0, 0x3dc" : "=r" (tbu));
-	return tbu;
-#else
-	return mftbu();
-#endif
-}
-#endif /* !CONFIG_PPC64 */
-
-static inline unsigned int get_rtcl(void)
-{
-	unsigned int rtcl;
-
-	asm volatile("mfrtcl %0" : "=r" (rtcl));
-	return rtcl;
-}
-
-static inline u64 get_rtc(void)
-{
-	unsigned int hi, lo, hi2;
-
-	do {
-		asm volatile("mfrtcu %0; mfrtcl %1; mfrtcu %2"
-			     : "=r" (hi), "=r" (lo), "=r" (hi2));
-	} while (hi2 != hi);
-	return (u64)hi * 1000000000 + lo;
-}
-
-#ifdef CONFIG_PPC64
-static inline u64 get_tb(void)
-{
-	return mftb();
-}
-#else /* CONFIG_PPC64 */
-static inline u64 get_tb(void)
-{
-	unsigned int tbhi, tblo, tbhi2;
-
-	do {
-		tbhi = get_tbu();
-		tblo = get_tbl();
-		tbhi2 = get_tbu();
-	} while (tbhi != tbhi2);
-
-	return ((u64)tbhi << 32) | tblo;
-}
-#endif /* !CONFIG_PPC64 */
-
-static inline u64 get_tb_or_rtc(void)
-{
-	return __USE_RTC() ? get_rtc() : get_tb();
-}
-
-static inline void set_tb(unsigned int upper, unsigned int lower)
-{
-	mtspr(SPRN_TBWL, 0);
-	mtspr(SPRN_TBWU, upper);
-	mtspr(SPRN_TBWL, lower);
-}
-
-/* Accessor functions for the decrementer register.
- * The 4xx doesn't even have a decrementer.  I tried to use the
- * generic timer interrupt code, which seems OK, with the 4xx PIT
- * in auto-reload mode.  The problem is PIT stops counting when it
- * hits zero.  If it would wrap, we could use it just like a decrementer.
- */
-static inline unsigned int get_dec(void)
-{
-#if defined(CONFIG_40x)
-	return (mfspr(SPRN_PIT));
-#else
-	return (mfspr(SPRN_DEC));
-#endif
-}
-
-/*
- * Note: Book E and 4xx processors differ from other PowerPC processors
- * in when the decrementer generates its interrupt: on the 1 to 0
- * transition for Book E/4xx, but on the 0 to -1 transition for others.
- */
-static inline void set_dec(int val)
-{
-#if defined(CONFIG_40x)
-	mtspr(SPRN_PIT, val);
-#elif defined(CONFIG_8xx_CPU6)
-	set_dec_cpu6(val - 1);
-#else
-#ifndef CONFIG_BOOKE
-	--val;
-#endif
-	mtspr(SPRN_DEC, val);
-#endif /* not 40x or 8xx_CPU6 */
-}
-
-static inline unsigned long tb_ticks_since(unsigned long tstamp)
-{
-	if (__USE_RTC()) {
-		int delta = get_rtcl() - (unsigned int) tstamp;
-		return delta < 0 ? delta + 1000000000 : delta;
-	}
-	return get_tbl() - tstamp;
-}
-
-#define mulhwu(x,y) \
-({unsigned z; asm ("mulhwu %0,%1,%2" : "=r" (z) : "r" (x), "r" (y)); z;})
-
-#ifdef CONFIG_PPC64
-#define mulhdu(x,y) \
-({unsigned long z; asm ("mulhdu %0,%1,%2" : "=r" (z) : "r" (x), "r" (y)); z;})
-#else
-extern u64 mulhdu(u64, u64);
-#endif
-
-extern void div128_by_32(u64 dividend_high, u64 dividend_low,
-			 unsigned divisor, struct div_result *dr);
-
-/* Used to store Processor Utilization register (purr) values */
-
-struct cpu_usage {
-        u64 current_tb;  /* Holds the current purr register values */
-};
-
-DECLARE_PER_CPU(struct cpu_usage, cpu_usage_array);
-
-#if defined(CONFIG_VIRT_CPU_ACCOUNTING)
-#define account_process_vtime(tsk)		account_process_tick(tsk, 0)
-#else
-#define account_process_vtime(tsk)		do { } while (0)
-#endif
-
-extern void secondary_cpu_time_init(void);
-
-DECLARE_PER_CPU(u64, decrementers_next_tb);
-
-#endif /* __KERNEL__ */
-#endif /* __POWERPC_TIME_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/timex.h b/ANDROID_3.4.5/arch/powerpc/include/asm/timex.h
deleted file mode 100644
index c55e14f7..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/timex.h
+++ /dev/null
@@ -1,50 +0,0 @@
-#ifndef _ASM_POWERPC_TIMEX_H
-#define _ASM_POWERPC_TIMEX_H
-
-#ifdef __KERNEL__
-
-/*
- * PowerPC architecture timex specifications
- */
-
-#include <asm/cputable.h>
-#include <asm/reg.h>
-
-#define CLOCK_TICK_RATE	1024000 /* Underlying HZ */
-
-typedef unsigned long cycles_t;
-
-static inline cycles_t get_cycles(void)
-{
-#ifdef __powerpc64__
-	return mftb();
-#else
-	cycles_t ret;
-
-	/*
-	 * For the "cycle" counter we use the timebase lower half.
-	 * Currently only used on SMP.
-	 */
-
-	ret = 0;
-
-	__asm__ __volatile__(
-		"97:	mftb %0\n"
-		"99:\n"
-		".section __ftr_fixup,\"a\"\n"
-		".align 2\n"
-		"98:\n"
-		"	.long %1\n"
-		"	.long 0\n"
-		"	.long 97b-98b\n"
-		"	.long 99b-98b\n"
-		"	.long 0\n"
-		"	.long 0\n"
-		".previous"
-		: "=r" (ret) : "i" (CPU_FTR_601));
-	return ret;
-#endif
-}
-
-#endif	/* __KERNEL__ */
-#endif	/* _ASM_POWERPC_TIMEX_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/tlb.h b/ANDROID_3.4.5/arch/powerpc/include/asm/tlb.h
deleted file mode 100644
index e2b428b0..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/tlb.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- *	TLB shootdown specifics for powerpc
- *
- * Copyright (C) 2002 Anton Blanchard, IBM Corp.
- * Copyright (C) 2002 Paul Mackerras, IBM Corp.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef _ASM_POWERPC_TLB_H
-#define _ASM_POWERPC_TLB_H
-#ifdef __KERNEL__
-
-#ifndef __powerpc64__
-#include <asm/pgtable.h>
-#endif
-#include <asm/pgalloc.h>
-#include <asm/tlbflush.h>
-#ifndef __powerpc64__
-#include <asm/page.h>
-#include <asm/mmu.h>
-#endif
-
-#include <linux/pagemap.h>
-
-#define tlb_start_vma(tlb, vma)	do { } while (0)
-#define tlb_end_vma(tlb, vma)	do { } while (0)
-
-extern void tlb_flush(struct mmu_gather *tlb);
-
-/* Get the generic bits... */
-#include <asm-generic/tlb.h>
-
-extern void flush_hash_entry(struct mm_struct *mm, pte_t *ptep,
-			     unsigned long address);
-
-static inline void __tlb_remove_tlb_entry(struct mmu_gather *tlb, pte_t *ptep,
-					  unsigned long address)
-{
-#ifdef CONFIG_PPC_STD_MMU_32
-	if (pte_val(*ptep) & _PAGE_HASHPTE)
-		flush_hash_entry(tlb->mm, ptep, address);
-#endif
-}
-
-#endif /* __KERNEL__ */
-#endif /* __ASM_POWERPC_TLB_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/tlbflush.h b/ANDROID_3.4.5/arch/powerpc/include/asm/tlbflush.h
deleted file mode 100644
index 81143fcb..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/tlbflush.h
+++ /dev/null
@@ -1,177 +0,0 @@
-#ifndef _ASM_POWERPC_TLBFLUSH_H
-#define _ASM_POWERPC_TLBFLUSH_H
-
-/*
- * TLB flushing:
- *
- *  - flush_tlb_mm(mm) flushes the specified mm context TLB's
- *  - flush_tlb_page(vma, vmaddr) flushes one page
- *  - local_flush_tlb_mm(mm, full) flushes the specified mm context on
- *                           the local processor
- *  - local_flush_tlb_page(vma, vmaddr) flushes one page on the local processor
- *  - flush_tlb_page_nohash(vma, vmaddr) flushes one page if SW loaded TLB
- *  - flush_tlb_range(vma, start, end) flushes a range of pages
- *  - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
- *
- *  This program is free software; you can redistribute it and/or
- *  modify it under the terms of the GNU General Public License
- *  as published by the Free Software Foundation; either version
- *  2 of the License, or (at your option) any later version.
- */
-#ifdef __KERNEL__
-
-#ifdef CONFIG_PPC_MMU_NOHASH
-/*
- * TLB flushing for software loaded TLB chips
- *
- * TODO: (CONFIG_FSL_BOOKE) determine if flush_tlb_range &
- * flush_tlb_kernel_range are best implemented as tlbia vs
- * specific tlbie's
- */
-
-struct vm_area_struct;
-struct mm_struct;
-
-#define MMU_NO_CONTEXT      	((unsigned int)-1)
-
-extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
-			    unsigned long end);
-extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
-
-extern void local_flush_tlb_mm(struct mm_struct *mm);
-extern void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
-
-extern void __local_flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr,
-				   int tsize, int ind);
-
-#ifdef CONFIG_SMP
-extern void flush_tlb_mm(struct mm_struct *mm);
-extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
-extern void __flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr,
-			     int tsize, int ind);
-#else
-#define flush_tlb_mm(mm)		local_flush_tlb_mm(mm)
-#define flush_tlb_page(vma,addr)	local_flush_tlb_page(vma,addr)
-#define __flush_tlb_page(mm,addr,p,i)	__local_flush_tlb_page(mm,addr,p,i)
-#endif
-#define flush_tlb_page_nohash(vma,addr)	flush_tlb_page(vma,addr)
-
-#elif defined(CONFIG_PPC_STD_MMU_32)
-
-/*
- * TLB flushing for "classic" hash-MMU 32-bit CPUs, 6xx, 7xx, 7xxx
- */
-extern void flush_tlb_mm(struct mm_struct *mm);
-extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
-extern void flush_tlb_page_nohash(struct vm_area_struct *vma, unsigned long addr);
-extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
-			    unsigned long end);
-extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
-static inline void local_flush_tlb_page(struct vm_area_struct *vma,
-					unsigned long vmaddr)
-{
-	flush_tlb_page(vma, vmaddr);
-}
-static inline void local_flush_tlb_mm(struct mm_struct *mm)
-{
-	flush_tlb_mm(mm);
-}
-
-#elif defined(CONFIG_PPC_STD_MMU_64)
-
-#define MMU_NO_CONTEXT		0
-
-/*
- * TLB flushing for 64-bit hash-MMU CPUs
- */
-
-#include <linux/percpu.h>
-#include <asm/page.h>
-
-#define PPC64_TLB_BATCH_NR 192
-
-struct ppc64_tlb_batch {
-	int			active;
-	unsigned long		index;
-	struct mm_struct	*mm;
-	real_pte_t		pte[PPC64_TLB_BATCH_NR];
-	unsigned long		vaddr[PPC64_TLB_BATCH_NR];
-	unsigned int		psize;
-	int			ssize;
-};
-DECLARE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);
-
-extern void __flush_tlb_pending(struct ppc64_tlb_batch *batch);
-
-extern void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
-			    pte_t *ptep, unsigned long pte, int huge);
-
-#define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
-
-static inline void arch_enter_lazy_mmu_mode(void)
-{
-	struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
-
-	batch->active = 1;
-}
-
-static inline void arch_leave_lazy_mmu_mode(void)
-{
-	struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
-
-	if (batch->index)
-		__flush_tlb_pending(batch);
-	batch->active = 0;
-}
-
-#define arch_flush_lazy_mmu_mode()      do {} while (0)
-
-
-extern void flush_hash_page(unsigned long va, real_pte_t pte, int psize,
-			    int ssize, int local);
-extern void flush_hash_range(unsigned long number, int local);
-
-
-static inline void local_flush_tlb_mm(struct mm_struct *mm)
-{
-}
-
-static inline void flush_tlb_mm(struct mm_struct *mm)
-{
-}
-
-static inline void local_flush_tlb_page(struct vm_area_struct *vma,
-					unsigned long vmaddr)
-{
-}
-
-static inline void flush_tlb_page(struct vm_area_struct *vma,
-				  unsigned long vmaddr)
-{
-}
-
-static inline void flush_tlb_page_nohash(struct vm_area_struct *vma,
-					 unsigned long vmaddr)
-{
-}
-
-static inline void flush_tlb_range(struct vm_area_struct *vma,
-				   unsigned long start, unsigned long end)
-{
-}
-
-static inline void flush_tlb_kernel_range(unsigned long start,
-					  unsigned long end)
-{
-}
-
-/* Private function for use by PCI IO mapping code */
-extern void __flush_hash_table_range(struct mm_struct *mm, unsigned long start,
-				     unsigned long end);
-
-#else
-#error Unsupported MMU type
-#endif
-
-#endif /*__KERNEL__ */
-#endif /* _ASM_POWERPC_TLBFLUSH_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/topology.h b/ANDROID_3.4.5/arch/powerpc/include/asm/topology.h
deleted file mode 100644
index c9718588..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/topology.h
+++ /dev/null
@@ -1,137 +0,0 @@
-#ifndef _ASM_POWERPC_TOPOLOGY_H
-#define _ASM_POWERPC_TOPOLOGY_H
-#ifdef __KERNEL__
-
-
-struct device;
-struct device_node;
-
-#ifdef CONFIG_NUMA
-
-/*
- * Before going off node we want the VM to try and reclaim from the local
- * node. It does this if the remote distance is larger than RECLAIM_DISTANCE.
- * With the default REMOTE_DISTANCE of 20 and the default RECLAIM_DISTANCE of
- * 20, we never reclaim and go off node straight away.
- *
- * To fix this we choose a smaller value of RECLAIM_DISTANCE.
- */
-#define RECLAIM_DISTANCE 10
-
-/*
- * Avoid creating an extra level of balancing (SD_ALLNODES) on the largest
- * POWER7 boxes which have a maximum of 32 nodes.
- */
-#define SD_NODES_PER_DOMAIN 32
-
-#include <asm/mmzone.h>
-
-static inline int cpu_to_node(int cpu)
-{
-	return numa_cpu_lookup_table[cpu];
-}
-
-#define parent_node(node)	(node)
-
-#define cpumask_of_node(node) ((node) == -1 ?				\
-			       cpu_all_mask :				\
-			       node_to_cpumask_map[node])
-
-struct pci_bus;
-#ifdef CONFIG_PCI
-extern int pcibus_to_node(struct pci_bus *bus);
-#else
-static inline int pcibus_to_node(struct pci_bus *bus)
-{
-	return -1;
-}
-#endif
-
-#define cpumask_of_pcibus(bus)	(pcibus_to_node(bus) == -1 ?		\
-				 cpu_all_mask :				\
-				 cpumask_of_node(pcibus_to_node(bus)))
-
-/* sched_domains SD_NODE_INIT for PPC64 machines */
-#define SD_NODE_INIT (struct sched_domain) {				\
-	.min_interval		= 8,					\
-	.max_interval		= 32,					\
-	.busy_factor		= 32,					\
-	.imbalance_pct		= 125,					\
-	.cache_nice_tries	= 1,					\
-	.busy_idx		= 3,					\
-	.idle_idx		= 1,					\
-	.newidle_idx		= 0,					\
-	.wake_idx		= 0,					\
-	.forkexec_idx		= 0,					\
-									\
-	.flags			= 1*SD_LOAD_BALANCE			\
-				| 0*SD_BALANCE_NEWIDLE			\
-				| 1*SD_BALANCE_EXEC			\
-				| 1*SD_BALANCE_FORK			\
-				| 0*SD_BALANCE_WAKE			\
-				| 1*SD_WAKE_AFFINE			\
-				| 0*SD_PREFER_LOCAL			\
-				| 0*SD_SHARE_CPUPOWER			\
-				| 0*SD_POWERSAVINGS_BALANCE		\
-				| 0*SD_SHARE_PKG_RESOURCES		\
-				| 1*SD_SERIALIZE			\
-				| 0*SD_PREFER_SIBLING			\
-				,					\
-	.last_balance		= jiffies,				\
-	.balance_interval	= 1,					\
-}
-
-extern int __node_distance(int, int);
-#define node_distance(a, b) __node_distance(a, b)
-
-extern void __init dump_numa_cpu_topology(void);
-
-extern int sysfs_add_device_to_node(struct device *dev, int nid);
-extern void sysfs_remove_device_from_node(struct device *dev, int nid);
-
-#else
-
-static inline void dump_numa_cpu_topology(void) {}
-
-static inline int sysfs_add_device_to_node(struct device *dev, int nid)
-{
-	return 0;
-}
-
-static inline void sysfs_remove_device_from_node(struct device *dev,
-						int nid)
-{
-}
-#endif /* CONFIG_NUMA */
-
-#if defined(CONFIG_NUMA) && defined(CONFIG_PPC_SPLPAR)
-extern int start_topology_update(void);
-extern int stop_topology_update(void);
-#else
-static inline int start_topology_update(void)
-{
-	return 0;
-}
-static inline int stop_topology_update(void)
-{
-	return 0;
-}
-#endif /* CONFIG_NUMA && CONFIG_PPC_SPLPAR */
-
-#include <asm-generic/topology.h>
-
-#ifdef CONFIG_SMP
-#include <asm/cputable.h>
-#define smt_capable()		(cpu_has_feature(CPU_FTR_SMT))
-
-#ifdef CONFIG_PPC64
-#include <asm/smp.h>
-
-#define topology_thread_cpumask(cpu)	(per_cpu(cpu_sibling_map, cpu))
-#define topology_core_cpumask(cpu)	(per_cpu(cpu_core_map, cpu))
-#define topology_core_id(cpu)		(cpu_to_core_id(cpu))
-#endif
-#endif
-
-#endif /* __KERNEL__ */
-#endif	/* _ASM_POWERPC_TOPOLOGY_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/trace.h b/ANDROID_3.4.5/arch/powerpc/include/asm/trace.h
deleted file mode 100644
index cbe2297d..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/trace.h
+++ /dev/null
@@ -1,133 +0,0 @@
-#undef TRACE_SYSTEM
-#define TRACE_SYSTEM powerpc
-
-#if !defined(_TRACE_POWERPC_H) || defined(TRACE_HEADER_MULTI_READ)
-#define _TRACE_POWERPC_H
-
-#include <linux/tracepoint.h>
-
-struct pt_regs;
-
-TRACE_EVENT(irq_entry,
-
-	TP_PROTO(struct pt_regs *regs),
-
-	TP_ARGS(regs),
-
-	TP_STRUCT__entry(
-		__field(struct pt_regs *, regs)
-	),
-
-	TP_fast_assign(
-		__entry->regs = regs;
-	),
-
-	TP_printk("pt_regs=%p", __entry->regs)
-);
-
-TRACE_EVENT(irq_exit,
-
-	TP_PROTO(struct pt_regs *regs),
-
-	TP_ARGS(regs),
-
-	TP_STRUCT__entry(
-		__field(struct pt_regs *, regs)
-	),
-
-	TP_fast_assign(
-		__entry->regs = regs;
-	),
-
-	TP_printk("pt_regs=%p", __entry->regs)
-);
-
-TRACE_EVENT(timer_interrupt_entry,
-
-	TP_PROTO(struct pt_regs *regs),
-
-	TP_ARGS(regs),
-
-	TP_STRUCT__entry(
-		__field(struct pt_regs *, regs)
-	),
-
-	TP_fast_assign(
-		__entry->regs = regs;
-	),
-
-	TP_printk("pt_regs=%p", __entry->regs)
-);
-
-TRACE_EVENT(timer_interrupt_exit,
-
-	TP_PROTO(struct pt_regs *regs),
-
-	TP_ARGS(regs),
-
-	TP_STRUCT__entry(
-		__field(struct pt_regs *, regs)
-	),
-
-	TP_fast_assign(
-		__entry->regs = regs;
-	),
-
-	TP_printk("pt_regs=%p", __entry->regs)
-);
-
-#ifdef CONFIG_PPC_PSERIES
-extern void hcall_tracepoint_regfunc(void);
-extern void hcall_tracepoint_unregfunc(void);
-
-TRACE_EVENT_FN(hcall_entry,
-
-	TP_PROTO(unsigned long opcode, unsigned long *args),
-
-	TP_ARGS(opcode, args),
-
-	TP_STRUCT__entry(
-		__field(unsigned long, opcode)
-	),
-
-	TP_fast_assign(
-		__entry->opcode = opcode;
-	),
-
-	TP_printk("opcode=%lu", __entry->opcode),
-
-	hcall_tracepoint_regfunc, hcall_tracepoint_unregfunc
-);
-
-TRACE_EVENT_FN(hcall_exit,
-
-	TP_PROTO(unsigned long opcode, unsigned long retval,
-		unsigned long *retbuf),
-
-	TP_ARGS(opcode, retval, retbuf),
-
-	TP_STRUCT__entry(
-		__field(unsigned long, opcode)
-		__field(unsigned long, retval)
-	),
-
-	TP_fast_assign(
-		__entry->opcode = opcode;
-		__entry->retval = retval;
-	),
-
-	TP_printk("opcode=%lu retval=%lu", __entry->opcode, __entry->retval),
-
-	hcall_tracepoint_regfunc, hcall_tracepoint_unregfunc
-);
-#endif
-
-#endif /* _TRACE_POWERPC_H */
-
-#undef TRACE_INCLUDE_PATH
-#undef TRACE_INCLUDE_FILE
-
-#define TRACE_INCLUDE_PATH asm
-#define TRACE_INCLUDE_FILE trace
-
-#include <trace/define_trace.h>
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/tsi108.h b/ANDROID_3.4.5/arch/powerpc/include/asm/tsi108.h
deleted file mode 100644
index f8b60793..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/tsi108.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * common routine and memory layout for Tundra TSI108(Grendel) host bridge
- * memory controller.
- *
- * Author: Jacob Pan (jacob.pan@freescale.com)
- *	   Alex Bounine (alexandreb@tundra.com)
- *
- * Copyright 2004-2006 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef __PPC_KERNEL_TSI108_H
-#define __PPC_KERNEL_TSI108_H
-
-#include <asm/pci-bridge.h>
-
-/* Size of entire register space */
-#define TSI108_REG_SIZE		(0x10000)
-
-/* Sizes of register spaces for individual blocks */
-#define TSI108_HLP_SIZE		0x1000
-#define TSI108_PCI_SIZE		0x1000
-#define TSI108_CLK_SIZE		0x1000
-#define TSI108_PB_SIZE		0x1000
-#define TSI108_SD_SIZE		0x1000
-#define TSI108_DMA_SIZE		0x1000
-#define TSI108_ETH_SIZE		0x1000
-#define TSI108_I2C_SIZE		0x400
-#define TSI108_MPIC_SIZE	0x400
-#define TSI108_UART0_SIZE	0x200
-#define TSI108_GPIO_SIZE	0x200
-#define TSI108_UART1_SIZE	0x200
-
-/* Offsets within Tsi108(A) CSR space for individual blocks */
-#define TSI108_HLP_OFFSET	0x0000
-#define TSI108_PCI_OFFSET	0x1000
-#define TSI108_CLK_OFFSET	0x2000
-#define TSI108_PB_OFFSET	0x3000
-#define TSI108_SD_OFFSET	0x4000
-#define TSI108_DMA_OFFSET	0x5000
-#define TSI108_ETH_OFFSET	0x6000
-#define TSI108_I2C_OFFSET	0x7000
-#define TSI108_MPIC_OFFSET	0x7400
-#define TSI108_UART0_OFFSET	0x7800
-#define TSI108_GPIO_OFFSET	0x7A00
-#define TSI108_UART1_OFFSET	0x7C00
-
-/* Tsi108 registers used by common code components */
-#define TSI108_PCI_CSR		(0x004)
-#define TSI108_PCI_IRP_CFG_CTL	(0x180)
-#define TSI108_PCI_IRP_STAT	(0x184)
-#define TSI108_PCI_IRP_ENABLE	(0x188)
-#define TSI108_PCI_IRP_INTAD	(0x18C)
-
-#define TSI108_PCI_IRP_STAT_P_INT	(0x00400000)
-#define TSI108_PCI_IRP_ENABLE_P_INT	(0x00400000)
-
-#define TSI108_CG_PWRUP_STATUS	(0x234)
-
-#define TSI108_PB_ISR		(0x00C)
-#define TSI108_PB_ERRCS		(0x404)
-#define TSI108_PB_AERR		(0x408)
-
-#define TSI108_PB_ERRCS_ES		(1 << 1)
-#define TSI108_PB_ISR_PBS_RD_ERR	(1 << 8)
-
-#define TSI108_PCI_CFG_SIZE		(0x01000000)
-
-/*
- * PHY Configuration Options
- *
- * Specify "bcm54xx" in the compatible property of your device tree phy
- * nodes if your board uses the Broadcom PHYs
- */
-#define TSI108_PHY_MV88E	0	/* Marvel 88Exxxx PHY */
-#define TSI108_PHY_BCM54XX	1	/* Broardcom BCM54xx PHY */
-
-/* Global variables */
-
-extern u32 tsi108_pci_cfg_base;
-/* Exported functions */
-
-extern int tsi108_bridge_init(struct pci_controller *hose, uint phys_csr_base);
-extern unsigned long tsi108_get_mem_size(void);
-extern unsigned long tsi108_get_cpu_clk(void);
-extern unsigned long tsi108_get_sdc_clk(void);
-extern int tsi108_direct_write_config(struct pci_bus *bus, unsigned int devfn,
-				      int offset, int len, u32 val);
-extern int tsi108_direct_read_config(struct pci_bus *bus, unsigned int devfn,
-				     int offset, int len, u32 * val);
-extern void tsi108_clear_pci_error(u32 pci_cfg_base);
-
-extern phys_addr_t get_csrbase(void);
-
-typedef struct {
-	u32 regs;		/* hw registers base address */
-	u32 phyregs;		/* phy registers base address */
-	u16 phy;		/* phy address */
-	u16 irq_num;		/* irq number */
-	u8 mac_addr[6];		/* phy mac address */
-	u16 phy_type;	/* type of phy on board */
-} hw_info;
-
-extern u32 get_vir_csrbase(void);
-extern u32 tsi108_csr_vir_base;
-
-static inline u32 tsi108_read_reg(u32 reg_offset)
-{
-	return in_be32((volatile u32 *)(tsi108_csr_vir_base + reg_offset));
-}
-
-static inline void tsi108_write_reg(u32 reg_offset, u32 val)
-{
-	out_be32((volatile u32 *)(tsi108_csr_vir_base + reg_offset), val);
-}
-
-#endif				/* __PPC_KERNEL_TSI108_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/tsi108_irq.h b/ANDROID_3.4.5/arch/powerpc/include/asm/tsi108_irq.h
deleted file mode 100644
index 6ed93979..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/tsi108_irq.h
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * (C) Copyright 2005 Tundra Semiconductor Corp.
- * Alex Bounine, <alexandreb at tundra.com).
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * definitions for interrupt controller initialization and external interrupt
- * demultiplexing on TSI108EMU/SVB boards.
- */
-
-#ifndef _ASM_POWERPC_TSI108_IRQ_H
-#define _ASM_POWERPC_TSI108_IRQ_H
-
-/*
- * Tsi108 interrupts
- */
-#ifndef TSI108_IRQ_REG_BASE
-#define TSI108_IRQ_REG_BASE		0
-#endif
-
-#define TSI108_IRQ(x)		(TSI108_IRQ_REG_BASE + (x))
-
-#define TSI108_MAX_VECTORS	(36 + 4)	/* 36 sources + PCI INT demux */
-#define MAX_TASK_PRIO	0xF
-
-#define TSI108_IRQ_SPURIOUS	(TSI108_MAX_VECTORS)
-
-#define DEFAULT_PRIO_LVL	10	/* initial priority level */
-
-/* Interrupt vectors assignment to external and internal
- * sources of requests. */
-
-/* EXTERNAL INTERRUPT SOURCES */
-
-#define IRQ_TSI108_EXT_INT0	TSI108_IRQ(0)	/* External Source at INT[0] */
-#define IRQ_TSI108_EXT_INT1	TSI108_IRQ(1)	/* External Source at INT[1] */
-#define IRQ_TSI108_EXT_INT2	TSI108_IRQ(2)	/* External Source at INT[2] */
-#define IRQ_TSI108_EXT_INT3	TSI108_IRQ(3)	/* External Source at INT[3] */
-
-/* INTERNAL INTERRUPT SOURCES */
-
-#define IRQ_TSI108_RESERVED0	TSI108_IRQ(4)	/* Reserved IRQ */
-#define IRQ_TSI108_RESERVED1	TSI108_IRQ(5)	/* Reserved IRQ */
-#define IRQ_TSI108_RESERVED2	TSI108_IRQ(6)	/* Reserved IRQ */
-#define IRQ_TSI108_RESERVED3	TSI108_IRQ(7)	/* Reserved IRQ */
-#define IRQ_TSI108_DMA0		TSI108_IRQ(8)	/* DMA0 */
-#define IRQ_TSI108_DMA1		TSI108_IRQ(9)	/* DMA1 */
-#define IRQ_TSI108_DMA2		TSI108_IRQ(10)	/* DMA2 */
-#define IRQ_TSI108_DMA3		TSI108_IRQ(11)	/* DMA3 */
-#define IRQ_TSI108_UART0	TSI108_IRQ(12)	/* UART0 */
-#define IRQ_TSI108_UART1	TSI108_IRQ(13)	/* UART1 */
-#define IRQ_TSI108_I2C		TSI108_IRQ(14)	/* I2C */
-#define IRQ_TSI108_GPIO		TSI108_IRQ(15)	/* GPIO */
-#define IRQ_TSI108_GIGE0	TSI108_IRQ(16)	/* GIGE0 */
-#define IRQ_TSI108_GIGE1	TSI108_IRQ(17)	/* GIGE1 */
-#define IRQ_TSI108_RESERVED4	TSI108_IRQ(18)	/* Reserved IRQ */
-#define IRQ_TSI108_HLP		TSI108_IRQ(19)	/* HLP */
-#define IRQ_TSI108_SDRAM	TSI108_IRQ(20)	/* SDC */
-#define IRQ_TSI108_PROC_IF	TSI108_IRQ(21)	/* Processor IF */
-#define IRQ_TSI108_RESERVED5	TSI108_IRQ(22)	/* Reserved IRQ */
-#define IRQ_TSI108_PCI		TSI108_IRQ(23)	/* PCI/X block */
-
-#define IRQ_TSI108_MBOX0	TSI108_IRQ(24)	/* Mailbox 0 register */
-#define IRQ_TSI108_MBOX1	TSI108_IRQ(25)	/* Mailbox 1 register */
-#define IRQ_TSI108_MBOX2	TSI108_IRQ(26)	/* Mailbox 2 register */
-#define IRQ_TSI108_MBOX3	TSI108_IRQ(27)	/* Mailbox 3 register */
-
-#define IRQ_TSI108_DBELL0	TSI108_IRQ(28)	/* Doorbell 0 */
-#define IRQ_TSI108_DBELL1	TSI108_IRQ(29)	/* Doorbell 1 */
-#define IRQ_TSI108_DBELL2	TSI108_IRQ(30)	/* Doorbell 2 */
-#define IRQ_TSI108_DBELL3	TSI108_IRQ(31)	/* Doorbell 3 */
-
-#define IRQ_TSI108_TIMER0	TSI108_IRQ(32)	/* Global Timer 0 */
-#define IRQ_TSI108_TIMER1	TSI108_IRQ(33)	/* Global Timer 1 */
-#define IRQ_TSI108_TIMER2	TSI108_IRQ(34)	/* Global Timer 2 */
-#define IRQ_TSI108_TIMER3	TSI108_IRQ(35)	/* Global Timer 3 */
-
-/*
- * PCI bus INTA# - INTD# lines demultiplexor
- */
-#define IRQ_PCI_INTAD_BASE	TSI108_IRQ(36)
-#define IRQ_PCI_INTA		(IRQ_PCI_INTAD_BASE + 0)
-#define IRQ_PCI_INTB		(IRQ_PCI_INTAD_BASE + 1)
-#define IRQ_PCI_INTC		(IRQ_PCI_INTAD_BASE + 2)
-#define IRQ_PCI_INTD		(IRQ_PCI_INTAD_BASE + 3)
-#define NUM_PCI_IRQS		(4)
-
-/* number of entries in vector dispatch table */
-#define IRQ_TSI108_TAB_SIZE	(TSI108_MAX_VECTORS + 1)
-
-/* Mapping of MPIC outputs to processors' interrupt pins */
-
-#define IDIR_INT_OUT0		0x1
-#define IDIR_INT_OUT1		0x2
-#define IDIR_INT_OUT2		0x4
-#define IDIR_INT_OUT3		0x8
-
-/*---------------------------------------------------------------
- * IRQ line configuration parameters */
-
-/* Interrupt delivery modes */
-typedef enum {
-	TSI108_IRQ_DIRECTED,
-	TSI108_IRQ_DISTRIBUTED,
-} TSI108_IRQ_MODE;
-#endif				/*  _ASM_POWERPC_TSI108_IRQ_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/tsi108_pci.h b/ANDROID_3.4.5/arch/powerpc/include/asm/tsi108_pci.h
deleted file mode 100644
index 5653d7cc..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/tsi108_pci.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Copyright 2007 IBM Corp
- *
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _ASM_POWERPC_TSI108_PCI_H
-#define _ASM_POWERPC_TSI108_PCI_H
-
-#include <asm/tsi108.h>
-
-/* Register definitions */
-#define TSI108_PCI_P2O_BAR0 (TSI108_PCI_OFFSET + 0x10)
-#define TSI108_PCI_P2O_BAR0_UPPER (TSI108_PCI_OFFSET + 0x14)
-#define TSI108_PCI_P2O_BAR2 (TSI108_PCI_OFFSET + 0x18)
-#define TSI108_PCI_P2O_BAR2_UPPER (TSI108_PCI_OFFSET + 0x1c)
-#define TSI108_PCI_P2O_PAGE_SIZES (TSI108_PCI_OFFSET + 0x4c)
-#define TSI108_PCI_PFAB_BAR0 (TSI108_PCI_OFFSET + 0x204)
-#define TSI108_PCI_PFAB_BAR0_UPPER (TSI108_PCI_OFFSET + 0x208)
-#define TSI108_PCI_PFAB_IO (TSI108_PCI_OFFSET + 0x20c)
-#define TSI108_PCI_PFAB_IO_UPPER (TSI108_PCI_OFFSET + 0x210)
-#define TSI108_PCI_PFAB_MEM32 (TSI108_PCI_OFFSET + 0x214)
-#define TSI108_PCI_PFAB_PFM3 (TSI108_PCI_OFFSET + 0x220)
-#define TSI108_PCI_PFAB_PFM4 (TSI108_PCI_OFFSET + 0x230)
-
-extern int tsi108_setup_pci(struct device_node *dev, u32 cfg_phys, int primary);
-extern void tsi108_pci_int_init(struct device_node *node);
-extern void tsi108_irq_cascade(unsigned int irq, struct irq_desc *desc);
-extern void tsi108_clear_pci_cfg_error(void);
-
-#endif				/*  _ASM_POWERPC_TSI108_PCI_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/types.h b/ANDROID_3.4.5/arch/powerpc/include/asm/types.h
deleted file mode 100644
index 0abf7f2c..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/types.h
+++ /dev/null
@@ -1,54 +0,0 @@
-#ifndef _ASM_POWERPC_TYPES_H
-#define _ASM_POWERPC_TYPES_H
-
-/*
- * This is here because we used to use l64 for 64bit powerpc
- * and we don't want to impact user mode with our change to ll64
- * in the kernel.
- *
- * However, some user programs are fine with this.  They can
- * flag __SANE_USERSPACE_TYPES__ to get int-ll64.h here.
- */
-#if !defined(__SANE_USERSPACE_TYPES__) && defined(__powerpc64__) && !defined(__KERNEL__)
-# include <asm-generic/int-l64.h>
-#else
-# include <asm-generic/int-ll64.h>
-#endif
-
-#ifndef __ASSEMBLY__
-
-/*
- * This file is never included by application software unless
- * explicitly requested (e.g., via linux/types.h) in which case the
- * application is Linux specific so (user-) name space pollution is
- * not a major issue.  However, for interoperability, libraries still
- * need to be careful to avoid a name clashes.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-typedef struct {
-	__u32 u[4];
-} __attribute__((aligned(16))) __vector128;
-
-#endif /* __ASSEMBLY__ */
-
-#ifdef __KERNEL__
-#ifndef __ASSEMBLY__
-
-typedef __vector128 vector128;
-
-typedef struct {
-	unsigned long entry;
-	unsigned long toc;
-	unsigned long env;
-} func_descr_t;
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_POWERPC_TYPES_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/uaccess.h b/ANDROID_3.4.5/arch/powerpc/include/asm/uaccess.h
deleted file mode 100644
index bd0fb849..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/uaccess.h
+++ /dev/null
@@ -1,496 +0,0 @@
-#ifndef _ARCH_POWERPC_UACCESS_H
-#define _ARCH_POWERPC_UACCESS_H
-
-#ifdef __KERNEL__
-#ifndef __ASSEMBLY__
-
-#include <linux/sched.h>
-#include <linux/errno.h>
-#include <asm/asm-compat.h>
-#include <asm/processor.h>
-#include <asm/page.h>
-
-#define VERIFY_READ	0
-#define VERIFY_WRITE	1
-
-/*
- * The fs value determines whether argument validity checking should be
- * performed or not.  If get_fs() == USER_DS, checking is performed, with
- * get_fs() == KERNEL_DS, checking is bypassed.
- *
- * For historical reasons, these macros are grossly misnamed.
- *
- * The fs/ds values are now the highest legal address in the "segment".
- * This simplifies the checking in the routines below.
- */
-
-#define MAKE_MM_SEG(s)  ((mm_segment_t) { (s) })
-
-#define KERNEL_DS	MAKE_MM_SEG(~0UL)
-#ifdef __powerpc64__
-/* We use TASK_SIZE_USER64 as TASK_SIZE is not constant */
-#define USER_DS		MAKE_MM_SEG(TASK_SIZE_USER64 - 1)
-#else
-#define USER_DS		MAKE_MM_SEG(TASK_SIZE - 1)
-#endif
-
-#define get_ds()	(KERNEL_DS)
-#define get_fs()	(current->thread.fs)
-#define set_fs(val)	(current->thread.fs = (val))
-
-#define segment_eq(a, b)	((a).seg == (b).seg)
-
-#ifdef __powerpc64__
-/*
- * This check is sufficient because there is a large enough
- * gap between user addresses and the kernel addresses
- */
-#define __access_ok(addr, size, segment)	\
-	(((addr) <= (segment).seg) && ((size) <= (segment).seg))
-
-#else
-
-#define __access_ok(addr, size, segment)	\
-	(((addr) <= (segment).seg) &&		\
-	 (((size) == 0) || (((size) - 1) <= ((segment).seg - (addr)))))
-
-#endif
-
-#define access_ok(type, addr, size)		\
-	(__chk_user_ptr(addr),			\
-	 __access_ok((__force unsigned long)(addr), (size), get_fs()))
-
-/*
- * The exception table consists of pairs of addresses: the first is the
- * address of an instruction that is allowed to fault, and the second is
- * the address at which the program should continue.  No registers are
- * modified, so it is entirely up to the continuation code to figure out
- * what to do.
- *
- * All the routines below use bits of fixup code that are out of line
- * with the main instruction path.  This means when everything is well,
- * we don't even have to jump over them.  Further, they do not intrude
- * on our cache or tlb entries.
- */
-
-struct exception_table_entry {
-	unsigned long insn;
-	unsigned long fixup;
-};
-
-/*
- * These are the main single-value transfer routines.  They automatically
- * use the right size if we just have the right pointer type.
- *
- * This gets kind of ugly. We want to return _two_ values in "get_user()"
- * and yet we don't want to do any pointers, because that is too much
- * of a performance impact. Thus we have a few rather ugly macros here,
- * and hide all the ugliness from the user.
- *
- * The "__xxx" versions of the user access functions are versions that
- * do not verify the address space, that must have been done previously
- * with a separate "access_ok()" call (this is used when we do multiple
- * accesses to the same area of user memory).
- *
- * As we use the same address space for kernel and user data on the
- * PowerPC, we can just do these as direct assignments.  (Of course, the
- * exception handling means that it's no longer "just"...)
- *
- * The "user64" versions of the user access functions are versions that
- * allow access of 64-bit data. The "get_user" functions do not
- * properly handle 64-bit data because the value gets down cast to a long.
- * The "put_user" functions already handle 64-bit data properly but we add
- * "user64" versions for completeness
- */
-#define get_user(x, ptr) \
-	__get_user_check((x), (ptr), sizeof(*(ptr)))
-#define put_user(x, ptr) \
-	__put_user_check((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr)))
-
-#define __get_user(x, ptr) \
-	__get_user_nocheck((x), (ptr), sizeof(*(ptr)))
-#define __put_user(x, ptr) \
-	__put_user_nocheck((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr)))
-
-#ifndef __powerpc64__
-#define __get_user64(x, ptr) \
-	__get_user64_nocheck((x), (ptr), sizeof(*(ptr)))
-#define __put_user64(x, ptr) __put_user(x, ptr)
-#endif
-
-#define __get_user_inatomic(x, ptr) \
-	__get_user_nosleep((x), (ptr), sizeof(*(ptr)))
-#define __put_user_inatomic(x, ptr) \
-	__put_user_nosleep((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr)))
-
-#define __get_user_unaligned __get_user
-#define __put_user_unaligned __put_user
-
-extern long __put_user_bad(void);
-
-/*
- * We don't tell gcc that we are accessing memory, but this is OK
- * because we do not write to any memory gcc knows about, so there
- * are no aliasing issues.
- */
-#define __put_user_asm(x, addr, err, op)			\
-	__asm__ __volatile__(					\
-		"1:	" op " %1,0(%2)	# put_user\n"		\
-		"2:\n"						\
-		".section .fixup,\"ax\"\n"			\
-		"3:	li %0,%3\n"				\
-		"	b 2b\n"					\
-		".previous\n"					\
-		".section __ex_table,\"a\"\n"			\
-			PPC_LONG_ALIGN "\n"			\
-			PPC_LONG "1b,3b\n"			\
-		".previous"					\
-		: "=r" (err)					\
-		: "r" (x), "b" (addr), "i" (-EFAULT), "0" (err))
-
-#ifdef __powerpc64__
-#define __put_user_asm2(x, ptr, retval)				\
-	  __put_user_asm(x, ptr, retval, "std")
-#else /* __powerpc64__ */
-#define __put_user_asm2(x, addr, err)				\
-	__asm__ __volatile__(					\
-		"1:	stw %1,0(%2)\n"				\
-		"2:	stw %1+1,4(%2)\n"			\
-		"3:\n"						\
-		".section .fixup,\"ax\"\n"			\
-		"4:	li %0,%3\n"				\
-		"	b 3b\n"					\
-		".previous\n"					\
-		".section __ex_table,\"a\"\n"			\
-			PPC_LONG_ALIGN "\n"			\
-			PPC_LONG "1b,4b\n"			\
-			PPC_LONG "2b,4b\n"			\
-		".previous"					\
-		: "=r" (err)					\
-		: "r" (x), "b" (addr), "i" (-EFAULT), "0" (err))
-#endif /* __powerpc64__ */
-
-#define __put_user_size(x, ptr, size, retval)			\
-do {								\
-	retval = 0;						\
-	switch (size) {						\
-	  case 1: __put_user_asm(x, ptr, retval, "stb"); break;	\
-	  case 2: __put_user_asm(x, ptr, retval, "sth"); break;	\
-	  case 4: __put_user_asm(x, ptr, retval, "stw"); break;	\
-	  case 8: __put_user_asm2(x, ptr, retval); break;	\
-	  default: __put_user_bad();				\
-	}							\
-} while (0)
-
-#define __put_user_nocheck(x, ptr, size)			\
-({								\
-	long __pu_err;						\
-	__typeof__(*(ptr)) __user *__pu_addr = (ptr);		\
-	if (!is_kernel_addr((unsigned long)__pu_addr))		\
-		might_sleep();					\
-	__chk_user_ptr(ptr);					\
-	__put_user_size((x), __pu_addr, (size), __pu_err);	\
-	__pu_err;						\
-})
-
-#define __put_user_check(x, ptr, size)					\
-({									\
-	long __pu_err = -EFAULT;					\
-	__typeof__(*(ptr)) __user *__pu_addr = (ptr);			\
-	might_sleep();							\
-	if (access_ok(VERIFY_WRITE, __pu_addr, size))			\
-		__put_user_size((x), __pu_addr, (size), __pu_err);	\
-	__pu_err;							\
-})
-
-#define __put_user_nosleep(x, ptr, size)			\
-({								\
-	long __pu_err;						\
-	__typeof__(*(ptr)) __user *__pu_addr = (ptr);		\
-	__chk_user_ptr(ptr);					\
-	__put_user_size((x), __pu_addr, (size), __pu_err);	\
-	__pu_err;						\
-})
-
-
-extern long __get_user_bad(void);
-
-#define __get_user_asm(x, addr, err, op)		\
-	__asm__ __volatile__(				\
-		"1:	"op" %1,0(%2)	# get_user\n"	\
-		"2:\n"					\
-		".section .fixup,\"ax\"\n"		\
-		"3:	li %0,%3\n"			\
-		"	li %1,0\n"			\
-		"	b 2b\n"				\
-		".previous\n"				\
-		".section __ex_table,\"a\"\n"		\
-			PPC_LONG_ALIGN "\n"		\
-			PPC_LONG "1b,3b\n"		\
-		".previous"				\
-		: "=r" (err), "=r" (x)			\
-		: "b" (addr), "i" (-EFAULT), "0" (err))
-
-#ifdef __powerpc64__
-#define __get_user_asm2(x, addr, err)			\
-	__get_user_asm(x, addr, err, "ld")
-#else /* __powerpc64__ */
-#define __get_user_asm2(x, addr, err)			\
-	__asm__ __volatile__(				\
-		"1:	lwz %1,0(%2)\n"			\
-		"2:	lwz %1+1,4(%2)\n"		\
-		"3:\n"					\
-		".section .fixup,\"ax\"\n"		\
-		"4:	li %0,%3\n"			\
-		"	li %1,0\n"			\
-		"	li %1+1,0\n"			\
-		"	b 3b\n"				\
-		".previous\n"				\
-		".section __ex_table,\"a\"\n"		\
-			PPC_LONG_ALIGN "\n"		\
-			PPC_LONG "1b,4b\n"		\
-			PPC_LONG "2b,4b\n"		\
-		".previous"				\
-		: "=r" (err), "=&r" (x)			\
-		: "b" (addr), "i" (-EFAULT), "0" (err))
-#endif /* __powerpc64__ */
-
-#define __get_user_size(x, ptr, size, retval)			\
-do {								\
-	retval = 0;						\
-	__chk_user_ptr(ptr);					\
-	if (size > sizeof(x))					\
-		(x) = __get_user_bad();				\
-	switch (size) {						\
-	case 1: __get_user_asm(x, ptr, retval, "lbz"); break;	\
-	case 2: __get_user_asm(x, ptr, retval, "lhz"); break;	\
-	case 4: __get_user_asm(x, ptr, retval, "lwz"); break;	\
-	case 8: __get_user_asm2(x, ptr, retval);  break;	\
-	default: (x) = __get_user_bad();			\
-	}							\
-} while (0)
-
-#define __get_user_nocheck(x, ptr, size)			\
-({								\
-	long __gu_err;						\
-	unsigned long __gu_val;					\
-	const __typeof__(*(ptr)) __user *__gu_addr = (ptr);	\
-	__chk_user_ptr(ptr);					\
-	if (!is_kernel_addr((unsigned long)__gu_addr))		\
-		might_sleep();					\
-	__get_user_size(__gu_val, __gu_addr, (size), __gu_err);	\
-	(x) = (__typeof__(*(ptr)))__gu_val;			\
-	__gu_err;						\
-})
-
-#ifndef __powerpc64__
-#define __get_user64_nocheck(x, ptr, size)			\
-({								\
-	long __gu_err;						\
-	long long __gu_val;					\
-	const __typeof__(*(ptr)) __user *__gu_addr = (ptr);	\
-	__chk_user_ptr(ptr);					\
-	if (!is_kernel_addr((unsigned long)__gu_addr))		\
-		might_sleep();					\
-	__get_user_size(__gu_val, __gu_addr, (size), __gu_err);	\
-	(x) = (__typeof__(*(ptr)))__gu_val;			\
-	__gu_err;						\
-})
-#endif /* __powerpc64__ */
-
-#define __get_user_check(x, ptr, size)					\
-({									\
-	long __gu_err = -EFAULT;					\
-	unsigned long  __gu_val = 0;					\
-	const __typeof__(*(ptr)) __user *__gu_addr = (ptr);		\
-	might_sleep();							\
-	if (access_ok(VERIFY_READ, __gu_addr, (size)))			\
-		__get_user_size(__gu_val, __gu_addr, (size), __gu_err);	\
-	(x) = (__typeof__(*(ptr)))__gu_val;				\
-	__gu_err;							\
-})
-
-#define __get_user_nosleep(x, ptr, size)			\
-({								\
-	long __gu_err;						\
-	unsigned long __gu_val;					\
-	const __typeof__(*(ptr)) __user *__gu_addr = (ptr);	\
-	__chk_user_ptr(ptr);					\
-	__get_user_size(__gu_val, __gu_addr, (size), __gu_err);	\
-	(x) = (__typeof__(*(ptr)))__gu_val;			\
-	__gu_err;						\
-})
-
-
-/* more complex routines */
-
-extern unsigned long __copy_tofrom_user(void __user *to,
-		const void __user *from, unsigned long size);
-
-#ifndef __powerpc64__
-
-static inline unsigned long copy_from_user(void *to,
-		const void __user *from, unsigned long n)
-{
-	unsigned long over;
-
-	if (access_ok(VERIFY_READ, from, n))
-		return __copy_tofrom_user((__force void __user *)to, from, n);
-	if ((unsigned long)from < TASK_SIZE) {
-		over = (unsigned long)from + n - TASK_SIZE;
-		return __copy_tofrom_user((__force void __user *)to, from,
-				n - over) + over;
-	}
-	return n;
-}
-
-static inline unsigned long copy_to_user(void __user *to,
-		const void *from, unsigned long n)
-{
-	unsigned long over;
-
-	if (access_ok(VERIFY_WRITE, to, n))
-		return __copy_tofrom_user(to, (__force void __user *)from, n);
-	if ((unsigned long)to < TASK_SIZE) {
-		over = (unsigned long)to + n - TASK_SIZE;
-		return __copy_tofrom_user(to, (__force void __user *)from,
-				n - over) + over;
-	}
-	return n;
-}
-
-#else /* __powerpc64__ */
-
-#define __copy_in_user(to, from, size) \
-	__copy_tofrom_user((to), (from), (size))
-
-extern unsigned long copy_from_user(void *to, const void __user *from,
-				    unsigned long n);
-extern unsigned long copy_to_user(void __user *to, const void *from,
-				  unsigned long n);
-extern unsigned long copy_in_user(void __user *to, const void __user *from,
-				  unsigned long n);
-
-#endif /* __powerpc64__ */
-
-static inline unsigned long __copy_from_user_inatomic(void *to,
-		const void __user *from, unsigned long n)
-{
-	if (__builtin_constant_p(n) && (n <= 8)) {
-		unsigned long ret = 1;
-
-		switch (n) {
-		case 1:
-			__get_user_size(*(u8 *)to, from, 1, ret);
-			break;
-		case 2:
-			__get_user_size(*(u16 *)to, from, 2, ret);
-			break;
-		case 4:
-			__get_user_size(*(u32 *)to, from, 4, ret);
-			break;
-		case 8:
-			__get_user_size(*(u64 *)to, from, 8, ret);
-			break;
-		}
-		if (ret == 0)
-			return 0;
-	}
-	return __copy_tofrom_user((__force void __user *)to, from, n);
-}
-
-static inline unsigned long __copy_to_user_inatomic(void __user *to,
-		const void *from, unsigned long n)
-{
-	if (__builtin_constant_p(n) && (n <= 8)) {
-		unsigned long ret = 1;
-
-		switch (n) {
-		case 1:
-			__put_user_size(*(u8 *)from, (u8 __user *)to, 1, ret);
-			break;
-		case 2:
-			__put_user_size(*(u16 *)from, (u16 __user *)to, 2, ret);
-			break;
-		case 4:
-			__put_user_size(*(u32 *)from, (u32 __user *)to, 4, ret);
-			break;
-		case 8:
-			__put_user_size(*(u64 *)from, (u64 __user *)to, 8, ret);
-			break;
-		}
-		if (ret == 0)
-			return 0;
-	}
-	return __copy_tofrom_user(to, (__force const void __user *)from, n);
-}
-
-static inline unsigned long __copy_from_user(void *to,
-		const void __user *from, unsigned long size)
-{
-	might_sleep();
-	return __copy_from_user_inatomic(to, from, size);
-}
-
-static inline unsigned long __copy_to_user(void __user *to,
-		const void *from, unsigned long size)
-{
-	might_sleep();
-	return __copy_to_user_inatomic(to, from, size);
-}
-
-extern unsigned long __clear_user(void __user *addr, unsigned long size);
-
-static inline unsigned long clear_user(void __user *addr, unsigned long size)
-{
-	might_sleep();
-	if (likely(access_ok(VERIFY_WRITE, addr, size)))
-		return __clear_user(addr, size);
-	if ((unsigned long)addr < TASK_SIZE) {
-		unsigned long over = (unsigned long)addr + size - TASK_SIZE;
-		return __clear_user(addr, size - over) + over;
-	}
-	return size;
-}
-
-extern int __strncpy_from_user(char *dst, const char __user *src, long count);
-
-static inline long strncpy_from_user(char *dst, const char __user *src,
-		long count)
-{
-	might_sleep();
-	if (likely(access_ok(VERIFY_READ, src, 1)))
-		return __strncpy_from_user(dst, src, count);
-	return -EFAULT;
-}
-
-/*
- * Return the size of a string (including the ending 0)
- *
- * Return 0 for error
- */
-extern int __strnlen_user(const char __user *str, long len, unsigned long top);
-
-/*
- * Returns the length of the string at str (including the null byte),
- * or 0 if we hit a page we can't access,
- * or something > len if we didn't find a null byte.
- *
- * The `top' parameter to __strnlen_user is to make sure that
- * we can never overflow from the user area into kernel space.
- */
-static inline int strnlen_user(const char __user *str, long len)
-{
-	unsigned long top = current->thread.fs.seg;
-
-	if ((unsigned long)str > top)
-		return 0;
-	return __strnlen_user(str, len, top);
-}
-
-#define strlen_user(str)	strnlen_user((str), 0x7ffffffe)
-
-#endif  /* __ASSEMBLY__ */
-#endif /* __KERNEL__ */
-
-#endif	/* _ARCH_POWERPC_UACCESS_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/ucc.h b/ANDROID_3.4.5/arch/powerpc/include/asm/ucc.h
deleted file mode 100644
index 46b09ba6..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/ucc.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
- *
- * Authors: 	Shlomi Gridish <gridish@freescale.com>
- * 		Li Yang <leoli@freescale.com>
- *
- * Description:
- * Internal header file for UCC unit routines.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-#ifndef __UCC_H__
-#define __UCC_H__
-
-#include <asm/immap_qe.h>
-#include <asm/qe.h>
-
-#define STATISTICS
-
-#define UCC_MAX_NUM	8
-
-/* Slow or fast type for UCCs.
-*/
-enum ucc_speed_type {
-	UCC_SPEED_TYPE_FAST = UCC_GUEMR_MODE_FAST_RX | UCC_GUEMR_MODE_FAST_TX,
-	UCC_SPEED_TYPE_SLOW = UCC_GUEMR_MODE_SLOW_RX | UCC_GUEMR_MODE_SLOW_TX
-};
-
-/* ucc_set_type
- * Sets UCC to slow or fast mode.
- *
- * ucc_num - (In) number of UCC (0-7).
- * speed   - (In) slow or fast mode for UCC.
- */
-int ucc_set_type(unsigned int ucc_num, enum ucc_speed_type speed);
-
-int ucc_set_qe_mux_mii_mng(unsigned int ucc_num);
-
-int ucc_set_qe_mux_rxtx(unsigned int ucc_num, enum qe_clock clock,
-	enum comm_dir mode);
-
-int ucc_mux_set_grant_tsa_bkpt(unsigned int ucc_num, int set, u32 mask);
-
-/* QE MUX clock routing for UCC
-*/
-static inline int ucc_set_qe_mux_grant(unsigned int ucc_num, int set)
-{
-	return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_GRANT);
-}
-
-static inline int ucc_set_qe_mux_tsa(unsigned int ucc_num, int set)
-{
-	return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_TSA);
-}
-
-static inline int ucc_set_qe_mux_bkpt(unsigned int ucc_num, int set)
-{
-	return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_BKPT);
-}
-
-#endif				/* __UCC_H__ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/ucc_fast.h b/ANDROID_3.4.5/arch/powerpc/include/asm/ucc_fast.h
deleted file mode 100644
index 839aab8b..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/ucc_fast.h
+++ /dev/null
@@ -1,244 +0,0 @@
-/*
- * Internal header file for UCC FAST unit routines.
- *
- * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
- *
- * Authors: 	Shlomi Gridish <gridish@freescale.com>
- * 		Li Yang <leoli@freescale.com>
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-#ifndef __UCC_FAST_H__
-#define __UCC_FAST_H__
-
-#include <linux/kernel.h>
-
-#include <asm/immap_qe.h>
-#include <asm/qe.h>
-
-#include "ucc.h"
-
-/* Receive BD's status */
-#define R_E	0x80000000	/* buffer empty */
-#define R_W	0x20000000	/* wrap bit */
-#define R_I	0x10000000	/* interrupt on reception */
-#define R_L	0x08000000	/* last */
-#define R_F	0x04000000	/* first */
-
-/* transmit BD's status */
-#define T_R	0x80000000	/* ready bit */
-#define T_W	0x20000000	/* wrap bit */
-#define T_I	0x10000000	/* interrupt on completion */
-#define T_L	0x08000000	/* last */
-
-/* Rx Data buffer must be 4 bytes aligned in most cases */
-#define UCC_FAST_RX_ALIGN			4
-#define UCC_FAST_MRBLR_ALIGNMENT		4
-#define UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT	8
-
-/* Sizes */
-#define UCC_FAST_URFS_MIN_VAL				0x88
-#define UCC_FAST_RECEIVE_VIRTUAL_FIFO_SIZE_FUDGE_FACTOR	8
-
-/* ucc_fast_channel_protocol_mode - UCC FAST mode */
-enum ucc_fast_channel_protocol_mode {
-	UCC_FAST_PROTOCOL_MODE_HDLC = 0x00000000,
-	UCC_FAST_PROTOCOL_MODE_RESERVED01 = 0x00000001,
-	UCC_FAST_PROTOCOL_MODE_RESERVED_QMC = 0x00000002,
-	UCC_FAST_PROTOCOL_MODE_RESERVED02 = 0x00000003,
-	UCC_FAST_PROTOCOL_MODE_RESERVED_UART = 0x00000004,
-	UCC_FAST_PROTOCOL_MODE_RESERVED03 = 0x00000005,
-	UCC_FAST_PROTOCOL_MODE_RESERVED_EX_MAC_1 = 0x00000006,
-	UCC_FAST_PROTOCOL_MODE_RESERVED_EX_MAC_2 = 0x00000007,
-	UCC_FAST_PROTOCOL_MODE_RESERVED_BISYNC = 0x00000008,
-	UCC_FAST_PROTOCOL_MODE_RESERVED04 = 0x00000009,
-	UCC_FAST_PROTOCOL_MODE_ATM = 0x0000000A,
-	UCC_FAST_PROTOCOL_MODE_RESERVED05 = 0x0000000B,
-	UCC_FAST_PROTOCOL_MODE_ETHERNET = 0x0000000C,
-	UCC_FAST_PROTOCOL_MODE_RESERVED06 = 0x0000000D,
-	UCC_FAST_PROTOCOL_MODE_POS = 0x0000000E,
-	UCC_FAST_PROTOCOL_MODE_RESERVED07 = 0x0000000F
-};
-
-/* ucc_fast_transparent_txrx - UCC Fast Transparent TX & RX */
-enum ucc_fast_transparent_txrx {
-	UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL = 0x00000000,
-	UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_TRANSPARENT = 0x18000000
-};
-
-/* UCC fast diagnostic mode */
-enum ucc_fast_diag_mode {
-	UCC_FAST_DIAGNOSTIC_NORMAL = 0x0,
-	UCC_FAST_DIAGNOSTIC_LOCAL_LOOP_BACK = 0x40000000,
-	UCC_FAST_DIAGNOSTIC_AUTO_ECHO = 0x80000000,
-	UCC_FAST_DIAGNOSTIC_LOOP_BACK_AND_ECHO = 0xC0000000
-};
-
-/* UCC fast Sync length (transparent mode only) */
-enum ucc_fast_sync_len {
-	UCC_FAST_SYNC_LEN_NOT_USED = 0x0,
-	UCC_FAST_SYNC_LEN_AUTOMATIC = 0x00004000,
-	UCC_FAST_SYNC_LEN_8_BIT = 0x00008000,
-	UCC_FAST_SYNC_LEN_16_BIT = 0x0000C000
-};
-
-/* UCC fast RTS mode */
-enum ucc_fast_ready_to_send {
-	UCC_FAST_SEND_IDLES_BETWEEN_FRAMES = 0x00000000,
-	UCC_FAST_SEND_FLAGS_BETWEEN_FRAMES = 0x00002000
-};
-
-/* UCC fast receiver decoding mode */
-enum ucc_fast_rx_decoding_method {
-	UCC_FAST_RX_ENCODING_NRZ = 0x00000000,
-	UCC_FAST_RX_ENCODING_NRZI = 0x00000800,
-	UCC_FAST_RX_ENCODING_RESERVED0 = 0x00001000,
-	UCC_FAST_RX_ENCODING_RESERVED1 = 0x00001800
-};
-
-/* UCC fast transmitter encoding mode */
-enum ucc_fast_tx_encoding_method {
-	UCC_FAST_TX_ENCODING_NRZ = 0x00000000,
-	UCC_FAST_TX_ENCODING_NRZI = 0x00000100,
-	UCC_FAST_TX_ENCODING_RESERVED0 = 0x00000200,
-	UCC_FAST_TX_ENCODING_RESERVED1 = 0x00000300
-};
-
-/* UCC fast CRC length */
-enum ucc_fast_transparent_tcrc {
-	UCC_FAST_16_BIT_CRC = 0x00000000,
-	UCC_FAST_CRC_RESERVED0 = 0x00000040,
-	UCC_FAST_32_BIT_CRC = 0x00000080,
-	UCC_FAST_CRC_RESERVED1 = 0x000000C0
-};
-
-/* Fast UCC initialization structure */
-struct ucc_fast_info {
-	int ucc_num;
-	enum qe_clock rx_clock;
-	enum qe_clock tx_clock;
-	u32 regs;
-	int irq;
-	u32 uccm_mask;
-	int bd_mem_part;
-	int brkpt_support;
-	int grant_support;
-	int tsa;
-	int cdp;
-	int cds;
-	int ctsp;
-	int ctss;
-	int tci;
-	int txsy;
-	int rtsm;
-	int revd;
-	int rsyn;
-	u16 max_rx_buf_length;
-	u16 urfs;
-	u16 urfet;
-	u16 urfset;
-	u16 utfs;
-	u16 utfet;
-	u16 utftt;
-	u16 ufpt;
-	enum ucc_fast_channel_protocol_mode mode;
-	enum ucc_fast_transparent_txrx ttx_trx;
-	enum ucc_fast_tx_encoding_method tenc;
-	enum ucc_fast_rx_decoding_method renc;
-	enum ucc_fast_transparent_tcrc tcrc;
-	enum ucc_fast_sync_len synl;
-};
-
-struct ucc_fast_private {
-	struct ucc_fast_info *uf_info;
-	struct ucc_fast __iomem *uf_regs; /* a pointer to the UCC regs. */
-	u32 __iomem *p_ucce;	/* a pointer to the event register in memory. */
-	u32 __iomem *p_uccm;	/* a pointer to the mask register in memory. */
-#ifdef CONFIG_UGETH_TX_ON_DEMAND
-	u16 __iomem *p_utodr;	/* pointer to the transmit on demand register */
-#endif
-	int enabled_tx;		/* Whether channel is enabled for Tx (ENT) */
-	int enabled_rx;		/* Whether channel is enabled for Rx (ENR) */
-	int stopped_tx;		/* Whether channel has been stopped for Tx
-				   (STOP_TX, etc.) */
-	int stopped_rx;		/* Whether channel has been stopped for Rx */
-	u32 ucc_fast_tx_virtual_fifo_base_offset;/* pointer to base of Tx
-						    virtual fifo */
-	u32 ucc_fast_rx_virtual_fifo_base_offset;/* pointer to base of Rx
-						    virtual fifo */
-#ifdef STATISTICS
-	u32 tx_frames;		/* Transmitted frames counter. */
-	u32 rx_frames;		/* Received frames counter (only frames
-				   passed to application). */
-	u32 tx_discarded;	/* Discarded tx frames counter (frames that
-				   were discarded by the driver due to errors).
-				   */
-	u32 rx_discarded;	/* Discarded rx frames counter (frames that
-				   were discarded by the driver due to errors).
-				   */
-#endif				/* STATISTICS */
-	u16 mrblr;		/* maximum receive buffer length */
-};
-
-/* ucc_fast_init
- * Initializes Fast UCC according to user provided parameters.
- *
- * uf_info  - (In) pointer to the fast UCC info structure.
- * uccf_ret - (Out) pointer to the fast UCC structure.
- */
-int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** uccf_ret);
-
-/* ucc_fast_free
- * Frees all resources for fast UCC.
- *
- * uccf - (In) pointer to the fast UCC structure.
- */
-void ucc_fast_free(struct ucc_fast_private * uccf);
-
-/* ucc_fast_enable
- * Enables a fast UCC port.
- * This routine enables Tx and/or Rx through the General UCC Mode Register.
- *
- * uccf - (In) pointer to the fast UCC structure.
- * mode - (In) TX, RX, or both.
- */
-void ucc_fast_enable(struct ucc_fast_private * uccf, enum comm_dir mode);
-
-/* ucc_fast_disable
- * Disables a fast UCC port.
- * This routine disables Tx and/or Rx through the General UCC Mode Register.
- *
- * uccf - (In) pointer to the fast UCC structure.
- * mode - (In) TX, RX, or both.
- */
-void ucc_fast_disable(struct ucc_fast_private * uccf, enum comm_dir mode);
-
-/* ucc_fast_irq
- * Handles interrupts on fast UCC.
- * Called from the general interrupt routine to handle interrupts on fast UCC.
- *
- * uccf - (In) pointer to the fast UCC structure.
- */
-void ucc_fast_irq(struct ucc_fast_private * uccf);
-
-/* ucc_fast_transmit_on_demand
- * Immediately forces a poll of the transmitter for data to be sent.
- * Typically, the hardware performs a periodic poll for data that the
- * transmit routine has set up to be transmitted. In cases where
- * this polling cycle is not soon enough, this optional routine can
- * be invoked to force a poll right away, instead. Proper use for
- * each transmission for which this functionality is desired is to
- * call the transmit routine and then this routine right after.
- *
- * uccf - (In) pointer to the fast UCC structure.
- */
-void ucc_fast_transmit_on_demand(struct ucc_fast_private * uccf);
-
-u32 ucc_fast_get_qe_cr_subblock(int uccf_num);
-
-void ucc_fast_dump_regs(struct ucc_fast_private * uccf);
-
-#endif				/* __UCC_FAST_H__ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/ucc_slow.h b/ANDROID_3.4.5/arch/powerpc/include/asm/ucc_slow.h
deleted file mode 100644
index 0980e6ad..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/ucc_slow.h
+++ /dev/null
@@ -1,290 +0,0 @@
-/*
- * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
- *
- * Authors: 	Shlomi Gridish <gridish@freescale.com>
- * 		Li Yang <leoli@freescale.com>
- *
- * Description:
- * Internal header file for UCC SLOW unit routines.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-#ifndef __UCC_SLOW_H__
-#define __UCC_SLOW_H__
-
-#include <linux/kernel.h>
-
-#include <asm/immap_qe.h>
-#include <asm/qe.h>
-
-#include "ucc.h"
-
-/* transmit BD's status */
-#define T_R	0x80000000	/* ready bit */
-#define T_PAD	0x40000000	/* add pads to short frames */
-#define T_W	0x20000000	/* wrap bit */
-#define T_I	0x10000000	/* interrupt on completion */
-#define T_L	0x08000000	/* last */
-
-#define T_A	0x04000000	/* Address - the data transmitted as address
-				   chars */
-#define T_TC	0x04000000	/* transmit CRC */
-#define T_CM	0x02000000	/* continuous mode */
-#define T_DEF	0x02000000	/* collision on previous attempt to transmit */
-#define T_P	0x01000000	/* Preamble - send Preamble sequence before
-				   data */
-#define T_HB	0x01000000	/* heartbeat */
-#define T_NS	0x00800000	/* No Stop */
-#define T_LC	0x00800000	/* late collision */
-#define T_RL	0x00400000	/* retransmission limit */
-#define T_UN	0x00020000	/* underrun */
-#define T_CT	0x00010000	/* CTS lost */
-#define T_CSL	0x00010000	/* carrier sense lost */
-#define T_RC	0x003c0000	/* retry count */
-
-/* Receive BD's status */
-#define R_E	0x80000000	/* buffer empty */
-#define R_W	0x20000000	/* wrap bit */
-#define R_I	0x10000000	/* interrupt on reception */
-#define R_L	0x08000000	/* last */
-#define R_C	0x08000000	/* the last byte in this buffer is a cntl
-				   char */
-#define R_F	0x04000000	/* first */
-#define R_A	0x04000000	/* the first byte in this buffer is address
-				   byte */
-#define R_CM	0x02000000	/* continuous mode */
-#define R_ID	0x01000000	/* buffer close on reception of idles */
-#define R_M	0x01000000	/* Frame received because of promiscuous
-				   mode */
-#define R_AM	0x00800000	/* Address match */
-#define R_DE	0x00800000	/* Address match */
-#define R_LG	0x00200000	/* Break received */
-#define R_BR	0x00200000	/* Frame length violation */
-#define R_NO	0x00100000	/* Rx Non Octet Aligned Packet */
-#define R_FR	0x00100000	/* Framing Error (no stop bit) character
-				   received */
-#define R_PR	0x00080000	/* Parity Error character received */
-#define R_AB	0x00080000	/* Frame Aborted */
-#define R_SH	0x00080000	/* frame is too short */
-#define R_CR	0x00040000	/* CRC Error */
-#define R_OV	0x00020000	/* Overrun */
-#define R_CD	0x00010000	/* CD lost */
-#define R_CL	0x00010000	/* this frame is closed because of a
-				   collision */
-
-/* Rx Data buffer must be 4 bytes aligned in most cases.*/
-#define UCC_SLOW_RX_ALIGN		4
-#define UCC_SLOW_MRBLR_ALIGNMENT	4
-#define UCC_SLOW_PRAM_SIZE		0x100
-#define ALIGNMENT_OF_UCC_SLOW_PRAM	64
-
-/* UCC Slow Channel Protocol Mode */
-enum ucc_slow_channel_protocol_mode {
-	UCC_SLOW_CHANNEL_PROTOCOL_MODE_QMC = 0x00000002,
-	UCC_SLOW_CHANNEL_PROTOCOL_MODE_UART = 0x00000004,
-	UCC_SLOW_CHANNEL_PROTOCOL_MODE_BISYNC = 0x00000008,
-};
-
-/* UCC Slow Transparent Transmit CRC (TCRC) */
-enum ucc_slow_transparent_tcrc {
-	/* 16-bit CCITT CRC (HDLC).  (X16 + X12 + X5 + 1) */
-	UCC_SLOW_TRANSPARENT_TCRC_CCITT_CRC16 = 0x00000000,
-	/* CRC16 (BISYNC).  (X16 + X15 + X2 + 1) */
-	UCC_SLOW_TRANSPARENT_TCRC_CRC16 = 0x00004000,
-	/* 32-bit CCITT CRC (Ethernet and HDLC) */
-	UCC_SLOW_TRANSPARENT_TCRC_CCITT_CRC32 = 0x00008000,
-};
-
-/* UCC Slow oversampling rate for transmitter (TDCR) */
-enum ucc_slow_tx_oversampling_rate {
-	/* 1x clock mode */
-	UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_1 = 0x00000000,
-	/* 8x clock mode */
-	UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_8 = 0x00010000,
-	/* 16x clock mode */
-	UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_16 = 0x00020000,
-	/* 32x clock mode */
-	UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_32 = 0x00030000,
-};
-
-/* UCC Slow Oversampling rate for receiver (RDCR)
-*/
-enum ucc_slow_rx_oversampling_rate {
-	/* 1x clock mode */
-	UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_1 = 0x00000000,
-	/* 8x clock mode */
-	UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_8 = 0x00004000,
-	/* 16x clock mode */
-	UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_16 = 0x00008000,
-	/* 32x clock mode */
-	UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_32 = 0x0000c000,
-};
-
-/* UCC Slow Transmitter encoding method (TENC)
-*/
-enum ucc_slow_tx_encoding_method {
-	UCC_SLOW_TRANSMITTER_ENCODING_METHOD_TENC_NRZ = 0x00000000,
-	UCC_SLOW_TRANSMITTER_ENCODING_METHOD_TENC_NRZI = 0x00000100
-};
-
-/* UCC Slow Receiver decoding method (RENC)
-*/
-enum ucc_slow_rx_decoding_method {
-	UCC_SLOW_RECEIVER_DECODING_METHOD_RENC_NRZ = 0x00000000,
-	UCC_SLOW_RECEIVER_DECODING_METHOD_RENC_NRZI = 0x00000800
-};
-
-/* UCC Slow Diagnostic mode (DIAG)
-*/
-enum ucc_slow_diag_mode {
-	UCC_SLOW_DIAG_MODE_NORMAL = 0x00000000,
-	UCC_SLOW_DIAG_MODE_LOOPBACK = 0x00000040,
-	UCC_SLOW_DIAG_MODE_ECHO = 0x00000080,
-	UCC_SLOW_DIAG_MODE_LOOPBACK_ECHO = 0x000000c0
-};
-
-struct ucc_slow_info {
-	int ucc_num;
-	int protocol;			/* QE_CR_PROTOCOL_xxx */
-	enum qe_clock rx_clock;
-	enum qe_clock tx_clock;
-	phys_addr_t regs;
-	int irq;
-	u16 uccm_mask;
-	int data_mem_part;
-	int init_tx;
-	int init_rx;
-	u32 tx_bd_ring_len;
-	u32 rx_bd_ring_len;
-	int rx_interrupts;
-	int brkpt_support;
-	int grant_support;
-	int tsa;
-	int cdp;
-	int cds;
-	int ctsp;
-	int ctss;
-	int rinv;
-	int tinv;
-	int rtsm;
-	int rfw;
-	int tci;
-	int tend;
-	int tfl;
-	int txsy;
-	u16 max_rx_buf_length;
-	enum ucc_slow_transparent_tcrc tcrc;
-	enum ucc_slow_channel_protocol_mode mode;
-	enum ucc_slow_diag_mode diag;
-	enum ucc_slow_tx_oversampling_rate tdcr;
-	enum ucc_slow_rx_oversampling_rate rdcr;
-	enum ucc_slow_tx_encoding_method tenc;
-	enum ucc_slow_rx_decoding_method renc;
-};
-
-struct ucc_slow_private {
-	struct ucc_slow_info *us_info;
-	struct ucc_slow __iomem *us_regs; /* Ptr to memory map of UCC regs */
-	struct ucc_slow_pram *us_pram;	/* a pointer to the parameter RAM */
-	u32 us_pram_offset;
-	int enabled_tx;		/* Whether channel is enabled for Tx (ENT) */
-	int enabled_rx;		/* Whether channel is enabled for Rx (ENR) */
-	int stopped_tx;		/* Whether channel has been stopped for Tx
-				   (STOP_TX, etc.) */
-	int stopped_rx;		/* Whether channel has been stopped for Rx */
-	struct list_head confQ;	/* frames passed to chip waiting for tx */
-	u32 first_tx_bd_mask;	/* mask is used in Tx routine to save status
-				   and length for first BD in a frame */
-	u32 tx_base_offset;	/* first BD in Tx BD table offset (In MURAM) */
-	u32 rx_base_offset;	/* first BD in Rx BD table offset (In MURAM) */
-	struct qe_bd *confBd;	/* next BD for confirm after Tx */
-	struct qe_bd *tx_bd;	/* next BD for new Tx request */
-	struct qe_bd *rx_bd;	/* next BD to collect after Rx */
-	void *p_rx_frame;	/* accumulating receive frame */
-	u16 *p_ucce;		/* a pointer to the event register in memory.
-				 */
-	u16 *p_uccm;		/* a pointer to the mask register in memory */
-	u16 saved_uccm;		/* a saved mask for the RX Interrupt bits */
-#ifdef STATISTICS
-	u32 tx_frames;		/* Transmitted frames counters */
-	u32 rx_frames;		/* Received frames counters (only frames
-				   passed to application) */
-	u32 rx_discarded;	/* Discarded frames counters (frames that
-				   were discarded by the driver due to
-				   errors) */
-#endif				/* STATISTICS */
-};
-
-/* ucc_slow_init
- * Initializes Slow UCC according to provided parameters.
- *
- * us_info  - (In) pointer to the slow UCC info structure.
- * uccs_ret - (Out) pointer to the slow UCC structure.
- */
-int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** uccs_ret);
-
-/* ucc_slow_free
- * Frees all resources for slow UCC.
- *
- * uccs - (In) pointer to the slow UCC structure.
- */
-void ucc_slow_free(struct ucc_slow_private * uccs);
-
-/* ucc_slow_enable
- * Enables a fast UCC port.
- * This routine enables Tx and/or Rx through the General UCC Mode Register.
- *
- * uccs - (In) pointer to the slow UCC structure.
- * mode - (In) TX, RX, or both.
- */
-void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode);
-
-/* ucc_slow_disable
- * Disables a fast UCC port.
- * This routine disables Tx and/or Rx through the General UCC Mode Register.
- *
- * uccs - (In) pointer to the slow UCC structure.
- * mode - (In) TX, RX, or both.
- */
-void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode);
-
-/* ucc_slow_poll_transmitter_now
- * Immediately forces a poll of the transmitter for data to be sent.
- * Typically, the hardware performs a periodic poll for data that the
- * transmit routine has set up to be transmitted. In cases where
- * this polling cycle is not soon enough, this optional routine can
- * be invoked to force a poll right away, instead. Proper use for
- * each transmission for which this functionality is desired is to
- * call the transmit routine and then this routine right after.
- *
- * uccs - (In) pointer to the slow UCC structure.
- */
-void ucc_slow_poll_transmitter_now(struct ucc_slow_private * uccs);
-
-/* ucc_slow_graceful_stop_tx
- * Smoothly stops transmission on a specified slow UCC.
- *
- * uccs - (In) pointer to the slow UCC structure.
- */
-void ucc_slow_graceful_stop_tx(struct ucc_slow_private * uccs);
-
-/* ucc_slow_stop_tx
- * Stops transmission on a specified slow UCC.
- *
- * uccs - (In) pointer to the slow UCC structure.
- */
-void ucc_slow_stop_tx(struct ucc_slow_private * uccs);
-
-/* ucc_slow_restart_tx
- * Restarts transmitting on a specified slow UCC.
- *
- * uccs - (In) pointer to the slow UCC structure.
- */
-void ucc_slow_restart_tx(struct ucc_slow_private *uccs);
-
-u32 ucc_slow_get_qe_cr_subblock(int uccs_num);
-
-#endif				/* __UCC_SLOW_H__ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/ucontext.h b/ANDROID_3.4.5/arch/powerpc/include/asm/ucontext.h
deleted file mode 100644
index d9a4ddf0..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/ucontext.h
+++ /dev/null
@@ -1,40 +0,0 @@
-#ifndef _ASM_POWERPC_UCONTEXT_H
-#define _ASM_POWERPC_UCONTEXT_H
-
-#ifdef __powerpc64__
-#include <asm/sigcontext.h>
-#else
-#include <asm/elf.h>
-#endif
-#include <asm/signal.h>
-
-#ifndef __powerpc64__
-struct mcontext {
-	elf_gregset_t	mc_gregs;
-	elf_fpregset_t	mc_fregs;
-	unsigned long	mc_pad[2];
-	elf_vrregset_t	mc_vregs __attribute__((__aligned__(16)));
-};
-#endif
-
-struct ucontext {
-	unsigned long	uc_flags;
-	struct ucontext __user *uc_link;
-	stack_t		uc_stack;
-#ifndef __powerpc64__
-	int		uc_pad[7];
-	struct mcontext	__user *uc_regs;/* points to uc_mcontext field */
-#endif
-	sigset_t	uc_sigmask;
-	/* glibc has 1024-bit signal masks, ours are 64-bit */
-#ifdef __powerpc64__
-	sigset_t	__unused[15];	/* Allow for uc_sigmask growth */
-	struct sigcontext uc_mcontext;	/* last for extensibility */
-#else
-	int		uc_maskext[30];
-	int		uc_pad2[3];
-	struct mcontext	uc_mcontext;
-#endif
-};
-
-#endif /* _ASM_POWERPC_UCONTEXT_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/udbg.h b/ANDROID_3.4.5/arch/powerpc/include/asm/udbg.h
deleted file mode 100644
index b3038817..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/udbg.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * (c) 2001, 2006 IBM Corporation.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_POWERPC_UDBG_H
-#define _ASM_POWERPC_UDBG_H
-#ifdef __KERNEL__
-
-#include <linux/compiler.h>
-#include <linux/init.h>
-
-extern void (*udbg_putc)(char c);
-extern void (*udbg_flush)(void);
-extern int (*udbg_getc)(void);
-extern int (*udbg_getc_poll)(void);
-
-extern void udbg_puts(const char *s);
-extern int udbg_write(const char *s, int n);
-extern int udbg_read(char *buf, int buflen);
-
-extern void register_early_udbg_console(void);
-extern void udbg_printf(const char *fmt, ...)
-	__attribute__ ((format (printf, 1, 2)));
-extern void udbg_progress(char *s, unsigned short hex);
-
-extern void udbg_init_uart(void __iomem *comport, unsigned int speed,
-			   unsigned int clock);
-extern unsigned int udbg_probe_uart_speed(void __iomem *comport,
-					  unsigned int clock);
-
-struct device_node;
-extern void udbg_scc_init(int force_scc);
-extern int udbg_adb_init(int force_btext);
-extern void udbg_adb_init_early(void);
-
-extern void __init udbg_early_init(void);
-extern void __init udbg_init_debug_lpar(void);
-extern void __init udbg_init_debug_lpar_hvsi(void);
-extern void __init udbg_init_pmac_realmode(void);
-extern void __init udbg_init_maple_realmode(void);
-extern void __init udbg_init_pas_realmode(void);
-extern void __init udbg_init_rtas_panel(void);
-extern void __init udbg_init_rtas_console(void);
-extern void __init udbg_init_debug_beat(void);
-extern void __init udbg_init_btext(void);
-extern void __init udbg_init_44x_as1(void);
-extern void __init udbg_init_40x_realmode(void);
-extern void __init udbg_init_cpm(void);
-extern void __init udbg_init_usbgecko(void);
-extern void __init udbg_init_wsp(void);
-extern void __init udbg_init_ehv_bc(void);
-extern void __init udbg_init_ps3gelic(void);
-extern void __init udbg_init_debug_opal_raw(void);
-extern void __init udbg_init_debug_opal_hvsi(void);
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_UDBG_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/uic.h b/ANDROID_3.4.5/arch/powerpc/include/asm/uic.h
deleted file mode 100644
index 597edfca..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/uic.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * IBM PPC4xx UIC external definitions and structure.
- *
- * Maintainer: David Gibson <dwg@au1.ibm.com>
- * Copyright 2007 IBM Corporation.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-#ifndef _ASM_POWERPC_UIC_H
-#define _ASM_POWERPC_UIC_H
-
-#ifdef __KERNEL__
-
-extern void __init uic_init_tree(void);
-extern unsigned int uic_get_irq(void);
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_UIC_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/unaligned.h b/ANDROID_3.4.5/arch/powerpc/include/asm/unaligned.h
deleted file mode 100644
index 5f1b1e3c..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/unaligned.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#ifndef _ASM_POWERPC_UNALIGNED_H
-#define _ASM_POWERPC_UNALIGNED_H
-
-#ifdef __KERNEL__
-
-/*
- * The PowerPC can do unaligned accesses itself in big endian mode.
- */
-#include <linux/unaligned/access_ok.h>
-#include <linux/unaligned/generic.h>
-
-#define get_unaligned	__get_unaligned_be
-#define put_unaligned	__put_unaligned_be
-
-#endif	/* __KERNEL__ */
-#endif	/* _ASM_POWERPC_UNALIGNED_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/uninorth.h b/ANDROID_3.4.5/arch/powerpc/include/asm/uninorth.h
deleted file mode 100644
index d12b11d7..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/uninorth.h
+++ /dev/null
@@ -1,229 +0,0 @@
-/*
- * uninorth.h: definitions for using the "UniNorth" host bridge chip
- *             from Apple. This chip is used on "Core99" machines
- *	       This also includes U2 used on more recent MacRISC2/3
- *             machines and U3 (G5) 
- *
- */
-#ifdef __KERNEL__
-#ifndef __ASM_UNINORTH_H__
-#define __ASM_UNINORTH_H__
-
-/*
- * Uni-N and U3 config space reg. definitions
- *
- * (Little endian)
- */
-
-/* Address ranges selection. This one should work with Bandit too */
-/* Not U3 */
-#define UNI_N_ADDR_SELECT		0x48
-#define UNI_N_ADDR_COARSE_MASK		0xffff0000	/* 256Mb regions at *0000000 */
-#define UNI_N_ADDR_FINE_MASK		0x0000ffff	/*  16Mb regions at f*000000 */
-
-/* AGP registers */
-/* Not U3 */
-#define UNI_N_CFG_GART_BASE		0x8c
-#define UNI_N_CFG_AGP_BASE		0x90
-#define UNI_N_CFG_GART_CTRL		0x94
-#define UNI_N_CFG_INTERNAL_STATUS	0x98
-#define UNI_N_CFG_GART_DUMMY_PAGE	0xa4
-
-/* UNI_N_CFG_GART_CTRL bits definitions */
-#define UNI_N_CFG_GART_INVAL		0x00000001
-#define UNI_N_CFG_GART_ENABLE		0x00000100
-#define UNI_N_CFG_GART_2xRESET		0x00010000
-#define UNI_N_CFG_GART_DISSBADET	0x00020000
-/* The following seems to only be used only on U3 <j.glisse@gmail.com> */
-#define U3_N_CFG_GART_SYNCMODE		0x00040000
-#define U3_N_CFG_GART_PERFRD		0x00080000
-#define U3_N_CFG_GART_B2BGNT		0x00200000
-#define U3_N_CFG_GART_FASTDDR		0x00400000
-
-/* My understanding of UniNorth AGP as of UniNorth rev 1.0x,
- * revision 1.5 (x4 AGP) may need further changes.
- *
- * AGP_BASE register contains the base address of the AGP aperture on
- * the AGP bus. It doesn't seem to be visible to the CPU as of UniNorth 1.x,
- * even if decoding of this address range is enabled in the address select
- * register. Apparently, the only supported bases are 256Mb multiples
- * (high 4 bits of that register).
- *
- * GART_BASE register appear to contain the physical address of the GART
- * in system memory in the high address bits (page aligned), and the
- * GART size in the low order bits (number of GART pages)
- *
- * The GART format itself is one 32bits word per physical memory page.
- * This word contains, in little-endian format (!!!), the physical address
- * of the page in the high bits, and what appears to be an "enable" bit
- * in the LSB bit (0) that must be set to 1 when the entry is valid.
- *
- * Obviously, the GART is not cache coherent and so any change to it
- * must be flushed to memory (or maybe just make the GART space non
- * cachable). AGP memory itself doesn't seem to be cache coherent neither.
- *
- * In order to invalidate the GART (which is probably necessary to inval
- * the bridge internal TLBs), the following sequence has to be written,
- * in order, to the GART_CTRL register:
- *
- *   UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_INVAL
- *   UNI_N_CFG_GART_ENABLE
- *   UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_2xRESET
- *   UNI_N_CFG_GART_ENABLE
- *
- * As far as AGP "features" are concerned, it looks like fast write may
- * not be supported but this has to be confirmed.
- *
- * Turning on AGP seem to require a double invalidate operation, one before
- * setting the AGP command register, on after.
- *
- * Turning off AGP seems to require the following sequence: first wait
- * for the AGP to be idle by reading the internal status register, then
- * write in that order to the GART_CTRL register:
- *
- *   UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_INVAL
- *   0
- *   UNI_N_CFG_GART_2xRESET
- *   0
- */
-
-/*
- * Uni-N memory mapped reg. definitions
- *
- * Those registers are Big-Endian !!
- *
- * Their meaning come from either Darwin and/or from experiments I made with
- * the bootrom, I'm not sure about their exact meaning yet
- *
- */
-
-/* Version of the UniNorth chip */
-#define UNI_N_VERSION			0x0000		/* Known versions: 3,7 and 8 */
-
-#define UNI_N_VERSION_107		0x0003		/* 1.0.7 */
-#define UNI_N_VERSION_10A		0x0007		/* 1.0.10 */
-#define UNI_N_VERSION_150		0x0011		/* 1.5 */
-#define UNI_N_VERSION_200		0x0024		/* 2.0 */
-#define UNI_N_VERSION_PANGEA		0x00C0		/* Integrated U1 + K */
-#define UNI_N_VERSION_INTREPID		0x00D2		/* Integrated U2 + K */
-#define UNI_N_VERSION_300		0x0030		/* 3.0 (U3 on G5) */
-
-/* This register is used to enable/disable various clocks */
-#define UNI_N_CLOCK_CNTL		0x0020
-#define UNI_N_CLOCK_CNTL_PCI		0x00000001	/* PCI2 clock control */
-#define UNI_N_CLOCK_CNTL_GMAC		0x00000002	/* GMAC clock control */
-#define UNI_N_CLOCK_CNTL_FW		0x00000004	/* FireWire clock control */
-#define UNI_N_CLOCK_CNTL_ATA100		0x00000010	/* ATA-100 clock control (U2) */
-
-/* Power Management control */
-#define UNI_N_POWER_MGT			0x0030
-#define UNI_N_POWER_MGT_NORMAL		0x00
-#define UNI_N_POWER_MGT_IDLE2		0x01
-#define UNI_N_POWER_MGT_SLEEP		0x02
-
-/* This register is configured by Darwin depending on the UniN
- * revision
- */
-#define UNI_N_ARB_CTRL			0x0040
-#define UNI_N_ARB_CTRL_QACK_DELAY_SHIFT	15
-#define UNI_N_ARB_CTRL_QACK_DELAY_MASK	0x0e1f8000
-#define UNI_N_ARB_CTRL_QACK_DELAY	0x30
-#define UNI_N_ARB_CTRL_QACK_DELAY105	0x00
-
-/* This one _might_ return the CPU number of the CPU reading it;
- * the bootROM decides whether to boot or to sleep/spinloop depending
- * on this register beeing 0 or not
- */
-#define UNI_N_CPU_NUMBER		0x0050
-
-/* This register appear to be read by the bootROM to decide what
- *  to do on a non-recoverable reset (powerup or wakeup)
- */
-#define UNI_N_HWINIT_STATE		0x0070
-#define UNI_N_HWINIT_STATE_SLEEPING	0x01
-#define UNI_N_HWINIT_STATE_RUNNING	0x02
-/* This last bit appear to be used by the bootROM to know the second
- * CPU has started and will enter it's sleep loop with IP=0
- */
-#define UNI_N_HWINIT_STATE_CPU1_FLAG	0x10000000
-
-/* This register controls AACK delay, which is set when 2004 iBook/PowerBook
- * is in low speed mode.
- */
-#define UNI_N_AACK_DELAY		0x0100
-#define UNI_N_AACK_DELAY_ENABLE		0x00000001
-
-/* Clock status for Intrepid */
-#define UNI_N_CLOCK_STOP_STATUS0	0x0150
-#define UNI_N_CLOCK_STOPPED_EXTAGP	0x00200000
-#define UNI_N_CLOCK_STOPPED_AGPDEL	0x00100000
-#define UNI_N_CLOCK_STOPPED_I2S0_45_49	0x00080000
-#define UNI_N_CLOCK_STOPPED_I2S0_18	0x00040000
-#define UNI_N_CLOCK_STOPPED_I2S1_45_49	0x00020000
-#define UNI_N_CLOCK_STOPPED_I2S1_18	0x00010000
-#define UNI_N_CLOCK_STOPPED_TIMER	0x00008000
-#define UNI_N_CLOCK_STOPPED_SCC_RTCLK18	0x00004000
-#define UNI_N_CLOCK_STOPPED_SCC_RTCLK32	0x00002000
-#define UNI_N_CLOCK_STOPPED_SCC_VIA32	0x00001000
-#define UNI_N_CLOCK_STOPPED_SCC_SLOT0	0x00000800
-#define UNI_N_CLOCK_STOPPED_SCC_SLOT1	0x00000400
-#define UNI_N_CLOCK_STOPPED_SCC_SLOT2	0x00000200
-#define UNI_N_CLOCK_STOPPED_PCI_FBCLKO	0x00000100
-#define UNI_N_CLOCK_STOPPED_VEO0	0x00000080
-#define UNI_N_CLOCK_STOPPED_VEO1	0x00000040
-#define UNI_N_CLOCK_STOPPED_USB0	0x00000020
-#define UNI_N_CLOCK_STOPPED_USB1	0x00000010
-#define UNI_N_CLOCK_STOPPED_USB2	0x00000008
-#define UNI_N_CLOCK_STOPPED_32		0x00000004
-#define UNI_N_CLOCK_STOPPED_45		0x00000002
-#define UNI_N_CLOCK_STOPPED_49		0x00000001
-
-#define UNI_N_CLOCK_STOP_STATUS1	0x0160
-#define UNI_N_CLOCK_STOPPED_PLL4REF	0x00080000
-#define UNI_N_CLOCK_STOPPED_CPUDEL	0x00040000
-#define UNI_N_CLOCK_STOPPED_CPU		0x00020000
-#define UNI_N_CLOCK_STOPPED_BUF_REFCKO	0x00010000
-#define UNI_N_CLOCK_STOPPED_PCI2	0x00008000
-#define UNI_N_CLOCK_STOPPED_FW		0x00004000
-#define UNI_N_CLOCK_STOPPED_GB		0x00002000
-#define UNI_N_CLOCK_STOPPED_ATA66	0x00001000
-#define UNI_N_CLOCK_STOPPED_ATA100	0x00000800
-#define UNI_N_CLOCK_STOPPED_MAX		0x00000400
-#define UNI_N_CLOCK_STOPPED_PCI1	0x00000200
-#define UNI_N_CLOCK_STOPPED_KLPCI	0x00000100
-#define UNI_N_CLOCK_STOPPED_USB0PCI	0x00000080
-#define UNI_N_CLOCK_STOPPED_USB1PCI	0x00000040
-#define UNI_N_CLOCK_STOPPED_USB2PCI	0x00000020
-#define UNI_N_CLOCK_STOPPED_7PCI1	0x00000008
-#define UNI_N_CLOCK_STOPPED_AGP		0x00000004
-#define UNI_N_CLOCK_STOPPED_PCI0	0x00000002
-#define UNI_N_CLOCK_STOPPED_18		0x00000001
-
-/* Intrepid registe to OF do-platform-clockspreading */
-#define UNI_N_CLOCK_SPREADING		0x190
-
-/* Uninorth 1.5 rev. has additional perf. monitor registers at 0xf00-0xf50 */
-
-
-/*
- * U3 specific registers
- */
-
-
-/* U3 Toggle */
-#define U3_TOGGLE_REG			0x00e0
-#define U3_PMC_START_STOP		0x0001
-#define U3_MPIC_RESET			0x0002
-#define U3_MPIC_OUTPUT_ENABLE		0x0004
-
-/* U3 API PHY Config 1 */
-#define U3_API_PHY_CONFIG_1		0x23030
-
-/* U3 HyperTransport registers */
-#define U3_HT_CONFIG_BASE      		0x70000
-#define U3_HT_LINK_COMMAND		0x100
-#define U3_HT_LINK_CONFIG		0x110
-#define U3_HT_LINK_FREQ			0x120
-
-#endif /* __ASM_UNINORTH_H__ */
-#endif /* __KERNEL__ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/unistd.h b/ANDROID_3.4.5/arch/powerpc/include/asm/unistd.h
deleted file mode 100644
index d3d1b5ef..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/unistd.h
+++ /dev/null
@@ -1,434 +0,0 @@
-#ifndef _ASM_POWERPC_UNISTD_H_
-#define _ASM_POWERPC_UNISTD_H_
-
-/*
- * This file contains the system call numbers.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#define __NR_restart_syscall	  0
-#define __NR_exit		  1
-#define __NR_fork		  2
-#define __NR_read		  3
-#define __NR_write		  4
-#define __NR_open		  5
-#define __NR_close		  6
-#define __NR_waitpid		  7
-#define __NR_creat		  8
-#define __NR_link		  9
-#define __NR_unlink		 10
-#define __NR_execve		 11
-#define __NR_chdir		 12
-#define __NR_time		 13
-#define __NR_mknod		 14
-#define __NR_chmod		 15
-#define __NR_lchown		 16
-#define __NR_break		 17
-#define __NR_oldstat		 18
-#define __NR_lseek		 19
-#define __NR_getpid		 20
-#define __NR_mount		 21
-#define __NR_umount		 22
-#define __NR_setuid		 23
-#define __NR_getuid		 24
-#define __NR_stime		 25
-#define __NR_ptrace		 26
-#define __NR_alarm		 27
-#define __NR_oldfstat		 28
-#define __NR_pause		 29
-#define __NR_utime		 30
-#define __NR_stty		 31
-#define __NR_gtty		 32
-#define __NR_access		 33
-#define __NR_nice		 34
-#define __NR_ftime		 35
-#define __NR_sync		 36
-#define __NR_kill		 37
-#define __NR_rename		 38
-#define __NR_mkdir		 39
-#define __NR_rmdir		 40
-#define __NR_dup		 41
-#define __NR_pipe		 42
-#define __NR_times		 43
-#define __NR_prof		 44
-#define __NR_brk		 45
-#define __NR_setgid		 46
-#define __NR_getgid		 47
-#define __NR_signal		 48
-#define __NR_geteuid		 49
-#define __NR_getegid		 50
-#define __NR_acct		 51
-#define __NR_umount2		 52
-#define __NR_lock		 53
-#define __NR_ioctl		 54
-#define __NR_fcntl		 55
-#define __NR_mpx		 56
-#define __NR_setpgid		 57
-#define __NR_ulimit		 58
-#define __NR_oldolduname	 59
-#define __NR_umask		 60
-#define __NR_chroot		 61
-#define __NR_ustat		 62
-#define __NR_dup2		 63
-#define __NR_getppid		 64
-#define __NR_getpgrp		 65
-#define __NR_setsid		 66
-#define __NR_sigaction		 67
-#define __NR_sgetmask		 68
-#define __NR_ssetmask		 69
-#define __NR_setreuid		 70
-#define __NR_setregid		 71
-#define __NR_sigsuspend		 72
-#define __NR_sigpending		 73
-#define __NR_sethostname	 74
-#define __NR_setrlimit		 75
-#define __NR_getrlimit		 76
-#define __NR_getrusage		 77
-#define __NR_gettimeofday	 78
-#define __NR_settimeofday	 79
-#define __NR_getgroups		 80
-#define __NR_setgroups		 81
-#define __NR_select		 82
-#define __NR_symlink		 83
-#define __NR_oldlstat		 84
-#define __NR_readlink		 85
-#define __NR_uselib		 86
-#define __NR_swapon		 87
-#define __NR_reboot		 88
-#define __NR_readdir		 89
-#define __NR_mmap		 90
-#define __NR_munmap		 91
-#define __NR_truncate		 92
-#define __NR_ftruncate		 93
-#define __NR_fchmod		 94
-#define __NR_fchown		 95
-#define __NR_getpriority	 96
-#define __NR_setpriority	 97
-#define __NR_profil		 98
-#define __NR_statfs		 99
-#define __NR_fstatfs		100
-#define __NR_ioperm		101
-#define __NR_socketcall		102
-#define __NR_syslog		103
-#define __NR_setitimer		104
-#define __NR_getitimer		105
-#define __NR_stat		106
-#define __NR_lstat		107
-#define __NR_fstat		108
-#define __NR_olduname		109
-#define __NR_iopl		110
-#define __NR_vhangup		111
-#define __NR_idle		112
-#define __NR_vm86		113
-#define __NR_wait4		114
-#define __NR_swapoff		115
-#define __NR_sysinfo		116
-#define __NR_ipc		117
-#define __NR_fsync		118
-#define __NR_sigreturn		119
-#define __NR_clone		120
-#define __NR_setdomainname	121
-#define __NR_uname		122
-#define __NR_modify_ldt		123
-#define __NR_adjtimex		124
-#define __NR_mprotect		125
-#define __NR_sigprocmask	126
-#define __NR_create_module	127
-#define __NR_init_module	128
-#define __NR_delete_module	129
-#define __NR_get_kernel_syms	130
-#define __NR_quotactl		131
-#define __NR_getpgid		132
-#define __NR_fchdir		133
-#define __NR_bdflush		134
-#define __NR_sysfs		135
-#define __NR_personality	136
-#define __NR_afs_syscall	137 /* Syscall for Andrew File System */
-#define __NR_setfsuid		138
-#define __NR_setfsgid		139
-#define __NR__llseek		140
-#define __NR_getdents		141
-#define __NR__newselect		142
-#define __NR_flock		143
-#define __NR_msync		144
-#define __NR_readv		145
-#define __NR_writev		146
-#define __NR_getsid		147
-#define __NR_fdatasync		148
-#define __NR__sysctl		149
-#define __NR_mlock		150
-#define __NR_munlock		151
-#define __NR_mlockall		152
-#define __NR_munlockall		153
-#define __NR_sched_setparam		154
-#define __NR_sched_getparam		155
-#define __NR_sched_setscheduler		156
-#define __NR_sched_getscheduler		157
-#define __NR_sched_yield		158
-#define __NR_sched_get_priority_max	159
-#define __NR_sched_get_priority_min	160
-#define __NR_sched_rr_get_interval	161
-#define __NR_nanosleep		162
-#define __NR_mremap		163
-#define __NR_setresuid		164
-#define __NR_getresuid		165
-#define __NR_query_module	166
-#define __NR_poll		167
-#define __NR_nfsservctl		168
-#define __NR_setresgid		169
-#define __NR_getresgid		170
-#define __NR_prctl		171
-#define __NR_rt_sigreturn	172
-#define __NR_rt_sigaction	173
-#define __NR_rt_sigprocmask	174
-#define __NR_rt_sigpending	175
-#define __NR_rt_sigtimedwait	176
-#define __NR_rt_sigqueueinfo	177
-#define __NR_rt_sigsuspend	178
-#define __NR_pread64		179
-#define __NR_pwrite64		180
-#define __NR_chown		181
-#define __NR_getcwd		182
-#define __NR_capget		183
-#define __NR_capset		184
-#define __NR_sigaltstack	185
-#define __NR_sendfile		186
-#define __NR_getpmsg		187	/* some people actually want streams */
-#define __NR_putpmsg		188	/* some people actually want streams */
-#define __NR_vfork		189
-#define __NR_ugetrlimit		190	/* SuS compliant getrlimit */
-#define __NR_readahead		191
-#ifndef __powerpc64__			/* these are 32-bit only */
-#define __NR_mmap2		192
-#define __NR_truncate64		193
-#define __NR_ftruncate64	194
-#define __NR_stat64		195
-#define __NR_lstat64		196
-#define __NR_fstat64		197
-#endif
-#define __NR_pciconfig_read	198
-#define __NR_pciconfig_write	199
-#define __NR_pciconfig_iobase	200
-#define __NR_multiplexer	201
-#define __NR_getdents64		202
-#define __NR_pivot_root		203
-#ifndef __powerpc64__
-#define __NR_fcntl64		204
-#endif
-#define __NR_madvise		205
-#define __NR_mincore		206
-#define __NR_gettid		207
-#define __NR_tkill		208
-#define __NR_setxattr		209
-#define __NR_lsetxattr		210
-#define __NR_fsetxattr		211
-#define __NR_getxattr		212
-#define __NR_lgetxattr		213
-#define __NR_fgetxattr		214
-#define __NR_listxattr		215
-#define __NR_llistxattr		216
-#define __NR_flistxattr		217
-#define __NR_removexattr	218
-#define __NR_lremovexattr	219
-#define __NR_fremovexattr	220
-#define __NR_futex		221
-#define __NR_sched_setaffinity	222
-#define __NR_sched_getaffinity	223
-/* 224 currently unused */
-#define __NR_tuxcall		225
-#ifndef __powerpc64__
-#define __NR_sendfile64		226
-#endif
-#define __NR_io_setup		227
-#define __NR_io_destroy		228
-#define __NR_io_getevents	229
-#define __NR_io_submit		230
-#define __NR_io_cancel		231
-#define __NR_set_tid_address	232
-#define __NR_fadvise64		233
-#define __NR_exit_group		234
-#define __NR_lookup_dcookie	235
-#define __NR_epoll_create	236
-#define __NR_epoll_ctl		237
-#define __NR_epoll_wait		238
-#define __NR_remap_file_pages	239
-#define __NR_timer_create	240
-#define __NR_timer_settime	241
-#define __NR_timer_gettime	242
-#define __NR_timer_getoverrun	243
-#define __NR_timer_delete	244
-#define __NR_clock_settime	245
-#define __NR_clock_gettime	246
-#define __NR_clock_getres	247
-#define __NR_clock_nanosleep	248
-#define __NR_swapcontext	249
-#define __NR_tgkill		250
-#define __NR_utimes		251
-#define __NR_statfs64		252
-#define __NR_fstatfs64		253
-#ifndef __powerpc64__
-#define __NR_fadvise64_64	254
-#endif
-#define __NR_rtas		255
-#define __NR_sys_debug_setcontext 256
-/* Number 257 is reserved for vserver */
-#define __NR_migrate_pages	258
-#define __NR_mbind		259
-#define __NR_get_mempolicy	260
-#define __NR_set_mempolicy	261
-#define __NR_mq_open		262
-#define __NR_mq_unlink		263
-#define __NR_mq_timedsend	264
-#define __NR_mq_timedreceive	265
-#define __NR_mq_notify		266
-#define __NR_mq_getsetattr	267
-#define __NR_kexec_load		268
-#define __NR_add_key		269
-#define __NR_request_key	270
-#define __NR_keyctl		271
-#define __NR_waitid		272
-#define __NR_ioprio_set		273
-#define __NR_ioprio_get		274
-#define __NR_inotify_init	275
-#define __NR_inotify_add_watch	276
-#define __NR_inotify_rm_watch	277
-#define __NR_spu_run		278
-#define __NR_spu_create		279
-#define __NR_pselect6		280
-#define __NR_ppoll		281
-#define __NR_unshare		282
-#define __NR_splice		283
-#define __NR_tee		284
-#define __NR_vmsplice		285
-#define __NR_openat		286
-#define __NR_mkdirat		287
-#define __NR_mknodat		288
-#define __NR_fchownat		289
-#define __NR_futimesat		290
-#ifdef __powerpc64__
-#define __NR_newfstatat		291
-#else
-#define __NR_fstatat64		291
-#endif
-#define __NR_unlinkat		292
-#define __NR_renameat		293
-#define __NR_linkat		294
-#define __NR_symlinkat		295
-#define __NR_readlinkat		296
-#define __NR_fchmodat		297
-#define __NR_faccessat		298
-#define __NR_get_robust_list	299
-#define __NR_set_robust_list	300
-#define __NR_move_pages		301
-#define __NR_getcpu		302
-#define __NR_epoll_pwait	303
-#define __NR_utimensat		304
-#define __NR_signalfd		305
-#define __NR_timerfd_create	306
-#define __NR_eventfd		307
-#define __NR_sync_file_range2	308
-#define __NR_fallocate		309
-#define __NR_subpage_prot	310
-#define __NR_timerfd_settime	311
-#define __NR_timerfd_gettime	312
-#define __NR_signalfd4		313
-#define __NR_eventfd2		314
-#define __NR_epoll_create1	315
-#define __NR_dup3		316
-#define __NR_pipe2		317
-#define __NR_inotify_init1	318
-#define __NR_perf_event_open	319
-#define __NR_preadv		320
-#define __NR_pwritev		321
-#define __NR_rt_tgsigqueueinfo	322
-#define __NR_fanotify_init	323
-#define __NR_fanotify_mark	324
-#define __NR_prlimit64		325
-#define __NR_socket		326
-#define __NR_bind		327
-#define __NR_connect		328
-#define __NR_listen		329
-#define __NR_accept		330
-#define __NR_getsockname	331
-#define __NR_getpeername	332
-#define __NR_socketpair		333
-#define __NR_send		334
-#define __NR_sendto		335
-#define __NR_recv		336
-#define __NR_recvfrom		337
-#define __NR_shutdown		338
-#define __NR_setsockopt		339
-#define __NR_getsockopt		340
-#define __NR_sendmsg		341
-#define __NR_recvmsg		342
-#define __NR_recvmmsg		343
-#define __NR_accept4		344
-#define __NR_name_to_handle_at	345
-#define __NR_open_by_handle_at	346
-#define __NR_clock_adjtime	347
-#define __NR_syncfs		348
-#define __NR_sendmmsg		349
-#define __NR_setns		350
-#define __NR_process_vm_readv	351
-#define __NR_process_vm_writev	352
-
-#ifdef __KERNEL__
-
-#define __NR_syscalls		353
-
-#define __NR__exit __NR_exit
-#define NR_syscalls	__NR_syscalls
-
-#ifndef __ASSEMBLY__
-
-#include <linux/types.h>
-#include <linux/compiler.h>
-#include <linux/linkage.h>
-
-#define __ARCH_WANT_IPC_PARSE_VERSION
-#define __ARCH_WANT_OLD_READDIR
-#define __ARCH_WANT_STAT64
-#define __ARCH_WANT_SYS_ALARM
-#define __ARCH_WANT_SYS_GETHOSTNAME
-#define __ARCH_WANT_SYS_IPC
-#define __ARCH_WANT_SYS_PAUSE
-#define __ARCH_WANT_SYS_SGETMASK
-#define __ARCH_WANT_SYS_SIGNAL
-#define __ARCH_WANT_SYS_TIME
-#define __ARCH_WANT_SYS_UTIME
-#define __ARCH_WANT_SYS_WAITPID
-#define __ARCH_WANT_SYS_SOCKETCALL
-#define __ARCH_WANT_SYS_FADVISE64
-#define __ARCH_WANT_SYS_GETPGRP
-#define __ARCH_WANT_SYS_LLSEEK
-#define __ARCH_WANT_SYS_NICE
-#define __ARCH_WANT_SYS_OLD_GETRLIMIT
-#define __ARCH_WANT_SYS_OLD_UNAME
-#define __ARCH_WANT_SYS_OLDUMOUNT
-#define __ARCH_WANT_SYS_SIGPENDING
-#define __ARCH_WANT_SYS_SIGPROCMASK
-#define __ARCH_WANT_SYS_RT_SIGACTION
-#define __ARCH_WANT_SYS_RT_SIGSUSPEND
-#ifdef CONFIG_PPC32
-#define __ARCH_WANT_OLD_STAT
-#endif
-#ifdef CONFIG_PPC64
-#define __ARCH_WANT_COMPAT_SYS_TIME
-#define __ARCH_WANT_COMPAT_SYS_RT_SIGSUSPEND
-#define __ARCH_WANT_SYS_NEWFSTATAT
-#endif
-
-/*
- * "Conditional" syscalls
- */
-#define cond_syscall(x) \
-	asmlinkage long x (void) __attribute__((weak,alias("sys_ni_syscall")))
-
-#endif		/* __ASSEMBLY__ */
-#endif		/* __KERNEL__ */
-
-#endif /* _ASM_POWERPC_UNISTD_H_ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/user.h b/ANDROID_3.4.5/arch/powerpc/include/asm/user.h
deleted file mode 100644
index 3fd4545d..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/user.h
+++ /dev/null
@@ -1,51 +0,0 @@
-#ifndef _ASM_POWERPC_USER_H
-#define _ASM_POWERPC_USER_H
-
-#include <asm/ptrace.h>
-#include <asm/page.h>
-
-/*
- * Adapted from <asm-alpha/user.h>
- *
- * Core file format: The core file is written in such a way that gdb
- * can understand it and provide useful information to the user (under
- * linux we use the `trad-core' bfd, NOT the osf-core).  The file contents
- * are as follows:
- *
- *  upage: 1 page consisting of a user struct that tells gdb
- *	what is present in the file.  Directly after this is a
- *	copy of the task_struct, which is currently not used by gdb,
- *	but it may come in handy at some point.  All of the registers
- *	are stored as part of the upage.  The upage should always be
- *	only one page long.
- *  data: The data segment follows next.  We use current->end_text to
- *	current->brk to pick up all of the user variables, plus any memory
- *	that may have been sbrk'ed.  No attempt is made to determine if a
- *	page is demand-zero or if a page is totally unused, we just cover
- *	the entire range.  All of the addresses are rounded in such a way
- *	that an integral number of pages is written.
- *  stack: We need the stack information in order to get a meaningful
- *	backtrace.  We need to write the data from usp to
- *	current->start_stack, so we round each of these in order to be able
- *	to write an integer number of pages.
- */
-struct user {
-	struct pt_regs	regs;			/* entire machine state */
-	size_t		u_tsize;		/* text size (pages) */
-	size_t		u_dsize;		/* data size (pages) */
-	size_t		u_ssize;		/* stack size (pages) */
-	unsigned long	start_code;		/* text starting address */
-	unsigned long	start_data;		/* data starting address */
-	unsigned long	start_stack;		/* stack starting address */
-	long int	signal;			/* signal causing core dump */
-	unsigned long	u_ar0;			/* help gdb find registers */
-	unsigned long	magic;			/* identifies a core file */
-	char		u_comm[32];		/* user command name */
-};
-
-#define NBPG			PAGE_SIZE
-#define UPAGES			1
-#define HOST_TEXT_START_ADDR	(u.start_code)
-#define HOST_DATA_START_ADDR	(u.start_data)
-#define HOST_STACK_END_ADDR	(u.start_stack + u.u_ssize * NBPG)
-#endif	/* _ASM_POWERPC_USER_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/vdso.h b/ANDROID_3.4.5/arch/powerpc/include/asm/vdso.h
deleted file mode 100644
index dc0419b6..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/vdso.h
+++ /dev/null
@@ -1,77 +0,0 @@
-#ifndef __PPC64_VDSO_H__
-#define __PPC64_VDSO_H__
-
-#ifdef __KERNEL__
-
-/* Default link addresses for the vDSOs */
-#define VDSO32_LBASE	0x100000
-#define VDSO64_LBASE	0x100000
-
-/* Default map addresses for 32bit vDSO */
-#define VDSO32_MBASE	VDSO32_LBASE
-
-#define VDSO_VERSION_STRING	LINUX_2.6.15
-
-/* Define if 64 bits VDSO has procedure descriptors */
-#undef VDS64_HAS_DESCRIPTORS
-
-#ifndef __ASSEMBLY__
-
-/* Offsets relative to thread->vdso_base */
-extern unsigned long vdso64_rt_sigtramp;
-extern unsigned long vdso32_sigtramp;
-extern unsigned long vdso32_rt_sigtramp;
-
-#else /* __ASSEMBLY__ */
-
-#ifdef __VDSO64__
-#ifdef VDS64_HAS_DESCRIPTORS
-#define V_FUNCTION_BEGIN(name)		\
-	.globl name;			\
-        .section ".opd","a";		\
-        .align 3;			\
-	name:				\
-	.quad .name,.TOC.@tocbase,0;	\
-	.previous;			\
-	.globl .name;			\
-	.type .name,@function; 		\
-	.name:				\
-
-#define V_FUNCTION_END(name)		\
-	.size .name,.-.name;
-
-#define V_LOCAL_FUNC(name) (.name)
-
-#else /* VDS64_HAS_DESCRIPTORS */
-
-#define V_FUNCTION_BEGIN(name)		\
-	.globl name;			\
-	name:				\
-
-#define V_FUNCTION_END(name)		\
-	.size name,.-name;
-
-#define V_LOCAL_FUNC(name) (name)
-
-#endif /* VDS64_HAS_DESCRIPTORS */
-#endif /* __VDSO64__ */
-
-#ifdef __VDSO32__
-
-#define V_FUNCTION_BEGIN(name)		\
-	.globl name;			\
-	.type name,@function; 		\
-	name:				\
-
-#define V_FUNCTION_END(name)		\
-	.size name,.-name;
-
-#define V_LOCAL_FUNC(name) (name)
-
-#endif /* __VDSO32__ */
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* __KERNEL__ */
-
-#endif /* __PPC64_VDSO_H__ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/vdso_datapage.h b/ANDROID_3.4.5/arch/powerpc/include/asm/vdso_datapage.h
deleted file mode 100644
index b73a8199..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/vdso_datapage.h
+++ /dev/null
@@ -1,124 +0,0 @@
-#ifndef _VDSO_DATAPAGE_H
-#define _VDSO_DATAPAGE_H
-#ifdef __KERNEL__
-
-/*
- * Copyright (C) 2002 Peter Bergner <bergner@vnet.ibm.com>, IBM
- * Copyright (C) 2005 Benjamin Herrenschmidy <benh@kernel.crashing.org>,
- * 		      IBM Corp.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-
-/*
- * Note about this structure:
- *
- * This structure was historically called systemcfg and exposed to
- * userland via /proc/ppc64/systemcfg. Unfortunately, this became an
- * ABI issue as some proprietary software started relying on being able
- * to mmap() it, thus we have to keep the base layout at least for a
- * few kernel versions.
- *
- * However, since ppc32 doesn't suffer from this backward handicap,
- * a simpler version of the data structure is used there with only the
- * fields actually used by the vDSO.
- *
- */
-
-/*
- * If the major version changes we are incompatible.
- * Minor version changes are a hint.
- */
-#define SYSTEMCFG_MAJOR 1
-#define SYSTEMCFG_MINOR 1
-
-#ifndef __ASSEMBLY__
-
-#include <linux/unistd.h>
-#include <linux/time.h>
-
-#define SYSCALL_MAP_SIZE      ((__NR_syscalls + 31) / 32)
-
-/*
- * So here is the ppc64 backward compatible version
- */
-
-#ifdef CONFIG_PPC64
-
-struct vdso_data {
-	__u8  eye_catcher[16];		/* Eyecatcher: SYSTEMCFG:PPC64	0x00 */
-	struct {			/* Systemcfg version numbers	     */
-		__u32 major;		/* Major number			0x10 */
-		__u32 minor;		/* Minor number			0x14 */
-	} version;
-
-	/* Note about the platform flags: it now only contains the lpar
-	 * bit. The actual platform number is dead and buried
-	 */
-	__u32 platform;			/* Platform flags		0x18 */
-	__u32 processor;		/* Processor type		0x1C */
-	__u64 processorCount;		/* # of physical processors	0x20 */
-	__u64 physicalMemorySize;	/* Size of real memory(B)	0x28 */
-	__u64 tb_orig_stamp;		/* Timebase at boot		0x30 */
-	__u64 tb_ticks_per_sec;		/* Timebase tics / sec		0x38 */
-	__u64 tb_to_xs;			/* Inverse of TB to 2^20	0x40 */
-	__u64 stamp_xsec;		/*				0x48 */
-	__u64 tb_update_count;		/* Timebase atomicity ctr	0x50 */
-	__u32 tz_minuteswest;		/* Minutes west of Greenwich	0x58 */
-	__u32 tz_dsttime;		/* Type of dst correction	0x5C */
-	__u32 dcache_size;		/* L1 d-cache size		0x60 */
-	__u32 dcache_line_size;		/* L1 d-cache line size		0x64 */
-	__u32 icache_size;		/* L1 i-cache size		0x68 */
-	__u32 icache_line_size;		/* L1 i-cache line size		0x6C */
-
-	/* those additional ones don't have to be located anywhere
-	 * special as they were not part of the original systemcfg
-	 */
-	__u32 dcache_block_size;		/* L1 d-cache block size     */
-	__u32 icache_block_size;		/* L1 i-cache block size     */
-	__u32 dcache_log_block_size;		/* L1 d-cache log block size */
-	__u32 icache_log_block_size;		/* L1 i-cache log block size */
-	__s32 wtom_clock_sec;			/* Wall to monotonic clock */
-	__s32 wtom_clock_nsec;
-	struct timespec stamp_xtime;	/* xtime as at tb_orig_stamp */
-	__u32 stamp_sec_fraction;	/* fractional seconds of stamp_xtime */
-   	__u32 syscall_map_64[SYSCALL_MAP_SIZE]; /* map of syscalls  */
-   	__u32 syscall_map_32[SYSCALL_MAP_SIZE]; /* map of syscalls */
-};
-
-#else /* CONFIG_PPC64 */
-
-/*
- * And here is the simpler 32 bits version
- */
-struct vdso_data {
-	__u64 tb_orig_stamp;		/* Timebase at boot		0x30 */
-	__u64 tb_ticks_per_sec;		/* Timebase tics / sec		0x38 */
-	__u64 tb_to_xs;			/* Inverse of TB to 2^20	0x40 */
-	__u64 stamp_xsec;		/*				0x48 */
-	__u32 tb_update_count;		/* Timebase atomicity ctr	0x50 */
-	__u32 tz_minuteswest;		/* Minutes west of Greenwich	0x58 */
-	__u32 tz_dsttime;		/* Type of dst correction	0x5C */
-	__s32 wtom_clock_sec;			/* Wall to monotonic clock */
-	__s32 wtom_clock_nsec;
-	struct timespec stamp_xtime;	/* xtime as at tb_orig_stamp */
-	__u32 stamp_sec_fraction;	/* fractional seconds of stamp_xtime */
-   	__u32 syscall_map_32[SYSCALL_MAP_SIZE]; /* map of syscalls */
-	__u32 dcache_block_size;	/* L1 d-cache block size     */
-	__u32 icache_block_size;	/* L1 i-cache block size     */
-	__u32 dcache_log_block_size;	/* L1 d-cache log block size */
-	__u32 icache_log_block_size;	/* L1 i-cache log block size */
-};
-
-#endif /* CONFIG_PPC64 */
-
-extern struct vdso_data *vdso_data;
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* __KERNEL__ */
-#endif /* _SYSTEMCFG_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/vga.h b/ANDROID_3.4.5/arch/powerpc/include/asm/vga.h
deleted file mode 100644
index a2eac409..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/vga.h
+++ /dev/null
@@ -1,53 +0,0 @@
-#ifndef _ASM_POWERPC_VGA_H_
-#define _ASM_POWERPC_VGA_H_
-
-#ifdef __KERNEL__
-
-/*
- *	Access to VGA videoram
- *
- *	(c) 1998 Martin Mares <mj@ucw.cz>
- */
-
-
-#include <asm/io.h>
-
-
-#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_MDA_CONSOLE)
-
-#define VT_BUF_HAVE_RW
-/*
- *  These are only needed for supporting VGA or MDA text mode, which use little
- *  endian byte ordering.
- *  In other cases, we can optimize by using native byte ordering and
- *  <linux/vt_buffer.h> has already done the right job for us.
- */
-
-static inline void scr_writew(u16 val, volatile u16 *addr)
-{
-    st_le16(addr, val);
-}
-
-static inline u16 scr_readw(volatile const u16 *addr)
-{
-    return ld_le16(addr);
-}
-
-#define VT_BUF_HAVE_MEMCPYW
-#define scr_memcpyw	memcpy
-
-#endif /* !CONFIG_VGA_CONSOLE && !CONFIG_MDA_CONSOLE */
-
-extern unsigned long vgacon_remap_base;
-
-#ifdef __powerpc64__
-#define VGA_MAP_MEM(x,s) ((unsigned long) ioremap((x), s))
-#else
-#define VGA_MAP_MEM(x,s) (x + vgacon_remap_base)
-#endif
-
-#define vga_readb(x) (*(x))
-#define vga_writeb(x,y) (*(y) = (x))
-
-#endif	/* __KERNEL__ */
-#endif	/* _ASM_POWERPC_VGA_H_ */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/vio.h b/ANDROID_3.4.5/arch/powerpc/include/asm/vio.h
deleted file mode 100644
index 6bfd5ffe..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/vio.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * IBM PowerPC Virtual I/O Infrastructure Support.
- *
- * Copyright (c) 2003 IBM Corp.
- *  Dave Engebretsen engebret@us.ibm.com
- *  Santiago Leon santil@us.ibm.com
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_POWERPC_VIO_H
-#define _ASM_POWERPC_VIO_H
-#ifdef __KERNEL__
-
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/device.h>
-#include <linux/dma-mapping.h>
-#include <linux/mod_devicetable.h>
-
-#include <asm/hvcall.h>
-#include <asm/scatterlist.h>
-
-/*
- * Architecture-specific constants for drivers to
- * extract attributes of the device using vio_get_attribute()
- */
-#define VETH_MAC_ADDR "local-mac-address"
-#define VETH_MCAST_FILTER_SIZE "ibm,mac-address-filters"
-
-/* End architecture-specific constants */
-
-#define h_vio_signal(ua, mode) \
-  plpar_hcall_norets(H_VIO_SIGNAL, ua, mode)
-
-#define VIO_IRQ_DISABLE		0UL
-#define VIO_IRQ_ENABLE		1UL
-
-/*
- * VIO CMO minimum entitlement for all devices and spare entitlement
- */
-#define VIO_CMO_MIN_ENT 1562624
-
-struct iommu_table;
-
-/**
- * vio_dev - This structure is used to describe virtual I/O devices.
- *
- * @desired: set from return of driver's get_desired_dma() function
- * @entitled: bytes of IO data that has been reserved for this device.
- * @allocated: bytes of IO data currently in use by the device.
- * @allocs_failed: number of DMA failures due to insufficient entitlement.
- */
-struct vio_dev {
-	const char *name;
-	const char *type;
-	uint32_t unit_address;
-	unsigned int irq;
-	struct {
-		size_t desired;
-		size_t entitled;
-		size_t allocated;
-		atomic_t allocs_failed;
-	} cmo;
-	struct device dev;
-};
-
-struct vio_driver {
-	const char *name;
-	const struct vio_device_id *id_table;
-	int (*probe)(struct vio_dev *dev, const struct vio_device_id *id);
-	int (*remove)(struct vio_dev *dev);
-	/* A driver must have a get_desired_dma() function to
-	 * be loaded in a CMO environment if it uses DMA.
-	 */
-	unsigned long (*get_desired_dma)(struct vio_dev *dev);
-	const struct dev_pm_ops *pm;
-	struct device_driver driver;
-};
-
-extern int __vio_register_driver(struct vio_driver *drv, struct module *owner,
-				 const char *mod_name);
-/*
- * vio_register_driver must be a macro so that KBUILD_MODNAME can be expanded
- */
-#define vio_register_driver(driver)		\
-	__vio_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
-extern void vio_unregister_driver(struct vio_driver *drv);
-
-extern int vio_cmo_entitlement_update(size_t);
-extern void vio_cmo_set_dev_desired(struct vio_dev *viodev, size_t desired);
-
-extern void __devinit vio_unregister_device(struct vio_dev *dev);
-
-struct device_node;
-
-extern struct vio_dev *vio_register_device_node(
-		struct device_node *node_vdev);
-extern const void *vio_get_attribute(struct vio_dev *vdev, char *which,
-		int *length);
-#ifdef CONFIG_PPC_PSERIES
-extern struct vio_dev *vio_find_node(struct device_node *vnode);
-extern int vio_enable_interrupts(struct vio_dev *dev);
-extern int vio_disable_interrupts(struct vio_dev *dev);
-#else
-static inline int vio_enable_interrupts(struct vio_dev *dev)
-{
-	return 0;
-}
-#endif
-
-static inline struct vio_driver *to_vio_driver(struct device_driver *drv)
-{
-	return container_of(drv, struct vio_driver, driver);
-}
-
-static inline struct vio_dev *to_vio_dev(struct device *dev)
-{
-	return container_of(dev, struct vio_dev, dev);
-}
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_VIO_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/wsp.h b/ANDROID_3.4.5/arch/powerpc/include/asm/wsp.h
deleted file mode 100644
index c7dc8308..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/wsp.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- *  Copyright 2011 Michael Ellerman, IBM Corp.
- *
- *  This program is free software; you can redistribute it and/or
- *  modify it under the terms of the GNU General Public License
- *  as published by the Free Software Foundation; either version
- *  2 of the License, or (at your option) any later version.
- */
-#ifndef __ASM_POWERPC_WSP_H
-#define __ASM_POWERPC_WSP_H
-
-extern int wsp_get_chip_id(struct device_node *dn);
-
-#endif /* __ASM_POWERPC_WSP_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/xics.h b/ANDROID_3.4.5/arch/powerpc/include/asm/xics.h
deleted file mode 100644
index 4ae9a09c..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/xics.h
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
- * Common definitions accross all variants of ICP and ICS interrupt
- * controllers.
- */
-
-#ifndef _XICS_H
-#define _XICS_H
-
-#include <linux/interrupt.h>
-
-#define XICS_IPI		2
-#define XICS_IRQ_SPURIOUS	0
-
-/* Want a priority other than 0.  Various HW issues require this. */
-#define	DEFAULT_PRIORITY	5
-
-/*
- * Mark IPIs as higher priority so we can take them inside interrupts
- * FIXME: still true now?
- */
-#define IPI_PRIORITY		4
-
-/* The least favored priority */
-#define LOWEST_PRIORITY		0xFF
-
-/* The number of priorities defined above */
-#define MAX_NUM_PRIORITIES	3
-
-/* Native ICP */
-#ifdef CONFIG_PPC_ICP_NATIVE
-extern int icp_native_init(void);
-#else
-static inline int icp_native_init(void) { return -ENODEV; }
-#endif
-
-/* PAPR ICP */
-#ifdef CONFIG_PPC_ICP_HV
-extern int icp_hv_init(void);
-#else
-static inline int icp_hv_init(void) { return -ENODEV; }
-#endif
-
-/* ICP ops */
-struct icp_ops {
-	unsigned int (*get_irq)(void);
-	void (*eoi)(struct irq_data *d);
-	void (*set_priority)(unsigned char prio);
-	void (*teardown_cpu)(void);
-	void (*flush_ipi)(void);
-#ifdef CONFIG_SMP
-	void (*cause_ipi)(int cpu, unsigned long data);
-	irq_handler_t ipi_action;
-#endif
-};
-
-extern const struct icp_ops *icp_ops;
-
-/* Native ICS */
-extern int ics_native_init(void);
-
-/* RTAS ICS */
-#ifdef CONFIG_PPC_ICS_RTAS
-extern int ics_rtas_init(void);
-#else
-static inline int ics_rtas_init(void) { return -ENODEV; }
-#endif
-
-/* HAL ICS */
-#ifdef CONFIG_PPC_POWERNV
-extern int ics_opal_init(void);
-#else
-static inline int ics_opal_init(void) { return -ENODEV; }
-#endif
-
-/* ICS instance, hooked up to chip_data of an irq */
-struct ics {
-	struct list_head link;
-	int (*map)(struct ics *ics, unsigned int virq);
-	void (*mask_unknown)(struct ics *ics, unsigned long vec);
-	long (*get_server)(struct ics *ics, unsigned long vec);
-	int (*host_match)(struct ics *ics, struct device_node *node);
-	char data[];
-};
-
-/* Commons */
-extern unsigned int xics_default_server;
-extern unsigned int xics_default_distrib_server;
-extern unsigned int xics_interrupt_server_size;
-extern struct irq_domain *xics_host;
-
-struct xics_cppr {
-	unsigned char stack[MAX_NUM_PRIORITIES];
-	int index;
-};
-
-DECLARE_PER_CPU(struct xics_cppr, xics_cppr);
-
-static inline void xics_push_cppr(unsigned int vec)
-{
-	struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
-
-	if (WARN_ON(os_cppr->index >= MAX_NUM_PRIORITIES - 1))
-		return;
-
-	if (vec == XICS_IPI)
-		os_cppr->stack[++os_cppr->index] = IPI_PRIORITY;
-	else
-		os_cppr->stack[++os_cppr->index] = DEFAULT_PRIORITY;
-}
-
-static inline unsigned char xics_pop_cppr(void)
-{
-	struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
-
-	if (WARN_ON(os_cppr->index < 1))
-		return LOWEST_PRIORITY;
-
-	return os_cppr->stack[--os_cppr->index];
-}
-
-static inline void xics_set_base_cppr(unsigned char cppr)
-{
-	struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
-
-	/* we only really want to set the priority when there's
-	 * just one cppr value on the stack
-	 */
-	WARN_ON(os_cppr->index != 0);
-
-	os_cppr->stack[0] = cppr;
-}
-
-static inline unsigned char xics_cppr_top(void)
-{
-	struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
-	
-	return os_cppr->stack[os_cppr->index];
-}
-
-DECLARE_PER_CPU_SHARED_ALIGNED(unsigned long, xics_ipi_message);
-
-extern void xics_init(void);
-extern void xics_setup_cpu(void);
-extern void xics_update_irq_servers(void);
-extern void xics_set_cpu_giq(unsigned int gserver, unsigned int join);
-extern void xics_mask_unknown_vec(unsigned int vec);
-extern irqreturn_t xics_ipi_dispatch(int cpu);
-extern int xics_smp_probe(void);
-extern void xics_register_ics(struct ics *ics);
-extern void xics_teardown_cpu(void);
-extern void xics_kexec_teardown_cpu(int secondary);
-extern void xics_migrate_irqs_away(void);
-#ifdef CONFIG_SMP
-extern int xics_get_irq_server(unsigned int virq, const struct cpumask *cpumask,
-			       unsigned int strict_check);
-#else
-#define xics_get_irq_server(virq, cpumask, strict_check) (xics_default_server)
-#endif
-
-
-#endif /* _XICS_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/xilinx_intc.h b/ANDROID_3.4.5/arch/powerpc/include/asm/xilinx_intc.h
deleted file mode 100644
index 343612f8..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/xilinx_intc.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * Xilinx intc external definitions
- *
- * Copyright 2007 Secret Lab Technologies Ltd.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-#ifndef _ASM_POWERPC_XILINX_INTC_H
-#define _ASM_POWERPC_XILINX_INTC_H
-
-#ifdef __KERNEL__
-
-extern void __init xilinx_intc_init_tree(void);
-extern unsigned int xilinx_intc_get_irq(void);
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_XILINX_INTC_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/xilinx_pci.h b/ANDROID_3.4.5/arch/powerpc/include/asm/xilinx_pci.h
deleted file mode 100644
index 7a8275ca..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/xilinx_pci.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * Xilinx pci external definitions
- *
- * Copyright 2009 Roderick Colenbrander
- * Copyright 2009 Secret Lab Technologies Ltd.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#ifndef INCLUDE_XILINX_PCI
-#define INCLUDE_XILINX_PCI
-
-#ifdef CONFIG_XILINX_PCI
-extern void __init xilinx_pci_init(void);
-#else
-static inline void __init xilinx_pci_init(void) { return; }
-#endif
-
-#endif /* INCLUDE_XILINX_PCI */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/xmon.h b/ANDROID_3.4.5/arch/powerpc/include/asm/xmon.h
deleted file mode 100644
index 5eb8e599..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/xmon.h
+++ /dev/null
@@ -1,33 +0,0 @@
-#ifndef __ASM_POWERPC_XMON_H
-#define __ASM_POWERPC_XMON_H
-
-/*
- * Copyrignt (C) 2006 IBM Corp
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifdef __KERNEL__
-
-#include <linux/irqreturn.h>
-
-#ifdef CONFIG_XMON
-extern void xmon_setup(void);
-extern void xmon_register_spus(struct list_head *list);
-struct pt_regs;
-extern int xmon(struct pt_regs *excp);
-extern irqreturn_t xmon_irq(int, void *);
-#else
-static inline void xmon_setup(void) { };
-static inline void xmon_register_spus(struct list_head *list) { };
-#endif
-
-#if defined(CONFIG_XMON) && defined(CONFIG_SMP)
-extern int cpus_are_in_xmon(void);
-#endif
-
-#endif /* __KERNEL __ */
-#endif /* __ASM_POWERPC_XMON_H */
diff --git a/ANDROID_3.4.5/arch/powerpc/include/asm/xor.h b/ANDROID_3.4.5/arch/powerpc/include/asm/xor.h
deleted file mode 100644
index c82eb12a..00000000
--- a/ANDROID_3.4.5/arch/powerpc/include/asm/xor.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/xor.h>