Moved, renamed, and deleted files

The original directory structure was scattered and unorganized.
Changes are basically to make it look like kernel structure.

65 files changed, 0 insertions, 15952 deletions

diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/Kconfig b/ANDROID_3.4.5/arch/arm/mach-wmt/Kconfig
deleted file mode 100755
index 5cf53f6e..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/Kconfig
+++ /dev/null
@@ -1,56 +0,0 @@
-if ARCH_WMT
-
-menu "WonderMedia Technology Implementations"
-
-config WMT_EVB
-        bool "WonderMedia Technology Evaluation Board"
-        depends on ARCH_WMT
-        default y
-	---help---
-	  Say Y here if you want to config the WonderMedia Technology specific parameters.
-
-choice
-	prompt "Select WonderMedia Technology evaluation board type"
-	depends on WMT_EVB
-	default WM0001
-	---help---
-	  Choose the type of WonderMedia Technology evaluation board type.
-	  There are four types of WonderMedia Technology EVB, depend on the mounted components.
-
-config WM0001
-	bool "WM0001"
-	---help---
-	  Say Y here if you intend to build kernel on VT9043A1.
-
-endchoice
-
-config WMT_USE_BOOTLOADER_ATAG
-	bool "Bootloader kernel parameter support"
-	depends on WMT_EVB
-	---help---
-	Say Y here if you want to use kernel parameters passed from the arm bootloader.
-
-config WMT_FIXUP_ATAG
-	bool "Force to fixup kernel parameter"
-	depends on WMT_EVB && WMT_USE_BOOTLOADER_ATAG
-	---help---
-	  Say Y here if you want to fixup the WonderMedia Technology kernel boot parameters.
-	  It is a temp solution if ATAG passing have problem or you don't 
-	  know how exactly setup kernel parameters.
-
-config OTZONE_ASYNC_NOTIFY_SUPPORT
-	bool "TrustZone asynchronous notify support"
-	depends on WMT_EVB
-	---help---
-	Say Y here if you want to use TrustZone asynchronous notify support.
-
-config OTZONE_AMP_SUPPORT
-	bool "TrustZone AMP support"
-	depends on WMT_EVB
-	---help---
-	Say Y here if you want to use TrustZone AMP support.	
-	  
-endmenu
-
-endif
-
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/Makefile b/ANDROID_3.4.5/arch/arm/mach-wmt/Makefile
deleted file mode 100755
index 04bd8894..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/Makefile
+++ /dev/null
@@ -1,21 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-
-# Common support
-obj-y   := generic.o irq.o board.o wmt_clk.o dma.o wmt_time.o wmt_reset.o wmt_smc.o gpio.o \
-	   gpio_customize_ease.o \
-	   wmt_misc.o \
-	   pwm.o
-
-plus_sec := $(call as-instr,.arch_extension sec,+sec)
-AFLAGS_wmt-smc.o                       :=-Wa,-march=armv7-a$(plus_sec)
-obj-$(CONFIG_PM)		+= pm.o pm_cpai.o sleep.o
-obj-y += gpio_ctrl.o
-
-# CPUFreq support
-obj-$(CONFIG_ARM_WMT_CPUFREQ)	+= wmt_cpufreq.o
-obj-$(CONFIG_CPU_IDLE)			+= wmt_cpuidle.o
-obj-$(CONFIG_SMP)		+= platsmp.o headsmp.o
-obj-$(CONFIG_HOTPLUG_CPU)	+= hotplug.o
-obj-$(CONFIG_COMMON_CLK)	+= wmt_clock.o
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/Makefile.boot b/ANDROID_3.4.5/arch/arm/mach-wmt/Makefile.boot
deleted file mode 100755
index e971f772..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/Makefile.boot
+++ /dev/null
@@ -1,3 +0,0 @@
-   zreladdr-y	:= 0x00008000 
-params_phys-y	:= 0x00000100
-initrd_phys-y	:= 0x01000000
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/board.c b/ANDROID_3.4.5/arch/arm/mach-wmt/board.c
deleted file mode 100755
index 30b215b7..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/board.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/*++
-linux/arch/arm/mach-wmt/board.c
-
-Copyright (c) 2012  WonderMedia Technologies, Inc.
-
-This program is free software: you can redistribute it and/or modify it under the
-terms of the GNU General Public License as published by the Free Software Foundation,
-either version 2 of the License, or (at your option) any later version.
-
-This program is distributed in the hope that it will be useful, but WITHOUT
-ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-PARTICULAR PURPOSE.  See the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License along with
-this program.  If not, see <http://www.gnu.org/licenses/>.
-
-WonderMedia Technologies, Inc.
-10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
---*/
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/pm.h>
-#include <linux/cpufreq.h>
-#include <linux/ioport.h>
-#include <linux/tty.h>
-#include <linux/mm.h>
-#include <linux/errno.h>
-#include <linux/serial_core.h>
-#include <linux/delay.h>
-
-#include <mach/hardware.h>
-#include <asm/system.h>
-#include <asm/mach-types.h>
-#include <asm/irq.h>
-#include <asm/setup.h>
-#include <asm/page.h>
-#include <asm/pgtable.h>
-#include <asm/tlbflush.h>
-#include <asm/sizes.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/hardware/gic.h>
-
-#include "generic.h"
-
-static void __init
-wmt_fixup(struct tag *tags,
-	char **cmdline, struct meminfo *mi)
-{
-#ifdef CONFIG_WMT_FIXUP_ATAG
-
-	struct tag *t = tags;
-
-	/*FIXME, remove following while ATAG passing from bootloader is ok.*/
-	t->hdr.tag              = ATAG_CORE;
-	t->hdr.size             = tag_size(tag_core);
-	t->u.core.flags         = 0;
-	t->u.core.pagesize      = PAGE_SIZE;
-	t->u.core.rootdev       = (RAMDISK_MAJOR << 8) | 0;
-	t = tag_next(t);
-
-	t->hdr.tag              = ATAG_MEM;
-	t->hdr.size             = tag_size(tag_mem32);
-	t->u.mem.start          = 0x00000000;
-	t->u.mem.size           = 64 * 1024 * 1024;
-	t = tag_next(t);
-	/**/
-	/* ramdisk.size = decompressed ramdisk size in _kilo_ bytes.*/
-	/**/
-	t->hdr.tag              = ATAG_RAMDISK;
-	t->hdr.size             = tag_size(tag_ramdisk);
-	t->u.ramdisk.flags      = 1;
-	t->u.ramdisk.size       = 8 * 1024;
-	t->u.ramdisk.start      = 0;
-	t = tag_next(t);
-	/**/
-	/* initrd.size = size of compressed ramdisk image in bytes.*/
-	/**/
-	t->hdr.tag              = ATAG_INITRD2;
-	t->hdr.size             = tag_size(tag_initrd);
-	t->u.initrd.start       = 0x01000000;   /* physical*/
-	/*t->u.initrd.size        = 3 * 1024 * 1024;*/
-	t->u.initrd.size        = 8 * 1024 * 1024;      /* depend on the size of ramdisk.gz*/
-	t = tag_next(t);
-
-	t->hdr.tag = ATAG_NONE;
-	t->hdr.size = 0;
-#endif
-}
-
-/* map wmt physical io address to virtual address */
-static struct map_desc wmt_io_desc[] __initdata = {
-	{
-			.virtual    = 0xFE000000,
-			.length     = SZ_16M,
-			.pfn        = __phys_to_pfn(0xD8000000),
-			.type       = MT_DEVICE
-	}
-};
-
-static void __init wmt_map_io(void)
-{
-	iotable_init(wmt_io_desc, ARRAY_SIZE(wmt_io_desc));
-
-	wmt_register_uart(0, 0);	/* mount ttyS0 (or ttyVT0) to UART0*/
-	wmt_register_uart(1, 1);	/* mount ttyS1 to UART1*/
-#ifdef CONFIG_UART_2_3_ENABLE
-	wmt_register_uart(2, 2);	/* mount ttyS2 to UART2*/
-	wmt_register_uart(3, 3);	/* mount ttyS3 to UART3*/
-#endif
-}
-
-extern struct sys_timer wmt_timer;
-
-MACHINE_START(WMT, "WMT")
-#ifdef CONFIG_WMT_USE_BOOTLOADER_ATAG
-	.boot_params	= 0x00000100,
-#endif
-	.fixup        = &wmt_fixup,
-	.map_io       = &wmt_map_io,
-	.init_irq     = wmt_init_irq,
-	.handle_irq   = gic_handle_irq,
-	.timer        = &wmt_timer,
-MACHINE_END
-
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/dma.c b/ANDROID_3.4.5/arch/arm/mach-wmt/dma.c
deleted file mode 100755
index ad6db63d..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/dma.c
+++ /dev/null
@@ -1,1361 +0,0 @@
-/*++
-	arch/arm/mach-wmt/dma.c - DMA 5 driver
-
-	Copyright (c) 2013  WonderMedia Technologies, Inc.
-
-	This program is free software: you can redistribute it and/or modify it under the
-	terms of the GNU General Public License as published by the Free Software Foundation,
-	either version 2 of the License, or (at your option) any later version.
-
-	This program is distributed in the hope that it will be useful, but WITHOUT
-	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-	PARTICULAR PURPOSE.  See the GNU General Public License for more details.
-	You should have received a copy of the GNU General Public License along with
-	this program.  If not, see <http://www.gnu.org/licenses/>.
-
-	WonderMedia Technologies, Inc.
-	10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
---*/
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/sched.h>
-#include <linux/spinlock.h>
-#include <linux/errno.h>
-#include <linux/proc_fs.h>
-#include <linux/syscore_ops.h>
-
-#include <linux/pm.h>
-#include <linux/delay.h>
-
-#include <asm/system.h>
-#include <asm/irq.h>
-#include <mach/hardware.h>
-#include <asm/dma.h>
-#include <asm/io.h>
-#include <linux/dma-mapping.h>
-#include <mach/dma.h>
-
-#undef DMA4_ERRATA
-#undef DEBUG
-/*#define DEBUG*/
-
-#ifdef DEBUG
-#define DPRINTK(fmt, args...)   printk("%s: " fmt, __func__ , ## args)
-#else
-#define DPRINTK(x...)
-#endif
-
-#define MAX_DESCRIPT_SIZE SIZE_1KB
-
-int revise_descript( dmach_t ch, struct dma_device_cfg_s device_cfg, struct dma_mem_reg_group_s dma_mem_reg);
-
-extern unsigned int wmt_read_oscr(void); 
-
-/*-----------------------------------------------------------------------------*/
-/* DMA channel structure.*/
-/*-----------------------------------------------------------------------------*/
-struct dma_info_s {
-	dmach_t  channel_no ;       /* channel no*/
-	struct dma_regs_s *regs;           /* points to appropriate DMA registers*/
-	int irq;                    /* IRQ Index used by the channel*/
-	const char *device_id;      /* device name*/
-	void (*callback)(void *data);    /* to call when buffers are done*/
-	void *callback_data;        /* with private data ptr*/
-	enum dma_device_e device_no ;    /* device no*/
-	struct dma_device_cfg_s device_cfg ;  /* device cfg*/
-	int in_use;                 /* Does someone own the channel*/
-	int des0cnt;                 /*  descript 0 current index*/
-	int des1cnt;                 /*descript 1 current index*/
-	int max_des0cnt;      /*the largest descript 0 number*/
-	int max_des1cnt;      /*the largest descript 1 number*/
-	int residue_des0cnt ; /*residue descript 0 count need to be xfer*/
-	int residue_des1cnt ; /*residue descript 1 count need to be xfer*/
-	struct dma_descript_addr des_addr;
-	dma_addr_t des0_phy_addr ;
-	dma_addr_t des1_phy_addr ;
-	unsigned int accu_size; /*accumlate size between the dma interrupt*/
-	unsigned int descript_size; /*the max descript size*/
-
-} ;
-
-struct dma_int_s {
-	unsigned int request_chans ;
-	struct dma_regs_s *regs;
-
-};
-
-struct des_attribute {
-	unsigned int end_descript;
-	unsigned int interrupt_en;
-	unsigned int size;
-	unsigned int fmt;
-	dma_addr_t data_addr;
-	dma_addr_t branch_addr;
-};
-
-
-/*-----------------------------------------------------------------------------*/
-/*  variable*/
-/*-----------------------------------------------------------------------------*/
-static struct dma_int_s    dma_int ;
-
-static struct dma_info_s dma_chan[MAX_DMA_CHANNELS];
-
-static struct dma_mem_reg_s *dma_mem_regs;
-
-static dma_addr_t dma_mem_phy;
-
-/* static spinlock_t dma_list_lock = SPIN_LOCK_UNLOCKED;*/
-static DEFINE_SPINLOCK(dma_list_lock);
-
-static unsigned int dma_irq_no[] = {
-	IRQ_DMA_NONS,
-	IRQ_DMA_NONS,
-	IRQ_DMA_NONS,
-	IRQ_DMA_NONS,
-	IRQ_DMA_NONS,
-	IRQ_DMA_NONS,
-	IRQ_DMA_NONS,
-	IRQ_DMA_NONS,
-	IRQ_DMA_NONS,
-	IRQ_DMA_NONS,
-	IRQ_DMA_NONS,
-	IRQ_DMA_NONS,
-	IRQ_DMA_NONS,
-	IRQ_DMA_NONS,
-	IRQ_DMA_NONS,
-	IRQ_DMA_NONS,
-};
-
-struct dma_device_cfg_s dma_device_cfg_table[] = {
-	/*   DeviceReq        , DefaultCCR , Source_0, Destination_0	*/
-	{ SPI0_DMA_TX_REQ , 0x00000100 , 0, 0 , SIZE_4KB},  /*spi0*/
-	{ SPI0_DMA_RX_REQ , 0x00000100 , 0, 0 , SIZE_4KB},  /*spi1*/
-	{ SPI1_DMA_TX_REQ , 0x00000100 , 0, 0 , SIZE_4KB},
-	{ SPI1_DMA_RX_REQ , 0x00000100 , 0, 0 , SIZE_4KB},
-	{ PCM1_TX_DMA_REQ , 0x00000100, 0, 0 , SIZE_4KB},
-	{ PCM1_RX_DMA_REQ , 0x00000100, 0, 0 , SIZE_4KB},
-	/* start from 0, above 5, below 6 */
-	{ UART_0_TX_DMA_REQ , UART_TX_DMA_CFG, 0, UART0_TX_FIFO , SIZE_1B},  /*uart0*/
-	{ UART_0_RX_DMA_REQ , UART_RX_DMA_CFG, 0, UART0_RX_FIFO , SIZE_4KB},  /*uart0*/
-	{ UART_1_TX_DMA_REQ , UART_TX_DMA_CFG, 0, UART1_TX_FIFO , SIZE_1B},  /*uart1*/
-	{ UART_1_RX_DMA_REQ , UART_RX_DMA_CFG, 0, UART1_RX_FIFO , SIZE_4KB},  /*uart1*/
-	{ UART_2_TX_DMA_REQ , UART_TX_DMA_CFG, 0, UART2_TX_FIFO , SIZE_1B},  /*uart2*/
-	/*start from 0, above 10, below 11 */
-	{ UART_2_RX_DMA_REQ , UART_RX_DMA_CFG, 0, UART2_RX_FIFO , SIZE_4KB},  /*uart2*/
-	{ UART_3_TX_DMA_REQ , UART_TX_DMA_CFG, 0, UART3_TX_FIFO , SIZE_1B},  /*uart3*/
-	{ UART_3_RX_DMA_REQ , UART_RX_DMA_CFG, 0, UART3_RX_FIFO , SIZE_4KB},  /*uart3*/
-	{ PCM_TX_DMA_REQ, PCM_TX_DMA_CFG, 0, PCM_TX_FIFO, SIZE_4KB},
-	{ PCM_RX_DMA_REQ, PCM_RX_DMA_CFG, 0, PCM_RX_FIFO, SIZE_4KB},
-	/*start from 0, above 15, below 16 */
-	{ DEVICE_RESERVED , 0x00000100, 0, 0 , SIZE_4KB},
-	{ DEVICE_RESERVED , 0x00000100, 0, 0 , SIZE_4KB},
-	{ DEVICE_RESERVED , 0x00000100, 0, 0 , SIZE_4KB},
-	{ DEVICE_RESERVED , 0x00000100, 0, 0 , SIZE_4KB},
-	{ DEVICE_RESERVED , 0x00000100, 0, 0 , SIZE_4KB},
-	/*start from 0, above 20, below 21 */
-	{ AHB1_AUD_DMA_REQ_0 , I2S_RX_DMA_CFG, 0, I2S_RX_FIFO , SIZE_16KB},
-	{ AHB1_AUD_DMA_REQ_1 , I2S_TX_DMA_CFG, 0, I2S_TX_FIFO , SIZE_16KB},
-	{ AHB1_AUD_DMA_REQ_2 , I2S_RX_DMA_CFG, 0, SPDIF_RX_FIFO, SIZE_16KB},
-	{ AHB1_AUD_DMA_REQ_3 , 0x00000100, 0, 0 , SIZE_4KB},
-	{ AHB1_AUD_DMA_REQ_4 , 0x00000100, 0, 0 , SIZE_4KB},
-	{ AHB1_AUD_DMA_REQ_5 , 0x00000100, 0, 0 , SIZE_4KB},
-	{ AHB1_AUD_DMA_REQ_6 , 0x00000100, 0, 0 , SIZE_4KB},
-	{ AHB1_AUD_DMA_REQ_7 , 0x00000100, 0, 0 , SIZE_4KB},
-	{ DEVICE_RESERVED , 0x00000100, 0, 0 , SIZE_4KB},
-	{ DEVICE_RESERVED , 0x00000100, 0, 0 , SIZE_4KB},
-	/*start from 0, above 30, below 31 */
-	{ DEVICE_RESERVED , 0x00000100, 0, 0 , SIZE_4KB},
-	{ MEMORY_DMA_REQ , 0x2a800000, 0x0a200000	, 0x0a220000 , SIZE_4KB},
-	{ DEVICE_RESERVED , 0x00000100, 0, 0 , SIZE_4KB},
-};
-EXPORT_SYMBOL(dma_device_cfg_table);
-
-/*===========================================================================*/
-/*  dma_irq_handler*/
-/**/
-/*  return: 0*/
-/*===========================================================================*/
-static irqreturn_t
-dma_irq_handler(int irq, void *dev_id)
-{
-	int ch ;
-	unsigned int global_st ;
-	unsigned char channel_st ;
-	struct dma_info_s *dma = NULL ;
-	struct dma_mem_reg_group_s dma_mem_reg ;
-
-	global_st = dma_int.regs->DMA_ISR & 0xFFFF ;
-
-	for (ch = 0 ; ch < MAX_DMA_CHANNELS ; ++ch) {
-		if (global_st & 1 << ch) {
-                        channel_st = dma_int.regs->DMA_CCR_CH[ch] & DMA_EVT_ID_MASK;
-			break ;
-		}
-	}
-	DPRINTK("%s :dma ch = %d\n", __func__, ch);
-	
-
-	if (ch >= MAX_DMA_CHANNELS) {
-		printk(KERN_ERR "DMA : unknown DMA IRQ\n\r") ;
-		return IRQ_HANDLED ;
-	}
-	/*
-	 * ch active handling
-	 */
-	dma = &dma_chan[ch] ;
-	dma_int.regs->DMA_ISR = 1 << ch ;
-	/*
-	 * Handle channel DMA error
-	 */
-	if ((channel_st == DMA_EVT_NO_STATUS)) {
-		/*
-		 * DMA request finished with no error	
-		 * Vincent 2009/05/19
-		 */
-		dma_mem_reg = wmt_get_dma_pos_info(ch);
-		revise_descript(ch, dma->device_cfg, dma_mem_reg);
-	} else if ((channel_st != DMA_EVT_SUCCESS) && (channel_st != DMA_EVT_NO_STATUS)) {
-		/* 1. clear error/abort status*/
-		/* 2. re-program src/des/cnt reg 0 and 1*/
-		/* 3. write "1" to csr bit6 to reset the buffer pointer to 0*/
-		/* 4. re-enable dma channle*/
-		printk(KERN_ERR "ch=%d status=0x%.2x err\n\r",
-			ch, channel_st) ;
-		/*
-		 * dma->callback(dma->callback_data) ; 
-		 * if callback runs, audio driver think this descp is done
-		 * Vincent 2009/05/19
-		 */
-		wmt_resume_dma(ch);
-		/* free buffer and callback to handle error*/
-		return IRQ_HANDLED ;
-	}
-	/*
-	* Decrease the channel descript usage indicator.
-	*/
-	if (dma->residue_des0cnt > 0)
-		--dma->residue_des0cnt;
-	if (dma->callback)
-		dma->callback(dma->callback_data) ;
-
-	return IRQ_HANDLED;
-}
-
-int create_fmt0_descript(
-	dmach_t ch,
-	struct dma_device_cfg_s device_cfg,
-	struct des_attribute descript_attr)
-{
-	struct dma_info_s *dma ;
-	struct dma_des_fmt0 descript;
-	unsigned int ReqCnt = 0;
-	unsigned int des_offset;
-	descript.DataAddr = 0;
-	descript.ReqCnt = 0;
-	dma = &dma_chan[ch] ;
-	des_offset = dma->des0cnt * sizeof(struct dma_des_fmt0)/sizeof(unsigned long);
-
-	DPRINTK("[%s] : create fmt 0 descript size=%x\n", __func__, descript_attr.size);
-	DPRINTK("[%s] : des0cnt = %x\n", __func__, dma->des0cnt);
-
-	if ((ch >= MAX_DMA_CHANNELS) || (dma_chan[ch].in_use == 0)) {
-		printk("%s: bad DMA identifier\n", __func__) ;
-		return -EINVAL ;
-	}
-
-	if (dma->device_no != device_cfg.DeviceReqType) {
-		printk("%s: bad Device_NO\n", __func__) ;
-		return -ENODEV ;
-	}
-
-	descript.DataAddr = (unsigned long)descript_attr.data_addr;
-	if (descript_attr.interrupt_en == 1)
-		ReqCnt |= DMA_INTEN_DES;
-	if (descript_attr.end_descript == 1)
-		ReqCnt |= DMA_DES_END;
-	if (descript_attr.size > (SIZE_64KB - 1))
-		return -EOVERFLOW ;
-	descript.ReqCnt = ReqCnt | descript_attr.size;
-	DPRINTK("[%s]:des_offset = %d , des0 = 0x%x\n",
-		 __func__, des_offset, dma->des_addr.des_0 + des_offset);
-	*(dma->des_addr.des_0 + des_offset) = descript.ReqCnt;
-	*(dma->des_addr.des_0 + des_offset + 1) = descript.DataAddr;
-	++dma->des0cnt;
-	return 0;
-
-}
-
-int create_fmt1_descript(
-	dmach_t ch,
-	struct dma_device_cfg_s device_cfg,
-	struct des_attribute descript_attr)
-{
-	struct dma_info_s *dma ;
-	struct dma_des_fmt1 descript;
-	unsigned int ReqCnt = 0;
-	unsigned int des_offset;
-	descript.DataAddr = 0;
-	descript.ReqCnt = 0;
-	dma = &dma_chan[ch] ;
-	des_offset = (dma->max_des0cnt - 1) * sizeof(struct dma_des_fmt0) / sizeof(unsigned long);
-
-	DPRINTK("[%s]:create fmt 1 descript size=%x\n", __func__, descript_attr.size);
-	DPRINTK("[%s]:des0cnt = %x\n", __func__, dma->des0cnt);
-	DPRINTK("[%s]:branch_addr = %x\n", __func__, descript_attr.branch_addr);
-
-	if ((ch >= MAX_DMA_CHANNELS) || (dma_chan[ch].in_use == 0)) {
-		printk("%s: bad DMA identifier\n", __func__) ;
-		return -EINVAL ;
-	}
-
-	if (dma->device_no != device_cfg.DeviceReqType) {
-		printk("%s: bad Device_NO\n", __func__) ;
-		return -ENODEV ;
-	}
-	/*if (descript_attr.size > (SIZE_64KB - 1))*/
-	descript.DataAddr = (unsigned long)descript_attr.data_addr;
-	descript.BrAddr = (unsigned long)descript_attr.branch_addr;
-	if (descript_attr.interrupt_en == 1)
-		ReqCnt |= DMA_INTEN_DES;
-	if (descript_attr.end_descript == 1)
-		ReqCnt |= DMA_DES_END;
-	if (descript_attr.fmt == 1)
-		ReqCnt |= DMA_FORMAT_DES1;
-	if (descript_attr.size > (SIZE_64KB - 1))
-		return -EOVERFLOW ;
-	DPRINTK("[%s] : fmt_1 des_offset = %d , des0 = 0x%x\n",
-		__func__, des_offset, dma->des_addr.des_0 + des_offset);
-	descript.ReqCnt = ReqCnt | descript_attr.size;
-	*(dma->des_addr.des_0 + des_offset) = descript.ReqCnt;
-	*(dma->des_addr.des_0 + des_offset + 1) = descript.DataAddr;
-	*(dma->des_addr.des_0 + des_offset + 2) = descript.BrAddr ;
-	dma->des0cnt = 0;
-	return 0;
-}
-
-int clear_last_descript(
-	dmach_t ch,
-	struct dma_device_cfg_s device_cfg)
-{
-	struct dma_info_s *dma ;
-	unsigned int des_offset;
-	dma = &dma_chan[ch] ;
-
-	if ((dma->des0cnt - 1 >= 0))
-		des_offset = (dma->des0cnt - 1) * sizeof(struct dma_des_fmt0) / sizeof(unsigned long);
-	else
-		des_offset = (dma->max_des0cnt - 1) * sizeof(struct dma_des_fmt0) / sizeof(unsigned long);
-
-	if ((ch >= MAX_DMA_CHANNELS) || (dma_chan[ch].in_use == 0)) {
-		printk("%s: bad DMA identifier\n", __func__) ;
-		return -EINVAL ;
-	}
-
-	if (dma->device_no != device_cfg.DeviceReqType) {
-		printk("%s: bad Device_NO\n", __func__) ;
-		return -ENODEV ;
-	}
-	*(dma->des_addr.des_0 + des_offset) &= ~(DMA_DES_END);
-	return 0;
-}
-int add_descript(
-	dmach_t ch,
-	struct dma_device_cfg_s device_cfg,
-	dma_addr_t dma_ptr ,
-	unsigned int size)
-{
-	struct dma_info_s *dma ;
-	unsigned int residue_size;
-	unsigned int xfer_size;
-	unsigned int xfer_index;
-	unsigned int ret = 0;
-	struct des_attribute descript_attr;
-	int need_add_descript_count = 0;
-	dma = &dma_chan[ch] ;
-	residue_size = size;
-	xfer_index = 0; 
-	need_add_descript_count = size/SIZE_32KB ;
-	if (size%SIZE_32KB)
-		++need_add_descript_count;
-	if ((ch >= MAX_DMA_CHANNELS) || (dma_chan[ch].in_use == 0)) {
-		printk("%s: bad DMA identifier\n", __func__) ;
-		return -EINVAL ;
-	}
-
-	if (dma->device_no != device_cfg.DeviceReqType) {
-		printk("%s: bad Device_NO\n", __func__) ;
-		return -ENODEV ;
-	}
-	if ((dma->max_des0cnt - dma->residue_des0cnt) < need_add_descript_count) {
-		printk("%s:dma descripts are full\n",__func__);
-		return -EBUSY ;
-	}
-	while (residue_size > 0) {
-		if (residue_size == size)
-			ret = clear_last_descript(ch, device_cfg);
-
-		xfer_size = residue_size;
-		if (residue_size > SIZE_32KB) {
- 			//xfer_size = residue_size - SIZE_32KB;
- 			xfer_size =  SIZE_32KB;//vincent
-			dma->accu_size += xfer_size;
-			residue_size -= SIZE_32KB;
-			dma_ptr += xfer_size * xfer_index;
-		} else {
-			xfer_size = residue_size;
-			dma_ptr += xfer_size * xfer_index;
-			dma->accu_size += xfer_size;
-			residue_size = 0;
-		}
-
-		if (dma->des0cnt < dma->max_des0cnt - 1) {
-			if (residue_size <= SIZE_32KB)
-				descript_attr.end_descript = 1;
-			if (dma->accu_size >= device_cfg.ChunkSize) {
-				descript_attr.interrupt_en = 1;
-				dma->accu_size = 0;
-				dma->accu_size += xfer_size;
-			}
-			descript_attr.data_addr = dma_ptr;
-			descript_attr.size = xfer_size ;
-			descript_attr.fmt = 0;
-			ret = create_fmt0_descript(ch,
-				device_cfg,
-				descript_attr);
-		} else {
-			if (residue_size <= SIZE_32KB)
-				descript_attr.end_descript = 1;
-			if (dma->accu_size >= device_cfg.ChunkSize) {
-				descript_attr.interrupt_en = 1;
-				dma->accu_size = 0;
-				dma->accu_size += xfer_size;
-			}
-			descript_attr.data_addr = dma_ptr;
-			descript_attr.branch_addr = dma->des0_phy_addr;
-			descript_attr.size = xfer_size ;
-			descript_attr.fmt = 1;
-			ret = create_fmt1_descript(ch,
-				device_cfg,
-				descript_attr);
-		}
-		xfer_index++;
-	}
-	return xfer_index;
-}
-
-int revise_descript(
-	dmach_t ch,
-	struct dma_device_cfg_s device_cfg,
-	struct dma_mem_reg_group_s dma_mem_reg)
-{
-	struct dma_info_s *dma ;
-	unsigned int ret = 0;
-	unsigned int des_offset = 0;
-	unsigned int req_count = 0;
-	unsigned int data_address = 0;
-#ifdef DMA4_ERRATA 
-	unsigned long flags;
-	unsigned int now_time = 0;
-	unsigned int delay_time = 0;
-#endif
-	dma = &dma_chan[ch] ;
-	if ((ch >= MAX_DMA_CHANNELS) || (dma_chan[ch].in_use == 0)) {
-		printk("%s: bad DMA identifier\n", __func__) ;
-		return -EINVAL ;
-	}
-
-	if (dma->device_no != device_cfg.DeviceReqType) {
-		printk("%s: bad Device_NO\n", __func__) ;
-		return -ENODEV ;
-	}
-#ifdef DMA4ERRATA
-	if (dma->regs->DMA_CCR_CH[ch] & (SYSTEM_DMA_RUN)) {
-		spin_lock_irqsave(&dma_list_lock, flags);
-		dma->regs->DMA_CCR_CH[ch] |= (DMA_UP_MEMREG_EN);/*update memory register before reading*/
-		now_time = wmt_read_oscr();
-		while (dma->regs->DMA_CCR_CH[ch] &  (DMA_UP_MEMREG_EN)) {
-			delay_time = wmt_read_oscr() - now_time;
-			if (delay_time > 15) {/*5us*/
-				DPRINTK("[%d]Warnning:up_mem_reg did not clear[%x]\n", ch, dma->regs->DMA_CCR_CH[ch]);
-				dma->regs->DMA_CCR_CH[ch] &= ~DMA_UP_MEMREG_EN;/*clear DMA_UP_MEMREG_EN*/
-				break;
-			}
-
-		}
-		spin_unlock_irqrestore(&dma_list_lock, flags);
-	}
-#endif
-	req_count = dma_mem_reg.DMA_IF0RBR_CH;
-	req_count &= (DMA_DES_REQCNT_MASK) ;/*Vincent 2009.5.4*/
-	data_address = dma_mem_reg.DMA_IF0DAR_CH;
-	des_offset = dma_mem_reg.DMA_IF0CPR_CH - dma->des0_phy_addr ;
-	if (req_count  > 0) {
-		*(dma->des_addr.des_0 + (des_offset / sizeof(unsigned long))) &= ~(DMA_DES_REQCNT_MASK);
-		*(dma->des_addr.des_0 + (des_offset / sizeof(unsigned long)))  |= req_count;
-		*(dma->des_addr.des_0 + (des_offset / sizeof(unsigned long)) + 1) = 0;
-		*(dma->des_addr.des_0 + (des_offset / sizeof(unsigned long)) + 1) = data_address;
-	} else {
-		/*Vincent 2009/05/19*/
-		if (des_offset < (dma->max_des0cnt - 1) * DMA_DES0_SIZE)
-			dma_mem_reg.DMA_IF0CPR_CH += 8;
-		else
-			dma_mem_reg.DMA_IF0CPR_CH = dma->des0_phy_addr;
-
-	}
-	return ret ;
-}
-/*=============================================================================*/
-/**/
-/* 	wmt_start_dma - submit a data buffer for DMA*/
-/*	Memory To Device or Device To Memory*/
-/* 	@ch: identifier for the channel to use*/
-/* 	@dma_ptr: buffer physical (or bus) start address*/
-/*	@dma_ptr2: device FIFO address*/
-/* 	@size: buffer size*/
-/**/
-/*	Memory To Memory*/
-/* 	@ch: identifier for the channel to use*/
-/* 	@dma_ptr: buffer physical (or bus) source start address*/
-/*	@dma_ptr2: buffer physical (or bus) destination start address*/
-/* 	@size: buffer size*/
-/**/
-/* 	This function hands the given data buffer to the hardware for DMA*/
-/* 	access. If another buffer is already in flight then this buffer*/
-/* 	will be queued so the DMA engine will switch to it automatically*/
-/* 	when the previous one is done.  The DMA engine is actually toggling*/
-/* 	between two buffers so at most 2 successful calls can be made before*/
-/* 	one of them terminates and the callback function is called.*/
-/**/
-/* 	The @ch identifier is provided by a successful call to*/
-/* 	wmt_request_dma().*/
-/**/
-/* 	The @size must not be larger than %MAX_DMA_SIZE.  If a given buffer*/
-/* 	is larger than that then it's the caller's responsibility to split*/
-/* 	it into smaller chunks and submit them separately. If this is the*/
-/* 	case then a @size of %CUT_DMA_SIZE is recommended to avoid ending*/
-/* 	up with too small chunks. The callback function can be used to chain*/
-/* 	submissions of buffer chunks.*/
-/**/
-/* 	Error return values:*/
-/* 	%-EOVERFLOW:	Given buffer size is too big.*/
-/* 	%-EBUSY:	Both DMA buffers are already in use.*/
-/* 	%-EAGAIN:	Both buffers were busy but one of them just completed*/
-/* 			but the interrupt handler has to execute first.*/
-/**/
-/*	This function returs 0 on success.*/
-/**/
-/*=============================================================================*/
-int wmt_start_dma(dmach_t ch, dma_addr_t dma_ptr, dma_addr_t dma_prt2, unsigned int size)
-{
-	unsigned long flags;
-	int count ;
-	int ret = 0;
-	int descript_count = 0;
-	struct dma_info_s *dma = &dma_chan[ch] ;
-	/*dump_dma_regs(ch);*/
-
-	DPRINTK("size = %x, chunksize=%x\n", size, dma->device_cfg.ChunkSize);
-
-	if (size == 0)
-		return -EINVAL ;
-
-	local_irq_save(flags);
-
-	descript_count = add_descript(ch, dma->device_cfg, dma_ptr, size);
-	if (descript_count < 0){
-		ret = -EBUSY;
-		goto start_dma_out;
-	}
-
-	dma->residue_des0cnt += descript_count ;
- 	if (dma->residue_des0cnt > dma->max_des0cnt - 1)
- 	{
- 	DPRINTK("%s: dma->residue_des0cnt(%d)  is too large\n",
- 		__func__,dma->residue_des0cnt );
- 	dma->residue_des0cnt = dma->max_des0cnt - 1;
- 	
- 	}
-	DPRINTK("%s: ch = %d, dma_ptr =  0x%8.8x, size = %d (0x%8.8X)\n",
-		__func__, ch , dma_ptr, size , size);
-
-	/* Calculate burst count*/
-	if (dma->regs->DMA_CCR_CH[ch] & SYSTEM_DMA_RUN) {/*still run*/
-		wmb();
-		dma->regs->DMA_CCR_CH[ch] |= DMA_WAKE;
-		wmb();
-	} else {
-		count = size ;
-		dma_mem_regs->mem_reg_group[ch].DMA_IF0CPR_CH = dma->des0_phy_addr;
-		DPRINTK("dma descript 0 phy addr = 0x%x\n", dma_mem_regs->mem_reg_group[ch].DMA_IF0CPR_CH);
-		if (dma->device_cfg.DeviceReqType == MEMORY_DMA_REQ)
-			dma_mem_regs->mem_reg_group[ch].DMA_IF1DAR_CH = dma->des0_phy_addr;
-		wmb();
-		dma->regs->DMA_CCR_CH[ch] |= (SYSTEM_DMA_RUN | SYSTEM_DMA_REQ_EN);
-		wmb();
-	}
-
-start_dma_out:
-	local_irq_restore(flags);
-	return ret ;
-}
-
-int wmt_wake_dma(
-	dmach_t ch,
-	dma_addr_t dma_ptr,
-	dma_addr_t dma_prt2,
-	unsigned int size)
-{
-	int ret = 0;
-	struct dma_info_s *dma = &dma_chan[ch] ;
-	/*dump_dma_regs(ch);*/
-
-	DPRINTK("size = %x, chunksize=%x\n", size, dma->device_cfg.ChunkSize);
-
-	if (size == 0)
-		return -EINVAL ;
-	if (size > dma->device_cfg.ChunkSize)
-		return -EOVERFLOW ;
-	if (dma->regs->DMA_CCR_CH[ch] & SYSTEM_DMA_RUN) { /*still run*/
-		ret = add_descript(ch, dma->device_cfg, dma_ptr, size);
-		dma->residue_des0cnt += ret ;
-		wmb();
-		dma->regs->DMA_CCR_CH[ch] |= DMA_WAKE;
-		wmb();
-	}
-	return ret ;
-}
-
-/*=============================================================================*/
-/**/
-/*	wmt_request_dma - allocate one of the DMA chanels*/
-/*      @channel: Pointer to the location of the allocated channel's identifier*/
-/*	@device_id: An ascii name for the claiming device*/
-/*	@device: The WMT peripheral targeted by this request*/
-/*	@callback: Function to be called when the DMA completes*/
-/*	@data: A cookie passed back to the callback function*/
-/**/
-/* 	This function will search for a free DMA channel and returns the*/
-/* 	address of the hardware registers for that channel as the channel*/
-/* 	identifier. This identifier is written to the location pointed by*/
-/* 	@dma_regs. The list of possible values for @device are listed into*/
-/* 	linux/include/asm-arm/arch-wmt/dma.h as a dma_device_t enum.*/
-/**/
-/* 	Note that reading from a port and writing to the same port are*/
-/* 	actually considered as two different streams requiring separate*/
-/* 	DMA registrations.*/
-/**/
-/* 	The @callback function is called from interrupt context when one*/
-/* 	of the two possible DMA buffers in flight has terminated. That*/
-/* 	function has to be small and efficient while posponing more complex*/
-/* 	processing to a lower priority execution context.*/
-/**/
-/* 	If no channels are available, or if the desired @device is already in*/
-/* 	use by another DMA channel, then an error code is returned.  This*/
-/* 	function must be called before any other DMA calls.*/
-/**/
-/*      return: 0 if successful*/
-/**/
-/*=============================================================================*/
-int wmt_request_dma(dmach_t *channel, const char *device_id, enum dma_device_e device,
-	void (*callback)(void *data), void *callback_data)
-{
-	int ch  ;
-	int descript_size = MAX_DESCRIPT_SIZE;
-	struct dma_info_s *dma = NULL;
-	*channel = -1;
-
-	/*  Ask for Free Channels*/
-	spin_lock(&dma_list_lock);
-	for (ch = 1 ; ch < MAX_DMA_CHANNELS ; ++ch) {
-		dma = &dma_chan[ch];
-		if (dma->in_use == 0)
-			break ;
-	}
-	if (ch >= MAX_DMA_CHANNELS) {
-		DPRINTK("DMA %s: no free DMA channel available\n", device_id);
-		return -EBUSY;
-	}
-	spin_unlock(&dma_list_lock);
-
-	dma_int.request_chans |= (1 << ch) ;
-
-	/* Configure DMA channel settings.*/
-	*channel            = ch;
-	dma->device_id      = device_id;
-	dma->device_no      = device ;
-	dma->callback       = callback;
-	dma->callback_data  = callback_data ;
-	dma->in_use         = 1 ;
-	dma->des0cnt = 0 ;
-	dma->des1cnt = 0;
-	dma->accu_size = 0;
-	dma->residue_des0cnt = 0;
-	dma->residue_des1cnt = 0;
-	dma->descript_size = descript_size;
-
-	/* clear status register*/
-	dma->regs->DMA_ISR = 1 << ch;
-	dma_mem_regs->mem_reg_group[ch].DMA_IF0CPR_CH = 0x0; /*reset descript*/
-	dma_mem_regs->mem_reg_group[ch].DMA_IF1DAR_CH = 0x0; /*reset descript*/
-	dma->des_addr.des_0 = (unsigned long *)dma_alloc_coherent(
-		NULL,
-		descript_size,
-		&dma->des0_phy_addr,
-		GFP_KERNEL);
-	dma->max_des0cnt = (descript_size - DMA_DES1_SIZE) / DMA_DES0_SIZE + 1;
-	DPRINTK("descript 0 addr--- virt:0x%x , phy:0x%x\n", dma->des_addr.des_0, dma->des0_phy_addr);
-
-	/* setup default device*/
-	dma->device_cfg = dma_device_cfg_table[device] ;
-
-	dma->regs->DMA_CCR_CH[ch] = (dma_device_cfg_table[device].DefaultCCR & DMA_USER_SET_MASK) ;
-
-	if (device != MEMORY_DMA_REQ)
-		/*need to set device req number*/
-		dma->regs->DMA_CCR_CH[ch] |= device << DMA_REQ_ID_SHIFT;
-
-	else {
-		dma->des_addr.des_1 = (unsigned long *)dma_alloc_coherent(NULL,
-				descript_size, &dma->des0_phy_addr, GFP_KERNEL);
-		dma->max_des1cnt = (descript_size - DMA_DES1_SIZE)/DMA_DES0_SIZE + 1;
-	}
-
-
-	DPRINTK("requested dma ch=%d to device=%d\n", ch, device);
-
-	return 0 ;      /* No error*/
-}
-
-/*=============================================================================*/
-/**/
-/*	wmt_clear_dma - clear DMA pointers*/
-/*	@ch:identifier for the channel to use*/
-/**/
-/*	This clear any DMA state so the DMA engine is ready to restart*/
-/*	with new buffers through wmt_start_dma(). Any buffers in flight*/
-/*	are discarded.*/
-/**/
-/*	The @regs identifier is provided by a successful call to*/
-/*	wmt_request_dma().*/
-/**/
-/*      return: NULL*/
-/*=============================================================================*/
-void wmt_clear_dma(dmach_t ch)
-{
-	unsigned long flags;
-	struct dma_info_s *dma ;
-	dma = &dma_chan[ch] ;
-
-	local_irq_save(flags);
-
-	/* clear status register*/
-	dma->regs->DMA_CCR_CH[ch] &= ~(SYSTEM_DMA_REQ_EN);
-	udelay(5);
-	dma->regs->DMA_CCR_CH[ch] &= ~(SYSTEM_DMA_RUN);
-	dma->regs->DMA_ISR = 1 << ch; /*write 1 clear*/
-	dma->des0cnt = 0;
-	dma->des1cnt = 0;
-	dma->accu_size = 0;
-	dma->residue_des0cnt = 0;
-	dma->residue_des0cnt = 0;
-	local_irq_restore(flags);
-}
-
-/*=============================================================================*/
-/**/
-/* 	wmt_free_dma - free a WMT DMA channel*/
-/* 	@ch: identifier for the channel to free*/
-/**/
-/* 	This clears all activities on a given DMA channel and releases it*/
-/* 	for future requests.  The @ch identifier is provided by a*/
-/* 	successful call to wmt_request_dma().*/
-/**/
-/*      return: NULL*/
-/**/
-/*=============================================================================*/
-void wmt_free_dma(dmach_t ch)
-{
-	struct dma_info_s *dma;
-	enum dma_device_e dev_no ;
-
-	if ((unsigned) ch >= MAX_DMA_CHANNELS) {
-		DPRINTK("%s: bad DMA identifier\n", __func__);
-		return ;
-	}
-
-	dma = &dma_chan[ch];
-	if (dma->in_use == 0) {
-		DPRINTK("%s: Trying to free DMA%d\n", __func__, ch);
-		return;
-	}
-
-	if (dma->device_no == DEVICE_RESERVED) {
-		DPRINTK("%s: Trying to free free DMA\n", __func__);
-		return ;
-	}
-
-	wmt_clear_dma(ch);
-
-	/* Int*/
-	dma_int.request_chans &= ~(1 << ch) ;
-
-	dev_no = dma->device_no ;
-	dma_free_coherent(NULL,
-		dma->descript_size,
-		(void *)dma->des_addr.des_0,
-		(dma_addr_t)dma->des0_phy_addr);
-	if (dma->device_no == MEMORY_DMA_REQ) 
-		dma_free_coherent(NULL,
-			dma->descript_size,
-			(void *)dma->des_addr.des_1,
-			(dma_addr_t)dma->des1_phy_addr);
-
-	dma->device_no  = DEVICE_RESERVED ;
-	dma_chan[ch].device_id  = NULL ;
-	dma_chan[ch].des0cnt = 0;
-	dma_chan[ch].des1cnt = 0;
-	dma_chan[ch].accu_size = 0;
-	dma_chan[ch].residue_des0cnt = 0;
-	dma_chan[ch].residue_des0cnt = 0;
-	dma_chan[ch].max_des0cnt = 0;
-	dma_chan[ch].max_des1cnt = 0;
-	dma_chan[ch].in_use = 0;
-}
-
-/*=============================================================================*/
-/**/
-/*	wmt_reset_dma - reset a DMA channel*/
-/*	@ch: identifier for the channel to use*/
-/**/
-/*	This function resets and reconfigure the given DMA channel. This is*/
-/*	particularly useful after a sleep/wakeup event.*/
-/**/
-/*	The @ch identifier is provided by a successful call to*/
-/*	request_dma().*/
-/**/
-/*      return: NULL*/
-/**/
-/*=============================================================================*/
-void wmt_reset_dma(dmach_t ch)
-{
-	if (ch >= MAX_DMA_CHANNELS) {
-		DPRINTK("%s: bad DMA identifier\n", __func__);
-		return;
-	}
-
-	wmt_clear_dma(ch);
-}
-
-/*===========================================================================*/
-/*  wmt_setup_dma*/
-/**/
-/*  Don't setup Dma channel while Dma is busy*/
-/**/
-/*  return: 0: success*/
-/*===========================================================================*/
-int wmt_setup_dma(dmach_t ch, struct dma_device_cfg_s device_cfg)
-{
-	struct dma_info_s *dma ;
-	enum dma_device_e dev_no ;
-
-	dma = &dma_chan[ch] ;
-
-	if ((ch >= MAX_DMA_CHANNELS) || (dma_chan[ch].in_use == 0)) {
-		printk("%s: bad DMA identifier\n", __func__) ;
-		return -EINVAL ;
-	}
-
-	if (dma->device_no != device_cfg.DeviceReqType) {
-		printk("%s: bad Device_NO\n", __func__) ;
-		return -ENODEV ;
-	}
-
-	/* Apply new device config to DMA interface.*/
-	dev_no = dma->device_no ;
-	dma_device_cfg_table[dev_no] = device_cfg ;
-	dma->device_cfg = dma_device_cfg_table[dev_no] ;
-
-	/* Clear status register.*/
-	dma->regs->DMA_ISR = 1<<ch;
-
-	DPRINTK("%s old CCR=0x%.8x\n", __func__, dma->regs->DMA_CCR_CH[ch]) ;
-
-	/* Apply new DMA config to DMA controller.*/
-	dma->regs->DMA_CCR_CH[ch] = dma_device_cfg_table[dev_no].DefaultCCR ;
-	DPRINTK("%s new CCR=0x%.8x\n", __func__, dma_device_cfg_table[dev_no].DefaultCCR) ;
-	DPRINTK("%s old CCR=0x%.8x\n", __func__, dma->regs->DMA_CCR_CH[ch].CCR) ;
-	if (device_cfg.DeviceReqType  != MEMORY_DMA_REQ)
-		dma->regs->DMA_CCR_CH[ch] |= device_cfg.DeviceReqType << DMA_REQ_ID_SHIFT;
-	/*Device -> Memory(Read) && Memory(Write)i-->Device*/
-	if (dev_no != MEMORY_DMA_REQ) {
-		dma_mem_regs->mem_reg_group[ch].DMA_IF1DAR_CH = dma->device_cfg.MIF1addr;
-		/*dma_mem_regs->mem_reg_group[ch].DMA_IF0CPR_CH = 0 ;*/
-	}
-	/*
-	if (dev_no == MEMORY_DMA_REQ) {
-		dma_mem_regs->mem_reg_group[ch].DMA_IF0CPR_CH = dma->des0_phy_addr;
-		dma_mem_regs->mem_reg_group[ch].DMA_IF1CPR_CH = dma->des1_phy_addr;
-	}
-	*/
-	DPRINTK("%s new CCR=0x%.8x\n", __func__, dma->regs->DMA_CCR_CH[ch]) ;
-
-	return 0;
-}
-
-/*=============================================================================*/
-/**/
-/*	wmt_stop_dma - stop DMA in progress*/
-/*	@regs: identifier for the channel to use*/
-/**/
-/*	This stops DMA without clearing buffer pointers. Unlike*/
-/*	clear_dma() this allows subsequent use of resume_dma()*/
-/*	or get_dma_pos().*/
-/**/
-/*	The @regs identifier is provided by a successful call to*/
-/*	request_dma().*/
-/**/
-/*=============================================================================*/
-void wmt_stop_dma(dmach_t ch)
-{
-	struct dma_info_s *dma;
-#ifdef DMA4_ERRATA
-	unsigned int now_time = 0;
-	unsigned int delay_time = 0;
-#endif
-
-	if ((ch >= MAX_DMA_CHANNELS) ||
-	     (dma_chan[ch].in_use == 0)) {
-		DPRINTK("%s: bad DMA identifier\n", __func__);
-		return;
-	}
-
-	dma = &dma_chan[ch];
-	dma->regs->DMA_CCR_CH[ch] &= ~(SYSTEM_DMA_REQ_EN);
-	udelay(5);
-#ifdef DMA4_ERRATA
-	if (dma->regs->DMA_CCR_CH[ch] & (SYSTEM_DMA_RUN)) {
-		dma->regs->DMA_CCR_CH[ch] |= (DMA_UP_MEMREG_EN);/*update memory register before reading*/
-		now_time = wmt_read_oscr();
-		while (dma->regs->DMA_CCR_CH[ch] & (DMA_UP_MEMREG_EN)) {
-			delay_time = wmt_read_oscr() - now_time;
-			if (delay_time > 15) {/*5us*/
-				DPRINTK("[%d]Warnning:up_mem_reg did not clear[%x]\n", ch, dma->regs->DMA_CCR_CH[ch]);
-				dma->regs->DMA_CCR_CH[ch] &= ~DMA_UP_MEMREG_EN;/*clear DMA_UP_MEMREG_EN*/
-				break;
-			}
-		}
-	}
-#endif
-	dma->regs->DMA_CCR_CH[ch] &= ~SYSTEM_DMA_RUN;
-}
-
-/*=============================================================================*/
-/**/
-/*	wmt_resume_dma - resume DMA on a stopped channel*/
-/*	@regs: identifier for the channel to use*/
-/**/
-/*	This resumes DMA on a channel previously stopped with*/
-/*	wmt_stop_dma().*/
-/**/
-/*	The @regs identifier is provided by a successful call to*/
-/*	wmt_request_dma().*/
-/**/
-/*=============================================================================*/
-void wmt_resume_dma(dmach_t ch)
-{
-	struct dma_info_s *dma;
-	struct dma_mem_reg_group_s dma_mem_reg ;
-	dma = &dma_chan[ch] ;
-	if (dma->regs->DMA_CCR_CH[ch] & DMA_ACTIVE) {/*if dma was active , disable dma first*/
-		dma->regs->DMA_CCR_CH[ch] &= ~(SYSTEM_DMA_REQ_EN);
-		udelay(5);
-		dma->regs->DMA_CCR_CH[ch] &= ~(SYSTEM_DMA_RUN);
-	}
-	if ((ch >= MAX_DMA_CHANNELS) ||
-		(dma_chan[ch].in_use == 0)) {
-		DPRINTK("%s: bad DMA identifier\n", __func__);
-		return;
-	}
-	dma_mem_reg = wmt_get_dma_pos_info(ch);
-	revise_descript(ch, dma->device_cfg, dma_mem_reg);
-	dma->regs->DMA_CCR_CH[ch] |= (SYSTEM_DMA_RUN | SYSTEM_DMA_REQ_EN);
-}
-
-/*=============================================================================*/
-/**/
-/*	wmt_get_dma_pos_info - return current DMA position*/
-/*	@ch: identifier for the channel to use*/
-/**/
-/*	This function returns the current physical (or bus) address for the*/
-/*	given DMA channel.  If the channel is running i.e. not in a stopped*/
-/*	state then the caller must disable interrupts prior calling this*/
-/*	function and process the returned value before re-enabling them to*/
-/*	prevent races with the completion interrupt handler and the callback*/
-/*	function. The validation of the returned value is the caller's*/
-/*	responsibility as well -- the hardware seems to return out of range*/
-/*	values when the DMA engine completes a buffer.*/
-/**/
-/*	The @ch identifier is provided by a successful call to*/
-/*	wmt_request_dma().*/
-/**/
-/*=============================================================================*/
-struct dma_mem_reg_group_s wmt_get_dma_pos_info(dmach_t ch)
-{
-	struct dma_mem_reg_group_s dma_mem_reg;
-#ifdef DMA4_ERRATA
-	struct dma_info_s *dma;
-	unsigned int now_time = 0;
-	unsigned long flags;
-	unsigned int delay_time = 0;
-	dma = &dma_chan[ch];
-#endif
-
-	if ((ch >= MAX_DMA_CHANNELS) ||
-	     (dma_chan[ch].in_use == 0)) {
-		DPRINTK("%s: bad DMA identifier\n", __func__);
-		goto out;
-	}
-#ifdef DMA4_ERRATA 
-	if (dma->regs->DMA_CCR_CH[ch] & (SYSTEM_DMA_RUN)) {
-		spin_lock_irqsave(&dma_list_lock, flags);
-		dma->regs->DMA_CCR_CH[ch] |= (DMA_UP_MEMREG_EN);/*update memory register before reading*/
-
-		now_time = wmt_read_oscr();
-		while (dma->regs->DMA_CCR_CH[ch] &  (DMA_UP_MEMREG_EN)) {
-			delay_time = wmt_read_oscr() - now_time;
-			if (delay_time > 15) {/*5us*/
-				DPRINTK("[%d]Warnning:up_mem_reg did not clear[%x]\n", ch, dma->regs->DMA_CCR_CH[ch]);
-				dma->regs->DMA_CCR_CH[ch] &= ~DMA_UP_MEMREG_EN;/*clear DMA_UP_MEMREG_EN*/
-				break;
-			}
-
-		}
-
-		spin_unlock_irqrestore(&dma_list_lock, flags);
-	}
-#endif
-
-	dma_mem_reg.DMA_IF0BAR_CH = dma_mem_regs->mem_reg_group[ch].DMA_IF0BAR_CH;
-	dma_mem_reg.DMA_IF0CPR_CH = dma_mem_regs->mem_reg_group[ch].DMA_IF0CPR_CH;
-	dma_mem_reg.DMA_IF0RBR_CH = dma_mem_regs->mem_reg_group[ch].DMA_IF0RBR_CH;
-	dma_mem_reg.DMA_IF0DAR_CH = dma_mem_regs->mem_reg_group[ch].DMA_IF0DAR_CH;
-	dma_mem_reg.DMA_IF1BAR_CH = dma_mem_regs->mem_reg_group[ch].DMA_IF1BAR_CH;
-	dma_mem_reg.DMA_IF1CPR_CH = dma_mem_regs->mem_reg_group[ch].DMA_IF1CPR_CH;
-	dma_mem_reg.DMA_IF1RBR_CH = dma_mem_regs->mem_reg_group[ch].DMA_IF1RBR_CH;
-	dma_mem_reg.DMA_IF1DAR_CH = dma_mem_regs->mem_reg_group[ch].DMA_IF1DAR_CH;
-
-out:
-	return dma_mem_reg;
-}
-
-/*=============================================================================*/
-/**/
-/*      wmt_get_dma_pos - return current DMA position*/
-/*      @ch: identifier for the channel to use*/
-/**/
-/*      This function returns the current physical (or bus) address for the*/
-/*      given DMA channel.  If the channel is running i.e. not in a stopped*/
-/*      state then the caller must disable interrupts prior calling this*/
-/*      function and process the returned value before re-enabling them to*/
-/*      prevent races with the completion interrupt handler and the callback*/
-/*      function. The validation of the returned value is the caller's*/
-/*      responsibility as well -- the hardware seems to return out of range*/
-/*      values when the DMA engine completes a buffer.*/
-/**/
-/*      The @ch identifier is provided by a successful call to*/
-/*      wmt_request_dma().*/
-/**/
-/*=============================================================================*/
-unsigned int  wmt_get_dma_pos(dmach_t ch)
-{
-	struct dma_mem_reg_group_s dma_mem_reg;
-	struct dma_info_s *dma;
-#ifdef DMA4_ERRATA
-	unsigned long flags;
-	unsigned int now_time;
-	unsigned int delay_time;
-#endif
-	dma = &dma_chan[ch];
-
-	if ((ch >= MAX_DMA_CHANNELS) ||
-	     (dma_chan[ch].in_use == 0)) {
-		DPRINTK("%s: bad DMA identifier\n", __func__);
-		goto out;
-	}
-#ifdef DAM4_ERRATA
-	if (dma->regs->DMA_CCR_CH[ch] & (SYSTEM_DMA_RUN)) {
-		spin_lock_irqsave(&dma_list_lock, flags);
-		dma->regs->DMA_CCR_CH[ch] |= (DMA_UP_MEMREG_EN);/*update memory register before reading*/
-		now_time = wmt_read_oscr();
-		while (dma->regs->DMA_CCR_CH[ch] & (DMA_UP_MEMREG_EN)) {
-			delay_time = wmt_read_oscr() - now_time;
-			if (delay_time > 15) {/*5us*/
-				dma->regs->DMA_CCR_CH[ch] &= ~DMA_UP_MEMREG_EN;/*clear DMA_UP_MEMREG_EN*/
-				break;
-			}
-		}
-		spin_unlock_irqrestore(&dma_list_lock, flags);
-	}
-#endif
-
-	dma_mem_reg.DMA_IF0BAR_CH = dma_mem_regs->mem_reg_group[ch].DMA_IF0BAR_CH;
-	dma_mem_reg.DMA_IF0CPR_CH = dma_mem_regs->mem_reg_group[ch].DMA_IF0CPR_CH;
-	dma_mem_reg.DMA_IF0RBR_CH = dma_mem_regs->mem_reg_group[ch].DMA_IF0RBR_CH;
-	dma_mem_reg.DMA_IF0DAR_CH = dma_mem_regs->mem_reg_group[ch].DMA_IF0DAR_CH;
-	dma_mem_reg.DMA_IF1BAR_CH = dma_mem_regs->mem_reg_group[ch].DMA_IF1BAR_CH;
-	dma_mem_reg.DMA_IF1CPR_CH = dma_mem_regs->mem_reg_group[ch].DMA_IF1CPR_CH;
-	dma_mem_reg.DMA_IF1RBR_CH = dma_mem_regs->mem_reg_group[ch].DMA_IF1RBR_CH;
-	dma_mem_reg.DMA_IF1DAR_CH = dma_mem_regs->mem_reg_group[ch].DMA_IF1DAR_CH;
-
-out:
-	return dma_mem_reg.DMA_IF0DAR_CH;
-}
-
-
-/*===========================================================================*/
-/*  wmt_dma_busy*/
-/**/
-/*  return: 1: busy , 0: not busy , other: fail*/
-/*===========================================================================*/
-int wmt_dma_busy(dmach_t ch)
-{
-	struct dma_info_s *dma;
-
-	dma = &dma_chan[ch];
-	if (ch >= MAX_DMA_CHANNELS || (dma_chan[ch].in_use == 0)) {
-		DPRINTK("%s: bad DMA identifier\n", __func__);
-		return -1 ;
-	}
-
-	if (dma->regs->DMA_ISR & (1<<ch)) {
-		dma->regs->DMA_ISR = (1<<ch); /*write 1 clear*/
-		return 0 ;
-	} else
-		return 1;
-}
-
-/*===========================================================================*/
-/*  wmt_dump_dma_regs*/
-/**/
-/*  return: NULL*/
-/*===========================================================================*/
-void wmt_dump_dma_regs(dmach_t ch)
-{
-	struct dma_info_s *dma = &dma_chan[ch] ;
-	struct dma_regs_s *regs  = dma->regs ;
-#ifdef DMA4_ERRATA
-	unsigned long flags;
-	unsigned int now_time = 0;
-	unsigned int delay_time = 0;
-#endif
-
-	printk("0x%8.8X : [0x%8.8X] GCR \n", \
-		(unsigned int)&(regs->DMA_GCR) , (unsigned int)regs->DMA_GCR) ;
-	printk("0x%8.8X : [0x%8.8X] MPRP \n", \
-		(unsigned int)&(regs->DMA_MRPR) , (unsigned int)regs->DMA_MRPR) ;
-	printk("0x%8.8X : [0x%8.8X] IER \n", \
-		(unsigned int)&(regs->DMA_IER) , (unsigned int)regs->DMA_IER) ;
-	printk("0x%8.8X : [0x%8.8X] ISR \n", \
-		(unsigned int)&(regs->DMA_ISR) , (unsigned int)regs->DMA_ISR) ;
-	printk("0x%8.8X : [0x%8.8X] TMR \n", \
-		(unsigned int)&(regs->DMA_TMR) , (unsigned int)regs->DMA_TMR) ;
-	printk("0x%8.8X : [0x%8.8X] CCR \n", \
-		(unsigned int)&(regs->DMA_CCR_CH[ch]) , (unsigned int)regs->DMA_CCR_CH[ch]) ;
-
-#ifdef DMA4_ERRATA 
-	if (dma->regs->DMA_CCR_CH[ch] & (SYSTEM_DMA_RUN)) {
-		spin_lock_irqsave(&dma_list_lock, flags);
-		dma->regs->DMA_CCR_CH[ch] |= (DMA_UP_MEMREG_EN);/*update memory register before reading*/
-
-		now_time = wmt_read_oscr();
-		while (dma->regs->DMA_CCR_CH[ch] &  (DMA_UP_MEMREG_EN)) {
-			delay_time = wmt_read_oscr() - now_time;
-			if (delay_time > 15) {/*5us*/
-				DPRINTK("[%d]Warnning:up_mem_reg did not clear[%x]\n", ch, dma->regs->DMA_CCR_CH[ch]);
-				dma->regs->DMA_CCR_CH[ch] &= ~DMA_UP_MEMREG_EN;/*clear DMA_UP_MEMREG_EN*/
-				break;
-			}
-
-		}
-
-		spin_unlock_irqrestore(&dma_list_lock, flags);
-	}
-#endif
-	printk("0x%8.8X : [0x%8.8X] Residue Bytes 0 \n", \
-		(unsigned int)&(dma_mem_regs->mem_reg_group[ch].DMA_IF0RBR_CH)
-		, (unsigned int)dma_mem_regs->mem_reg_group[ch].DMA_IF0RBR_CH) ;
-	printk("0x%8.8X : [0x%8.8X] Data Address 0 \n", \
-		(unsigned int)&(dma_mem_regs->mem_reg_group[ch].DMA_IF0DAR_CH)
-		, (unsigned int)dma_mem_regs->mem_reg_group[ch].DMA_IF0DAR_CH) ;
-	printk("0x%8.8X : [0x%8.8X] Branch Address 0 \n", \
-		(unsigned int)&(dma_mem_regs->mem_reg_group[ch].DMA_IF0BAR_CH)
-		, (unsigned int)dma_mem_regs->mem_reg_group[ch].DMA_IF0BAR_CH) ;
-	printk("0x%8.8X : [0x%8.8X] Command Pointer  0 \n", \
-		(unsigned int)&(dma_mem_regs->mem_reg_group[ch].DMA_IF0CPR_CH)
-		, (unsigned int)dma_mem_regs->mem_reg_group[ch].DMA_IF0CPR_CH) ;
-
-	printk("0x%8.8X : [0x%8.8X] Residue Bytes 1 \n", \
-		(unsigned int)&(dma_mem_regs->mem_reg_group[ch].DMA_IF1RBR_CH)
-		, (unsigned int)dma_mem_regs->mem_reg_group[ch].DMA_IF1RBR_CH) ;
-	printk("0x%8.8X : [0x%8.8X] Data Address 1 \n", \
-		(unsigned int)&(dma_mem_regs->mem_reg_group[ch].DMA_IF1DAR_CH)
-		, (unsigned int)dma_mem_regs->mem_reg_group[ch].DMA_IF1DAR_CH) ;
-	printk("0x%8.8X : [0x%8.8X] Branch Address 1 \n", \
-		(unsigned int)&(dma_mem_regs->mem_reg_group[ch].DMA_IF1BAR_CH)
-		, (unsigned int)dma_mem_regs->mem_reg_group[ch].DMA_IF1BAR_CH) ;
-	printk("0x%8.8X : [0x%8.8X] Command Pointer  1 \n", \
-		(unsigned int)&(dma_mem_regs->mem_reg_group[ch].DMA_IF1CPR_CH)
-		, (unsigned int)dma_mem_regs->mem_reg_group[ch].DMA_IF1CPR_CH) ;
-
-}
-
-
-#ifdef CONFIG_PM
-static int dma_suspend(void)
-{
-	return 0;
-}
-
-static void dma_resume(void)
-{
-	struct dma_regs_s *dma_regs ;
-	auto_pll_divisor(DEV_DMA, CLK_ENABLE, 0, 0);
-	dma_regs = (struct dma_regs_s *) (io_p2v(DMA_CTRL_CFG_BASE_ADDR)) ;
-	/*dma_regs->GCR = ( DMA_GCR_GDMA_ENABLE | DMA_GCR_PRIORITY_FIXED | DMA_GCR_GINT_ENABLE ) ;*/
-	dma_regs->DMA_GCR |= DMA_GLOBAL_EN;
-	dma_regs->DMA_ISR = ALL_INT_CLEAR;
-	dma_regs->DMA_IER |= ALL_INT_EN;
-	dma_regs->DMA_TMR &= ~SCHEDULE_RR_DISABLE; /*use RR schedule*/
-	dma_regs->DMA_MRPR = (unsigned int)dma_mem_phy;
-}
-
-#else
-#define dma_suspend NULL
-#define dma_resume  NULL
-#endif /* CONFIG_PM */
-
-
-static struct syscore_ops wmt_dma_syscore_ops = {
-	.suspend	= dma_suspend,
-	.resume		= dma_resume,
-};
-
-static int __init wmt_dma_init_devicefs(void)
-{
-	register_syscore_ops(&wmt_dma_syscore_ops);
-	return 0;
-}
-
-device_initcall(wmt_dma_init_devicefs);
-
-/*===========================================================================*/
-/*  wmt_dma_init*/
-/**/
-/*  return: 0*/
-/*===========================================================================*/
-static int __init
-wmt_dma_init(void)
-{
-	int ch ;
-	int ret = 0;
-	struct dma_regs_s *dma_regs ;
-	/*
-	*(volatile unsigned int *)(0xD8130254) |= BIT5;
-	*/
-	auto_pll_divisor(DEV_DMA, CLK_ENABLE, 0, 0);
-
-	dma_regs = (struct dma_regs_s *) (io_p2v(DMA_CTRL_CFG_BASE_ADDR)) ;
-
-	/**/
-	/* software initial*/
-	/**/
-	dma_int.request_chans = 0 ;
-	dma_int.regs = (struct dma_regs_s *) (io_p2v(DMA_CTRL_CFG_BASE_ADDR)) ;
-
-	for (ch = 0 ; ch < MAX_DMA_CHANNELS ; ++ch) {
-		dma_chan[ch].channel_no = ch ;
-		dma_chan[ch].regs       = (struct dma_regs_s *) (io_p2v(DMA_CTRL_CFG_BASE_ADDR)) ;
-		dma_chan[ch].irq        = ch ;
-		dma_chan[ch].device_no  = DEVICE_RESERVED ;
-		dma_chan[ch].in_use     = 0 ;
-	}
-
-	dma_mem_regs = (struct dma_mem_reg_s *) (io_p2v((DMA_CTRL_CFG_BASE_ADDR + DMA_MEM_REG_OFFSET)));
-	if (!dma_mem_regs) {
-		printk("dma memory register allocate failed\n");
-		ret = -1;
-		return ret;
-	}
-	dma_mem_phy = DMA_CTRL_CFG_BASE_ADDR + DMA_MEM_REG_OFFSET;
-	DPRINTK("MEM_REGS ADDR:Virt = 0x%x , Phy = 0x%x\n", dma_mem_regs , dma_mem_phy);
-
-	if (dma_mem_phy & 0x000000FF) {/*8 DW alignment*/
-		printk("dma memory registers did not 8 DW alignment");
-		ret = -1;
-		return ret;
-	}
-
-	/**/
-	/* hardware initial*/
-	/**/
-	dma_regs->DMA_GCR |= DMA_SW_RST ;
-	dma_regs->DMA_GCR |= DMA_GLOBAL_EN;
-	dma_regs->DMA_ISR = ALL_INT_CLEAR;
-	dma_regs->DMA_IER |= ALL_INT_EN;
-	dma_regs->DMA_TMR &= ~SCHEDULE_RR_DISABLE; /*use RR schedule*/
-	dma_regs->DMA_MRPR = (unsigned int)dma_mem_phy;
-	DPRINTK("0x%8.8X : [0x%8.8X] DMA_GSR_REG \n", \
-		(unsigned int)&dma_regs->GSR , dma_regs->GSR) ;
-
-	for (ch = 0 ; ch < MAX_DMA_CHANNELS ; ++ch) {
-		dma_mem_regs->mem_reg_group[ch].DMA_IF0CPR_CH = 0x100;
-		dma_mem_regs->mem_reg_group[ch].DMA_IF1DAR_CH = 0x100;
-		dma_regs->DMA_CCR_CH[ch] = 0x0;
-	}
-	DPRINTK("0x%8.8X : [0x%8.8X] DMA_GCR_REG \n", \
-		(unsigned int)&dma_regs->DMA_GCR , dma_regs->DMA_GCR) ;
-	/*
-	for (ch = 0; ch < MAX_DMA_CHANNELS ; ++ch)
-		request_irq(dma_irq_no[ch], dma_irq_handler, IRQF_DISABLED, "dma", NULL);
-	*/
-	request_irq(IRQ_DMA_NONS, dma_irq_handler, IRQF_DISABLED, "dma", NULL);
-
-	return ret;
-}
-
-/*===========================================================================*/
-/*  dma_exit*/
-/**/
-/*  return: 0*/
-/*===========================================================================*/
-static void __exit
-wmt_dma_exit(void)
-{
-	int ch;
-	/*remove_proc_entry("driver/dma", NULL);*/
-	dma_free_coherent(NULL,
-		sizeof(struct dma_mem_reg_s),
-		dma_mem_regs,
-		dma_mem_phy);
-
-	for (ch = 0; ch < MAX_DMA_CHANNELS ; ++ch)
-		free_irq(dma_irq_no[ch], NULL);
-}
-
-__initcall(wmt_dma_init);
-__exitcall(wmt_dma_exit);
-
-EXPORT_SYMBOL(wmt_request_dma);
-EXPORT_SYMBOL(wmt_setup_dma);
-EXPORT_SYMBOL(wmt_free_dma);
-EXPORT_SYMBOL(wmt_clear_dma);
-EXPORT_SYMBOL(wmt_reset_dma);
-EXPORT_SYMBOL(wmt_start_dma);
-EXPORT_SYMBOL(wmt_stop_dma);
-EXPORT_SYMBOL(wmt_resume_dma);
-EXPORT_SYMBOL(wmt_get_dma_pos_info);
-EXPORT_SYMBOL(wmt_dma_busy);
-EXPORT_SYMBOL(wmt_dump_dma_regs);
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/generic.c b/ANDROID_3.4.5/arch/arm/mach-wmt/generic.c
deleted file mode 100755
index 95edaef0..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/generic.c
+++ /dev/null
@@ -1,790 +0,0 @@
-/*++
-	linux/arch/arm/mach-wmt/generic.c
-
-	wmt generic architecture level codes
-	Copyright (c) 2013  WonderMedia Technologies, Inc.
-
-	This program is free software: you can redistribute it and/or modify it under the
-	terms of the GNU General Public License as published by the Free Software Foundation,
-	either version 2 of the License, or (at your option) any later version.
-
-	This program is distributed in the hope that it will be useful, but WITHOUT
-	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-	PARTICULAR PURPOSE.  See the GNU General Public License for more details.
-	You should have received a copy of the GNU General Public License along with
-	this program.  If not, see <http://www.gnu.org/licenses/>.
-
-	WonderMedia Technologies, Inc.
-	10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
---*/
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/pm.h>
-#include <linux/cpufreq.h>
-#include <linux/ioport.h>
-#include <linux/platform_device.h>
-
-#include <mach/hardware.h>
-#include <mach/wmt_secure.h>
-#include <asm/system.h>
-#include <asm/pgtable.h>
-#include <asm/mach/map.h>
-#include <asm/irq.h>
-#include <asm/sizes.h>
-#include <linux/i2c.h>
-
-#include <linux/mfd/wm8994/pdata.h>
-#include <linux/regulator/fixed.h>
-#include <linux/regulator/machine.h>
-
-#include "generic.h"
-#include <linux/spi/spi.h>
-
-#ifdef CONFIG_WMT_NEWSPI_SUPPORT 
-#include <mach/wmt-spi.h>
-#endif
-
-#ifdef CONFIG_WMT_NEWSPI1_SUPPORT 
-#include <mach/wmt-spi.h>
-#endif
-
-#include <asm/hardware/cache-l2x0.h>
-#include <mach/wmt_env.h>
-
-extern void enable_user_access(void);
-
-/* TODO*/
-#define PMHC_HIBERNATE 0x205
-extern void __init wmt_gpio_init(void);
-
-extern void wmt_power_up_debounce_value(void);
-extern void wmt_restart(char mode, const char *cmd);
-extern void (*arm_pm_restart)(char str, const char *cmd);
-static void wmt_power_off(void)
-{
-#ifdef CONFIG_PM
-	/*set power button debounce value*/
-	wmt_power_up_debounce_value();
-#endif
-	mdelay(100);
-	local_irq_disable();
-
-	*(volatile unsigned int *)0xfe018008 |= 0x03030303; //scu output pm	
-	
-#ifndef CONFIG_SMP
-	PMCEU_VAL |= 0x00800000;//sf boot, enable sf for single core pm
-	mdelay(1);
-#endif
-	
-	/*
-	 * Set scratchpad to zero, just in case it is used as a restart
-	 * address by the bootloader. Since PB_RESUME button has been
-	 * set to be one of the wakeup sources, clean the resume address
-	 * will cause zacboot to issue a SW_RESET, for design a behavior
-	 * to let PB_RESUME button be a power on button.
-	 *
-	 * Also force to disable watchdog timer, if it has been enabled.
-	 */
-	HSP0_VAL = 0;
-	OSTW_VAL &= ~OSTW_WE;
-
-	/*
-	 * Well, I cannot power-off myself,
-	 * so try to enter power-off suspend mode.
-	 */
-	
-	//for single core
-#ifndef CONFIG_SMP
-	HSP7_VAL = 0xffffffb8;
-	while(HSP7_VAL != 0xffffffb8);
-	asm("sev" : : "r" (0));
-#endif		
-		
-	//PMWTC_VAL = 0x2000;//DCDET falling
-	*(unsigned char *)0xfe13005c = 0x0;
-#if 0	
-	PMWT_VAL = 0x40000000;
-	mdelay(1);
-	PMWS_VAL = PMWS_VAL;
-	mdelay(1);
-	PMWE_VAL = 0x00004080;//DCDET + PWRBTN
-	mdelay(1);
-	WK_TRG_EN_VAL = 0x00004080;//DCDET + PWRBTN
-
-	if (DCDET_STS_VAL & 0x100)
-		PMHC_VAL = PMHC_SUSPEND;
-//#else
-	if (DCDET_STS_VAL & 0x100)
-		PMSR_VAL = PMSR_SWR;
-		
-	else		
-#endif		
-	PMHC_VAL = PMHC_HIBERNATE;
-	//asm("mcr%? p15, 0, %0, c7, c0, 4" : : "r" (0));		/* Force ARM to idle mode*/
-	do {
-		asm("wfi" : : "r" (0));		/* Force ARM to idle mode*/
-	} while(1);
-}
-
-static struct resource wmt_uart0_resources[] = {
-	[0] = {
-		.start  = UART0_BASE_ADDR,
-		.end    = (UART0_BASE_ADDR + 0xFFFF),
-		.flags  = IORESOURCE_MEM,
-	},
-};
-
-static struct resource wmt_uart1_resources[] = {
-	[0] = {
-		.start  = UART1_BASE_ADDR,
-		.end    = (UART1_BASE_ADDR + 0xFFFF),
-		.flags  = IORESOURCE_MEM,
-	},
-};
-
-#ifdef CONFIG_UART_2_3_ENABLE
-static struct resource wmt_uart2_resources[] = {
-	[0] = {
-		.start  = UART2_BASE_ADDR,
-		.end    = (UART2_BASE_ADDR + 0xFFFF),
-		.flags  = IORESOURCE_MEM,
-	},
-};
-
-static struct resource wmt_uart3_resources[] = {
-	[0] = {
-		.start  = UART3_BASE_ADDR,
-		.end    = (UART3_BASE_ADDR + 0xFFFF),
-		.flags  = IORESOURCE_MEM,
-	},
-};
-#endif
-
-static struct platform_device wmt_uart0_device = {
-	.name           = "uart",
-	.id             = 0,
-	.num_resources  = ARRAY_SIZE(wmt_uart0_resources),
-	.resource       = wmt_uart0_resources,
-};
-
-static struct platform_device wmt_uart1_device = {
-	.name           = "uart",
-	.id             = 1,
-	.num_resources  = ARRAY_SIZE(wmt_uart1_resources),
-	.resource       = wmt_uart1_resources,
-};
-
-#ifdef CONFIG_UART_2_3_ENABLE
-static struct platform_device wmt_uart2_device = {
-	.name           = "uart",
-	.id             = 2,
-	.num_resources  = ARRAY_SIZE(wmt_uart2_resources),
-	.resource       = wmt_uart2_resources,
-};
-
-static struct platform_device wmt_uart3_device = {
-	.name           = "uart",
-	.id             = 3,
-	.num_resources  = ARRAY_SIZE(wmt_uart3_resources),
-	.resource       = wmt_uart3_resources,
-};
-#endif
-
-static struct resource wmt_sf_resources[] = {
-	[0] = {
-		.start  = SF_MEM_CTRL_CFG_BASE_ADDR,
-		.end    = SF_MEM_CTRL_CFG_BASE_ADDR + 0x3FF,
-		.flags  = IORESOURCE_MEM,
-	},
-};
-
-static struct platform_device wmt_sf_device = {
-	.name           = "sf",
-	.id             = 0,
-	.num_resources  = ARRAY_SIZE(wmt_sf_resources),
-	.resource       = wmt_sf_resources,
-};
-
-#ifdef CONFIG_MTD_WMT_NOR
-static struct resource wmt_nor_resources[] = {
-	[0] = {
-		.start  = NOR_CTRL_CFG_BASE_ADDR,
-		.end    = NOR_CTRL_CFG_BASE_ADDR + 0x3FF,
-		.flags  = IORESOURCE_MEM,
-	},
-};
-
-static struct platform_device wmt_nor_device = {
-	.name           = "nor",
-	.id             = 0,
-	.num_resources  = ARRAY_SIZE(wmt_nor_resources),
-	.resource       = wmt_nor_resources,
-};
-#endif
-
-static struct resource wmt_nand_resources[] = {
-	[0] = {
-		.start  = NF_CTRL_CFG_BASE_ADDR,
-		.end    = NF_CTRL_CFG_BASE_ADDR + 0x3FF,
-		.flags  = IORESOURCE_MEM,
-	},
-};
-
-static u64 wmt_nand_dma_mask = 0xffffffffUL;
-
-static struct platform_device wmt_nand_device = {
-	.name           = "nand",
-	.id             = 0,
-	.dev            = {
-	.dma_mask 		= &wmt_nand_dma_mask,
-	.coherent_dma_mask = ~0,
-	},
-	.num_resources  = ARRAY_SIZE(wmt_nand_resources),
-	.resource       = wmt_nand_resources,
-};
-static struct resource wmt_i2s_resources[] = {
-    [0] = {
-		.start  = 0xD80ED800,
-		.end    = 0xD80EDBFF,
-		.flags  = IORESOURCE_MEM,
-    },
-};
-
-static struct resource wmt_pcm_resources[] = {
-    [0] = {
-		.start  = 0xD82D0000,
-		.end    = 0xD82D0000 + 0x4f,
-		.flags  = IORESOURCE_MEM,
-    },
-};
-static u64 wmt_i2s_dma_mask = 0xffffffffUL;
-static u64 wmt_pcm_dma_mask = 0xffffffffUL;
-
-static struct platform_device wmt_i2s_device = {
-	.name           = "wmt-i2s",
-	.id             = 0,
-	.dev            = {
-	.dma_mask 		= &wmt_i2s_dma_mask,
-	.coherent_dma_mask = ~0,
-	},
-	.num_resources  = ARRAY_SIZE(wmt_i2s_resources),
-	.resource       = wmt_i2s_resources,
-};
-
-static struct platform_device wmt_pcm_controller_device = {
-	.name           = "wmt-pcm-controller",
-	.id             = 0,
-	.dev            = {
-	.dma_mask 		= &wmt_pcm_dma_mask,
-	.coherent_dma_mask = ~0,
-	},
-	.num_resources  = ARRAY_SIZE(wmt_pcm_resources),
-	.resource       = wmt_pcm_resources,
-};
-
-static struct platform_device wmt_pcm_dma_device = {
-	.name           = "wmt-pcm-dma",
-	.id             = 0,
-};
-static struct platform_device wmt_aud_pcm_device = {
-	.name           = "wmt-audio-pcm",
-	.id             = 0,
-};
-
-static struct platform_device wmt_i2s_hwdac_device = {
-	.name           = "wmt-i2s-hwdac",
-	.id             = 0,
-};
-
-static struct platform_device wmt_switch_device = {
-	.name = "wmt-switch",
-	.id   = 0,
-};
-
-static struct resource wmt_pwm_resources[] = {
-    [0] = {
-		.start  = 0xD8220000,
-		.end    = 0xD8220000 + 0x44,
-		.flags  = IORESOURCE_MEM,
-    },
-};
-
-struct platform_device wm8880_device_pwm = {
-	.name		= "wm8880-pwm",
-	.id		= 0,
-	.num_resources     = ARRAY_SIZE(wmt_pwm_resources),
-	.resource          = wmt_pwm_resources,
-};
-
-#ifdef CONFIG_WMT_NEWSPI_SUPPORT
-static struct spi_board_info wmt_spi_board_info[] = {
-};
-#endif
-
-#ifdef CONFIG_WMT_NEWSPI1_SUPPORT
-static struct spi_board_info wmt_spi1_board_info[] = {
-};
-#endif
-
-#ifdef CONFIG_WMT_NEWSPI_SUPPORT
-static struct wmt_spi_hw wmt_spi_info = {
-	/* spi on wmt can support dma */
-	.dma_support       = SPI_DMA_ENABLE,
-	/* can support 4 slaves when WMT spi as master */
-	.num_chipselect    = MAX_SPI_SLAVE,
-	/* wmt spi support 16bits_per_word? i'm not sure */
-	.bits_per_word_en  = BITS8_PER_WORD_EN,
-	/* wmt spi can support multi-master also, but it seems we do not need it */
-	.port_mode         = PORT_MODE_PTP,
-	/* ssn driven low when enable */
-	.ssn_ctrl          = SSN_CTRL_HARDWARE,
-	/* actual 36bytes, but we use 32bytes */
-	.fifo_size         = SPI_FIFO_SIZE,
-	/* 4Kbytes, same as the DMA */
-	.max_transfer_length = SPI_MAX_TRANSFER_LENGTH,
-	/* it's really needed? i'm not sure   */
-	.min_freq_hz       = SPI_MIN_FREQ_HZ,
-	/* max freq 100Mhz */
-	.max_freq_hz       = SPI_MAX_FREQ_HZ,
-};
-
-static struct resource wmt_spi_resources[] = {
-	[0] = {
-		.start = SPI0_BASE_ADDR,
-		.end   = SPI0_BASE_ADDR + 0xFFFF,
-		.flags = IORESOURCE_MEM,
-	      },
-	[1] = {
-		.start = IRQ_SPI0,
-		.end   = IRQ_SPI0,
-		.flags = IORESOURCE_IRQ,
-	      },
-};
-
-static u64 wmt_spi_dma_mask = 0xFFFFFFFFUL;
-
-static struct platform_device wmt_spi_device = {
-	.name              = "wmt_spi_0",
-	.id                = 0,
-	.dev               = {
-		.dma_mask          = &wmt_spi_dma_mask,
-		.coherent_dma_mask = ~0,
-		.platform_data     = &wmt_spi_info,
-	},
-	.num_resources     = ARRAY_SIZE(wmt_spi_resources),
-	.resource          = wmt_spi_resources,
-};
-#endif
-
-#ifdef CONFIG_WMT_NEWSPI1_SUPPORT
-static struct wmt_spi_hw wmt_spi1_info = {
-	/* spi on wmt can support dma */
-	.dma_support       = SPI_DMA_ENABLE,
-	/* can support 4 slaves when wmt spi as master */
-	.num_chipselect    = MAX_SPI_SLAVE,
-	/* wmt spi support 16bits_per_word? i'm not sure */
-	.bits_per_word_en  = BITS8_PER_WORD_EN,
-	/* wmt spi can support multi-master also, but it seems we do not need it */
-	.port_mode         = PORT_MODE_PTP,
-	/* ssn driven low when enable */
-	.ssn_ctrl          = SSN_CTRL_HARDWARE,
-	/* actual 36bytes, but we use 32bytes */
-	.fifo_size         = SPI_FIFO_SIZE,
-	/* 4Kbytes, same as the DMA */
-	.max_transfer_length = SPI_MAX_TRANSFER_LENGTH,
-	/* it's really needed? i'm not sure   */
-	.min_freq_hz       = SPI_MIN_FREQ_HZ,
-	/* max freq 100Mhz */
-	.max_freq_hz       = SPI_MAX_FREQ_HZ,
-};
-
-static struct resource wmt_spi1_resources[] = {
-	[0] = {
-		.start = SPI1_BASE_ADDR,
-		.end   = SPI1_BASE_ADDR + 0x0000FFFF,
-		.flags = IORESOURCE_MEM,
-	      },
-	[1] = {
-		.start = IRQ_SPI1,
-		.end   = IRQ_SPI1,
-		.flags = IORESOURCE_IRQ,
-	      },
-};
-
-static u64 wmt_spi1_dma_mask = 0xFFFFFFFFUL;
-
-static struct platform_device wmt_spi1_device = {
-	.name              = "wmt_spi_1",
-	.id                = 1,
-	.dev               = {
-		.dma_mask          = &wmt_spi1_dma_mask,
-		.coherent_dma_mask = ~0,
-		.platform_data     = &wmt_spi1_info,
-	},
-	.num_resources     = ARRAY_SIZE(wmt_spi1_resources),
-	.resource          = wmt_spi1_resources,
-};
-#endif
-
-#ifdef CONFIG_DRM_MALI
-static struct platform_device wmt_mali_drm_device = {
-	.name = "mali_drm",
-	.id   = -1,
-};
-#endif
-
-#ifdef CONFIG_I2S_CODEC_WM8994
-static struct regulator_consumer_supply wm8994_fixed_voltage0_supplies[] = {
-	REGULATOR_SUPPLY("DBVDD", "4-001a"),
-	REGULATOR_SUPPLY("AVDD2", "4-001a"),
-	REGULATOR_SUPPLY("CPVDD", "4-001a"),
-};
-
-static struct regulator_consumer_supply wm8994_fixed_voltage1_supplies[] = {
-	REGULATOR_SUPPLY("SPKVDD1", "4-001a"),
-	REGULATOR_SUPPLY("SPKVDD2", "4-001a"),
-};
-
-static struct regulator_init_data wm8994_fixed_voltage0_init_data = {
-	.constraints = {
-		.always_on = 1,
-	},
-	.num_consumer_supplies	= ARRAY_SIZE(wm8994_fixed_voltage0_supplies),
-	.consumer_supplies	= wm8994_fixed_voltage0_supplies,
-};
-
-static struct regulator_init_data wm8994_fixed_voltage1_init_data = {
-	.constraints = {
-		.always_on = 1,
-	},
-	.num_consumer_supplies	= ARRAY_SIZE(wm8994_fixed_voltage1_supplies),
-	.consumer_supplies	= wm8994_fixed_voltage1_supplies,
-};
-
-static struct fixed_voltage_config wm8994_fixed_voltage0_config = {
-	.supply_name	= "VCC_1.8V_PDA",
-	.microvolts	= 1800000,
-	.gpio		= -EINVAL,
-	.init_data	= &wm8994_fixed_voltage0_init_data,
-};
-
-static struct fixed_voltage_config wm8994_fixed_voltage1_config = {
-	.supply_name	= "V_BAT",
-	.microvolts	= 3700000,
-	.gpio		= -EINVAL,
-	.init_data	= &wm8994_fixed_voltage1_init_data,
-};
-
-static struct platform_device wm8994_fixed_voltage0 = {
-	.name		= "reg-fixed-voltage",
-	.id		= 0,
-	.dev		= {
-		.platform_data	= &wm8994_fixed_voltage0_config,
-	},
-};
-
-static struct platform_device wm8994_fixed_voltage1 = {
-	.name		= "reg-fixed-voltage",
-	.id		= 1,
-	.dev		= {
-		.platform_data	= &wm8994_fixed_voltage1_config,
-	},
-};
-
-static struct regulator_consumer_supply wm8994_avdd1_supply =
-	REGULATOR_SUPPLY("AVDD1", "4-001a");
-
-static struct regulator_consumer_supply wm8994_dcvdd_supply =
-	REGULATOR_SUPPLY("DCVDD", "4-001a");
-
-static struct regulator_init_data wm8994_ldo1_data = {
-	.constraints	= {
-		.name		= "AVDD1_3.0V",
-	},
-	.num_consumer_supplies	= 1,
-	.consumer_supplies	= &wm8994_avdd1_supply,
-};
-
-static struct regulator_init_data wm8994_ldo2_data = {
-	.constraints	= {
-		.name		= "DCVDD_1.0V",
-	},
-	.num_consumer_supplies	= 1,
-	.consumer_supplies	= &wm8994_dcvdd_supply,
-};
-
-static struct wm8994_pdata wm8994_platform_data = {
-	/* configure gpio1 function for ADCLRCLK */
-	.gpio_defaults[0] = 0x0100,
-	/* configure gpio2 & gpio6 function for gpio */
-	.gpio_defaults[1] = 0x8101, // read-only
-	.gpio_defaults[5] = 0x0001, // output
-	/* configure gpio3/4/5/7 function for AIF2 voice */
-	.gpio_defaults[2] = 0x8100,
-	.gpio_defaults[3] = 0x8100,
-	.gpio_defaults[4] = 0x8100,
-	.gpio_defaults[6] = 0x0100,
-	/* configure gpio8/9/10/11 function for AIF3 BT */
-	.gpio_defaults[7] = 0x8100,
-	.gpio_defaults[8] = 0x0100,
-	.gpio_defaults[9] = 0x0100,
-	.gpio_defaults[10] = 0x0100,
-	.ldo[0]	= { 0, &wm8994_ldo1_data },	/* XM0FRNB_2 */
-	.ldo[1]	= { 0, &wm8994_ldo2_data },
-};
-
-static struct i2c_board_info wm8994_i2c_dev[] __initdata = {
-	{I2C_BOARD_INFO("wm8994", 0x1a), .platform_data	= &wm8994_platform_data,},
-};
-#endif
-
-
-#ifdef CONFIG_ISDBT_MTV23x
-static struct i2c_board_info isdbt_i2c_dev[] __initdata = {
-	{I2C_BOARD_INFO("isdbti2c", 0x43), .platform_data	= NULL,},
-};
-#endif
-
-#ifdef CONFIG_CACHE_L2X0
-extern int wmt_getsyspara(char *varname, unsigned char *varval, int *varlen);
-static	void __iomem *l2x0_base;
-static DEFINE_RAW_SPINLOCK(l2x0_lock);
-
-static void wmt_l2x0_disable(void)
-{
-	unsigned long flags;
-
-	raw_spin_lock_irqsave(&l2x0_lock, flags);
-//	__l2x0_flush_all();
-	wmt_smc(WMT_SMC_CMD_PL310CTRL, 0);
-	dsb();
-	raw_spin_unlock_irqrestore(&l2x0_lock, flags);
-}
-#endif
-
-static struct platform_device *wmt_devices[] __initdata = {
-	&wmt_uart0_device,
-	&wmt_uart1_device,
-#ifdef CONFIG_UART_2_3_ENABLE
-	&wmt_uart2_device,
-	&wmt_uart3_device,
-#endif
-	&wmt_sf_device,
-#ifdef CONFIG_MTD_WMT_NOR
-	&wmt_nor_device,
-#endif
-	&wmt_nand_device,
-	&wmt_i2s_device,
-	&wmt_pcm_controller_device,
-	&wmt_pcm_dma_device,
-	&wmt_aud_pcm_device,
-	&wmt_i2s_hwdac_device,
-//	&wmt_pcm_device,
-	&wmt_switch_device,
-#ifdef CONFIG_WMT_NEWSPI_SUPPORT
-	&wmt_spi_device,
-#endif
-#ifdef CONFIG_WMT_NEWSPI1_SUPPORT
-	&wmt_spi1_device,
-#endif
-#ifdef CONFIG_DRM_MALI
-	&wmt_mali_drm_device,
-#endif
-#ifdef CONFIG_I2S_CODEC_WM8994
-	&wm8994_fixed_voltage0,
-	&wm8994_fixed_voltage1,
-#endif
-	&wm8880_device_pwm,
-};
-
-#ifdef CONFIG_VT1603_IOCTRL_SPI
-static struct wmt_spi_slave vt1603_codec_info = {
-	.dma_en        = SPI_DMA_DISABLE,
-	.bits_per_word = 8,
-};
-static struct spi_board_info vt1603_spi_board_info[] __initdata = {
-	{
-		.modalias               = "vt1609",
-		.bus_num                = 0,
-		.chip_select            = 0,
-		.max_speed_hz           = 12000000,
-		.irq                    = -1,
-		.mode = SPI_CLK_MODE3,
-		.controller_data = &vt1603_codec_info,
-	},
-};
-#endif
-
-
-static struct i2c_board_info cp2682_i2c_dev[] __initdata = {
-	{I2C_BOARD_INFO("cp2682", (0x2c)),},
-};
-
-static char ns_printk_buf[1024];
-void sprintk(unsigned int buf, unsigned int len)
-{
-	local_irq_disable();
-        printk(ns_printk_buf);
-	wmt_smc(WMT_SMC_CMD_PRINTK_RET, 0);
-}
-void notify_log_buf()
-{
-	wmt_smc(WMT_SMC_CMD_LOGBUFOK, (unsigned int)sprintk);
-	wmt_smc(WMT_SMC_CMD_LOGBUF_ADDR, (unsigned int)virt_to_phys(ns_printk_buf));
-}
-
-static void wmt_default_idle(void)
-{
-	if (!need_resched()) {
-		asm("dsb");
-		asm("wfi");
-	}
-	local_irq_enable();
-}
-static int __init wmt_init(void)
-{
-	/* Add for enable user access to pmu */
-	unsigned char buf[40];
-	int varlen=40;
-	unsigned int pmu_param;
-	int ret = 0;
-	int vt1603_spi = 0; //0-->spi, 1-->i2c
-	/* Add End */
-
-#ifdef CONFIG_CACHE_L2X0
-	__u32 power_ctrl = 0;
-	unsigned int onoff = 0;
-	unsigned int aux = 0x3E440000;
-	unsigned int prefetch_ctrl = 0x70000007;
-	unsigned int en_static_address_filtering = 0;
-	unsigned int address_filtering_start = 0xD8000000;
-	unsigned int address_filtering_end = 0xD9000000;
-	unsigned int cpu_trustzone_enabled = 0;
-	unsigned long flags;
-#endif
-
-	wmt_gpio_init();
-
-	pm_power_off = wmt_power_off;
-	pm_idle = wmt_default_idle;
-	arm_pm_restart = wmt_restart;
-
-#ifdef CONFIG_WMT_NEWSPI_SUPPORT
-	spi_register_board_info(wmt_spi_board_info, ARRAY_SIZE(wmt_spi_board_info));
-#endif
-#ifdef CONFIG_WMT_NEWSPI1_SUPPORT
-	spi_register_board_info(wmt_spi1_board_info, ARRAY_SIZE(wmt_spi1_board_info));
-#endif
-#ifdef CONFIG_VT1603_IOCTRL_SPI
-	memset(buf, 0, sizeof(buf));
-	ret = wmt_getsyspara("wmt.vt1603.bus", buf, &varlen);
-	
-	if (!ret)
-	{
-		sscanf(buf, "%d", &vt1603_spi); // 0-->spi, 1-->i2c
-		
-	}
-	if (
-	    (!vt1603_spi) &&  // 0-->spi, 1-->i2c
-	    ((!wmt_getsyspara("wmt.audio.i2s", buf, &varlen) &&
-	     (!strncmp(buf, "vt1603", 6) || !strncmp(buf, "vt1609", 6))) ||	/* audio */
-
-	    (!wmt_getsyspara("wmt.battery.param", buf, &varlen) && 		/* battery */
-	     (!strncmp(buf, "vt1603", 6) || !strncmp(buf, "vt1609", 6))))
-	     )
-	{
-
-		spi_register_board_info(vt1603_spi_board_info,
-					ARRAY_SIZE(vt1603_spi_board_info));
-	}
-#endif
-
-#ifdef CONFIG_I2S_CODEC_WM8994
-	i2c_register_board_info(4, wm8994_i2c_dev, ARRAY_SIZE(wm8994_i2c_dev));
-#endif
-
-#ifdef CONFIG_ISDBT_MTV23x
-	i2c_register_board_info(4, isdbt_i2c_dev, ARRAY_SIZE(isdbt_i2c_dev));
-#endif
-
-#ifdef CONFIG_CACHE_L2X0
-	if (wmt_getsyspara("wmt.l2c.param",buf,&varlen) == 0)
-		sscanf(buf,"%d:%x:%x:%d:%x:%x",&onoff, &aux, &prefetch_ctrl, &en_static_address_filtering, &address_filtering_start, &address_filtering_end);
-
-	if (wmt_getsyspara("wmt.secure.param",buf,&varlen) == 0)
-		sscanf(buf,"%d",&cpu_trustzone_enabled);
-	if(cpu_trustzone_enabled != 1)
-		cpu_trustzone_enabled = 0;
-
-	if (onoff == 1) {
-		l2x0_base = ioremap(0xD9000000, SZ_4K);
-
-
-		if(cpu_trustzone_enabled == 0)
-		{
-			if (en_static_address_filtering == 1) {
-				writel_relaxed(address_filtering_end, l2x0_base + 0xC04);
-				writel_relaxed((address_filtering_start | 0x01), l2x0_base + 0xC00);
-			}
-			
-			writel_relaxed(0x110, l2x0_base + L2X0_TAG_LATENCY_CTRL);
-			writel_relaxed(0x110, l2x0_base + L2X0_DATA_LATENCY_CTRL);
-	
-			power_ctrl = readl_relaxed(l2x0_base + L2X0_POWER_CTRL) | L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN;
-			writel_relaxed(power_ctrl, l2x0_base + L2X0_POWER_CTRL);        
-	
-			writel_relaxed(prefetch_ctrl, l2x0_base + L2X0_PREFETCH_CTRL);         
-		}
-		else
-		{
-			if (en_static_address_filtering == 1) {
-				wmt_smc(WMT_SMC_CMD_PL310FILTER_END, address_filtering_end);
-				wmt_smc(WMT_SMC_CMD_PL310FILTER_START, (address_filtering_start | 0x01));
-			}
-
-			wmt_smc(WMT_SMC_CMD_PL310TAG_LATENCY, 0x110);
-			wmt_smc(WMT_SMC_CMD_PL310DATA_LATENCY, 0x110);
-			power_ctrl = readl_relaxed(l2x0_base + L2X0_POWER_CTRL) | L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN;
-			wmt_smc(WMT_SMC_CMD_PL310POWER, power_ctrl);
-
-			wmt_smc(WMT_SMC_CMD_PL310PREFETCH, prefetch_ctrl);
-
-			raw_spin_lock_irqsave(&l2x0_lock, flags);
-			writel_relaxed(0xffff, l2x0_base + L2X0_INV_WAY);
-			while ( readl_relaxed(l2x0_base + L2X0_INV_WAY)  & 0xffff)
-				cpu_relax();
-			writel_relaxed(0, l2x0_base + L2X0_CACHE_SYNC);
-			raw_spin_unlock_irqrestore(&l2x0_lock, flags);
-			
-			/* enable L2X0 */
-			wmt_smc(WMT_SMC_CMD_PL310CTRL, 1);
-		}
-
-		/* 512KB (32KB/way) 16-way associativity */
-		l2x0_init(l2x0_base, aux, 0);
-		
-		if(cpu_trustzone_enabled != 0)
-			outer_cache.disable = wmt_l2x0_disable;
-	}
-#endif
-
-#ifdef CONFIG_MTD_WMT_SF
-/* Add for enable user access to ARM11 performance monitor */
-	if(wmt_getsyspara("wmt.pmu.param",buf,&varlen) == 0)
-		sscanf(buf,"%d",&pmu_param );         
-	if(pmu_param & 0x1){
-		//enable_user_access();
-	}
-#endif
-/* Add End */
-
-	if(cpu_trustzone_enabled == 1)
-		notify_log_buf();//Lch for SecureOS_printk
-	return platform_add_devices(wmt_devices, ARRAY_SIZE(wmt_devices));
-}
-
-
-arch_initcall(wmt_init);
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/generic.h b/ANDROID_3.4.5/arch/arm/mach-wmt/generic.h
deleted file mode 100755
index 14ed9764..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/generic.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*++
-linux/arch/arm/mach-wmt/generic.h
-
-Copyright (c) 2008  WonderMedia Technologies, Inc.
-
-This program is free software: you can redistribute it and/or modify it under the
-terms of the GNU General Public License as published by the Free Software Foundation,
-either version 2 of the License, or (at your option) any later version.
-
-This program is distributed in the hope that it will be useful, but WITHOUT
-ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-PARTICULAR PURPOSE.  See the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License along with
-this program.  If not, see <http://www.gnu.org/licenses/>.
-
-WonderMedia Technologies, Inc.
-10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
---*/
-
-#ifndef __wmt_GENERIC_H
-#define __wmt_GENERIC_H
-
-extern void __init wmt_init_irq(void);
-
-#define SET_BANK(__nr, __start, __size) \
-					mi->bank[__nr].start = (__start), \
-					mi->bank[__nr].size = (__size), \
-					mi->bank[__nr].node = (((unsigned)(__start) - PHYS_OFFSET) >> 27)
-
-/*
- * CPUFreq interface
- */
-struct cpufreq_policy;
-
-/*
- * System clocks interface
- */
-extern unsigned int wmt_arm_khz(void);
-extern unsigned int wmt_ahb_khz(void);
-
-#endif  /* __wmt_GENERIC_H */
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/gpio.c b/ANDROID_3.4.5/arch/arm/mach-wmt/gpio.c
deleted file mode 100755
index 7558c137..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/gpio.c
+++ /dev/null
@@ -1,614 +0,0 @@
-/* linux/arch/arm/mach-wmt/gpio.c
- *
- * Copyright (c) 2013 WonderMedia Technologies, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#include <linux/module.h>
-#include <linux/device.h>
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <linux/seq_file.h>
-#include <linux/kobject.h>
-#include <linux/debugfs.h>
-
-#include <mach/hardware.h>
-#include <mach/wmt_iomux.h>
-
-#undef	WMT_PIN
-#define WMT_PIN(__gp, __bit, __irq, __name)	\
-	{ .label = #__name, .regoff = __gp, .shift = __bit, .irqnum = __irq },
-
-const static struct wmt_gpio {
-	const char *label;
-	unsigned char regoff;
-	unsigned char shift;
-	int irqnum;
-} wmt_gpios[] = {
-	#include <mach/iomux.h>
-};
-
-#define to_wmt(__chip)	container_of(__chip, struct wmt_gpio_port, chip)
-
-struct wmt_gpio_port {
-	uint32_t base;
-	uint32_t gpio_irq_no_base;
-	int gpio_irq_nr;
-	struct gpio_chip chip;
-	spinlock_t lock;
-};
-
-static struct wmt_gpio_port wmt_gpio_port;
-
-#define INVALUE_REGS		0x00
-#define ENABLE_REGS		0x40
-#define DIRECTION_REGS		0x80
-#define OUTVALUE_REGS		0xc0
-
-#define INTMASK_REGS		0x300
-#define INTSTAT_REGS		0x360
-
-#define PULLENABLE_REGS		0x480
-#define PULLCONTROL_REGS	0x4c0
-
-#define GPIO_INT_LOW_LEV	0x0
-#define GPIO_INT_HIGH_LEV	0x1
-#define GPIO_INT_FALL_EDGE	0x2
-#define GPIO_INT_RISE_EDGE	0x3
-#define GPIO_INT_BOTH_EDGE	0x4
-
-#define CHIP_GPIO_BASE	0
-
-static void _clear_gpio_irqstatus(u32 irqindex)
-{
-	struct wmt_gpio_port *port = &wmt_gpio_port;
-	u32 addr = port->base + INTSTAT_REGS + (irqindex >> 3);
-	u8 index = irqindex & 0x7;
-
-	__raw_writeb(1 << index, addr);
-}
-
-static int _gpio_irqstatus(u32 irqindex)
-{
-	u8 l;
-	struct wmt_gpio_port *port = &wmt_gpio_port;
-	u32 addr = port->base + INTSTAT_REGS + (irqindex >> 3);
-	u8 index = irqindex & 0x7;
-	l = __raw_readb(addr);
-	return l & (1<<index);
-}
-
-int gpio_irqstatus(unsigned int gpio)
-{
-	int offset = gpio - CHIP_GPIO_BASE;
-	int irqindex = wmt_gpios[offset].irqnum;	
-	return _gpio_irqstatus(irqindex);
-}
-EXPORT_SYMBOL(gpio_irqstatus);
-
-static void _set_gpio_irqenable(u32 irqindex, int enable)
-{
-	struct wmt_gpio_port *port = &wmt_gpio_port;
-	u32 addr = port->base + INTMASK_REGS + irqindex;
-	u8 l;
-
-	l = __raw_readb(addr);
-	l = (l & 0x7f) | (!!enable << 7);
-	__raw_writeb(l, addr);
-}
-
-int is_gpio_irqenable(unsigned int gpio)
-{
-	u8 l;
-	int offset = gpio - CHIP_GPIO_BASE;
-	int irqindex = wmt_gpios[offset].irqnum;
-	struct wmt_gpio_port *port = &wmt_gpio_port;
-	u32 addr = port->base + INTMASK_REGS + irqindex;
-	
-	l = __raw_readb(addr);
-	return (l & 0x80);
-}
-EXPORT_SYMBOL(is_gpio_irqenable);
-
-void wmt_gpio_ack_irq(unsigned int gpio)
-{
-	int offset = gpio - CHIP_GPIO_BASE;
-	int irqindex = wmt_gpios[offset].irqnum;
-
-	_clear_gpio_irqstatus(irqindex);
-}
-EXPORT_SYMBOL(wmt_gpio_ack_irq);
-
-void wmt_gpio_mask_irq(unsigned int gpio)
-{
-	int offset = gpio - CHIP_GPIO_BASE;
-	int irqindex = wmt_gpios[offset].irqnum;
-
-	_set_gpio_irqenable(irqindex, 0);
-}
-EXPORT_SYMBOL(wmt_gpio_mask_irq);
-
-void wmt_gpio_unmask_irq(unsigned int gpio)
-{
-	int offset = gpio - CHIP_GPIO_BASE;
-	int irqindex = wmt_gpios[offset].irqnum;
-
-	_set_gpio_irqenable(irqindex, 1);
-}
-EXPORT_SYMBOL(wmt_gpio_unmask_irq);
-
-int wmt_gpio_set_irq_type(unsigned int gpio, u32 type)
-{
-	struct wmt_gpio_port *port = &wmt_gpio_port;
-	int offset = gpio - CHIP_GPIO_BASE;
-	int irqindex = wmt_gpios[offset].irqnum;
-	int edge;
-	u32 reg, val;
-
-	switch (type) {
-	case IRQ_TYPE_EDGE_RISING:
-		edge = GPIO_INT_RISE_EDGE;
-		break;
-	case IRQ_TYPE_EDGE_FALLING:
-		edge = GPIO_INT_FALL_EDGE;
-		break;
-	case IRQ_TYPE_EDGE_BOTH:
-		edge = GPIO_INT_BOTH_EDGE;
-		break;
-	case IRQ_TYPE_LEVEL_LOW:
-		edge = GPIO_INT_LOW_LEV;
-		break;
-	case IRQ_TYPE_LEVEL_HIGH:
-		edge = GPIO_INT_HIGH_LEV;
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	reg  = port->base + INTMASK_REGS + irqindex;
-	val = __raw_readb(reg) & 0xf8;
-	__raw_writeb(val | edge, reg);
-
-	_clear_gpio_irqstatus(irqindex);
-
-	return 0;
-}
-EXPORT_SYMBOL(wmt_gpio_set_irq_type);
-
-#ifdef WMT_GPIO_IRQ
-static void gpio_ack_irq(struct irq_data *d)
-{
-	struct wmt_gpio_port *port = &wmt_gpio_port;
-	int irqindex = d->irq - port->gpio_irq_no_base;
-
-	_clear_gpio_irqstatus(irqindex);
-}
-
-static void gpio_mask_irq(struct irq_data *d)
-{
-	struct wmt_gpio_port *port = &wmt_gpio_port;
-	int irqindex = d->irq - port->gpio_irq_no_base;
-
-	_set_gpio_irqenable(irqindex, 0);
-}
-
-static void gpio_unmask_irq(struct irq_data *d)
-{
-	struct wmt_gpio_port *port = &wmt_gpio_port;
-	int irqindex = d->irq - port->gpio_irq_no_base;
-
-	_set_gpio_irqenable(irqindex, 1);
-}
-
-static int gpio_set_irq_type(struct irq_data *d, u32 type)
-{
-	struct wmt_gpio_port *port = &wmt_gpio_port;
-	int edge, irqindex;
-	u32 reg, val;
-
-	switch (type) {
-	case IRQ_TYPE_EDGE_RISING:
-		edge = GPIO_INT_RISE_EDGE;
-		break;
-	case IRQ_TYPE_EDGE_FALLING:
-		edge = GPIO_INT_FALL_EDGE;
-		break;
-	case IRQ_TYPE_EDGE_BOTH:
-		edge = GPIO_INT_BOTH_EDGE;
-		break;
-	case IRQ_TYPE_LEVEL_LOW:
-		edge = GPIO_INT_LOW_LEV;
-		break;
-	case IRQ_TYPE_LEVEL_HIGH:
-		edge = GPIO_INT_HIGH_LEV;
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	irqindex = d->irq - port->gpio_irq_no_base;
-	reg  = port->base + INTMASK_REGS + irqindex;
-	val = __raw_readb(reg) & 0xf8;
-	__raw_writeb(val | edge, reg);
-
-	_clear_gpio_irqstatus(irqindex);
-
-	return 0;
-}
-
-/* WMT has one interrupt *for all* gpio ports */
-static void wmt_gpio_irq_handler(u32 irq, struct irq_desc *desc)
-{
-	int i;
-	u32 irq_msk, irq_stat;
-	struct wmt_gpio_port *port = &wmt_gpio_port;
-
-	/* walk through all interrupt status registers */
-	for (i = 0; i < 4; i++) {
-		irq_msk = __raw_readl(port->base + INTMASK_REGS + i*4);
-		if (!irq_msk)
-			continue;
-
-		irq_stat = __raw_readl(port->base + INTSTAT_REGS + i*4) & irq_msk;
-		while (irq_stat != 0) {
-			int irqoffset = fls(irq_stat) - 1;
-
-			generic_handle_irq(port->gpio_irq_no_base + i*32 + irqoffset);
-
-			irq_stat &= ~(1 << irqoffset);
-		}
-	}
-}
-
-static struct irq_chip gpio_irq_chip = {
-	.name = "GPIO",
-	.irq_ack = gpio_ack_irq,
-	.irq_mask = gpio_mask_irq,
-	.irq_unmask = gpio_unmask_irq,
-	.irq_set_type = gpio_set_irq_type,
-};
-#endif
-
-static int wmt_gpio_request(struct gpio_chip *chip, unsigned offset)
-{
-	struct wmt_gpio_port *port = to_wmt(chip);
-	uint32_t base = port->base;
-	uint8_t regoff = wmt_gpios[offset].regoff;
-	uint8_t shift  = wmt_gpios[offset].shift;
-	uint8_t val;
-
-	unsigned long flags;
-
-	spin_lock_irqsave(&port->lock, flags);
-
-	WARN_ON(offset >= ARRAY_SIZE(wmt_gpios));
-
-	val = readb(base + ENABLE_REGS + regoff);
-	val |= (1 << shift);
-	writeb(val, base + ENABLE_REGS + regoff);
-
-	spin_unlock_irqrestore(&port->lock, flags);
-	return 0;
-}
-
-static void wmt_gpio_free(struct gpio_chip *chip, unsigned offset)
-{
-	struct wmt_gpio_port *port = to_wmt(chip);
-//	uint32_t base = port->base;
-//	uint8_t regoff = wmt_gpios[offset].regoff;
-//	uint8_t shift  = wmt_gpios[offset].shift;
-//	uint8_t val;
-
-	unsigned long flags;
-
-	spin_lock_irqsave(&port->lock, flags);
-
-	WARN_ON(offset >= ARRAY_SIZE(wmt_gpios));
-
-//	val = readb(base + ENABLE_REGS + regoff);
-//	val &= ~(1 << shift);
-//	writeb(val, base + ENABLE_REGS + regoff);
-
-	spin_unlock_irqrestore(&port->lock, flags);
-}
-
-static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset, int dir)
-{
-	struct wmt_gpio_port *port = to_wmt(chip);
-	uint32_t base = port->base;
-	uint8_t regoff = wmt_gpios[offset].regoff;
-	uint8_t shift  = wmt_gpios[offset].shift;
-	uint8_t val;
-	unsigned long flags;
-
-	spin_lock_irqsave(&port->lock, flags);
-
-	WARN_ON(offset >= ARRAY_SIZE(wmt_gpios));
-
-	val = readb(base + DIRECTION_REGS + regoff);
-	if (dir)
-		val |= (1 << shift);
-	else
-		val &= ~(1 << shift);
-	writeb(val, base + DIRECTION_REGS + regoff);
-
-	spin_unlock_irqrestore(&port->lock, flags);
-}
-
-static int wmt_gpio_get_value(struct gpio_chip *chip, unsigned offset)
-{
-	struct wmt_gpio_port *port = to_wmt(chip);
-	uint32_t base = port->base;
-	uint8_t regoff = wmt_gpios[offset].regoff;
-	uint8_t shift  = wmt_gpios[offset].shift;
-	uint8_t val;
-	int dir;
-
-	WARN_ON(offset >= ARRAY_SIZE(wmt_gpios));
-
-	val = readb(base + DIRECTION_REGS + regoff);
-	dir = (val >> shift) & 1;
-
-	if (dir)
-		return (readb(base + OUTVALUE_REGS + regoff) >> shift) & 1;
-	else
-		return (readb(base + INVALUE_REGS + regoff) >> shift) & 1;
-}
-
-static void wmt_gpio_set_value(struct gpio_chip *chip,
-			       unsigned offset, int value)
-{
-	struct wmt_gpio_port *port = to_wmt(chip);
-	uint32_t base = port->base;
-	uint8_t regoff = wmt_gpios[offset].regoff;
-	uint8_t shift  = wmt_gpios[offset].shift;
-	uint8_t val;
-	unsigned long flags;
-
-	spin_lock_irqsave(&port->lock, flags);
-
-	WARN_ON(offset >= ARRAY_SIZE(wmt_gpios));
-
-	val = readb(base + OUTVALUE_REGS + regoff);
-
-	if (value)
-		val |= (1 << shift);
-	else
-		val &= ~(1 << shift);
-
-	writeb(val, base + OUTVALUE_REGS + regoff);
-
-	spin_unlock_irqrestore(&port->lock, flags);
-}
-
-static int wmt_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
-{
-	_set_gpio_direction(chip, offset, 0);
-	return 0;
-}
-
-static int wmt_gpio_direction_output(struct gpio_chip *chip,
-				     unsigned offset, int value)
-{
-	wmt_gpio_set_value(chip, offset, value);
-	_set_gpio_direction(chip, offset, 1);
-	return 0;
-}
-
-static void _set_gpio_pullenable(unsigned offset, int enable)
-{
-	struct wmt_gpio_port *port = &wmt_gpio_port;
-	uint32_t base = port->base;
-	uint8_t regoff = wmt_gpios[offset].regoff;
-	uint8_t shift  = wmt_gpios[offset].shift;
-	uint8_t val;
-	unsigned long flags;
-
-	spin_lock_irqsave(&port->lock, flags);
-
-	WARN_ON(offset >= ARRAY_SIZE(wmt_gpios));
-
-	val = readb(base + PULLENABLE_REGS + regoff);
-	if (enable)
-		val |= (1 << shift);
-	else
-		val &= ~(1 << shift);
-	writeb(val, base + PULLENABLE_REGS + regoff);
-
-	spin_unlock_irqrestore(&port->lock, flags);
-}
-
-static void _set_gpio_pullup(unsigned offset, int up)
-{
-	struct wmt_gpio_port *port = &wmt_gpio_port;
-	uint32_t base = port->base;
-	uint8_t regoff = wmt_gpios[offset].regoff;
-	uint8_t shift  = wmt_gpios[offset].shift;
-	uint8_t val;
-	unsigned long flags;
-
-	spin_lock_irqsave(&port->lock, flags);
-
-	WARN_ON(offset >= ARRAY_SIZE(wmt_gpios));
-
-	val = readb(base + PULLCONTROL_REGS + regoff);
-	if (up)
-		val |= (1 << shift);
-	else
-		val &= ~(1 << shift);
-	writeb(val, base + PULLCONTROL_REGS + regoff);
-
-	spin_unlock_irqrestore(&port->lock, flags);
-}
-
-int wmt_gpio_setpull(unsigned int gpio, enum wmt_gpio_pulltype pull)
-{
-	int offset = gpio - CHIP_GPIO_BASE;
-
-	switch (pull) {
-	case WMT_GPIO_PULL_NONE:
-		_set_gpio_pullenable(offset, 0);
-		break;
-	case WMT_GPIO_PULL_UP:
-		_set_gpio_pullenable(offset, 1);
-		_set_gpio_pullup(offset, 1);
-		break;
-	case WMT_GPIO_PULL_DOWN:
-		_set_gpio_pullenable(offset, 1);
-		_set_gpio_pullup(offset, 0);
-		break;
-	default:
-		return -EINVAL;
-	}
-	return 0;
-}
-
-static int _get_gpio_pull(unsigned offset)
-{
-	struct wmt_gpio_port *port = &wmt_gpio_port;
-	uint32_t base = port->base;
-	uint8_t regoff = wmt_gpios[offset].regoff;
-	uint8_t shift  = wmt_gpios[offset].shift;
-	uint8_t val;
-	int dir;
-
-	WARN_ON(offset >= ARRAY_SIZE(wmt_gpios));
-
-	val = readb(base + DIRECTION_REGS + regoff);
-	dir = (val >> shift) & 1;
-
-	if (dir)
-		return (readb(base + OUTVALUE_REGS + regoff) >> shift) & 1;
-	else
-		return (readb(base + INVALUE_REGS + regoff) >> shift) & 1;
-}
-
-
-int wmt_gpio_getpull(unsigned int gpio)
-{
-	int offset = gpio - CHIP_GPIO_BASE;
-
-	return _get_gpio_pull(offset);
-}
-
-EXPORT_SYMBOL(wmt_gpio_setpull);
-EXPORT_SYMBOL(wmt_gpio_getpull);
-
-#ifdef WMT_GPIO_IRQ
-static int wmt_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
-{
-	struct wmt_gpio_port *port = &wmt_gpio_port;
-
-	WARN_ON(offset >= ARRAY_SIZE(wmt_gpios));
-
-	if (wmt_gpios[offset].irqnum < 0)
-		return -EINVAL;
-
-	return port->gpio_irq_no_base + wmt_gpios[offset].irqnum;
-}
-#endif
-
-static struct wmt_gpio_port wmt_gpio_port = {
-	.base = GPIO_BASE_ADDR,
-#ifdef WMT_GPIO_IRQ
-	.gpio_irq_no_base = WMT_GPIO_IRQ_START,
-	.gpio_irq_nr = WMT_GPIO_IRQS,
-#endif
-	.chip = {
-		.label			= "wmt-gpio",
-		.direction_input	= wmt_gpio_direction_input,
-		.direction_output	= wmt_gpio_direction_output,
-		.request		= wmt_gpio_request,
-		.free			= wmt_gpio_free,
-		.get			= wmt_gpio_get_value,
-		.set			= wmt_gpio_set_value,
-#ifdef WMT_GPIO_IRQ
-		.to_irq			= wmt_gpio_to_irq,
-#endif
-		.can_sleep		= 0,
-		.base			= CHIP_GPIO_BASE,
-		.ngpio			= ARRAY_SIZE(wmt_gpios),
-	},
-};
-
-void __init wmt_gpio_init(void)
-{
-#ifdef WMT_GPIO_IRQ
-	int irq;
-#endif
-
-	spin_lock_init(&wmt_gpio_port.lock);
-	BUG_ON(gpiochip_add(&wmt_gpio_port.chip) < 0);
-
-	/* XXX conflict with touchscreen irq */
-#ifdef WMT_GPIO_IRQ
-	for (irq = wmt_gpio_port.gpio_irq_no_base;
-	     irq < wmt_gpio_port.gpio_irq_no_base + wmt_gpio_port.gpio_irq_nr;
-	     irq++) {
-		irq_set_chip_and_handler(irq, &gpio_irq_chip, handle_level_irq);
-		set_irq_flags(irq, IRQF_VALID);
-	}
-
-	irq_set_chained_handler(IRQ_GPIO, wmt_gpio_irq_handler);
-#endif
-}
-
-const char *wmt_gpio_name(int gpio)
-{
-	if (gpio >= ARRAY_SIZE(wmt_gpios)) {
-		pr_err("wmt: can not find gpio-%d\n", gpio);
-		return NULL;
-	}
-
-	return wmt_gpios[gpio].label;
-}
-
-#ifdef CONFIG_DEBUG_FS
-
-static int wmt_gpio_show(struct seq_file *s, void *unused)
-{
-	unsigned i;
-
-	seq_printf(s, "GPIONUM  , REGOFF , SHIFT , MACRO NAME\n");
-	seq_printf(s, "---------+--------+-------+-----------\n");
-
-	for (i = 0; i < wmt_gpio_port.chip.ngpio; i++) {
-		seq_printf(s, "gpio-%-3d ,  0x%02x  ,    %d  , %s",
-			   i, wmt_gpios[i].regoff, wmt_gpios[i].shift, wmt_gpios[i].label);
-		seq_printf(s, "\n");
-	}
-	return 0;
-}
-
-static int wmt_gpio_open(struct inode *inode, struct file *file)
-{
-	return single_open(file, wmt_gpio_show, NULL);
-}
-
-static const struct file_operations wmt_gpio_operations = {
-	.open		= wmt_gpio_open,
-	.read		= seq_read,
-	.llseek		= seq_lseek,
-	.release	= single_release,
-};
-
-static int __init wmt_gpio_debugfs_init(void)
-{
-	/* /sys/kernel/debug/wmt-gpio */
-	(void) debugfs_create_file("wmt-gpio", S_IFREG | S_IRUGO,
-				   NULL, NULL, &wmt_gpio_operations);
-	return 0;
-}
-subsys_initcall(wmt_gpio_debugfs_init);
-
-#endif	/* DEBUG_FS */
-
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/gpio_ctrl.c b/ANDROID_3.4.5/arch/arm/mach-wmt/gpio_ctrl.c
deleted file mode 100755
index 8c1c2d76..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/gpio_ctrl.c
+++ /dev/null
@@ -1,202 +0,0 @@
-/*

- *  procfs1.c -  create a "file" in /proc

- *

- */

-#include <linux/module.h>	/* Specifically, a module */

-#include <linux/kernel.h>	/* We're doing kernel work */

-#include <linux/proc_fs.h>	/* Necessary because we use the proc fs */

-#include <linux/gpio.h>

-#include <mach/wmt_iomux.h>

-#include <asm/uaccess.h>   //for copy_from_user

-#include <linux/delay.h> // for mdelay

-

-#define DRIVER_AUTHOR		"rubbitxiao "

-#define DRIVER_DESC		"printer power control"

-

-

-#define procfs_name "gpio_ctrl"

-

-extern int wmt_getsyspara(char *varname, unsigned char *varval, int *varlen);

-extern struct proc_dir_entry proc_root;

-/**

- * This structure hold information about the /proc file

- *

- */

-static struct proc_dir_entry *Our_Proc_File;

-

-int power_on = -1;  //control printer power on/off

-int lid_stat = -1;  //inflext printer lid open or close status

-

-enum{

-	LOW=0,

-	HIGH,

-};

-

-/* Put data into the proc fs file.

- * 

- * Arguments

- * =========

- * 1. The buffer where the data is to be inserted, if

- *    you decide to use it.

- * 2. A pointer to a pointer to characters. This is

- *    useful if you don't want to use the buffer

- *    allocated by the kernel.

- * 3. The current position in the file

- * 4. The size of the buffer in the first argument.

- * 5. Write a "1" here to indicate EOF.

- * 6. A pointer to data (useful in case one common 

- *    read for multiple /proc/... entries)

- *

- * Usage and Return Value

- * ======================

- * A return value of zero means you have no further

- * information at this time (end of file). A negative

- * return value is an error condition.

- *

- * For More Information

- * ====================

- * The way I discovered what to do with this function

- * wasn't by reading documentation, but by reading the

- * code which used it. I just looked to see what uses

- * the get_info field of proc_dir_entry struct (I used a

- * combination of find and grep, if you're interested),

- * and I saw that  it is used in <kernel source

- * directory>/fs/proc/array.c.

- *

- * If something is unknown about the kernel, this is

- * usually the way to go. In Linux we have the great

- * advantage of having the kernel source code for

- * free - use it.

- */

-static int

-procfile_read(char *buffer,

-	      char **buffer_location,

-	      off_t offset, int buffer_length, int *eof, void *data)

-{

-	int ret;

-	int value = -1;

-	

-	if (offset > 0) {

-		/* we have finished to read, return 0 */

-		ret  = 0;

-	} else {

-		if(lid_stat >=0){

-			gpio_direction_input(lid_stat);

-			value = __gpio_get_value(lid_stat);

-			/* fill the buffer, return the buffer size */

-			ret = sprintf(buffer,"%d",value);

-		}else{

-			printk("err! have not set wmt.gpo.printer uboot variant\n");

-			ret = -1;

-		}

-	}

-

-	return ret;

-}

-

-

-static int procfile_write(struct file *file, const char __user *buffer,

-			   unsigned long count, void *data)

-{

-	int ret = 0;

-	char tmp[128];

-	int num;

-

-	int on = 0;

-	

-	if(buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) {

-

-		num = sscanf(tmp, "%d", &on);				

-		printk("your input power on/off:%d\n",on);

-		if(power_on<0){

-			printk("err! have not set wmt.gpo.printer uboot variant\n");

-			return -1;

-		}

-		if(on){	

-			gpio_direction_output(power_on, HIGH);

-			mdelay(200);

-			printk("power on printer\n");

-		}else{

-			gpio_direction_output(power_on, LOW);

-			printk("power off printer\n");

-		}	

-				

-		return strlen(tmp);

-	}else{

-		printk("copy_from_user failed or buffer is null\n");

-		return -1;

-	}

-}	

-

-

-static int __init wifi_proc_init(void)

-{

-	int retval = 0;

-	int varlen = 127;                                                                                                       

-    char buf[200]={0};      

-

-	Our_Proc_File = create_proc_entry(procfs_name, 0644, NULL);

-	

-	if (Our_Proc_File == NULL) {

-		remove_proc_entry(procfs_name, NULL);

-		printk(KERN_ALERT "Error: Could not initialize /proc/%s\n",

-		       procfs_name);

-		return -ENOMEM;

-	}

-	/*

-	*  wmt.gpo.printer format as follows:

-	*   power_on:lid_stat

-	*  for example: setenv wmt.gpo.printer 153:3

-	*    gpio8 for power on; gpio9 for lid status

-	*/

-	retval = wmt_getsyspara("wmt.gpo.printer", buf, &varlen);                   

-	if(!retval)                                                              

-	{                                                                          

-		sscanf(buf, "%d:%d",&power_on,&lid_stat);    			                                                			                                                                                                                                               

-		printk("power_on:%d,lid_stat:%d\n", power_on,lid_stat);    

-		//request gpio for printer power control

-		retval = gpio_request(power_on, "printer power pin");

-		if(retval < 0) {

-			printk("reques gpio:%x failed!!! for printer power pin\n",power_on);

-			return -1;

-		}else{

-			printk("request gpio:%d for printer power pin success!!!\n", power_on);			

-		}

-		//request gpio for printer lid status

-		retval = gpio_request(lid_stat, "printer lid status");

-		if(retval < 0) {

-			printk("reques gpio:%x failed!!! for printer lid status\n",lid_stat);

-			return -1;

-		}else{

-			printk("request gpio:%d for printer lid status success!!!\n", lid_stat);			

-		}

-	}else{

-		printk("have not set wmt.gpo.printer");

-	}

-	

-	Our_Proc_File->read_proc = procfile_read;

-	Our_Proc_File->write_proc = procfile_write;

-	Our_Proc_File->mode 	 = S_IFREG | S_IRUGO;

-	Our_Proc_File->uid 	 = 0;

-	Our_Proc_File->gid 	 = 0;

-	Our_Proc_File->size 	 = 37;

-

-	return 0;	/* everything is ok */

-}

-

-static void __exit wifi_proc_uninit(void)

-{

-	remove_proc_entry(procfs_name, NULL);

-	if(power_on)

-		gpio_free(power_on);

-	if(lid_stat)

-		gpio_free(lid_stat);

-}

-

-

-module_init(wifi_proc_init);

-module_exit(wifi_proc_uninit);

-MODULE_AUTHOR(DRIVER_AUTHOR);

-MODULE_DESCRIPTION(DRIVER_DESC);

-MODULE_LICENSE("GPL");

-MODULE_VERSION("1.0");

diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/gpio_customize_ease.c b/ANDROID_3.4.5/arch/arm/mach-wmt/gpio_customize_ease.c
deleted file mode 100755
index 8825f5da..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/gpio_customize_ease.c
+++ /dev/null
@@ -1,3 +0,0 @@
-#if 0

-//no use,delete by kevin

-#endif

diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/headsmp.S b/ANDROID_3.4.5/arch/arm/mach-wmt/headsmp.S
deleted file mode 100755
index 180cbb5f..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/headsmp.S
+++ /dev/null
@@ -1,53 +0,0 @@
-/*++
-	linux/arch/arm/mach-wmt/headsmp.S
-
-	Copyright (c) 2013  WonderMedia Technologies, Inc.
-
-	Copyright (C) 2002 ARM Ltd.
-	All Rights Reserved
-
-	This program is free software: you can redistribute it and/or modify it under the
-	terms of the GNU General Public License as published by the Free Software Foundation,
-	either version 2 of the License, or (at your option) any later version.
-
-	This program is distributed in the hope that it will be useful, but WITHOUT
-	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-	PARTICULAR PURPOSE.  See the GNU General Public License for more details.
-	You should have received a copy of the GNU General Public License along with
-	this program.  If not, see <http://www.gnu.org/licenses/>.
-
-	WonderMedia Technologies, Inc.
-	10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
---*/
-
-#include <linux/linkage.h>
-#include <linux/init.h>
-
-	__CPUINIT
-
-/*
- * WMT specific entry point for secondary CPUs.  This provides
- * a "holding pen" into which all secondary cores are held until we're
- * ready for them to initialise.
- */
-ENTRY(wmt_secondary_startup)
-	mrc	p15, 0, r0, c0, c0, 5
-	and	r0, r0, #15
-	adr	r4, 1f
-	ldmia	r4, {r5, r6}
-	sub	r4, r4, r5
-	add	r6, r6, r4
-pen:	ldr	r7, [r6]
-	cmp	r7, r0
-	bne	pen
-
-	/*
-	 * we've been released from the holding pen: secondary_stack
-	 * should now contain the SVC stack for this core
-	 */
-	b	secondary_startup
-ENDPROC(wmt_secondary_startup)
-
-	.align 2
-1:	.long	.
-	.long	pen_release
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/hotplug.c b/ANDROID_3.4.5/arch/arm/mach-wmt/hotplug.c
deleted file mode 100755
index b5ce4691..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/hotplug.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/*++
-	linux arch/arm/mach-wmt/hotplug.c
-
-	Copyright (c) 2013  WonderMedia Technologies, Inc.
-
-	Copyright (C) 2002 ARM Ltd.
-	All Rights Reserved
-
-	This program is free software: you can redistribute it and/or modify it under the
-	terms of the GNU General Public License as published by the Free Software Foundation,
-	either version 2 of the License, or (at your option) any later version.
-
-	This program is distributed in the hope that it will be useful, but WITHOUT
-	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-	PARTICULAR PURPOSE.  See the GNU General Public License for more details.
-	You should have received a copy of the GNU General Public License along with
-	this program.  If not, see <http://www.gnu.org/licenses/>.
-
-	WonderMedia Technologies, Inc.
-	10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
---*/
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/smp.h>
-
-#include <asm/cacheflush.h>
-#include <asm/cp15.h>
-#include <asm/smp_plat.h>
-
-extern volatile int pen_release;
-
-static inline void cpu_enter_lowpower(void)
-{
-	unsigned int v;
-
-	flush_cache_all();
-	asm volatile(
-	"	mcr	p15, 0, %1, c7, c5, 0\n"
-	"	mcr	p15, 0, %1, c7, c10, 4\n"
-	/*
-	 * Turn off coherency
-	 */
-	"	mrc	p15, 0, %0, c1, c0, 1\n"
-	"	bic	%0, %0, #0x20\n"
-	"	mcr	p15, 0, %0, c1, c0, 1\n"
-	"	mrc	p15, 0, %0, c1, c0, 0\n"
-	"	bic	%0, %0, %2\n"
-	"	mcr	p15, 0, %0, c1, c0, 0\n"
-	  : "=&r" (v)
-	  : "r" (0), "Ir" (CR_C)
-	  : "cc");
-}
-
-static inline void cpu_leave_lowpower(void)
-{
-	unsigned int v;
-
-	asm volatile(	"mrc	p15, 0, %0, c1, c0, 0\n"
-	"	orr	%0, %0, %1\n"
-	"	mcr	p15, 0, %0, c1, c0, 0\n"
-	"	mrc	p15, 0, %0, c1, c0, 1\n"
-	"	orr	%0, %0, #0x20\n"
-	"	mcr	p15, 0, %0, c1, c0, 1\n"
-	  : "=&r" (v)
-	  : "Ir" (CR_C)
-	  : "cc");
-}
-
-static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
-{
-	/*
-	 * there is no power-control hardware on this platform, so all
-	 * we can do is put the core into WFI; this is safe as the calling
-	 * code will have already disabled interrupts
-	 */
-	for (;;) {
-		/*
-		 * here's the WFI
-		 */
-		asm(".word	0xe320f003\n"
-		    :
-		    :
-		    : "memory", "cc");
-
-		if (pen_release == cpu_logical_map(cpu)) {
-			/*
-			 * OK, proper wakeup, we're done
-			 */
-			break;
-		}
-
-		/*
-		 * Getting here, means that we have come out of WFI without
-		 * having been woken up - this shouldn't happen
-		 *
-		 * Just note it happening - when we're woken, we can report
-		 * its occurrence.
-		 */
-		(*spurious)++;
-	}
-}
-
-int platform_cpu_kill(unsigned int cpu)
-{
-	return 1;
-}
-
-/*
- * platform-specific code to shutdown a CPU
- *
- * Called with IRQs disabled
- */
-void platform_cpu_die(unsigned int cpu)
-{
-	int spurious = 0;
-
-	/*
-	 * we're ready for shutdown now, so do it
-	 */
-	cpu_enter_lowpower();
-	platform_do_lowpower(cpu, &spurious);
-
-	/*
-	 * bring this CPU back into the world of cache
-	 * coherency, and then restore interrupts
-	 */
-	cpu_leave_lowpower();
-
-	if (spurious)
-		pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
-}
-
-int platform_cpu_disable(unsigned int cpu)
-{
-	/*
-	 * we don't allow CPU 0 to be shutdown (it is still too special
-	 * e.g. clock tick interrupts)
-	 */
-	return cpu == 0 ? -EPERM : 0;
-}
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/com-video.h b/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/com-video.h
deleted file mode 100755
index a0093ee8..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/com-video.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/*++ 
- * Copyright (c) 2008-2013  WonderMedia  Technologies, Inc.
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- *
- * WonderMedia Technologies, Inc.
- * 4F, 533, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C
- */
-#ifndef COM_VIDEO_H
-/* To assert that only one occurrence is included */
-#define COM_VIDEO_H
-
-/*-------------------- MODULE DEPENDENCY -------------------------------------*/
-#ifdef __KERNEL__
-#include <linux/bitops.h>         // for BIT
-#else
-#ifndef BIT
-#define BIT(x)              (1<<x)
-#endif
-#endif
-
-/*-------------------- EXPORTED PRIVATE CONSTANTS ----------------------------*/
-
-
-/*------------------------------------------------------------------------------
-
-------------------------------------------------------------------------------*/
-
-/*------------------------------------------------------------------------------
-    Definitions of enum
-------------------------------------------------------------------------------*/
-
-typedef enum {
-    VDO_COL_FMT_YUV420,   /* NV12: YC420 with Cb Cr order */
-    VDO_COL_FMT_YUV422H,  
-    VDO_COL_FMT_YUV422V,
-    VDO_COL_FMT_YUV444,
-    VDO_COL_FMT_YUV411,
-    VDO_COL_FMT_GRAY,
-    VDO_COL_FMT_BGRA,     /* B G R A from offset 0 ~ 3 */
-    VDO_COL_FMT_AUTO,
-    VDO_COL_FMT_RGB_888,
-    VDO_COL_FMT_RGB_666,
-    VDO_COL_FMT_RGB_565,
-    VDO_COL_FMT_RGB_1555,
-    VDO_COL_FMT_RGB_5551,
-    VDO_COL_FMT_RGBA,     /* R G B A from offset 0 ~ 3 */
-    VDO_COL_FMT_NV21,     /* YC420 with Cr Cb order */
-    VDO_COL_FMT_MAX,
-    VDO_COL_FMT_UNKNOWN,
-
-    VDO_COL_FMT_ARGB = VDO_COL_FMT_BGRA,
-    VDO_COL_FMT_ABGR = VDO_COL_FMT_RGBA,
-    VDO_COL_FMT_NV12 = VDO_COL_FMT_YUV420  
-} vdo_color_fmt;
-
-
-/*------------------------------------------------------------------------------
-    Definitions of Struct
-------------------------------------------------------------------------------*/
-
-typedef struct {
-    /* Physical address for kernel space */
-    unsigned int    y_addr;   /* Addr of Y plane in YUV domain or RGB plane in ARGB domain */
-    unsigned int    c_addr;   /* C plane address */
-    unsigned int    y_size;   /* Buffer size in bytes */
-    unsigned int    c_size;   /* Buffer size in bytes */
-    unsigned int    img_w;    /* width of valid image (unit: pixel) */
-    unsigned int    img_h;    /* height of valid image (unit: line) */
-    unsigned int    fb_w;     /* width of frame buffer (scanline offset) (unit: pixel)*/
-    unsigned int    fb_h;     /* height of frame buffer (unit: line) */
-    unsigned int    bpp;      /* bits per pixel (8/16/24/32) */
-    
-    vdo_color_fmt   col_fmt;  /* Color format on frame buffer */
-
-    unsigned int    h_crop;   /* Horental Crop (unit: pixel) */
-    unsigned int    v_crop;   /* Vertical Crop (unit: pixel) */
-	
-	unsigned int 	flag;	  /* frame flags */
-} vdo_framebuf_t;
-
-#define VDO_FLAG_INTERLACE		BIT(0)
-#define VDO_FLAG_MOTION_VECTOR	BIT(1)		/* frame buffer with motion vector table after C frame */
-#define VDO_FLAG_MB_ONE			BIT(2)		/* Y/C frame alloc in one mb */
-#define VDO_FLAG_MB_NO			BIT(3)		/* frame buffer is not alloc from mb */
-
-typedef struct {
-	unsigned int resx_src;       /* source x resolution */
-	unsigned int resy_src;       /* source y resolution */
-	unsigned int resx_virtual;   /* virtual x resolution */
-	unsigned int resy_virtual;   /* virtual y resolution */
-	unsigned int resx_visual;    /* visual x resolution */
-	unsigned int resy_visual;    /* visual y resolution */
-	unsigned int posx;           /* x position to display screen */
-	unsigned int posy;           /* y postion to display screen */
-	unsigned int offsetx;        /* x pixel offset from source left edge */
-	unsigned int offsety;        /* y pixel offset from source top edge */
-} vdo_view_t;
-
-
-#endif /* ifndef COM_VIDEO_H */
-
-/*=== END com-video.h ==========================================================*/
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/common_def.h b/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/common_def.h
deleted file mode 100755
index f5b1a1b7..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/common_def.h
+++ /dev/null
@@ -1,171 +0,0 @@
-/*++
- * Copyright (c) 2008-2013  WonderMedia  Technologies, Inc.
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- *
- * WonderMedia Technologies, Inc.
- * 4F, 533, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C
---*/
-
-#ifndef __COMMON_DEF_H
-#define __COMMON_DEF_H
-
-/*
- * Common Constant define
- */
-/*
-#define TRUE    1
-#define FALSE   !TRUE
-
-#define SUCCESS 1
-#define FAIL    !SUCCESS
-
-#ifndef NULL
-#define NULL 0
-#endif
-*/
-
-/*
- * Register pointer and value definitions moved to hardware.h
- */
-
-/*
- * Some type-definitions used by Gatien and Tia, keep them temporaty.
- */
-#define U32 unsigned int
-#define U16 unsigned short
-#define S32 int
-#define S16 short int
-#define U8  unsigned char
-#define S8  char
-
-/*
- * Bits definitions
- */
-#define BIT0                0x00000001
-#define BIT1                0x00000002
-#define BIT2                0x00000004
-#define BIT3                0x00000008
-#define BIT4                0x00000010
-#define BIT5                0x00000020
-#define BIT6                0x00000040
-#define BIT7                0x00000080
-#define BIT8                0x00000100
-#define BIT9                0x00000200
-#define BIT10               0x00000400
-#define BIT11               0x00000800
-#define BIT12               0x00001000
-#define BIT13               0x00002000
-#define BIT14               0x00004000
-#define BIT15               0x00008000
-#define BIT16               0x00010000
-#define BIT17               0x00020000
-#define BIT18               0x00040000
-#define BIT19               0x00080000
-#define BIT20               0x00100000
-#define BIT21               0x00200000
-#define BIT22               0x00400000
-#define BIT23               0x00800000
-#define BIT24               0x01000000
-#define BIT25               0x02000000
-#define BIT26               0x04000000
-#define BIT27               0x08000000
-#define BIT28               0x10000000
-#define BIT29               0x20000000
-#define BIT30               0x40000000
-#define BIT31               0x80000000
-
-/*
- * Size definitions, I recommend to use SZ_xxx in <asm/sizes.h>
- * But I still keep them temporary.
- */
-#define SIZE_1B             0x00000001
-#define SIZE_2B             0x00000002
-#define SIZE_4B             0x00000004
-#define SIZE_8B             0x00000008
-#define SIZE_16B            0x00000010
-#define SIZE_32B            0x00000020
-#define SIZE_64B            0x00000040
-#define SIZE_128B           0x00000080
-#define SIZE_256B           0x00000100
-#define SIZE_512B           0x00000200
-#define SIZE_1KB            0x00000400
-#define SIZE_2KB            0x00000800
-#define SIZE_4KB            0x00001000
-#define SIZE_8KB            0x00002000
-#define SIZE_16KB           0x00004000
-#define SIZE_32KB           0x00008000
-#define SIZE_64KB           0x00010000
-#define SIZE_128KB          0x00020000
-#define SIZE_256KB          0x00040000
-#define SIZE_512KB          0x00080000
-#define SIZE_1MB            0x00100000
-#define SIZE_2MB            0x00200000
-#define SIZE_4MB            0x00400000
-#define SIZE_8MB            0x00800000
-#define SIZE_16MB           0x01000000
-#define SIZE_32MB           0x02000000
-#define SIZE_64MB           0x04000000
-#define SIZE_128MB          0x08000000
-#define SIZE_256MB          0x10000000
-#define SIZE_512MB          0x20000000
-#define SIZE_1GB            0x40000000
-#define SIZE_2GB            0x80000000
-
-/*
- * Get any byte from a word
- */
-#define GET_LE_BYTE0(x)          ((unsigned char)((x) & 0xFF))
-#define GET_LE_BYTE1(x)          ((unsigned char)((x) >> 8 & 0xFF))
-#define GET_LE_BYTE2(x)          ((unsigned char)((x) >> 16 & 0xFF))
-#define GET_LE_BYTE3(x)          ((unsigned char)((x) >> 24 & 0xFF))
-
-/*
- * Following are kept for Ellope temporary.
- *
- * Harry to Ellope: If you think they are no more need, just remove the
- * following section on VSS.
- */
-
-/*  !!! Special Note !!! for packed
- *
- *  use packed that will treat all member as "char" type.
- *  Please use "packed" very carefully.
- *
- *  We should take care to use "packed"
- *  Make sure that each item in the structure will have the same align.
- *
- */
-#ifdef __GNUC__
-    #define MAKE_PACKED(X) X __attribute__((packed))
-
-#elif defined (__arm)
-   #define MAKE_PACKED(X) __packed X
-   #define __FUNCTION__ __func__
-#else
-#error "Unknown Compile"
-#endif
-/*
-Example for packed structure:
-------------------------------
-typedef MAKE_PACKED( struct Test1_s
-{
-    unsigned short s1 ;
-    unsigned short s2 ;
-    unsigned int   i1 ;
-    unsigned int   i2 ;
-} ) Test1_t  ;
-
-*/
-#endif  /* __COMMON_DEF_H */
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/debug-macro.S b/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/debug-macro.S
deleted file mode 100755
index e9337f6d..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/debug-macro.S
+++ /dev/null
@@ -1,74 +0,0 @@
-/*++
-	linux/include/asm-arm/arch-wmt/debug-macro.S
-	
-	Debugging macro include header
-
-	Copyright (c) 2008  WonderMedia Technologies, Inc.
-
-	This program is free software: you can redistribute it and/or modify it under the
-	terms of the GNU General Public License as published by the Free Software Foundation,
-	either version 2 of the License, or (at your option) any later version.
-
-	This program is distributed in the hope that it will be useful, but WITHOUT
-	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-	PARTICULAR PURPOSE.  See the GNU General Public License for more details.
-	You should have received a copy of the GNU General Public License along with
-	this program.  If not, see <http://www.gnu.org/licenses/>.
-
-	WonderMedia Technologies, Inc.
-	10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
---*/
-
-	@Current kernel I/O mmap design is phys = virt
-
-/*
-	.macro	addruart,rx,rd
-	mrc	p15, 0, \rx, c1, c0
-	tst	\rx, #1			@ MMU enabled?
-	moveq	\rx, #0xD8000000	@ Physical base address
-	movne	\rx, #0xFE000000	@ Virtual base address
-	add     \rx, \rx, #0x00200000   @ UART0_BASE = 0xd8200000
-	.endm
-
-	.macro	senduart,rd,rx
-	ldr	r4,  [\rx, #0x20]           @ FIFO control register
-	tst	r4,  #0x01                  @ Check FIFOEN bit
-	strne   \rd, [\rx, #0x1000]     @ TX FIFO
-	streq	\rd, [\rx]              @ Transmit data register
-	.endm
-*/
-
-	.macro addruart,rp,rv,rx
-	 ldr \rp, =0xD8000000 @ Physical base address
-	 ldr \rv, =0xFE000000 @ Virtual base address  
-	 add     \rp, \rp, #0x00200000   @ UART0_BASE = 0xd8200000
-	 add     \rv, \rv, #0x00200000   @ UART0_BASE = 0xfe200000
-	 .endm
-
-	 .macro senduart,rd,rx
-	 stmfd sp!,{r4}
- 
-	 ldr r4,  [\rx, #0x20]           @ FIFO control register
-	 tst r4,  #0x01                  @ Check FIFOEN bit
-	 mov r4,  #0x1000
-	 strne   \rd, [\rx, r4]     @ TX FIFO
-	 streq \rd, [\rx]              @ Transmit data register
-	  
-	 ldmfd sp!,{r4}
-	 .endm
-
-
-	.macro	waituart,rd,rx
-1001:
-	ldr	\rd, [\rx, #0x1C]       @ Status register
-	tst	\rd, #2                 @ Transmit busy
-	bne	1001b                   @ If busy then wait
-	.endm
-
-	.macro	busyuart,rd,rx
-1001:
-	ldr	\rd, [\rx, #0x1C]       @ Status register
-	tst	\rd, #2                 @ Transmit busy
-	bne	1001b
-	.endm
-
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/dma.h b/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/dma.h
deleted file mode 100755
index 2c72a023..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/dma.h
+++ /dev/null
@@ -1,485 +0,0 @@
-/*++
-	linux/include/asm-arm/arch-wmt/dma.h
-
-	Copyright (c) 2013  WonderMedia Technologies, Inc.
-
-	This program is free software: you can redistribute it and/or modify it under the
-	terms of the GNU General Public License as published by the Free Software Foundation,
-	either version 2 of the License, or (at your option) any later version.
-
-	This program is distributed in the hope that it will be useful, but WITHOUT
-	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-	PARTICULAR PURPOSE.  See the GNU General Public License for more details.
-	You should have received a copy of the GNU General Public License along with
-	this program.  If not, see <http://www.gnu.org/licenses/>.
-
-	WonderMedia Technologies, Inc.
-	10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
---*/
-
-#ifndef __ASM_ARCH_DMA_H
-#define __ASM_ARCH_DMA_H
-
-#include <asm/sizes.h>
-#include "hardware.h"
-
-#define dmach_t unsigned int
-
-/*
- * This is the maximum DMA address that can be DMAd to.
- */
-
-/*
-#define MAX_DMA_ADDRESS		        0xFFFFFFFF
-*/
-#define DMA_MEM_REG_OFFSET		0x100
-
-/*
- * Maximum physical DMA buffer size
- */
-
-#define MAX_DMA_SIZE			SZ_16K
-#define CUT_DMA_SIZE			SZ_4K
-
-/***********************************************
-* The WM3437 has 16 internal DMA channels.
-*************************************************/
-
-#define DMA_CHANNELS    16
-#define MAX_DMA_CHANNELS DMA_CHANNELS
-
-/************************************
-*
-*  DMA GLOBAL CONTROL
-*
-*************************************/
-#define DMA_SW_RST	BIT8
-#define DMA_BIG_ENDIAN	BIT1
-#define DMA_GLOBAL_EN	BIT0
-/************************************
-*
-*  DMA_INTERRUPT ENABLE
-*
-*************************************/
-#define CH00_INT_EN	BIT0
-#define CH01_INT_EN	BIT1
-#define CH02_INT_EN	BIT2
-#define CH03_INT_EN	BIT3
-#define CH04_INT_EN	BIT4
-#define CH05_INT_EN	BIT5
-#define CH06_INT_EN	BIT6
-#define CH07_INT_EN	BIT7
-#define CH08_INT_EN	BIT8
-#define CH09_INT_EN	BIT9
-#define CH10_INT_EN	BIT10
-#define CH11_INT_EN	BIT11
-#define CH12_INT_EN	BIT12
-#define CH13_INT_EN	BIT13
-#define CH14_INT_EN	BIT14
-#define CH15_INT_EN	BIT15
-#define ALL_INT_EN	0x0000FFFF
-
-/************************************
-*
-*  DMA_INTERRUPT STATUS
-*
-*************************************/
-#define CH00_INT_STS	BIT0
-#define CH01_INT_STS	BIT1
-#define CH02_INT_STS	BIT2
-#define CH03_INT_STS	BIT3
-#define CH04_INT_STS	BIT4
-#define CH05_INT_STS	BIT5
-#define CH06_INT_STS	BIT6
-#define CH07_INT_STS	BIT7
-#define CH08_INT_STS	BIT8
-#define CH09_INT_STS	BIT9
-#define CH10_INT_STS	BIT10
-#define CH11_INT_STS	BIT11
-#define CH12_INT_STS	BIT12
-#define CH13_INT_STS	BIT13
-#define CH14_INT_STS	BIT14
-#define CH15_INT_STS	BIT15
-#define ALL_INT_CLEAR	0x0000FFFF
-
-/************************************
-*
-*  DMA SCHEDULE SCHEME
-*
-*************************************/
-#define SCHEDULE_RR_DISABLE	BIT0
-#define TIMER_1_SHIFT	16
-#define TIMER_2_SHIFT	8
-/************************************
-*
-*  DMA_CCR SETTIGN
-*
-*************************************/
-/*WRAP MODE [31:30]*/
-#define DMA_WRAP_1	0x00000000
-#define DMA_WRAP_2	BIT30
-#define DMA_WRAP_4	BIT31
-#define DMA_WRAP_8	(BIT31|BIT30)
-#define DMA_WRQP_MASK	0xC0000000
-/*BUST[29:28]*/
-#define DMA_BURST_1	0x00000000
-#define DMA_BURST_2	BIT28
-#define DMA_BURST_4	BIT29
-#define DMA_BURST_8	(BIT29|BIT28)
-#define DMA_BURST_MASK	0x30000000
-/*TRANSFER SIZE[[27:26]*/
-#define DMA_SIZE_8	0x00000000
-#define DMA_SIZE_16	BIT26
-#define DMA_SIZE_32	BIT27
-#define DMA_SIZE_64	(BIT26|BIT27)
-#define DMA_SIZE_MASK	0x0C000000
-/*/1/2 addr mode[25:24]*/
-#define DMA_WRAP_MODE	0x00000000
-#define DMA_INC_MODE	BIT24
-#define DMA_SG_MODE	BIT25
-#define DMA_ADDR_MODE_MASK	0x03000000
-/*SW REQUEST ENABLE[23]*/
-#define DMA_SW_REQ	BIT23
-#define DMA_SW_REQ_MASK	0x00800000
-/*DMA 1/2 TRANS DIRECTION[22]*/
-#define DEVICE_TO_MEM	BIT22
-#define DEVICE_TO_MEM_MASK	0x00400000
-/*DMA REQ NUM[20:16]*/
-#define DMA_REQ_ID_SHIFT	16
-#define DMA_REQ_ID_MASK		0x000F8000
-
-/*DMA complete BIT*/
-#define DMA_P0_COMPLETE	BIT9	   /*0:complete 1:did't complete*/
-#define DMA_P1_COMPLETE	BIT8
-
-#define SYSTEM_DMA_RUN	BIT7
-#define DMA_RUN_MASK	0x00000080
-#define DMA_WAKE BIT6
-#define DMA_WAKE_MASK	0x00000040
-#define DMA_ACTIVE	BIT4
-#define DMA_ACTIVE_MASK	0x00000010
-#define DMA_USER_SET_MASK	0xFFFE0000
-#define SYSTEM_DMA_REQ_EN BIT11
-
-/*DMA ERROR ID[3:0]*/
-#define DMA_EVT_ID_MASK	0x0000000F
-#define DMA_EVT_NO_STATUS	0
-#define DMA_EVT_REG	1
-#define DMA_EVT_FF_UNDERRUN	2
-#define DMA_EVT_FF_OVERRUN	3
-#define DMA_EVT_DESP_READ	4
-#define DMA_EVT_DESP_WRITE	5
-#define DMA_EVT_MR_READ		6
-#define DMA_EVT_MR_WRITE	7
-#define DMA_EVT_DATA_READ	8
-#define DMA_EVT_DATA_WRITE	9
-#define DMA_EVT_SUCCESS		15
-
-/*DMA UPDATE MEMORY REG. BIT*/
-#define DMA_UP_MEMREG_EN BIT5
-
-/*****************************************
-	DMA descript setting
-******************************************/
-#define DMA_DES_END	BIT31
-#define DMA_FORMAT_DES1	BIT30
-#define DMA_INTEN_DES	BIT29
-#define DMA_DONE_DES    BIT16
-#define DMA_DES0_SIZE 0x8	/*8 byte*/
-#define DMA_DES1_SIZE 0x10	/*16 byte*/
-#define DMA_DES_REQCNT_MASK 0xFFFF
-
-
-/**/
-/*  I2S CFG setting*/
-/**/
-
-#define I2S_RX_SETTING    (DMA_WRAP_MODE | DEVICE_TO_MEM)
-#define I2S_TX_SETTING    (DMA_WRAP_MODE)
-
-#define I2S_8BITS_SETTING          (DMA_WRAP_1 | DMA_BURST_8 | DMA_SIZE_8)
-#define I2S_16BITS_SETTING         (DMA_WRAP_1 | DMA_BURST_8 | DMA_SIZE_16)
-#define I2S_32BITS_SETTING         (DMA_WRAP_1 | DMA_BURST_4 | DMA_SIZE_32)
-
-#define I2S_RX_DMA_8BITS_CFG   (I2S_8BITS_SETTING  | I2S_RX_SETTING)
-#define I2S_RX_DMA_16BITS_CFG  (I2S_16BITS_SETTING | I2S_RX_SETTING)
-#define I2S_RX_DMA_32BITS_CFG  (I2S_32BITS_SETTING | I2S_RX_SETTING)
-
-#define I2S_TX_DMA_8BITS_CFG   (I2S_8BITS_SETTING  | I2S_TX_SETTING)
-#define I2S_TX_DMA_16BITS_CFG  (I2S_16BITS_SETTING | I2S_TX_SETTING)
-#define I2S_TX_DMA_32BITS_CFG  (I2S_32BITS_SETTING | I2S_TX_SETTING)
-
-#define I2S_RX_DMA_CFG         (I2S_RX_DMA_32BITS_CFG)
-#define I2S_TX_DMA_CFG         (I2S_TX_DMA_32BITS_CFG)
-
-#define I2S_TX_FIFO 0xD80EDB60
-#define I2S_RX_FIFO 0xD80EDB00
-#define SPDIF_RX_FIFO 0xD80EDB20
-
-/**/
-/*  PCM CFG setting*/
-/**/
-
-#define PCM_RX_SETTING    (DMA_WRAP_MODE | DEVICE_TO_MEM)
-#define PCM_TX_SETTING    (DMA_WRAP_MODE)
-
-#define PCM_8BITS_SETTING          (DMA_WRAP_1 | DMA_BURST_8 | DMA_SIZE_8)
-#define PCM_16BITS_SETTING         (DMA_WRAP_1 | DMA_BURST_8 | DMA_SIZE_16)
-#define PCM_32BITS_SETTING         (DMA_WRAP_1 | DMA_BURST_8 | DMA_SIZE_32)
-
-#define PCM_RX_DMA_8BITS_CFG   (PCM_8BITS_SETTING  | PCM_RX_SETTING)
-#define PCM_RX_DMA_16BITS_CFG  (PCM_16BITS_SETTING | PCM_RX_SETTING)
-#define PCM_RX_DMA_32BITS_CFG  (PCM_32BITS_SETTING | PCM_RX_SETTING)
-
-#define PCM_TX_DMA_8BITS_CFG   (PCM_8BITS_SETTING  | PCM_TX_SETTING)
-#define PCM_TX_DMA_16BITS_CFG  (PCM_16BITS_SETTING | PCM_TX_SETTING)
-#define PCM_TX_DMA_32BITS_CFG  (PCM_32BITS_SETTING | PCM_TX_SETTING)
-
-#define PCM_RX_DMA_CFG         (PCM_RX_DMA_16BITS_CFG)
-#define PCM_TX_DMA_CFG         (PCM_TX_DMA_16BITS_CFG)
-
-#define PCM_TX_FIFO (0xD82D0000 + 0x10)
-#define PCM_RX_FIFO (0xD82D0000 + 0x30)
-
-/**/
-/*  AC97 CFG setting*/
-/**/
-#define AC97_RX_SETTING    (DMA_WRAP_MODE | DEVICE_TO_MEM)
-#define AC97_TX_SETTING    (DMA_WRAP_MODE)
-
-#define AC97_8BITS_SETTING          (DMA_WRAP_1 | DMA_BURST_8 | DMA_SIZE_8)
-#define AC97_16BITS_SETTING         (DMA_WRAP_1 | DMA_BURST_8 | DMA_SIZE_16)
-#define AC97_32BITS_SETTING         (DMA_WRAP_1 | DMA_BURST_8 | DMA_SIZE_32)
-
-#define AC97_MIC_DMA_8BITS_CFG      (AC97_8BITS_SETTING  | AC97_RX_SETTING)
-#define AC97_MIC_DMA_16BITS_CFG     (AC97_16BITS_SETTING | AC97_RX_SETTING)
-
-#define AC97_RX_DMA_8BITS_CFG   (AC97_8BITS_SETTING  | AC97_RX_SETTING)
-#define AC97_RX_DMA_16BITS_CFG  (AC97_16BITS_SETTING | AC97_RX_SETTING)
-#define AC97_RX_DMA_32BITS_CFG  (AC97_32BITS_SETTING | AC97_RX_SETTING)
-
-#define AC97_TX_DMA_8BITS_CFG   (AC97_8BITS_SETTING  | AC97_TX_SETTING)
-#define AC97_TX_DMA_16BITS_CFG  (AC97_16BITS_SETTING | AC97_TX_SETTING)
-#define AC97_TX_DMA_32BITS_CFG  (AC97_32BITS_SETTING | AC97_TX_SETTING)
-
-#define AC97_MIC_DMA_CFG            (AC97_MIC_DMA_16BITS_CFG)
-#define AC97_RX_DMA_CFG         (AC97_RX_DMA_32BITS_CFG)
-#define AC97_TX_DMA_CFG         (AC97_TX_DMA_32BITS_CFG)
-
-#define AC97_TX_FIFO 0xD8290080
-#define AC97_RX_FIFO 0xD82900C0 
-#define AC97_MIC_FIFO 0xD8290100 
-
-/**/
-/*  SPI CFG setting*/
-/**/
-
-#define SPI_RX_SETTING    (DMA_WRAP_MODE | DEVICE_TO_MEM)
-#define SPI_TX_SETTING    (DMA_WRAP_MODE)
-
-#define SPI_8BITS_SETTING          (DMA_WRAP_1 | DMA_BURST_1 | DMA_SIZE_8)
-#define SPI_16BITS_SETTING         (DMA_WRAP_1 | DMA_BURST_8 | DMA_SIZE_16)
-#define SPI_32BITS_SETTING         (DMA_WRAP_1 | DMA_BURST_8 | DMA_SIZE_32)
-#define SPI_64BITS_SETTING         (DMA_WRAP_1 | DMA_BURST_1 | DMA_SIZE_64)
-
-#define SPI_RX_DMA_8BITS_CFG   (SPI_8BITS_SETTING  | SPI_RX_SETTING)
-#define SPI_RX_DMA_16BITS_CFG  (SPI_16BITS_SETTING | SPI_RX_SETTING)
-#define SPI_RX_DMA_32BITS_CFG  (SPI_32BITS_SETTING | SPI_RX_SETTING)
-
-#define SPI_TX_DMA_8BITS_CFG   (SPI_8BITS_SETTING  | SPI_TX_SETTING)
-#define SPI_TX_DMA_16BITS_CFG  (SPI_16BITS_SETTING | SPI_TX_SETTING)
-#define SPI_TX_DMA_32BITS_CFG  (SPI_32BITS_SETTING | SPI_TX_SETTING)
-
-#define SPI_RX_DMA_CFG         (SPI_RX_DMA_8BITS_CFG)
-#define SPI_TX_DMA_CFG         (SPI_TX_DMA_8BITS_CFG)
-
-#define SPI_RX_DMA_64BITS_CFG  (SPI_64BITS_SETTING | SPI_RX_SETTING)
-#define SPI_TX_DMA_64BITS_CFG  (SPI_64BITS_SETTING | SPI_TX_SETTING)
-#define SPISLAVE_RX_DMA_CFG         (SPI_RX_DMA_64BITS_CFG)
-#define SPISLAVE_TX_DMA_CFG         (SPI_TX_DMA_64BITS_CFG)
-
-#define SPI0_TX_FIFO 0xD8240010
-#define SPI0_RX_FIFO 0xD8240030 
-#define SPI1_TX_FIFO 0xD8250010
-#define SPI1_RX_FIFO 0xD8250030 
-
-/**/
-/*  UART CFG setting*/
-/**/
-
-#define UART_RX_SETTING    (DMA_WRAP_MODE | DEVICE_TO_MEM)
-#define UART_TX_SETTING    (DMA_WRAP_MODE)
-
-#define UART_8BITS_SETTING          (DMA_WRAP_1 | DMA_BURST_1 | DMA_SIZE_8)
-#define UART_16BITS_SETTING         (DMA_WRAP_1 | DMA_BURST_1 | DMA_SIZE_16)
-#define UART_32BITS_SETTING         (DMA_WRAP_1 | DMA_BURST_1 | DMA_SIZE_32)
-
-#define UART_RX_DMA_8BITS_CFG   (UART_8BITS_SETTING  | UART_RX_SETTING)
-#define UART_RX_DMA_16BITS_CFG  (UART_16BITS_SETTING | UART_RX_SETTING)
-#define UART_RX_DMA_32BITS_CFG  (UART_32BITS_SETTING | UART_RX_SETTING)
-
-#define UART_TX_DMA_8BITS_CFG   (UART_8BITS_SETTING  | UART_TX_SETTING)
-#define UART_TX_DMA_16BITS_CFG  (UART_16BITS_SETTING | UART_TX_SETTING)
-#define UART_TX_DMA_32BITS_CFG  (UART_32BITS_SETTING | UART_TX_SETTING)
-
-#define UART_RX_DMA_CFG         (UART_RX_DMA_8BITS_CFG)
-#define UART_TX_DMA_CFG         (UART_TX_DMA_8BITS_CFG)
-
-#define UART0_TX_FIFO (0x1000+UART0_BASE_ADDR-WMT_MMAP_OFFSET)
-#define UART0_RX_FIFO (0x1020+UART0_BASE_ADDR-WMT_MMAP_OFFSET)
-
-#define UART1_TX_FIFO (0x1000+UART1_BASE_ADDR-WMT_MMAP_OFFSET)
-#define UART1_RX_FIFO (0x1020+UART1_BASE_ADDR-WMT_MMAP_OFFSET)
-
-#define UART2_TX_FIFO (0x1000+UART2_BASE_ADDR-WMT_MMAP_OFFSET)
-#define UART2_RX_FIFO (0x1020+UART2_BASE_ADDR-WMT_MMAP_OFFSET)
-
-#define UART3_TX_FIFO (0x1000+UART3_BASE_ADDR-WMT_MMAP_OFFSET)
-#define UART3_RX_FIFO (0x1020+UART3_BASE_ADDR-WMT_MMAP_OFFSET)
-
-/*
- * All possible devices a DMA channel can be attached to.
- */
-
-enum dma_device_e {
-	SPI0_DMA_TX_REQ = 0 , /*spi0tx*/
-	SPI0_DMA_RX_REQ = 1 , /*spi0rx*/
-	SPI1_DMA_TX_REQ = 2 , /*spi1tx*/
-	SPI1_DMA_RX_REQ = 3 , /*spi1tx*/
-	PCM1_TX_DMA_REQ = 4 ,/* pcm*/
-	PCM1_RX_DMA_REQ = 5 ,/* pcm*/
-	UART_0_TX_DMA_REQ = 6,/* uart0*/
-	UART_0_RX_DMA_REQ = 7,/* uart0*/
-	UART_1_TX_DMA_REQ = 8,/* uart1*/
-	UART_1_RX_DMA_REQ = 9,/* uart1*/
-	UART_2_TX_DMA_REQ = 10,/* uart2*/
-	UART_2_RX_DMA_REQ = 11,/* uart2*/
-	UART_3_TX_DMA_REQ = 12,/* uart3*/
-	UART_3_RX_DMA_REQ = 13,/* uart3*/
-	PCM_TX_DMA_REQ = 14 ,/* pcm*/
-	PCM_RX_DMA_REQ = 15 ,/* pcm*/
-	AHB1_AUD_DMA_REQ_0 = 21,
-	AHB1_AUD_DMA_REQ_1 = 22,
-	AHB1_AUD_DMA_REQ_2 = 23,
-	AHB1_AUD_DMA_REQ_3 = 24,
-	AHB1_AUD_DMA_REQ_4 = 25,
-	AHB1_AUD_DMA_REQ_5 = 26,
-	AHB1_AUD_DMA_REQ_6 = 27,
-	AHB1_AUD_DMA_REQ_7 = 28,
-	MEMORY_DMA_REQ = 32,/* memory*/
-	DEVICE_RESERVED = 33 /* reserved*/
-};
-
-/*
- * DMA device configuration structure
- * when memory to memory
- *	MIF0addr : source address
- *	MIF1addr : destination address
- * when device to memory or memory to device
- *	MIF0addr : memory address
- *	MIF1addr : device FIFO address
- */
-
-struct dma_device_cfg_s {
-	enum dma_device_e DeviceReqType;
-	unsigned long DefaultCCR;
-	unsigned long MIF0addr;
-	unsigned long MIF1addr;
-	unsigned int  ChunkSize;
-};
-
-/*
-* DMA descriptor registers
-*/
-
-struct dma_des_fmt0 {
-	volatile unsigned long ReqCnt;
-	volatile unsigned long DataAddr;
-};
-struct dma_des_fmt1 {
-	volatile unsigned long ReqCnt;
-	volatile unsigned long DataAddr;
-	volatile unsigned long BrAddr;
-	volatile unsigned long reserved;
-
-};
-struct dma_descript_addr {
-	volatile unsigned long *des_0;
-	volatile unsigned long *des_1;
-};
-
-/*
-* DMA MEMORY REGISTER
-*/
-struct dma_mem_reg_group_s {
-	volatile unsigned long DMA_IF0RBR_CH;
-	volatile unsigned long DMA_IF0DAR_CH;
-	volatile unsigned long DMA_IF0BAR_CH;
-	volatile unsigned long DMA_IF0CPR_CH;
-	volatile unsigned long DMA_IF1RBR_CH;
-	volatile unsigned long DMA_IF1DAR_CH;
-	volatile unsigned long DMA_IF1BAR_CH;
-	volatile unsigned long DMA_IF1CPR_CH;
-};
-struct dma_mem_reg_s {
-	struct dma_mem_reg_group_s mem_reg_group[MAX_DMA_CHANNELS];
-};
-
-/*
- * DMA control register set structure
- */
-struct dma_regs_s {
-	volatile unsigned long RESERVED[0x10];/*0x00-0x3F*/
-	volatile unsigned long DMA_GCR; /*0x40-0x43*/
-	volatile unsigned long DMA_MRPR;/*0x44-0x47*/
-	volatile unsigned long DMA_IER; /*0x48-0x4B*/
-	volatile unsigned long DMA_ISR; /*0x4C-0x4F*/
-	volatile unsigned long DMA_TMR; /*0x50-0x53*/
-	volatile unsigned long RESERVED_1[0xB];/*0x54-0x7F*/
-	volatile unsigned long DMA_CCR_CH[0x10];/*0x80-0xBF*/
-	volatile unsigned long RESERVED_2[0x10];/*0xC0-0xFF*/
-};
-
-extern struct dma_device_cfg_s dma_device_cfg_table[];         /* DMA device config table */
-
-/*
- * DMA function prototypes
- */
-
-extern
-int wmt_request_dma(dmach_t *channel, const char *device_id, enum dma_device_e device,
-		void (*callback)(void *data), void *callback_data);
-extern
-void wmt_free_dma(dmach_t ch);
-
-extern
-int wmt_start_dma(dmach_t ch, dma_addr_t dma_ptr, dma_addr_t dma_ptr2, unsigned int size);
-
-extern
-void wmt_reset_dma(dmach_t ch);
-
-extern
-void wmt_clear_dma(dmach_t ch);
-
-extern
-int wmt_setup_dma(dmach_t ch, struct dma_device_cfg_s device_cfg);
-
-extern
-void wmt_stop_dma(dmach_t ch);
-
-extern
-void wmt_resume_dma(dmach_t ch);
-
-extern
-struct dma_mem_reg_group_s wmt_get_dma_pos_info(dmach_t ch);
-
-extern
-unsigned int wmt_get_dma_pos(dmach_t ch);
-
-extern
-int wmt_dma_busy(dmach_t ch);
-
-extern
-void wmt_dump_dma_regs(dmach_t ch);
-
-#endif  /* _ASM_ARCH_DMA_H */
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/gmt-core.h b/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/gmt-core.h
deleted file mode 100755
index 768c89da..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/gmt-core.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*++
-	drivers/mtd/gmt/gmt-core.c - GMT Core driver
-
-	Copyright (c) 2013  WonderMedia Technologies, Inc.
-
-	This program is free software: you can redistribute it and/or modify it under the
-	terms of the GNU General Public License as published by the Free Software Foundation,
-	either version 2 of the License, or (at your option) any later version.
-
-	This program is distributed in the hope that it will be useful, but WITHOUT
-	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-	PARTICULAR PURPOSE.  See the GNU General Public License for more details.
-	You should have received a copy of the GNU General Public License along with
-	this program.  If not, see <http://www.gnu.org/licenses/>.
-
-	WonderMedia Technologies, Inc.
-	10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
---*/
-enum gmt_device_type {
-	GMT2214,
-};
-
-/**
- * @dev: master device of the chip (can be used to access platform data)
- * @i2c: i2c client private data for regulator
- * @iolock: mutex for serializing io access
- * @irqlock: mutex for buslock
- */
-struct gmt2214_dev {
-	struct device *dev;
-	struct regmap *regmap;
-	struct i2c_client *i2c;
-	struct mutex iolock;
-
-	int device_type;
-};
-
-extern int gmt2214_reg_read(struct gmt2214_dev *gmt2214, u8 reg, void *dest);
-extern int gmt2214_reg_write(struct gmt2214_dev *gmt2214, u8 reg, u8 value);
-
-struct gmt2214_platform_data {
-	int				device_type;
-};
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/gpio.h b/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/gpio.h
deleted file mode 100755
index 793d8ce9..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/gpio.h
+++ /dev/null
@@ -1,191 +0,0 @@
-/*++
-linux/include/asm-arm/arch-wmt/gpio.h
-
-Copyright (c) 2008  WonderMedia Technologies, Inc.
-
-This program is free software: you can redistribute it and/or modify it under the
-terms of the GNU General Public License as published by the Free Software Foundation,
-either version 2 of the License, or (at your option) any later version.
-
-This program is distributed in the hope that it will be useful, but WITHOUT
-ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-PARTICULAR PURPOSE.  See the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License along with
-this program.  If not, see <http://www.gnu.org/licenses/>.
-
-WonderMedia Technologies, Inc.
-10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
---*/
-
-#ifndef __ASM_ARCH_GPIO_H
-#define __ASM_ARCH_GPIO_H
-
-/*
- * For GPIO_BASE + 0x0020 + (0x0020*n), n=0 to 2
- */
-typedef struct gpio_uart_s {             /* total 32 bits */
-	/* UART1 */
-	unsigned char uart1_cts:1;
-	unsigned char uart1_rts:1;
-	unsigned char uart1_rxd:1;
-	unsigned char uart1_txd:1;
-	unsigned char reserve1:4;
-	/* UART2 */
-	unsigned char uart2_cts:1;
-	unsigned char uart2_rts:1;
-	unsigned char uart2_rxd:1;
-	unsigned char uart2_txd:1;
-	unsigned char reserve2:4;
-	/* UART3 */
-	unsigned char uart3_cts:1;
-	unsigned char uart3_rts:1;
-	unsigned char uart3_rxd:1;
-	unsigned char uart3_txd:1;
-	unsigned char reserve3:4;
-	/* UART4 */
-	unsigned char uart4_cts:1;
-	unsigned char uart4_rts:1;
-	unsigned char uart4_rxd:1;
-	unsigned char uart4_txd:1;
-	unsigned char reserve4:4;
-
-} gpio_uart_t;
-
-/*
- * For GPIO_BASE + 0x0024 + (0x0020*n), n=0 to 2
- */
-typedef struct gpio_spi_s {              /* total 32 bits */
-	/* SPI1 */
-	unsigned char spi1_clk:1;
-	unsigned char spi1_miso:1;
-	unsigned char spi1_mosi:1;
-	unsigned char spi1_ssn:1;
-	unsigned char reserve1:4;
-	/* SPI2 */
-	unsigned char spi2_clk:1;
-	unsigned char spi2_miso:1;
-	unsigned char spi2_mosi:1;
-	unsigned char spi2_ssn:1;
-	unsigned char reserve2:4;
-	/* SPI3 */
-	unsigned char spi3_clk:1;
-	unsigned char spi3_miso:1;
-	unsigned char spi3_mosi:1;
-	unsigned char spi3_ssn:1;
-	unsigned char reserve3:4;
-	/* SPI4 */
-	unsigned char spi4_clk:1;
-	unsigned char spi4_miso:1;
-	unsigned char spi4_mosi:1;
-	unsigned char spi4_ssn:1;
-	unsigned char reserve4:4;
-
-} gpio_spi_t;
-
-/*
- * For GPIO_BASE + 0x0028 + (0x0020*n), n=0 to 2
- */
-typedef struct gpio_kpad_s {             /* total 32 bits */
-	/* KPAD_COW[7:0] */
-	unsigned char cow0:1;
-	unsigned char cow1:1;
-	unsigned char cow2:1;
-	unsigned char cow3:1;
-	unsigned char cow4:1;
-	unsigned char cow5:1;
-	unsigned char cow6:1;
-	unsigned char cow7:1;
-	/* KPAD_ROW[7:0] */
-	unsigned char row0:1;
-	unsigned char row1:1;
-	unsigned char row2:1;
-	unsigned char row3:1;
-	unsigned char row4:1;
-	unsigned char row5:1;
-	unsigned char row6:1;
-	unsigned char row7:1;
-	/* VIC_DATA[7:0] */
-	unsigned char data0:1;
-	unsigned char data1:1;
-	unsigned char data2:1;
-	unsigned char data3:1;
-	unsigned char data4:1;
-	unsigned char data5:1;
-	unsigned char data6:1;
-	unsigned char data7:1;
-	/* VIC misc pins */
-	unsigned char clk:1;
-	unsigned char vreq:1;
-	unsigned char vsync:1;
-	unsigned char hsync:1;
-	unsigned char reserv1:4;
-
-} gpio_kpad_t;
-
-/*
- * For GPIO_BASE + 0x002C + (0x0020*n), n=0 to 2
- */
-typedef struct gpio_misc_s {             /* total 32 bits */
-	/* SDMMC */
-	unsigned char sd_data0:1;
-	unsigned char sd_data1:1;
-	unsigned char sd_data2:1;
-	unsigned char sd_data3:1;
-	unsigned char sd_clk:1;
-	unsigned char sd_cmd:1;
-	unsigned char reverse1:2;
-	/* I2S */
-	unsigned char i2s_sclk:1;
-	unsigned char i2s_sysclk:1;
-	unsigned char i2s_sdi:1;
-	unsigned char i2s_sdo:1;
-	unsigned char i2s_ws:1;
-	/* Wake-up[4:2] */
-	unsigned char wakeup2:1;
-	unsigned char wakeup3:1;
-	unsigned char wakeup4:1;
-	/* I2C */
-	unsigned char i2c_scl:1;
-	unsigned char i2c_sda:1;
-	/* Wake-up[1:0] */
-	unsigned char wakeup0:1;
-	unsigned char wakeup1:1;
-	/* AC'97 */
-	unsigned char ac97_bclk:1;
-	unsigned char ac97_sdi:1;
-	unsigned char ac97_sdo:1;
-	unsigned char ac97_sync:1;
-	/* PWM_OUT[3:0] */
-	unsigned char pwm0:1;
-	unsigned char pwm1:1;
-	unsigned char pwm2:1;
-	unsigned char pwm3:1;
-	/* PCM */
-	unsigned char pcm_clk:1;
-	unsigned char pcm_in:1;
-	unsigned char pcm_out:1;
-	unsigned char pcm_sync:1;
-
-} gpio_misc_t;
-
-/*
- * For GPIO_BASE + 0x0084
- */
-typedef struct gpio_irqt_s {
-	/* GPIO_IRQ[9:0] type */
-	unsigned char  irqt0:2;
-	unsigned char  irqt1:2;
-	unsigned char  irqt2:2;
-	unsigned char  irqt3:2;
-	unsigned char  irqt4:2;
-	unsigned char  irqt5:2;
-	unsigned char  irqt6:2;
-	unsigned char  irqt7:2;
-	unsigned char  irqt8:2;
-	unsigned char  irqt9:2;
-	unsigned char  reverse1:4;
-	unsigned char  reverse2;
-
-} gpio_irqt_t;
-
-#endif /* __ASM_ARCH_GPIO_H */
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/gpio_customize_ease.h b/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/gpio_customize_ease.h
deleted file mode 100755
index 2ce13487..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/gpio_customize_ease.h
+++ /dev/null
@@ -1,3 +0,0 @@
-#if 0
-//no use,delete by kevin
-#endif
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/hardware.h b/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/hardware.h
deleted file mode 100755
index c62c9423..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/hardware.h
+++ /dev/null
@@ -1,171 +0,0 @@
-/*++
-linux/include/asm-arm/arch-wmt/hardware.h
-
-Copyright (c) 2012  WonderMedia Technologies, Inc.
-
-This program is free software: you can redistribute it and/or modify it under the
-terms of the GNU General Public License as published by the Free Software Foundation,
-either version 2 of the License, or (at your option) any later version.
-
-This program is distributed in the hope that it will be useful, but WITHOUT
-ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-PARTICULAR PURPOSE.  See the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License along with
-this program.  If not, see <http://www.gnu.org/licenses/>.
-
-WonderMedia Technologies, Inc.
-10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
---*/
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-/*
- * Those are statically mapped PCMCIA IO space for designs using it as a
- * generic IO bus, typically with ISA parts, hardwired IDE interfaces, etc.
- * The actual PCMCIA code is mapping required IO region at run time.
- */
-
-/*#define PCMCIA_IO_0_BASE      0xf6000000 */
-/*#define PCMCIA_IO_1_BASE      0xf7000000 */
-
-
-/*
- * We requires absolute addresses i.e. (PCMCIA_IO_0_BASE + 0x3f8) for
- * in*()/out*() macros to be usable for all cases.
- */
-#define PCIO_BASE               0
-
-/*
- * WMT internal I/O mappings, designed as offset addressing
- *
- *      phys != virt
- */
-#define PIO_BASE                0xFE000000      /* physical start of IO space */
-#define VIO_BASE                0xFE000000      /* virtual start of IO space */
-#define VIO_OFFSET              0               /* x = Virtual IO address offset */
-#define IO_SIZE                 0x01000000      /* 16 MB */
-
-#define io_p2v(x)               (x)
-#define io_v2p(x)               (x)
-
-#ifndef __ASSEMBLY__    /* C language */
-#include <asm/types.h>
-
-#if 0                   /* Method 1, straight forward */
-
-/*
- * Register pointer
- */
-# define REG32_PTR(x)           ((volatile u32 *)io_p2v(x))
-# define REG16_PTR(x)           ((volatile u16 *)io_p2v(x))
-# define REG8_PTR(x)            ((volatile u8  *)io_p2v(x))
-
-/*
- * Register value
- */
-# define REG32_VAL(x)           (*(REG32_PTR(x)))
-# define REG16_VAL(x)           (*(REG16_PTR(x)))
-# define REG8_VAL(x)            (*(REG8_PTR(x)))
-
-#else                   /* Method 2, GNU's original method */
-
-/*
- * This REGxx_VAL() version gives the same results as the one above,
- * except that we are fooling gcc somehow so it generates far better and
- * smaller assembly code for access to contigous registers.  It's a shame
- * that gcc doesn't guess this by itself.
- */
-typedef struct {
-	volatile u32 offset[4096];      /* 4K * 4 = SZ_16K */
-
-} __regbase32;
-
-typedef struct {
-	volatile u16 offset[4096];      /* 4K * 2 = SZ_8K */
-
-} __regbase16;
-
-typedef struct {
-	volatile u8 offset[4096];       /* 4K * 1 = SZ_4K */
-
-} __regbase8;
-
-# define __REG32P(x)    (((__regbase32 *)((x)&~4095))->offset[((x)&4095)>>2])
-# define __REG16P(x)    (((__regbase16 *)((x)&~4095))->offset[((x)&4095)>>1])
-# define __REG8P(x)     (((__regbase8 *)((x)&~4095))->offset[((x)&4095)>>0])
-# define __REGP(x)      (((__regbase32 *)((x)&~4095))->offset[((x)&4095)>>2])
-
-/*
- * Register pointer
- */
-# define REG32_PTR(x)   (&(__REG32P(io_p2v(x))))
-# define REG16_PTR(x)   (&(__REG16P(io_p2v(x))))
-# define REG8_PTR(x)    (&(__REG8P(io_p2v(x))))
-
-/*
- * Register value
- */
-# define REG32_VAL(x)   __REG32P(io_p2v(x))
-# define REG16_VAL(x)   __REG16P(io_p2v(x))
-# define REG8_VAL(x)    __REG8P(io_p2v(x))
-
-#endif
-
-/*
- * General 32-bit Register value
- */
-# define __REG(x)       REG32_VAL((x))
-
-/*
- * Pointer and Value for Memory
- */
-# define MEM32_PTR(x)           REG32_PTR(x)
-# define MEM16_PTR(x)           REG16_PTR(x)
-# define MEM8_PTR(x)            REG8_PTR(x)
-
-# define MEM32_VAL(x)           REG32_VAL(x)
-# define MEM16_VAL(x)           REG16_VAL(x)
-# define MEM8_VAL(x)            REG8_VAL(x)
-
-/*
- * Physical Register from virtual address
- */
-# define __PREG32(x)    (io_v2p((u32)&(x)))
-# define __PREG16(x)    (io_v2p((u16)&(x)))
-# define __PREG8(x)     (io_v2p((u8)&(x)))
-
-# define __PREG(x)      __PREG32(x)
-
-#else                   /* Assembly */
-
-# define __REG(x)       io_p2v(x)
-# define __PREG(x)      io_v2p(x)
-
-# define REG32_PTR(x)           io_p2v(x)
-# define REG16_PTR(x)           io_p2v(x)
-# define REG8_PTR(x)            io_p2v(x)
-
-#endif
-
-#include "wmt.h"     /* Memory map entry */
-#include "../../wmt_clk.h"
-
-/*
- * VT8500 GPIO edge detection for IRQs:
- * IRQs are generated on High, Low, Falling-Edge, and Rising-Edge.
- * This must be called *before* the corresponding IRQ is registered.
- */
-#define GPIO_HIGH               0
-#define GPIO_LOW                1
-#define GPIO_FALLING            2
-#define GPIO_RISING             3
-
-//#define pcibios_assign_all_busses()     1
-/* no used
-#define PCIBIOS_MIN_IO          0x6000
-#define PCIBIOS_MIN_MEM         0x50000000
-*/
-/*#define PCIMEM_BASE		0xe8000000*/
-
-#endif  /* __ASM_ARCH_HARDWARE_H */
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/io.h b/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/io.h
deleted file mode 100755
index bc1ad517..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/io.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*++
-linux/include/asm-arm/arch-wmt/io.h
-
-Copyright (c) 2008  WonderMedia Technologies, Inc.
-
-This program is free software: you can redistribute it and/or modify it under the
-terms of the GNU General Public License as published by the Free Software Foundation,
-either version 2 of the License, or (at your option) any later version.
-
-This program is distributed in the hope that it will be useful, but WITHOUT
-ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-PARTICULAR PURPOSE.  See the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License along with
-this program.  If not, see <http://www.gnu.org/licenses/>.
-
-WonderMedia Technologies, Inc.
-10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
---*/
-
-#ifndef __ASM_ARCH_IO_H
-#define __ASM_ARCH_IO_H
-
-#define IO_SPACE_LIMIT 0xffffffff
-#define PCIO_BASE               0
-
-/*
- * We don't actually have real ISA nor PCI buses, but there is so many
- * drivers out there that might just work if we fake them...
- */
-#define __io(a)			(PCIO_BASE + (a))
-#define __mem_pci(a)		((unsigned long)(a))
-#define __mem_isa(a)		((unsigned long)(a))
-
-#endif
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/iomux.h b/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/iomux.h
deleted file mode 100755
index 45fba962..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/iomux.h
+++ /dev/null
@@ -1,246 +0,0 @@
-/*
- * --------------------------------------------------------------------------
- *
- *       Filename:  iomux-wm8880.h
- *
- *    Description:  gpio table for wm8880
- *
- *        Version:  0.01
- *        Created:  2013Äê04ÔÂ09ÈÕ 10ʱ16·Ö20Ãë
- *
- *         Author:  sammei (sammei@wondermedia.com.cn),
- *        Company:
- * --------------------------------------------------------------------------
- */
-
-/*
- * Base address:	0xd8110000
- * register offset:
- * 	Data Input	- 0x0000
- * 	Gpio Enable	- 0x0040
- * 	Output Enable	- 0x0080
- * 	Output Data	- 0x00c0
- * 	Pull Enable	- 0x0480
- * 	Pull Control	- 0x04c0
- * 	IO Strength	- 0x0800
- */
-
-/*       GPn  bit  irq   macro-name */
-
-/* GP0 */
-WMT_PIN(0x00, 0, 0x00, WMT_PIN_GP0_GPIO0)		/* 0 */
-WMT_PIN(0x00, 1, 0x01, WMT_PIN_GP0_GPIO1)		/* 1 */
-WMT_PIN(0x00, 2, 0x02, WMT_PIN_GP0_GPIO2)		/* 2 */
-WMT_PIN(0x00, 3, 0x03, WMT_PIN_GP0_GPIO3)		/* 3 */
-WMT_PIN(0x00, 4, 0x04, WMT_PIN_GP0_GPIO4)		/* 4 */
-WMT_PIN(0x00, 5, 0x05, WMT_PIN_GP0_GPIO5)		/* 5 */
-WMT_PIN(0x00, 6, 0x06, WMT_PIN_GP0_GPIO6)		/* 6 */
-WMT_PIN(0x00, 7, 0x07, WMT_PIN_GP0_GPIO7)		/* 7 */
-
-/* GP1 */
-WMT_PIN(0x01, 0, 0x08, WMT_PIN_GP1_GPIO8)		/* 8  */
-WMT_PIN(0x01, 1, 0x09, WMT_PIN_GP1_GPIO9)		/* 9  */
-WMT_PIN(0x01, 2, 0x0a, WMT_PIN_GP1_GPIO10)		/* 10 */
-WMT_PIN(0x01, 3, 0x0b, WMT_PIN_GP1_GPIO11)		/* 11 */
-WMT_PIN(0x01, 4, 0x0c, WMT_PIN_GP1_GPIO12)		/* 12 */
-WMT_PIN(0x01, 5, 0x0d, WMT_PIN_GP1_GPIO13)		/* 13 */
-WMT_PIN(0x01, 6, 0x0e, WMT_PIN_GP1_GPIO14)		/* 14 */
-WMT_PIN(0x01, 7, 0x0f, WMT_PIN_GP1_GPIO15)		/* 15 */
-
-/* GP2 */
-WMT_PIN(0x02, 0, 0x10, WMT_PIN_GP2_GPIO16)		/* 16 */
-WMT_PIN(0x02, 1, 0x11, WMT_PIN_GP2_GPIO17)		/* 17 */
-WMT_PIN(0x02, 2, 0x12, WMT_PIN_GP2_GPIO18)		/* 18 */
-WMT_PIN(0x02, 3, 0x13, WMT_PIN_GP2_GPIO19)		/* 19 */
-
-/* GP4 */
-WMT_PIN(0x04, 0,   -1, WMT_PIN_GP4_VDOUT0)		/* 20 */
-WMT_PIN(0x04, 1,   -1, WMT_PIN_GP4_VDOUT1)		/* 21 */
-WMT_PIN(0x04, 2,   -1, WMT_PIN_GP4_VDOUT2)		/* 22 */
-WMT_PIN(0x04, 3,   -1, WMT_PIN_GP4_VDOUT3)		/* 23 */
-WMT_PIN(0x04, 4,   -1, WMT_PIN_GP4_VDOUT4)		/* 24 */
-WMT_PIN(0x04, 5,   -1, WMT_PIN_GP4_VDOUT5)		/* 25 */
-WMT_PIN(0x04, 6,   -1, WMT_PIN_GP4_VDOUT6)		/* 26 */
-WMT_PIN(0x04, 7,   -1, WMT_PIN_GP4_VDOUT7)		/* 27 */
-
-/* GP5 */
-WMT_PIN(0x05, 0,   -1, WMT_PIN_GP5_VDOUT8)		/* 28 */
-WMT_PIN(0x05, 1,   -1, WMT_PIN_GP5_VDOUT9)		/* 29 */
-WMT_PIN(0x05, 2,   -1, WMT_PIN_GP5_VDOUT10)		/* 30 */
-WMT_PIN(0x05, 3, 0x14, WMT_PIN_GP5_VDOUT11)		/* 31 */
-WMT_PIN(0x05, 4, 0x15, WMT_PIN_GP5_VDOUT12)		/* 32 */
-WMT_PIN(0x05, 5,   -1, WMT_PIN_GP5_VDOUT13)		/* 33 */
-WMT_PIN(0x05, 6,   -1, WMT_PIN_GP5_VDOUT14)		/* 34 */
-WMT_PIN(0x05, 7,   -1, WMT_PIN_GP5_VDOUT15)		/* 35 */
-
-/* GP6 */
-WMT_PIN(0x06, 0,   -1, WMT_PIN_GP6_VDOUT16)		/* 36 */
-WMT_PIN(0x06, 1,   -1, WMT_PIN_GP6_VDOUT17)		/* 37 */
-WMT_PIN(0x06, 2, 0x16, WMT_PIN_GP6_VDOUT18)		/* 38 */
-WMT_PIN(0x06, 3, 0x17, WMT_PIN_GP6_VDOUT19)		/* 39 */
-WMT_PIN(0x06, 4, 0x18, WMT_PIN_GP6_VDOUT20)		/* 40 */
-WMT_PIN(0x06, 5, 0x19, WMT_PIN_GP6_VDOUT21)		/* 41 */
-WMT_PIN(0x06, 6,   -1, WMT_PIN_GP6_VDOUT22)		/* 42 */
-WMT_PIN(0x06, 7,   -1, WMT_PIN_GP6_VDOUT23)		/* 43 */
-
-/* GP7 */
-WMT_PIN(0x07, 0,   -1, WMT_PIN_GP7_VDDEN)		/* 44 */
-WMT_PIN(0x07, 1,   -1, WMT_PIN_GP7_VDHSYNC)		/* 45 */
-WMT_PIN(0x07, 2,   -1, WMT_PIN_GP7_VDVSYNC)		/* 46 */
-WMT_PIN(0x07, 3,   -1, WMT_PIN_GP7_VDCLK)		/* 47 */
-
-/* GP8 */
-WMT_PIN(0x08, 0,   -1, WMT_PIN_GP8_VDIN0)		/* 48 */
-WMT_PIN(0x08, 1,   -1, WMT_PIN_GP8_VDIN1)		/* 49 */
-WMT_PIN(0x08, 2,   -1, WMT_PIN_GP8_VDIN2)		/* 50 */
-WMT_PIN(0x08, 3,   -1, WMT_PIN_GP8_VDIN3)		/* 51 */
-WMT_PIN(0x08, 4,   -1, WMT_PIN_GP8_VDIN4)		/* 52 */
-WMT_PIN(0x08, 5,   -1, WMT_PIN_GP8_VDIN5)		/* 53 */
-WMT_PIN(0x08, 6,   -1, WMT_PIN_GP8_VDIN6)		/* 54 */
-WMT_PIN(0x08, 7,   -1, WMT_PIN_GP8_VDIN7)		/* 55 */
-
-/* GP9 */
-WMT_PIN(0x09, 0,   -1, WMT_PIN_GP9_VHSYNC)		/* 56 */
-WMT_PIN(0x09, 1,   -1, WMT_PIN_GP9_VVSYNC)		/* 57 */
-WMT_PIN(0x09, 2,   -1, WMT_PIN_GP9_VCLK)		/* 58 */
-
-/* GP10 */
-WMT_PIN(0x0a, 0,   -1, WMT_PIN_GP10_I2SDACDAT0)		/* 59 */
-WMT_PIN(0x0a, 1,   -1, WMT_PIN_GP10_I2SDACDAT1)		/* 60 */
-WMT_PIN(0x0a, 2,   -1, WMT_PIN_GP10_I2SDACDAT2)		/* 61 */
-WMT_PIN(0x0a, 3,   -1, WMT_PIN_GP10_I2SDACDAT3)		/* 62 */
-WMT_PIN(0x0a, 4,   -1, WMT_PIN_GP10_I2SADCDAT2)		/* 63 */
-WMT_PIN(0x0a, 5,   -1, WMT_PIN_GP10_I2SDACLRC)		/* 64 */
-WMT_PIN(0x0a, 6,   -1, WMT_PIN_GP10_I2SDACBCLK)		/* 65 */
-WMT_PIN(0x0a, 7,   -1, WMT_PIN_GP10_I2SDACMCLK)		/* 66 */
-
-/* GP11 */
-WMT_PIN(0x0b, 0,   -1, WMT_PIN_GP11_I2SADCDATA0)	/* 67 */
-WMT_PIN(0x0b, 1,   -1, WMT_PIN_GP11_I2SADCDATA1)	/* 68 */
-WMT_PIN(0x0b, 2,   -1, WMT_PIN_GP11_I2SSPDIF0)		/* 69 */
-
-/* GP12 */
-WMT_PIN(0x0c, 0,   -1, WMT_PIN_GP12_SPI0CLK)		/* 70 */
-WMT_PIN(0x0c, 1,   -1, WMT_PIN_GP12_SPI0MISO)		/* 71 */
-WMT_PIN(0x0c, 2,   -1, WMT_PIN_GP12_SPI0MOSI)		/* 72 */
-WMT_PIN(0x0c, 3,   -1, WMT_PIN_GP12_SD018SEL)		/* 73 */
-
-/* GP13 */
-WMT_PIN(0x0d, 0,   -1, WMT_PIN_GP13_SD0CLK)		/* 74 */
-WMT_PIN(0x0d, 1,   -1, WMT_PIN_GP13_SD0CMD)		/* 75 */
-WMT_PIN(0x0d, 2,   -1, WMT_PIN_GP13_SD0WP)		/* 76 */
-WMT_PIN(0x0d, 3,   -1, WMT_PIN_GP13_SD0DATA0)		/* 77 */
-WMT_PIN(0x0d, 4,   -1, WMT_PIN_GP13_SD0DATA1)		/* 78 */
-WMT_PIN(0x0d, 5,   -1, WMT_PIN_GP13_SD0DATA2)		/* 79 */
-WMT_PIN(0x0d, 6,   -1, WMT_PIN_GP13_SD0DATA3)		/* 80 */
-WMT_PIN(0x0d, 7,   -1, WMT_PIN_GP13_SD0PWRSW)		/* 81 */
-
-/* GP14 */
-WMT_PIN(0x0e, 0,   -1, WMT_PIN_GP14_NANDALE)		/* 82 */
-WMT_PIN(0x0e, 1,   -1, WMT_PIN_GP14_NANDCLE)		/* 83 */
-WMT_PIN(0x0e, 2,   -1, WMT_PIN_GP14_NANDWE)		/* 84 */
-WMT_PIN(0x0e, 3,   -1, WMT_PIN_GP14_NANDRE)		/* 85 */
-WMT_PIN(0x0e, 4,   -1, WMT_PIN_GP14_NANDWP)		/* 86 */
-WMT_PIN(0x0e, 5,   -1, WMT_PIN_GP14_NANDWPD)		/* 87 */
-WMT_PIN(0x0e, 6,   -1, WMT_PIN_GP14_NANDRB0)		/* 88 */
-WMT_PIN(0x0e, 7,   -1, WMT_PIN_GP14_NANDRB1)		/* 89 */
-
-/* GP15 */
-WMT_PIN(0x0f, 0,   -1, WMT_PIN_GP14_NANDCE0)		/* 90 */
-WMT_PIN(0x0f, 1,   -1, WMT_PIN_GP14_NANDCE1)		/* 91 */
-WMT_PIN(0x0f, 2,   -1, WMT_PIN_GP14_NANDCE2)		/* 92 */
-WMT_PIN(0x0f, 3,   -1, WMT_PIN_GP14_NANDCE3)		/* 93 */
-WMT_PIN(0x0f, 4,   -1, WMT_PIN_GP14_NANDDQS)		/* 94 */
-
-/* GP16 */
-WMT_PIN(0x10, 0,   -1, WMT_PIN_GP16_NANDDIO0)		/* 95 */
-WMT_PIN(0x10, 1,   -1, WMT_PIN_GP16_NANDDIO1)		/* 96 */
-WMT_PIN(0x10, 2,   -1, WMT_PIN_GP16_NANDDIO2)		/* 97 */
-WMT_PIN(0x10, 3,   -1, WMT_PIN_GP16_NANDDIO3)		/* 98 */
-WMT_PIN(0x10, 4,   -1, WMT_PIN_GP16_NANDDIO4)		/* 99 */
-WMT_PIN(0x10, 5,   -1, WMT_PIN_GP16_NANDDIO5)		/* 100 */
-WMT_PIN(0x10, 6,   -1, WMT_PIN_GP16_NANDDIO6)		/* 101 */
-WMT_PIN(0x10, 7,   -1, WMT_PIN_GP16_NANDDIO7)		/* 102 */
-
-/* GP17 */
-WMT_PIN(0x11, 0,   -1, WMT_PIN_GP17_I2C0SCL)		/* 103 */
-WMT_PIN(0x11, 1,   -1, WMT_PIN_GP17_I2C0SDA)		/* 104 */
-WMT_PIN(0x11, 2,   -1, WMT_PIN_GP17_I2C1SCL)		/* 105 */
-WMT_PIN(0x11, 3,   -1, WMT_PIN_GP17_I2C1SDA)		/* 106 */
-WMT_PIN(0x11, 4,   -1, WMT_PIN_GP17_I2C2SCL)		/* 107 */
-WMT_PIN(0x11, 5,   -1, WMT_PIN_GP17_I2C2SDA)		/* 108 */
-WMT_PIN(0x11, 6,   -1, WMT_PIN_GP17_C24MOUT)		/* 109 */
-
-/* GP18 */
-WMT_PIN(0x12, 0,   -1, WMT_PIN_GP18_UART0TXD)		/* 110 */
-WMT_PIN(0x12, 1,   -1, WMT_PIN_GP18_UART0RXD)		/* 111 */
-WMT_PIN(0x12, 2,   -1, WMT_PIN_GP18_UART0RTS)		/* 112 */
-WMT_PIN(0x12, 3,   -1, WMT_PIN_GP18_UART0CTS)		/* 113 */
-WMT_PIN(0x12, 4,   -1, WMT_PIN_GP18_UART1TXD)		/* 114 */
-WMT_PIN(0x12, 5,   -1, WMT_PIN_GP18_UART1RXD)		/* 115 */
-WMT_PIN(0x12, 6,   -1, WMT_PIN_GP18_UART1RTS)		/* 116 */
-WMT_PIN(0x12, 7,   -1, WMT_PIN_GP18_UART1CTS)		/* 117 */
-
-/* GP19 */
-WMT_PIN(0x13, 0,   -1, WMT_PIN_GP19_SD2DATA0)		/* 118 */
-WMT_PIN(0x13, 1,   -1, WMT_PIN_GP19_SD2DATA1)		/* 119 */
-WMT_PIN(0x13, 2,   -1, WMT_PIN_GP19_SD2DATA2)		/* 120 */
-WMT_PIN(0x13, 3,   -1, WMT_PIN_GP19_SD2DATA3)		/* 121 */
-WMT_PIN(0x13, 4,   -1, WMT_PIN_GP19_SD2CMD)		/* 122 */
-WMT_PIN(0x13, 5,   -1, WMT_PIN_GP19_SD2CLK)		/* 123 */
-WMT_PIN(0x13, 6,   -1, WMT_PIN_GP19_SD2PWRSW)		/* 124 */
-WMT_PIN(0x13, 7,   -1, WMT_PIN_GP19_SD2WP)		/* 125 */
-
-/* GP20 */
-WMT_PIN(0x14, 0,   -1, WMT_PIN_GP20_C24MHZCLKI)		/* 126 */
-WMT_PIN(0x14, 1,   -1, WMT_PIN_GP20_PWMOUT0)		/* 127 */
-
-/* GP21 */
-WMT_PIN(0x15, 0,   -1, WMT_PIN_GP21_HDMIDCSDA)		/* 128 */
-WMT_PIN(0x15, 1,   -1, WMT_PIN_GP21_HDMIDCSCL)		/* 129 */
-WMT_PIN(0x15, 2,   -1, WMT_PIN_GP21_HDMIHPD)		/* 130 */
-
-/* GP23 */
-WMT_PIN(0x17, 0,   -1, WMT_PIN_GP23_I2C3SDA)		/* 131 */
-WMT_PIN(0x17, 1,   -1, WMT_PIN_GP23_I2C3SCL)		/* 132 */
-WMT_PIN(0x17, 2,   -1, WMT_PIN_GP23_HDMICEC)		/* 133 */
-
-/* GP24 */
-WMT_PIN(0x18, 0,   -1, WMT_PIN_GP24_SFCS0)		/* 134 */
-WMT_PIN(0x18, 1,   -1, WMT_PIN_GP24_SFCS1)		/* 135 */
-WMT_PIN(0x18, 2,   -1, WMT_PIN_GP24_SFCLK)		/* 136 */
-WMT_PIN(0x18, 3,   -1, WMT_PIN_GP24_SFDI)		/* 137 */
-WMT_PIN(0x18, 4,   -1, WMT_PIN_GP24_SFDO)		/* 138 */
-
-/* GP25 */
-
-/* Reversed */
-
-/* GP26 */
-WMT_PIN(0x1a, 0,   -1, WMT_PIN_GP26_PCM1MCLK)		/* 139 */
-WMT_PIN(0x1a, 1,   -1, WMT_PIN_GP26_PCM1CLK)		/* 140 */
-WMT_PIN(0x1a, 2,   -1, WMT_PIN_GP26_PCM1SYNC)		/* 141 */
-WMT_PIN(0x1a, 3,   -1, WMT_PIN_GP26_PCM1OUT)		/* 142 */
-WMT_PIN(0x1a, 4,   -1, WMT_PIN_GP26_PCM1IN)		/* 143 */
-
-/* GP60 */
-WMT_PIN(0x3c, 0,   -1, WMT_PIN_GP60_USBSW0)		/* 144 */
-WMT_PIN(0x3c, 1,   -1, WMT_PIN_GP60_USBATTTA0)		/* 145 */
-WMT_PIN(0x3c, 2,   -1, WMT_PIN_GP60_USB0C0)		/* 146 */
-WMT_PIN(0x3c, 3,   -1, WMT_PIN_GP60_USB0C1)		/* 147 */
-WMT_PIN(0x3c, 4,   -1, WMT_PIN_GP60_USB0C2)		/* 148 */
-
-/* GP62 */
-WMT_PIN(0x3e, 0,   -1, WMT_PIN_GP62_WAKEUP0)		/* 149 */
-WMT_PIN(0x3e, 1,   -1, WMT_PIN_GP62_CIRIN)		/* 150 */
-WMT_PIN(0x3e, 2,   -1, WMT_PIN_GP62_WAKEUP2)		/* 151 */
-WMT_PIN(0x3e, 3,   -1, WMT_PIN_GP62_WAKEUP3)		/* 152 */
-WMT_PIN(0x3e, 4,   -1, WMT_PIN_GP62_WAKEUP4)		/* 153 */
-WMT_PIN(0x3e, 5,   -1, WMT_PIN_GP62_WAKEUP5)		/* 154 */
-WMT_PIN(0x3e, 6,   -1, WMT_PIN_GP62_SUSGPIO0)		/* 155 */
-WMT_PIN(0x3e, 7,   -1, WMT_PIN_GP62_SUSGPIO1)		/* 156 */
-
-/* GP63 */
-WMT_PIN(0x3f, 2,   -1, WMT_PIN_GP63_SD0CD)		/* 157 */
-WMT_PIN(0x3f, 4,   -1, WMT_PIN_GP63_SD2CD)		/* 158 */
-
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/irqs.h b/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/irqs.h
deleted file mode 100755
index 4b7f646c..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/irqs.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- *	linux/include/asm-arm/arch-wmt/irqs.h
- *
- *	Copyright (c) 2008 WonderMedia Technologies, Inc.
- *
- *	This program is free software: you can redistribute it and/or modify it under the
- *	terms of the GNU General Public License as published by the Free Software Foundation,
- *	either version 2 of the License, or (at your option) any later version.
- *
- *	This program is distributed in the hope that it will be useful, but WITHOUT
- *	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
- *	PARTICULAR PURPOSE.  See the GNU General Public License for more details.
- *	You should have received a copy of the GNU General Public License along with
- *	this program.  If not, see <http://www.gnu.org/licenses/>.
- *
- *	WonderMedia Technologies, Inc.
- *	10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
- */
-
-#ifndef __ASM_ARCH_IRQS_H
-#define __ASM_ARCH_IRQS_H
-
-/* PPI: Private Peripheral Interrupt */
-#define IRQ_PPI(x)			(x + 16)
-
-/* SPI: Shared Peripheral Interrupt */
-#define IRQ_SPI(x)			(x + 32)
-
-#define WMT_GIC_DIST_BASE	0xFE019000
-#define WMT_GIC_CPU_BASE	0xFE018100
-
-/*
- *
- *  Interrupt sources.
- *
- */
-/* #define IRQ_REVERSED      0		*/
-#define IRQ_SDC1			IRQ_SPI(1)		/* SD Host controller 0 */
-#define IRQ_SDC1_DMA		IRQ_SPI(2)
-/* IRQ_REVERSED				3      */
-#define IRQ_PMC_AXI_PWR		IRQ_SPI(4)
-#define IRQ_GPIO			IRQ_SPI(5)
-/* IRQ_REVERSED				6      */
-#define IRQ_I2C2			IRQ_SPI(7)
-#define IRQ_TZPC_NS			IRQ_SPI(8)
-#define IRQ_MC5_SECURE		IRQ_SPI(9)
-/* IRQ_REVERSED				10      */
-#define IRQ_SDC2			IRQ_SPI(11)
-#define IRQ_SDC2_DMA		IRQ_SPI(12)
-/* IRQ_REVERSED				13~14   */
-#define IRQ_I2C3			IRQ_SPI(15)
-#define IRQ_APBB			IRQ_SPI(16)
-#define IRQ_DMA_SECURE		IRQ_SPI(17)
-#define IRQ_I2C1			IRQ_SPI(18)		/* I2C controller */
-#define IRQ_I2C0			IRQ_SPI(19)		/* I2C controller */
-#define IRQ_SDC0			IRQ_SPI(20)		/* SD Host controller 1 */
-#define IRQ_SDC0_DMA		IRQ_SPI(21)
-#define IRQ_PMC_WAKEUP		IRQ_SPI(22)		/* PMC wakeup */
-#define IRQ_PCM				IRQ_SPI(23)
-#define IRQ_SPI0			IRQ_SPI(24)		/* Serial Peripheral Interface 0 */
-#define IRQ_SPI1			IRQ_SPI(25)
-#define IRQ_UHDC			IRQ_SPI(26)
-#define IRQ_DMA_NONS		IRQ_SPI(27)
-#define IRQ_NFC				IRQ_SPI(28)
-#define IRQ_NFC_DMA			IRQ_SPI(29)
-#define IRQ_PCM1			IRQ_SPI(30)
-#define IRQ_I2C4			IRQ_SPI(31)
-#define IRQ_UART0			IRQ_SPI(32)
-#define IRQ_UART1			IRQ_SPI(33)
-#define IRQ_TSC				IRQ_SPI(34)
-/* IRQ_REVERSED				35      */
-#define IRQ_OST0			IRQ_SPI(36)		/* OS Timer match 0 */
-#define IRQ_OST1			IRQ_SPI(37)		/* OS Timer match 1 */
-#define IRQ_OST2			IRQ_SPI(38)		/* OS Timer match 2 */
-#define IRQ_OST3			IRQ_SPI(39)		/* OS Timer match 3 */
-/* IRQ_REVERSED				40~41   */
-#define IRQ_OST4			IRQ_SPI(42)
-#define IRQ_OST5			IRQ_SPI(43)
-#define IRQ_OST6			IRQ_SPI(44)
-#define IRQ_OST7			IRQ_SPI(45)
-/* IRQ_REVERSED				46      */
-#define IRQ_UART2			IRQ_SPI(47)
-#define IRQ_RTC1			IRQ_SPI(48)		/* RTC_PCLK_INTR */
-#define IRQ_RTC2			IRQ_SPI(49)		/* RTC_PCLK_RTI */
-#define IRQ_UART3			IRQ_SPI(50)
-/* IRQ_REVERSED				51      */
-#define IRQ_PMC_MDM_RDY		IRQ_SPI(52)
-/* IRQ_REVERSED				53      */
-#define IRQ_PMC_MDM_WAKE_AP	IRQ_SPI(54)
-#define IRQ_CIR				IRQ_SPI(55)
-#define IRQ_JDEC			IRQ_SPI(56)
-#define IRQ_JENC			IRQ_SPI(57)
-#define IRQ_SE				IRQ_SPI(58)
-#define IRQ_VPP_IRQ0		IRQ_SPI(59)		/* SCL_INISH_INT */
-#define IRQ_VPP_IRQ1		IRQ_SPI(60)		/* SCL_INIT */
-#define IRQ_VPP_IRQ2		IRQ_SPI(61)		/* SCL444_TG_INT */
-#define IRQ_MSVD			IRQ_SPI(62)
-/* IRQ_REVERSED				63      */
-#define IRQ_DZ_0			IRQ_SPI(64)		/* AUDPRF */
-#define IRQ_DZ_1			IRQ_SPI(65)
-#define IRQ_DZ_2			IRQ_SPI(66)
-#define IRQ_DZ_3			IRQ_SPI(67)
-#define IRQ_DZ_4			IRQ_SPI(68)
-#define IRQ_DZ_5			IRQ_SPI(69)
-#define IRQ_DZ_6			IRQ_SPI(70)
-#define IRQ_DZ_7			IRQ_SPI(71)
-#define IRQ_VPP_IRQ3		IRQ_SPI(72)		/* VPP_INT */
-#define IRQ_VPP_IRQ4		IRQ_SPI(73)		/* GOVW_TG_INT */
-#define IRQ_VPP_IRQ5		IRQ_SPI(74)		/* GOVW_INT */
-#define IRQ_VPP_IRQ6		IRQ_SPI(75)		/* GOV_INT */
-#define IRQ_VPP_IRQ7		IRQ_SPI(76)		/* GE_INT */
-#define IRQ_VPP_IRQ8		IRQ_SPI(77)		/* GOVRHD_TG_INT */
-#define IRQ_VPP_IRQ9		IRQ_SPI(78)		/* DVO_INT */
-#define IRQ_VPP_IRQ10		IRQ_SPI(79)		/* VID_INT */
-#define IRQ_H264			IRQ_SPI(80)
-/* IRQ_REVERSED				81      */
-#define IRQ_MALI_PMU		IRQ_SPI(82)
-#define IRQ_MALI_GPMMU		IRQ_SPI(83)
-#define IRQ_VPP_IRQ25		IRQ_SPI(84)
-#define IRQ_VPP_IRQ26		IRQ_SPI(85)
-#define IRQ_VPP_IRQ27		IRQ_SPI(86)
-#define IRQ_VPP_IRQ28		IRQ_SPI(87)
-/* IRQ_REVERSED				88~90   */
-#define IRQ_MALI_PPMMU1		IRQ_SPI(91)
-#define IRQ_MALI_PP1		IRQ_SPI(92)
-#define IRQ_MALI_GP			IRQ_SPI(93)
-#define IRQ_MALI_PPMMU0		IRQ_SPI(94)
-#define IRQ_MALI_PP0		IRQ_SPI(95)
-#define IRQ_VPP_IRQ19		IRQ_SPI(96)
-#define IRQ_VPP_IRQ20		IRQ_SPI(97)
-/* IRQ_REVERSED				98      */
-#define IRQ_VPP_IRQ21		IRQ_SPI(99)
-#define IRQ_VPP_IRQ22		IRQ_SPI(100)
-#define IRQ_VPP_IRQ23		IRQ_SPI(101)
-#define IRQ_VPP_IRQ24		IRQ_SPI(102)
-#define IRQ_DZ_8			IRQ_SPI(103)
-#define IRQ_VPP_IRQ11		IRQ_SPI(104)	/* GOVR_INT */
-#define IRQ_VPP_IRQ12		IRQ_SPI(105)	/* GOVRSD_TG_INT */
-#define IRQ_VPP_IRQ13		IRQ_SPI(106)	/* VPU_INT */
-#define IRQ_VPP_IRQ14		IRQ_SPI(107)	/* VPU_TG_INT */
-#define IRQ_VPP_IRQ15		IRQ_SPI(108)	/* unused */
-#define IRQ_VPP_IRQ16		IRQ_SPI(109)	/* NA12 */
-#define IRQ_VPP_IRQ17		IRQ_SPI(110)	/* NA12 */
-#define IRQ_VPP_IRQ18		IRQ_SPI(111)	/* NA12 */
-#define IRQ_OST0_NS			IRQ_SPI(112)
-#define IRQ_OST1_NS			IRQ_SPI(113)
-#define IRQ_OST2_NS			IRQ_SPI(114)
-#define IRQ_OST3_NS			IRQ_SPI(115)
-#define IRQ_OST4_NS			IRQ_SPI(116)
-#define IRQ_OST5_NS			IRQ_SPI(117)
-#define IRQ_OST6_NS			IRQ_SPI(118)
-#define IRQ_OST7_NS			IRQ_SPI(119)
-#define IRQ_END				IRQ_OST7_NS
-
-#define NR_IRQS				192
-
-#endif
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/kpad.h b/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/kpad.h
deleted file mode 100755
index dce27ba7..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/kpad.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/*++
-linux/include/asm-arm/arch-wmt/kpad.h
-
-Copyright (c) 2008  WonderMedia Technologies, Inc.
-
-This program is free software: you can redistribute it and/or modify it under the
-terms of the GNU General Public License as published by the Free Software Foundation,
-either version 2 of the License, or (at your option) any later version.
-
-This program is distributed in the hope that it will be useful, but WITHOUT
-ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-PARTICULAR PURPOSE.  See the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License along with
-this program.  If not, see <http://www.gnu.org/licenses/>.
-
-WonderMedia Technologies, Inc.
-10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
---*/
-
-#ifndef __ASM_ARCH_KPAD_H
-#define __ASM_ARCH_KPAD_H
-
-#include <linux/ioport.h>
-
-/*
- * Keypad register set structure
- */
-struct kpad_regs_s {
-	unsigned int volatile kpmcr;
-	unsigned int volatile kpdcr;
-	unsigned int volatile kpicr;
-	unsigned int volatile kpstr;
-	unsigned int volatile kpmar;
-	unsigned int volatile kpdsr;
-	unsigned int volatile kpmmr;
-	unsigned int volatile kprir;
-	unsigned int volatile kpmr0;
-	unsigned int volatile kpmr1;
-	unsigned int volatile kpmr2;
-	unsigned int volatile kpmr3;
-	unsigned int volatile kpmir;
-	unsigned int volatile kpdir;
-
-};
-
-struct multi_key_s {
-	unsigned int even:8;            /* even col row input */
-	unsigned int res0:8;            /* reserved bits      */
-	unsigned int odd:8;             /* odd col row input  */
-	unsigned int res1:7;            /* reserved bits      */
-	unsigned int flag:1;            /* valid flag         */
-
-};
-
-/*
- * Keypad interrupt event counters.
- */
-struct kpad_ints_s {
-	/*
-	 * Global Status.
-	 */
-	unsigned int mda;       /* Keypad matrix manual debounce active */
-	unsigned int asa;       /* Keypad matrix automatic scan on activity */
-	unsigned int asc;       /* Keypad matrix automatic scan completed */
-	unsigned int dia;       /* Keypad direct input active */
-	unsigned int err;       /* Error keypad interrupts */
-
-};
-
-/*
- * Context need to be saved while hibernation.
- */
-struct kpad_saved_s {
-	unsigned int kpmcr;
-	unsigned int kpdcr;
-	unsigned int kpicr;
-	unsigned int kpmir;
-	unsigned int kpdir;
-
-};
-
-/*
- * wmt keypad operation structure.
- */
-struct wmt_kpad_s {
-	/* Module reference counter */
-	unsigned int ref;
-
-	/* I/O Resource */
-	struct resource *res;
-
-	/* Keypad I/O register set. */
-	struct kpad_regs_s *regs;
-
-	/* Interrupt number and status counters. */
-	unsigned int irq;
-	struct kpad_ints_s ints;
-
-};
-
-#define KPAD_IO_SIZE            sizeof(struct kpad_regs_s)
-#define KPAD_INTS_SIZE          sizeof(struct kpad_ints_s)
-
-#endif /* __ASM_ARCH_KPAD_H */
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/memory.h b/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/memory.h
deleted file mode 100755
index e8cd6316..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/memory.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*++
-linux/include/asm-arm/arch-wmt/memory.h
-
-Copyright (c) 2008  WonderMedia Technologies, Inc.
-
-This program is free software: you can redistribute it and/or modify it under the
-terms of the GNU General Public License as published by the Free Software Foundation,
-either version 2 of the License, or (at your option) any later version.
-
-This program is distributed in the hope that it will be useful, but WITHOUT
-ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-PARTICULAR PURPOSE.  See the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License along with
-this program.  If not, see <http://www.gnu.org/licenses/>.
-
-WonderMedia Technologies, Inc.
-10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
---*/
-
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-/*
- */
-#define PHYS_OFFSET	UL(0x00000000)
-
-/*
- * These are exactly the same on the S3C2410 as the
- * physical memory view.
-*/
-
-#define __virt_to_bus(x) __virt_to_phys(x)
-#define __bus_to_virt(x) __phys_to_virt(x)
-
-#define __pfn_to_bus(x) __pfn_to_phys(x)
-#define __bus_to_pfn(x)	__phys_to_pfn(x)
-
-#endif
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/serial.h b/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/serial.h
deleted file mode 100755
index 324bcca3..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/serial.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*++
-linux/include/asm-arm/arch-wmt/serial.h
-
-Copyright (c) 2008  WonderMedia Technologies, Inc.
-
-This program is free software: you can redistribute it and/or modify it under the
-terms of the GNU General Public License as published by the Free Software Foundation,
-either version 2 of the License, or (at your option) any later version.
-
-This program is distributed in the hope that it will be useful, but WITHOUT
-ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-PARTICULAR PURPOSE.  See the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License along with
-this program.  If not, see <http://www.gnu.org/licenses/>.
-
-WonderMedia Technologies, Inc.
-10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
---*/
-
-#ifndef __ASM_ARCH_SERIAL_H
-#define __ASM_ARCH_SERIAL_H
-
-/*
- * This assumes you have a 1.8432 MHz clock for your UART.
- *
- * It'd be nice if someone built a serial card with a 24.576 MHz
- * clock, since the 16550A is capable of handling a top speed of 1.5
- * megabits/second; but this requires the faster clock.
- *
- * TODO: Review BASE_BAUD definition.
- */
-#define BASE_BAUD (1843200 / 16)
-
-/* Standard COM flags */
-#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
-
-
-/*
- * Rather empty table...
- * Hardwired serial ports should be defined here.
- * PCMCIA will fill it dynamically.
- *
- * static struct old_serial_port old_serial_port[] = {
- *	SERIAL_PORT_DFNS // defined in <asm/serial.h>, used in driver/serial/8250.c
- * };
- *
- * TODO: Review if we really need it.
- */
-#define STD_SERIAL_PORT_DEFNS	\
-       /* UART	CLK     	PORT		IRQ	FLAGS		*/
-	{ 0,	BASE_BAUD,	0, 		0,	STD_COM_FLAGS },
-	{ 0,	BASE_BAUD,	0, 		0,	STD_COM_FLAGS },
-	{ 0,	BASE_BAUD,	0, 		0,	STD_COM_FLAGS },
-	{ 0,	BASE_BAUD,	0, 		0,	STD_COM_FLAGS }
-
-#define EXTRA_SERIAL_PORT_DEFNS
-
-#endif  /* __ASM_ARCH_SERIAL_H */
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/system.h b/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/system.h
deleted file mode 100755
index 478e33b8..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/system.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*++
-linux/include/asm-arm/arch-wmt/system.h
-
-Copyright (c) 2008  WonderMedia Technologies, Inc.
-
-This program is free software: you can redistribute it and/or modify it under the
-terms of the GNU General Public License as published by the Free Software Foundation,
-either version 2 of the License, or (at your option) any later version.
-
-This program is distributed in the hope that it will be useful, but WITHOUT
-ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-PARTICULAR PURPOSE.  See the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License along with
-this program.  If not, see <http://www.gnu.org/licenses/>.
-
-WonderMedia Technologies, Inc.
-10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
---*/
-
-#include <mach/hardware.h>
-
-static inline void arch_idle(void)
-{
-	cpu_do_idle();
-}
-
-extern inline void arch_reset(char mode)
-{
-	if (mode == 's') {
-		/* Jump into ROM at address 0 */
-		cpu_reset(0);
-	} else {
-		/* Use on-chip reset capability */
-		PMSR_VAL = PMSR_SWR;
-	}
-}
-
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/timex.h b/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/timex.h
deleted file mode 100755
index ee12a7c0..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/timex.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*++
-linux/include/asm-arm/arch-wmt/timex.h
-
-Copyright (c) 2008  WonderMedia Technologies, Inc.
-
-This program is free software: you can redistribute it and/or modify it under the
-terms of the GNU General Public License as published by the Free Software Foundation,
-either version 2 of the License, or (at your option) any later version.
-
-This program is distributed in the hope that it will be useful, but WITHOUT
-ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-PARTICULAR PURPOSE.  See the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License along with
-this program.  If not, see <http://www.gnu.org/licenses/>.
-
-WonderMedia Technologies, Inc.
-10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
---*/
-
-#ifndef __ASM_ARCH_TIMEX_H
-#define __ASM_ARCH_TIMEX_H
-/*
- * WMT SoC timer parameters
- */
-#define CLOCK_TICK_RATE		3000000
-#define CLOCK_TICK_FACTOR	80
-
-#endif  /* __ASM_ARCH_TIMEX_H */
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/uncompress.h b/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/uncompress.h
deleted file mode 100755
index c1a411c8..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/uncompress.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/*++
-linux/include/asm-arm/arch-wmt/uncompress.h
-
-Copyright (c) 2008  WonderMedia Technologies, Inc.
-
-This program is free software: you can redistribute it and/or modify it under the
-terms of the GNU General Public License as published by the Free Software Foundation,
-either version 2 of the License, or (at your option) any later version.
-
-This program is distributed in the hope that it will be useful, but WITHOUT
-ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-PARTICULAR PURPOSE.  See the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License along with
-this program.  If not, see <http://www.gnu.org/licenses/>.
-
-WonderMedia Technologies, Inc.
-10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
---*/
-
-#include "hardware.h"
-
-/*
- * The following code assumes the serial port has already been
- * initialized by the bootloader.  We search for the first enabled
- * port in the most probable order.  If you didn't setup a port in
- * your bootloader then nothing will appear (which might be desired).
- */
-
-/*
- * Macros to manipulate UART port.
- */
-#define UART(x)         (*(volatile unsigned long *)(serial_port + (x)))
-/*
- * This one is unique bacause UART TX FIFO access is 8-bit write.
- */
-#define UART_URTXF      (*(volatile unsigned char *)(serial_port + URTXF))
-
-static void putc(char s)
-{
-	unsigned long serial_port;
-
-	do {
-		/*
-		 * If UART0 ready, do puts().
-		 */
-		serial_port = UART0_PHY_BASE_ADDR;
-
-		if (UART(URLCR) & URLCR_TXEN)
-			break;
-	} while (0);
-
-	/*
-	 * Force to use register mode.
-	 */
-	UART(URFCR) &= ~URFCR_FIFOEN;
-
-	/*
-	 * wait for space in the UART's transmiter
-	 */
-	while (UART(URUSR) & URUSR_TXDBSY)
-		;
-
-	/*
-	 * Send the character out.
-	 */
-	UART(URTDR) = s;
-
-	/*
-	 * if there comes a LF, also do CR...
-	 *
-	 * Line Feed == '\n' == 10
-	 */
-	if (s == 10) {
-		while (UART(URUSR) & URUSR_TXDBSY)
-			;
-		/*
-		 * CR = Carriage Return == '\r' == 13
-		 */
-		UART(URTDR) = 13;
-	}
-}
-static inline void flush(void)
-{
-}
-/*
- * Nothing to do for these
- */
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/viatel.h b/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/viatel.h
deleted file mode 100755
index 5bd9c6dc..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/viatel.h
+++ /dev/null
@@ -1,178 +0,0 @@
-#ifndef VIATEL_H
-#define VIATEL_H
-
-#include <linux/irq.h>
-#include <linux/notifier.h>
-
-#define GPIO_OEM_UNKNOW (-1)
-#define GPIO_OEM_VALID(gpio) ((gpio == GPIO_OEM_UNKNOW) ? 0 : 1)
-
-//////////////////////////////////////////////////////////////////////////////////
-/*******************************  Gpio Config ***********************************/
-//////////////////////////////////////////////////////////////////////////////////
-#if defined(CONFIG_MACH_OMAP_KUNLUN)
-/*Note: must redefine the GPIO pins according to your board, keep GPIO_VIATEL_UNKNOW if not used*/
-#define GPIO_VIATEL_MDM_PWR_EN  126
-#define GPIO_VIATEL_MDM_PWR_IND GPIO_OEM_UNKNOW
-#define GPIO_VIATEL_MDM_RST     149
-#define GPIO_VIATEL_MDM_RST_IND GPIO_OEM_UNKNOW
-#define GPIO_VIATEL_MDM_BOOT_SEL GPIO_OEM_UNKNOW
-#define GPIO_VIATEL_MDM_ETS_SEL GPIO_OEM_UNKNOW
-
-#define GPIO_VIATEL_USB_AP_RDY 129
-#define GPIO_VIATEL_USB_MDM_RDY 128
-#define GPIO_VIATEL_USB_AP_WAKE_MDM 127
-#define GPIO_VIATEL_USB_MDM_WAKE_AP 173
-#endif
-
-#if defined(CONFIG_SOC_JZ4770)
-#include <asm/jzsoc.h>
-/*Note: must redefine the GPIO pins according to your board, keep GPIO_VIATEL_UNKNOW if not used*/
-#define GPIO_VIATEL_MDM_PWR_EN  GPIO_OEM_UNKNOW
-#define GPIO_VIATEL_MDM_PWR_IND GPIO_OEM_UNKNOW
-#define GPIO_VIATEL_MDM_RST     GPIO_EVDO_AP_BB_RST
-#define GPIO_VIATEL_MDM_RST_IND GPIO_OEM_UNKNOW
-#define GPIO_VIATEL_MDM_BOOT_SEL GPIO_OEM_UNKNOW
-#define GPIO_VIATEL_MDM_ETS_SEL GPIO_EVDO_ETS_SEL_CON
-
-#define GPIO_VIATEL_USB_AP_RDY GPIO_EVDO_AP_RDY_N
-#define GPIO_VIATEL_USB_MDM_RDY GPIO_EVDO_CP_RDY_N
-#define GPIO_VIATEL_USB_AP_WAKE_MDM GPIO_EVDO_AP_WAKE_BB_N
-#define GPIO_VIATEL_USB_MDM_WAKE_AP GPIO_EVDO_CP_WAKE_AP_N
-#define GPIO_VIATEL_UART_MDM_WAKE_AP GPIO_EVDO_AP_REV_GPIO5
-#define GPIO_VIATEL_UART_AP_RDY GPIO_EVDO_AP_REV_GPIO3
-#endif
-
-#if defined(EVDO_DT_SUPPORT)
-#include <mach/mt6575_gpio.h>
-#include <mach/eint.h>
-
-/*Note: must redefine the GPIO pins according to your board, keep GPIO_VIATEL_UNKNOW if not used*/
-#define GPIO_VIATEL_MDM_PWR_EN  GPIO192
-#define GPIO_VIATEL_MDM_PWR_IND GPIO_OEM_UNKNOW //GPIO193
-#define GPIO_VIATEL_MDM_RST     GPIO188
-#define GPIO_VIATEL_MDM_RST_IND GPIO189
-#define GPIO_VIATEL_MDM_BOOT_SEL GPIO_OEM_UNKNOW //GPIO196
-#define GPIO_VIATEL_MDM_ETS_SEL GPIO_OEM_UNKNOW
-
-#define GPIO_VIATEL_USB_AP_RDY GPIO209
-#define GPIO_VIATEL_USB_MDM_RDY GPIO202
-#define GPIO_VIATEL_USB_AP_WAKE_MDM GPIO201
-#define GPIO_VIATEL_USB_MDM_WAKE_AP GPIO207
-
-#define GPIO_VIATEL_UART_MDM_WAKE_AP GPIO193
-#define GPIO_VIATEL_UART_AP_RDY GPIO196
-
-#endif
-
-
-#define EVDO_WMT8850 1
-#if defined(EVDO_WMT8850)
-//#include <mach/hardware.h>
-
-#define GPIO_VIATEL_UART_MDM_WAKE_AP 		-1		//not use
-#define GPIO_VIATEL_UART_AP_RDY 			-2		//not use
-#define GPIO_VIATEL_USB_AP_RDY 				 0  
-#define GPIO_VIATEL_USB_MDM_RDY 			 1
-#define GPIO_VIATEL_USB_AP_WAKE_MDM 		 2
-#define GPIO_VIATEL_USB_MDM_WAKE_AP 		 3
-
-int oem_gpio_convert_init(void);
-#endif
-//////////////////////////////////////////////////////////////////////////////////
-/****************************** Gpio Function   *********************************/
-//////////////////////////////////////////////////////////////////////////////////
-int oem_gpio_request(int gpio, const char *label);
-void oem_gpio_free(int gpio);
-/*config the gpio to be input for irq if the SOC need*/
-int oem_gpio_direction_input_for_irq(int gpio);
-int oem_gpio_direction_output(int gpio, int value);
-int oem_gpio_output(int gpio, int value);
-int oem_gpio_get_value(int gpio);
-int oem_gpio_to_irq(int gpio);
-int oem_irq_to_gpio(int irq);
-int oem_gpio_set_irq_type(int gpio, unsigned int type);
-int oem_gpio_request_irq(int gpio, irq_handler_t handler, unsigned long flags,
-	    const char *name, void *dev);
-void oem_gpio_irq_mask(int gpio);
-void oem_gpio_irq_unmask(int gpio);
-int oem_gpio_irq_isenable(int gpio);
-int oem_gpio_irq_isint(int gpio);
-int oem_gpio_irq_clear(int gpio);
-
-
-//////////////////////////////////////////////////////////////////////////////////
-/*******************************  Sync Control **********************************/
-//////////////////////////////////////////////////////////////////////////////////
-/* notifer events */
-#define ASC_NTF_TX_READY      0x0001 /*notifie CBP is ready to work*/
-#define ASC_NTF_TX_UNREADY    0x0002 /*notifie CBP is not ready to work*/
-#define ASC_NTF_RX_PREPARE    0x1001 /* notifier the device active to receive data from CBP*/
-#define ASC_NTF_RX_POST       0x1002 /* notifer the device CBP stop tx data*/
-
-#define ASC_NAME_LEN   (64)
-
-/*used to register handle*/
-struct asc_config{
-    int gpio_ready;
-    int gpio_wake;
-    /*the level which indicate ap is ready*/
-    int polar;
-    char name[ASC_NAME_LEN];
-};
-
-/*Used to registe user accoring to handle*/
-struct asc_infor {
-    void *data;
-    int (*notifier)(int, void *);
-    char name[ASC_NAME_LEN];
-};
-
-#define USB_TX_HD_NAME "UsbTxHd"
-#define USB_RX_HD_NAME "UsbRxHd"
-#define USB_TX_USER_NAME "usb"
-#define USB_RX_USER_NAME "usb"
-#define RAWBULK_TX_USER_NAME "rawbulk"
-#define RAWBULK_RX_USER_NAME "rawbulk"
-
-#define UART_TX_HD_NAME "UartTxHd"
-#define UART_RX_HD_NAME "UartRxHd"
-#define UART_TX_USER_NAME "uart"
-#define UART_RX_USER_NAME "uart"
-
-#define ASC_PATH(hd, user) hd"."user
-
-int asc_tx_register_handle(struct asc_config *cfg);
-int asc_tx_add_user(const char *name, struct asc_infor *infor);
-void asc_tx_del_user(const char *path);
-int asc_tx_get_ready(const char *path, int sync);
-int asc_tx_put_ready(const char *path, int sync);
-int asc_tx_auto_ready(const char *name, int sync);
-int asc_tx_check_ready(const char *name);
-int asc_tx_set_auto_delay(const char *name, int delay);
-int asc_tx_user_count(const char *path);
-void asc_tx_reset(const char *name);
-
-int asc_rx_register_handle(struct asc_config *cfg);
-int asc_rx_add_user(const char *name, struct asc_infor *infor);
-void asc_rx_del_user(const char *path);
-int asc_rx_confirm_ready(const char *name, int ready);
-void asc_rx_reset(const char *name);
-int asc_rx_check_on_start(const char *name);
-
-//////////////////////////////////////////////////////////////////////////////////
-/*******************************  Power Control *********************************/
-//////////////////////////////////////////////////////////////////////////////////
-/* modem event notification values */
-enum clock_event_nofitiers {
-	MDM_EVT_NOTIFY_POWER_ON = 0,
-	MDM_EVT_NOTIFY_POWER_OFF,
-	MDM_EVT_NOTIFY_RESET_ON,
-	MDM_EVT_NOTIFY_RESET_OFF,
-	MDM_EVT_NOTIFY_NUM
-};
-
-void modem_notify_event(unsigned long event);
-int modem_register_notifier(struct notifier_block *nb);
-int modem_unregister_notifier(struct notifier_block *nb);
-#endif
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/vmalloc.h b/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/vmalloc.h
deleted file mode 100755
index 6ca87ae5..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/vmalloc.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*++
-	linux/include/asm-arm/arch-wmt/vmalloc.h
-
-	Copyright (c) 2008  WonderMedia Technologies, Inc.
-
-	This program is free software: you can redistribute it and/or modify it under the
-	terms of the GNU General Public License as published by the Free Software Foundation,
-	either version 2 of the License, or (at your option) any later version.
-
-	This program is distributed in the hope that it will be useful, but WITHOUT
-	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-	PARTICULAR PURPOSE.  See the GNU General Public License for more details.
-	You should have received a copy of the GNU General Public License along with
-	this program.  If not, see <http://www.gnu.org/licenses/>.
-
-	WonderMedia Technologies, Inc.
-	10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
---*/
-
-
-/*
- * Just any arbitrary offset to the start of the vmalloc VM area: the
- * current 8MB value just means that there will be a 8MB "hole" after the
- * physical memory until the kernel virtual memory starts.  That means that
- * any out-of-bounds memory accesses will hopefully be caught.
- * The vmalloc() routines leaves a hole of 4kB between each vmalloced
- * area for the same reason. ;)
- */
-#define VMALLOC_OFFSET	  (8*1024*1024)
-#define VMALLOC_START	  (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
-#define VMALLOC_END       (0xFE000000)
-
-/* #define MODULE_START	(PAGE_OFFSET - 16*1048576) */
-/* #define MODULE_END	(PAGE_OFFSET) */
-
-/*
- * VMALLOC_START
- * VMALLOC_END
- *      Virtual addresses bounding the vmalloc() area.  There must not be
- *      any static mappings in this area; vmalloc will overwrite them.
- *      The addresses must also be in the kernel segment (see above).
- *      Normally, the vmalloc() area starts VMALLOC_OFFSET bytes above the
- *      last virtual RAM address (found using variable high_memory).
- *
- * VMALLOC_OFFSET
- *      Offset normally incorporated into VMALLOC_START to provide a hole
- *      between virtual RAM and the vmalloc area.  We do this to allow
- *      out of bounds memory accesses (eg, something writing off the end
- *      of the mapped memory map) to be caught.  Normally set to 8MB.
- */
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt-i2c-bus.h b/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt-i2c-bus.h
deleted file mode 100755
index 9a67b22e..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt-i2c-bus.h
+++ /dev/null
@@ -1,39 +0,0 @@
-#include <mach/hardware.h>
-#include <linux/i2c.h>
-
-struct i2c_slave_dev {
-	unsigned short addr;
-	char * dev_name;
-	void (*callback)(void *data);
-	struct i2c_msg *msg;
-};
-
-struct wmt_i2cbusfifo {
-	struct i2c_msg *msg;
-	int msg_num;
-	struct list_head busfifohead;
-	int non_block;/*1:non-block, 0: block*/
-	int xfer_length;
-	int xfer_msgnum;
-	int restart;
-	void (*callback)(void *data);
-	void *data;
-};
-
-
-struct i2c_algo_wmt_data {
-	int  (*write_msg)(unsigned int slave_addr, char *buf, unsigned int length , int restart, int last) ;
-	int  (*read_msg)(unsigned int slave_addr, char *buf, unsigned int length , int restart, int last) ;
-	int  (*send_request)(struct i2c_msg *msg, int msg_num, int non_block, void (*callbck)(void *data), void *data);
-#ifdef CONFIG_SND_SOC_VT1603
-	int (*vt1603_write_for_read)(unsigned int slave_addr, char *buf, unsigned int length , int restart, int last);
-#endif
-	int  (*wait_bus_not_busy) (void);
-	void (*reset) (void);
-	void (*set_mode)(enum i2c_mode_e) ;
-	int  udelay;
-	int  timeout;
-};
-
-extern int wmt_i2c_transfer(struct i2c_msg* msgs, int msg_num, int bus_id, void (*callback)(void *data), void *data);
-
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt-spi.h b/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt-spi.h
deleted file mode 100755
index 4eced8d2..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt-spi.h
+++ /dev/null
@@ -1,311 +0,0 @@
-/*++
-	linux/arch/arm/mach-wmt/include/mach/wmt-spi.h
-
-	Copyright (c) 2008  WonderMedia Technologies, Inc.
-
-	This program is free software: you can redistribute it and/or modify it under the
-	terms of the GNU General Public License as published by the Free Software Foundation,
-	either version 2 of the License, or (at your option) any later version.
-
-	This program is distributed in the hope that it will be useful, but WITHOUT
-	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-	PARTICULAR PURPOSE.  See the GNU General Public License for more details.
-	You should have received a copy of the GNU General Public License along with
-	this program.  If not, see <http://www.gnu.org/licenses/>.
-
-	WonderMedia Technologies, Inc.
-	10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
---*/
-
-#ifndef __WMT_NEWSPI_H__
-#define __WMT_NEWSPI_H__
-
-#include <asm/dma.h>
-#include <mach/wmt_mmap.h>
-#include <mach/dma.h>
-
-/* wmt spi controller configure parameters */
-#define SPI_DMA_DISABLE    0x00
-#define SPI_DMA_ENABLE     0x01
-
-#define BITS8_PER_WORD_EN  0x01
-#define BITS16_PER_WORD_EN 0x10
-
-#define PORT_MODE_PTP      0x01
-#define PORT_MODE_MMS      0x00
-
-#define SSN_CTRL_PROGRAM   0x01
-#define SSN_CTRL_HARDWARE  0x00
-
-#define BIT_ORDER_LSB      0x00
-#define BIT_ORDER_MSB      0x01
-
-#define MAX_SPI_SLAVE      255
-#define SPI_FIFO_SIZE      0x20
-#define SPI_MIN_FREQ_HZ    (SPI_MAX_FREQ_HZ/0x7FF/2)  //22889hz actually
-#define SPI_MAX_FREQ_HZ    (100*1000*1000)            //93.707566Mhz actually
-#define SPI_DFLT_FREQ      (5*1000*1000)
-
-/**
- *struct wmt_spi_hw - wmt spi controller config information
- * @dma_support:         spi master can support dma or not
- * @num_chipselect:      how many slaves can support
- * @bits_per_word_en:    bits_per_word type support
- * @port_mode:           port mode, point-to-point or multi-master
- * @ssn_ctrl:            ssn control by program or hardware auto
- * @fifo_size:           spi tx and rx fifo size
- * @max_transfer_length  max data length in a spi transfer action
- * @min_freq_hz:         min spi frequence can be supported
- * @max_freq_hz:         max spi frenquece can be supported
- **/
-struct wmt_spi_hw {
-	u8  dma_support;
-	u8  num_chipselect;
-	u8  bits_per_word_en;
-	u8  port_mode;
-	u8  ssn_ctrl;
-	u8  fifo_size;
-	u16 max_transfer_length;
-	u32 min_freq_hz;
-	u32 max_freq_hz;
-};
-
-/**
- * struct wmt_spi_slave - wmt spi slave config infomatin
- * @dma_en:        transfer use dma or not 
- * @bits_per_word: bit_per_word this chip only can work with
- */
-struct wmt_spi_slave {
-	u8  dma_en;
-	u8  bits_per_word;
-};
-
-/**
- *struct wmt_spi  - wmt spi controller driver data
- */
-struct wmt_spi {
-	struct platform_device *pdev;  /* Driver model hookup     */
-	struct spi_master *master;     /* SPI framework hookup    */
-	void __iomem *regs_base;       /* SPI regs base of wmt */
-	int irq;                       /* SPI IRQ number          */
-
-	spinlock_t spinlock;           /* Prevent multi user confiliciton */
-	struct workqueue_struct *workqueue;
-	struct work_struct work;
-	struct list_head queue;
-	wait_queue_head_t waitq;
-
-	struct wmt_spi_hw *spi_hw_info;
-	struct wmt_spi_dma *spi_dma_info;
-};
-
-
-struct wmt_spi_dma {
-	unsigned int  rx_ch;
-	unsigned int  tx_ch;
-	dma_addr_t    phys_raddr;
-	dma_addr_t    phys_waddr;
-	u8 *io_raddr;
-	u8 *io_waddr;
-	wait_queue_head_t rx_event;
-	volatile int rx_ack;
-	wait_queue_head_t tx_event;
-	volatile int tx_ack;
-	struct dma_device_cfg_s tx_config;
-	struct dma_device_cfg_s rx_config;
-};
-
-#define SPI_CLK_MODE0   0x00
-#define SPI_CLK_MODE1   0x01
-#define SPI_CLK_MODE2   0x02
-#define SPI_CLK_MODE3   0x03
-
-#define SPI_OP_POLLING  0x00
-#define SPI_OP_DMA      0x01
-#define SPI_OP_IRQ      0x02
-
-#define POLLING_SPI_REG_TIMEOUT   0x20000
-
-#define GPIO_SPI0_CLK BIT0
-#define GPIO_SPI0_MISO BIT1
-#define GPIO_SPI0_MOSI BIT2
-#define GPIO_SPI0_SS0 BIT3
-
-#define GPIO_SPI0_CLK_PULL_EN BIT0
-#define GPIO_SPI0_MISO_PULL_EN BIT1
-#define GPIO_SPI0_MOSI_PULL_EN BIT2
-#define GPIO_SPI0_SS0_PULL_EN BIT3
-
-#define GPIO_SPI0_CLK_PULL_UP BIT0
-#define GPIO_SPI0_MISO_PULL_UP BIT1
-#define GPIO_SPI0_MOSI_PULL_UP BIT2
-#define GPIO_SPI0_SS0_PULL_UP BIT3
-/* SPI register setting related */
-#define PMC_REG_BASE            PM_CTRL_BASE_ADDR
-
-#define SPI_CLK_DIV_VAL         0x04  
-#define PLL_25MHZ               25000
-#define PLL_B_MULTI_RANGE_REG   0x0204
-#define SPI_CLK_ENABLE_REG      0x0250
-#define SPI_CLK_DIV_REG         0x033C
-
-#define SPI_CR     0X00  /* SPI Control Register Offset             */
-#define SPI_SR     0X04  /* SPI Status Register Offset              */
-#define SPI_DFCR   0X08  /* SPI Data Format Control Register Offset */
-#define SPI_CRE    0X0C
-#define SPI_TXFIFO 0X10  /* SPI TX FIFO Offset                      */
-#define SPI_RXFIFO 0X30  /* SPI RX FIFO Offset                      */
-
-/************ Control Register ************/
-/* Transmit Clock Driver*/
-#define SPI_CR_TCD_SHIFT    21
-#define SPI_CR_TCD_MASK     (BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21)
-/* Slave Selection*/
-#define SPI_CR_SS_SHIFT     19
-#define SPI_CR_SS_MASK      (BIT20|BIT19)
-/* Transmit FIFO Byte Write Method*/
-#define SPI_CR_WM_SHIFT     18
-#define SPI_CR_WM_MASK      (BIT18)
-/* Receive FIFO Reset*/
-#define SPI_CR_RFR_SHIFT    17
-#define SPI_CR_RFR_MASK     (BIT17)
-/* Transmit FIFO Reset*/
-#define SPI_CR_TFR_SHIFT    16
-#define SPI_CR_TFR_MASK     (BIT16)
-/* DMA Request Control*/
-#define SPI_CR_DRC_SHIFT    15
-#define SPI_CR_DRC_MASK     (BIT15)
-/* Receive FIFO Threshold Selection*/
-#define SPI_CR_RFTS_SHIFT   14
-#define SPI_CR_RFTS_MASK    (BIT14)
-/* Transmit FIFO Threshold Selection*/
-#define SPI_CR_TFTS_SHIFT   13
-#define SPI_CR_TFTS_MASK    (BIT13)
-/* Transmit FIFO Under-run Interrupt*/
-#define SPI_CR_TFUI_SHIFT   12
-#define SPI_CR_TFUI_MASK    (BIT12)
-/* Transmit FIFO Empty Interrupt*/
-#define SPI_CR_TFEI_SHIFT   11
-#define SPI_CR_TFEI_MASK    (BIT11)
-/* Receive FIFO Over-run Interrupt*/
-#define SPI_CR_RFOI_SHIFT   10
-#define SPI_CR_RFOI_MASK    (BIT10)
-/* Receive FIFO Full Interrupt*/
-#define SPI_CR_RFFI_SHIFT   9
-#define SPI_CR_RFFI_MASK    (BIT9)
-/* Receive FIFO Empty Interrupt*/
-#define SPI_CR_RFEI_SHIFT   8
-#define SPI_CR_RFEI_MASK    (BIT8)
-/* Threshold IRQ/DMA Selection*/
-#define SPI_CR_TIDS_SHIFT   7
-#define SPI_CR_TIDS_MASK    (BIT7)
-/* Interrupt Enable*/
-#define SPI_CR_IE_SHIFT     6
-#define SPI_CR_IE_MASK      (BIT6)
-/* Module Enable*/
-#define SPI_CR_ME_SHIFT     5
-#define SPI_CR_ME_MASK      (BIT5)
-/* Module Fault Error Interrupt*/
-#define SPI_CR_MFEI_SHIFT   4
-#define SPI_CR_MFEI_MASK    (BIT4)
-/* Master/Slave Mode Select*/
-#define SPI_CR_MSMS_SHIFT   3
-#define SPI_CR_MSMS_MASK    (BIT3)
-/* Clock Polarity Select*/
-#define SPI_CR_CPS_SHIFT    2
-#define SPI_CR_CPS_MASK     (BIT2)
-/* Clock Phase Select*/
-#define SPI_CR_CPHS_SHIFT   1
-#define SPI_CR_CPHS_MASK    (BIT1)
-/* Module Fault Error Feature*/
-#define SPI_CR_MFEF_SHIFT   0
-#define SPI_CR_MFEF_MASK    (BIT0)
-/* SPI Control Register Reset Value*/
-#define SPI_CR_RESET_MASK   SPI_CR_MSMS_MASK
-
-/************ Status Register *************/
-/* RX FIFO Count*/
-#define SPI_SR_RFCNT_SHIFT    24
-#define SPI_SR_RFCNT_MASK   (BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24)
-/* TX FIFO Count*/
-#define SPI_SR_TFCNT_SHIFT    16
-#define SPI_SR_TFCNT_MASK   (BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)
-/* TX FIFO Empty Status*/
-#define SPI_SR_TFES_SHIFT   15
-#define SPI_SR_TFES_MASK    (BIT15)
-/* Receive FIFO Threshold Passed Interrupt*/
-#define SPI_SR_RFTPI_SHIFT    14
-#define SPI_SR_RFTPI_MASK   (BIT14)
-/* Transmit FIFO Threshold Passed Interrupt*/
-#define SPI_SR_TFTPI_SHIFT    13
-#define SPI_SR_TFTPI_MASK   (BIT13)
-/* Transmit FIFO Under-run Interrupt*/
-#define SPI_SR_TFUI_SHIFT   12
-#define SPI_SR_TFUI_MASK    (BIT12)
-/* Transmit FIFO Empty Interrupt*/
-#define SPI_SR_TFEI_SHIFT   11
-#define SPI_SR_TFEI_MASK    (BIT11)
-/* Receive FIFO Over-run Interrupt*/
-#define SPI_SR_RFOI_SHIFT   10
-#define SPI_SR_RFOI_MASK    (BIT10)
-/* Receive FIFO Full Interrupt*/
-#define SPI_SR_RFFI_SHIFT   9
-#define SPI_SR_RFFI_MASK    (BIT9)
-/* Receive FIFO Empty Interrupt*/
-#define SPI_SR_RFEI_SHIFT   8
-#define SPI_SR_RFEI_MASK    (BIT8)
-/* SPI Busy*/
-#define SPI_SR_BUSY_SHIFT   7
-#define SPI_SR_BUSY_MASK    (BIT7)
-/* Mode Fault Error Interrupt*/
-#define SPI_SR_MFEI_SHIFT   4
-#define SPI_SR_MFEI_MASK    (BIT4)
-
-/****** Data Format Control Register ******/
-/*Preset Counter*/
-#define SPI_SSN_PRE_COUNTER_SHIFT 28
-#define SPI_SSN_PRE_COUNTER_MASK (BIT31|BIT30|BIT29|BIT28)
-/*HOLD EN*/
-#define SPI_SSN_HOLD_EN BIT26
-/*Microwire EN*/
-#define SPI_MICROWIRE_EN BIT25
-/*RX theshold Pass Interrupt Enable*/
-#define SPI_RX_THESHOLD_INT_EN BIT24
-/* Mode Fault Delay Count*/
-#define SPI_DFCR_MFDCNT_SHIFT 16
-#define SPI_DFCR_MFDCNT_MASK  (BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)
-/* TX Drive Count*/
-#define SPI_DFCR_TDCNT_SHIFT  8
-#define SPI_DFCR_TDCNT_MASK   (BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8)
-/* TX Drive Enable*/
-#define SPI_DFCR_TDE_SHIFT    7
-#define SPI_DFCR_TDE_MASK   (BIT7)
-/* TX No Data Value*/
-#define SPI_DFCR_TNDV_SHIFT   6
-#define SPI_DFCR_TNDV_MASK    (BIT6)
-/* Direct SSN Enable*/
-#define SPI_DFCR_DSE_SHIFT    5
-#define SPI_DFCR_DSE_MASK   (BIT5)
-/* Direct SSN Value*/
-#define SPI_DFCR_DSV_SHIFT    4
-#define SPI_DFCR_DSV_MASK   (BIT4)
-/* SSN Control*/
-#define SPI_DFCR_SC_SHIFT   3
-#define SPI_DFCR_SC_MASK    (BIT3)
-/* SSN Port Mode*/
-#define SPI_DFCR_SPM_SHIFT    2
-#define SPI_DFCR_SPM_MASK   (BIT2)
-/* Receive Significant Bit Order*/
-#define SPI_DFCR_RSBO_SHIFT   1
-#define SPI_DFCR_RSBO_MASK    (BIT1)
-/* Transmit Significant Bit Order*/
-#define SPI_DFCR_TSBO_SHIFT   0
-#define SPI_DFCR_TSBO_MASK    (BIT0)
-/* SPI Data Format Control Register Reset Value*/
-#define SPI_DFCR_RESET_MASK   (SPI_DFCR_DSV_MASK|SPI_DFCR_DSE_MASK)
-
-
-/* spi dma related */
-#define SPI_DMA_CHUNK_SIZE          1
-#define SPI_MAX_TRANSFER_LENGTH     (4*1024)
-#endif /* __VT34XX_SPI_H */
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt.h b/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt.h
deleted file mode 100755
index d4b0a0d7..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*++
-linux/include/asm-arm/arch-wmt/wmt.h
-
-Copyright (c) 2008  WonderMedia Technologies, Inc.
-
-This program is free software: you can redistribute it and/or modify it under the
-terms of the GNU General Public License as published by the Free Software Foundation,
-either version 2 of the License, or (at your option) any later version.
-
-This program is distributed in the hope that it will be useful, but WITHOUT
-ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-PARTICULAR PURPOSE.  See the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License along with
-this program.  If not, see <http://www.gnu.org/licenses/>.
-
-WonderMedia Technologies, Inc.
-10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
---*/
-
-/* Be sure that virtual mapping is defined right */
-#ifndef __ASM_ARCH_HARDWARE_H
-#error "You must include hardware.h, not wmt.h"
-#endif
-
-#ifndef __WMT_H
-#define __WMT_H
-#include "wmt_mmap.h"        /* register base address definitions */
-#include "common_def.h"      /* common define */
-#include "wmt_scc.h"         /* system configuration controller */
-#include "wmt_sdmmc.h"       /* sd/mmc card controller */
-#include "wmt_uart.h"        /* uart controller */
-#include "wmt_rtc.h"         /* real time clock */
-#include "wmt_gpio.h"        /* gpio controller */
-#include "wmt_pmc.h"         /* power management controller */
-#include "wmt_sf.h"          /* spi flash controller */
-#include "wmt_i2s.h"         /* i2s controller */
-#include "wmt_pcm.h"         /* pcm controller */
-#include "wmt_i2c.h"         /* i2c address */
-#include "wmt_kpad.h"        /* kpad address */
-#include "wmt_mc5.h"         /* memory controller */
-
-#ifndef __ASSEMBLY__
-extern unsigned int processor_id;
-#endif
-
-#endif /* __WMT_H */
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_env.h b/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_env.h
deleted file mode 100755
index a5349988..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_env.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*++
-	Copyright (c) 2008  WonderMedia Technologies, Inc.   All Rights Reserved.
-
-	This PROPRIETARY SOFTWARE is the property of WonderMedia Technologies, Inc.
-	and may contain trade secrets and/or other confidential information of
-	WonderMedia Technologies, Inc. This file shall not be disclosed to any third
-	party, in whole or in part, without prior written consent of WonderMedia.
-
-	THIS PROPRIETARY SOFTWARE AND ANY RELATED DOCUMENTATION ARE PROVIDED AS IS,
-	WITH ALL FAULTS, AND WITHOUT WARRANTY OF ANY KIND EITHER EXPRESS OR IMPLIED,
-	AND WonderMedia TECHNOLOGIES, INC. DISCLAIMS ALL EXPRESS OR IMPLIED WARRANTIES
-	OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR
-	NON-INFRINGEMENT.
-
-	Module Name:
-
-	Revision History:
-
-	$JustDate: 2012/07/23 $
---*/
-
-int wmt_setsyspara(char *varname, char *varval);
-int wmt_getsyspara(char *varname, unsigned char *varval, int *varlen);
-int wmt_getsocinfo(unsigned int *chipid, unsigned int *bondingid);
\ No newline at end of file
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_gpio.h b/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_gpio.h
deleted file mode 100755
index f5aa1749..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_gpio.h
+++ /dev/null
@@ -1,815 +0,0 @@
-/*++
-linux/arch/arm/mach-wmt/include/mach/wmt_gpio.h
-
-Copyright (c) 2013  WonderMedia Technologies, Inc.
-
-This program is free software: you can redistribute it and/or modify it under the
-terms of the GNU General Public License as published by the Free Software Foundation,
-either version 2 of the License, or (at your option) any later version.
-
-This program is distributed in the hope that it will be useful, but WITHOUT
-ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-PARTICULAR PURPOSE.  See the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License along with
-this program.  If not, see <http://www.gnu.org/licenses/>.
-
-WonderMedia Technologies, Inc.
-10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
---*/
-
-/* Be sure that virtual mapping is defined right */
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#error "You must include hardware.h, not wmt_gpio.h"
-#endif
-
-#ifndef __WMT_GPIO_H
-/* To assert that only one occurrence is included */
-#define __WMT_GPIO_H
-
-/*=== wmt_gpio.h ================================================================
-*   Copyright (C) 2013  WonderMedia Technologies, Inc.
-*
-* MODULE       : wmt_gpio.h --
-* AUTHOR       : Kenny Chou
-* DATE         : 2009/01/07
-* DESCRIPTION  : General Purpose Input/Output definition
-*------------------------------------------------------------------------------*/
-
-/*--- History -------------------------------------------------------------------
-*Version 0.01 , Kenny Chou, 2009/01/07
-*    First version
-*
-*Version 0.02 , Tommy Huang, 2009/01/19
-*    Second version
-*
-*------------------------------------------------------------------------------*/
-/*-------------------- MODULE DEPENDENCY --------------------------------------*/
-#ifndef APPLICATION
-#else
-#endif
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#include <mach/hardware.h>
-#endif
-
-/*-------------------- EXPORTED PRIVATE CONSTANTS -----------------------------*/
-
-/*-------------------- EXPORTED PRIVATE TYPES----------------------------------*/
-
-/*-------------------- EXPORTED PRIVATE VARIABLES -----------------------------*/
-#ifdef XXX_C /* allocate memory for variables only in xxx.c */
-#       define EXTERN
-#else
-#       define EXTERN   extern
-#endif /* ifdef XXX_C */
-
-
-#undef EXTERN
-
-/*--------------------- EXPORTED PRIVATE MACROS -------------------------------*/
-#define __GPIO_BASE      GPIO_BASE_ADDR
-
-#define GIRQ_LOW                        0x00            /* Input zero generate GPIO_IRQ signal */
-#define GIRQ_HIGH                       0x01            /* Input one generate GPIO_IRQ signal */
-#define GIRQ_FALLING            0x02            /* Falling edge generate GPIO_IRQ signal */
-#define GIRQ_RISING                     0x03            /* Rising edge generate GPIO_IRQ signal */
-#define GIRQ_BOTHEDGE           0x04
-#define GIRQ_TYPEMASK           0x07
-#define GIRQ_TYPE(idx, type)    ((type & GIRQ_TYPEMASK) << (idx * 8)) /* idx must be 0-3 */
-#define GIRQ_EN_STS(idx)                ( 1 << ((idx+1)*8-1) )  /* idx must be 0-3 */
-
-#define GPIO_ID_GP0_BYTE_ADDR					(__GPIO_BASE + 0x00  )/* [0x0] */
-#define GPIO_ID_GP1_BYTE_ADDR 					(__GPIO_BASE + 0x01  )/* [0x1] */
-#define GPIO_ID_GP2_BYTE_ADDR					(__GPIO_BASE + 0x02  )/* [0x2] */
-#define GPIO_ID_GP4_VDOUT_7_0_BYTE_ADDR			(__GPIO_BASE + 0x04  )/* [0x4] */
-#define GPIO_ID_GP5_VDOUT_15_8_BYTE_ADDR		(__GPIO_BASE + 0x05  )/* [0x5] */
-#define GPIO_ID_GP6_VDOUT_23_16_BYTE_ADDR		(__GPIO_BASE + 0x06  )/* [0x6] */
-#define GPIO_ID_GP7_VD_BYTE_ADDR				(__GPIO_BASE + 0x07  )/* [0x7] */
-#define GPIO_ID_GP8_VDIN_BYTE_ADDR				(__GPIO_BASE + 0x08  )/* [0x8] */
-#define GPIO_ID_GP9_VSYNC_BYTE_ADDR 			(__GPIO_BASE + 0x09  )/* [0x9] */
-#define GPIO_ID_GP10_I2S_BYTE_ADDR				(__GPIO_BASE + 0x0A  )/* [0xA] */
-#define GPIO_ID_GP11_I2S_BYTE_ADDR      		(__GPIO_BASE + 0x0B  )/* [0xB] */
-#define GPIO_ID_GP12_SPI_BYTE_ADDR				(__GPIO_BASE + 0x0C  )/* [0xC] */
-#define GPIO_ID_GP13_SD0_BYTE_ADDR   			(__GPIO_BASE + 0x0D  )/* [0xD] */
-#define GPIO_ID_GP14_NAND_SD1_BYTE_ADDR			(__GPIO_BASE + 0x0E  )/* [0xE] */
-#define GPIO_ID_GP15_NAND_BYTE_ADDR				(__GPIO_BASE + 0x0F  )/* [0xF] */
-#define GPIO_ID_GP16_NAND_SD1_BYTE_ADDR			(__GPIO_BASE + 0x10  )/* [0x10] */
-#define GPIO_ID_GP17_I2C_BYTE_ADDR       		(__GPIO_BASE + 0x11  )/* [0x11] */
-#define GPIO_ID_GP18_UART_BYTE_ADDR				(__GPIO_BASE + 0x12  )/* [0x12] */
-#define GPIO_ID_GP19_SD2_BYTE_ADDR   	    	(__GPIO_BASE + 0x13  )/* [0x13] */
-#define GPIO_ID_GP20_PWM0_BYTE_ADDR       		(__GPIO_BASE + 0x14  )/* [0x14] */
-#define GPIO_ID_GP21_HDMI_BYTE_ADDR       		(__GPIO_BASE + 0x15  )/* [0x15] */
-#define GPIO_ID_GP23_I2C3_BYTE_ADDR	    	   	(__GPIO_BASE + 0x17  )/* [0x17] */
-#define GPIO_ID_GP24_SF_BYTE_ADDR				(__GPIO_BASE + 0x18  )/* [0x18] */
-#define GPIO_ID_GP26_PCM_BYTE_ADDR       		(__GPIO_BASE + 0x1A  )/* [0x1A] */
-#define GPIO_ID_GP60_USB_BYTE_ADDR				(__GPIO_BASE + 0x3C  )/* [0x3C] */
-#define GPIO_ID_GP62_WAKEUP_SUS_BYTE_ADDR		(__GPIO_BASE + 0x3E  )/* [0x3E] */
-#define GPIO_ID_GP63_SD02CD_BYTE_ADDR			(__GPIO_BASE + 0x3F  )/* [0x3F] */
-#define GPIO_CTRL_GP0_BYTE_ADDR 				(__GPIO_BASE + 0x40  )/* [0x40] */
-#define GPIO_CTRL_GP1_BYTE_ADDR 				(__GPIO_BASE + 0x41  )/* [0x41] */
-#define GPIO_CTRL_GP2_BYTE_ADDR 				(__GPIO_BASE + 0x42  )/* [0x42] */
-#define GPIO_CTRL_GP4_VDOUT_7_0_BYTE_ADDR		(__GPIO_BASE + 0x44  )/* [0x44] */
-#define GPIO_CTRL_GP5_VDOUT_15_8_BYTE_ADDR		(__GPIO_BASE + 0x45  )/* [0x45] */
-#define GPIO_CTRL_GP6_VDOUT_23_16_BYTE_ADDR		(__GPIO_BASE + 0x46  )/* [0x46] */
-#define GPIO_CTRL_GP7_VD_BYTE_ADDR				(__GPIO_BASE + 0x47  )/* [0x47] */
-#define GPIO_CTRL_GP8_VDIN_BYTE_ADDR			(__GPIO_BASE + 0x48  )/* [0x48] */
-#define GPIO_CTRL_GP9_VSYNC_BYTE_ADDR 			(__GPIO_BASE + 0x49  )/* [0x49] */
-#define GPIO_CTRL_GP10_I2S_BYTE_ADDR			(__GPIO_BASE + 0x4A  )/* [0x4A] */
-#define GPIO_CTRL_GP11_I2S_BYTE_ADDR      		(__GPIO_BASE + 0x4B  )/* [0x4B] */
-#define GPIO_CTRL_GP12_SPI_BYTE_ADDR			(__GPIO_BASE + 0x4C  )/* [0x4C] */
-#define GPIO_CTRL_GP13_SD0_BYTE_ADDR       		(__GPIO_BASE + 0x4D  )/* [0x4D] */
-#define GPIO_CTRL_GP14_NAND_SD1_BYTE_ADDR		(__GPIO_BASE + 0x4E  )/* [0x4E] */
-#define GPIO_CTRL_GP15_NAND_BYTE_ADDR			(__GPIO_BASE + 0x4F  )/* [0x4F] */
-#define GPIO_CTRL_GP16_NAND_SD1_BYTE_ADDR		(__GPIO_BASE + 0x50  )/* [0x50] */
-#define GPIO_CTRL_GP17_I2C_BYTE_ADDR       		(__GPIO_BASE + 0x51  )/* [0x51] */
-#define GPIO_CTRL_GP18_UART_BYTE_ADDR			(__GPIO_BASE + 0x52  )/* [0x52] */
-#define GPIO_CTRL_GP19_SD2_BYTE_ADDR   	    	(__GPIO_BASE + 0x53  )/* [0x53] */
-#define GPIO_CTRL_GP20_PWM0_BYTE_ADDR       	(__GPIO_BASE + 0x54  )/* [0x54] */
-#define GPIO_CTRL_GP21_HDMI_BYTE_ADDR       	(__GPIO_BASE + 0x55  )/* [0x55] */
-#define GPIO_CTRL_GP23_I2C3_BYTE_ADDR	    	(__GPIO_BASE + 0x57  )/* [0x57] */
-#define GPIO_CTRL_GP24_SF_BYTE_ADDR				(__GPIO_BASE + 0x58  )/* [0x58] */
-#define GPIO_CTRL_GP26_PCM_BYTE_ADDR       		(__GPIO_BASE + 0x5A  )/* [0x5A] */
-#define GPIO_CTRL_GP60_USB_BYTE_ADDR			(__GPIO_BASE + 0x7C  )/* [0x7C] */
-#define GPIO_CTRL_GP62_WAKEUP_SUS_BYTE_ADDR		(__GPIO_BASE + 0x7E  )/* [0x7E] */
-#define GPIO_CTRL_GP63_SD02CD_BYTE_ADDR			(__GPIO_BASE + 0x7F  )/* [0x7F] */
-#define GPIO_OC_GP0_BYTE_ADDR 					(__GPIO_BASE + 0x80  )/* [0x80] */
-#define GPIO_OC_GP1_BYTE_ADDR 					(__GPIO_BASE + 0x81  )/* [0x81] */
-#define GPIO_OC_GP2_BYTE_ADDR					(__GPIO_BASE + 0x82  )/* [0x82] */
-#define GPIO_OC_GP4_VDOUT_7_0_BYTE_ADDR			(__GPIO_BASE + 0x84  )/* [0x84] */
-#define GPIO_OC_GP5_VDOUT_15_8_BYTE_ADDR		(__GPIO_BASE + 0x85  )/* [0x85] */
-#define GPIO_OC_GP6_VDOUT_23_16_BYTE_ADDR		(__GPIO_BASE + 0x86  )/* [0x86] */
-#define GPIO_OC_GP7_VD_BYTE_ADDR				(__GPIO_BASE + 0x87  )/* [0x87] */
-#define GPIO_OC_GP8_VDIN_BYTE_ADDR				(__GPIO_BASE + 0x88  )/* [0x88] */
-#define GPIO_OC_GP9_VSYNC_BYTE_ADDR 			(__GPIO_BASE + 0x89  )/* [0x89] */
-#define GPIO_OC_GP10_I2S_BYTE_ADDR				(__GPIO_BASE + 0x8A  )/* [0x8A] */
-#define GPIO_OC_GP11_I2S_BYTE_ADDR      		(__GPIO_BASE + 0x8B  )/* [0x8B] */
-#define GPIO_OC_GP12_SPI_BYTE_ADDR				(__GPIO_BASE + 0x8C  )/* [0x8C] */
-#define GPIO_OC_GP13_SD0_BYTE_ADDR   			(__GPIO_BASE + 0x8D  )/* [0x8D] */
-#define GPIO_OC_GP14_NAND_SD1_BYTE_ADDR			(__GPIO_BASE + 0x8E  )/* [0x8E] */
-#define GPIO_OC_GP15_NAND_BYTE_ADDR				(__GPIO_BASE + 0x8F  )/* [0x8F] */
-#define GPIO_OC_GP16_NAND_SD1_BYTE_ADDR			(__GPIO_BASE + 0x90  )/* [0x90] */
-#define GPIO_OC_GP17_I2C_BYTE_ADDR       		(__GPIO_BASE + 0x91  )/* [0x91] */
-#define GPIO_OC_GP18_UART_BYTE_ADDR				(__GPIO_BASE + 0x92  )/* [0x92] */
-#define GPIO_OC_GP19_SD2_BYTE_ADDR   	    	(__GPIO_BASE + 0x93  )/* [0x93] */
-#define GPIO_OC_GP20_PWM0_BYTE_ADDR       		(__GPIO_BASE + 0x94  )/* [0x94] */
-#define GPIO_OC_GP21_HDMI_BYTE_ADDR       		(__GPIO_BASE + 0x95  )/* [0x95] */
-#define GPIO_OC_GP22_I2C3_BYTE_ADDR	     	  	(__GPIO_BASE + 0x96  )/* [0x96] */
-#define GPIO_OC_GP24_SF_BYTE_ADDR				(__GPIO_BASE + 0x98  )/* [0x98] */
-#define GPIO_OC_GP26_PCM_BYTE_ADDR       		(__GPIO_BASE + 0x9A  )/* [0x9A] */
-#define GPIO_OC_GP60_USB_BYTE_ADDR				(__GPIO_BASE + 0xBC  )/* [0xBC] */
-#define GPIO_OC_GP62_WAKEUP_SUS_BYTE_ADDR		(__GPIO_BASE + 0xBE  )/* [0xBE] */
-#define GPIO_OC_GP63_SD02CD_BYTE_ADDR			(__GPIO_BASE + 0xBF  )/* [0xBF] */
-#define GPIO_OD_GP0_BYTE_ADDR 					(__GPIO_BASE + 0xC0  )/* [0xC0] */
-#define GPIO_OD_GP1_BYTE_ADDR 					(__GPIO_BASE + 0xC1  )/* [0xC1] */
-#define GPIO_OD_GP2_BYTE_ADDR					(__GPIO_BASE + 0xC2  )/* [0xC2] */
-#define GPIO_OD_GP4_VDOUT_7_0_BYTE_ADDR			(__GPIO_BASE + 0xC4  )/* [0xC4] */
-#define GPIO_OD_GP5_VDOUT_15_8_BYTE_ADDR		(__GPIO_BASE + 0xC5  )/* [0xC5] */
-#define GPIO_OD_GP6_VDOUT_23_16_BYTE_ADDR		(__GPIO_BASE + 0xC6  )/* [0xC6] */
-#define GPIO_OD_GP7_VD_BYTE_ADDR				(__GPIO_BASE + 0xC7  )/* [0xC7] */
-#define GPIO_OD_GP8_VDIN_BYTE_ADDR				(__GPIO_BASE + 0xC8  )/* [0xC8] */
-#define GPIO_OD_GP9_VSYNC_BYTE_ADDR 			(__GPIO_BASE + 0xC9  )/* [0xC9] */
-#define GPIO_OD_GP10_I2S_BYTE_ADDR				(__GPIO_BASE + 0xCA  )/* [0xCA] */
-#define GPIO_OD_GP11_I2S_BYTE_ADDR      		(__GPIO_BASE + 0xCB  )/* [0xCB] */
-#define GPIO_OD_GP12_SPI_BYTE_ADDR				(__GPIO_BASE + 0xCC  )/* [0xCC] */
-#define GPIO_OD_GP13_SD0_BYTE_ADDR   			(__GPIO_BASE + 0xCD  )/* [0xCD] */
-#define GPIO_OD_GP14_NAND_SD1_BYTE_ADDR			(__GPIO_BASE + 0xCE  )/* [0xCE] */
-#define GPIO_OD_GP15_NAND_BYTE_ADDR				(__GPIO_BASE + 0xCF  )/* [0xCF] */
-#define GPIO_OD_GP16_NAND_SD1_BYTE_ADDR			(__GPIO_BASE + 0xD0  )/* [0xD0] */
-#define GPIO_OD_GP17_I2C_BYTE_ADDR       		(__GPIO_BASE + 0xD1  )/* [0xD1] */
-#define GPIO_OD_GP18_UART_BYTE_ADDR				(__GPIO_BASE + 0xD2  )/* [0xD2] */
-#define GPIO_OD_GP19_SD2_BYTE_ADDR   	    	(__GPIO_BASE + 0xD3  )/* [0xD3] */
-#define GPIO_OD_GP20_PWM0_BYTE_ADDR       		(__GPIO_BASE + 0xD4  )/* [0xD4] */
-#define GPIO_OD_GP21_HDMI_BYTE_ADDR       		(__GPIO_BASE + 0xD5  )/* [0xD5] */
-#define GPIO_OD_GP23_I2C3_BYTE_ADDR	       		(__GPIO_BASE + 0xD7  )/* [0xD7] */
-#define GPIO_OD_GP24_SF_BYTE_ADDR				(__GPIO_BASE + 0xD8  )/* [0xD8] */
-#define GPIO_OD_GP26_PCM_BYTE_ADDR       		(__GPIO_BASE + 0xDA  )/* [0xDA] */
-#define GPIO_OD_GP60_USB_BYTE_ADDR				(__GPIO_BASE + 0xFC  )/* [0xFC] */
-#define GPIO_OD_GP62_WAKEUP_SUS_BYTE_ADDR		(__GPIO_BASE + 0xFE  )/* [0xFE] */
-#define GPIO_OD_GP63_SD02CD_BYTE_ADDR			(__GPIO_BASE + 0xFF  )/* [0xFF] */
-#define STRAP_STATUS_ADDR					(__GPIO_BASE + 0x100  )/* [0x100 ~ 0x103] */
-#define AHB_CTRL_4BYTE_ADDR 				(__GPIO_BASE + 0x108  )/* [0x108 ~ 0x10B] */
-#define USB_OP_CTRL_4BYTE_ADDR				(__GPIO_BASE + 0x10C  )/* [0x10C ~ 0x10F] */
-#define BONDING_OPTION_4BYTE_ADDR			(__GPIO_BASE + 0x110  )/* [0x110 ~ 0x113] */
-#define PIN_SHARING_SEL_4BYTE_ADDR 			(__GPIO_BASE + 0x200  )/* [0x200 ~ 0x203] */
-#define TPIU_CLK_DATA_4BYTE_ADDR 			(__GPIO_BASE + 0x244  )/* [0x244 ~ 0x247] */
-#define GPIO0_INT_REQ_TYPE_ADDR				(__GPIO_BASE + 0x300  )/* [0x300] */
-#define GPIO1_INT_REQ_TYPE_ADDR				(__GPIO_BASE + 0x301  )/* [0x301] */
-#define GPIO2_INT_REQ_TYPE_ADDR				(__GPIO_BASE + 0x302  )/* [0x302] */
-#define GPIO3_INT_REQ_TYPE_ADDR				(__GPIO_BASE + 0x303  )/* [0x303] */
-#define GPIO4_INT_REQ_TYPE_ADDR				(__GPIO_BASE + 0x304  )/* [0x304] */
-#define GPIO5_INT_REQ_TYPE_ADDR				(__GPIO_BASE + 0x305  )/* [0x305] */
-#define GPIO6_INT_REQ_TYPE_ADDR				(__GPIO_BASE + 0x306  )/* [0x306] */
-#define GPIO7_INT_REQ_TYPE_ADDR				(__GPIO_BASE + 0x307  )/* [0x307] */
-#define GPIO8_INT_REQ_TYPE_ADDR				(__GPIO_BASE + 0x308  )/* [0x308] */
-#define GPIO9_INT_REQ_TYPE_ADDR				(__GPIO_BASE + 0x309  )/* [0x309] */
-#define GPIO10_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x30A  )/* [0x30A] */
-#define GPIO11_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x30B  )/* [0x30B] */
-#define GPIO12_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x30C  )/* [0x30C] */
-#define GPIO13_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x30D  )/* [0x30D] */
-#define GPIO18_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x30E  )/* [0x30E] */
-#define GPIO19_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x30F  )/* [0x30F] */
-#define VOUT20_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x310  )/* [0x310] */
-#define VOUT21_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x311  )/* [0x311] */
-#define VOUT22_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x312  )/* [0x312] */
-#define VOUT23_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x313  )/* [0x313] */
-#define GPIO20_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x314  )/* [0x314] */
-#define GPIO21_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x315  )/* [0x315] */
-#define GPIO22_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x316  )/* [0x316] */
-#define GPIO23_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x317  )/* [0x317] */
-#define GPIO24_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x318  )/* [0x318] */
-#define GPIO25_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x319  )/* [0x319] */
-#define GPIO0_INT_REQ_STS_ADDR				(__GPIO_BASE + 0x360  )/* [0x360] */
-#define GPIO1_INT_REQ_STS_ADDR				(__GPIO_BASE + 0x361  )/* [0x361] */
-#define GPIO2_INT_REQ_STS_ADDR				(__GPIO_BASE + 0x362  )/* [0x362] */
-#define GPIO3_INT_REQ_STS_ADDR				(__GPIO_BASE + 0x363  )/* [0x363] */
-#define DRV_DVO_CLK_BYTE_ADDR				(__GPIO_BASE + 0x402  )/* [0x402] */
-#define DRV_DVO_VDEN_BYTE_ADDR				(__GPIO_BASE + 0x403  )/* [0x403] */
-#define SD0_DPCTL_4BYTE_ADDR				(__GPIO_BASE + 0x404  )/* [0x404 ~ 0x407] */
-#define SD0_DNCTL_4BYTE_ADDR				(__GPIO_BASE + 0x408  )/* [0x408 ~ 0x40B] */
-#define DRV_SD0_USB_BYTE_ADDR				(__GPIO_BASE + 0x464  )/* [0x464] */	
-#define DRV_USB_SWOC0_BYTE_ADDR				(__GPIO_BASE + 0x465  )/* [0x465] */	
-#define DRV_USB_OC12_BYTE_ADDR				(__GPIO_BASE + 0x466  )/* [0x466] */
-#define DRV_USBOC3_CIR_BYTE_ADDR			(__GPIO_BASE + 0x467  )/* [0x467] */
-#define DRV_PWREN_BYTE_ADDR					(__GPIO_BASE + 0x468  )/* [0x468] */
-#define DRV_PWREN_WAKEUP0_BYTE_ADDR			(__GPIO_BASE + 0x469  )/* [0x469] */
-#define DRV_SUSGP01_BYTE_ADDR				(__GPIO_BASE + 0x46A  )/* [0x46A] */
-#define DRV_WAKEUP23_BYTE_ADDR				(__GPIO_BASE + 0x46B  )/* [0x46B] */
-#define DRV_WAKEUP45_BYTE_ADDR				(__GPIO_BASE + 0x46C  )/* [0x46C] */
-#define DRV_I2C_BYTE_ADDR					(__GPIO_BASE + 0x46D  )/* [0x46D] */
-#define DRV_HDMI_BYTE_ADDR					(__GPIO_BASE + 0x46E  )/* [0x46E] */	
-#define PULL_EN_GP0_BYTE_ADDR				(__GPIO_BASE + 0x480  )/* [0x480] */
-#define PULL_EN_GP1_BYTE_ADDR				(__GPIO_BASE + 0x481  )/* [0x481] */
-#define PULL_EN_GP2_BYTE_ADDR				(__GPIO_BASE + 0x482  )/* [0x482] */
-#define PULL_EN_GP4_VDOUT_7_0_BYTE_ADDR		(__GPIO_BASE + 0x484  )/* [0x484] */
-#define PULL_EN_GP5_VDOUT_15_8_BYTE_ADDR	(__GPIO_BASE + 0x485  )/* [0x485] */
-#define PULL_EN_GP6_VDOUT_23_16_BYTE_ADDR	(__GPIO_BASE + 0x486  )/* [0x486] */
-#define PULL_EN_GP7_VD_BYTE_ADDR     		(__GPIO_BASE + 0x487  )/* [0x487] */
-#define PULL_EN_GP8_VDIN_BYTE_ADDR   		(__GPIO_BASE + 0x488  )/* [0x488] */
-#define PULL_EN_GP9_VSYNC_BYTE_ADDR 		(__GPIO_BASE + 0x489  )/* [0x489] */
-#define PULL_EN_GP10_I2S_BYTE_ADDR 			(__GPIO_BASE + 0x48A  )/* [0x48A] */
-#define PULL_EN_GP11_I2S_BYTE_ADDR     		(__GPIO_BASE + 0x48B  )/* [0x48B] */
-#define PULL_EN_GP12_SPI_BYTE_ADDR			(__GPIO_BASE + 0x48C  )/* [0x48C] */
-#define PULL_EN_GP13_SD0_BYTE_ADDR       	(__GPIO_BASE + 0x48D  )/* [0x48D] */
-#define PULL_EN_GP14_NAND_BYTE_ADDR      	(__GPIO_BASE + 0x48E  )/* [0x48E] */
-#define PULL_EN_GP15_NAND_BYTE_ADDR			(__GPIO_BASE + 0x48F  )/* [0x48F] */
-#define PULL_EN_GP16_NANDIO_BYTE_ADDR		(__GPIO_BASE + 0x490  )/* [0x490] */
-#define PULL_EN_GP17_I2C_BYTE_ADDR			(__GPIO_BASE + 0x491  )/* [0x491] */
-#define PULL_EN_GP18_UART_BYTE_ADDR			(__GPIO_BASE + 0x492  )/* [0x492] */
-#define PULL_EN_GP19_SD2_BYTE_ADDR			(__GPIO_BASE + 0x493  )/* [0x493] */
-#define PULL_EN_GP20_PWM0_BYTE_ADDR			(__GPIO_BASE + 0x494  )/* [0x494] */
-#define PULL_EN_GP21_HDMI_BYTE_ADDR      	(__GPIO_BASE + 0x495  )/* [0x495] */
-#define PULL_EN_GP23_I2C3_BYTE_ADDR			(__GPIO_BASE + 0x497  )/* [0x497] */
-#define PULL_EN_GP24_SF_BYTE_ADDR			(__GPIO_BASE + 0x498  )/* [0x498] */
-#define PULL_EN_GP26_PCM_BYTE_ADDR			(__GPIO_BASE + 0x49A  )/* [0x49A] */
-#define PULL_EN_GP60_USB_BYTE_ADDR			(__GPIO_BASE + 0x4BC  )/* [0x4BC] */
-#define PULL_EN_GP62_WAKEUP_SUS_BYTE_ADDR	(__GPIO_BASE + 0x4BE  )/* [0x4BE] */
-#define PULL_EN_GP63_SD02_BYTE_ADDR			(__GPIO_BASE + 0x4BF  )/* [0x4BF] */
-#define PULL_CTRL_GP0_BYTE_ADDR				(__GPIO_BASE + 0x4C0  )/* [0x4C0] */
-#define PULL_CTRL_GP1_BYTE_ADDR				(__GPIO_BASE + 0x4C1  )/* [0x4C1] */
-#define PULL_CTRL_GP2_BYTE_ADDR				(__GPIO_BASE + 0x4C2  )/* [0x4C2] */
-#define PULL_CTRL_GP4_VDOUT_7_0_BYTE_ADDR	(__GPIO_BASE + 0x4C4  )/* [0x4C4] */
-#define PULL_CTRL_GP5_VDOUT_15_8_BYTE_ADDR	(__GPIO_BASE + 0x4C5  )/* [0x4C5] */
-#define PULL_CTRL_GP6_VDOUT_23_16_BYTE_ADDR	(__GPIO_BASE + 0x4C6  )/* [0x4C6] */
-#define PULL_CTRL_GP7_VD_BYTE_ADDR			(__GPIO_BASE + 0x4C7  )/* [0x4C7] */
-#define PULL_CTRL_GP8_VDIN_BYTE_ADDR		(__GPIO_BASE + 0x4C8  )/* [0x4C8] */
-#define PULL_CTRL_GP9_VSYNC_BYTE_ADDR		(__GPIO_BASE + 0x4C9  )/* [0x4C9] */
-#define PULL_CTRL_GP10_I2S_BYTE_ADDR		(__GPIO_BASE + 0x4CA  )/* [0x4CA] */
-#define PULL_CTRL_GP11_I2S_BYTE_ADDR		(__GPIO_BASE + 0x4CB  )/* [0x4CB] */
-#define PULL_CTRL_GP12_SPI_BYTE_ADDR		(__GPIO_BASE + 0x4CC  )/* [0x4CC] */
-#define PULL_CTRL_GP13_SD0_BYTE_ADDR		(__GPIO_BASE + 0x4CD  )/* [0x4CD] */
-#define PULL_CTRL_GP14_NAND_BYTE_ADDR       (__GPIO_BASE + 0x4CE  )/* [0x4CE] */
-#define PULL_CTRL_GP15_NAND_BYTE_ADDR		(__GPIO_BASE + 0x4CF  )/* [0x4CF] */
-#define PULL_CTRL_GP16_NANDIO_BYTE_ADDR		(__GPIO_BASE + 0x4D0  )/* [0x4D0] */
-#define PULL_CTRL_GP17_I2C_BYTE_ADDR     	(__GPIO_BASE + 0x4D1  )/* [0x4D1] */
-#define PULL_CTRL_GP18_UART_BYTE_ADDR     	(__GPIO_BASE + 0x4D2  )/* [0x4D2] */
-#define PULL_CTRL_GP19_SD2_BYTE_ADDR     	(__GPIO_BASE + 0x4D3  )/* [0x4D3] */
-#define PULL_CTRL_GP20_PWM0_BYTE_ADDR      	(__GPIO_BASE + 0x4D4  )/* [0x4D4] */
-#define PULL_CTRL_GP21_HDMI_BYTE_ADDR		(__GPIO_BASE + 0x4D5  )/* [0x4D5] */
-#define PULL_CTRL_GP23_I2C3_BYTE_ADDR		(__GPIO_BASE + 0x4D7  )/* [0x4D7] */
-#define PULL_CTRL_GP24_SF_BYTE_ADDR     	(__GPIO_BASE + 0x4D8  )/* [0x4D8] */
-#define PULL_CTRL_GP26_PCM_BYTE_ADDR		(__GPIO_BASE + 0x4DA  )/* [0x4DA] */
-#define PULL_CTRL_GP27_SD0_BYTE_ADDR		(__GPIO_BASE + 0x4DB  )/* [0x4DB] */
-#define PULL_CTRL_GP60_USB_BYTE_ADDR		(__GPIO_BASE + 0x4FC  )/* [0x4FC] */
-#define PULL_CTRL_GP62_WAKEUP_SUS_BYTE_ADDR	(__GPIO_BASE + 0x4FE  )/* [0x4FE] */
-#define PULL_CTRL_GP63_SD02_BYTE_ADDR		(__GPIO_BASE + 0x4FF  )/* [0x4FF] */
-#define DRV_GPIO_7_0_4BYTE_ADDR				(__GPIO_BASE + 0x800  )/* [0x800 ~ 0x803] */
-#define DRV_GPIO_13_8_4BYTE_ADDR			(__GPIO_BASE + 0x804  )/* [0x804 ~ 0x807] */
-#define DRV_GPIO_19_14_4BYTE_ADDR			(__GPIO_BASE + 0x808  )/* [0x808 ~ 0x80B] */
-#define DRV_VDIN_3_0_4BYTE_ADDR				(__GPIO_BASE + 0x80C  )/* [0x80C ~ 0x80F] */
-#define DRV_VDIN_4_6_4BYTE_ADDR				(__GPIO_BASE + 0x810  )/* [0x810 ~ 0x813] */
-#define DRV_VDIN_SPI_4BYTE_ADDR				(__GPIO_BASE + 0x814  )/* [0x814 ~ 0x817] */
-#define DRV_SPI_NAND_4BYTE_ADDR				(__GPIO_BASE + 0x818  )/* [0x818 ~ 0x81B] */
-#define DRV_NAND_4BYTE_ADDR					(__GPIO_BASE + 0x81C  )/* [0x81C ~ 0x81F] */
-#define DRV_NANDIO_4BYTE_ADDR				(__GPIO_BASE + 0x820  )/* [0x820 ~ 0x823] */
-#define DRV_HDMI_I2C_4BYTE_ADDR				(__GPIO_BASE + 0x824  )/* [0x824 ~ 0x827] */
-#define DRV_I2C_SD0_4BYTE_ADDR				(__GPIO_BASE + 0x828  )/* [0x828 ~ 0x82B] */
-#define DRV_SD0_SD2_4BYTE_ADDR				(__GPIO_BASE + 0x82C  )/* [0x82C ~ 0x82F] */
-#define DRV_SD2_I2S_4BYTE_ADDR				(__GPIO_BASE + 0x830  )/* [0x830 ~ 0x833] */
-#define DRV_I2S_UART_4BYTE_ADDR				(__GPIO_BASE + 0x834  )/* [0x834 ~ 0x837] */
-#define DRV_UART_4BYTE_ADDR					(__GPIO_BASE + 0x838  )/* [0x838 ~ 0x83B] */
-#define DRV_SF_JTAGT_4BYTE_ADDR				(__GPIO_BASE + 0x83C  )/* [0x83C ~ 0x83F] */
-#define DRV_JTAGT_PWM_4BYTE_ADDR			(__GPIO_BASE + 0x840  )/* [0x840 ~ 0x843] */
-#define DRV_PCM_BYTE_ADDR					(__GPIO_BASE + 0x844  )/* [0x844] */
-#define DRV_SPI_BYTE_ADDR					(__GPIO_BASE + 0x84C  )/* [0x84C] */
-
-
-
-#define GPIO_ID_GP0_BYTE_REG					REG8_PTR(GPIO_ID_GP0_BYTE_ADDR )
-#define GPIO_ID_GP1_BYTE_REG 					REG8_PTR(GPIO_ID_GP1_BYTE_ADDR )
-#define GPIO_ID_GP2_BYTE_REG					REG8_PTR(GPIO_ID_GP2_BYTE_ADDR )
-#define GPIO_ID_GP4_VDOUT_7_0_BYTE_REG			REG8_PTR(GPIO_ID_GP4_VDOUT_7_0_BYTE_ADDR )
-#define GPIO_ID_GP5_VDOUT_15_8_BYTE_REG			REG8_PTR(GPIO_ID_GP5_VDOUT_15_8_BYTE_ADDR )
-#define GPIO_ID_GP6_VDOUT_23_16_BYTE_REG		REG8_PTR(GPIO_ID_GP6_VDOUT_23_16_BYTE_ADDR )
-#define GPIO_ID_GP7_VD_BYTE_REG					REG8_PTR(GPIO_ID_GP7_VD_BYTE_ADDR )
-#define GPIO_ID_GP8_VDIN_BYTE_REG				REG8_PTR(GPIO_ID_GP8_VDIN_BYTE_ADDR )
-#define GPIO_ID_GP9_VSYNC_BYTE_REG				REG8_PTR(GPIO_ID_GP9_VSYNC_BYTE_ADDR )
-#define GPIO_ID_GP10_I2S_BYTE_REG				REG8_PTR(GPIO_ID_GP10_I2S_BYTE_ADDR )
-#define GPIO_ID_GP11_I2S_BYTE_REG				REG8_PTR(GPIO_ID_GP11_I2S_BYTE_ADDR )
-#define GPIO_ID_GP12_SPI_BYTE_REG				REG8_PTR(GPIO_ID_GP12_SPI_BYTE_ADDR )
-#define GPIO_ID_GP13_SD0_BYTE_REG   		REG8_PTR(GPIO_ID_GP13_SD0_BYTE_ADDR )
-#define GPIO_ID_GP14_NAND_SD1_BYTE_REG			REG8_PTR(GPIO_ID_GP14_NAND_SD1_BYTE_ADDR )
-#define GPIO_ID_GP15_NAND_BYTE_REG				REG8_PTR(GPIO_ID_GP15_NAND_BYTE_ADDR )
-#define GPIO_ID_GP16_NAND_SD1_BYTE_REG			REG8_PTR(GPIO_ID_GP16_NAND_SD1_BYTE_ADDR )
-#define GPIO_ID_GP17_I2C_BYTE_REG       		REG8_PTR(GPIO_ID_GP17_I2C_BYTE_ADDR )
-#define GPIO_ID_GP18_UART_BYTE_REG				REG8_PTR(GPIO_ID_GP18_UART_BYTE_ADDR )
-#define GPIO_ID_GP19_SD2_BYTE_REG   	    	REG8_PTR(GPIO_ID_GP19_SD2_BYTE_ADDR )
-#define GPIO_ID_GP20_PWM0_BYTE_REG       		REG8_PTR(GPIO_ID_GP20_PWM0_BYTE_ADDR )
-#define GPIO_ID_GP21_HDMI_BYTE_REG       		REG8_PTR(GPIO_ID_GP21_HDMI_BYTE_ADDR )
-#define GPIO_ID_GP23_I2C3_BYTE_REG	    	   	REG8_PTR(GPIO_ID_GP23_I2C3_BYTE_ADDR )
-#define GPIO_ID_GP24_SF_BYTE_REG				REG8_PTR(GPIO_ID_GP24_SF_BYTE_ADDR )
-#define GPIO_ID_GP26_PCM_BYTE_REG       		REG8_PTR(GPIO_ID_GP26_PCM_BYTE_ADDR )
-#define GPIO_ID_GP60_USB_BYTE_REG				REG8_PTR(GPIO_ID_GP60_USB_BYTE_ADDR )
-#define GPIO_ID_GP62_WAKEUP_SUS_BYTE_REG		REG8_PTR(GPIO_ID_GP62_WAKEUP_SUS_BYTE_ADDR )
-#define GPIO_ID_GP63_SD02CD_BYTE_REG			REG8_PTR(GPIO_ID_GP63_SD02CD_BYTE_ADDR )
-#define GPIO_CTRL_GP0_BYTE_REG 					REG8_PTR(GPIO_CTRL_GP0_BYTE_ADDR )
-#define GPIO_CTRL_GP1_BYTE_REG 					REG8_PTR(GPIO_CTRL_GP1_BYTE_ADDR )
-#define GPIO_CTRL_GP2_BYTE_REG 					REG8_PTR(GPIO_CTRL_GP2_BYTE_ADDR )
-#define GPIO_CTRL_GP4_VDOUT_7_0_BYTE_REG		REG8_PTR(GPIO_CTRL_GP4_VDOUT_7_0_BYTE_ADDR )
-#define GPIO_CTRL_GP5_VDOUT_15_8_BYTE_REG		REG8_PTR(GPIO_CTRL_GP5_VDOUT_15_8_BYTE_ADDR )
-#define GPIO_CTRL_GP6_VDOUT_23_16_BYTE_REG		REG8_PTR(GPIO_CTRL_GP6_VDOUT_23_16_BYTE_ADDR )
-#define GPIO_CTRL_GP7_VD_BYTE_REG				REG8_PTR(GPIO_CTRL_GP7_VD_BYTE_ADDR )
-#define GPIO_CTRL_GP8_VDIN_BYTE_REG				REG8_PTR(GPIO_CTRL_GP8_VDIN_BYTE_ADDR )
-#define GPIO_CTRL_GP9_VSYNC_BYTE_REG 			REG8_PTR(GPIO_CTRL_GP9_VSYNC_BYTE_ADDR )
-#define GPIO_CTRL_GP10_I2S_BYTE_REG				REG8_PTR(GPIO_CTRL_GP10_I2S_BYTE_ADDR )
-#define GPIO_CTRL_GP11_I2S_BYTE_REG      		REG8_PTR(GPIO_CTRL_GP11_I2S_BYTE_ADDR )
-#define GPIO_CTRL_GP12_SPI_BYTE_REG				REG8_PTR(GPIO_CTRL_GP12_SPI_BYTE_ADDR )
-#define GPIO_CTRL_GP13_SD0_BYTE_REG       	REG8_PTR(GPIO_CTRL_GP13_SD0_BYTE_ADDR )
-#define GPIO_CTRL_GP14_NAND_SD1_BYTE_REG		REG8_PTR(GPIO_CTRL_GP14_NAND_SD1_BYTE_ADDR )
-#define GPIO_CTRL_GP15_NAND_BYTE_REG			REG8_PTR(GPIO_CTRL_GP15_NAND_BYTE_ADDR )
-#define GPIO_CTRL_GP16_NAND_SD1_BYTE_REG		REG8_PTR(GPIO_CTRL_GP16_NAND_SD1_BYTE_ADDR )
-#define GPIO_CTRL_GP17_I2C_BYTE_REG       		REG8_PTR(GPIO_CTRL_GP17_I2C_BYTE_ADDR )
-#define GPIO_CTRL_GP18_UART_BYTE_REG			REG8_PTR(GPIO_CTRL_GP18_UART_BYTE_ADDR )
-#define GPIO_CTRL_GP19_SD2_BYTE_REG   	    	REG8_PTR(GPIO_CTRL_GP19_SD2_BYTE_ADDR )
-#define GPIO_CTRL_GP20_PWM0_BYTE_REG       		REG8_PTR(GPIO_CTRL_GP20_PWM0_BYTE_ADDR )
-#define GPIO_CTRL_GP21_HDMI_BYTE_REG       		REG8_PTR(GPIO_CTRL_GP21_HDMI_BYTE_ADDR )
-#define GPIO_CTRL_GP23_I2C3_BYTE_REG	    	REG8_PTR(GPIO_CTRL_GP23_I2C3_BYTE_ADDR )
-#define GPIO_CTRL_GP24_SF_BYTE_REG				REG8_PTR(GPIO_CTRL_GP24_SF_BYTE_ADDR )
-#define GPIO_CTRL_GP26_PCM_BYTE_REG       		REG8_PTR(GPIO_CTRL_GP26_PCM_BYTE_ADDR )
-#define GPIO_CTRL_GP60_USB_BYTE_REG				REG8_PTR(GPIO_CTRL_GP60_USB_BYTE_ADDR )
-#define GPIO_CTRL_GP62_WAKEUP_SUS_BYTE_REG		REG8_PTR(GPIO_CTRL_GP62_WAKEUP_SUS_BYTE_ADDR )
-#define GPIO_CTRL_GP63_SD02CD_BYTE_REG			REG8_PTR(GPIO_CTRL_GP63_SD02CD_BYTE_ADDR )
-#define GPIO_OC_GP0_BYTE_REG 					REG8_PTR(GPIO_OC_GP0_BYTE_ADDR )
-#define GPIO_OC_GP1_BYTE_REG 					REG8_PTR(GPIO_OC_GP1_BYTE_ADDR )
-#define GPIO_OC_GP2_BYTE_REG					REG8_PTR(GPIO_OC_GP2_BYTE_ADDR )
-#define GPIO_OC_GP4_VDOUT_7_0_BYTE_REG			REG8_PTR(GPIO_OC_GP4_VDOUT_7_0_BYTE_ADDR )
-#define GPIO_OC_GP5_VDOUT_15_8_BYTE_REG			REG8_PTR(GPIO_OC_GP5_VDOUT_15_8_BYTE_ADDR )
-#define GPIO_OC_GP6_VDOUT_23_16_BYTE_REG		REG8_PTR(GPIO_OC_GP6_VDOUT_23_16_BYTE_ADDR )
-#define GPIO_OC_GP7_VD_BYTE_REG					REG8_PTR(GPIO_OC_GP7_VD_BYTE_ADDR )
-#define GPIO_OC_GP8_VDIN_BYTE_REG				REG8_PTR(GPIO_OC_GP8_VDIN_BYTE_ADDR )
-#define GPIO_OC_GP9_VSYNC_BYTE_REG 				REG8_PTR(GPIO_OC_GP9_VSYNC_BYTE_ADDR )
-#define GPIO_OC_GP10_I2S_BYTE_REG				REG8_PTR(GPIO_OC_GP10_I2S_BYTE_ADDR )
-#define GPIO_OC_GP11_I2S_BYTE_REG      			REG8_PTR(GPIO_OC_GP11_I2S_BYTE_ADDR )
-#define GPIO_OC_GP12_SPI_BYTE_REG				REG8_PTR(GPIO_OC_GP12_SPI_BYTE_ADDR )
-#define GPIO_OC_GP13_SD0_BYTE_REG   		REG8_PTR(GPIO_OC_GP13_SD0_BYTE_ADDR )
-#define GPIO_OC_GP14_NAND_SD1_BYTE_REG			REG8_PTR(GPIO_OC_GP14_NAND_SD1_BYTE_ADDR )
-#define GPIO_OC_GP15_NAND_BYTE_REG				REG8_PTR(GPIO_OC_GP15_NAND_BYTE_ADDR )
-#define GPIO_OC_GP16_NAND_SD1_BYTE_REG			REG8_PTR(GPIO_OC_GP16_NAND_SD1_BYTE_ADDR )
-#define GPIO_OC_GP17_I2C_BYTE_REG       		REG8_PTR(GPIO_OC_GP17_I2C_BYTE_ADDR )
-#define GPIO_OC_GP18_UART_BYTE_REG				REG8_PTR(GPIO_OC_GP18_UART_BYTE_ADDR )
-#define GPIO_OC_GP19_SD2_BYTE_REG   	    	REG8_PTR(GPIO_OC_GP19_SD2_BYTE_ADDR )
-#define GPIO_OC_GP20_PWM0_BYTE_REG       		REG8_PTR(GPIO_OC_GP20_PWM0_BYTE_ADDR )
-#define GPIO_OC_GP21_HDMI_BYTE_REG       		REG8_PTR(GPIO_OC_GP21_HDMI_BYTE_ADDR )
-#define GPIO_OC_GP22_I2C3_BYTE_REG	     	  	REG8_PTR(GPIO_OC_GP22_I2C3_BYTE_ADDR )
-#define GPIO_OC_GP24_SF_BYTE_REG				REG8_PTR(GPIO_OC_GP24_SF_BYTE_ADDR )
-#define GPIO_OC_GP26_PCM_BYTE_REG       		REG8_PTR(GPIO_OC_GP26_PCM_BYTE_ADDR )
-#define GPIO_OC_GP60_USB_BYTE_REG				REG8_PTR(GPIO_OC_GP60_USB_BYTE_ADDR )
-#define GPIO_OC_GP62_WAKEUP_SUS_BYTE_REG		REG8_PTR(GPIO_OC_GP62_WAKEUP_SUS_BYTE_ADDR )
-#define GPIO_OC_GP63_SD02CD_BYTE_REG			REG8_PTR(GPIO_OC_GP63_SD02CD_BYTE_ADDR )
-#define GPIO_OD_GP0_BYTE_REG 					REG8_PTR(GPIO_OD_GP0_BYTE_ADDR )
-#define GPIO_OD_GP1_BYTE_REG 					REG8_PTR(GPIO_OD_GP1_BYTE_ADDR )
-#define GPIO_OD_GP2_BYTE_REG					REG8_PTR(GPIO_OD_GP2_BYTE_ADDR )
-#define GPIO_OD_GP4_VDOUT_7_0_BYTE_REG			REG8_PTR(GPIO_OD_GP4_VDOUT_7_0_BYTE_ADDR )
-#define GPIO_OD_GP5_VDOUT_15_8_BYTE_REG			REG8_PTR(GPIO_OD_GP5_VDOUT_15_8_BYTE_ADDR )
-#define GPIO_OD_GP6_VDOUT_23_16_BYTE_REG		REG8_PTR(GPIO_OD_GP6_VDOUT_23_16_BYTE_ADDR )
-#define GPIO_OD_GP7_VD_BYTE_REG					REG8_PTR(GPIO_OD_GP7_VD_BYTE_ADDR )
-#define GPIO_OD_GP8_VDIN_BYTE_REG				REG8_PTR(GPIO_OD_GP8_VDIN_BYTE_ADDR )
-#define GPIO_OD_GP9_VSYNC_BYTE_REG 				REG8_PTR(GPIO_OD_GP9_VSYNC_BYTE_ADDR )
-#define GPIO_OD_GP10_I2S_BYTE_REG				REG8_PTR(GPIO_OD_GP10_I2S_BYTE_ADDR )
-#define GPIO_OD_GP11_I2S_BYTE_REG      			REG8_PTR(GPIO_OD_GP11_I2S_BYTE_ADDR )
-#define GPIO_OD_GP12_SPI_BYTE_REG				REG8_PTR(GPIO_OD_GP12_SPI_BYTE_ADDR )
-#define GPIO_OD_GP13_SD0_BYTE_REG   		REG8_PTR(GPIO_OD_GP13_SD0_BYTE_ADDR )
-#define GPIO_OD_GP14_NAND_SD1_BYTE_REG			REG8_PTR(GPIO_OD_GP14_NAND_SD1_BYTE_ADDR )
-#define GPIO_OD_GP15_NAND_BYTE_REG				REG8_PTR(GPIO_OD_GP15_NAND_BYTE_ADDR )
-#define GPIO_OD_GP16_NAND_SD1_BYTE_REG			REG8_PTR(GPIO_OD_GP16_NAND_SD1_BYTE_ADDR )
-#define GPIO_OD_GP17_I2C_BYTE_REG       		REG8_PTR(GPIO_OD_GP17_I2C_BYTE_ADDR )
-#define GPIO_OD_GP18_UART_BYTE_REG				REG8_PTR(GPIO_OD_GP18_UART_BYTE_ADDR )
-#define GPIO_OD_GP19_SD2_BYTE_REG   	    	REG8_PTR(GPIO_OD_GP19_SD2_BYTE_ADDR )
-#define GPIO_OD_GP20_PWM0_BYTE_REG       		REG8_PTR(GPIO_OD_GP20_PWM0_BYTE_ADDR )
-#define GPIO_OD_GP21_HDMI_BYTE_REG       		REG8_PTR(GPIO_OD_GP21_HDMI_BYTE_ADDR )
-#define GPIO_OD_GP23_I2C3_BYTE_REG	       		REG8_PTR(GPIO_OD_GP23_I2C3_BYTE_ADDR )
-#define GPIO_OD_GP24_SF_BYTE_REG				REG8_PTR(GPIO_OD_GP24_SF_BYTE_ADDR )
-#define GPIO_OD_GP26_PCM_BYTE_REG       		REG8_PTR(GPIO_OD_GP26_PCM_BYTE_ADDR )
-#define GPIO_OD_GP60_USB_BYTE_REG				REG8_PTR(GPIO_OD_GP60_USB_BYTE_ADDR )
-#define GPIO_OD_GP62_WAKEUP_SUS_BYTE_REG		REG8_PTR(GPIO_OD_GP62_WAKEUP_SUS_BYTE_ADDR )
-#define GPIO_OD_GP63_SD02CD_BYTE_REG			REG8_PTR(GPIO_OD_GP63_SD02CD_BYTE_ADDR )
-#define STRAP_STATUS_REG					REG32_PTR(STRAP_STATUS_ADDR )
-#define AHB_CTRL_4BYTE_REG 					REG32_PTR(AHB_CTRL_4BYTE_ADDR )
-#define USB_OP_CTRL_4BYTE_REG				REG32_PTR(USB_OP_CTRL_4BYTE_ADDR )
-#define BONDING_OPTION_4BYTE_REG			REG32_PTR(BONDING_OPTION_4BYTE_ADDR )
-#define PIN_SHARING_SEL_4BYTE_REG 			REG32_PTR(PIN_SHARING_SEL_4BYTE_ADDR )
-#define TPIU_CLK_DATA_4BYTE_REG 			REG32_PTR(TPIU_CLK_DATA_4BYTE_ADDR )
-#define GPIO0_INT_REQ_TYPE_REG				REG8_PTR(GPIO0_INT_REQ_TYPE_ADDR )
-#define GPIO1_INT_REQ_TYPE_REG				REG8_PTR(GPIO1_INT_REQ_TYPE_ADDR )
-#define GPIO2_INT_REQ_TYPE_REG				REG8_PTR(GPIO2_INT_REQ_TYPE_ADDR )
-#define GPIO3_INT_REQ_TYPE_REG				REG8_PTR(GPIO3_INT_REQ_TYPE_ADDR )
-#define GPIO4_INT_REQ_TYPE_REG				REG8_PTR(GPIO4_INT_REQ_TYPE_ADDR )
-#define GPIO5_INT_REQ_TYPE_REG				REG8_PTR(GPIO5_INT_REQ_TYPE_ADDR )
-#define GPIO6_INT_REQ_TYPE_REG				REG8_PTR(GPIO6_INT_REQ_TYPE_ADDR )
-#define GPIO7_INT_REQ_TYPE_REG				REG8_PTR(GPIO7_INT_REQ_TYPE_ADDR )
-#define GPIO8_INT_REQ_TYPE_REG				REG8_PTR(GPIO8_INT_REQ_TYPE_ADDR )
-#define GPIO9_INT_REQ_TYPE_REG				REG8_PTR(GPIO9_INT_REQ_TYPE_ADDR )
-#define GPIO10_INT_REQ_TYPE_REG				REG8_PTR(GPIO10_INT_REQ_TYPE_ADDR )
-#define GPIO11_INT_REQ_TYPE_REG				REG8_PTR(GPIO11_INT_REQ_TYPE_ADDR )
-#define GPIO12_INT_REQ_TYPE_REG				REG8_PTR(GPIO12_INT_REQ_TYPE_ADDR )
-#define GPIO13_INT_REQ_TYPE_REG				REG8_PTR(GPIO13_INT_REQ_TYPE_ADDR )
-#define GPIO18_INT_REQ_TYPE_REG				REG8_PTR(GPIO18_INT_REQ_TYPE_ADDR )
-#define GPIO19_INT_REQ_TYPE_REG				REG8_PTR(GPIO19_INT_REQ_TYPE_ADDR )
-#define VOUT20_INT_REQ_TYPE_REG				REG8_PTR(VOUT20_INT_REQ_TYPE_ADDR )
-#define VOUT21_INT_REQ_TYPE_REG				REG8_PTR(VOUT21_INT_REQ_TYPE_ADDR )
-#define VOUT22_INT_REQ_TYPE_REG				REG8_PTR(VOUT22_INT_REQ_TYPE_ADDR )
-#define VOUT23_INT_REQ_TYPE_REG				REG8_PTR(VOUT23_INT_REQ_TYPE_ADDR )
-#define GPIO20_INT_REQ_TYPE_REG				REG8_PTR(GPIO20_INT_REQ_TYPE_ADDR )
-#define GPIO21_INT_REQ_TYPE_REG				REG8_PTR(GPIO21_INT_REQ_TYPE_ADDR )
-#define GPIO22_INT_REQ_TYPE_REG				REG8_PTR(GPIO22_INT_REQ_TYPE_ADDR )
-#define GPIO23_INT_REQ_TYPE_REG				REG8_PTR(GPIO23_INT_REQ_TYPE_ADDR )
-#define GPIO24_INT_REQ_TYPE_REG				REG8_PTR(GPIO24_INT_REQ_TYPE_ADDR )
-#define GPIO25_INT_REQ_TYPE_REG				REG8_PTR(GPIO25_INT_REQ_TYPE_ADDR )
-#define GPIO0_INT_REQ_STS_REG				REG8_PTR(GPIO0_INT_REQ_STS_ADDR )
-#define GPIO1_INT_REQ_STS_REG				REG8_PTR(GPIO1_INT_REQ_STS_ADDR )
-#define GPIO2_INT_REQ_STS_REG				REG8_PTR(GPIO2_INT_REQ_STS_ADDR )
-#define GPIO3_INT_REQ_STS_REG				REG8_PTR(GPIO3_INT_REQ_STS_ADDR )
-#define DRV_DVO_CLK_BYTE_REG				REG8_PTR(DRV_DVO_CLK_BYTE_ADDR )
-#define DRV_DVO_VDEN_BYTE_REG				REG8_PTR(DRV_DVO_VDEN_BYTE_ADDR )
-#define SD0_DPCTL_4BYTE_REG					REG32_PTR(SD0_DPCTL_4BYTE_ADDR )
-#define SD0_DNCTL_4BYTE_REG					REG32_PTR(SD0_DNCTL_4BYTE_ADDR )
-#define DRV_SD0_USB_BYTE_REG				REG8_PTR(DRV_SD0_USB_BYTE_ADDR )	
-#define DRV_USB_SWOC0_BYTE_REG				REG8_PTR(DRV_USB_SWOC0_BYTE_ADDR )
-#define DRV_USB_OC12_BYTE_REG				REG8_PTR(DRV_USB_OC12_BYTE_ADDR )
-#define DRV_USBOC3_CIR_BYTE_REG				REG8_PTR(DRV_USBOC3_CIR_BYTE_ADDR )
-#define DRV_PWREN_BYTE_REG					REG8_PTR(DRV_PWREN_BYTE_ADDR )
-#define DRV_PWREN_WAKEUP0_BYTE_REG			REG8_PTR(DRV_PWREN_WAKEUP0_BYTE_ADDR )
-#define DRV_SUSGP01_BYTE_REG				REG8_PTR(DRV_SUSGP01_BYTE_ADDR )
-#define DRV_WAKEUP23_BYTE_REG				REG8_PTR(DRV_WAKEUP23_BYTE_ADDR )
-#define DRV_WAKEUP45_BYTE_REG				REG8_PTR(DRV_WAKEUP45_BYTE_ADDR )
-#define DRV_I2C_BYTE_REG					REG8_PTR(DRV_I2C_BYTE_ADDR )
-#define DRV_HDMI_BYTE_REG					REG8_PTR(DRV_HDMI_BYTE_ADDR )	
-#define PULL_EN_GP0_BYTE_REG				REG8_PTR(PULL_EN_GP0_BYTE_ADDR )
-#define PULL_EN_GP1_BYTE_REG				REG8_PTR(PULL_EN_GP1_BYTE_ADDR )
-#define PULL_EN_GP2_BYTE_REG				REG8_PTR(PULL_EN_GP2_BYTE_ADDR )
-#define PULL_EN_GP4_VDOUT_7_0_BYTE_REG		REG8_PTR(PULL_EN_GP4_VDOUT_7_0_BYTE_ADDR )
-#define PULL_EN_GP5_VDOUT_15_8_BYTE_REG		REG8_PTR(PULL_EN_GP5_VDOUT_15_8_BYTE_ADDR )
-#define PULL_EN_GP6_VDOUT_23_16_BYTE_REG	REG8_PTR(PULL_EN_GP6_VDOUT_23_16_BYTE_ADDR )
-#define PULL_EN_GP7_VD_BYTE_REG     		REG8_PTR(PULL_EN_GP7_VD_BYTE_ADDR )
-#define PULL_EN_GP8_VDIN_BYTE_REG   		REG8_PTR(PULL_EN_GP8_VDIN_BYTE_ADDR )
-#define PULL_EN_GP9_VSYNC_BYTE_REG 			REG8_PTR(PULL_EN_GP9_VSYNC_BYTE_ADDR )
-#define PULL_EN_GP10_I2S_BYTE_REG 			REG8_PTR(PULL_EN_GP10_I2S_BYTE_ADDR )
-#define PULL_EN_GP11_I2S_BYTE_REG     		REG8_PTR(PULL_EN_GP11_I2S_BYTE_ADDR )
-#define PULL_EN_GP12_SPI_BYTE_REG			REG8_PTR(PULL_EN_GP12_SPI_BYTE_ADDR )
-#define PULL_EN_GP13_SD0_BYTE_REG       	REG8_PTR(PULL_EN_GP13_SD0_BYTE_ADDR )
-#define PULL_EN_GP14_NAND_BYTE_REG      	REG8_PTR(PULL_EN_GP14_NAND_BYTE_ADDR )
-#define PULL_EN_GP15_NAND_BYTE_REG			REG8_PTR(PULL_EN_GP15_NAND_BYTE_ADDR )
-#define PULL_EN_GP16_NANDIO_BYTE_REG		REG8_PTR(PULL_EN_GP16_NANDIO_BYTE_ADDR )
-#define PULL_EN_GP17_I2C_BYTE_REG			REG8_PTR(PULL_EN_GP17_I2C_BYTE_ADDR )
-#define PULL_EN_GP18_UART_BYTE_REG			REG8_PTR(PULL_EN_GP18_UART_BYTE_ADDR )
-#define PULL_EN_GP19_SD2_BYTE_REG			REG8_PTR(PULL_EN_GP19_SD2_BYTE_ADDR )
-#define PULL_EN_GP20_PWM0_BYTE_REG			REG8_PTR(PULL_EN_GP20_PWM0_BYTE_ADDR )
-#define PULL_EN_GP21_HDMI_BYTE_REG      	REG8_PTR(PULL_EN_GP21_HDMI_BYTE_ADDR )
-#define PULL_EN_GP23_I2C3_BYTE_REG			REG8_PTR(PULL_EN_GP23_I2C3_BYTE_ADDR )
-#define PULL_EN_GP24_SF_BYTE_REG			REG8_PTR(PULL_EN_GP24_SF_BYTE_ADDR )
-#define PULL_EN_GP26_PCM_BYTE_REG			REG8_PTR(PULL_EN_GP26_PCM_BYTE_ADDR )
-#define PULL_EN_GP60_USB_BYTE_REG			REG8_PTR(PULL_EN_GP60_USB_BYTE_ADDR )
-#define PULL_EN_GP62_WAKEUP_SUS_BYTE_REG	REG8_PTR(PULL_EN_GP62_WAKEUP_SUS_BYTE_ADDR )
-#define PULL_EN_GP63_SD02_BYTE_REG			REG8_PTR(PULL_EN_GP63_SD02_BYTE_ADDR )
-#define PULL_CTRL_GP0_BYTE_REG				REG8_PTR(PULL_CTRL_GP0_BYTE_ADDR )
-#define PULL_CTRL_GP1_BYTE_REG				REG8_PTR(PULL_CTRL_GP1_BYTE_ADDR )
-#define PULL_CTRL_GP2_BYTE_REG				REG8_PTR(PULL_CTRL_GP2_BYTE_ADDR )
-#define PULL_CTRL_GP4_VDOUT_7_0_BYTE_REG	REG8_PTR(PULL_CTRL_GP4_VDOUT_7_0_BYTE_ADDR )
-#define PULL_CTRL_GP5_VDOUT_15_8_BYTE_REG	REG8_PTR(PULL_CTRL_GP5_VDOUT_15_8_BYTE_ADDR )
-#define PULL_CTRL_GP6_VDOUT_23_16_BYTE_REG	REG8_PTR(PULL_CTRL_GP6_VDOUT_23_16_BYTE_ADDR )
-#define PULL_CTRL_GP7_VD_BYTE_REG			REG8_PTR(PULL_CTRL_GP7_VD_BYTE_ADDR )
-#define PULL_CTRL_GP8_VDIN_BYTE_REG			REG8_PTR(PULL_CTRL_GP8_VDIN_BYTE_ADDR )
-#define PULL_CTRL_GP9_VSYNC_BYTE_REG		REG8_PTR(PULL_CTRL_GP9_VSYNC_BYTE_ADDR )
-#define PULL_CTRL_GP10_I2S_BYTE_REG			REG8_PTR(PULL_CTRL_GP10_I2S_BYTE_ADDR )
-#define PULL_CTRL_GP11_I2S_BYTE_REG			REG8_PTR(PULL_CTRL_GP11_I2S_BYTE_ADDR )
-#define PULL_CTRL_GP12_SPI_BYTE_REG			REG8_PTR(PULL_CTRL_GP12_SPI_BYTE_ADDR )
-#define PULL_CTRL_GP13_SD0_BYTE_REG			REG8_PTR(PULL_CTRL_GP13_SD0_BYTE_ADDR )
-#define PULL_CTRL_GP14_NAND_BYTE_REG       	REG8_PTR(PULL_CTRL_GP14_NAND_BYTE_ADDR )
-#define PULL_CTRL_GP15_NAND_BYTE_REG		REG8_PTR(PULL_CTRL_GP15_NAND_BYTE_ADDR )
-#define PULL_CTRL_GP16_NANDIO_BYTE_REG		REG8_PTR(PULL_CTRL_GP16_NANDIO_BYTE_ADDR )
-#define PULL_CTRL_GP17_I2C_BYTE_REG     	REG8_PTR(PULL_CTRL_GP17_I2C_BYTE_ADDR )
-#define PULL_CTRL_GP18_UART_BYTE_REG     	REG8_PTR(PULL_CTRL_GP18_UART_BYTE_ADDR )
-#define PULL_CTRL_GP19_SD2_BYTE_REG     	REG8_PTR(PULL_CTRL_GP19_SD2_BYTE_ADDR )
-#define PULL_CTRL_GP20_PWM0_BYTE_REG      	REG8_PTR(PULL_CTRL_GP20_PWM0_BYTE_ADDR )
-#define PULL_CTRL_GP21_HDMI_BYTE_REG		REG8_PTR(PULL_CTRL_GP21_HDMI_BYTE_ADDR )
-#define PULL_CTRL_GP23_I2C3_BYTE_REG		REG8_PTR(PULL_CTRL_GP23_I2C3_BYTE_ADDR )
-#define PULL_CTRL_GP24_SF_BYTE_REG     		REG8_PTR(PULL_CTRL_GP24_SF_BYTE_ADDR )
-#define PULL_CTRL_GP26_PCM_BYTE_REG			REG8_PTR(PULL_CTRL_GP26_PCM_BYTE_ADDR )
-#define PULL_CTRL_GP27_SD0_BYTE_REG			REG8_PTR(PULL_CTRL_GP27_SD0_BYTE_ADDR )
-#define PULL_CTRL_GP60_USB_BYTE_REG			REG8_PTR(PULL_CTRL_GP60_USB_BYTE_ADDR )
-#define PULL_CTRL_GP62_WAKEUP_SUS_BYTE_REG	REG8_PTR(PULL_CTRL_GP62_WAKEUP_SUS_BYTE_ADDR )
-#define PULL_CTRL_GP63_SD02_BYTE_REG		REG8_PTR(PULL_CTRL_GP63_SD02_BYTE_ADDR )
-#define DRV_GPIO_7_0_4BYTE_REG				REG32_PTR(DRV_GPIO_7_0_4BYTE_ADDR )
-#define DRV_GPIO_13_8_4BYTE_REG				REG32_PTR(DRV_GPIO_13_8_4BYTE_ADDR )
-#define DRV_GPIO_19_14_4BYTE_REG			REG32_PTR(DRV_GPIO_19_14_4BYTE_ADDR )
-#define DRV_VDIN_3_0_4BYTE_REG				REG32_PTR(DRV_VDIN_3_0_4BYTE_ADDR )
-#define DRV_VDIN_4_6_4BYTE_REG				REG32_PTR(DRV_VDIN_3_0_4BYTE_ADDR )
-#define DRV_VDIN_SPI_4BYTE_REG				REG32_PTR(DRV_VDIN_SPI_4BYTE_ADDR )
-#define DRV_SPI_NAND_4BYTE_REG				REG32_PTR(DRV_SPI_NAND_4BYTE_ADDR )
-#define DRV_NAND_4BYTE_REG					REG32_PTR(DRV_NAND_4BYTE_ADDR )
-#define DRV_NANDIO_4BYTE_REG				REG32_PTR(DRV_NANDIO_4BYTE_ADDR )
-#define DRV_HDMI_I2C_4BYTE_REG				REG32_PTR(DRV_HDMI_I2C_4BYTE_ADDR )
-#define DRV_I2C_SD0_4BYTE_REG				REG32_PTR(DRV_I2C_SD0_4BYTE_ADDR )
-#define DRV_SD0_SD2_4BYTE_REG				REG32_PTR(DRV_SD0_SD2_4BYTE_ADDR )
-#define DRV_SD2_I2S_4BYTE_REG				REG32_PTR(DRV_SD2_I2S_4BYTE_ADDR )
-#define DRV_I2S_UART_4BYTE_REG				REG32_PTR(DRV_I2S_UART_4BYTE_ADDR )
-#define DRV_UART_4BYTE_REG					REG32_PTR(DRV_UART_4BYTE_ADDR )
-#define DRV_SF_JTAGT_4BYTE_REG				REG32_PTR(DRV_SF_JTAGT_4BYTE_ADDR )
-#define DRV_JTAGT_PWM_4BYTE_REG				REG32_PTR(DRV_JTAGT_PWM_4BYTE_ADDR )
-#define DRV_PCM_BYTE_REG					REG8_PTR(DRV_PCM_BYTE_ADDR )
-#define DRV_SPI_BYTE_REG					REG8_PTR(DRV_SPI_BYTE_ADDR )
-
-#define GPIO_ID_GP0_BYTE_VAL					REG8_VAL(GPIO_ID_GP0_BYTE_ADDR )
-#define GPIO_ID_GP1_BYTE_VAL 					REG8_VAL(GPIO_ID_GP1_BYTE_ADDR )
-#define GPIO_ID_GP2_BYTE_VAL					REG8_VAL(GPIO_ID_GP2_BYTE_ADDR )
-#define GPIO_ID_GP4_VDOUT_7_0_BYTE_VAL			REG8_VAL(GPIO_ID_GP4_VDOUT_7_0_BYTE_ADDR )
-#define GPIO_ID_GP5_VDOUT_15_8_BYTE_VAL			REG8_VAL(GPIO_ID_GP5_VDOUT_15_8_BYTE_ADDR )
-#define GPIO_ID_GP6_VDOUT_23_16_BYTE_VAL		REG8_VAL(GPIO_ID_GP6_VDOUT_23_16_BYTE_ADDR )
-#define GPIO_ID_GP7_VD_BYTE_VAL					REG8_VAL(GPIO_ID_GP7_VD_BYTE_ADDR )
-#define GPIO_ID_GP8_VDIN_BYTE_VAL				REG8_VAL(GPIO_ID_GP8_VDIN_BYTE_ADDR )
-#define GPIO_ID_GP9_VSYNC_BYTE_VAL				REG8_VAL(GPIO_ID_GP9_VSYNC_BYTE_ADDR )
-#define GPIO_ID_GP10_I2S_BYTE_VAL				REG8_VAL(GPIO_ID_GP10_I2S_BYTE_ADDR )
-#define GPIO_ID_GP11_I2S_BYTE_VAL				REG8_VAL(GPIO_ID_GP11_I2S_BYTE_ADDR )
-#define GPIO_ID_GP12_SPI_BYTE_VAL				REG8_VAL(GPIO_ID_GP12_SPI_BYTE_ADDR )
-#define GPIO_ID_GP13_SD0_BYTE_VAL   		REG8_VAL(GPIO_ID_GP13_SD0_BYTE_ADDR )
-#define GPIO_ID_GP14_NAND_SD1_BYTE_VAL			REG8_VAL(GPIO_ID_GP14_NAND_SD1_BYTE_ADDR )
-#define GPIO_ID_GP15_NAND_BYTE_VAL				REG8_VAL(GPIO_ID_GP15_NAND_BYTE_ADDR )
-#define GPIO_ID_GP16_NAND_SD1_BYTE_VAL			REG8_VAL(GPIO_ID_GP16_NAND_SD1_BYTE_ADDR )
-#define GPIO_ID_GP17_I2C_BYTE_VAL       		REG8_VAL(GPIO_ID_GP17_I2C_BYTE_ADDR )
-#define GPIO_ID_GP18_UART_BYTE_VAL				REG8_VAL(GPIO_ID_GP18_UART_BYTE_ADDR )
-#define GPIO_ID_GP19_SD2_BYTE_VAL   	    	REG8_VAL(GPIO_ID_GP19_SD2_BYTE_ADDR )
-#define GPIO_ID_GP20_PWM0_BYTE_VAL       		REG8_VAL(GPIO_ID_GP20_PWM0_BYTE_ADDR )
-#define GPIO_ID_GP21_HDMI_BYTE_VAL       		REG8_VAL(GPIO_ID_GP21_HDMI_BYTE_ADDR )
-#define GPIO_ID_GP23_I2C3_BYTE_VAL	    	   	REG8_VAL(GPIO_ID_GP23_I2C3_BYTE_ADDR )
-#define GPIO_ID_GP24_SF_BYTE_VAL				REG8_VAL(GPIO_ID_GP24_SF_BYTE_ADDR )
-#define GPIO_ID_GP26_PCM_BYTE_VAL       		REG8_VAL(GPIO_ID_GP26_PCM_BYTE_ADDR )
-#define GPIO_ID_GP60_USB_BYTE_VAL				REG8_VAL(GPIO_ID_GP60_USB_BYTE_ADDR )
-#define GPIO_ID_GP62_WAKEUP_SUS_BYTE_VAL		REG8_VAL(GPIO_ID_GP62_WAKEUP_SUS_BYTE_ADDR )
-#define GPIO_ID_GP63_SD02CD_BYTE_VAL			REG8_VAL(GPIO_ID_GP63_SD02CD_BYTE_ADDR )
-#define GPIO_CTRL_GP0_BYTE_VAL 					REG8_VAL(GPIO_CTRL_GP0_BYTE_ADDR )
-#define GPIO_CTRL_GP1_BYTE_VAL 					REG8_VAL(GPIO_CTRL_GP1_BYTE_ADDR )
-#define GPIO_CTRL_GP2_BYTE_VAL 					REG8_VAL(GPIO_CTRL_GP2_BYTE_ADDR )
-#define GPIO_CTRL_GP4_VDOUT_7_0_BYTE_VAL		REG8_VAL(GPIO_CTRL_GP4_VDOUT_7_0_BYTE_ADDR )
-#define GPIO_CTRL_GP5_VDOUT_15_8_BYTE_VAL		REG8_VAL(GPIO_CTRL_GP5_VDOUT_15_8_BYTE_ADDR )
-#define GPIO_CTRL_GP6_VDOUT_23_16_BYTE_VAL		REG8_VAL(GPIO_CTRL_GP6_VDOUT_23_16_BYTE_ADDR )
-#define GPIO_CTRL_GP7_VD_BYTE_VAL				REG8_VAL(GPIO_CTRL_GP7_VD_BYTE_ADDR )
-#define GPIO_CTRL_GP8_VDIN_BYTE_VAL				REG8_VAL(GPIO_CTRL_GP8_VDIN_BYTE_ADDR )
-#define GPIO_CTRL_GP9_VSYNC_BYTE_VAL 			REG8_VAL(GPIO_CTRL_GP9_VSYNC_BYTE_ADDR )
-#define GPIO_CTRL_GP10_I2S_BYTE_VAL				REG8_VAL(GPIO_CTRL_GP10_I2S_BYTE_ADDR )
-#define GPIO_CTRL_GP11_I2S_BYTE_VAL      		REG8_VAL(GPIO_CTRL_GP11_I2S_BYTE_ADDR )
-#define GPIO_CTRL_GP12_SPI_BYTE_VAL				REG8_VAL(GPIO_CTRL_GP12_SPI_BYTE_ADDR )
-#define GPIO_CTRL_GP13_SD0_BYTE_VAL       	REG8_VAL(GPIO_CTRL_GP13_SD0_BYTE_ADDR )
-#define GPIO_CTRL_GP14_NAND_SD1_BYTE_VAL		REG8_VAL(GPIO_CTRL_GP14_NAND_SD1_BYTE_ADDR )
-#define GPIO_CTRL_GP15_NAND_BYTE_VAL			REG8_VAL(GPIO_CTRL_GP15_NAND_BYTE_ADDR )
-#define GPIO_CTRL_GP16_NAND_SD1_BYTE_VAL		REG8_VAL(GPIO_CTRL_GP16_NAND_SD1_BYTE_ADDR )
-#define GPIO_CTRL_GP17_I2C_BYTE_VAL       		REG8_VAL(GPIO_CTRL_GP17_I2C_BYTE_ADDR )
-#define GPIO_CTRL_GP18_UART_BYTE_VAL			REG8_VAL(GPIO_CTRL_GP18_UART_BYTE_ADDR )
-#define GPIO_CTRL_GP19_SD2_BYTE_VAL   	    	REG8_VAL(GPIO_CTRL_GP19_SD2_BYTE_ADDR )
-#define GPIO_CTRL_GP20_PWM0_BYTE_VAL       		REG8_VAL(GPIO_CTRL_GP20_PWM0_BYTE_ADDR )
-#define GPIO_CTRL_GP21_HDMI_BYTE_VAL       		REG8_VAL(GPIO_CTRL_GP21_HDMI_BYTE_ADDR )
-#define GPIO_CTRL_GP23_I2C3_BYTE_VAL	    	REG8_VAL(GPIO_CTRL_GP23_I2C3_BYTE_ADDR )
-#define GPIO_CTRL_GP24_SF_BYTE_VAL				REG8_VAL(GPIO_CTRL_GP24_SF_BYTE_ADDR )
-#define GPIO_CTRL_GP26_PCM_BYTE_VAL       		REG8_VAL(GPIO_CTRL_GP26_PCM_BYTE_ADDR )
-#define GPIO_CTRL_GP60_USB_BYTE_VAL				REG8_VAL(GPIO_CTRL_GP60_USB_BYTE_ADDR )
-#define GPIO_CTRL_GP62_WAKEUP_SUS_BYTE_VAL		REG8_VAL(GPIO_CTRL_GP62_WAKEUP_SUS_BYTE_ADDR )
-#define GPIO_CTRL_GP63_SD02CD_BYTE_VAL			REG8_VAL(GPIO_CTRL_GP63_SD02CD_BYTE_ADDR )
-#define GPIO_OC_GP0_BYTE_VAL 					REG8_VAL(GPIO_OC_GP0_BYTE_ADDR )
-#define GPIO_OC_GP1_BYTE_VAL 					REG8_VAL(GPIO_OC_GP1_BYTE_ADDR )
-#define GPIO_OC_GP2_BYTE_VAL					REG8_VAL(GPIO_OC_GP2_BYTE_ADDR )
-#define GPIO_OC_GP4_VDOUT_7_0_BYTE_VAL			REG8_VAL(GPIO_OC_GP4_VDOUT_7_0_BYTE_ADDR )
-#define GPIO_OC_GP5_VDOUT_15_8_BYTE_VAL			REG8_VAL(GPIO_OC_GP5_VDOUT_15_8_BYTE_ADDR )
-#define GPIO_OC_GP6_VDOUT_23_16_BYTE_VAL		REG8_VAL(GPIO_OC_GP6_VDOUT_23_16_BYTE_ADDR )
-#define GPIO_OC_GP7_VD_BYTE_VAL					REG8_VAL(GPIO_OC_GP7_VD_BYTE_ADDR )
-#define GPIO_OC_GP8_VDIN_BYTE_VAL				REG8_VAL(GPIO_OC_GP8_VDIN_BYTE_ADDR )
-#define GPIO_OC_GP9_VSYNC_BYTE_VAL 				REG8_VAL(GPIO_OC_GP9_VSYNC_BYTE_ADDR )
-#define GPIO_OC_GP10_I2S_BYTE_VAL				REG8_VAL(GPIO_OC_GP10_I2S_BYTE_ADDR )
-#define GPIO_OC_GP11_I2S_BYTE_VAL      			REG8_VAL(GPIO_OC_GP11_I2S_BYTE_ADDR )
-#define GPIO_OC_GP12_SPI_BYTE_VAL				REG8_VAL(GPIO_OC_GP12_SPI_BYTE_ADDR )
-#define GPIO_OC_GP13_SD0_BYTE_VAL   		REG8_VAL(GPIO_OC_GP13_SD0_BYTE_ADDR )
-#define GPIO_OC_GP14_NAND_SD1_BYTE_VAL			REG8_VAL(GPIO_OC_GP14_NAND_SD1_BYTE_ADDR )
-#define GPIO_OC_GP15_NAND_BYTE_VAL				REG8_VAL(GPIO_OC_GP15_NAND_BYTE_ADDR )
-#define GPIO_OC_GP16_NAND_SD1_BYTE_VAL			REG8_VAL(GPIO_OC_GP16_NAND_SD1_BYTE_ADDR )
-#define GPIO_OC_GP17_I2C_BYTE_VAL       		REG8_VAL(GPIO_OC_GP17_I2C_BYTE_ADDR )
-#define GPIO_OC_GP18_UART_BYTE_VAL				REG8_VAL(GPIO_OC_GP18_UART_BYTE_ADDR )
-#define GPIO_OC_GP19_SD2_BYTE_VAL   	    	REG8_VAL(GPIO_OC_GP19_SD2_BYTE_ADDR )
-#define GPIO_OC_GP20_PWM0_BYTE_VAL       		REG8_VAL(GPIO_OC_GP20_PWM0_BYTE_ADDR )
-#define GPIO_OC_GP21_HDMI_BYTE_VAL       		REG8_VAL(GPIO_OC_GP21_HDMI_BYTE_ADDR )
-#define GPIO_OC_GP22_I2C3_BYTE_VAL	     	  	REG8_VAL(GPIO_OC_GP22_I2C3_BYTE_ADDR )
-#define GPIO_OC_GP24_SF_BYTE_VAL				REG8_VAL(GPIO_OC_GP24_SF_BYTE_ADDR )
-#define GPIO_OC_GP26_PCM_BYTE_VAL       		REG8_VAL(GPIO_OC_GP26_PCM_BYTE_ADDR )
-#define GPIO_OC_GP60_USB_BYTE_VAL				REG8_VAL(GPIO_OC_GP60_USB_BYTE_ADDR )
-#define GPIO_OC_GP62_WAKEUP_SUS_BYTE_VAL		REG8_VAL(GPIO_OC_GP62_WAKEUP_SUS_BYTE_ADDR )
-#define GPIO_OC_GP63_SD02CD_BYTE_VAL			REG8_VAL(GPIO_OC_GP63_SD02CD_BYTE_ADDR )
-#define GPIO_OD_GP0_BYTE_VAL 					REG8_VAL(GPIO_OD_GP0_BYTE_ADDR )
-#define GPIO_OD_GP1_BYTE_VAL 					REG8_VAL(GPIO_OD_GP1_BYTE_ADDR )
-#define GPIO_OD_GP2_BYTE_VAL					REG8_VAL(GPIO_OD_GP2_BYTE_ADDR )
-#define GPIO_OD_GP4_VDOUT_7_0_BYTE_VAL			REG8_VAL(GPIO_OD_GP4_VDOUT_7_0_BYTE_ADDR )
-#define GPIO_OD_GP5_VDOUT_15_8_BYTE_VAL			REG8_VAL(GPIO_OD_GP5_VDOUT_15_8_BYTE_ADDR )
-#define GPIO_OD_GP6_VDOUT_23_16_BYTE_VAL		REG8_VAL(GPIO_OD_GP6_VDOUT_23_16_BYTE_ADDR )
-#define GPIO_OD_GP7_VD_BYTE_VAL					REG8_VAL(GPIO_OD_GP7_VD_BYTE_ADDR )
-#define GPIO_OD_GP8_VDIN_BYTE_VAL				REG8_VAL(GPIO_OD_GP8_VDIN_BYTE_ADDR )
-#define GPIO_OD_GP9_VSYNC_BYTE_VAL 				REG8_VAL(GPIO_OD_GP9_VSYNC_BYTE_ADDR )
-#define GPIO_OD_GP10_I2S_BYTE_VAL				REG8_VAL(GPIO_OD_GP10_I2S_BYTE_ADDR )
-#define GPIO_OD_GP11_I2S_BYTE_VAL      			REG8_VAL(GPIO_OD_GP11_I2S_BYTE_ADDR )
-#define GPIO_OD_GP12_SPI_BYTE_VAL				REG8_VAL(GPIO_OD_GP12_SPI_BYTE_ADDR )
-#define GPIO_OD_GP13_SD0_BYTE_VAL   		REG8_VAL(GPIO_OD_GP13_SD0_BYTE_ADDR )
-#define GPIO_OD_GP14_NAND_SD1_BYTE_VAL			REG8_VAL(GPIO_OD_GP14_NAND_SD1_BYTE_ADDR )
-#define GPIO_OD_GP15_NAND_BYTE_VAL				REG8_VAL(GPIO_OD_GP15_NAND_BYTE_ADDR )
-#define GPIO_OD_GP16_NAND_SD1_BYTE_VAL			REG8_VAL(GPIO_OD_GP16_NAND_SD1_BYTE_ADDR )
-#define GPIO_OD_GP17_I2C_BYTE_VAL       		REG8_VAL(GPIO_OD_GP17_I2C_BYTE_ADDR )
-#define GPIO_OD_GP18_UART_BYTE_VAL				REG8_VAL(GPIO_OD_GP18_UART_BYTE_ADDR )
-#define GPIO_OD_GP19_SD2_BYTE_VAL   	    	REG8_VAL(GPIO_OD_GP19_SD2_BYTE_ADDR )
-#define GPIO_OD_GP20_PWM0_BYTE_VAL       		REG8_VAL(GPIO_OD_GP20_PWM0_BYTE_ADDR )
-#define GPIO_OD_GP21_HDMI_BYTE_VAL       		REG8_VAL(GPIO_OD_GP21_HDMI_BYTE_ADDR )
-#define GPIO_OD_GP23_I2C3_BYTE_VAL	       		REG8_VAL(GPIO_OD_GP23_I2C3_BYTE_ADDR )
-#define GPIO_OD_GP24_SF_BYTE_VAL				REG8_VAL(GPIO_OD_GP24_SF_BYTE_ADDR )
-#define GPIO_OD_GP26_PCM_BYTE_VAL       		REG8_VAL(GPIO_OD_GP26_PCM_BYTE_ADDR )
-#define GPIO_OD_GP60_USB_BYTE_VAL				REG8_VAL(GPIO_OD_GP60_USB_BYTE_ADDR )
-#define GPIO_OD_GP62_WAKEUP_SUS_BYTE_VAL		REG8_VAL(GPIO_OD_GP62_WAKEUP_SUS_BYTE_ADDR )
-#define GPIO_OD_GP63_SD02CD_BYTE_VAL			REG8_VAL(GPIO_OD_GP63_SD02CD_BYTE_ADDR )
-#define STRAP_STATUS_VAL					REG32_VAL(STRAP_STATUS_ADDR )
-#define AHB_CTRL_4BYTE_VAL 					REG32_VAL(AHB_CTRL_4BYTE_ADDR )
-#define USB_OP_CTRL_4BYTE_VAL				REG32_VAL(USB_OP_CTRL_4BYTE_ADDR )
-#define BONDING_OPTION_4BYTE_VAL			REG32_VAL(BONDING_OPTION_4BYTE_ADDR )
-#define PIN_SHARING_SEL_4BYTE_VAL 			REG32_VAL(PIN_SHARING_SEL_4BYTE_ADDR )
-#define TPIU_CLK_DATA_4BYTE_VAL 			REG32_VAL(TPIU_CLK_DATA_4BYTE_ADDR )
-#define GPIO0_INT_REQ_TYPE_VAL				REG8_VAL(GPIO0_INT_REQ_TYPE_ADDR )
-#define GPIO1_INT_REQ_TYPE_VAL				REG8_VAL(GPIO1_INT_REQ_TYPE_ADDR )
-#define GPIO2_INT_REQ_TYPE_VAL				REG8_VAL(GPIO2_INT_REQ_TYPE_ADDR )
-#define GPIO3_INT_REQ_TYPE_VAL				REG8_VAL(GPIO3_INT_REQ_TYPE_ADDR )
-#define GPIO4_INT_REQ_TYPE_VAL				REG8_VAL(GPIO4_INT_REQ_TYPE_ADDR )
-#define GPIO5_INT_REQ_TYPE_VAL				REG8_VAL(GPIO5_INT_REQ_TYPE_ADDR )
-#define GPIO6_INT_REQ_TYPE_VAL				REG8_VAL(GPIO6_INT_REQ_TYPE_ADDR )
-#define GPIO7_INT_REQ_TYPE_VAL				REG8_VAL(GPIO7_INT_REQ_TYPE_ADDR )
-#define GPIO8_INT_REQ_TYPE_VAL				REG8_VAL(GPIO8_INT_REQ_TYPE_ADDR )
-#define GPIO9_INT_REQ_TYPE_VAL				REG8_VAL(GPIO9_INT_REQ_TYPE_ADDR )
-#define GPIO10_INT_REQ_TYPE_VAL				REG8_VAL(GPIO10_INT_REQ_TYPE_ADDR )
-#define GPIO11_INT_REQ_TYPE_VAL				REG8_VAL(GPIO11_INT_REQ_TYPE_ADDR )
-#define GPIO12_INT_REQ_TYPE_VAL				REG8_VAL(GPIO12_INT_REQ_TYPE_ADDR )
-#define GPIO13_INT_REQ_TYPE_VAL				REG8_VAL(GPIO13_INT_REQ_TYPE_ADDR )
-#define GPIO18_INT_REQ_TYPE_VAL				REG8_VAL(GPIO18_INT_REQ_TYPE_ADDR )
-#define GPIO19_INT_REQ_TYPE_VAL				REG8_VAL(GPIO19_INT_REQ_TYPE_ADDR )
-#define VOUT20_INT_REQ_TYPE_VAL				REG8_VAL(VOUT20_INT_REQ_TYPE_ADDR )
-#define VOUT21_INT_REQ_TYPE_VAL				REG8_VAL(VOUT21_INT_REQ_TYPE_ADDR )
-#define VOUT22_INT_REQ_TYPE_VAL				REG8_VAL(VOUT22_INT_REQ_TYPE_ADDR )
-#define VOUT23_INT_REQ_TYPE_VAL				REG8_VAL(VOUT23_INT_REQ_TYPE_ADDR )
-#define GPIO20_INT_REQ_TYPE_VAL				REG8_VAL(GPIO20_INT_REQ_TYPE_ADDR )
-#define GPIO21_INT_REQ_TYPE_VAL				REG8_VAL(GPIO21_INT_REQ_TYPE_ADDR )
-#define GPIO22_INT_REQ_TYPE_VAL				REG8_VAL(GPIO22_INT_REQ_TYPE_ADDR )
-#define GPIO23_INT_REQ_TYPE_VAL				REG8_VAL(GPIO23_INT_REQ_TYPE_ADDR )
-#define GPIO24_INT_REQ_TYPE_VAL				REG8_VAL(GPIO24_INT_REQ_TYPE_ADDR )
-#define GPIO25_INT_REQ_TYPE_VAL				REG8_VAL(GPIO25_INT_REQ_TYPE_ADDR )
-#define GPIO0_INT_REQ_STS_VAL				REG8_VAL(GPIO0_INT_REQ_STS_ADDR )
-#define GPIO1_INT_REQ_STS_VAL				REG8_VAL(GPIO1_INT_REQ_STS_ADDR )
-#define GPIO2_INT_REQ_STS_VAL				REG8_VAL(GPIO2_INT_REQ_STS_ADDR )
-#define GPIO3_INT_REQ_STS_VAL				REG8_VAL(GPIO3_INT_REQ_STS_ADDR )
-#define DRV_DVO_CLK_BYTE_VAL				REG8_VAL(DRV_DVO_CLK_BYTE_ADDR )
-#define DRV_DVO_VDEN_BYTE_VAL				REG8_VAL(DRV_DVO_VDEN_BYTE_ADDR )
-#define SD0_DPCTL_4BYTE_VAL					REG32_VAL(SD0_DPCTL_4BYTE_ADDR )
-#define SD0_DNCTL_4BYTE_VAL					REG32_VAL(SD0_DNCTL_4BYTE_ADDR )
-#define DRV_SD0_USB_BYTE_VAL				REG8_VAL(DRV_SD0_USB_BYTE_ADDR )	
-#define DRV_USB_SWOC0_BYTE_VAL				REG8_VAL(DRV_USB_SWOC0_BYTE_ADDR )
-#define DRV_USB_OC12_BYTE_VAL				REG8_VAL(DRV_USB_OC12_BYTE_ADDR )
-#define DRV_USBOC3_CIR_BYTE_VAL				REG8_VAL(DRV_USBOC3_CIR_BYTE_ADDR )
-#define DRV_PWREN_BYTE_VAL					REG8_VAL(DRV_PWREN_BYTE_ADDR )
-#define DRV_PWREN_WAKEUP0_BYTE_VAL			REG8_VAL(DRV_PWREN_WAKEUP0_BYTE_ADDR )
-#define DRV_SUSGP01_BYTE_VAL				REG8_VAL(DRV_SUSGP01_BYTE_ADDR )
-#define DRV_WAKEUP23_BYTE_VAL				REG8_VAL(DRV_WAKEUP23_BYTE_ADDR )
-#define DRV_WAKEUP45_BYTE_VAL				REG8_VAL(DRV_WAKEUP45_BYTE_ADDR )
-#define DRV_I2C_BYTE_VAL					REG8_VAL(DRV_I2C_BYTE_ADDR )
-#define DRV_HDMI_BYTE_VAL					REG8_VAL(DRV_HDMI_BYTE_ADDR )	
-#define PULL_EN_GP0_BYTE_VAL				REG8_VAL(PULL_EN_GP0_BYTE_ADDR )
-#define PULL_EN_GP1_BYTE_VAL				REG8_VAL(PULL_EN_GP1_BYTE_ADDR )
-#define PULL_EN_GP2_BYTE_VAL				REG8_VAL(PULL_EN_GP2_BYTE_ADDR )
-#define PULL_EN_GP4_VDOUT_7_0_BYTE_VAL		REG8_VAL(PULL_EN_GP4_VDOUT_7_0_BYTE_ADDR )
-#define PULL_EN_GP5_VDOUT_15_8_BYTE_VAL		REG8_VAL(PULL_EN_GP5_VDOUT_15_8_BYTE_ADDR )
-#define PULL_EN_GP6_VDOUT_23_16_BYTE_VAL	REG8_VAL(PULL_EN_GP6_VDOUT_23_16_BYTE_ADDR )
-#define PULL_EN_GP7_VD_BYTE_VAL     		REG8_VAL(PULL_EN_GP7_VD_BYTE_ADDR )
-#define PULL_EN_GP8_VDIN_BYTE_VAL   		REG8_VAL(PULL_EN_GP8_VDIN_BYTE_ADDR )
-#define PULL_EN_GP9_VSYNC_BYTE_VAL 			REG8_VAL(PULL_EN_GP9_VSYNC_BYTE_ADDR )
-#define PULL_EN_GP10_I2S_BYTE_VAL 			REG8_VAL(PULL_EN_GP10_I2S_BYTE_ADDR )
-#define PULL_EN_GP11_I2S_BYTE_VAL     		REG8_VAL(PULL_EN_GP11_I2S_BYTE_ADDR )
-#define PULL_EN_GP12_SPI_BYTE_VAL			REG8_VAL(PULL_EN_GP12_SPI_BYTE_ADDR )
-#define PULL_EN_GP13_SD0_BYTE_VAL       	REG8_VAL(PULL_EN_GP13_SD0_BYTE_ADDR )
-#define PULL_EN_GP14_NAND_BYTE_VAL      	REG8_VAL(PULL_EN_GP14_NAND_BYTE_ADDR )
-#define PULL_EN_GP15_NAND_BYTE_VAL			REG8_VAL(PULL_EN_GP15_NAND_BYTE_ADDR )
-#define PULL_EN_GP16_NANDIO_BYTE_VAL		REG8_VAL(PULL_EN_GP16_NANDIO_BYTE_ADDR )
-#define PULL_EN_GP17_I2C_BYTE_VAL			REG8_VAL(PULL_EN_GP17_I2C_BYTE_ADDR )
-#define PULL_EN_GP18_UART_BYTE_VAL			REG8_VAL(PULL_EN_GP18_UART_BYTE_ADDR )
-#define PULL_EN_GP19_SD2_BYTE_VAL			REG8_VAL(PULL_EN_GP19_SD2_BYTE_ADDR )
-#define PULL_EN_GP20_PWM0_BYTE_VAL			REG8_VAL(PULL_EN_GP20_PWM0_BYTE_ADDR )
-#define PULL_EN_GP21_HDMI_BYTE_VAL      	REG8_VAL(PULL_EN_GP21_HDMI_BYTE_ADDR )
-#define PULL_EN_GP23_I2C3_BYTE_VAL			REG8_VAL(PULL_EN_GP23_I2C3_BYTE_ADDR )
-#define PULL_EN_GP24_SF_BYTE_VAL			REG8_VAL(PULL_EN_GP24_SF_BYTE_ADDR )
-#define PULL_EN_GP26_PCM_BYTE_VAL			REG8_VAL(PULL_EN_GP26_PCM_BYTE_ADDR )
-#define PULL_EN_GP60_USB_BYTE_VAL			REG8_VAL(PULL_EN_GP60_USB_BYTE_ADDR )
-#define PULL_EN_GP62_WAKEUP_SUS_BYTE_VAL	REG8_VAL(PULL_EN_GP62_WAKEUP_SUS_BYTE_ADDR )
-#define PULL_EN_GP63_SD02_BYTE_VAL			REG8_VAL(PULL_EN_GP63_SD02_BYTE_ADDR )
-#define PULL_CTRL_GP0_BYTE_VAL				REG8_VAL(PULL_CTRL_GP0_BYTE_ADDR )
-#define PULL_CTRL_GP1_BYTE_VAL				REG8_VAL(PULL_CTRL_GP1_BYTE_ADDR )
-#define PULL_CTRL_GP2_BYTE_VAL				REG8_VAL(PULL_CTRL_GP2_BYTE_ADDR )
-#define PULL_CTRL_GP4_VDOUT_7_0_BYTE_VAL	REG8_VAL(PULL_CTRL_GP4_VDOUT_7_0_BYTE_ADDR )
-#define PULL_CTRL_GP5_VDOUT_15_8_BYTE_VAL	REG8_VAL(PULL_CTRL_GP5_VDOUT_15_8_BYTE_ADDR )
-#define PULL_CTRL_GP6_VDOUT_23_16_BYTE_VAL	REG8_VAL(PULL_CTRL_GP6_VDOUT_23_16_BYTE_ADDR )
-#define PULL_CTRL_GP7_VD_BYTE_VAL			REG8_VAL(PULL_CTRL_GP7_VD_BYTE_ADDR )
-#define PULL_CTRL_GP8_VDIN_BYTE_VAL			REG8_VAL(PULL_CTRL_GP8_VDIN_BYTE_ADDR )
-#define PULL_CTRL_GP9_VSYNC_BYTE_VAL		REG8_VAL(PULL_CTRL_GP9_VSYNC_BYTE_ADDR )
-#define PULL_CTRL_GP10_I2S_BYTE_VAL			REG8_VAL(PULL_CTRL_GP10_I2S_BYTE_ADDR )
-#define PULL_CTRL_GP11_I2S_BYTE_VAL			REG8_VAL(PULL_CTRL_GP11_I2S_BYTE_ADDR )
-#define PULL_CTRL_GP12_SPI_BYTE_VAL			REG8_VAL(PULL_CTRL_GP12_SPI_BYTE_ADDR )
-#define PULL_CTRL_GP13_SD0_BYTE_VAL			REG8_VAL(PULL_CTRL_GP13_SD0_BYTE_ADDR )
-#define PULL_CTRL_GP14_NAND_BYTE_VAL       	REG8_VAL(PULL_CTRL_GP14_NAND_BYTE_ADDR )
-#define PULL_CTRL_GP15_NAND_BYTE_VAL		REG8_VAL(PULL_CTRL_GP15_NAND_BYTE_ADDR )
-#define PULL_CTRL_GP16_NANDIO_BYTE_VAL		REG8_VAL(PULL_CTRL_GP16_NANDIO_BYTE_ADDR )
-#define PULL_CTRL_GP17_I2C_BYTE_VAL     	REG8_VAL(PULL_CTRL_GP17_I2C_BYTE_ADDR )
-#define PULL_CTRL_GP18_UART_BYTE_VAL     	REG8_VAL(PULL_CTRL_GP18_UART_BYTE_ADDR )
-#define PULL_CTRL_GP19_SD2_BYTE_VAL     	REG8_VAL(PULL_CTRL_GP19_SD2_BYTE_ADDR )
-#define PULL_CTRL_GP20_PWM0_BYTE_VAL      	REG8_VAL(PULL_CTRL_GP20_PWM0_BYTE_ADDR )
-#define PULL_CTRL_GP21_HDMI_BYTE_VAL		REG8_VAL(PULL_CTRL_GP21_HDMI_BYTE_ADDR )
-#define PULL_CTRL_GP23_I2C3_BYTE_VAL		REG8_VAL(PULL_CTRL_GP23_I2C3_BYTE_ADDR )
-#define PULL_CTRL_GP24_SF_BYTE_VAL     		REG8_VAL(PULL_CTRL_GP24_SF_BYTE_ADDR )
-#define PULL_CTRL_GP26_PCM_BYTE_VAL			REG8_VAL(PULL_CTRL_GP26_PCM_BYTE_ADDR )
-#define PULL_CTRL_GP27_SD0_BYTE_VAL			REG8_VAL(PULL_CTRL_GP27_SD0_BYTE_ADDR )
-#define PULL_CTRL_GP60_USB_BYTE_VAL			REG8_VAL(PULL_CTRL_GP60_USB_BYTE_ADDR )
-#define PULL_CTRL_GP62_WAKEUP_SUS_BYTE_VAL	REG8_VAL(PULL_CTRL_GP62_WAKEUP_SUS_BYTE_ADDR )
-#define PULL_CTRL_GP63_SD02_BYTE_VAL		REG8_VAL(PULL_CTRL_GP63_SD02_BYTE_ADDR )
-#define DRV_GPIO_7_0_4BYTE_VAL				REG32_VAL(DRV_GPIO_7_0_4BYTE_ADDR )
-#define DRV_GPIO_13_8_4BYTE_VAL				REG32_VAL(DRV_GPIO_13_8_4BYTE_ADDR )
-#define DRV_GPIO_19_14_4BYTE_VAL			REG32_VAL(DRV_GPIO_19_14_4BYTE_ADDR )
-#define DRV_VDIN_3_0_4BYTE_VAL				REG32_VAL(DRV_VDIN_3_0_4BYTE_ADDR )
-#define DRV_VDIN_4_6_4BYTE_VAL				REG32_VAL(DRV_VDIN_3_0_4BYTE_ADDR )
-#define DRV_VDIN_SPI_4BYTE_VAL				REG32_VAL(DRV_VDIN_SPI_4BYTE_ADDR )
-#define DRV_SPI_NAND_4BYTE_VAL				REG32_VAL(DRV_SPI_NAND_4BYTE_ADDR )
-#define DRV_NAND_4BYTE_VAL					REG32_VAL(DRV_NAND_4BYTE_ADDR )
-#define DRV_NANDIO_4BYTE_VAL				REG32_VAL(DRV_NANDIO_4BYTE_ADDR )
-#define DRV_HDMI_I2C_4BYTE_VAL				REG32_VAL(DRV_HDMI_I2C_4BYTE_ADDR )
-#define DRV_I2C_SD0_4BYTE_VAL				REG32_VAL(DRV_I2C_SD0_4BYTE_ADDR )
-#define DRV_SD0_SD2_4BYTE_VAL				REG32_VAL(DRV_SD0_SD2_4BYTE_ADDR )
-#define DRV_SD2_I2S_4BYTE_VAL				REG32_VAL(DRV_SD2_I2S_4BYTE_ADDR )
-#define DRV_I2S_UART_4BYTE_VAL				REG32_VAL(DRV_I2S_UART_4BYTE_ADDR )
-#define DRV_UART_4BYTE_VAL					REG32_VAL(DRV_UART_4BYTE_ADDR )
-#define DRV_SF_JTAGT_4BYTE_VAL				REG32_VAL(DRV_SF_JTAGT_4BYTE_ADDR )
-#define DRV_JTAGT_PWM_4BYTE_VAL				REG32_VAL(DRV_JTAGT_PWM_4BYTE_ADDR )
-#define DRV_PCM_BYTE_VAL					REG8_VAL(DRV_PCM_BYTE_ADDR )
-#define DRV_SPI_BYTE_VAL					REG8_VAL(DRV_SPI_BYTE_ADDR )
-
-#define GPIO_STRAP_STS_VAL  		REG32_VAL(0x0100+BA_GPIO)
-
-/* [Rx300] GPIO Interrupt Request Type Register */
-#define GPIO_IRQT_LOW	  	0
-#define GPIO_IRQT_HIGH		BIT0
-#define GPIO_IRQT_FALLING	BIT1
-#define GPIO_IRQT_RISING	(BIT1 | BIT0)
-#define GPIO_IRQT_DOUBLE	BIT2
-
-/* GPIO Control Register for I2C */
-#define GPIO_I2C0_SCL	BIT0
-#define GPIO_I2C0_SDA	BIT1
-#define GPIO_I2C1_SCL	BIT2
-#define GPIO_I2C1_SDA	BIT3
-#define GPIO_I2C2_SCL	BIT4
-#define GPIO_I2C2_SDA	BIT5
-#define GPIO_I2C3_SCL	BIT0
-#define GPIO_I2C3_SDA	BIT1
-#define GPIO_I2C0_SCL_PULL_EN BIT0
-#define GPIO_I2C0_SDA_PULL_EN BIT1
-#define GPIO_I2C1_SCL_PULL_EN BIT2
-#define GPIO_I2C1_SDA_PULL_EN BIT3
-#define GPIO_I2C2_SCL_PULL_EN BIT4
-#define GPIO_I2C2_SDA_PULL_EN BIT5
-#define GPIO_I2C3_SCL_PULL_EN BIT0
-#define GPIO_I2C3_SDA_PULL_EN BIT1
-
-#endif
-/*=== END wmt_gpio.h ==========================================================*/
-
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_i2c.h b/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_i2c.h
deleted file mode 100755
index 73f9c3e6..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_i2c.h
+++ /dev/null
@@ -1,403 +0,0 @@
-/*++
-	linux/include/asm-arm/arch-wmt/wmt_i2c.h
-
-	Copyright (c) 2008  WonderMedia Technologies, Inc.
-
-	This program is free software: you can redistribute it and/or modify it under the
-	terms of the GNU General Public License as published by the Free Software Foundation,
-	either version 2 of the License, or (at your option) any later version.
-
-	This program is distributed in the hope that it will be useful, but WITHOUT
-	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-	PARTICULAR PURPOSE.  See the GNU General Public License for more details.
-	You should have received a copy of the GNU General Public License along with
-	this program.  If not, see <http://www.gnu.org/licenses/>.
-
-	WonderMedia Technologies, Inc.
-	10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
-
---*/
-/* Be sure that virtual mapping is defined right */
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#error "You must include hardware.h, not wmt_i2c.h"
-#endif
-
-#ifndef _WMT_I2C_H_
-#define _WMT_I2C_H_
-/*-------------------- MODULE DEPENDENCY -------------------------------------*/
-
-#include "wmt_mmap.h"
-/*
- *   Refer I2C 0.1 Module
- *
- */
-/*
-    i2c api address
-
-      Since i2c bus would probe all device which connect with it to add i2c adapter
-   ,but we dont make sure which would connect with it. In order to reduce probe time
-   ,we give a fake slave address for probing only.
-   Be carefully, the i2c api address must be different from real device address 
-*/
-
-#define         WMT_I2C_API_I2C_ADDR            0x59           /*API address*/
-
-/*
- * Address
- */
-#define I2C_CR_ADDR                     (0x0000+I2C_BASE_ADDR)
-#define I2C_TCR_ADDR                    (0x0002+I2C_BASE_ADDR)
-#define I2C_CSR_ADDR                    (0x0004+I2C_BASE_ADDR)
-#define I2C_ISR_ADDR                    (0x0006+I2C_BASE_ADDR)
-#define I2C_IMR_ADDR                    (0x0008+I2C_BASE_ADDR)
-#define I2C_CDR_ADDR                    (0x000A+I2C_BASE_ADDR)
-#define I2C_TR_ADDR                     (0x000C+I2C_BASE_ADDR)
-#define I2C_DIV_ADDR                    (0x000E+I2C_BASE_ADDR)
-
-#define I2C1_CR_ADDR                     (0x0000+I2C1_BASE_ADDR)
-#define I2C1_TCR_ADDR                    (0x0002+I2C1_BASE_ADDR)
-#define I2C1_CSR_ADDR                    (0x0004+I2C1_BASE_ADDR)
-#define I2C1_ISR_ADDR                    (0x0006+I2C1_BASE_ADDR)
-#define I2C1_IMR_ADDR                    (0x0008+I2C1_BASE_ADDR)
-#define I2C1_CDR_ADDR                    (0x000A+I2C1_BASE_ADDR)
-#define I2C1_TR_ADDR                     (0x000C+I2C1_BASE_ADDR)
-#define I2C1_DIV_ADDR                    (0x000E+I2C1_BASE_ADDR)
-
-#define I2C2_CR_ADDR                     (0x0000+I2C2_BASE_ADDR)
-#define I2C2_TCR_ADDR                    (0x0002+I2C2_BASE_ADDR)
-#define I2C2_CSR_ADDR                    (0x0004+I2C2_BASE_ADDR)
-#define I2C2_ISR_ADDR                    (0x0006+I2C2_BASE_ADDR)
-#define I2C2_IMR_ADDR                    (0x0008+I2C2_BASE_ADDR)
-#define I2C2_CDR_ADDR                    (0x000A+I2C2_BASE_ADDR)
-#define I2C2_TR_ADDR                     (0x000C+I2C2_BASE_ADDR)
-#define I2C2_DIV_ADDR                    (0x000E+I2C2_BASE_ADDR)
-
-#define I2C3_CR_ADDR                     (0x0000+I2C3_BASE_ADDR)
-#define I2C3_TCR_ADDR                    (0x0002+I2C3_BASE_ADDR)
-#define I2C3_CSR_ADDR                    (0x0004+I2C3_BASE_ADDR)
-#define I2C3_ISR_ADDR                    (0x0006+I2C3_BASE_ADDR)
-#define I2C3_IMR_ADDR                    (0x0008+I2C3_BASE_ADDR)
-#define I2C3_CDR_ADDR                    (0x000A+I2C3_BASE_ADDR)
-#define I2C3_TR_ADDR                     (0x000C+I2C3_BASE_ADDR)
-#define I2C3_DIV_ADDR                    (0x000E+I2C3_BASE_ADDR)
-
-#define I2C4_CR_ADDR                     (0x0000+I2C4_BASE_ADDR)
-#define I2C4_TCR_ADDR                    (0x0002+I2C4_BASE_ADDR)
-#define I2C4_CSR_ADDR                    (0x0004+I2C4_BASE_ADDR)
-#define I2C4_ISR_ADDR                    (0x0006+I2C4_BASE_ADDR)
-#define I2C4_IMR_ADDR                    (0x0008+I2C4_BASE_ADDR)
-#define I2C4_CDR_ADDR                    (0x000A+I2C4_BASE_ADDR)
-#define I2C4_TR_ADDR                     (0x000C+I2C4_BASE_ADDR)
-#define I2C4_DIV_ADDR                    (0x000E+I2C4_BASE_ADDR)
-
-/* Slave Address*/
-#define I2C_SCR_ADDR                    (0x0010+I2C_BASE_ADDR)
-#define I2C_SSR_ADDR                    (0x0012+I2C_BASE_ADDR)
-#define I2C_SISR_ADDR                   (0x0014+I2C_BASE_ADDR)
-#define I2C_SIMR_ADDR                   (0x0016+I2C_BASE_ADDR)
-#define I2C_SDR_ADDR                    (0x0018+I2C_BASE_ADDR)
-#define I2C_STR_ADDR                    (0x001A+I2C_BASE_ADDR)
-
-/*
- * Registers
- */
-#define I2C_CR_REG                      REG16_PTR(0x0000+I2C_BASE_ADDR)
-#define I2C_TCR_REG                     REG16_PTR(0x0002+I2C_BASE_ADDR)
-#define I2C_CSR_REG                     REG16_PTR(0x0004+I2C_BASE_ADDR)
-#define I2C_ISR_REG                     REG16_PTR(0x0006+I2C_BASE_ADDR)
-#define I2C_IMR_REG                     REG16_PTR(0x0008+I2C_BASE_ADDR)
-#define I2C_CDR_REG                     REG16_PTR(0x000A+I2C_BASE_ADDR)
-#define I2C_TR_REG                      REG16_PTR(0x000C+I2C_BASE_ADDR)
-#define I2C_DIV_REG                     REG16_PTR(0x000E+I2C_BASE_ADDR)
-
-#define I2C1_CR_REG                      REG16_PTR(0x0000+I2C1_BASE_ADDR)
-#define I2C1_TCR_REG                     REG16_PTR(0x0002+I2C1_BASE_ADDR)
-#define I2C1_CSR_REG                     REG16_PTR(0x0004+I2C1_BASE_ADDR)
-#define I2C1_ISR_REG                     REG16_PTR(0x0006+I2C1_BASE_ADDR)
-#define I2C1_IMR_REG                     REG16_PTR(0x0008+I2C1_BASE_ADDR)
-#define I2C1_CDR_REG                     REG16_PTR(0x000A+I2C1_BASE_ADDR)
-#define I2C1_TR_REG                      REG16_PTR(0x000C+I2C1_BASE_ADDR)
-#define I2C1_DIV_REG                     REG16_PTR(0x000E+I2C1_BASE_ADDR)
-
-#define I2C2_CR_REG                      REG16_PTR(0x0000+I2C2_BASE_ADDR)
-#define I2C2_TCR_REG                     REG16_PTR(0x0002+I2C2_BASE_ADDR)
-#define I2C2_CSR_REG                     REG16_PTR(0x0004+I2C2_BASE_ADDR)
-#define I2C2_ISR_REG                     REG16_PTR(0x0006+I2C2_BASE_ADDR)
-#define I2C2_IMR_REG                     REG16_PTR(0x0008+I2C2_BASE_ADDR)
-#define I2C2_CDR_REG                     REG16_PTR(0x000A+I2C2_BASE_ADDR)
-#define I2C2_TR_REG                      REG16_PTR(0x000C+I2C2_BASE_ADDR)
-#define I2C2_DIV_REG                     REG16_PTR(0x000E+I2C2_BASE_ADDR)
-
-#define I2C3_CR_REG                      REG16_PTR(0x0000+I2C3_BASE_ADDR)
-#define I2C3_TCR_REG                     REG16_PTR(0x0002+I2C3_BASE_ADDR)
-#define I2C3_CSR_REG                     REG16_PTR(0x0004+I2C3_BASE_ADDR)
-#define I2C3_ISR_REG                     REG16_PTR(0x0006+I2C3_BASE_ADDR)
-#define I2C3_IMR_REG                     REG16_PTR(0x0008+I2C3_BASE_ADDR)
-#define I2C3_CDR_REG                     REG16_PTR(0x000A+I2C3_BASE_ADDR)
-#define I2C3_TR_REG                      REG16_PTR(0x000C+I2C3_BASE_ADDR)
-#define I2C3_DIV_REG                     REG16_PTR(0x000E+I2C3_BASE_ADDR)
-
-#define I2C4_CR_REG                      REG16_PTR(0x0000+I2C4_BASE_ADDR)
-#define I2C4_TCR_REG                     REG16_PTR(0x0002+I2C4_BASE_ADDR)
-#define I2C4_CSR_REG                     REG16_PTR(0x0004+I2C4_BASE_ADDR)
-#define I2C4_ISR_REG                     REG16_PTR(0x0006+I2C4_BASE_ADDR)
-#define I2C4_IMR_REG                     REG16_PTR(0x0008+I2C4_BASE_ADDR)
-#define I2C4_CDR_REG                     REG16_PTR(0x000A+I2C4_BASE_ADDR)
-#define I2C4_TR_REG                      REG16_PTR(0x000C+I2C4_BASE_ADDR)
-#define I2C4_DIV_REG                     REG16_PTR(0x000E+I2C4_BASE_ADDR)
-
-/* Slave Registers*/
-#define I2C_SCR_REG                     REG16_PTR(0x0010+I2C_BASE_ADDR)
-#define I2C_SSR_REG                     REG16_PTR(0x0012+I2C_BASE_ADDR)
-#define I2C_SISR_REG                    REG16_PTR(0x0014+I2C_BASE_ADDR)
-#define I2C_SIMR_REG                    REG16_PTR(0x0016+I2C_BASE_ADDR)
-#define I2C_SDR_REG                     REG16_PTR(0x0018+I2C_BASE_ADDR)
-#define I2C_STR_REG                     REG16_PTR(0x001A+I2C_BASE_ADDR)
-
-/*
- * Val Registers
- */
-#define I2C_CR_VAL                      REG16_VAL(0x0000+I2C_BASE_ADDR)
-#define I2C_TCR_VAL                     REG16_VAL(0x0002+I2C_BASE_ADDR)
-#define I2C_CSR_VAL                     REG16_VAL(0x0004+I2C_BASE_ADDR)
-#define I2C_ISR_VAL                     REG16_VAL(0x0006+I2C_BASE_ADDR)
-#define I2C_IMR_VAL                     REG16_VAL(0x0008+I2C_BASE_ADDR)
-#define I2C_CDR_VAL                     REG16_VAL(0x000A+I2C_BASE_ADDR)
-#define I2C_TR_VAL                      REG16_VAL(0x000C+I2C_BASE_ADDR)
-#define I2C_DIV_VAL                     REG16_VAL(0x000E+I2C_BASE_ADDR)
-
-#define I2C1_CR_VAL                      REG16_VAL(0x0000+I2C1_BASE_ADDR)
-#define I2C1_TCR_VAL                     REG16_VAL(0x0002+I2C1_BASE_ADDR)
-#define I2C1_CSR_VAL                     REG16_VAL(0x0004+I2C1_BASE_ADDR)
-#define I2C1_ISR_VAL                     REG16_VAL(0x0006+I2C1_BASE_ADDR)
-#define I2C1_IMR_VAL                     REG16_VAL(0x0008+I2C1_BASE_ADDR)
-#define I2C1_CDR_VAL                     REG16_VAL(0x000A+I2C1_BASE_ADDR)
-#define I2C1_TR_VAL                      REG16_VAL(0x000C+I2C1_BASE_ADDR)
-#define I2C1_DIV_VAL                     REG16_VAL(0x000E+I2C1_BASE_ADDR)
-
-#define I2C2_CR_VAL                      REG16_VAL(0x0000+I2C2_BASE_ADDR)
-#define I2C2_TCR_VAL                     REG16_VAL(0x0002+I2C2_BASE_ADDR)
-#define I2C2_CSR_VAL                     REG16_VAL(0x0004+I2C2_BASE_ADDR)
-#define I2C2_ISR_VAL                     REG16_VAL(0x0006+I2C2_BASE_ADDR)
-#define I2C2_IMR_VAL                     REG16_VAL(0x0008+I2C2_BASE_ADDR)
-#define I2C2_CDR_VAL                     REG16_VAL(0x000A+I2C2_BASE_ADDR)
-#define I2C2_TR_VAL                      REG16_VAL(0x000C+I2C2_BASE_ADDR)
-#define I2C2_DIV_VAL                     REG16_VAL(0x000E+I2C2_BASE_ADDR)
-
-#define I2C3_CR_VAL                      REG16_VAL(0x0000+I2C3_BASE_ADDR)
-#define I2C3_TCR_VAL                     REG16_VAL(0x0002+I2C3_BASE_ADDR)
-#define I2C3_CSR_VAL                     REG16_VAL(0x0004+I2C3_BASE_ADDR)
-#define I2C3_ISR_VAL                     REG16_VAL(0x0006+I2C3_BASE_ADDR)
-#define I2C3_IMR_VAL                     REG16_VAL(0x0008+I2C3_BASE_ADDR)
-#define I2C3_CDR_VAL                     REG16_VAL(0x000A+I2C3_BASE_ADDR)
-#define I2C3_TR_VAL                      REG16_VAL(0x000C+I2C3_BASE_ADDR)
-#define I2C3_DIV_VAL                     REG16_VAL(0x000E+I2C3_BASE_ADDR)
-
-#define I2C4_CR_VAL                      REG16_VAL(0x0000+I2C4_BASE_ADDR)
-#define I2C4_TCR_VAL                     REG16_VAL(0x0002+I2C4_BASE_ADDR)
-#define I2C4_CSR_VAL                     REG16_VAL(0x0004+I2C4_BASE_ADDR)
-#define I2C4_ISR_VAL                     REG16_VAL(0x0006+I2C4_BASE_ADDR)
-#define I2C4_IMR_VAL                     REG16_VAL(0x0008+I2C4_BASE_ADDR)
-#define I2C4_CDR_VAL                     REG16_VAL(0x000A+I2C4_BASE_ADDR)
-#define I2C4_TR_VAL                      REG16_VAL(0x000C+I2C4_BASE_ADDR)
-#define I2C4_DIV_VAL                     REG16_VAL(0x000E+I2C4_BASE_ADDR)
-
-/* Slave Val Registers*/
-#define I2C_SCR_VAL                     REG16_VAL(0x0010+I2C_BASE_ADDR)
-#define I2C_SSR_VAL                     REG16_VAL(0x0012+I2C_BASE_ADDR)
-#define I2C_SISR_VAL                    REG16_VAL(0x0014+I2C_BASE_ADDR)
-#define I2C_SIMR_VAL                    REG16_VAL(0x0016+I2C_BASE_ADDR)
-#define I2C_SDR_VAL                     REG16_VAL(0x0018+I2C_BASE_ADDR)
-#define I2C_STR_VAL                     REG16_VAL(0x001A+I2C_BASE_ADDR)
-
-/*
- *  I2C_CR_REG
- *  I2C Controller Control
- */
-/* Reserved [15:05] */
-/* [04:04] -- PCLK_SLE tied to Zero */
-#define I2C_CR_CPU_RDY                  0x0008
-#define I2C_CR_TX_END                   0x0004
-#define I2C_CR_TX_NEXT_NO_ACK           0x0002
-#define I2C_CR_TX_NEXT_ACK              0x0000
-#define I2C_CR_ENABLE                   0x0001
-#define I2C_SLAV_MODE_SEL		0x8000
-/*
- *  I2C_TCR_REG
- *  I2C Transfer Control
- *
- */
-#define I2C_TCR_HS_MODE			0x2000		/* [13:13] */
-#define I2C_TCR_STANDARD_MODE           0x0000          /* [15:15] */
-#define I2C_TCR_FAST_MODE               0x8000
-#define I2C_TCR_MASTER_WRITE            0x0000          /* [14:14] */
-#define I2C_TCR_MASTER_READ             0x4000
-/* Reserved [13:07] */
-#define I2C_TCR_SLAVE_ADDR_MASK         0x007F          /* [06:00] */
-
-/*
- *  I2C_CSR_REG
- *  I2C Status
- *
- */
-/* Reserved [15:02] */
-#define I2C_READY                       0x0002          /* [01:01] R */
-#define I2C_BUSY                        0x0000
-#define I2C_STATUS_MASK                 0x0002
-#define I2C_CSR_RCV_ACK                 0x0000          /* [00:00] R */
-#define I2C_CSR_RCV_NOT_ACK             0x0001
-#define I2C_CSR_RCV_ACK_MASK            0x0001
-
-/*
- *  I2C_ISR_REG
- *  I2C Interrupt Status
- *
- */
-/* Reserved [15:03] */
-#define I2C_ISR_SCL_TIME_OUT              0x0004          /* [02:02] R */
-#define I2C_ISR_SCL_TIME_OUT_WRITE_CLEAR  0x0004
-#define I2C_ISR_BYTE_END                  0x0002          /* [01:01] R */
-#define I2C_ISR_BYTE_END_WRITE_CLEAR      0x0002
-#define I2C_ISR_NACK_ADDR                 0x0001          /* [00:00] R */
-#define I2C_ISR_NACK_ADDR_WRITE_CLEAR     0x0001
-
-#define I2C_ISR_ALL_WRITE_CLEAR           0x0007
-/*
- *  I2C_IMR_REG
- *  I2C Interrupt Mask
- *
- */
-/* Reserved [15:03] */
-#define I2C_IMR_SCL_TIME_OUT_MASK       0x0004          /* [02:02]  */
-#define I2C_IMR_BYTE_END_MASK           0x0002          /* [01:01]  */
-#define I2C_IMR_NACK_ADDR_MASK          0x0001          /* [00:00]  */
-
-#define I2C_IMR_ALL_ENABLE              0x0007
-/*
- *  I2C_CDR_REG
- *  I2C Data IO
- *
- */
-#define I2C_CDR_DATA_READ_MASK          0xFF00          /* [15:08]  */
-#define I2C_CDR_DATA_WRITE_MASK         0x00FF          /* [07:00]  */
-
-
-/*
- *  I2C_TR_REG
- *  I2C Timer Parameters
- *
- */
-#define I2C_TR_SCL_TIME_OUT_MASK        0xFF00          /* [15:08]  */
-#define I2C_TR_FSTP_MASK                0x00FF          /* [07:00]  */
-
-#define I2C_TR_STD_VALUE                0xFF64    /* standard mode*/
-#define I2C_TR_FAST_VALUE               0xFF19    /* fast mode*/
-
-
-/*
- *  I2C_DIV_REG
- *  I2C DIV
- *
- */
-#define APB_96M_I2C_DIV                 7  /*Dean revised 2007/9/11 */
-#define APB_166M_I2C_DIV                12 /*Dean revised 2008/5/9 */
-
-
-
-/*
- *  I2C slave registers setting
- *
- */
-#define HS_MASTER_CODE			0x0800
-
-#define I2C_SLAVE_ADDR 0x59
-#define I2C_SLAVE_MASK 0x007F
-#define I2C_SLAVE_NACK BIT12
-#define I2C_SLAVE_HS_MODE BIT14
-#define I2C_SLAVE_EN BIT15
-
-#define I2C_SISR_SCL_TIME_OUT              0x0004          /* [02:02] R */
-#define I2C_SISR_SCL_TIME_OUT_WRITE_CLEAR  0x0004
-#define I2C_SISR_BYTE_END                  0x0002          /* [01:01] R */
-#define I2C_SISR_BYTE_END_WRITE_CLEAR      0x0002
-#define I2C_SISR_DAT_REQ                      0x0001          /* [00:00] R */
-#define I2C_SISR_DAT_REQ_WRITE_CLEAR          0x0001
-
-#define I2C_SISR_ALL_WRITE_CLEAR           0x0007
-
-#define I2C_SIMR_SCL_TIME_OUT_MASK       0x0004          /* [02:02]  */
-#define I2C_SIMR_BYTE_END_MASK           0x0002          /* [01:01]  */
-#define I2C_SIMR_NACK_ADDR_MASK          0x0001          /* [00:00]  */
-
-#define I2C_SIMR_ALL_ENABLE              0x0007
-
-#define I2C_SRCV_NACK BIT0
-#define I2C_SREAD BIT1
-#define I2C_SACT BIT2
-
-#define I2C_SLAVE_WRITE_DATA_SHIFT 0
-#define I2C_SLAVE_READ_DATA_SHIFT 8
-#define I2C_SLAVE_READ_DATA_MASK 0xFF00
-#define I2C_SLAVE_WRITE_DATA_MASK 0x00FF
-
-enum i2c_mode_e {
-	I2C_STANDARD_MODE = 0 ,
-	I2C_FAST_MODE     = 1,
-	I2C_HS_MODE	= 2,
-};
-
-struct i2c_regs_s {
-	volatile unsigned short cr_reg;		/* IIC controller control register*/
-	volatile unsigned short tcr_reg;		/* IIC controller transfer control register*/
-	volatile unsigned short csr_reg;		/* IIC controller status register*/
-	volatile unsigned short isr_reg;		/* IIC controller interrupt status register*/
-	volatile unsigned short imr_reg;		/* IIC controller interrupt mask register*/
-	volatile unsigned short cdr_reg;		/* IIC controller data I/O buffer register*/
-	volatile unsigned short tr_reg;		/* IIC controller time parameter register*/
-	volatile unsigned short div_reg;		/* IIC controller clock divider register*/
-	volatile unsigned short scr_reg;		/* IIC slave controller control register*/
-	volatile unsigned short cssr_reg;		/* IIC slave controller status register*/
-	volatile unsigned short sisr_reg;	/* IIC slave controller interrupt status register*/
-	volatile unsigned short simr_reg;	/* IIC slave controller interrupt mask register*/
-	volatile unsigned short csdr_reg;		/* IIC slave controller data I/O buffer register*/
-	volatile unsigned short str_reg;		/* IIC slave controller time parameter register*/
-};
-
-#define SUSPEND_NOTIFY 0
-#define SUSPEND_SAVE_STATE 1
-#define SUSPEND_DISABLE 2
-#define SUSPEND_POWER_DOWN 3
-#define RESUME_POWER_ON 0
-#define RESUME_RESTORE_STATE 1
-#define RESUME_ENABLE 2
-
-#define I2C_ALGO_WMT                 0x00900000    /* via WMT on-chip i2c algo*/
-
-#define I2C_ADAPTER_RETRIES             3
-#define I2C_ALGO_UDELAY                 10
-#define I2C_ALGO_TIMEOUT                500
-
-#define MAX_MESSAGES            65536   /* maximum number of messages to send*/
-
-
-#define I2C_SET_STANDARD_MODE           0x07A0
-#define I2C_SET_FAST_MODE                       0x07A1
-
-#if 0
-struct i2c_algo_wmt_data {
-	int  (*write_msg)(unsigned int slave_addr, char *buf, unsigned int length , int restart, int last) ;
-	int  (*read_msg)(unsigned int slave_addr, char *buf, unsigned int length , int restart, int last) ;
-	int  (*send_request)(struct i2c_msg *msg, int msg_num, int non_block);
-#ifdef CONFIG_SND_SOC_VT1603
-	int (*vt1603_write_for_read)(unsigned int slave_addr, char *buf, unsigned int length , int restart, int last);
-#endif
-	int  (*wait_bus_not_busy) (void);
-	void (*reset) (void);
-	void (*set_mode)(enum i2c_mode_e) ;
-	int  udelay;
-	int  timeout;
-};
-#endif
-
-#endif
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_i2s.h b/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_i2s.h
deleted file mode 100755
index 9e7268c1..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_i2s.h
+++ /dev/null
@@ -1,197 +0,0 @@
-/*++
-linux/include/asm-arm/arch-wmt/wmt_i2s.h
-
-Copyright (c) 2008  WonderMedia Technologies, Inc.
-
-This program is free software: you can redistribute it and/or modify it under the
-terms of the GNU General Public License as published by the Free Software Foundation,
-either version 2 of the License, or (at your option) any later version.
-
-This program is distributed in the hope that it will be useful, but WITHOUT
-ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-PARTICULAR PURPOSE.  See the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License along with
-this program.  If not, see <http://www.gnu.org/licenses/>.
-
-WonderMedia Technologies, Inc.
-10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
---*/
-/* Be sure that virtual mapping is defined right */
-#ifndef __ASM_ARCH_HARDWARE_H
-#error "You must include hardware.h, not wmt_i2s.h"
-#endif
-
-#ifndef _WMT_I2S_H_
-#define _WMT_I2S_H_
-
-
-/******************************************************************************
- *
- * Address constant for each register.
- *
- ******************************************************************************/
-#define	DACCFG_ADDR       		(I2S_BASE_ADDR + 0x0040)
-#define HDACKGEN_ADDR			(I2S_BASE_ADDR + 0x0070)
-#define ADCCFG_ADDR				(I2S_BASE_ADDR + 0x0080)
-#define AADCF0CFG_ADDR			(I2S_BASE_ADDR + 0x008C)
-#define AADCF0STA_ADDR			(I2S_BASE_ADDR + 0x0090)
-#define AADCF1CFG_ADDR			(I2S_BASE_ADDR + 0x009C)
-#define AADCF1STA_ADDR			(I2S_BASE_ADDR + 0x00A0)
-#define DGOCFG_ADDR				(I2S_BASE_ADDR + 0x00C0)
-
-#define ASMPFCFG_ADDR			(I2S_BASE_ADDR + 0x0180)
-#define ASMPFRDY_ADDR			(I2S_BASE_ADDR + 0x0184)
-#define ASMPF2HDACFG_ADDR		(I2S_BASE_ADDR + 0x0188)
-#define ASMPF2HDACHCFG_ADDR		(I2S_BASE_ADDR + 0x018C)
-#define ASMPFCHCFG0_ADDR		(I2S_BASE_ADDR + 0x0194)
-#define ASMPFCHCFG1_ADDR		(I2S_BASE_ADDR + 0x0198)
-#define AUDPRFRST_ADDR			(I2S_BASE_ADDR + 0x0244)
-#define AADCFOBDOUT_DMA_ADDR	(I2S_BASE_ADDR + 0x0300)
-#define ASMPFDP_DMA_ADDR		(I2S_BASE_ADDR + 0x0360)
-#define DZDRQ8_CFG_ADDR			(I2S_BASE_ADDR + 0x03A0)
-#define DZDRQ9_CFG_ADDR			(I2S_BASE_ADDR + 0x03A4)
-#define DZDRQA_CFG_ADDR			(I2S_BASE_ADDR + 0x03A8)
-#define DGOCS0A_ADDR			(I2S_BASE_ADDR + 0x0114)
-#define DGOCS1A_ADDR			(I2S_BASE_ADDR + 0x012C)
-
-
-/******************************************************************************
- *
- * Register pointer.
- *
- ******************************************************************************/
-#define	DACCFG_REG        		(REG32_PTR(DACCFG_ADDR))
-#define	HDACKGEN_REG        	(REG32_PTR(HDACKGEN_ADDR))
-#define	ADCCFG_REG        		(REG32_PTR(ADCCFG_ADDR))
-#define	AADCF0CFG_REG      		(REG32_PTR(AADCF0CFG_ADDR))
-#define	AADCF0STA_REG        	(REG32_PTR(AADCF0STA_ADDR))
-#define	AADCF1CFG_REG      		(REG32_PTR(AADCF1CFG_ADDR))
-#define	AADCF1STA_REG        	(REG32_PTR(AADCF1STA_ADDR))
-#define	DGOCFG_REG        		(REG32_PTR(DGOCFG_ADDR))
-
-#define	ASMPFCFG_REG        	(REG32_PTR(ASMPFCFG_ADDR))
-#define	ASMPFRDY_REG        	(REG32_PTR(ASMPFRDY_ADDR))
-#define	ASMPF2HDACFG_REG        (REG32_PTR(ASMPF2HDACFG_ADDR))
-#define	ASMPF2HDACHCFG_REG      (REG32_PTR(ASMPF2HDACHCFG_ADDR))
-#define	ASMPFCHCFG0_REG        	(REG32_PTR(ASMPFCHCFG0_ADDR))
-#define	ASMPFCHCFG1_REG        	(REG32_PTR(ASMPFCHCFG1_ADDR))
-#define	AUDPRFRST_REG        	(REG32_PTR(AUDPRFRST_ADDR))
-#define	AADCFOBDOUT_DMA_REG		(REG32_PTR(AADCFOBDOUT_DMA_ADDR))
-#define	ASMPFDP_DMA_REG			(REG32_PTR(ASMPFDP_DMA_ADDR))
-#define	DZDRQ8_CFG_REG			(REG32_PTR(DZDRQ8_CFG_ADDR))
-#define	DZDRQ9_CFG_REG			(REG32_PTR(DZDRQ9_CFG_ADDR))
-#define	DZDRQA_CFG_REG			(REG32_PTR(DZDRQA_CFG_ADDR))
-#define	DGOCS0A_REG				(REG32_PTR(DGOCS0A_ADDR))
-#define	DGOCS1A_REG				(REG32_PTR(DGOCS1A_ADDR))
-
-
-/******************************************************************************
- *
- * Register value.
- *
- ******************************************************************************/
-#define	DACCFG_VAL        		(REG32_VAL(DACCFG_ADDR))
-#define	HDACKGEN_VAL        	(REG32_VAL(HDACKGEN_ADDR))
-#define	ADCCFG_VAL        		(REG32_VAL(ADCCFG_ADDR))
-#define	AADCF0CFG_VAL      		(REG32_VAL(AADCF0CFG_ADDR))
-#define	AADCF0STA_VAL     		(REG32_VAL(AADCF0STA_ADDR))
-#define	AADCF1CFG_VAL      		(REG32_VAL(AADCF1CFG_ADDR))
-#define	AADCF1STA_VAL     		(REG32_VAL(AADCF1STA_ADDR))
-#define	DGOCFG_VAL     			(REG32_VAL(DGOCFG_ADDR))
-
-#define	ASMPFCFG_VAL        	(REG32_VAL(ASMPFCFG_ADDR))
-#define	ASMPFRDY_VAL        	(REG32_VAL(ASMPFRDY_ADDR))
-#define	ASMPF2HDACFG_VAL        (REG32_VAL(ASMPF2HDACFG_ADDR))
-#define	ASMPF2HDACHCFG_VAL      (REG32_VAL(ASMPF2HDACHCFG_ADDR))
-#define	ASMPFCHCFG0_VAL        	(REG32_VAL(ASMPFCHCFG0_ADDR))
-#define	ASMPFCHCFG1_VAL        	(REG32_VAL(ASMPFCHCFG1_ADDR))
-#define	AUDPRFRST_VAL        	(REG32_VAL(AUDPRFRST_ADDR))
-#define	AADCFOBDOUT_DMA_VAL		(REG32_VAL(AADCFOBDOUT_DMA_ADDR))
-#define	ASMPFDP_DMA_VAL			(REG32_VAL(ASMPFDP_DMA_ADDR))
-#define	DZDRQ8_CFG_VAL			(REG32_VAL(DZDRQ8_CFG_ADDR))
-#define	DZDRQ9_CFG_VAL			(REG32_VAL(DZDRQ9_CFG_ADDR))
-#define	DZDRQA_CFG_VAL			(REG32_VAL(DZDRQA_CFG_ADDR))
-#define	DGOCS0A_VAL				(REG32_VAL(DGOCS0A_ADDR))
-#define	DGOCS1A_VAL				(REG32_VAL(DGOCS1A_ADDR))
-
-
-/******************************************************************************
- *
- * 
- *
- ******************************************************************************/
-#define DACITF_ENABLE				BIT22			/* DAC interface enable */
-
-#define ASMPF_8BIT_SMP				0x00			/* sample quantization config for 8 bit */
-#define ASMPF_16BIT_SMP				0x10			/* sample quantization config for 16 bit */
-#define ASMPF_32BIT_SMP				0x20			/* sample quantization config for 32 bit */
-#define ASMPF_ENABLE				BIT6			/* sample FIFO enable */
-#define ASMPF_EXCH_FMT				BIT7			/* sample FIFO exchange unsigned/signed format enable */
-#define ASMPF_EXCH_ENDIAN			BIT8			/* sample FIFO exchange little/big endian enable */
-
-#define AADCF_ENABLE				BIT0			/* ADC FIFO enable */
-#define AADCF16_ENABLE				BIT1			/* ADC FIFO 16-bits enable */
-#define AADCITF_ENABLE				BIT2			/* ADC interface enable */
-#define DGOITF_ENABLE				BIT7			/* ADGO(SPDIF-out) interface enable */
-#define ADGIF16_ENABLE				BIT14			/* ADGI FIFO 16-bits enable */
-#define ADGIITF_ENABLE				BIT1			/* ADGI(SPDIF-in) interface enable */
-#define ADGI_EXTRACTOR_ENABLE		BIT0			/* ADGI-Extractor enable */
-
-#define ASMPF_RESET					BIT1			/* sample FIFO reset */
-#define DACITF_RESET				BIT2			/* DAC interface reset */
-#define ADCITF_RESET				BIT3			/* ADC interface & ADC FIFO reset */
-#define DGOITF_RESET				BIT4			/* SPDIF out reset */
-
-#define HDACKGEN_ENABLE				BIT4			/* HDAudio Reference Clock enable */
-
-
-#define WMT_SND_I2C_BUS				0x00
-#define WMT_SND_SPI_BUS				0x01
-
-#define WMT_SND_LINEIN_1			0x00
-#define WMT_SND_MICIN_1				0x01
-#define WMT_SND_DMIC_IN				0x02
-#define WMT_SND_LINEIN_12			0x03
-#define WMT_SND_LINEIN_2			0x04
-#define WMT_SND_MICIN_2				0x05
-#define WMT_SND_MICIN_12			0x06
-
-
-
-
-
-
-
-
-
-struct i2s_ints_s {
-	/* Tx FIFO Status. */
-	unsigned int tfoe;      /* Tx FIFO Overrun Error */
-	unsigned int tfue;      /* Tx FIFO Underrun Error */
-	unsigned int tfa;       /* Tx FIFO Almost Empty */
-	unsigned int tfe;       /* Tx FIFO Empty */
-
-	/* Tx FIFO Status. */
-	unsigned int rfoe;      /* Tx FIFO Overrun Error */
-	unsigned int rfue;      /* Tx FIFO Underrun Error */
-	unsigned int rfa;       /* Tx FIFO Almost Full */
-	unsigned int rff;       /* Tx FIFO Full */
-
-};
-
-struct i2s_s {
-	/* Interrupt status counters.*/
-	struct i2s_ints_s             ints;
-	/* I2S Controller info. */
-	const unsigned int      irq;            /* I2S controller irq*/
-	unsigned int            ref;            /* I2S reference counter*/
-	unsigned int			channels;
-	int						format;
-	unsigned int			fragment_sz;
-	unsigned int			rate;
-	/* Basic handlers.*/
-	void                    (*init)(int mode);
-	void                    (*exit)(void);
-};
-
-#endif /* __WMT_I2S_H */
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_iomux.h b/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_iomux.h
deleted file mode 100755
index fdb81566..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_iomux.h
+++ /dev/null
@@ -1,45 +0,0 @@
-
-#ifndef __MACH_WMT_IOMUX_H__
-#define __MACH_WMT_IOMUX_H__
-
-#include <linux/types.h>
-
-#undef	WMT_PIN
-#define WMT_PIN(__gp, __bit, __irq, __name)	__name,
-enum iomux_pins {
-	#include "iomux.h"
-};
-
-/* use gpiolib dispatchers */
-#define gpio_get_value		__gpio_get_value
-#define gpio_set_value		__gpio_set_value
-#define gpio_cansleep		__gpio_cansleep
-
-enum wmt_gpio_pulltype {
-	WMT_GPIO_PULL_NONE = 0,
-	WMT_GPIO_PULL_UP,
-	WMT_GPIO_PULL_DOWN,
-};
-extern int wmt_gpio_setpull(unsigned int gpio, enum wmt_gpio_pulltype pull);
-extern int wmt_gpio_getpull(unsigned int gpio);
-extern const char *wmt_gpio_name(int gpio);
-
-/* below for gpio irq */
-
-extern void wmt_gpio_ack_irq(unsigned int gpio);
-extern void wmt_gpio_mask_irq(unsigned int gpio);
-extern void wmt_gpio_unmask_irq(unsigned int gpio);
-extern int is_gpio_irqenable(u32 irqindex);
-extern int gpio_irqstatus(unsigned int gpio);
-/*
- * current support type: (in <linux/irq.h>)
- *	IRQ_TYPE_EDGE_RISING
- *	IRQ_TYPE_EDGE_FALLING
- *	IRQ_TYPE_EDGE_BOTH
- *	IRQ_TYPE_LEVEL_LOW
- *	IRQ_TYPE_LEVEL_HIGH
- */
-extern int wmt_gpio_set_irq_type(unsigned int gpio, u32 type);
-
-#endif /* #ifndef __MACH_WMT_IOMUX_H__ */
-
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_kpad.h b/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_kpad.h
deleted file mode 100755
index 43ca0ea2..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_kpad.h
+++ /dev/null
@@ -1,270 +0,0 @@
-/*++
-linux/include/asm-arm/arch-wmt/wmt_lpad.h
-
-Copyright (c) 2008  WonderMedia Technologies, Inc.
-
-This program is free software: you can redistribute it and/or modify it under the
-terms of the GNU General Public License as published by the Free Software Foundation,
-either version 2 of the License, or (at your option) any later version.
-
-This program is distributed in the hope that it will be useful, but WITHOUT
-ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-PARTICULAR PURPOSE.  See the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License along with
-this program.  If not, see <http://www.gnu.org/licenses/>.
-
-WonderMedia Technologies, Inc.
-10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
---*/
-/* Be sure that virtual mapping is defined right */
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#error "You must include hardware.h, not wmt_kpad.h"
-#endif
-
-#ifndef __WMT_KPAD_H
-#define __WMT_KPAD_H
-
-/*=============================================================================
- *
- *Define the register access macros.
- *
- *Note: Current policy in standalone program is using register as a pointer.
- *
- *=============================================================================*/
-
-/*=============================================================================
- *
- * WMT Keypad Base Address.
- *
- *=============================================================================*/
-#ifdef __KPAD_BASE
-#error "__KPAD_BASE has already been defined in another file."
-#else
-    #define    __KPAD_BASE    KPAD_BASE_ADDR /* 64K */
-#endif
-/*=============================================================================
- *
- * WMT Keypad control registers.
- *
- * Registers Abbreviations:
- *
- * KPMCR_REG    Keypad Matrix Control Register.
- *
- * KPDCR_REG    Keypad Direct Input Control Register.
- *
- * KPICR_REG    Keypad Invert Input Control Register.
- *
- * KPSTR_REG    Keypad STatus Register.
- *
- * KPMAR_REG    Keypad Matrix Primary Key Automatic Scan Register.
- *
- * KPDSR_REG    Keypad Direct Input Key Scan Register.
- *
- * KPMMR_REG    Keypad Matrix Manual Key Scan Register.
- *
- * KPRIR_REG    Keypad Row Input Register.
- *
- * KPMR0_REG    Keypad Matrix Multiple Keys Scan Register 0.
- *
- * KPMR1_REG    Keypad Matrix Multiple Keys Scan Register 1.
- *
- * KPMR2_REG    Keypad Matrix Multiple Keys Scan Register 2.
- *
- * KPMR3_REG    Keypad Matrix Multiple Keys Scan Register 3.
- *
- * KPMIR_REG    Keypad Matrix Debounce and Scan Interval Register.
- *
- * KPDIR_REG    Keypad Direct Input Debounce Interval Register.
- *
- *=============================================================================*/
-/*=============================================================================
- *
- * Address constant for each register.
- *
- *=============================================================================*/
-#define    KPMCR_ADDR		(__KPAD_BASE + 0x00)
-#define    KPDCR_ADDR		(__KPAD_BASE + 0x04)
-#define    KPICR_ADDR		(__KPAD_BASE + 0x08)
-#define    KPSTR_ADDR		(__KPAD_BASE + 0x0C)
-#define    KPMAR_ADDR		(__KPAD_BASE + 0x10)
-#define    KPDSR_ADDR		(__KPAD_BASE + 0x14)
-#define    KPMMR_ADDR		(__KPAD_BASE + 0x18)
-#define    KPRIR_ADDR		(__KPAD_BASE + 0x1C)
-#define    KPMR0_ADDR		(__KPAD_BASE + 0x20)
-#define    KPMR1_ADDR		(__KPAD_BASE + 0x24)
-#define    KPMR2_ADDR		(__KPAD_BASE + 0x28)
-#define    KPMR3_ADDR		(__KPAD_BASE + 0x2C)
-#define    KPMIR_ADDR		(__KPAD_BASE + 0x30)
-#define    KPDIR_ADDR		(__KPAD_BASE + 0x34)
-
-
-/*=============================================================================
- *
- * Register pointer.
- *
- *=============================================================================*/
-#define    KPMCR_REG       (REG32_PTR(KPMCR_ADDR))
-#define    KPDCR_REG       (REG32_PTR(KPDCR_ADDR))
-#define    KPICR_REG       (REG32_PTR(KPICR_ADDR))
-#define    KPSTR_REG       (REG32_PTR(KPSTR_ADDR))
-#define    KPMAR_REG       (REG32_PTR(KPMAR_ADDR))
-#define    KPDSR_REG       (REG32_PTR(KPDSR_ADDR))
-#define    KPMMR_REG       (REG32_PTR(KPMMR_ADDR))
-#define    KPRIR_REG       (REG32_PTR(KPRIR_ADDR))
-#define    KPMR0_REG       (REG32_PTR(KPMR0_ADDR))
-#define    KPMR1_REG       (REG32_PTR(KPMR1_ADDR))
-#define    KPMR2_REG       (REG32_PTR(KPMR2_ADDR))
-#define    KPMR3_REG       (REG32_PTR(KPMR3_ADDR))
-#define    KPMIR_REG       (REG32_PTR(KPMIR_ADDR))
-#define    KPDIR_REG       (REG32_PTR(KPDIR_ADDR))
-
-/*=============================================================================
- *
- * Register value.
- *
- *=============================================================================*/
-#define    KPMCR_VAL       (REG32_VAL(KPMCR_ADDR))
-#define    KPDCR_VAL       (REG32_VAL(KPDCR_ADDR))
-#define    KPICR_VAL       (REG32_VAL(KPICR_ADDR))
-#define    KPSTR_VAL       (REG32_VAL(KPSTR_ADDR))
-#define    KPMAR_VAL       (REG32_VAL(KPMAR_ADDR))
-#define    KPDSR_VAL       (REG32_VAL(KPDSR_ADDR))
-#define    KPMMR_VAL       (REG32_VAL(KPMMR_ADDR))
-#define    KPRIR_VAL       (REG32_VAL(KPRIR_ADDR))
-#define    KPMR0_VAL       (REG32_VAL(KPMR0_ADDR))
-#define    KPMR1_VAL       (REG32_VAL(KPMR1_ADDR))
-#define    KPMR2_VAL       (REG32_VAL(KPMR2_ADDR))
-#define    KPMR3_VAL       (REG32_VAL(KPMR3_ADDR))
-#define    KPMIR_VAL       (REG32_VAL(KPMIR_ADDR))
-#define    KPDIR_VAL       (REG32_VAL(KPDIR_ADDR))
-
-/*=============================================================================
- *
- *    16' h0038-16' hFFFF Reserved (Read-only, all zeros)
- *
- *=============================================================================*/
-
-/*=============================================================================
- *
- * KPMCR_REG    Keypad Matrix Control Register.
- *
- *=============================================================================*/
-#define KPMCR_EN			BIT0		/* Keypad Matrix Enable bit. */
-#define KPMCR_IEN			BIT1		/* Keypad Matrix Interrupt Request Enable bit. */
-#define KPMCR_AS			BIT2		/* Keypad Matrix Automatic Scan bit. */
-#define KPMCR_ASA			BIT3		/* Keypad Matrix Automatic Scan on Activity bit. */
-#define KPMCR_IMK			BIT4		/* Keypad Matrix Ignore Multiple Key-press bit. */
-#define KPMCR_COLMASK		0x0700		/* Keypad Matrix Column Number bits. */
-#define KPMCR_ROWMASK		0x7000		/* Keypad Matrix Row Number bits. */
-#define KPMCR_MSMASK		(0xFF << 16)	/* Manual Keypad Matrix Scan Output signals */
-#define KPMCR_COL(x)		(((x) <<  8) & KPMCR_COLMASK)
-#define KPMCR_ROW(x)		(((x) << 12) & KPMCR_ROWMASK)
-#define KPMCR_MS(x)			(((x) << 16) & KPMCR_MSMASK)
-
-/*=============================================================================
- *
- * KPDCR_REG    Keypad Direct Input Control Register.
- *
- *=============================================================================*/
-#define KPDCR_EN			BIT0			/* Direct Input Enable */
-#define KPDCR_IEN			BIT1			/* Direct Input Interrupt Request Enable */
-#define KPDCR_ASA			BIT3			/* Direct Input Automatic Scan on Activity */
-#define KPDCR_IMK			BIT4			/* Direct Input Ignore Muiltiple Key-press */
-#define KPDCR_DENMASK		(0xFF << 16)	/* Direct Input Enable bit[0:7] */
-#define KPDCR_DEN(x)		(((x) << 16) & KPDCR_DENMASK)
-
-/*=============================================================================
- *
- * KPICR_REG    Keypad Invert Input Control Register.
- *
- *=============================================================================*/
-#define KPICR_IRIMASK		(0xFF << 16)	/* Invert Row input signals */
-#define KPICR_IRI(x)		(((x) << 16) & KPICR_IRIMASK)
-
-/*=============================================================================
- *
- * KPSTR_REG    Keypad Status Register.
- *
- *=============================================================================*/
-#define KPSTR_MDA			BIT0		/* Keypad Matrix Manual Debounce Active Key bit. */
-#define KPSTR_ASA			BIT1		/* Keypad Matrix Automatic Scan on Activity bit. */
-#define KPSTR_ASC			BIT2		/* Keypad Matrix Automatic Scan Completed bit.   */
-#define KPSTR_DIA			BIT3		/* Keypad Direct Input Active bit.               */
-#define KPSTR_MASK			0xF
-
-/*=============================================================================
- *
- * KPMAR_REG    Keypad Matrix Primary Key Automatic Scan Register.
- *
- *=============================================================================*/
-#define KPMAR_COLMASK		(BIT0 | BIT1 | BIT2)
-#define KPMAR_ROWMASK		(BIT4 | BIT5 | BIT6)
-#define KPMAR_KEYMASK		(BIT29 | BIT30)
-#define KPMAR_KEYSHIFT		29
-#define KPMAR_KEY(reg)		(((reg) & KPMAR_KEYMASK) >> KPMAR_KEYSHIFT)
-#define KPMAR_NOKEY			0x0		/* Bit[29:30] no key pressed.  */
-#define KPMAR_ONEKEY		0x1		/* Bit[29:30] one key pressed. */
-#define KPMAR_MULTIKEYS		0x2		/* Bit[29:30] multiple keys pressed.*/
-/* Notice that 0x3 is also multikeys */
-#define KPMAR_VALID			BIT31
-
-/*
- * Keypad Direct Input Key Scan Register
- */
-#define Dir_Input			(BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6|BIT7)
-#define Dir_Vaild_Scan		(BIT31)
-
-/*
- * Keypad Manual Matrix Key Scan Register
- */
-
-/*
- * Keypad Row Input Register
- */
-#define Row_Input			(BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6|BIT7)
-
-/*=============================================================================
- *
- * KPMR0_REG    Keypad Matrix Multiple Key Scan Register 0.
- * KPMR1_REG    Keypad Matrix Multiple Key Scan Register 1.
- * KPMR2_REG    Keypad Matrix Multiple Key Scan Register 2.
- * KPMR3_REG    Keypad Matrix Multiple Key Scan Register 3.
- *
- *=============================================================================*/
-#define KPMRX_VALID			BIT31
-#define KPMRX_EVENMASK		0xFF			/* Even Column Row Input Active bits. */
-#define KPMRX_ODDMASK		(0xFF << 16)	/* Odd Column Row Input Active bits.  */
-
-/*=============================================================================
- *
- * KPMIR_REG    Keypad Matrix Debounce and Scan Interval Register.
- *
- *=============================================================================*/
-#define KPMIR_DIMASK		0x0FFF			/* Matrix debounce interval mask */
-#define KPMIR_SIMASK		(0xFF << 16)	/* Keypaf scan interval mask */
-#define KPMIR_DI(x)			((x) & KPMIR_DIMASK)
-#define KPMIR_SI(x)			(((x) << 16) & KPMIR_SIMASK)
-
-/*=============================================================================
- *
- * KPDIR_REG    Keypad Direct Debounce and Scan Interval Register.
- *
- *=============================================================================*/
-#define KPDIR_DIMASK		0x0FFF			/* Direct input debounce interval mask */
-#define KPDIR_DI(x)			((x) & KPDIR_DIMASK)
-
-/*=============================================================================
- *
- * Feature Supported (Keypad Module)
- *
- *=============================================================================*/
-/*
-#define AutoScna		(MIE | MAS | MASA)
-#define ManualScan		(MIE & (~MAS) & (~MASA))
-#define DirectScan		((~MAS) & (~MASA))
-#define Col3xRow4		(Col3 | Row4)
-#define Col4xRow4		(Col4 | Row4)
-*/
-#endif
-
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_mc5.h b/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_mc5.h
deleted file mode 100755
index ba21407f..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_mc5.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/*++
-linux/include/asm-arm/arch-wmt/wmt_mc5.h
-
-Copyright (c) 2008  WonderMedia Technologies, Inc.
-
-This program is free software: you can redistribute it and/or modify it under the
-terms of the GNU General Public License as published by the Free Software Foundation,
-either version 2 of the License, or (at your option) any later version.
-
-This program is distributed in the hope that it will be useful, but WITHOUT
-ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-PARTICULAR PURPOSE.  See the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License along with
-this program.  If not, see <http://www.gnu.org/licenses/>.
-
-WonderMedia Technologies, Inc.
-10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
---*/
-
-/* Be sure that virtual mapping is defined right */
-#ifndef __ASM_ARCH_HARDWARE_H
-#error "You must include hardware.h, not vt8500_pmc.h"
-#endif
-
-#ifndef __VT8500_MC5_H
-#define __VT8500_MC5_H
-
-/******************************************************************************
- *
- * Define the register access macros.
- *
- * Note: Current policy in standalone program is using register as a pointer.
- *
- ******************************************************************************/
-#include "wmt_mmap.h"
-
-/******************************************************************************
- *
- * VT8500 Power Management Controller Base Address.
- *
- ******************************************************************************/
-#ifdef __MC5_BASE
-#error "__RTC_BASE has already been defined in another file."
-#endif
-#ifdef MEMORY_CTRL_V4_CFG_BASE_ADDR               /* From vt8500.mmap.h */
-#define __MC5_BASE      MEMORY_CTRL_V4_CFG_BASE_ADDR
-#else
-#define __MC5_BASE      0xFE000400      /* 64K */
-#endif
-
-/******************************************************************************
- *
- * VT8500 memory control registers.
- *
- ******************************************************************************/
-/******************************************************************************
- *
- * Address constant for each register.
- *
- ******************************************************************************/
-#define MC_CLOCK_CTRL0_ADDR      (__MC5_BASE + 0x0024)
-#define MC_CLOCK_CTRL1_ADDR      (__MC5_BASE + 0x0028)
-#define MC_CONF_ADDR      (__MC5_BASE + 0x0034)
-
-
-/******************************************************************************
- *
- * Register pointer.
- *
- ******************************************************************************/
-#define MC_CLOCK_CTRL0_REG			(REG32_PTR(MC_CLOCK_CTRL0_ADDR))/*0x24*/
-#define MC_CLOCK_CTRL1_REG			(REG32_PTR(MC_CLOCK_CTRL1_ADDR))/*0x28*/
-#define MC_CONF_REG      (REG32_PTR(MC_CONF_ADDR))/*0x34*/
-
-/******************************************************************************
- *
- * Register value.
- *
- ******************************************************************************/
-#define MC_CLOCK_CTRL0_VAL			(REG32_VAL(MC_CLOCK_CTRL0_ADDR))/*0x24*/
-#define MC_CLOCK_CTRL1_VAL			(REG32_VAL(MC_CLOCK_CTRL1_ADDR))/*0x28*/
-#define MC_CONF_VAL			(REG32_VAL(MC_CONF_ADDR))/*0x28*/
-
-
-//#define UDC_HOTPLUG_TIMER
-
-#endif /* __VT8500_PMC_H */
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_misc.h b/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_misc.h
deleted file mode 100755
index 10be6d3a..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_misc.h
+++ /dev/null
@@ -1,8 +0,0 @@
-extern void detect_wifi_module(void * pbool);

-extern void wifi_power_ctrl(int open);

-extern int is_mtk6622(void);

-extern int is_rda5991(void);

-extern void wifi_power_ctrl_comm(int open,int mdelay);

-//extern void force_remove_sdio2(void);

-//extern void wmt_detect_sdio2(void);

-

diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_mmap.h b/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_mmap.h
deleted file mode 100755
index ac43beea..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_mmap.h
+++ /dev/null
@@ -1,180 +0,0 @@
-/*++
-linux/include/asm-arm/arch-wmt/wmt_mmap.h
-
-Copyright (c) 2008  WonderMedia Technologies, Inc.
-
-This program is free software: you can redistribute it and/or modify it under the
-terms of the GNU General Public License as published by the Free Software Foundation,
-either version 2 of the License, or (at your option) any later version.
-
-This program is distributed in the hope that it will be useful, but WITHOUT
-ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-PARTICULAR PURPOSE.  See the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License along with
-this program.  If not, see <http://www.gnu.org/licenses/>.
-
-WonderMedia Technologies, Inc.
-10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
---*/
-
-/* Be sure that virtual mapping is defined right */
-#ifndef __ASM_ARCH_HARDWARE_H
-#error "You must include hardware.h, not wmt_mmap.h"
-#endif
-
-#ifndef __WMT_MMAP_H
-#define __WMT_MMAP_H
-
-/**
- * WMT Memory Map for Physical Address 0xD8000000 will be mapped to 
- * Virtual Address 0xFE000000
- */
-#define WMT_MMAP_OFFSET                         (0xFE000000-0xD8000000)
-
-#define EXTERNAL_AHB_BRIDGE_BASE_ADDR           0xB0000000
-#define INTERNAL_AHB_SLAVES_BASE_ADDR           (0xD8000000 + WMT_MMAP_OFFSET)
-#define INTERNAL_APB_SLAVES_BASE_ADDR           (0xD8100000 + WMT_MMAP_OFFSET)
-
-/**
- *  Internal AHB Slaves Memory Address Map
- */
-#define MEMORY_CTRL_V3_CFG_BASE_ADDR            (0xD8000000 + WMT_MMAP_OFFSET)  /* 1K , 8/16/32 RW */
-#define MEMORY_CTRL_V4_CFG_BASE_ADDR            (0xD8000400 + WMT_MMAP_OFFSET)  /* 1K , 8/16/32 RW */
-#define DMA_CTRL0_V3_CFG_BASE_ADDR              (0xD8001000 + WMT_MMAP_OFFSET)  /* 1K , 8/16/32 RW */
-#define DMA_CTRL1_V3_CFG_BASE_ADDR              (0xD8001400 + WMT_MMAP_OFFSET)  /* 1K , 8/16/32 RW */
-#define DMA_CTRL_V4_CFG_BASE_ADDR               (0xD8001800 + WMT_MMAP_OFFSET)  /* 1K , 8/16/32 RW */
-#define PICTOR_DMA_CTRL_CFG_BASE_ADDR           (0xD8001C00 + WMT_MMAP_OFFSET)  /* 1K , 8/16/32 RW */
-#define SF_MEM_CTRL_CFG_BASE_ADDR               (0xD8002000 + WMT_MMAP_OFFSET)  /* 1K , 8/16/32 RW */
-#define LPC_MEM_CTRL_CFG_BASE_ADDR              (0xD8003000 + WMT_MMAP_OFFSET)  /* 1K , 8/16/32 RW */
-#define SPI_MEM_CTRL_CFG_BASE_ADDR              (0xD8003000 + WMT_MMAP_OFFSET)  /* 1K , 8/16/32 RW */
-
-#define ETHERNET_MAC_0_CFG_BASE_ADDR            (0xD8004000 + WMT_MMAP_OFFSET)  /* 1K , 8/16/32 RW */
-
-#define ETHERNET_MAC_1_CFG_BASE_ADDR            (0xD8005000 + WMT_MMAP_OFFSET)  /* 1K , 8/16/32 RW */
-
-#define SECURITY_ENGINE_CFG_BASE_ADDR           (0xD8006000 + WMT_MMAP_OFFSET)  /* 1K , 8/16/32 RW */
-#define SECURITY_ENGINE_CFG_EXTENT_BASE_ADDR    (0xD8006400 + WMT_MMAP_OFFSET)  /* 3K , 8/16/32 RW */
-#define USB20_HOST_CFG_BASE_ADDR                (0xD8007000 + WMT_MMAP_OFFSET)  /* 2K , 8/16/32 RW */
-#define USB20_HOST_DEVICE_CFG_BASE_ADDR         (0xD8007800 + WMT_MMAP_OFFSET)  /* 2K , 8/16/32 RW */
-#define PATA_CTRL_CFG_BASE_ADDR                 (0xD8008000 + WMT_MMAP_OFFSET)  /* 2K , 8/16/32 RW */
-#define PS2_CFG_BASE_ADDR                       (0xD8008800 + WMT_MMAP_OFFSET)  /* 1K , 8/16/32 RW */
-#define USB20_HOST_CFG_EXTENT_BASE_ADDR         (0xD8008C00 + WMT_MMAP_OFFSET)  /* 1K , 8/16/32 RW */
-#define NF_CTRL_CFG_BASE_ADDR                   (0xD8009000 + WMT_MMAP_OFFSET)  /* 1K , 8/16/32 RW */
-#define NOR_CTRL_CFG_BASE_ADDR                  (0xD8009400 + WMT_MMAP_OFFSET)  /* 1K , 8/16/32 RW */
-#define USB20_DEVICE_CFG_BASE_ADDR              (0xD8009800 + WMT_MMAP_OFFSET)  /* 2K , 8/16/32 RW */
-#define SD0_SDIO_MMC_BASE_ADDR                  (0xD800A000 + WMT_MMAP_OFFSET)  /* 1K , 8/16/32 RW */
-#define SD1_SDIO_MMC_BASE_ADDR                  (0xD800A400 + WMT_MMAP_OFFSET)  /* 1K , 8/16/32 RW */
-#define SD2_SDIO_MMC_BASE_ADDR                  (0xD800A800 + WMT_MMAP_OFFSET)  /* 1K , 8/16/32 RW */
-#define MPCORE_PRIVATE_MEM			(0xD8018000 + WMT_MMAP_OFFSET)
-
-
-#define MS_CTRL_CFG_BASE_ADDR                   (0xD800B000 + WMT_MMAP_OFFSET)  /* 1K , 8/16/32 RW */
-#define XD_CTRL_CFG_BASE_ADDR                   (0xD800B400 + WMT_MMAP_OFFSET)  /* 1K , 8/16/32 RW */
-
-#define CF_CTRL_CFG_BASE_ADDR                   (0xD800C000 + WMT_MMAP_OFFSET)  /* 1K , 8/16/32 RW */
-
-#define SATA_CTRL_CFG_BASE_ADDR                 (0xD800D000 + WMT_MMAP_OFFSET)  /* 2K , 8/16/32 RW */
-
-#define XOR_CTRL_CFG_BASE_ADDR                  (0xD800E000 + WMT_MMAP_OFFSET)  /* 1K , 8/16/32 RW */
-#define LCD_CTRL_CFG_BASE_ADDR                  (0xD800E400 + WMT_MMAP_OFFSET)  /* 1K , 8/16/32 RW */
-
-#define ASYNC_APB_BRIDGE_BASE_ADDR              (0xD802FC00 + WMT_MMAP_OFFSET)  /* 1K , 8/16/32 RW */
-#define LPC_TPM_CFG_BASE_ADDR                   (0xD8030000 + WMT_MMAP_OFFSET)  /* 64K , 8/16/32 RW */
-#define LPC_SUPERIO_CFG_BASE_ADDR               (0xD8040000 + WMT_MMAP_OFFSET)  /* 64K , 8/16/32 RW */
-
-#define VPU_BASE_ADDR                           (0xD8050100 + WMT_MMAP_OFFSET)  /* 256 , 8/16/32 RW */
-#define VPU_BASE2_ADDR                          (0xD8050200 + WMT_MMAP_OFFSET)  /* 256 , 8/16/32 RW */
-#define SPU1_BASE_ADDR                          (0xD8050100 + WMT_MMAP_OFFSET)  /* 256 , 8/16/32 RW */
-#define SPU2_BASE_ADDR                          (0xD8050200 + WMT_MMAP_OFFSET)  /* 256 , 8/16/32 RW */
-#define GOVM_BASE_ADDR                          (0xD8050300 + WMT_MMAP_OFFSET)  /* 256 , 8/16/32 RW */
-#define GE1_BASE_ADDR                           (0xD8050400 + WMT_MMAP_OFFSET)  /* 256 , 8/16/32 RW */
-#define GE2_BASE_ADDR                           (0xD8050500 + WMT_MMAP_OFFSET)  /* 256 , 8/16/32 RW */
-#define GE3_BASE_ADDR                           (0xD8050600 + WMT_MMAP_OFFSET)  /* 256 , 8/16/32 RW */
-#define DISP_BASE_ADDR                          (0xD8050700 + WMT_MMAP_OFFSET)  /* 256 , 8/16/32 RW */
-#define GOVRH_BASE1_ADDR                        (0xD8050800 + WMT_MMAP_OFFSET)  /* 256 , 8/16/32 RW */
-#define GOVRH_BASE2_ADDR                        (0xD8050900 + WMT_MMAP_OFFSET)  /* 256 , 8/16/32 RW */
-#define VID_BASE_ADDR                           (0xD8050A00 + WMT_MMAP_OFFSET)  /* 256 , 8/16/32 RW */
-#define HDTV_CTRL_BASE_ADDR                     (0xD8050B00 + WMT_MMAP_OFFSET)  /* 256 , 8/16/32 RW */
-#define GOVW_BASE_ADDR                          (0xD8050C00 + WMT_MMAP_OFFSET)  /* 256 , 8/16/32 RW */
-#define SCL_BASE_ADDR                           (0xD8050D00 + WMT_MMAP_OFFSET)  /* 256 , 8/16/32 RW */
-#define SCL_BASE2_ADDR                          (0xD8050000 + WMT_MMAP_OFFSET)  /* 256 , 8/16/32 RW */
-#define DISP2_BASE_ADDR                         (0xD8050E00 + WMT_MMAP_OFFSET)  /* 256 , 8/16/32 RW */
-#define VPP_BASE_ADDR                           (0xD8050F00 + WMT_MMAP_OFFSET)  /* 256 , 8/16/32 RW */
-#define LVDS_BASE_ADDR							(0xD8051000 + WMT_MMAP_OFFSET)  /* 256 , 8/16/32 RW */
-#define GOVRH2_BASE1_ADDR                       (0xD8051700 + WMT_MMAP_OFFSET)  /* 256 , 8/16/32 RW */
-#define GOVRH2_BASE2_ADDR                       (0xD8051800 + WMT_MMAP_OFFSET)  /* 256 , 8/16/32 RW */
-#define HDMI_BASE2_ADDR							(0xD8051F00 + WMT_MMAP_OFFSET)  /* 256 , 8/16/32 RW */
-
-#define HDMI_TRANSMITTE_BASE_ADDR               (0xD8060000 + WMT_MMAP_OFFSET)  /* 64K , 8/16/32 RW */
-#define HDMI_CP_BASE_ADDR                       (0xD8070000 + WMT_MMAP_OFFSET)  /* 64K , 8/16/32 RW */
-
-#define USB2_OTG_CFG_BASE_ADDR                  (0xD80E4000 + WMT_MMAP_OFFSET)  /* 16K , 8/16/32 RW */
-
-#define AUDREGF_BASE_ADDR                       (0xD80ED800 + WMT_MMAP_OFFSET)  /* 1K , 8/16/32 RW */
-#define PART_OF_AUDREGF_BASE_ADDR               (0xD80EDC00 + WMT_MMAP_OFFSET)  /* 1K , 8/16/32 RW */
-#define DSS_MBOX_BASE_ADDR                      (0xD80EE000 + WMT_MMAP_OFFSET)  /* 1K , 8/16/32 RW */
-#define DSS_PERM_BASE_ADDR                      (0xD80EE400 + WMT_MMAP_OFFSET)  /* 1K , 8/16/32 RW */
-
-#define MSVD_BASE_ADDR                          (0xD80F0000 + WMT_MMAP_OFFSET)  /* 1K , 8/16/32 RW */
-#define JPEG_ENCODER_BASE_ADDR                  (0xD80F2000 + WMT_MMAP_OFFSET)  /* 4K , 8/16/32 RW */
-#define JPEG_DECODER_BASE_ADDR                  (0xD80F4000 + WMT_MMAP_OFFSET)  /* 4K , 8/16/32 RW */
-#define H264_ENCODER_BASE_ADDR                  (0xD80F6000 + WMT_MMAP_OFFSET)  /* 16K , 8/16/32 RW */
-#define CNM_BIT_BASE_ADDR                       (0xD80F8000 + WMT_MMAP_OFFSET)  /* 4K , 8/16/32 RW */
-
-/**
- *  Internal APB Slaves Memory Address Map
- */
-#define RTC_BASE_ADDR                           (0xD8100000 + WMT_MMAP_OFFSET)  /* 64K  */
-#define GPIO_BASE_ADDR                          (0xD8110000 + WMT_MMAP_OFFSET)  /* 64K  */
-#define SYSTEM_CFG_CTRL_BASE_ADDR               (0xD8120000 + WMT_MMAP_OFFSET)  /* 64K  */
-#define PM_CTRL_BASE_ADDR                       (0xD8130000 + WMT_MMAP_OFFSET)  /* 64K  */
-#define INTERRUPT0_CTRL_BASE_ADDR               (0xD8140000 + WMT_MMAP_OFFSET)  /* 64K  */
-#define INTERRUPT1_CTRL_BASE_ADDR               (0xD8150000 + WMT_MMAP_OFFSET)  /* 64K  */
-
-#define AUDIO_CODEC_BASE_ADDR                   (0xD81F0000 + WMT_MMAP_OFFSET)  /* 64K  */
-#define UART0_BASE_ADDR                         (0xD8200000 + WMT_MMAP_OFFSET)  /* 64K  */
-#define UART1_BASE_ADDR                         (0xD82b0000 + WMT_MMAP_OFFSET)  /* 64K  */
-#define UART2_BASE_ADDR                         (0xD8210000 + WMT_MMAP_OFFSET)  /* 64K  */
-#define UART3_BASE_ADDR                         (0xD82c0000 + WMT_MMAP_OFFSET)  /* 64K  */
-#define PWM0_BASE_ADDR                          (0xD8220000 + WMT_MMAP_OFFSET)  /* 64K  */
-
-#define SPI0_BASE_ADDR                          (0xD8240000 + WMT_MMAP_OFFSET)  /* 64K  */
-#define SPI1_BASE_ADDR                          (0xD8250000 + WMT_MMAP_OFFSET)  /* 64K  */
-#define SPI2_BASE_ADDR                          (0xD82A0000 + WMT_MMAP_OFFSET)  /* 64K  */
-#define KPAD_BASE_ADDR                          (0xD8260000 + WMT_MMAP_OFFSET)  /* 64K  */
-#define CIR_BASE_ADDR                           (0xD8270000 + WMT_MMAP_OFFSET)  /* 64K  */
-#define I2C0_BASE_ADDR                          (0xD8280000 + WMT_MMAP_OFFSET)  /* 64K  */
-#define I2C1_BASE_ADDR                          (0xD8320000 + WMT_MMAP_OFFSET)  /* 64K  */
-#define PCM_BASE_ADDR                           (0xD82D0000 + WMT_MMAP_OFFSET)  /* 64K  */
-#define AC97_BASE_ADDR                          (0xD8290000 + WMT_MMAP_OFFSET)  /* 64K  */
-#define I2C2_BASE_ADDR                          (0xD83A0000 + WMT_MMAP_OFFSET)  /* 64K  */
-#define I2C3_BASE_ADDR                          (0xD83B0000 + WMT_MMAP_OFFSET)  /* 64K  */
-
-#define AHB_ACCESS_MONITOR0_BASE_ADDR           (0xD82E0000 + WMT_MMAP_OFFSET)
-#define AHB_ACCESS_MONITOR1_BASE_ADDR           (0xD82F0000 + WMT_MMAP_OFFSET)
-#define AHB_ACCESS_MONITOR2_BASE_ADDR           (0xD8300000 + WMT_MMAP_OFFSET)
-#define AHB_ACCESS_MONITOR3_BASE_ADDR           (0xD8310000 + WMT_MMAP_OFFSET)
-
-#define ADC_BASE_ADDR                           (0xD8340000 + WMT_MMAP_OFFSET)  /* 64K  */
-#define ROTARY_DETECTOR_BASE_ADDR               (0xD8350000 + WMT_MMAP_OFFSET)  /* 64K  */
-#define SMART_CARD_INTERFACE_BASE_ADDR          (0xD8360000 + WMT_MMAP_OFFSET)  /* 64K  */
-#define POWER_MOS_BASE_ADDR                     (0xD8390000 + WMT_MMAP_OFFSET)  /* 64K  */
-#define I2C4_BASE_ADDR                          (0xD8400000 + WMT_MMAP_OFFSET)  /* 64K  */
-// check
-#define MEMORY_CTRL_CFG_BASE_ADDR               MEMORY_CTRL_V3_CFG_BASE_ADDR
-#define DMA_CTRL_CFG_BASE_ADDR                  DMA_CTRL_V4_CFG_BASE_ADDR
-#define LPC_CTRL_CFG_BASE_ADDR                  LPC_SUPERIO_CFG_BASE_ADDR
-#define HDMI1_BASE_ADDR                         (0xD806C000 + WMT_MMAP_OFFSET)
-#define HDMI2_BASE_ADDR                         (0xD8070000 + WMT_MMAP_OFFSET)
-#define GOVR_BASE_ADDR                          (0xD8050B00 + WMT_MMAP_OFFSET)
-#define INTERRUPT_CTRL_BASE_ADDR                INTERRUPT0_CTRL_BASE_ADDR
-#define SPI_BASE_ADDR                           SPI0_BASE_ADDR
-#define I2C_BASE_ADDR                           I2C0_BASE_ADDR
-#define I2S_BASE_ADDR                           AUDREGF_BASE_ADDR
-
-
-/* WMT Memory Map for Physical Address*/
-#define UART0_PHY_BASE_ADDR                     0xD8200000  /* 64K  */
-#define UART1_PHY_BASE_ADDR                     0xD82b0000  /* 64K  */
-
-#endif	/* __WMT_MMAP_H */
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_pcm.h b/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_pcm.h
deleted file mode 100755
index af3aa899..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_pcm.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*++
-linux/include/asm-arm/arch-wmt/wmt_pcm.h
-
-Copyright (c) 2008  WonderMedia Technologies, Inc.
-
-This program is free software: you can redistribute it and/or modify it under the
-terms of the GNU General Public License as published by the Free Software Foundation,
-either version 2 of the License, or (at your option) any later version.
-
-This program is distributed in the hope that it will be useful, but WITHOUT
-ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-PARTICULAR PURPOSE.  See the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License along with
-this program.  If not, see <http://www.gnu.org/licenses/>.
-
-WonderMedia Technologies, Inc.
-10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
---*/
-
-/* Be sure that virtual mapping is defined right */
-#ifndef __ASM_ARCH_HARDWARE_H
-#error "You must include hardware.h, not vt8500_pcm.h"
-#endif
-
-#ifndef __VT8500_PCM_H
-#define __VT8500_PCM_H
-
-/*
- *   Refer vt8500 pcm register 1.61
- *
- */
-/* #define PCM_BASE_ADDR                                   0xF8160000  // 64K */
-
-/*
- * Address
- */
-#define PCM_CR_ADDR                     (0x0000+PCM_BASE_ADDR)
-#define PCM_SR_ADDR                     (0x0004+PCM_BASE_ADDR)
-/* Reserved 0x0008 ~ 0x000F */
-#define PCM_DFCR_ADDR                   (0x0008+PCM_BASE_ADDR)
-#define PCM_DIVR_ADDR                   (0x000C+PCM_BASE_ADDR)
-/* Reserved 0x0020 ~ 0x007F */
-#define PCM_TFIFO_ADDR                  (0x0010+PCM_BASE_ADDR)
-#define PCM_TFIFO_1_ADDR                (0x0014+PCM_BASE_ADDR)
-
-#define PCM_RFIFO_ADDR                  (0x0030+PCM_BASE_ADDR)
-#define PCM_RFIFO_1_ADDR                (0x0034+PCM_BASE_ADDR)
-
-#define SHARE_PIN_SELEC                   (GPIO_BASE_ADDR+0x200)
-/* Reserved 0x0100 ~ 0xFFFF */
-
-#endif /* __VT8500_I2S_H */
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_pmc.h b/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_pmc.h
deleted file mode 100755
index 4b23b2c2..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_pmc.h
+++ /dev/null
@@ -1,1402 +0,0 @@
-/*++
-linux/include/asm-arm/arch-wmt/wmt_pmc.h
-
-Copyright (c) 2008  WonderMedia Technologies, Inc.
-
-This program is free software: you can redistribute it and/or modify it under the
-terms of the GNU General Public License as published by the Free Software Foundation,
-either version 2 of the License, or (at your option) any later version.
-
-This program is distributed in the hope that it will be useful, but WITHOUT
-ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-PARTICULAR PURPOSE.  See the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License along with
-this program.  If not, see <http://www.gnu.org/licenses/>.
-
-WonderMedia Technologies, Inc.
-10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
---*/
-
-/* Be sure that virtual mapping is defined right */
-#ifndef __ASM_ARCH_HARDWARE_H
-#error "You must include hardware.h, not vt8500_pmc.h"
-#endif
-
-#ifndef __VT8500_PMC_H
-#define __VT8500_PMC_H
-
-/******************************************************************************
- *
- * Define the register access macros.
- *
- * Note: Current policy in standalone program is using register as a pointer.
- *
- ******************************************************************************/
-#include "wmt_mmap.h"
-
-/******************************************************************************
- *
- * VT8500 Power Management Controller Base Address.
- *
- ******************************************************************************/
-#ifdef __PMC_BASE
-#error "__RTC_BASE has already been defined in another file."
-#endif
-#ifdef PM_CTRL_BASE_ADDR               /* From vt8500.mmap.h */
-#define __PMC_BASE      PM_CTRL_BASE_ADDR
-#else
-#define __PMC_BASE      0xD8130000      /* 64K */
-#endif
-
-/******************************************************************************
- *
- * VT8500 Power Management (PM) control registers.
- *
- * Registers Abbreviations:
- *
- * PMCS_REG     	PM (Current) Status Register.
- *
- * PMIR_REG     	PM Idle processor Request Register.
- *
- * PMTC_REG     	PM power-up Time Control Register.
- *
- * PMHV_REG     	PM Hibernation Value Register.
- *
- * PMHC_REG     	PM Hibernation Control Register.
- *
- * PMWS_REG     	PM Wake-up Status register.
- *
- * PMWE_REG     	PM Wake-up event Enable Register.
- *
- * PMWT_REG     	PM Wake-up event Type Register.
- *
- * HSP0_REG     	PM Hibernation Scratch Pad Register 0
- *
- * HSP1_REG     	PM Hibernation Scratch Pad Register 1
- *
- * HSP2_REG     	PM Hibernation Scratch Pad Register 2
- *
- * HSP3_REG     	PM Hibernation Scratch Pad Register 3
- *
- * PMRS_REG     	PM Reset Status Register.
- *
- * PMPB_REG			PM Button Control Register
- *
- * PMSR_REG     	PM Software Reset request Register.
- *
- * PMPATA_REG     	PM PATA I/Os Drive strength Register
- *
- * OSM0_REG     	OS Timer Match Register 0
- *
- * OSM1_REG     	OS Timer Match Register 1
- *
- * OSM2_REG     	OS Timer Match Register 2
- *
- * OSM3_REG     	OS Timer Match Register 3
- *
- * OSCR_REG     	OS Timer Count Register.
- *
- * OSTS_REG     	OS Timer Status Register.
- *
- * OSTW_REG     	OS Timer Watchdog enable Register.
- *
- * OSTI_REG     	OS Timer Interrupt enable Register.
- *
- * OSTC_REG     	OS Timer Control Register.
- *
- * OSTA_REG     	OS Timer Access status Register.
- *
- * PMMISC_REG    	PM miscellaneous (Peripherals) Clock Control Register.
- *
- * PMPMA_REG    	PM PLL_A Multiplier and range values Register.
- *
- * PMPMB_REG    	PM PLL_B Multiplier and range values Register.
- *
- * PMPMC_REG    	PM PLL_C Multiplier and range values Register.
- *
- * PMPMD_REG    	PM PLL_D Multiplier and range values Register.
- *
- * PMCEL_REG	  	PM	Clock Enables Lower Register
- *
- * PMCEU_REG	 	PM	Clock Enables Upper Register
- *
- * PMZD_REG    		PM ZAC2_MA clock's "P" Divisor value Register.
- *
- * PMZH_REG    		PM ZAC2_MA clock's High pulse is the wide pulse Register.
- *
- * PMAD_REG    		PM AHB clock's "A" Divisor value Register.
- *
- * PMMC_REG		 	PM DDR Memory Control Clock Divisor Register
- *
- * PMSF_REG    		PM Serial Flash controller clock's Divisor value Register.
- *
- * PMSFH_REG   		PM Serial flash controller clock's High pulse is the wide
- *             		pulse Register.
- *
- * PMCC_REG    		PM Compact flash clock Control
- *
- * PMCCH_REG   		PM Compact flash controller clock's High pulse is the wide
- *
- * PMSDMMC_REG 		PM SD/MMC clock Control
- *
- * PMSDMMCH_REG   	PM SD/MMC controller clock's High pulse is the wide
- *
- * PMMS_REG    		PM MS&MS-pro clock Control
- *
- * PMMSH_REG   		PM MS&MS-pro controller clock's High pulse is the wide
- *
- * PMNAND_REG  		PM nand clock Control
- *
- * PMNANDH_REG 		PM nand controller clock's High pulse is the wide
- *
- * PMLPC_REG    	PM LPC memory clock Control
- *
- * PMLPCH_REG  		PM LPC memory controller clock's High pulse is the wide
- *
- * PMSPI_REG    	PM SPI clock Control
- *
- * PMSPIH_REG  		PM SPI controller clock's High pulse is the wide
- *
- ******************************************************************************/
-/******************************************************************************
- *
- * Address constant for each register.
- *
- ******************************************************************************/
-#define PMCS_ADDR       (__PMC_BASE + 0x0000)
-#define PMCSH_ADDR      (__PMC_BASE + 0x0004)
-#define PMIR_ADDR       (__PMC_BASE + 0x0008)
-#define PMTC_ADDR       (__PMC_BASE + 0x000C)
-#define PMHV_ADDR       (__PMC_BASE + 0x0010)
-#define PMHC_ADDR       (__PMC_BASE + 0x0012)
-#define PMWS_ADDR       (__PMC_BASE + 0x0014)
-#define PMCS2_ADDR			(__PMC_BASE + 0x0018)
-#define PMWE_ADDR       (__PMC_BASE + 0x001C)
-#define PMWT_ADDR       (__PMC_BASE + 0x0020)
-#define PMWTC_ADDR      (__PMC_BASE + 0x0024)
-
-#define PMCWS_ADDR      (__PMC_BASE + 0x0028)       /* Card_UDC wakeup status */
-#define PMCAD_ADDR      (__PMC_BASE + 0x002C)       /* Card attach debounce control */
-
-#define HSP0_ADDR       (__PMC_BASE + 0x0030)
-#define HSP1_ADDR       (__PMC_BASE + 0x0034)
-#define HSP2_ADDR       (__PMC_BASE + 0x0038)
-#define HSP3_ADDR       (__PMC_BASE + 0x003C)
-#define HSP4_ADDR       (__PMC_BASE + 0x0040)
-#define HSP5_ADDR       (__PMC_BASE + 0x0044)
-#define HSP6_ADDR       (__PMC_BASE + 0x0048)
-#define HSP7_ADDR       (__PMC_BASE + 0x004C)
-#define PMRS_ADDR       (__PMC_BASE + 0x0050)
-#define PMPB_ADDR       (__PMC_BASE + 0x0054)
-#define PMAXILPI_ADDR   (__PMC_BASE + 0x0058)
-#define DCDET_STS_ADDR  (__PMC_BASE + 0x005C)
-#define PMSR_ADDR       (__PMC_BASE + 0x0060)
-#define TIOUT_RST_ADDR  (__PMC_BASE + 0x0064)
-#define BROM_PD_ADDR	  (__PMC_BASE + 0x0068)
-#define CA9MP_RSTC_ADDR (__PMC_BASE + 0x006C)
-#define CA9MP_RSTS_ADDR (__PMC_BASE + 0x0070)
-
-#define PMCIS_ADDR      (__PMC_BASE + 0x0074)      /* Interrupt status from wakeup source */
-#define PMCIE_ADDR      (__PMC_BASE + 0x007C)      /* Interrupt enable from wakeup source */
-#define INT_TYPE0_ADDR    (__PMC_BASE + 0x0080)
-#define INT_TYPE1_ADDR    (__PMC_BASE + 0x0084)
-#define INT_TYPE2_ADDR    (__PMC_BASE + 0x0088)
-
-
-#define RST_VECT_MAP_ADDR (__PMC_BASE + 0x0090)      /* USB OTG operation mode select */
-#define RTCCM_ADDR      	(__PMC_BASE + 0x0094)      /* RTC Clock Exist Monitor */
-#define PMSTM_ADDR      	(__PMC_BASE + 0x0098)      /* Suspend to DRAM */
-#define WK_EVT_TYPE_ADDR	(__PMC_BASE + 0x00A0)      /* WAKE UP EVENT TYPE */
-#define WK_TRG_EN_ADDR		(__PMC_BASE + 0x00B0)
-#define INT_TRG_EN_ADDR		(__PMC_BASE + 0x00B4)
-#define CA9MPC0_ADDR			(__PMC_BASE + 0x00C0)
-#define CA9MPC1_ADDR			(__PMC_BASE + 0x00C4)
-
-#define PWRUP_SRC_ADDR			(__PMC_BASE + 0x00D0)
-
-#define OSM4_ADDR       (__PMC_BASE + 0x00F0)
-#define OSM5_ADDR       (__PMC_BASE + 0x00F4)
-#define OSM6_ADDR       (__PMC_BASE + 0x00F8)
-#define OSM7_ADDR       (__PMC_BASE + 0x00FC)
-#define OSM0_ADDR       (__PMC_BASE + 0x0100)
-#define OSM1_ADDR       (__PMC_BASE + 0x0104)
-#define OSM2_ADDR       (__PMC_BASE + 0x0108)
-#define OSM3_ADDR       (__PMC_BASE + 0x010C)
-#define OSCR_ADDR       (__PMC_BASE + 0x0110)
-#define OSTS_ADDR       (__PMC_BASE + 0x0114)
-#define OSTW_ADDR       (__PMC_BASE + 0x0118)
-#define OSTI_ADDR       (__PMC_BASE + 0x011C)
-#define OSTC_ADDR       (__PMC_BASE + 0x0120)
-#define OSTA_ADDR       (__PMC_BASE + 0x0124)
-
-#define PMMISC_ADDR     (__PMC_BASE + 0x01FC)
-
-#define PMPMA_ADDR      (__PMC_BASE + 0x0200)
-#define PMPMB_ADDR      (__PMC_BASE + 0x0204)
-#define PMPMC_ADDR      (__PMC_BASE + 0x0208)
-#define PMPMD_ADDR      (__PMC_BASE + 0x020C)
-#define PMPME_ADDR      (__PMC_BASE + 0x0210)
-#define PMPMF_ADDR      (__PMC_BASE + 0x0214)     /* PLL Audio(I2S) Control Register */
-#define PMPMG_ADDR      (__PMC_BASE + 0x0218)
-
-#define PMCEL_ADDR      (__PMC_BASE + 0x0250)
-#define PMCEU_ADDR      (__PMC_BASE + 0x0254)
-#define PMCE2_ADDR      (__PMC_BASE + 0x0258)
-#define PMCE3_ADDR      (__PMC_BASE + 0x025C)
-#define DVFSSTS_ADDR    (__PMC_BASE + 0x0260)
-#define DVFSE0_ADDR     (__PMC_BASE + 0x0280)
-#define DVFSE1_ADDR     (__PMC_BASE + 0x0284)
-#define DVFSE2_ADDR     (__PMC_BASE + 0x0288)
-#define DVFSE3_ADDR     (__PMC_BASE + 0x028C)
-#define DVFSE4_ADDR     (__PMC_BASE + 0x0290)
-#define DVFSE5_ADDR     (__PMC_BASE + 0x0294)
-#define DVFSE6_ADDR     (__PMC_BASE + 0x0298)
-#define DVFSE7_ADDR     (__PMC_BASE + 0x029C)
-#define DVFSE8_ADDR     (__PMC_BASE + 0x02A0)
-#define DVFSE9_ADDR     (__PMC_BASE + 0x02A4)
-#define DVFSE10_ADDR    (__PMC_BASE + 0x02A8)
-#define DVFSE11_ADDR    (__PMC_BASE + 0x02AC)
-#define DVFSE12_ADDR    (__PMC_BASE + 0x02B0)
-#define DVFSE13_ADDR    (__PMC_BASE + 0x02B4)
-#define DVFSE14_ADDR    (__PMC_BASE + 0x02B8)
-#define DVFSE15_ADDR    (__PMC_BASE + 0x02BC)
-
-#define PMARM_ADDR      (__PMC_BASE + 0x0300)			/* ARM */
-#define PMARMH_ADDR     (__PMC_BASE + 0x0301)
-#define PMAHB_ADDR      (__PMC_BASE + 0x0304)			/* AHB */
-#define PML2C_ADDR      (__PMC_BASE + 0x030C)			/* L2C */
-#define PML2CH_ADDR     (__PMC_BASE + 0x030D)
-#define PMMC_ADDR       (__PMC_BASE + 0x0310)
-
-#define PMSF_ADDR       (__PMC_BASE + 0x0314)     /* SF */
-#define PMSFH_ADDR      (__PMC_BASE + 0x0315)
-#define PMNAND_ADDR     (__PMC_BASE + 0x0318)     /* NAND */
-#define PMNANDH_ADDR    (__PMC_BASE + 0x0319)
-#define PMNOR_ADDR 	    (__PMC_BASE + 0x031C)     /* NOR */
-#define PMNORH_ADDR	    (__PMC_BASE + 0x031D)
-#define PMAPB0_ADDR	    (__PMC_BASE + 0x0320)     /* APB 0 */
-#define PMAPB0H_ADDR 	  (__PMC_BASE + 0x0321)
-#define PMPCM0_ADDR	    (__PMC_BASE + 0x0324)     /* PCM 0 */
-#define PMPCM1_ADDR	    (__PMC_BASE + 0x0328)     /* PCM 1 */
-#define PMSDMMC_ADDR    (__PMC_BASE + 0x0330)     /* SD/MMC 0 */
-#define PMSDMMCH_ADDR   (__PMC_BASE + 0x0331)
-#define PMSDMMC1_ADDR   (__PMC_BASE + 0x0334)    	/* SD/MMC 1 */
-#define PMSDMMC1H_ADDR  (__PMC_BASE + 0x0335)
-#define PMSDMMC2_ADDR   (__PMC_BASE + 0x0338)    	/* SD/MMC 2 */
-#define PMSDMMC2H_ADDR  (__PMC_BASE + 0x0339)
-#define PMSDMMC3_ADDR   (__PMC_BASE + 0x033C)    	/* SD/MMC 3 */
-#define PMSDMMC3H_ADDR  (__PMC_BASE + 0x033D)                   
-#define PMSPI_ADDR      (__PMC_BASE + 0x0340)     /* SPI 0 */
-#define PMSPIH_ADDR	    (__PMC_BASE + 0x0341)
-#define PMSPI1_ADDR     (__PMC_BASE + 0x0344)     /* SPI 1 */
-#define PMSPI1H_ADDR	  (__PMC_BASE + 0x0345)
-#define PMSE_ADDR  		  (__PMC_BASE + 0x0348)     /* SE */
-#define PMSEH_ADDR		  (__PMC_BASE + 0x0349)
-#define PMPWM_ADDR      (__PMC_BASE + 0x0350)     /* PWM */
-#define PMPWMH_ADDR	    (__PMC_BASE + 0x0351)
-#define PMPAXI_ADDR     (__PMC_BASE + 0x0354)     /* PAXI */
-#define PMPAXIH_ADDR	  (__PMC_BASE + 0x0355)
-#define PMWMTNA_ADDR	  (__PMC_BASE + 0x0358)     /* NA 01 */
-#define PMWMTNAH_ADDR	  (__PMC_BASE + 0x0359)
-#define PMNA12_ADDR	    (__PMC_BASE + 0x035C)     /* NA 12 */
-#define PMNA12H_ADDR	  (__PMC_BASE + 0x035D)
-#define PMCNMNA_ADDR    (__PMC_BASE + 0x0360)     /* CNM NA */
-#define PMCNMNAH_ADDR   (__PMC_BASE + 0x0361)
-#define PMWMTVDU_ADDR	  (__PMC_BASE + 0x0368)     /* WMT VDU */
-#define PMWMTVDUH_ADDR	(__PMC_BASE + 0x0369)
-#define PMHDMITV_ADDR	  (__PMC_BASE + 0x036C)     /* HDMITV */
-#define PMHDMITVH_ADDR  (__PMC_BASE + 0x036D)
-#define PMDVO_ADDR  	  (__PMC_BASE + 0x0370)     /* DVO */
-#define PMDVOH_ADDR     (__PMC_BASE + 0x0371)
-#define PMAUDIO_ADDR		(__PMC_BASE + 0x0374) 		/* AUDIO/I2S */
-#define PMAUDIOH_ADDR	  (__PMC_BASE + 0x0375)
-#define PMCSI0_ADDR			(__PMC_BASE + 0x0380) 		/* CSI0 */
-#define PMCSI0H_ADDR	  (__PMC_BASE + 0x0381)
-#define PMCSI1_ADDR			(__PMC_BASE + 0x0384) 		/* CSI1 */
-#define PMCSI1H_ADDR	  (__PMC_BASE + 0x0385)
-#define PMMALI_ADDR	 		(__PMC_BASE + 0x0388)     /* MALI */
-#define PMMALIH_ADDR	  (__PMC_BASE + 0x0389)
-#define PMCNMVDU_ADDR		(__PMC_BASE + 0x038C)     /* CNM VDU */
-#define PMCNMVDUH_ADDR  (__PMC_BASE + 0x038D)
-#define PMHDI2C_ADDR    (__PMC_BASE + 0x0390)     /* HDMII2C */
-#define PMHDI2CH_ADDR	  (__PMC_BASE + 0x0391)
-#define PMADC_ADDR		  (__PMC_BASE + 0x0394)     /* ADC */
-#define PMADCH_ADDR		  (__PMC_BASE + 0x0395)
-#define PMI2C4_ADDR	    (__PMC_BASE + 0x039C)     /* I2C 4 */
-#define PMI2C4H_ADDR	  (__PMC_BASE + 0x039D)
-#define PMI2C0_ADDR	    (__PMC_BASE + 0x03A0)     /* I2C 0 */
-#define PMI2C0H_ADDR	  (__PMC_BASE + 0x03A1)
-#define PMI2C1_ADDR	    (__PMC_BASE + 0x03A4)     /* I2C 1 */
-#define PMI2C1H_ADDR	  (__PMC_BASE + 0x03A5)
-#define PMI2C2_ADDR	    (__PMC_BASE + 0x03A8)     /* I2C 2 */
-#define PMI2C2H_ADDR	  (__PMC_BASE + 0x03A9)
-#define PMI2C3_ADDR	    (__PMC_BASE + 0x03AC)     /* I2C 3 */
-#define PMI2C3H_ADDR	  (__PMC_BASE + 0x03AD)
-#define PML2CAXI_ADDR	  (__PMC_BASE + 0x03B0)     /* L2C AXI*/
-#define PML2CAXIH_ADDR	(__PMC_BASE + 0x03B1)
-#define PMATCLK_ADDR	  (__PMC_BASE + 0x03B4)     /* AT CLK*/
-#define PMATCLKH_ADDR		(__PMC_BASE + 0x03B5)
-#define PMPERI_ADDR			(__PMC_BASE + 0x03B8)     /* PERI CLK*/
-#define PMPERIH_ADDR		(__PMC_BASE + 0x03B9)
-#define PMTRACE_ADDR		(__PMC_BASE + 0x03BC)     /* TRACE CLK*/
-#define PMTRACEH_ADDR		(__PMC_BASE + 0x03BD)
-#define PMDBGAPB_ADDR		(__PMC_BASE + 0x03D0)     /* DBG APB*/
-#define PMDBGAPBH_ADDR 	(__PMC_BASE + 0x03D1)
-#define PM24MHZ_ADDR  	(__PMC_BASE + 0x03E4)     /* 24MHZ */
-#define PM24MHZH_ADDR   (__PMC_BASE + 0x03E5)
-#define PML2CTAG_ADDR	  (__PMC_BASE + 0x03F0)     /* L2C TAG */
-#define PML2CTAGH_ADDR  (__PMC_BASE + 0x03F1)
-#define PML2CDATA_ADDR	(__PMC_BASE + 0x03F4)     /* L2C DATA */
-#define PML2CDATAH_ADDR (__PMC_BASE + 0x03F5)
-#define PMCA9PMWDOD_ADDR 	(__PMC_BASE + 0x0480)		/* WATCH DOG RESET */
-#define PMSDPS_ADDR			 	(__PMC_BASE + 0x0500)		/* SD 0~2 POWER SWITCH */
-#define PMMALIGPPWR_ADDR	(__PMC_BASE + 0x0600)		/* MALI GP Power Shut Off Control and Status Register */
-#define PMWMTVDUPWR_ADDR	(__PMC_BASE + 0x0604)		/* WMT VDU Power Shut Off Control and Status Register */
-#define PMCA9C0PWR_ADDR 	(__PMC_BASE + 0x0608)	  /* CA9 CORE 0 Power Shut Off Control and Status Register */
-#define PML2CRAMPWR_ADDR 	(__PMC_BASE + 0x060C)		/* L2CRAM Power Shut Off Control and Status Register */
-#define PMNEON0PWR_ADDR 	(__PMC_BASE + 0x0610)	  /* NEON 0 Power Shut Off Control and Status Register */
-#define PMCA9C1PWR_ADDR 	(__PMC_BASE + 0x0614)	  /* CA9 CORE 1 Power Shut Off Control and Status Register */
-#define PMNEON1PWR_ADDR 	(__PMC_BASE + 0x0618)	  /* NEON 1 Power Shut Off Control and Status Register */
-#define PMC_MPWR_ADDR   	(__PMC_BASE + 0x061C)		  /* C&M Power Shut Off Control and Status Register */
-#define PMMALIL2CPWR_ADDR	(__PMC_BASE + 0x0620)		/* MALI L2C Power Shut Off Control and Status Register */
-#define PMMALIPP0PWR_ADDR	(__PMC_BASE + 0x0624)		/* MALI PP0 Power Shut Off Control and Status Register */
-#define PMMALIPP1PWR_ADDR	(__PMC_BASE + 0x0628)		/* MALI PP1 Power Shut Off Control and Status Register */
-#define AXI2AHB_ADDR     (__PMC_BASE + 0x0650)		/* AXI TO AHB POWER control */
-#define EBMCTS_ADDR     (__PMC_BASE + 0x0700)			/* EBM control and status */
-#define EBMINTCTS_ADDR  (__PMC_BASE + 0x0704)     /* EBM interrupt control and status */
-
-/******************************************************************************
- *
- * Register pointer.
- *
- ******************************************************************************/
-#define PMCS_REG			(REG32_PTR(PMCS_ADDR))/*0x00*/
-#define PMCSH_REG			(REG32_PTR(PMCSH_ADDR))/*0x04*/
-#define PMIR_REG			(REG8_PTR(PMIR_ADDR))/*0x08*/
-#define PMTC_REG			(REG8_PTR(PMTC_ADDR))/*0x0C*/
-#define PMHV_REG			(REG16_PTR(PMHV_ADDR))/*0x10*/
-#define PMHC_REG			(REG16_PTR(PMHC_ADDR))/*0x12*/
-#define PMWS_REG			(REG32_PTR(PMWS_ADDR))/*0x14*/
-#define PMCS2_REG			(REG32_PTR(PMCS2_ADDR))/*0x18*/
-#define PMWE_REG			(REG32_PTR(PMWE_ADDR))/*0x1C*/
-#define PMWT_REG			(REG32_PTR(PMWT_ADDR))/*0x20*/
-#define PMWTC_REG			(REG32_PTR(PMWTC_ADDR))/*0x24*/
-
-#define PMCWS_REG			(REG32_PTR(PMCWS_ADDR))/*0x28*/
-#define PMCAD_REG			(REG32_PTR(PMCAD_ADDR))/*0x2C*/
-
-#define HSP0_REG			(REG32_PTR(HSP0_ADDR))/*0x30*/
-#define HSP1_REG			(REG32_PTR(HSP1_ADDR))/*0x34*/
-#define HSP2_REG			(REG32_PTR(HSP2_ADDR))/*0x38*/
-#define HSP3_REG			(REG32_PTR(HSP3_ADDR))/*0x3c*/
-#define PMRS_REG			(REG32_PTR(PMRS_ADDR))/*0x50*/
-#define PMPB_REG			(REG32_PTR(PMPB_ADDR))/*0x54*/
-#define DCDET_STS_REG	(REG32_PTR(DCDET_STS_ADDR))/*0x5c*/
-#define PMSR_REG			(REG32_PTR(PMSR_ADDR))/*0x60*/
-#define TIOUT_RST_REG		(REG32_PTR(TIOUT_RST_ADDR))/*0x64*/
-#define BROM_PD_REG			(REG32_PTR(BROM_PD_ADDR))/*0x68*/
-#define CA9MP_RSTC_REG	(REG32_PTR(CA9MP_RSTC_ADDR))/*0x6C*/
-#define CA9MP_RSTS_REG	(REG32_PTR(CA9MP_RSTS_ADDR))/*0x70*/
-
-#define PMCIS_REG				(REG32_PTR(PMCIS_ADDR))/*0x74*/
-#define PMCIE_REG				(REG32_PTR(PMCIE_ADDR))/*0x7C*/
-#define INT_TYPE0_REG		(REG32_VAL(INT_TYPE0_ADDR))/*0x80*/
-#define INT_TYPE1_REG		(REG32_VAL(INT_TYPE1_ADDR))/*0x84*/
-#define INT_TYPE2_REG		(REG32_VAL(INT_TYPE2_ADDR))/*0x88*/
-
-#define RST_VECT_MAP_REG	(REG32_PTR(RST_VECT_MAP_ADDR))/*0x90*/
-#define RTCCM_REG			(REG32_PTR(RTCCM_ADDR))/*0x94*/
-#define PMSTM_REG			(REG32_PTR(PMSTM_ADDR))/*0x98*/
-
-#define WK_EVT_TYPE_REG	(REG32_PTR(WK_EVT_TYPE_ADDR))/*0xA0*/
-#define WK_TRG_EN_REG		(REG32_PTR(WK_TRG_EN_ADDR))/*0xB0*/
-#define INT_TRG_EN_REG	(REG32_PTR(INT_TRG_EN_ADDR))/*0xB4*/
-#define CA9MPC0_REG			(REG32_PTR(CA9MPC0_ADDR))/*0xC0*/
-#define CA9MPC1_REG			(REG32_PTR(CA9MPC1_ADDR))/*0xC4*/
-#define PWRUP_SRC_REG		(REG32_PTR(PWRUP_SRC_ADDR))/*0xD0*/
-
-
-#define OSM4_REG			(REG32_PTR(OSM4_ADDR))/*0xF0*/
-#define OSM5_REG			(REG32_PTR(OSM5_ADDR))
-#define OSM6_REG			(REG32_PTR(OSM6_ADDR))
-#define OSM7_REG			(REG32_PTR(OSM7_ADDR))
-#define OSM0_REG			(REG32_PTR(OSM0_ADDR))/*0x100*/
-#define OSM1_REG			(REG32_PTR(OSM1_ADDR))
-#define OSM2_REG			(REG32_PTR(OSM2_ADDR))
-#define OSM3_REG			(REG32_PTR(OSM3_ADDR))
-#define OSCR_REG			(REG32_PTR(OSCR_ADDR))
-#define OSTS_REG			(REG32_PTR(OSTS_ADDR))
-#define OSTW_REG			(REG32_PTR(OSTW_ADDR))
-#define OSTI_REG			(REG32_PTR(OSTI_ADDR))
-#define OSTC_REG			(REG32_PTR(OSTC_ADDR))
-#define OSTA_REG			(REG32_PTR(OSTA_ADDR))/*0x124*/
-
-#define PMMISC_REG		(REG32_PTR(PMMISC_ADDR))/*0x1FC*/
-#define PMPMA_REG			(REG32_PTR(PMPMA_ADDR))/*0x200*/
-#define PMPMB_REG			(REG32_PTR(PMPMB_ADDR))
-#define PMPMC_REG			(REG32_PTR(PMPMC_ADDR))
-#define PMPMD_REG			(REG32_PTR(PMPMD_ADDR))
-#define PMPME_REG			(REG32_PTR(PMPME_ADDR))
-#define PMPMF_REG 		(REG32_PTR(PMPMF_ADDR))
-#define PMPMG_REG 		(REG32_PTR(PMPMG_ADDR))
-
-#define PMCEL_REG			(REG32_PTR(PMCEL_ADDR))/*0x250*/
-#define PMCEU_REG			(REG32_PTR(PMCEU_ADDR))
-#define PMCE2_REG			(REG32_PTR(PMCE2_ADDR))
-#define PMCE3_REG			(REG32_PTR(PMCE3_ADDR))
-#define DVFSSTS_REG   (REG32_PTR(DVFSSTS_ADDR))/*0x260*/
-#define DVFSE0_REG    (REG32_PTR(DVFSE0_ADDR))    
-#define DVFSE1_REG    (REG32_PTR(DVFSE1_ADDR))    
-#define DVFSE2_REG    (REG32_PTR(DVFSE2_ADDR))    
-#define DVFSE3_REG    (REG32_PTR(DVFSE3_ADDR))    
-#define DVFSE4_REG    (REG32_PTR(DVFSE4_ADDR))    
-#define DVFSE5_REG    (REG32_PTR(DVFSE5_ADDR))    
-#define DVFSE6_REG    (REG32_PTR(DVFSE6_ADDR))    
-#define DVFSE7_REG    (REG32_PTR(DVFSE7_ADDR))    
-#define DVFSE8_REG    (REG32_PTR(DVFSE8_ADDR))    
-#define DVFSE9_REG    (REG32_PTR(DVFSE9_ADDR))    
-#define DVFSE10_REG   (REG32_PTR(DVFSE10_ADDR))    
-#define DVFSE11_REG   (REG32_PTR(DVFSE11_ADDR))    
-#define DVFSE12_REG   (REG32_PTR(DVFSE12_ADDR))    
-#define DVFSE13_REG   (REG32_PTR(DVFSE13_ADDR))    
-#define DVFSE14_REG   (REG32_PTR(DVFSE14_ADDR))    
-#define DVFSE15_REG   (REG32_PTR(DVFSE15_ADDR))
-    
-#define PMARM_REG				(REG8_PTR(PMARM_ADDR))
-#define PMARMH_REG			(REG8_PTR(PMARMH_ADDR))
-#define PMAHB_REG				(REG8_PTR(PMAHB_ADDR))
-#define PMAHBH_REG			(REG8_PTR(PMAHBH_ADDR))
-#define PMMC_REG				(REG8_PTR(PMMC_ADDR))
-#define PML2C_REG				(REG8_PTR(PML2C_ADDR))
-#define PML2CH_REG			(REG8_PTR(PML2CH_ADDR))
-
-#define PMSF_REG				(REG8_PTR(PMSF_ADDR))
-#define PMSFH_REG				(REG8_PTR(PMSFH_ADDR))
-#define PMAPB1_REG			(REG8_PTR(PMAPB1_ADDR))
-#define PMAPB1H_REG			(REG8_PTR(PMAPB1H_ADDR))
-#define PMAPB0_REG			(REG8_PTR(PMAPB0_ADDR))
-#define PMAPB0H_REG			(REG8_PTR(PMAPB0H_ADDR))
-#define PMPCM0_REG			(REG8_PTR(PMPCM0_ADDR))
-#define PMPCM1_REG			(REG8_PTR(PMPCM1_ADDR))
-#define PMSDMMC_REG			(REG8_PTR(PMSDMMC_ADDR))
-#define PMSDMMCH_REG		(REG8_PTR(PMSDMMCH_ADDR))
-#define PMMSP_REG				(REG8_PTR(PMMSP_ADDR))
-#define PMMSPH_REG			(REG8_PTR(PMMSPH_ADDR))
-#define PMNAND_REG			(REG8_PTR(PMNAND_ADDR))
-#define PMNANDH_REG			(REG8_PTR(PMNANDH_ADDR))
-#define PMXD_REG			(REG8_PTR(PMXD_ADDR))
-#define PMXDH_REG			(REG8_PTR(PMXDH_ADDR))
-#define PMLCD_REG			(REG8_PTR(PMXD_ADDR))
-#define PMLCDH_REG			(REG8_PTR(PMXDH_ADDR))
-#define PMSPI_REG			(REG8_PTR(PMSPI_ADDR))
-#define PMSPIH_REG			(REG8_PTR(PMSPIH_ADDR))
-#define PMSPI1_REG			(REG8_PTR(PMSPI1_ADDR))
-#define PMSPI1H_REG			(REG8_PTR(PMSPI1H_ADDR))
-#define PMSE_REG			(REG8_PTR(PMSE_ADDR))
-#define PMSEH_REG			(REG8_PTR(PMSEH_ADDR))
-#define PMSDMMC1_REG		(REG8_PTR(PMSDMMC1_ADDR))
-#define PMSDMMC1H_REG		(REG8_PTR(PMSDMMC1H_ADDR))
-#define PMSDMMC2_REG		(REG8_PTR(PMSDMMC2_ADDR))
-#define PMSDMMC2H_REG		(REG8_PTR(PMSDMMC2H_ADDR))
-#define PMPWM_REG			(REG8_PTR(PMPWM_ADDR))
-#define PMPWMH_REG			(REG8_PTR(PMPWMH_ADDR))
-#define PMPAXI_REG			(REG8_PTR(PMPAXI_ADDR))
-#define PMPAXIH_REG			(REG8_PTR(PMPAXIH_ADDR))
-#define PMWMTNA_REG			(REG8_PTR(PMWMTNA_ADDR))
-#define PMWMTNAH_REG		(REG8_PTR(PMWMTNAH_ADDR))
-
-#define PMNA12_REG			(REG8_PTR(PMNA12_ADDR))
-#define PMNA12H_REG			(REG8_PTR(PMNA12H_ADDR))
-#define PMCNMNA_REG			(REG8_PTR(PMCNMNA_ADDR))
-#define PMCNMNAH_REG		(REG8_PTR(PMCNMNAH_ADDR))
-#define PMWMTVDU_REG		(REG8_PTR(PMWMTVDU_ADDR))
-#define PMWMTVDUH_REG		(REG8_PTR(PMWMTVDUH_ADDR))
-#define PMHDMITV_REG		(REG8_PTR(PMHDMITV_ADDR))
-#define PMHDMITVH_REG		(REG8_PTR(PMHDMITVH_ADDR))
-#define PMDVO_REG				(REG8_PTR(PMDVO_ADDR))
-#define PMDVOH_REG			(REG8_PTR(PMDVOH_ADDR))
-#define PMAUDIO_REG			(REG8_PTR(PMAUDIO_ADDR))
-#define PMAUDIOH_REG		(REG8_PTR(PMAUDIOH_ADDR))
-#define PMCSI0_REG			(REG8_PTR(PMCSI0_ADDR))
-#define PMCSI0H_REG			(REG8_PTR(PMCSI0H_ADDR))
-#define PMCSI1_REG			(REG8_PTR(PMCSI1_ADDR))
-#define PMCSI1H_REG			(REG8_PTR(PMCSI1H_ADDR))
-
-#define PMMALI_REG			(REG8_PTR(PMMALI_ADDR))
-#define PMMALIH_REG			(REG8_PTR(PMMALIH_ADDR))
-#define PMCNMVDU_REG		(REG8_PTR(PMCNMVDU_ADDR))
-#define PMCNMVDUH_REG		(REG8_PTR(PMCNMVDUH_ADDR))
-#define PMHDI2C_REG			(REG8_PTR(PMHDI2C_ADDR))
-#define PMHDI2CH_REG		(REG8_PTR(PMHDI2CH_ADDR))
-#define PMADC_REG				(REG8_PTR(PMADC_ADDR))
-#define PMADCH_REG			(REG8_PTR(PMADCH_ADDR))
-
-#define PMI2C4_REG			(REG8_PTR(PMI2C4_ADDR))
-#define PMI2C4H_REG			(REG8_PTR(PMI2C4H_ADDR))
-#define PMI2C0_REG			(REG8_PTR(PMI2C0_ADDR))
-#define PMI2C0H_REG			(REG8_PTR(PMI2C0H_ADDR))
-#define PMI2C1_REG			(REG8_PTR(PMI2C1_ADDR))
-#define PMI2C1H_REG			(REG8_PTR(PMI2C1H_ADDR))
-#define PMI2C2_REG			(REG8_PTR(PMI2C2_ADDR))
-#define PMI2C2H_REG			(REG8_PTR(PMI2C2H_ADDR))
-#define PMI2C3_REG			(REG8_PTR(PMI2C3_ADDR))
-#define PMI2C3H_REG			(REG8_PTR(PMI2C3H_ADDR))
-
-#define PML2CAXI_REG	(REG8_PTR(PML2CAXI_ADDR))
-#define PML2CAXIH_REG	(REG8_PTR(PML2CAXIH_ADDR))
-#define PMPERI_REG		(REG8_PTR(PMPERI_ADDR))
-#define PMPERIH_REG		(REG8_PTR(PMPERIH_ADDR))
-#define PMTRACE_REG		(REG8_PTR(PMTRACE_ADDR))
-#define PMTRACEH_REG	(REG8_PTR(PMTRACEH_ADDR))
-#define PMDBGAPB_REG	(REG8_PTR(PMDBGAPB_ADDR))
-#define PMDBGAPBH_REG	(REG8_PTR(PMDBGAPBH_ADDR))
-#define PML2CTAG_REG	(REG8_PTR(PML2CTAG_ADDR))
-#define PML2CTAGH_REG	(REG8_PTR(PML2CTAGH_ADDR))
-#define PML2CDATA_REG	(REG8_PTR(PML2CDATA_ADDR))
-#define PML2CDATAH_REG	(REG8_PTR(PML2CDATAH_ADDR))
-
-#define PMCA9PMWDOD_REG 	(REG8_PTR(PMCA9PMWDOD_ADDR))		/* WATCH DOG RESET */
-#define PMSDPS_REG			 	(REG8_PTR(PMSDPS_ADDR))					/* SD 0~2 POWER SWITCH */
-#define PMMALIGPPWR_REG		(REG8_PTR(PMMALIGPPWR_ADDR))		/* MALI GP Power Shut Off Control and Status Register */
-#define PMWMTVDUPWR_REG		(REG8_PTR(PMWMTVDUPWR_ADDR))		/* WMT VDU Power Shut Off Control and Status Register */
-#define PMCA9C0PWR_REG	 	(REG8_PTR(PMCA9C0PWR_ADDR))	  	/* CA9 CORE 0 Power Shut Off Control and Status Register */
-#define PML2CRAMPWR_REG 	(REG8_PTR(PML2CRAMPWR_ADDR))		/* L2CRAM Power Shut Off Control and Status Register */
-#define PMNEON0PWR_REG 		(REG8_PTR(PMNEON0PWR_ADDR))		  /* NEON 0 Power Shut Off Control and Status Register */
-#define PMCA9C1PWR_REG 		(REG8_PTR(PMCA9C1PWR_ADDR))		  /* CA9 CORE 1 Power Shut Off Control and Status Register */
-#define PMNEON1PWR_REG	 	(REG8_PTR(PMNEON1PWR_ADDR))		  /* NEON 1 Power Shut Off Control and Status Register */
-#define PMC_MPWR_REG	   	(REG8_PTR(PMC_MPWR_ADDR))			  /* C&M Power Shut Off Control and Status Register */
-#define PMMALIL2CPWR_REG	(REG8_PTR(PMMALIL2CPWR_ADDR))		/* MALI L2C Power Shut Off Control and Status Register */
-#define PMMALIPP0PWR_REG	(REG8_PTR(PMMALIPP0PWR_ADDR))		/* MALI PP0 Power Shut Off Control and Status Register */
-#define PMMALIPP1PWR_REG	(REG8_PTR(PMMALIPP1PWR_ADDR))		/* MALI PP1 Power Shut Off Control and Status Register */
-#define AXI2AHB_REG     	(REG8_PTR(AXI2AHB_ADDR))				/* AXI TO AHB POWER control */
-
-/******************************************************************************
- *
- * Register value.
- *
- ******************************************************************************/
-#define PMCS_VAL			(REG32_VAL(PMCS_ADDR))/*0x00*/
-#define PMCSH_VAL			(REG32_VAL(PMCSH_ADDR))/*0x04*/
-#define PMIR_VAL			(REG8_VAL(PMIR_ADDR))/*0x08*/
-#define PMTC_VAL			(REG8_VAL(PMTC_ADDR))/*0x0C*/
-#define PMHV_VAL			(REG16_VAL(PMHV_ADDR))/*0x10*/
-#define PMHC_VAL			(REG16_VAL(PMHC_ADDR))/*0x12*/
-#define PMWS_VAL			(REG32_VAL(PMWS_ADDR))/*0x14*/
-#define PMCS2_VAL			(REG32_VAL(PMCS2_ADDR))/*0x18*/
-#define PMWE_VAL			(REG32_VAL(PMWE_ADDR))/*0x1C*/
-#define PMWT_VAL			(REG32_VAL(PMWT_ADDR))/*0x20*/
-#define PMWTC_VAL			(REG32_VAL(PMWTC_ADDR))/*0x24*/
-
-#define PMCWS_VAL			(REG32_VAL(PMCWS_ADDR))/*0x28*/
-#define PMCAD_VAL			(REG32_VAL(PMCAD_ADDR))/*0x2C*/
-
-#define HSP0_VAL			(REG32_VAL(HSP0_ADDR))/*0x30*/
-#define HSP1_VAL			(REG32_VAL(HSP1_ADDR))/*0x34*/
-#define HSP2_VAL			(REG32_VAL(HSP2_ADDR))/*0x38*/
-#define HSP3_VAL			(REG32_VAL(HSP3_ADDR))/*0x3c*/
-#define HSP4_VAL			(REG32_VAL(HSP4_ADDR))/*0x40*/
-#define HSP5_VAL			(REG32_VAL(HSP5_ADDR))/*0x44*/
-#define HSP6_VAL			(REG32_VAL(HSP6_ADDR))/*0x48*/
-#define HSP7_VAL			(REG32_VAL(HSP7_ADDR))/*0x4c*/
-#define PMRS_VAL			(REG32_VAL(PMRS_ADDR))/*0x50*/
-#define PMPB_VAL			(REG32_VAL(PMPB_ADDR))/*0x54*/
-#define DCDET_STS_VAL		(REG32_VAL(DCDET_STS_ADDR))/*0x5c*/
-#define PMSR_VAL			(REG32_VAL(PMSR_ADDR))/*0x60*/
-#define TIOUT_RST_VAL		(REG32_VAL(TIOUT_RST_ADDR))/*0x64*/
-#define BROM_PD_VAL			(REG32_VAL(BROM_PD_ADDR))/*0x68*/
-#define CA9MP_RSTC_VAL		(REG32_VAL(CA9MP_RSTC_ADDR))/*0x6C*/
-#define CA9MP_RSTS_VAL		(REG32_VAL(CA9MP_RSTS_ADDR))/*0x70*/
-
-#define PMCIS_VAL			(REG32_VAL(PMCIS_ADDR))/*0x74*/
-#define PMCIE_VAL			(REG32_VAL(PMCIE_ADDR))/*0x7C*/
-#define INT_TYPE0_VAL		(REG32_VAL(INT_TYPE0_ADDR))/*0x80*/
-#define INT_TYPE1_VAL		(REG32_VAL(INT_TYPE1_ADDR))/*0x84*/
-#define INT_TYPE2_VAL		(REG32_VAL(INT_TYPE2_ADDR))/*0x88*/
-
-#define RST_VECT_MAP_VAL	(REG32_VAL(RST_VECT_MAP_ADDR))/*0x90*/
-#define RTCCM_VAL			(REG32_VAL(RTCCM_ADDR))/*0x94*/
-#define PMSTM_VAL			(REG32_VAL(PMSTM_ADDR))/*0x98*/
-
-#define WK_EVT_TYPE_VAL		(REG32_VAL(WK_EVT_TYPE_ADDR))/*0xA0*/
-#define WK_TRG_EN_VAL		(REG32_VAL(WK_TRG_EN_ADDR))/*0xB0*/
-#define INT_TRG_EN_VAL		(REG32_VAL(INT_TRG_EN_ADDR))/*0xB4*/
-#define CA9MPC0_VAL			(REG32_VAL(CA9MPC0_ADDR))/*0xC0*/
-#define CA9MPC1_VAL			(REG32_VAL(CA9MPC1_ADDR))/*0xC4*/
-#define PWRUP_SRC_VAL		(REG32_VAL(PWRUP_SRC_ADDR))/*0xD0*/
-
-#define OSM4_VAL			(REG32_VAL(OSM4_ADDR))
-#define OSM5_VAL			(REG32_VAL(OSM5_ADDR))
-#define OSM6_VAL			(REG32_VAL(OSM6_ADDR))
-#define OSM7_VAL			(REG32_VAL(OSM7_ADDR))
-#define OSM0_VAL			(REG32_VAL(OSM0_ADDR))
-#define OSM1_VAL			(REG32_VAL(OSM1_ADDR))
-#define OSM2_VAL			(REG32_VAL(OSM2_ADDR))
-#define OSM3_VAL			(REG32_VAL(OSM3_ADDR))
-#define OSCR_VAL			(REG32_VAL(OSCR_ADDR))
-#define OSTS_VAL			(REG32_VAL(OSTS_ADDR))
-#define OSTW_VAL			(REG32_VAL(OSTW_ADDR))
-#define OSTI_VAL			(REG32_VAL(OSTI_ADDR))
-#define OSTC_VAL			(REG32_VAL(OSTC_ADDR))
-#define OSTA_VAL			(REG32_VAL(OSTA_ADDR))
-
-#define PMMISC_VAL			(REG32_VAL(PMMISC_ADDR))/*0x1FC*/
-#define PMPMA_VAL			(REG32_VAL(PMPMA_ADDR))/*0x200*/
-#define PMPMB_VAL			(REG32_VAL(PMPMB_ADDR))
-#define PMPMC_VAL			(REG32_VAL(PMPMC_ADDR))
-#define PMPMD_VAL			(REG32_VAL(PMPMD_ADDR))
-#define PMPME_VAL			(REG32_VAL(PMPME_ADDR))
-#define PMPMF_VAL			(REG32_VAL(PMPMF_ADDR))
-#define PMPMG_VAL			(REG32_VAL(PMPMG_ADDR))
-
-#define PMCEL_VAL			(REG32_VAL(PMCEL_ADDR))
-#define PMCEU_VAL			(REG32_VAL(PMCEU_ADDR))
-#define PMCE2_VAL			(REG32_VAL(PMCE2_ADDR))
-#define PMCE3_VAL			(REG32_VAL(PMCE3_ADDR))
-#define DVFSSTS_VAL   		(REG32_VAL(DVFSSTS_ADDR))
-#define DVFSE0_VAL    		(REG32_VAL(DVFSE0_ADDR))    
-#define DVFSE1_VAL    		(REG32_VAL(DVFSE1_ADDR))    
-#define DVFSE2_VAL    		(REG32_VAL(DVFSE2_ADDR))    
-#define DVFSE3_VAL    		(REG32_VAL(DVFSE3_ADDR))    
-#define DVFSE4_VAL    		(REG32_VAL(DVFSE4_ADDR))    
-#define DVFSE5_VAL    		(REG32_VAL(DVFSE5_ADDR))    
-#define DVFSE6_VAL    		(REG32_VAL(DVFSE6_ADDR))    
-#define DVFSE7_VAL    		(REG32_VAL(DVFSE7_ADDR))    
-#define DVFSE8_VAL    		(REG32_VAL(DVFSE8_ADDR))    
-#define DVFSE9_VAL    		(REG32_VAL(DVFSE9_ADDR))    
-#define DVFSE10_VAL   		(REG32_VAL(DVFSE10_ADDR))    
-#define DVFSE11_VAL   		(REG32_VAL(DVFSE11_ADDR))    
-#define DVFSE12_VAL   		(REG32_VAL(DVFSE12_ADDR))    
-#define DVFSE13_VAL   		(REG32_VAL(DVFSE13_ADDR))    
-#define DVFSE14_VAL   		(REG32_VAL(DVFSE14_ADDR))    
-#define DVFSE15_VAL   		(REG32_VAL(DVFSE15_ADDR))
-
-#define PMARM_VAL			(REG8_VAL(PMARM_ADDR))
-#define PMARMH_VAL			(REG8_VAL(PMARMH_ADDR))
-#define PMAHB_VAL			(REG8_VAL(PMAHB_ADDR))
-#define PMAHBH_VAL			(REG8_VAL(PMAHBH_ADDR))
-#define PMMC_VAL			(REG8_VAL(PMMC_ADDR))
-#define PML2C_VAL			(REG8_VAL(PML2C_ADDR))
-#define PML2CH_VAL			(REG8_VAL(PML2CH_ADDR))
-
-#define PMSF_VAL			(REG8_VAL(PMSF_ADDR))
-#define PMSFH_VAL			(REG8_VAL(PMSFH_ADDR))
-#define PMAPB1_VAL			(REG8_VAL(PMMAPB1_ADDR))
-#define PMAPB1H_VAL			(REG8_VAL(PMMAPB1H_ADDR))
-#define PMAPB0_VAL			(REG8_VAL(PMAPB0_ADDR))
-#define PMAPB0H_VAL			(REG8_VAL(PMAPB0H_ADDR))
-#define PMPCM0_VAL			(REG8_VAL(PMPCM0_ADDR))
-#define PMPCM0H_VAL			(REG8_VAL(PMPCM0H_ADDR))
-#define PMPCM1_VAL			(REG8_VAL(PMPCM1_ADDR))
-#define PMPCM1H_VAL			(REG8_VAL(PMPCM1H_ADDR))
-#define PMSDMMC_VAL			(REG8_VAL(PMSDMMC_ADDR))
-#define PMSDMMCH_VAL		(REG8_VAL(PMSDMMCH_ADDR))
-#define PMMSP_VAL			(REG8_VAL(PMMSP_ADDR))
-#define PMMSPH_VAL			(REG8_VAL(PMMSPH_ADDR))
-#define PMNAND_VAL			(REG8_VAL(PMNAND_ADDR))
-#define PMNANDH_VAL			(REG8_VAL(PMNANDH_ADDR))
-#define PMXD_VAL			(REG8_VAL(PMXD_ADDR))
-#define PMXDH_VAL			(REG8_VAL(PMXDH_ADDR))
-#define PMLCD_VAL			(REG8_VAL(PMLCD_ADDR))
-#define PMLCDH_VAL			(REG8_VAL(PMLCDH_ADDR))
-#define PMSPI_VAL			(REG8_VAL(PMSPI_ADDR))
-#define PMSPIH_VAL			(REG8_VAL(PMSPIH_ADDR))
-#define PMSPI1_VAL			(REG8_VAL(PMSPI1_ADDR))
-#define PMSPI1H_VAL			(REG8_VAL(PMSPI1H_ADDR))
-#define PMSE_VAL			(REG8_VAL(PMSE_ADDR))
-#define PMSEH_VAL			(REG8_VAL(PMSEH_ADDR))
-#define PMSDMMC1_VAL		(REG8_VAL(PMSDMMC1_ADDR))
-#define PMSDMMC1H_VAL		(REG8_VAL(PMSDMMC1H_ADDR))
-#define PMSDMMC2_VAL		(REG8_VAL(PMSDMMC2_ADDR))
-#define PMSDMMC2H_VAL		(REG8_VAL(PMSDMMC2H_ADDR))
-
-#define PMPWM_VAL			(REG8_VAL(PMPWM_ADDR))
-#define PMPWMH_VAL			(REG8_VAL(PMPWMH_ADDR))
-#define PMPAXI_VAL			(REG8_VAL(PMPAXI_ADDR))
-#define PMPAXIH_VAL			(REG8_VAL(PMPAXIH_ADDR))
-#define PMWMTNA_VAL			(REG8_VAL(PMWMTNA_ADDR))
-#define PMWMTNAH_VAL		(REG8_VAL(PMWMTNAH_ADDR))
-
-#define PMNA12_VAL			(REG8_VAL(PMNA12_ADDR))
-#define PMNA12H_VAL			(REG8_VAL(PMNA12H_ADDR))
-#define PMCNMNA_VAL			(REG8_VAL(PMCNMNA_ADDR))
-#define PMCNMNAH_VAL		(REG8_VAL(PMCNMNAH_ADDR))
-#define PMWMTVDU_VAL		(REG8_VAL(PMWMTVDU_ADDR))
-#define PMWMTVDUH_VAL		(REG8_VAL(PMWMTVDUH_ADDR))
-#define PMHDMITV_VAL		(REG8_VAL(PMHDMITV_ADDR))
-#define PMHDMITVH_VAL		(REG8_VAL(PMHDMITVH_ADDR))
-#define PMDVO_VAL			(REG8_VAL(PMDVO_ADDR))
-#define PMDVOH_VAL			(REG8_VAL(PMDVOH_ADDR))
-#define PMAUDIO_VAL			(REG8_VAL(PMAUDIO_ADDR))
-#define PMAUDIOH_VAL		(REG8_VAL(PMAUDIOH_ADDR))
-#define PMCSI0_VAL			(REG8_VAL(PMCSI0_ADDR))
-#define PMCSI0H_VAL			(REG8_VAL(PMCSI0H_ADDR))
-#define PMCSI1_VAL			(REG8_VAL(PMCSI1_ADDR))
-#define PMCSI1H_VAL			(REG8_VAL(PMCSI1H_ADDR))
-
-#define PMMALI_VAL			(REG8_VAL(PMMALI_ADDR))
-#define PMMALIH_VAL			(REG8_VAL(PMMALIH_ADDR))
-#define PMCNMVDU_VAL		(REG8_VAL(PMCNMVDU_ADDR))
-#define PMCNMVDUH_VAL		(REG8_VAL(PMCNMVDUH_ADDR))
-#define PMHDI2C_VAL			(REG8_VAL(PMHDI2C_ADDR))
-#define PMHDI2CH_VAL		(REG8_VAL(PMHDI2CH_ADDR))
-#define PMADC_VAL			(REG8_VAL(PMADC_ADDR))
-#define PMADCH_VAL			(REG8_VAL(PMADCH_ADDR))
-
-#define PMI2C4_VAL			(REG8_VAL(PMI2C4_ADDR))
-#define PMI2C4H_VAL			(REG8_VAL(PMI2C4H_ADDR))
-#define PMI2C0_VAL			(REG8_VAL(PMI2C0_ADDR))
-#define PMI2C0H_VAL			(REG8_VAL(PMI2C0H_ADDR))
-#define PMI2C1_VAL			(REG8_VAL(PMI2C1_ADDR))
-#define PMI2C1H_VAL			(REG8_VAL(PMI2C1H_ADDR))
-#define PMI2C2_VAL			(REG8_VAL(PMI2C2_ADDR))
-#define PMI2C2H_VAL			(REG8_VAL(PMI2C2H_ADDR))
-#define PMI2C3_VAL			(REG8_VAL(PMI2C3_ADDR))
-#define PMI2C3H_VAL			(REG8_VAL(PMI2C3H_ADDR))
-
-#define PML2CAXI_VAL		(REG8_VAL(PML2CAXI_ADDR))
-#define PML2CAXIH_VAL		(REG8_VAL(PML2CAXIH_ADDR))
-#define PMPERI_VAL			(REG8_VAL(PMPERI_ADDR))
-#define PMPERIH_VAL			(REG8_VAL(PMPERIH_ADDR))
-#define PMTRACE_VAL			(REG8_VAL(PMTRACE_ADDR))
-#define PMTRACEH_VAL		(REG8_VAL(PMTRACEH_ADDR))
-#define PMDBGAPB_VAL		(REG8_VAL(PMDBGAPB_ADDR))
-#define PMDBGAPBH_VAL		(REG8_VAL(PMDBGAPBH_ADDR))
-#define PML2CTAG_VAL		(REG8_VAL(PML2CTAG_ADDR))
-#define PML2CTAGH_VAL		(REG8_VAL(PML2CTAGH_ADDR))
-#define PML2CDATA_VAL		(REG8_VAL(PML2CDATA_ADDR))
-#define PML2CDATAH_VAL	(REG8_VAL(PML2CDATAH_ADDR))
-
-#define PMCA9PMWDOD_VAL 	(REG8_VAL(PMCA9PMWDOD_ADDR))		/* WATCH DOG RESET */
-#define PMSDPS_VAL			 	(REG8_VAL(PMSDPS_ADDR))					/* SD 0~2 POWER SWITCH */
-#define PMMALIGPPWR_VAL		(REG8_VAL(PMMALIGPPWR_ADDR))		/* MALI GP Power Shut Off Control and Status Register */
-#define PMWMTVDUPWR_VAL		(REG8_VAL(PMWMTVDUPWR_ADDR))		/* WMT VDU Power Shut Off Control and Status Register */
-#define PMCA9C0PWR_VAL	 	(REG8_VAL(PMCA9C0PWR_ADDR))	  	/* CA9 CORE 0 Power Shut Off Control and Status Register */
-#define PML2CRAMPWR_VAL 	(REG8_VAL(PML2CRAMPWR_ADDR))		/* L2CRAM Power Shut Off Control and Status Register */
-#define PMNEON0PWR_VAL 		(REG8_VAL(PMNEON0PWR_ADDR))		  /* NEON 0 Power Shut Off Control and Status Register */
-#define PMCA9C1PWR_VAL 		(REG8_VAL(PMCA9C1PWR_ADDR))		  /* CA9 CORE 1 Power Shut Off Control and Status Register */
-#define PMNEON1PWR_VAL	 	(REG8_VAL(PMNEON1PWR_ADDR))		  /* NEON 1 Power Shut Off Control and Status Register */
-#define PMC_MPWR_VAL	   	(REG8_VAL(PMC_MPWR_ADDR))			  /* C&M Power Shut Off Control and Status Register */
-#define PMMALIL2CPWR_VAL	(REG8_VAL(PMMALIL2CPWR_ADDR))		/* MALI L2C Power Shut Off Control and Status Register */
-#define PMMALIPP0PWR_VAL	(REG8_VAL(PMMALIPP0PWR_ADDR))		/* MALI PP0 Power Shut Off Control and Status Register */
-#define PMMALIPP1PWR_VAL	(REG8_VAL(PMMALIPP1PWR_ADDR))		/* MALI PP1 Power Shut Off Control and Status Register */
-#define AXI2AHB_VAL     	(REG8_VAL(AXI2AHB_ADDR))				/* AXI TO AHB POWER control */
-#define PMDSPPWR_VAL			(REG16_VAL(PMDSPPWR_ADDR))
-
-/*
- * (URRDR) Receive Data Regiser Description
- */
-#define URRDR_PER               0x100   /* Parity Error. This bit is the same as URISR[8] */
-#define URRDR_FER               0x200   /* Frame Error. This bit is the same as URISR[9] */
-
-/******************************************************************************
- *
- * PMCS_REG     PM (Current) Status Register bits definitions.
- *
- ******************************************************************************/
-#define PMCS_NORTC              BIT0    /* RTC Clock Logic Disabled       */
-#define PMCS_IDLE               BIT1    /* IDLE Operation Active          */
-#define PMCS_HIBER              BIT2    /* Hibernation Operation Active   */
-#define PMCS_ANY_CLK_DIV        BIT4    /* Updating Any Clock Divisor     */
-#define PMCS_ANY_PLL_MUL        BIT5    /* Updating Any PLL Multiplier    */
-#define PMCS_ZAC2               BIT8    /* Updating ZAC2_MA Clock Divisor */
-#define PMCS_AHB                BIT9    /* Updating AHB Clock Divisor     */
-#define PMCS_DSP                BIT10   /* Updating DSP Clock Divisor     */
-#define PMCS_LCD                BIT11   /* Updating LCD Clock Divisor     */
-#define PMCS_MC                 BIT12   /* Updating Memory Controller Clock Divisor */
-#define PMCS_CFC                BIT13   /* Updating Compact Flash Controller Clock Divisor */
-#define PMCS_USB                BIT14   /* Updating USB Clock Divisor     */
-#define PMCS_PCM                BIT15   /* Updating Pulse Code Modulation Clock Divisor */
-#define PMCS_PLLA               BIT16   /* Updating PLL A Multiplier Value */
-#define PMCS_PLLB               BIT17   /* Updating PLL B Multiplier Value */
-#define PMCS_PLLC               BIT18   /* Updating PLL C Multiplier Value */
-#define PMCS_SF                 BIT19   /* Updating Serial Flash Memory Cntrlr Divisor */
-#define PMCS_PATA               BIT21   /* Updating PATA Clock Divisor     */
-#define PMCS_SDMMC              BIT22   /* Updating SD/MMC Clock Divisor   */
-#define PMCS_MSC                BIT23   /* Updating MS/MSPRO Clock Divisor */
-#define PMCS_LPC                BIT24   /* Updating LPC Memory Cntrlr Clock Divisor */
-#define PMCS_NAND               BIT25   /* Updating NAND Clock Divisor     */
-#define PMCS_SPI                BIT26   /* Updating SPI Clock Divisor      */
-#define PMCS_PLLD               BIT27   /* Updating PLL D Multiplier Value */
-#define PMCS_BUSY               0xfffffffe
-
-/******************************************************************************
- *
- * PMIR_REG     PM Idle processor Request Register bit function.
- *
- ******************************************************************************/
-#define PMIR_IDLE                       /* IDLE Processor Request Bit */
-
-
-/******************************************************************************
- *
- * PMHC_REG     PM Hibernation Control Register bits functions.
- *
- ******************************************************************************/
-#define PMHC_SLEEP              0x03   /* A Power-on Hibernation Mode  */
-#define PMHC_SUSPEND            0x201   /* A Power-off Hibernation Mode */
-#define PMHC_SHUTDOWN           0x05   /* A Power-off Hibernation Mode */
-#define PMHC_25M_OSCLR          BIT8    /* 25MHz Oscillator Enable      */
-
-/******************************************************************************
- *
- * PMWS_REG     PM Wake-up Status register bits definitions.
- *
- ******************************************************************************/
-#define PMWS_WAKEMASK           0xFF    /* General Purpose Wake-up Status */
-#define PMWS_PWRBUTTON          BIT14   /* Power Button Wake-up Status    */
-#define PMWS_RTC                BIT15   /* RTC Wake-up Status             */
-
-/******************************************************************************
- *
- * PMWE_REG     PM Wake-up event Enable Register bits functions.
- *
- ******************************************************************************/
-#define PMWE_WAKEMASK           0xFF                    /* General Purpose Wake-up Enable */
-#define PMWE_WAKEUP(x)          (BIT0 << ((x) & 0x7))   /* Genaral Wake-up 0-7 Enable     */
-#define PMWE_RTC                BIT15                   /* RTC Wake-up Enable             */
-
-/******************************************************************************
- *
- * PMWT_REG     PM Wake-up event Type Register bits functions.
- *
- ******************************************************************************/
-#define PMWT_ZERO               0x00            /* Wake-up signal is a zero */
-#define PMWT_ONE                0x01            /* Wake-up signal is a one  */
-#define PMWT_FALLING            0x02            /* Wake-up signal generates a falling edge */
-#define PMWT_RISING             0x03            /* Wake-up signal generates a rising edge  */
-#define PMWT_EDGE               0x04            /* Wake-up signal generates an edge        */
-
-#define PMWT_TYPEMASK           0xFF   /* Wake-up event Type Mask                 */
-
-#define PMWT_WAKEUP0(x) (((x) & PMWT_TYPEMASK) << 0)  /* General Purpose Wake-up 0 Type bits */
-
-#define PMWT_WAKEUP1(x) (((x) & PMWT_TYPEMASK) << 4)  /* General Purpose Wake-up 1 Type bits */
-
-#define PMWT_WAKEUP2(x) (((x) & PMWT_TYPEMASK) << 8)  /* General Purpose Wake-up 2 Type bits */
-
-#define PMWT_WAKEUP3(x) (((x) & PMWT_TYPEMASK) << 12) /* General Purpose Wake-up 3 Type bits */
-
-#define PMWT_WAKEUP4(x) (((x) & PMWT_TYPEMASK) << 16) /* General Purpose Wake-up 4 Type bits */
-
-#define PMWT_WAKEUP5(x) (((x) & PMWT_TYPEMASK) << 20) /* General Purpose Wake-up 5 Type bits */
-
-#define PMWT_WAKEUP6(x) (((x) & PMWT_TYPEMASK) << 24) /* General Purpose Wake-up 6 Type bits */
-
-#define PMWT_WAKEUP7(x) (((x) & PMWT_TYPEMASK) << 28) /* General Purpose Wake-up 7 Type bits */
-
-#define PMWT_WAKEUPMASK         0x07            /* Max wakeup source number                */
-
-#define PMWT_WAKEUP(src, type)  ((type & PMWT_TYPEMASK) << ((src & PMWT_WAKEUPMASK) * 4))
-
-/******************************************************************************
- *
- * PMRS_REG     PM Reset Status Register bits definitions.
- *
- ******************************************************************************/
-#define PMRS_PMR                BIT0    /* Power Managment Reset  */
-#define PMRS_IOR                BIT1    /* I/O normal power Reset */
-#define PMRS_HBR                BIT2    /* HiBernation Reset      */
-#define PMRS_WDR                BIT3    /* WatchDog Reset         */
-#define PMRS_SWR                BIT4    /* SoftWare Reset         */
-#define PMRS_SHR                BIT5    /* Shutdown Reset         */
-#define PMRS_PGR                BIT6    /* Power good reset       */
-/* Bits 7-31: Reserved */
-
-/******************************************************************************
- *
- * PMPB_REG     PM Power Button Control Register
- *
- ******************************************************************************/
-#define PMPB_SOFTPWR            BIT0    /* Soft Power Enable      */
-#define PMPB_DEBOUNCE(x)		(((x) & 0xFF) << 16) /* PWRBTN debounce value unit ~ 32ms*/
-/* Bits 1-31: Reserved */
-
-/******************************************************************************
- *
- * PMSR_REG     PM Software Reset request Register bit function.
- *
- ******************************************************************************/
-#define PMSR_SWR                BIT0    /* SoftWare Reset request */
-/* Bits 1-31: Reserved */
-
-/******************************************************************************
- *
- * PMPATA_REG   PM PATA Interface Drive Strength Register (8-bit Register)
- *
- ******************************************************************************/
-#define PMPATA_ONETHIRD         0x00    /* One-third Drive Strength */
-#define PMPATA_ONEHALF          0x01    /* One-half Drive Strength  */
-#define PMPATA_TWOTHIRD         0x02    /* Two-third Drive Strength */
-#define PMPATA_FULL             0x03    /* Full Drive Strength      */
-#define PMSR_SWR                BIT0    /* SoftWare Reset request */
-/* Bits 2-7: Reserved */
-
-/******************************************************************************
- *
- * OSTS_REG     OS Timer Status Register bits definitions.
- *
- ******************************************************************************/
-#define OSTS_M0                 BIT0    /* OS Timer 0 Match detected */
-#define OSTS_M1                 BIT1    /* OS Timer 1 Match detected */
-#define OSTS_M2                 BIT2    /* OS Timer 2 Match detected */
-#define OSTS_M3                 BIT3    /* OS Timer 3 Match detected */
-#define OSTS_MASK               0xF
-/* Bits 4-31: Reserved */
-
-/******************************************************************************
- *
- * OSTW_REG     OS Timer Watchdog enable Register bit function.
- *
- ******************************************************************************/
-#define OSTW_WE                 BIT0    /* OS Timer Channel 0 Watchdog Enable */
-/* Bits 1-31: Reserved */
-
-/******************************************************************************
- *
- * OSTI_REG     OS Timer Interrupt enable Register bits functions.
- *
- ******************************************************************************/
-#define OSTI_E0                 BIT0    /* OS Timer Channel 0 Interrupt Enable */
-#define OSTI_E1                 BIT1    /* OS Timer Channel 0 Interrupt Enable */
-#define OSTI_E2                 BIT2    /* OS Timer Channel 0 Interrupt Enable */
-#define OSTI_E3                 BIT3    /* OS Timer Channel 0 Interrupt Enable */
-/* Bits 4-31: Reserved */
-/******************************************************************************
- *
- * OSTC_REG     OS Timer Control Register bits functions.
- *
- ******************************************************************************/
-#define OSTC_ENABLE             BIT0    /* OS Timer Enable bit             */
-#define OSTC_RDREQ              BIT1    /* OS Timer Read Count Request bit */
-/* Bits 2-31: Reserved */
-
-/******************************************************************************
- *
- * OSTA_REG     OS Timer Access status Register bits definitions.
- *
- ******************************************************************************/
-#define OSTA_MWA0               BIT0    /* OS Timer Match 0 Write Active */
-#define OSTA_MWA1               BIT1    /* OS Timer Match 1 Write Active */
-#define OSTA_MWA2               BIT2    /* OS Timer Match 2 Write Active */
-#define OSTA_MWA3               BIT3    /* OS Timer Match 3 Write Active */
-#define OSTA_CWA                BIT4    /* OS Timer Count Write Active   */
-#define OSTA_RCA                BIT5    /* OS Timer Read Count Active    */
-/* Bits 6-31: Reserved */
-
-/******************************************************************************
- *
- * PMMISC_REG   PM Miscellaneous Clock Controls Register
- *
- ******************************************************************************/
-#define PMMISC_24MHZ            BIT0    /* 24MHz Clock Source            */
-/* Bits 1-31: Reserved */
-
-/******************************************************************************
- *
- * Miscellaneous definitions
- *
- ******************************************************************************/
-#define __OST_BASE              0xD8130100      /* OS Timers base address */
-#define OST_MAX_CHANNEL         4               /* Four channels OS Timer */
-
-#if 1
-typedef struct _PMC_REG_ {
-	volatile unsigned int PM_Div_Upt0_sts; /* [Rx00-03] Device clock update status 0 Register*/
-	volatile unsigned int PM_Div_Upt1_sts; /* [Rx04-07] Device clock update status 1 Register*/
-	volatile unsigned char Idle;/* [Rx08] IDEL Processor Request Register*/
-	volatile unsigned char Resv9_0B[3];/* [Rx09 - 0B] Reserved*/
-	volatile unsigned short PU_Time_Ctrl;/* [Rx0C] Power-up Tme Control Register*/
-	volatile unsigned char Resv0E_0F[2];/* Reserved*/
-	volatile unsigned short Hib_Val;/* [Rx10 - Rx11] Hibernation Value Register*/
-	volatile unsigned short Hib_Ctrl;/* [Rx12 - Rx13] Hibernation Control Register*/
-	volatile unsigned int Wakeup_Sts;/* [Rx14-17]Wake up Status register*/
-	volatile unsigned int PM_Sts;/* [Rx18-1B] Power Management Status Register*/
-	volatile unsigned int Wakeup_Event_Enable;/* [Rx1C-1F] Wake-up Event Enable Register*/
-	volatile unsigned int Wakeup_Event_Type;/* [Rx20-23] Wake-up Event Type Register*/
-	volatile unsigned int Wakeup_CardDet_Event_Type;/* [Rx24-27] Card Detect Wake-up Event Type Register*/
-	volatile unsigned int CardDet_Sts_Int;/* [Rx28-2B] Card Detect Status And Card Detect Interrupt Register*/
-	volatile unsigned int CardReader_Debounce_Int_Type;/* [Rx2C-2F] Card Reader Attachment Debounce Control and Interrupt Type Register*/
-	volatile unsigned int Hib_Scratch0;/* [Rx30-33] Hibernate Scratch Pad Register0*/
-	volatile unsigned int Hib_Scratch1;/* [Rx34-37] Hibernate Scratch Pad Register1*/
-	volatile unsigned int Hib_Scratch2;/* [Rx38-3B] Hibernate Scratch Pad Register2*/
-	volatile unsigned int Hib_Scratch3;/* [Rx3c-3F] Hibernate Scratch Pad Register3*/
-	volatile unsigned int Hib_Scratch4;/* [Rx40-43] Hibernate Scratch Pad Register4*/
-	volatile unsigned int Hib_Scratch5;/* [Rx44-47] Hibernate Scratch Pad Register5*/
-	volatile unsigned int Hib_Scratch6;/* [Rx48-4B] Hibernate Scratch Pad Register6*/
-	volatile unsigned int Hib_Scratch7;/* [Rx4c-4F] Hibernate Scratch Pad Register7*/
-	volatile unsigned int Reset_Sts;/* [Rx50-53] Reset Status Register*/
-	volatile unsigned int PB_Control;/* [Rx54-57] Power Button Control Register;*/
-	volatile unsigned int AXI_LowPwr_Control;/* [Rx58-5B] AXI Low Power Interface Control Register;*/
-	volatile unsigned int Resv5c_5F[1];
-	volatile unsigned int SW_Reset_Req;/* [Rx60-63] Software Reset Request Register*/
-	volatile unsigned int Tout_Rstart;/* [Rx64-67] time out restart Control Register */
-	volatile unsigned int Broom_Powerdown;/* [Rx68-69] bootroom Powerdown, Cache-As-Ram, L2C RAM power force on, L2C bypass control*/
-	volatile unsigned char Resv6A_6B[0x2];
-	volatile unsigned int CA9MP_Sft_Rst_Ctrl;/* [Rx6C-6F] CA9MP soft reset control */
-	volatile unsigned int CA9MP_Sft_Rst_Sts;/* [Rx70-73] CA9MP soft reset ststus */
-	volatile unsigned int Int_Wak_Sts;/* [Rx74-77] interrupt status from wakeup source */
-	volatile unsigned int Resv78_7B[0x1];
-	volatile unsigned int Int_Wak_En;/* [Rx7C-7F] interrupt Enable from wakeup source */
-	volatile unsigned int Int_Wak_Type0;/* [Rx80-83] interrupt type0 from wakeup source */
-	volatile unsigned int Int_Wak_Type1;/* [Rx84-87] interrupt type1 from wakeup source */
-	volatile unsigned int Int_Wak_Type2;/* [Rx88-8B] interrupt type2 from wakeup source */
-	volatile unsigned int Resv8C_8F[0x1];
-	volatile unsigned int Rst_Vector_Rmap;/* [Rx90-93] Reset vector remap address register */
-	volatile unsigned int RTC_Clk_Exist_Monitor; /* [Rx94-97] RTC clock exist monitor Register */
-	volatile unsigned int Suspend_To_Dram_En; /* [Rx98-9B] suspend to DRAM enable register */
-	volatile unsigned char Resv9C_9F[0x4];
-	volatile unsigned int Wak_Event_Type; /* [RxA0-A3] wake event type for USBSW0, CIR ..*/
-	volatile unsigned int ResvA4_AC[0x3];
-	volatile unsigned int Wak_Trig_En; /* [RxB0-B3] wake triggle enable */
-	volatile unsigned int Int_Trig_En; /* [RxB4-B7] interrupt triggle enable */
-	volatile unsigned int ResvB8_BF[0x2];
-	volatile unsigned int CA9MP_Core0_Retvec; /* [RxC0-C3] CA9MP core 0 retvec register */
-	volatile unsigned int CA9MP_Core1_Retvec; /* [RxC4-C7] CA9MP core 1 retvec register */
-	volatile unsigned char PU_Src_Sts; /* [RxD0] Power up Source Status register */
-	volatile unsigned char ResvD1_EF[0x1F];
-	volatile unsigned int OS_Timer_Match4;/* [RxF0-RxF3] OS Timer Match Register4*/
-	volatile unsigned int OS_Timer_Match5;/* [RxF4-RxF7] OS Timer Match Registe5*/
-	volatile unsigned int OS_Timer_Match6;/* [RxF8-RxFB] OS Timer Match Register6*/
-	volatile unsigned int OS_Timer_Match7;/* [RxFC-RxFF] OS Timer Match Register7*/
-	volatile unsigned int OS_Timer_Match0;/* [Rx100-Rx103] OS Timer Match Register0*/
-	volatile unsigned int OS_Timer_Match1;/* [Rx104-Rx107] OS Timer Match Registe1*/
-	volatile unsigned int OS_Timer_Match2;/* [Rx108-Rx10B] OS Timer Match Register2*/
-	volatile unsigned int OS_Timer_Match3;/* [Rx10C-Rx10F] OS Timer Match Register3*/
-	volatile unsigned int OS_Timer_Count;/* [Rx110-113] OS Timer Counter Register*/
-	volatile unsigned int OS_Timer_Sts;/* [Rx114-117] OS Timer Status Register*/
-	volatile unsigned int OS_Timer_WatchDog_Enable;/* [Rx118-Rx11B]*/
-	volatile unsigned int OS_Timer_Int_Enable;/* [Rx11C-Rx11F]*/
-	volatile unsigned int OS_Timer_Ctrl;/* [Rx120-Rx123] OS Timer Control Register*/
-	volatile unsigned int OS_Timer_Access_Sts;/* [Rx124-Rx127] OS Timer Access Status Register*/
-	volatile unsigned int Resv128_1FB[0x35];
-	volatile unsigned int Misc_Clk_Ctrl;/* [Rx1FC-Rx1FF] miscellaneous clock controls register*/
-	volatile unsigned int PLLA;/* [Rx200-203] PLLA Multiplier and Range Values Register*/
-	volatile unsigned int PLLB;/* [Rx204-207] PLLB Multiplier and Range Values Register*/
-	volatile unsigned int PLLC;/* [Rx208-20B] PLLC Multiplier and Range Values Register*/
-	volatile unsigned int PLLD;/* [Rx20C-20F] PLLD Multiplier and Range Values Register*/
-	volatile unsigned int PLLE;/* [Rx210-213] PLLE Multiplier and Range Values Register*/
-	volatile unsigned int PLLF;/* [Rx214-217] PLLF Multiplier and Range Values Register*/
-	volatile unsigned int PLLG;/* [Rx218-21B] PLLG Multiplier and Range Values Register*/
-	volatile unsigned int PLL_AUD;/* [Rx21C-21F] PLL_AUD Multiplier and Range Values Register*/
-	volatile unsigned int PLL_Rdy_Sts;/* [Rx220-223] PLL Ready Status Register*/
-	volatile unsigned int Resv224_24F[0x0B];
-	volatile unsigned int Clock_Enable0;/* [Rx250-253] Clock Enable 0 Register*/
-	volatile unsigned int Clock_Enable1;/* [Rx254-257] Clock Enable 1 Register*/
-	volatile unsigned int Clock_Enable2;/* [Rx258-25B] Clock Enable 2 Register*/
-	volatile unsigned int Clock_Enable3;/* [Rx25C-25F] Clock Enable 3 Register*/
-	volatile unsigned int DVFS_Sts;/* [Rx260-263] DVFS Status Register*/
-	volatile unsigned int Resv264_27F[0x7];
-	volatile unsigned int DVFS_Entry0;/* [Rx280-283] DVFS Entry 0 Register*/
-	volatile unsigned int DVFS_Entry1;/* [Rx284-287] DVFS Entry 1 Register*/
-	volatile unsigned int DVFS_Entry2;/* [Rx288-28B] DVFS Entry 2 Register*/
-	volatile unsigned int DVFS_Entry3;/* [Rx28C-28F] DVFS Entry 3 Register*/
-	volatile unsigned int DVFS_Entry4;/* [Rx290-293] DVFS Entry 4 Register*/
-	volatile unsigned int DVFS_Entry5;/* [Rx294-297] DVFS Entry 5 Register*/
-	volatile unsigned int DVFS_Entry6;/* [Rx298-29B] DVFS Entry 6 Register*/
-	volatile unsigned int DVFS_Entry7;/* [Rx29c-29F] DVFS Entry 7 Register*/
-	volatile unsigned int DVFS_Entry8;/* [Rx2A0-2A3] DVFS Entry 8 Register*/
-	volatile unsigned int DVFS_Entry9;/* [Rx2A4-2A7] DVFS Entry 9 Register*/
-	volatile unsigned int DVFS_Entry10;/* [Rx2A8-2AB] DVFS Entry 10 Register*/
-	volatile unsigned int DVFS_Entry11;/* [Rx2AC-2AF] DVFS Entry 11 Register*/
-	volatile unsigned int DVFS_Entry12;/* [Rx2B0-2B3] DVFS Entry 12 Register*/
-	volatile unsigned int DVFS_Entry13;/* [Rx2B4-2B7] DVFS Entry 13 Register*/
-	volatile unsigned int DVFS_Entry14;/* [Rx2B8-2BB] DVFS Entry 14 Register*/
-	volatile unsigned int DVFS_Entry15;/* [Rx2BC-2BF] DVFS Entry 15 Register*/
-	volatile unsigned int Resv2C0_2FF[0x10];
-	volatile unsigned char ARM_Clock_Divisor;/* [Rx300] ARM Clock Divisor Register*/
-	/* [Rx301] ARM Clock High Pulse is the Wide Pulse Register*/
-	volatile unsigned char ARM_Clock_HiPulse;
-	volatile unsigned char Resv302_303[2];
-	volatile unsigned char AHB_Clock_Divisor;/* [Rx304] AHB Clock Divisor Value Register*/
-	volatile unsigned char Resv305_30B[7];
-	volatile unsigned char L2C_Clock_Divisor;/* [Rx30C] Clock Divisor Value L2C Register*/
-	volatile unsigned char L2C_Clock_HiPulse;
-	volatile unsigned char Resv30E_30F[2];
-	/* [Rx310] DDR Memory Controller Clock Divisor Value Register*/
-	volatile unsigned char DDR_Clock_Divisor;
-	volatile unsigned char Resv311_313[3];
-	/* [Rx314] Serial Flash Memory Controller Clock Divisor Value Register*/
-	volatile unsigned char SF_Clock_Divisor;
-	volatile unsigned char SF_Clock_HiPulse;/* [Rx315]*/
-	volatile unsigned char Resv316_317[2];
-	volatile unsigned char NF_Clock_Divisor;/* [Rx318] NF Clock Divisor Value Register*/
-	volatile unsigned char NF_Clock_HiPulse;/* [Rx319]*/
-	volatile unsigned char Resv31A_31B[2];
-	volatile unsigned char NOR_Clock_Divisor;/* [Rx31C] NOR Clock Divisor Value Register*/
-	volatile unsigned char NOR_Clock_HiPulse;/* [Rx31D]*/
-	volatile unsigned char Resv31E_31F[2];
-	volatile unsigned char APB_Clock_Divisor;/* [Rx320] APB Clock Divisor Value Register*/
-	volatile unsigned char Resv321_323[3];
-	volatile unsigned char PCM0_Clock_Divisor;/* [Rx324] PCM0 Clock Divisor Value Reigster*/
-	volatile unsigned char PCM0_Clock_HiPulse;/* [Rx325]*/
-	volatile unsigned char Resv326_327[2];
-	volatile unsigned char PCM1_Clock_Divisor;/* [Rx328] PCM1 Clock Divisor Value Reigster*/
-	volatile unsigned char PCM1_Clock_HiPulse;/* [Rx329]*/
-	volatile unsigned char Resv32A_32B[2];
-	volatile unsigned char Resv32C_32F[4];
-	volatile unsigned char SD_Clock_Divisor;/* [Rx330] SD/MMC Clock Divisor Value Reigster*/
-	volatile unsigned char SD_Clock_HiPulse;/* [Rx331]*/
-	volatile unsigned char Resv332_333[2];
-	volatile unsigned char SD1_Clock_Divisor;/* [Rx334] SD/MMC1 Clock Divisor Value Reigster*/
-	volatile unsigned char SD1_Clock_HiPulse;/* [Rx335]*/
-	volatile unsigned char Resv336_337[2];
-	volatile unsigned char SD2_Clock_Divisor;/* [Rx338] SD/MMC2 Clock Divisor Value Reigster*/
-	volatile unsigned char SD2_Clock_HiPulse;/* [Rx339]*/
-	volatile unsigned char Resv33A_33B[2];
-	volatile unsigned char Resv33C_33F[4];
-	volatile unsigned char SPI0_Clock_Divisor;/* [Rx340] SPI0 Clock Divisor Value Register*/
-	/* [Rx341] SPI0 Clock High Pulse is the Wide Pulse Register*/
-	volatile unsigned char SPI0_Clock_HiPulse;
-	volatile unsigned char Resv342_343[2];
-	volatile unsigned char SPI1_Clock_Divisor;/* [Rx344] SPI1 Clock Divisor Value Register*/
-	/* [Rx345] SPI1 Clock High Pulse is the Wide Pulse Register*/
-	volatile unsigned char SPI1_Clock_HiPulse;
-	volatile unsigned char Resv346_347[2];
-	volatile unsigned char SE_Clock_Divisor;/* [Rx348] SE Clock Divisor Value Register*/
-	/* [Rx349] SE Clock High Pulse is the Wide Pulse Register*/
-	volatile unsigned char SE_Clock_HiPulse;
-	volatile unsigned char Resv34A_34F[6];
-	volatile unsigned char PWM_Clock_Divisor;/* [Rx350] PWM Clock Divisor Register*/
-	volatile unsigned char PWM_Clock_HiPulse;/* [Rx351] PWM Clock High Pulse is the Wide Pulse Register*/
-	volatile unsigned char Resv352_353[2];
-	volatile unsigned char PAXI_Clock_Divisor;/* [Rx354] PAXI Clock Divisor Value Register*/
-	volatile unsigned char PAXI_Clock_HiPulse;/* [Rx355] PAXI Clock High Pulse is the Wide Pulse Register*/
-	volatile unsigned char Resv356_357[2];
-	volatile unsigned char WMT_NA_Clock_Divisor;/* [Rx358]*/
-	volatile unsigned char WMT_NA_Clock_HiPulse;/* [Rx359] WMT NA0 Clock High Pulse is the Wide Pulse Register*/
-	volatile unsigned char Resv35A_35B[2];
-	volatile unsigned char NA12_Clock_Divisor;/* [Rx35C]*/
-	volatile unsigned char NA12_Clock_HiPulse;/* [Rx35D] NA12 Clock High Pulse is the Wide Pulse Register*/
-	volatile unsigned char Resv35E_35F[2];
-	volatile unsigned char CNM_NA_Clock_Divisor;/* [Rx360]*/
-	volatile unsigned char CNM_NA_Clock_HiPulse;/* [Rx361] CNM NA Clock High Pulse is the Wide Pulse Register*/
-	volatile unsigned char Resv362_367[6];
-	volatile unsigned char WMT_VDU_Clock_Divisor;/* [Rx368]*/
-	volatile unsigned char WMT_VDU_Clock_HiPulse;/* [Rx369] WMT VDU Clock High Pulse is the Wide Pulse Register*/
-	volatile unsigned char Resv36A_36B[2];
-	volatile unsigned char DVOTV2_Clock_Divisor;/* [Rx36C]*/
-	volatile unsigned char DVOTV2_Clock_HiPulse;/* [Rx36D] DVOTV2 Clock High Pulse is the Wide Pulse Register*/
-	volatile unsigned char TV2_Encoder_En;/* [Rx36E]*/
-	volatile unsigned char Resv36F[1];
-	volatile unsigned char DVO2_Clock_Divisor;/* [Rx370]*/
-	volatile unsigned char DVO2_Clock_HiPulse;/* [Rx371] DVO2 Clock High Pulse is the Wide Pulse Register*/
-	volatile unsigned char Resv372_373[2];
-	volatile unsigned char AUD_Clock_Divisor;/* [Rx374] AUD Clock Divisor Value Register*/
-	volatile unsigned char AUD_Clock_HiPulse;/* [Rx375] AUD Clock High Pulse is the Wide Pulse Register*/
-	volatile unsigned char Resv376_377[2];
-	volatile unsigned char Ring1_Clock_Divisor;/* [Rx378] Ring OSC 1st divider Register*/
-	volatile unsigned char Resv379_37B[3];
-	volatile unsigned char Ring2_Clock_Divisor;/* [Rx37C] Ring OSC 2st divider Register*/
-	volatile unsigned char Resv37D_37F[3];
-	volatile unsigned char CSI0_Clock_Divisor;/* [Rx380]*/
-	volatile unsigned char CSI0_Clock_HiPulse;/* [Rx381] CSI0 Clock High Pulse is the Wide Pulse Register*/
-	volatile unsigned char Resv382_383[2];
-	volatile unsigned char CSI1_Clock_Divisor;/* [Rx384]*/
-	volatile unsigned char CSI1_Clock_HiPulse;/* [Rx385] CSI1 Clock High Pulse is the Wide Pulse Register*/
-	volatile unsigned char Resv386_387[2];
-	volatile unsigned char MALI_Clock_Divisor;/* [Rx388]*/
-	volatile unsigned char MALI_Clock_HiPulse;/* [Rx389] MALI Clock High Pulse is the Wide Pulse Register*/
-	volatile unsigned char Resv38A_38B[2];
-	volatile unsigned char CNM_VDU_Clock_Divisor;/* [Rx38C]*/
-	volatile unsigned char CNM_VDU_Clock_HiPulse;/* [Rx38D] CNM VDU Clock High Pulse is the Wide Pulse Register*/
-	volatile unsigned char Resv38E_38F[2];
-	volatile unsigned char HDMI_I2C_Clock_Divisor;/* [Rx390]*/
-	volatile unsigned char HDMI_I2C_Clock_HiPulse;/* [Rx391] HDMI Clock High Pulse is the Wide Pulse Register*/
-	volatile unsigned char Resv392_393[2];
-	volatile unsigned char ADC_Clock_Divisor;/* [Rx394] ADC Clock Divisor Value Register*/
-	volatile unsigned char ADC_Clock_HiPulse;/* [Rx395]*/
-	volatile unsigned char Resv396_39F[6];
-	volatile unsigned char I2C4_Clock_Divisor;/* [Rx39C]*/
-	volatile unsigned char I2C4_Clock_HiPulse;/* [Rx39D] I2C4 Clock High Pulse is the Wide Pulse Register*/
-	volatile unsigned char Resv39E_39F[2];
-	volatile unsigned char I2C0_Clock_Divisor;/* [Rx3A0]*/
-	volatile unsigned char I2C0_Clock_HiPulse;/* [Rx3A1] I2C0 Clock High Pulse is the Wide Pulse Register*/
-	volatile unsigned char Resv3A2_3A3[2];
-	volatile unsigned char I2C1_Clock_Divisor;/* [Rx3A4]*/
-	volatile unsigned char I2C1_Clock_HiPulse;/* [Rx3A5] I2C1 Clock High Pulse is the Wide Pulse Register*/
-	volatile unsigned char Resv3A6_3A7[2];
-	volatile unsigned char I2C2_Clock_Divisor;/* [Rx3A8]*/
-	volatile unsigned char I2C2_Clock_HiPulse;/* [Rx3A9] I2C2 Clock High Pulse is the Wide Pulse Register*/
-	volatile unsigned char Resv3AA_3AB[2];
-	volatile unsigned char I2C3_Clock_Divisor;/* [Rx3AC]*/
-	volatile unsigned char I2C3_Clock_HiPulse;/* [Rx3AD] I2C3 Clock High Pulse is the Wide Pulse Register*/
-	volatile unsigned char Resv3AE_3AF[2];
-	volatile unsigned char L2C_AXI_Clock_Divisor;/* [Rx3B0]*/
-	volatile unsigned char L2C_AXI_Clock_HiPulse;/* [Rx3B1] L2C_AXI Clock High Pulse is the Wide Pulse Register*/
-	volatile unsigned char Resv3B2_3B3[2];
-	volatile unsigned char ATCLK_Clock_Divisor;/* [Rx3B4]*/
-	volatile unsigned char ATCLK_Clock_HiPulse;/* [Rx3B5] ATCLK Clock High Pulse is the Wide Pulse Register*/
-	volatile unsigned char Resv3B6_3B7[2];
-	volatile unsigned char PERICLK_Clock_Divisor;/* [Rx3B8]*/
-	volatile unsigned char PERICLK_Clock_HiPulse;/* [Rx3B9] PERICLK Clock High Pulse is the Wide Pulse Register*/
-	volatile unsigned char Resv3BA_3BB[2];
-	volatile unsigned char TRACECLK_Clock_Divisor;/* [Rx3BC]*/
-	volatile unsigned char TRACECLK_Clock_HiPulse;/* [Rx3BD] TRACECLK Clock High Pulse is the Wide Pulse Register*/
-	volatile unsigned char Resv3BE_3BF[2];
-	volatile unsigned char Resv3C0_3CF[0x10];
-	volatile unsigned char DBUG_APB_Clock_Divisor;/* [Rx3D0]*/
-	volatile unsigned char DBUG_APB_Clock_HiPulse;/* [Rx3D1] DBUG APB Clock High Pulse is the Wide Pulse Register*/
-	volatile unsigned char Resv3D2_3D3[2];
-	volatile unsigned char Resv3D4_3E3[0x10];
-	volatile unsigned char Hz24M_Clock_Divisor;/* [Rx3E4]*/
-	volatile unsigned char Hz24M_Clock_HiPulse;/* [Rx3E5] 24MHZ Clock High Pulse is the Wide Pulse Register*/
-	volatile unsigned char Resv3E6_3EF[10];
-	volatile unsigned char L2C_TAG_Clock_Divisor;/* [Rx3F0]*/
-	volatile unsigned char L2C_TAG_Clock_HiPulse;/* [Rx3F1] L2C_TAG Clock High Pulse is the Wide Pulse Register*/
-	volatile unsigned char Resv3F2_3F3[2];
-	volatile unsigned char L2C_DATA_Clock_Divisor;/* [Rx3F4]*/
-	volatile unsigned char L2C_DATA_Clock_HiPulse;/* [Rx3F5] L2C_DATA Clock High Pulse is the Wide Pulse Register*/
-	volatile unsigned char Resv3F6_47F[0x8A];
-	volatile unsigned char CA9MP_Watchdog_Rst_Ctrl;/* [Rx480]*/
-	volatile unsigned char Resv481_4FF[0x7F];
-	volatile unsigned char PS_Control;/* [Rx500] 1.1.1.85	CARD, SD0~2 Power Switch Control Register*/
-	volatile unsigned char Resv501[0xFF];
-	volatile unsigned int MALI_GP_PWR_Shut_Off_CTRL_STS;/* [Rx600-603] mali GP power shut off control and status Register*/
-	volatile unsigned int WMT_VDU_PWR_Shut_Off_CTRL_STS;/* [Rx604-607] WMT VDU power shut off control and status Register*/
-	volatile unsigned int CA9MP_CORE0_PWR_Shut_Off_CTRL_STS;/* [Rx608-60B] CA9MP CORE0 power shut off control and status Register*/
-	volatile unsigned int L2C_DATA_PWR_Shut_Off_CTRL_STS;/* [Rx60C-60F] L2C DATA power shut off control and status Register*/
-	volatile unsigned int NEON0_PWR_Shut_Off_CTRL_STS;/* [Rx610-613] NEON0 power shut off control and status Register*/
-	volatile unsigned int CA9MP_CORE1_PWR_Shut_Off_CTRL_STS;/* [Rx614-617] CA9MP CORE1 power shut off control and status Register*/
-	volatile unsigned int NEON1_PWR_Shut_Off_CTRL_STS;/* [Rx618-61B] NEON1 power shut off control and status Register*/
-	volatile unsigned int CNM_NA_PWR_Shut_Off_CTRL_STS;/* [Rx61C-61F] C&M NA power shut off control and status Register*/
-	volatile unsigned int MALI_L2C_PWR_Shut_Off_CTRL_STS;/* [Rx620-623] mali L2C power shut off control and status Register*/
-	volatile unsigned int MALI_PP0_PWR_Shut_Off_CTRL_STS;/* [Rx624-627] mali PP0 power shut off control and status Register*/
-	volatile unsigned int MALI_PP1_PWR_Shut_Off_CTRL_STS;/* [Rx628-62B] mali PP1 power shut off control and status Register*/
-	volatile unsigned char Resv62C_64F[0x24];
-	volatile unsigned int AXI_TO_AHB_Bridge_Pwr_Ctrl;/* [Rx650-653] AXI to AHB bridge power control and status Register*/
-	volatile unsigned int PAXI_TO_AHB_Bridge_Pwr_Ctrl;/* [Rx654-657] PAXI to AHB bridge power control and status Register*/
-} PMC_REG, *PPMC_REG;
-#endif
-
-/******************************************************************************
- *
- * clock enable/disbale macro define
- * CLOCKSET(CLOCK_BIT,CLOCK_SET) 
- * example:
- * CLOCKSET(UART3_CB,EN_C);  --> enable uart3 clock
- * CLOCKSET(UART3_CB,DIS_C); --> disable uart3 clock
- *
- ******************************************************************************/
-
-#if 0
-enum CLOCK_BIT {
-	I2C1_CB			= 0,	/* I2C1 clock					*/
-	UART0_CB,					/* UART0 Clock				*/
-	UART1_CB,					/* UART1 Clock				*/
-	UART2_CB,					/* UART2 Clock				*/
-	UART3_CB,					/* UART3 Clock				*/
-	I2C0_CB,					/* I2C0 clock					*/
-	RTC_CB			= 7,	/* RTC clock					*/
-	KEYPAD_CB		= 9,	/* KEYPAD clock				*/
-	PWM_CB,						/* PWM clock					*/
-	GPIO_CB,					/* GPIO clock					*/
-	SPI0_CB,					/* SPI0 clock					*/
-	SPI1_CB,					/* SPI1 clock					*/
-	AHB1_CB			=15,	/* AHB1 clock					*/
-	I2S_CB,						/* I2S clock					*/
-	CIR_CB,						/* CIR clock					*/
-	DVO_CB,						/* DVO clock					*/
-	AC97_CB,					/* AC97 clock					*/
-	PCM_CB,						/* PCM clock					*/
-	SCC_CB,						/* SCC clock					*/
-	JDEC_CB,					/* JDEC clock					*/
-	MSCD_CB,					/* MSCD clock					*/
-	AMP_CB,						/* AMP clock					*/
-	DSP_CB,						/* DSP clock					*/
-	DISP_CB,					/* DISP clock					*/
-	VPU_CB,						/* VPU clock					*/
-	MBOX_CB,					/* MBOX clock					*/
-	GE_CB,						/* GE clock						*/
-	GOVRHD_CB,				/* GOVRHD clock				*/
-	DDR_CB			=32,	/* DDR clock					*/
-	NA0_CB,						/* NA0 clock					*/
-	NA12_CB,					/* NA12 clock					*/
-	ARF_CB,						/* ARF clock					*/
-	ARFP_CB,					/* ARFP clock					*/
-	DMA_CB,						/* DMA clock					*/
-	ROT_CB,						/* ROT clock					*/
-	UHDC_CB,					/* UHDC clock					*/
-	PERM_CB,					/* PERM clock					*/
-	PDMA_CB,					/* PDMA clock					*/
-	SMARTCARD_CB,			/* SMARTCARD clock		*/
-	IDE100_CB,				/* IDE100 clock				*/
-	IDE133_CB,				/* IDE133 clock				*/
-	AHBB_CB,					/* AHBB clock					*/
-	SDTV_CB,					/* SDTV clock					*/
-	XD_CB,						/* XD clock						*/
-	NAND_CB,					/* NAND clock					*/
-	MSP_CB,						/* MSP clock					*/
-	SD0_CB,						/* SD0 clock					*/
-	SD1_CB,						/* SD1 clock					*/
-	MAC0_CB,					/* MAC0 clock					*/
-	SYS_CB,						/* SYS clock					*/
-	TSBK_CB,					/* TSBK clock					*/
-	SF_CB,						/* SF clock						*/
-	SAE_CB,						/* SAE clock					*/
-	H264_CB,					/* H264 clock					*/
-	EPHY_CB,					/* EPHY clock					*/
-	SCL444U_CB	=60,	/* SCL444U clock			*/
-	GOVW_CB,					/* GOVW clock					*/
-	VID_CB,						/* VID clock					*/
-	VPP_CB						/* VPP clock					*/
-};
-#endif
-
-enum CLOCK_BIT {
-        IDE100_CB = 43,	
-	XD_CB     = 47					/* XD clock */		
-};
-
-enum CLOCK_SET {
-	DIS_C         = 0,   /* Disabble clock          */
-	EN_C                 /* Enable Clock            */
-};
-
-#define CLOCKDIS(x)	((x < 32) ? (PMCEL_VAL &= ~(1 << x)):(PMCEU_VAL &= ~(1 << (x-32))))
-#define CLOCKEN(x)	((x < 32) ? (PMCEL_VAL |= (1 << x)):(PMCEU_VAL |= (1 << (x-32))))
-
-#define CLOCKSET(x,op) ((op) ? CLOCKEN(x):CLOCKDIS(x))
-
-#if 1
-/*wakeup event*/
-//#define PMWT_C_WAKEUP(src, type)  ((type & PMWT_TYPEMASK) << (((src - 24) & PMWT_WAKEUPMASK) * 4))
-
-enum wakeup_src_e {
-	WKS_WK0         = 0,    /* General Purpose Wakeup Source 0          */
-	WKS_WK2,                /* General Purpose Wakeup Source 1          */
-	WKS_WK3,                /* General Purpose Wakeup Source 2          */
-	WKS_WK4,                /* General Purpose Wakeup Source 3          */
-	WKS_SUS0,                /* General Purpose Wakeup Source 4          */
-	WKS_SUS1,                /* General Purpose Wakeup Source 5          */
-	WKS_USBATTA0,            /* USBATTA0          */
-	WKS_CIRIN,               /* CIRIN          */	
-	WKS_PWRBTN		= 14,    /* PWRBTN as wakeup            */
-	WKS_RTC			= 15,    /* RTC as wakeup            */
-	WKS_USBOC0		= 16,    /* WKS_USBOC0 as wakeup            */
-	WKS_USBOC1		= 17,    /* WKS_USBOC0 as wakeup            */
-	WKS_USBOC2		= 18,    /* WKS_USBOC0 as wakeup            */
-	WKS_USBOC3		= 19,    /* WKS_USBOC0 as wakeup            */		
-	WKS_UHC			= 20,    /* UHC interrupt as wakeup                  */
-	WKS_UDC			= 21,    /* WKS_UDC interrupt as wakeup              */	
-	WKS_CIR			= 22,    /* CIR interrupt as wakeupr                 */
-	WKS_USBSW0		= 23,    /* USBSW0 interrupt as wakeupr          */
-	WKS_SD3			= 26,    /* SD3 interrupt as wakeupr                 */	
-	WKS_DCDET		= 27,    /* DCDET interrupt as wakeupr               */	
-	WKS_SD2			= 28,    /* SD2 interrupt as wakeupr                 */	
-	WKS_HDMICEC		= 29,    /* HDMICEC interrupt as wakeupr             */	
-	WKS_SD0			= 30,    /* SD0 interrupt as wakeupr                 */
-	WKS_WK5			= 31     /* Wakeup event number                      */
-};
-
-extern void pmc_enable_wakeup_isr(enum wakeup_src_e wakeup_event, unsigned int type);
-extern void pmc_disable_wakeup_isr(enum wakeup_src_e wakeup_event);
-extern void pmc_clear_intr_status(enum wakeup_src_e wakeup_event);
-extern void pmc_clear_wakeup_status(enum wakeup_src_e wakeup_event);
-extern void pmc_enable_wakeup_event(enum wakeup_src_e wakeup_event, unsigned int type);
-extern void pmc_disable_wakeup_event(enum wakeup_src_e wakeup_event);
-
-#endif
-
-//#define UDC_HOTPLUG_TIMER
-
-#endif /* __VT8500_PMC_H */
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_rtc.h b/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_rtc.h
deleted file mode 100755
index 842d8e56..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_rtc.h
+++ /dev/null
@@ -1,330 +0,0 @@
-/*++
-linux/include/asm-arm/arch-wmt/wmt_rtc.h
-
-Copyright (c) 2008  WonderMedia Technologies, Inc.
-
-This program is free software: you can redistribute it and/or modify it under the
-terms of the GNU General Public License as published by the Free Software Foundation,
-either version 2 of the License, or (at your option) any later version.
-
-This program is distributed in the hope that it will be useful, but WITHOUT
-ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-PARTICULAR PURPOSE.  See the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License along with
-this program.  If not, see <http://www.gnu.org/licenses/>.
-
-WonderMedia Technologies, Inc.
-10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
---*/
-
-/* Be sure that virtual mapping is defined right */
-#ifndef __ASM_ARCH_HARDWARE_H
-#error "You must include hardware.h, not wmt_rtc.h"
-#endif
-
-#ifndef __WMT_RTC_H
-#define __WMT_RTC_H
-
-/******************************************************************************
- *
- * Define the register access macros.
- *
- * Note: Current policy in standalone program is using register as a pointer.
- *
- ******************************************************************************/
-#include "wmt_mmap.h"
-
-/******************************************************************************
- *
- * WMT Real Time Clock Base Address.
- *
- ******************************************************************************/
-#ifdef __RTC_BASE
-#error  "__RTC_BASE has already been defined in another file."
-#endif
-#define __RTC_BASE      RTC_BASE_ADDR
-
-/******************************************************************************
- *
- * macros to translate to/from binary and binary-coded decimal
- *
- ******************************************************************************/
-#define BCD2BIN(x)    (((x)&0x0f) + ((x) >> 4)*10)
-#define BIN2BCD(x)    ((((x)/10) << 4) + (x)%10)
-
-/******************************************************************************
- *
- * WMT Real Time Clock (RTC) control registers.
- *
- * Registers Abbreviations:
- *
- * RTTS_REG     RTC Time Set Register.
- *
- * RTDS_REG     RTC Date Set Register.
- *
- * RTAS_REG     RTC Alarm Set Register.
- *
- * RTCC_REG     RTC Control Register.
- *
- * RTCT_REG     RTC Current Time Register.
- *
- * RTCD_REG     RTC Current Date Register.
- *
- * RTWS_REG     RTC Write Status Register.
- *
- * RTTM_REG     RTC Test Mode Register.
- *
- * RTTC_REG     RTC Time Calibration Register.
- *
- * RTIS_REG     RTC Interrupt Status Register.
- *
- ******************************************************************************/
-/******************************************************************************
- *
- * Address constant for each register.
- *
- ******************************************************************************/
-#define	RTTS_ADDR       (__RTC_BASE + 0x00)
-#define	RTDS_ADDR       (__RTC_BASE + 0x04)
-#define	RTAS_ADDR       (__RTC_BASE + 0x08)
-#define	RTCC_ADDR       (__RTC_BASE + 0x0C)
-#define	RTCT_ADDR       (__RTC_BASE + 0x10)
-#define	RTCD_ADDR       (__RTC_BASE + 0x14)
-#define	RTWS_ADDR       (__RTC_BASE + 0x18)
-#define	RTTM_ADDR       (__RTC_BASE + 0x1C)
-#define	RTTC_ADDR       (__RTC_BASE + 0x20)
-#define	RTIS_ADDR       (__RTC_BASE + 0x24)
-#define	RTSR_ADDR       (__RTC_BASE + 0x28)
-
-
-/******************************************************************************
- *
- * Register pointer.
- *
- ******************************************************************************/
-#define	RTTS_REG        (REG32_PTR(RTTS_ADDR))
-#define	RTDS_REG        (REG32_PTR(RTDS_ADDR))
-#define	RTAS_REG        (REG32_PTR(RTAS_ADDR))
-#define	RTCC_REG        (REG32_PTR(RTCC_ADDR))
-#define	RTCT_REG        (REG32_PTR(RTCT_ADDR))
-#define	RTCD_REG        (REG32_PTR(RTCD_ADDR))
-#define	RTWS_REG        (REG32_PTR(RTWS_ADDR))
-#define	RTTM_REG        (REG32_PTR(RTTM_ADDR))
-#define	RTTC_REG        (REG32_PTR(RTTC_ADDR))
-#define	RTIS_REG        (REG32_PTR(RTIS_ADDR))
-#define	RTSR_REG        (REG32_PTR(RTSR_ADDR))
-
-/*16'h002c-16'hFFFF Reserved (Read-only, all zeros) */
-
-/******************************************************************************
- *
- * Register value.
- *
- ******************************************************************************/
-#define	RTTS_VAL        (REG32_VAL(RTTS_ADDR))
-#define	RTDS_VAL        (REG32_VAL(RTDS_ADDR))
-#define	RTAS_VAL        (REG32_VAL(RTAS_ADDR))
-#define	RTCC_VAL        (REG32_VAL(RTCC_ADDR))
-#define	RTCT_VAL        (REG32_VAL(RTCT_ADDR))
-#define	RTCD_VAL        (REG32_VAL(RTCD_ADDR))
-#define	RTWS_VAL        (REG32_VAL(RTWS_ADDR))
-#define	RTTM_VAL        (REG32_VAL(RTTM_ADDR))
-#define	RTTC_VAL        (REG32_VAL(RTTC_ADDR))
-#define	RTIS_VAL        (REG32_VAL(RTIS_ADDR))
-#define	RTSR_VAL        (REG32_VAL(RTSR_ADDR))
-/*16'h002c-16'hFFFF Reserved (Read-only, all zeros) */
-
-/******************************************************************************
- *
- * RTTS_REG     RTC Time Set Register bits functions.
- *
- ******************************************************************************/
-#define	RTTS_OSEC               (BIT0 | BIT1 | BIT2 | BIT3)         /* One digit */
-#define	RTTS_TSEC               (BIT4 | BIT5 | BIT6)                /* Ten digit */
-#define	RTTS_OMIN               (BIT7 | BIT8 | BIT9 | BIT10)
-#define	RTTS_TMIN               (BIT11 | BIT12 | BIT13)
-#define	RTTS_OHOUR              (BIT14 | BIT15 | BIT16 | BIT17)
-#define	RTTS_THOUR              (BIT18 | BIT19)
-#define	RTTS_WDAY               (BIT20 | BIT21 | BIT22)             /* wday      */
-#define	RTTS_TIME               0x7FFFFF                            /* Bits 0-22 */
-/* Bits 23-31: Reserved */
-
-/* BIN2BCD macros
- * in  : sec, min, hour, wday (in binary)
- * out : RTTS_VAL
- */
-#define	RTTS_SEC(x)             ((BIN2BCD(x) << 0) & (RTTS_OSEC | RTTS_TSEC))
-#define	RTTS_MIN(x)             ((BIN2BCD(x) << 7) & (RTTS_OMIN | RTTS_TMIN))
-#define	RTTS_HOUR(x)            ((BIN2BCD(x) << 14) & (RTTS_OHOUR | RTTS_THOUR))
-#define	RTTS_DAY(x)             ((BIN2BCD(x) << 20) &  RTTS_WDAY)
-
-/******************************************************************************
- *
- * RTDS_REG     RTC Date Set Register bits functions.
- *
- ******************************************************************************/
-#define	RTDS_ODAY               (BIT0 | BIT1 | BIT2 | BIT3)       /* One digit */
-#define	RTDS_TDAY               (BIT4 | BIT5)                     /* Ten digit */
-#define	RTDS_OMON               (BIT6 | BIT7 | BIT8 | BIT9)
-#define	RTDS_TMON               BIT10
-#define	RTDS_OYEAR              (BIT11 | BIT12 | BIT13 | BIT14)
-#define	RTDS_TYEAR              (BIT15 | BIT16 | BIT17 | BIT18)
-#define RTDS_CEN                BIT19
-#define	RTDS_DATE               0x000FFFFF                        /* Bits 0-19 */
-/* Bits 20-31: Reserved */
-
-/* BIN2BCD macros
- * in  : mday, mon, year, century (in binary)
- * out : RTDS_VAL
- */
-#define	RTDS_MDAY(x)            ((BIN2BCD(x) << 0) & (RTDS_ODAY | RTDS_TDAY))
-#define	RTDS_MON(x)             ((BIN2BCD(x) << 6) & (RTDS_OMON | RTDS_TMON))
-#define	RTDS_YEAR(x)            ((BIN2BCD(x) << 11) & (RTDS_OYEAR | RTDS_TYEAR))
-#define	RTDS_CENT(x)            ((BIN2BCD(x) << 19) & RTDS_CEN)
-
-/******************************************************************************
- *
- * RTAS_REG     RTC Alarm Set Register bits functions.
- *
- ******************************************************************************/
-#define	RTAS_OSEC               (BIT0 | BIT1 | BIT2 | BIT3)         /* One digit */
-#define	RTAS_TSEC               (BIT4 | BIT5 | BIT6)                /* Ten digit */
-#define	RTAS_OMIN               (BIT7 | BIT8 | BIT9 | BIT10)
-#define	RTAS_TMIN               (BIT11 | BIT12 | BIT13)
-#define	RTAS_OHOUR              (BIT14 | BIT15 | BIT16 | BIT17)
-#define	RTAS_THOUR              (BIT18 | BIT19)
-#define	RTAS_ODAY               (BIT20 | BIT21 | BIT22 | BIT23)     /* mday      */
-#define	RTAS_TDAY               (BIT24 | BIT25)
-#define	RTAS_ALMASK             0x03FFFFFF                          /* Bits 0-25 */
-#define RTAS_CMPSEC             BIT26
-#define RTAS_CMPMIN             BIT27
-#define RTAS_CMPHOUR            BIT28
-#define RTAS_CMPDAY             BIT29
-#define RTAS_CMPMASK            (BIT26 | BIT27 | BIT28 | BIT29)
-/* Bits 30-31: Reserved */
-
-/* BIN2BCD macros
- * in  : sec, min, hour, mday (in binary)
- * out : RTAS_VAL
- */
-#define	RTAS_SEC(x)             ((BIN2BCD(x) << 0) & (RTAS_OSEC | RTAS_TSEC))
-#define	RTAS_MIN(x)             ((BIN2BCD(x) << 7) & (RTAS_OMIN | RTAS_TMIN))
-#define	RTAS_HOUR(x)            ((BIN2BCD(x) << 14) & (RTAS_OHOUR | RTAS_THOUR))
-#define	RTAS_DAY(x)             ((BIN2BCD(x) << 20) & (RTAS_ODAY | RTAS_TDAY))
-
-/******************************************************************************
- *
- * RTCC_REG     RTC Control Register bit function.
- *
- ******************************************************************************/
-#define	RTCC_ENA                BIT0    /* Real Time Clock Enable           */
-#define	RTCC_12HR               BIT1    /* Time Format 1:12-hour 0:24-hour  */
-#define	RTCC_INTENA             BIT2    /* Sec/Min Interrupt Request Enable */
-#define	RTCC_INTTYPE            BIT3    /* Sec/Min Type Select
-										 * 0:Generate interrupt every minute.
-										 * 1:Generate interrupt every sec.  */
-#define	RTCC_CALIBRATION        BIT4    /* Calibration Enable               */
-#define	RTCC_CTRLMASK           0x1F    /* Bits 0-4                         */
-/* Bits 5-31: Reserved */
-
-/******************************************************************************
- *
- * RTCT_REG     RTC Current Time Register bits definitions.
- *
- ******************************************************************************/
-#define	RTCT_OSEC               (BIT0 | BIT1 | BIT2 | BIT3)       /* One digit */
-#define	RTCT_TSEC               (BIT4 | BIT5 | BIT6)              /* Ten digit */
-#define	RTCT_OMIN               (BIT7 | BIT8 | BIT9 | BIT10)
-#define	RTCT_TMIN               (BIT11 | BIT12 | BIT13)
-#define	RTCT_OHOUR              (BIT14 | BIT15 | BIT16 | BIT17)
-#define	RTCT_THOUR              (BIT18 | BIT19)
-#define	RTCT_WDAY               (BIT20 | BIT21 | BIT22)           /* wday      */
-/* Bits 23-30: Reserved */
-#define	RTCT_INVALID            BIT31                             /* 1:invalid */
-
-/* BCD2BIN macros
- * in  : RTCT_VAL
- * out : sec, min, hour, wday (in binary)
- */
-#define	RTCT_SEC(x)             BCD2BIN(((x) & (RTCT_OSEC | RTCT_TSEC)) >> 0)
-#define	RTCT_MIN(x)             BCD2BIN(((x) & (RTCT_OMIN | RTCT_TMIN)) >> 7)
-#define	RTCT_HOUR(x)            BCD2BIN(((x) & (RTCT_OHOUR | RTCT_THOUR)) >> 14)
-#define	RTCT_DAY(x)             BCD2BIN(((x) & (RTCT_WDAY))             >> 20)
-
-/******************************************************************************
- *
- * RTCD_REG     RTC Current Date Register bits definitions.
- *
- ******************************************************************************/
-#define	RTCD_ODAY               (BIT0 | BIT1 | BIT2 | BIT3)      /* One digit */
-#define	RTCD_TDAY               (BIT4 | BIT5)                    /* Ten digit */
-#define	RTCD_OMON               (BIT6 | BIT7 | BIT8 | BIT9)
-#define	RTCD_TMON               BIT10
-#define	RTCD_OYEAR              (BIT11 | BIT12 | BIT13 | BIT14)
-#define	RTCD_TYEAR              (BIT15 | BIT16 | BIT17 | BIT18)
-#define	RTCD_CEN                BIT19
-/* Bits 20-30: Reserved */
-#define	RTCD_INVALID            BIT31                            /* 1:invalid */
-
-/* BCD2BIN macros
- * in  : RTCD_VAL
- * out : mday, mon, year, century (in binary)
- */
-#define	RTCD_MDAY(x)            BCD2BIN(((x) & (RTCD_ODAY | RTCD_TDAY)) >> 0)
-#define	RTCD_MON(x)             BCD2BIN(((x) & (RTCD_OMON | RTCD_TMON)) >> 6)
-#define	RTCD_YEAR(x)            BCD2BIN(((x) & (RTCD_OYEAR | RTCD_TYEAR)) >> 11)
-#define	RTCD_CENT(x)            BCD2BIN(((x) & (RTCD_CEN))              >> 19)
-
-/******************************************************************************
- *
- * RTWS_REG     RTC Write Status Register bits definitions.
- *
- ******************************************************************************/
-#define	RTWS_TIMESET            BIT0    /* RTC Time Set Register Busy         */
-#define	RTWS_DATESET            BIT1    /* RTC Date Set Register Busy         */
-#define	RTWS_ALARMSET           BIT2    /* RTC Alarm Set Register Busy        */
-#define	RTWS_CONTROL            BIT3    /* RTC Control Register Busy          */
-#define	RTWS_TESTMODE           BIT4    /* RTC Test Mode Register Busy        */
-#define	RTWS_CALIBRATION        BIT5    /* RTC Time Calibration Register Busy */
-/* Bits 6-30: Reserved */
-
-/******************************************************************************
- *
- * RTTM_REG     RTC Test Mode Register bit definition.
- *
- ******************************************************************************/
-#define	RTTM_ENABLE             BIT0    /* RTC Test Mode Enable */
-#define	RTTM_TESTMASK           0x01    /* Bits 0 only now      */
-/* Bits 1-30: Reserved */
-
-/******************************************************************************
- *
- * RTTC_REG     RTC Time Calibration Register bits definitions.
- *
- ******************************************************************************/
-
-/* Calibration value Bit0-14 If all one(0x7FFF), means add or sub one second. */
-#define	RTTC_VALUEMASK          0x7FFF
-
-#define	RTTC_TYPE               BIT15
-#define	RTTC_CALIMASK           0xFFFF   /* Bits 0-15 */
-/* Bits 16-30: Reserved */
-
-/******************************************************************************
- *
- * RTIS_REG	RTC Interrupt Status bits definition.
- *
- ******************************************************************************/
-#define RTIS_ALARM              BIT0    /* RTC Alarm interrupt          */
-#define RTIS_UPDATE             BIT1    /* RTC sec/min update interrupt */
-/* Bits 2-31: Reserved */
-
-/******************************************************************************
- *
- * RTSR_REG	RTC RTC Status Register bits definition.
- *
- ******************************************************************************/
-#define RTSR_VAILD              BIT0    /* RTC Vaild Time status     */
-/* Bits 1-31: Reserved */
-
-#endif /* __WMT_RTC_H */
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_saradc.h b/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_saradc.h
deleted file mode 100755
index 676fb59b..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_saradc.h
+++ /dev/null
@@ -1,164 +0,0 @@
-/*++
-linux/drivers/input/keyboard/wmt_kpad.c
-
-Some descriptions of such software. Copyright (c) 2008  WonderMedia Technologies, Inc.
-
-This program is free software: you can redistribute it and/or modify it under the
-terms of the GNU General Public License as published by the Free Software Foundation,
-either version 2 of the License, or (at your option) any later version.
-
-This program is distributed in the hope that it will be useful, but WITHOUT
-ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-PARTICULAR PURPOSE.  See the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License along with
-this program.  If not, see <http://www.gnu.org/licenses/>.
-
-WonderMedia Technologies, Inc.
-10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
---*/
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/types.h>
-#include <linux/input.h>
-#include <linux/kernel.h>
-#include <linux/delay.h>
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/cpufreq.h>
-#include <linux/delay.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/errno.h>
-#include <asm/mach-types.h>
-#include <mach/hardware.h>
-#include <linux/suspend.h>
-
-
-/*=============================================================================
-//
-// WM3498 SARADC control registers.
-//
-// Registers Abbreviations:
-//
-// ADCCtrl0_REG  ADC Control0 Register.
-//
-// ADCCtrl1_REG  ADC Control1 Register.
-//
-// ADCCTRL2_REG  ADC Control2 Register.
-//
-//=============================================================================*/
-/*=============================================================================
-//
-// Address constant for each register.
-//
-//============================================================================*/
-#define ADCCtl0_ADDR	(ADC_BASE_ADDR + 0x00)
-#define ADCCtl1_ADDR	(ADC_BASE_ADDR + 0x04)
-#define ADCCtl2_ADDR	(ADC_BASE_ADDR + 0x08)
-
-/*=============================================================================
-//
-// Register pointer.
-//
-//=============================================================================*/
-#define ADCCtl0_REG		(REG32_PTR(ADCCtl0_ADDR))
-#define ADCCtl1_REG		(REG32_PTR(ADCCtl1_ADDR))
-#define ADCCtl2_REG		(REG32_PTR(ADCCtl2_ADDR))
-
-/*=============================================================================
-//
-// Register value.
-//
-//=============================================================================*/
-#define ADCCtl0_VAL		(REG32_VAL(ADCCtl0_ADDR))
-#define ADCCtl1_VAL		(REG32_VAL(ADCCtl1_ADDR))
-#define ADCCtl2_VAL		(REG32_VAL(ADCCtl2_ADDR))
-
-/*=============================================================================
-//
-// ADCCtl0_REG  ADC Control0 Register.
-//
-//=============================================================================*/
-#define TOutDlyMask         0xFFFF          /* Time Out Interrupt Delay Value */
-#define TOutDly(x)          ((x) & TOutDlyMask)
-#define ClrIntTOut          BIT16           /* ADC Timeout Interrupt CLEAR signal */
-#define ClrIntADC           BIT17           /* ADC sample point Conversion Finished Interrupt CLEAR signal */
-#define EndcIntEn           BIT18           /* ADC Conversion Finished Interrupt Enable. */
-#define TOutEn              BIT19           /* Time Out Interrupt Enable. */
-#define TempEn              BIT20           /* Manual output valid. */
-#define AutoMode            BIT21           /* Auto mode select. */
-#define SDataSel            BIT22           /* Serial DATA select. */
-#define DigClkEn            BIT23           /* Digital clock enable. */
-#define StartEn             BIT24           /* A/D conversion starts by enable. */
-#define AdcChSel            BIT25           /* Analog input channel selection */
-#define DBNSMASK            0x00000007      /* DBNS_SIZE bits can detect certain MSB bits comparison. */
-#define DbnsSize(x)         (((x) >>  26) & DBNSMASK)
-#define PMSel               BIT29           /* SAR ADC works in Power Mode. */
-#define PD                  BIT30           /* SAR ADC Power */
-#define TestMode            BIT31           /* SAR ADC Test Mode */
-
-/*=============================================================================
-//
-// ADCCtrl1_REG  ADC Control1 Register.
-//
-//=============================================================================*/
-#define SARCodeMask         0x1FF           /* SARADC data output. */
-#define SARCode(x)          ((x) & SARCodeMask)
-#define BufRd               BIT13           /* Buffer read signal */
-#define ValDetIntEn         BIT14           /* ADC value changing detection INTERRUPT ENABLE */
-#define ClrIntValDet        BIT15           /* ADC value changing detection Interrupt CLEAR signal */
-#define AutoTmpSlotMask     0xFFFF          /* This value controls SAMPLE RATE */
-#define AutoTmpSlot(x)      (((x) >> 16) & AutoTmpSlotMask)
-
-/*=============================================================================
-//
-// ADCCtrl2_REG  ADC Control1 Register.
-//
-//=============================================================================*/
-#define SARCodeVld          BIT0            /* SARADC valid signal. */
-#define BufEmpty            BIT8            /* Buffer empty signal */
-#define TestDataMask        0x7F            /* Test DATA */
-#define TestData(x)         (((x) >> 9) & TestDataMask)
-#define EndcIntStatus       BIT16           /* ADC Conversion Finished Interrupt status */
-#define BufDataMask         0x1FF           /* Buffer read data (changed value saved in buffer) */
-#define BufData(x)	        (((x) >> 17) & BufDataMask)
-#define TOutStatus          BIT26           /* Time Out interrupt status */
-#define ValDetIntStatus     BIT27           /* Value changing detection interrupt status */
-
-
-/*
- * Saradc register set structure
- */
-struct saradc_regs_s {
-	unsigned int volatile Ctr0;
-	unsigned int volatile Ctr1;
-	unsigned int volatile Ctr2;
-};
-
-
-/*
- * wmt keypad operation structure.
- */
-struct wmt_saradc_s {
-	/* Module reference counter */
-	unsigned int ref;
-
-	/* I/O Resource */
-	struct resource *res;
-
-	/* Saradc I/O register set. */
-	struct saradc_regs_s *regs;
-
-	/* Interrupt number and status counters. */
-	unsigned int irq;
-
-};
-
-extern int wmt_getsyspara(char *varname, unsigned char *varval, int *varlen);
-extern unsigned int wmt_read_oscr(void);
-
-MODULE_AUTHOR("WonderMedia Technologies, Inc.");
-MODULE_DESCRIPTION("WMT [generic keypad] driver");
-MODULE_LICENSE("GPL");
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_scc.h b/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_scc.h
deleted file mode 100755
index df51750e..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_scc.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*++
-linux/include/asm-arm/arch-wmt/wmt_scc.h
-
-Copyright (c) 2012  WonderMedia Technologies, Inc.
-
-This program is free software: you can redistribute it and/or modify it under the
-terms of the GNU General Public License as published by the Free Software Foundation,
-either version 2 of the License, or (at your option) any later version.
-
-This program is distributed in the hope that it will be useful, but WITHOUT
-ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-PARTICULAR PURPOSE.  See the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License along with
-this program.  If not, see <http://www.gnu.org/licenses/>.
-
-WonderMedia Technologies, Inc.
-10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
---*/
-
-
-/* Be sure that virtual mapping is defined right */
-#ifndef __ASM_ARCH_HARDWARE_H
-#error "You must include hardware.h, not wmt_scc.h"
-#endif
-
-#ifndef __WMT_SCC_H
-#define __WMT_SCC_H
-
-/*
- *   Refer SCC module register set.pdf ver. 0.15
- *
- */
-
-/*#define SYSTEM_CFG_CTRL_BASE_ADDR                       0xF8400000  // 64K */
-
-/*
- * Address
- */
-#define SCC_CHIP_ID_ADDR                    (0x0000+SYSTEM_CFG_CTRL_BASE_ADDR)
-
-/*
- * Registers
- */
-#define SCC_CHIP_ID_REG                     REG32_PTR(0x0000+SYSTEM_CFG_CTRL_BASE_ADDR)
-
-/*
- * VAL Registers
- */
-#define SCC_CHIP_ID_VAL                     REG32_VAL(0x0000+SYSTEM_CFG_CTRL_BASE_ADDR)
-
-/*
- *  SCC_CHIP_ID_REG
- *
- */
-#define SCC_ID_PART_NUMBER_MASK             0xFFFF0000
-#define SCC_ID_MAJOR_MASK                   0x0000FF00
-#define SCC_ID_METAL_MASK                   0x000000FF
-#define SCC_CHIP_ID_MASK                    0xFFFFFFFF
-#define SCC_ID_DEFAULT_PART_NUMBER          0x33000000
-#define SCC_ID_MAJOR_01                     0x00000100
-#define SCC_ID_METAL_01                     0x00000001
-#define SCC_CHIP_ID_01                      (SCC_ID_DEFAULT_PART_NUMBER|SCC_ID_MAJOR_01|SCC_ID_METAL_01)
-
-#endif /* __WMT_SCC_H */
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_sdmmc.h b/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_sdmmc.h
deleted file mode 100755
index 5b6dc653..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_sdmmc.h
+++ /dev/null
@@ -1,638 +0,0 @@
-/*++
-linux/include/asm-arm/arch-wmt/wmt_sdmmc.h
-
-Copyright (c) 2008  WonderMedia Technologies, Inc.
-
-This program is free software: you can redistribute it and/or modify it under the
-terms of the GNU General Public License as published by the Free Software Foundation,
-either version 2 of the License, or (at your option) any later version.
-
-This program is distributed in the hope that it will be useful, but WITHOUT
-ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-PARTICULAR PURPOSE.  See the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License along with
-this program.  If not, see <http://www.gnu.org/licenses/>.
-
-WonderMedia Technologies, Inc.
-10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
---*/
-
-
-/* Be sure that virtual mapping is defined right */
-#ifndef __ASM_ARCH_HARDWARE_H
-#error "You must include hardware.h, not wmt_sdmmc.h"
-#endif
-
-#ifndef	__WMT_SDMMC_H
-#define	__WMT_SDMMC_H
-
-#ifdef	__SDMMC_BASE
-#error "__SDMMC_BASE has already been defined in another file."
-#endif
-#ifdef	SD_SDIO_MMC_BASE_ADDR		/* from vt8500_mmap.h */
-#define	__SDMMC_BASE	SD0_SDIO_MMC_BASE_ADDR
-#else
-#ifdef ARL_EXTERNAL_SDHOST
-#define	__SDMMC_BASE	0xC0000000	/* 64K */
-#else
-#define	__SDMMC_BASE	0xC0000000	/* 64K */
-#endif
-#endif
-
-
-#define		MEM8(addr)		(*(volatile char *)(addr))
-#define		MEM32(addr)		(MEM16(addr+2)<<16 | MEM16(addr))
-#define		MEM16(addr)		(MEM8(addr+1)<<8 | MEM8(addr))
-
-/*
- *  SD/SDIO/MMC Host Control Register Offset
- */
-#define		_CTLR		0x00
-#define		_CMDI		0X01
-#define		_REST		0X02
-#define		_CMDA3		0X03
-#define		_CMDA2		0X04
-#define		_CMDA1		0X05
-#define		_CMDA0		0X06
-#define		_BUSM		0X07
-#define		_BLKL1		0X08
-#define		_BLKL0		0X09
-#define		_BLKC1		0X0A
-#define		_BLKC0		0X0B
-#define		_RESR		0X0C
-#define		_DATR		0X0D
-#define		_IMR0		0X0E
-#define		_IMR1		0X0F
-#define		_STR0		0X10
-#define		_STR1		0X11
-#define		_STR2		0X12
-#define		_STR3		0X13
-#define		_RTOR		0X14
-#define		_DTOR2		0X15
-#define		_DTOR1		0X16
-#define		_DTOR0		0X17
-#define		_CKDR		0X18
-#define		_DMAC		0X19
-
-/*
- * Address constant for each register.
- */
-#define	CTLR_ADDR	(__SDMMC_BASE+_CTLR)
-#define CMDI_ADDR	(__SDMMC_BASE+_CMDI)
-#define REST_ADDR	(__SDMMC_BASE+_REST)
-#define CMDA3_ADDR	(__SDMMC_BASE+_CMDA3)
-#define CMDA2_ADDR	(__SDMMC_BASE+_CMDA2)
-#define CMDA1_ADDR	(__SDMMC_BASE+_CMDA1)
-#define CMDA0_ADDR	(__SDMMC_BASE+_CMDA0)
-#define BUSM_ADDR	(__SDMMC_BASE+_BUSM)
-#define BLKL1_ADDR	(__SDMMC_BASE+_BLKL1)
-#define BLKL0_ADDR	(__SDMMC_BASE+_BLKL0)
-#define BLKC1_ADDR	(__SDMMC_BASE+_BLKC1)
-#define BLKC0_ADDR	(__SDMMC_BASE+_BLKC0)
-#define RESR_ADDR	(__SDMMC_BASE+_RESR)
-#define DATR_ADDR	(__SDMMC_BASE+_DATR)
-#define IMR0_ADDR	(__SDMMC_BASE+_IMR0)
-#define IMR1_ADDR	(__SDMMC_BASE+_IMR1)
-#define STR0_ADDR	(__SDMMC_BASE+_STR0)
-#define STR1_ADDR	(__SDMMC_BASE+_STR1)
-#define STR2_ADDR	(__SDMMC_BASE+_STR2)
-#define STR3_ADDR	(__SDMMC_BASE+_STR3)
-#define RTOR_ADDR	(__SDMMC_BASE+_RTOR)
-#define DTOR2_ADDR	(__SDMMC_BASE+_DTOR2)
-#define DTOR1_ADDR	(__SDMMC_BASE+_DTOR1)
-#define DTOR0_ADDR	(__SDMMC_BASE+_DTOR0)
-#define CKDR_ADDR	(__SDMMC_BASE+_CKDR)
-#define DMAC_ADDR	(__SDMMC_BASE+_DMAC)
-
-/*
- * Register pointer.
- */
-#define CTLR_REG	(REG8_PTR(CTLR_ADDR))
-#define CMDI_REG	(REG8_PTR(CMDI_ADDR))
-#define REST_REG	(REG8_PTR(REST_ADDR))
-#define CMDA3_REG	(REG8_PTR(CMDA3_ADDR))
-#define CMDA2_REG	(REG8_PTR(CMDA2_ADDR))
-#define CMDA1_REG	(REG8_PTR(CMDA1_ADDR))
-#define CMDA0_REG	(REG8_PTR(CMDA0_ADDR))
-#define BUSM_REG	(REG8_PTR(BUSM_ADDR))
-#define BLKL1_REG	(REG8_PTR(BLKL1_ADDR))
-#define BLKL0_REG	(REG8_PTR(BLKL0_ADDR))
-#define BLKC1_REG	(REG8_PTR(BLKC1_ADDR))
-#define BLKC0_REG	(REG8_PTR(BLKC0_ADDR))
-#define RESR_REG	(REG8_PTR(RESR_ADDR))
-#define DATR_REG	(REG8_PTR(DATR_ADDR))
-#define IMR0_REG	(REG8_PTR(IMR0_ADDR))
-#define IMR1_REG	(REG8_PTR(IMR1_ADDR))
-#define STR0_REG	(REG8_PTR(STR0_ADDR))
-#define STR1_REG	(REG8_PTR(STR1_ADDR))
-#define STR2_REG	(REG8_PTR(STR2_ADDR))
-#define STR3_REG	(REG8_PTR(STR3_ADDR))
-#define RTOR_REG	(REG8_PTR(RTOR_ADDR))
-#define DTOR2_REG	(REG8_PTR(DTOR2_ADDR))
-#define DTOR1_REG	(REG8_PTR(DTOR1_ADDR))
-#define DTOR0_REG	(REG8_PTR(DTOR0_ADDR))
-#define CKDR_REG	(REG8_PTR(CKDR_ADDR))
-#define DMAC_REG	(REG8_PTR(DMAC_ADDR))
-
-/*
- * SDH Command Index value
- */
-#define CMD(x) (x)
-#define ACMD(x) (x)
-
-
-/*
- * SDH DATA STRUCTURES
- */
-#define SECTOR_SIZE	512
-#define TEST_FILE_SIZE	32768
-
-/*
- * SDH Parameter Base Address Value
- *
- * Clark - I had to slow the AHB to 12 MHz to be able to communicate with the
- * xilinx part on the external AHB. This caused the ddr to not work properly.
- * I then changed the board to use the SDRAM and moved these storage locations
- * into SDRAM
- */
-#define BLOCK_ORG_BASE		0x30000000
-#define BLOCK_TMP_BASE		0x30002000
-
-/*
-#define BLOCK_TMP_BASE		0x03000000
-#define FAT_TMP_BASE		0x03100000
-#define FAT_ORG_BASE		0x03200000
-#define ROOT_TMP_BASE		0x03300000
-#define ROOT_ORG_BASE		0x03400000
-#define TEST_FILE_BASE		0x03500000
-#define TEST_FILE_TMP_BASE 	0x03600000
-*/
-
-
-/*
- * SD Host Register Bit Fields
- */
-
-/* Control Register */
-#define STR	        BIT0
-#define SPISTP      BIT1
-#define RXTX        BIT2
-#define FFRST       BIT3
-#define CT          (BIT4 | BIT5 | BIT6 | BIT7)
-
-/* Command Index Register */
-
-/* Response Type Register */
-#define RT          (BIT0 | BIT1 | BIT2 | BIT3)
-#define RY          BIT4
-
-/* Command Argument Register 0,1,2,3 */
-
-/* Bus Mode Register */
-#define SPI         BIT0
-#define WB          BIT1
-#define RW          BIT2
-#define SPICRC      BIT3
-#define CST         BIT4
-#define SPICS       BIT5
-#define SDPWR       BIT6
-#define SFTRST      BIT7
-
-
-/* Block Length Register 0,1 */
-#define BS_L        (BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7)
-#define BS_H        (BIT8 | BIT9 | BIT10)
-#define CFD         BIT4
-#define INTEN       BIT7
-
-
-/* Block Count Register 0,1 */
-
-
-/* Response Register */
-
-
-/* Data Register */
-
-
-/* Interrupt Mask Register 0 */
-#define THIE        BIT0
-#define TEIE        BIT1
-#define TAIE        BIT2
-#define RHIE        BIT3
-#define RFIE        BIT4
-#define RPIE        BIT5
-#define CDIE        BIT6
-#define SIIE        BIT7
-
-
-/* Interrupt Mask Register 1 */
-#define IOIE        BIT0
-#define CRIE        BIT1
-#define RAIE        BIT2
-#define DDIE        BIT3
-#define DTIE        BIT4
-#define SCIE        BIT5
-#define RCIE        BIT6
-#define WCIE        BIT7
-
-
-/* SD Status Register 0 */
-#define TH          BIT0
-#define TE          BIT1
-#define TA          BIT2
-#define RH          BIT3
-#define RF          BIT4
-#define PP          BIT5
-#define SD_CD       BIT6
-#define SI          BIT7
-
-
-/* SD Status Register 1 */
-#define SD_IO       BIT0
-#define CR          BIT1
-#define RA          BIT2
-#define DD          BIT3
-#define DT          BIT4
-#define SC          BIT5
-#define RC          BIT6
-#define WC          BIT7
-
-
-/* SD Status Register 2 */
-#define CRCW        (BIT0 | BIT1 | BIT2)
-#define CB          BIT4
-#define DB          BIT5
-#define CF          BIT6
-
-
-/* SD Status Register 3 */
-#define SPIE        BIT0
-#define CCE         BIT1
-#define CEF         BIT2
-#define OOR         BIT3
-#define SPIRE       BIT4
-#define REIE        BIT5
-
-
-/* Response Time Out Register */
-#define RESTO       (BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7)
-
-
-/* Data Time Out Register 0,1,2 */
-#define TMAX        (BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7)
-
-
-/* Clock Divisor Register */
-#define DIV         (BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7)
-
-
-/* DMA Control Register */
-#define DMA         BIT0
-#define DEM         BIT1
-#define LCNT        (BIT2 | BIT3)
-#define DCNT        (BIT4 | BIT5 | BIT6 | BIT7)
-
-/*
- * DMAC Registers
- */
-
-#define SAR_OFFSET          0x10	/* size 32 */
-#define DAR_OFFSET          0x10
-#define TCR_OFFSET          0x10
-#define CCR_OFFSET          0x10
-#define CTR_OFFSET          0x01	/* size 8 */
-#define CSR_OFFSET          0x01
-
-#define DMA_SAR_0_VAL(ch)	REG32_VAL(DMA_SAR_CH0_0_ADDR+SAR_OFFSET*ch)
-#define DMA_DAR_0_VAL(ch)	REG32_VAL(DMA_DAR_CH0_0_ADDR+DAR_OFFSET*ch)
-#define DMA_TCR_0_VAL(ch)	REG32_VAL(DMA_TCR_CH0_0_ADDR+TCR_OFFSET*ch)
-#define DMA_CCR_0_VAL(ch)	REG32_VAL(DMA_CCR_CH0_ADDR+CCR_OFFSET*ch)
-#define DMA_CTR_VAL(ch)		REG8_VAL(DMA_CTR_CH0_ADDR+CTR_OFFSET*ch)
-#define DMA_CSR_VAL(ch)		REG8_VAL(DMA_CSR_CH0_ADDR+CSR_OFFSET*ch)
-#define DMA_SAR_1_VAL(ch)	REG32_VAL(DMA_SAR_CH0_1_ADDR+SAR_OFFSET*ch)
-#define DMA_DAR_1_VAL(ch)	REG32_VAL(DMA_DAR_CH0_1_ADDR+DAR_OFFSET*ch)
-#define DMA_TCR_1_VAL(ch)	REG32_VAL(DMA_TCR_CH0_1_ADDR+TCR_OFFSET*ch)
-
-//#define SD_BASE_ADDR        0xD800A000
-#define SD_FALSE            0
-#define SD_TRUE             1
-
-#define	SD1_0               0x00
-#define	SD1_1               0x01
-#define	SD2_0               0x02
-
-
-
-/*
- * SD command definition
- */
-
-#define	GO_IDLE_STATE           0
-#define	SEND_OP_COND            1   /*for MMC */
-#define	ALL_SEND_CID            2
-#define	SEND_RELATIVE_ADDR      3
-#define	SET_RELATIVE_ADDR       3   /*for MMC1 */
-#define	SET_DSR                 4
-#define	SELECT_DESELECT_CARD    7
-#define	SEND_IF_COND            8	/*for SD2.0  */
-#define	SEND_EXT_CSD            8	/*for MMC  */
-#define	SEND_CSD                9
-#define	SEND_CID                10
-/*#define READ_DAT_UNTIL_STOP     11  */
-#define	STOP_TRANSMISSION       12
-#define	SEND_STATUS             13
-/*#define SET_BUS_WIDTH_REGISTER  14 */
-#define	GO_INACTIVE_STATE       15
-#define	SET_BLOCKLEN            16
-#define	READ_SINGLE_BLOCK       17
-#define	READ_MULTIPLE_BLOCK     18
-/*#define WRITE_DAT_UNTIL_STOP    20  */
-#define	WRITE_SINGLE_BLOCK      24
-#define	WRITE_MULTIPLE_BLOCK    25
-/*#define PROGRAM_CID             26 */
-#define	PROGRAM_CSD             27
-#define	SET_WRITE_PROT          28
-#define	CLR_WRITE_PROT          29
-#define	SEND_WRITE_PROT         30
-#define	ERASE_START             32
-#define	ERASE_END               33
-/*#define UNTAG_SECTOR            34  */
-/*#define TAG_ERASE_GROUP_START   35  */
-/*#define TAG_ERASE_GROUP_END     36  */
-/*#define UNTAG_ERASE_GROUP       37  */
-#define	ERASE_GO                38
-/*for SPI mode  */
-#define	READ_OCR                58   /*for SPI */
-#define	CRC_ON_OFF              59
-#define	APP_CMD                 55
-/*APP command */
-#define	SET_BUS_WIDTH           6
-#define	SD_STATUS               13
-#define	SD_NUM_WR_BLOCKS        22
-#define	SD_WR_BLK_ERASE_COUNT   23
-#define	SD_APP_OP_COND          41
-#define	SD_SET_CLR_CARD_DETECT  42
-#define	SD_SEND_SCR             51
-
-
-/* SD Response types  */
-#define	R0          0       /* NONE response */
-#define	R1          1       /* Basic response format  */
-#define	R2          2       /* R2 response. Used by ALL_SEND_CID(CMD2),  */
-							/* SEND_CID(CMD10) and SEND_CSD(CMD9) */
-#define	R3          3       /* R3 response. Used by SEND_APP_OP_COND(ACMD41)  */
-#define	R6          6       /* R6 response. Used by SEND_RELATIVE_ADDR(CMD3)  */
-#define	R1b         9
-/*response format in SPI mode */
-#define	SPI_R1      7       /* Format R1. used in SPI mode  */
-#define	SPI_R2      8       /* Format R2. used in SPI mode, SEND_STATUS, SD_STATUS  */
-/*#define    	SPI_R3	9      // Format R3. used in SPI mode, READ_OCR      */
-
-
-/*
- *  32bit status in Response
- */
-#define		OUT_OF_RANGE_ERROR      0x80000000      /* Bit 31 */
-#define		ADDRESS_ERROR           0x40000000      /* Bit 30 */
-#define		BLOCK_LEN_ERROR         0x20000000      /* Bit 29 */
-#define		ERASE_SEQ_ERROR         0x10000000      /* Bit 28 */
-#define		ERASE_PARAM_ERROR       0x08000000      /* Bit 27 */
-#define		WP_VIOLATION            0x04000000      /* Bit 26 */
-#define		CARD_IS_LOCKED          0x02000000      /* Bit 25 */
-#define		LOCK_UNLOCK_FAILED      0x01000000      /* Bit 24 */
-#define		CMD_CRC_ERROR           0x00800000      /* Bit 23 */
-#define		ILLEAGL_COMMAND         0x00400000      /* Bit 22 */
-#define		CARD_ECC_FAILED         0x00200000      /* Bit 21 */
-#define		CC_ERROR                0x00100000      /* Bit 20 */
-#define		EERROR                  0x00080000      /* Bit 19 */
-#define		UNDERRUN                0x00040000      /* Bit 18 */
-#define		OVERRUN                 0x00020000      /* Bit 17 */
-#define		CIDCSD_OVERWRITE        0x00010000      /* Bit 16 */
-#define		WP_ERASE_SKIP           0x00008000      /* Bit 15 */
-#define		CARD_ECC_DISABLED       0x00004000      /* Bit 14 */
-#define		ERASE_RESET             0x00002000      /* Bit 13 */
-#define		READY_FOR_DATA          0x00000100      /* Bit 8  */
-#define		APPL_CMD                0x00000020      /* Bit 5  */
-#define		AKE_SEQ_ERROR           0x00000008      /* Bit 3  */
-
-/* current status bit12 ~ bit9 */
-#define		IDLE                    0x00000000
-#define		READY                   0x00000200
-#define		IDENT                   0x00000400
-#define		STBY                    0x00000600
-#define		TRAN                    0x00000800
-#define		DATA                    0x00000A00
-#define		RCV                     0x00000C00
-#define		PRG                     0x00000E00
-#define		DIS                     0x00001000
-
-/*bit definition for SD controller register */
-
-/* 0x0 Control register */
-#define		FIFO_RESET				0x08
-#define		CMD_START				0x01
-#define		CMD_READ				0x00
-#define		CMD_WRITE				0x04
-#define		CMD_SWRITE				0x10
-#define		CMD_SREAD				0x20
-#define		CMD_MWRITE				0x30
-#define		CMD_MREAD				0x40
-
-/*0x08 BusMode register */
-#define		SOFT_RESET				0x80
-#define		SD_POWER	  			0x40
-#define		SPI_CS		  			0x20
-#define		SD_OFF					0x10
-#define		FOURBIT_MODE			0x02
-#define 	SPI_MODE				0x01
-#define		SD_MODE					0x00
-
-
-/*0x0C BlkLen */
-#define		INT_ENABLE				0x80
-#define		DATA3_CD	  			0x40
-#define		GPI_CD		  			0x20
-#define		CD_POL_HIGH				0x10
-#define		CRCERR_ABORT			0x08 /*abort multiple-blk-transfer when CRC-Err  */
-
-
-/*0x24 IntMask0 */
-#define DI_INT_EN             		0x80
-#define CD_INT_EN             		0x40
-#define BLK_TRAN_DONE_INT_EN  		0x20
-#define MBLK_TRAN_DONE_INT_EN 		0x10
-
-/*0x25 IntMask0 */
-#define WCRC_ERR_INT_EN             0x80
-#define RCRC_ERR_INT_EN             0x40
-#define RESCRC_ERR_INT_EN           0x20
-#define DATA_TOUT_INT_EN            0x10
-#define MBLK_AUTO_STOP_INT_EN       0x08
-#define CMD_RES_TOUT_INT_EN         0x04
-#define CMD_RES_TRAN_DONE_INT_EN    0x02
-
-/*0x28 Status0 register */
-#define		DEVICE_INS				0x80
-#define		CARD_DETECT				0x40
-#define		BLK_DONE				0x20
-#define		MBLK_DONE				0x10
-#define		CD_GPI					0x08
-#define		CD_DATA3				0x04
-#define		Write_Protect			0x02
-
-
-/*0x29 Status1 register */
-#define		WCRC_ERR				0x80
-#define		RCRC_ERR				0x40
-#define		RSP_CRC_ERR				0x20
-#define		DATA_TIMEOUT			0x10
-#define		AUTOSTOP_DONE			0x08
-#define		RSP_TIMEOUT				0x04
-#define		CMDRSP_DONE				0x02
-#define		SDIO_INT				0x01
-
-/*0x2A Status2 register */
-#define		DIS_FORCECLK			0x80
-#define		DATARSP_BUSY			0x20
-#define		CMD_RES_BUSY  			0x10
-
-/*0x30 Clock register */
-#define		Clk_375					0x00
-#define		Clk_10					0x01
-#define		Clk_12					0x02
-#define		Clk_15					0x03
-#define		Clk_20					0x04
-#define		Clk_24					0x05
-#define		Clk_30					0x06
-#define		Clk_40					0x07
-
-/*0x34 Extension Control register */
-#define		ArgShift				0x02
-#define		AutoStop				0x01
-
-/*return sdstatus */
-#define 	CMD_OK					0x00
-#define		CMDRSP_TOUT				0x01
-#define		RSP_CRCERR				0x02
-#define 	APPCMD_FAIL				0x03
-#define		DATA_TOUT				0x04
-#define		WRITE_CRCERR			0x05
-#define		READ_CRCERR				0x06
-#define		TYPE_UNKNOWN			0x07
-#define		NOCARD_INSERT			0x08
-#define		POWER_FAIL				0x09
-#define		READ_CID_ERR			0x0a
-#define		READ_RCA_ERR			0x0b
-#define		SET_RCA_ERR				0x0c
-#define		READ_CSD_ERR			0x0d
-#define		SELECT_CARD_ERR			0x0e
-#define		READ_SCR_ERR			0x0f
-#define		SET_BUSWIDTH_ERR		0x10
-#define		SET_BLKLEN_ERR			0x11
-#define		STOP_FAIL				0x12
-#define		MBLK_FAIL				0x13
-#define		TURE_T					0x14
-#define		FALSE_F					0x15
-
-
-/*
- * SD TPE DMA
- */
-
-/*
- *   Refer AHB DMA Controller for TPE Peripherals
- */
-//#define SD_DMA_BASE_ADDR			0xD800A100
-
-
-/*SD DMA channel configuration registers -- CCR */
-#define SD_DMA_CCR_TR_SIZE_8                   0x00000000      /* [1:0] -- desired_transfer_size 8-bit */
-#define SD_DMA_CCR_TR_SIZE_16                  0x00000001      /* [1:0] -- desired_transfer_size 16-bit */
-#define SD_DMA_CCR_TR_SIZE_32                  0x00000002      /* [1:0] -- desired_transfer_size 32-bit */
-#define SD_DMA_CCR_TRANSFER_SIZE_MASK          0x00000003
-/* Reserved [3:2] */
-#define SD_DMA_CCR_BURST_SINGLE                0x00000000      /* [5:4] -- burst_length single */
-#define SD_DMA_CCR_BURST_INC4                  0x00000010      /* [5:4] -- burst_length INC4   */
-#define SD_DMA_CCR_BURST_INC8                  0x00000020      /* [5:4] -- burst_length INC8   */
-/* Reserved [7:6] */
-#define SD_DMA_CCR_PROT_OP_FETCH               0x00000000      /* [11:08] */
-#define SD_DMA_CCR_PROT_DATA_ACCESS            0x00000100
-#define SD_DMA_CCR_PROT_USER_ACCESS            0x00000000
-#define SD_DMA_CCR_PROT_PRIV_ACCESS            0x00000200
-#define SD_DMA_CCR_PROT_NOT_BUF                0x00000000
-#define SD_DMA_CCR_PROT_BUF                    0x00000400
-#define SD_DMA_CCR_PROT_NOT_CACHE              0x00000000
-#define SD_DMA_CCR_PROT_CACHE                  0x00000800
-#define SD_DMA_CCR_SRC_NON_INC                 0x00000000      /* [12:12] -- Source address mode */
-#define SD_DMA_CCR_SRC_INC                     0x00001000      /* [12:12] -- Source address mode */
-#define SD_DMA_CCR_DES_INC                     0x00001000
-
-/* Reserved [15:13] */
-#define SD_DMA_CCR_SYS_TO_MEM                  0x00000000
-#define SD_DMA_CCR_MEM_TO_SYS                  0x00010000      /* [16:16] -- SD DMA transfer direction */
-/* Reserved [19:17] */
-#define SD_DMA_CCR_TC_INT_EN                   0x00100000      /* [20:20] -- Terminal Count Inttrupt Enable */
-#define SD_DMA_CCR_TR_COMPLETE_INT_EN          0x00200000      /* [21:21] -- Transfer Complete Inttrupt Enable */
-#define SD_DMA_CCR_AHB_ERR_INT_EN              0x00400000      /* [22:22] -- AHB Bus Error Inttrupt Enable */
-#define SD_DMA_CCR_FIFO_EMPTY_INT_EN           0x00800000      /* [23:23] -- FIFO Empty Inttrupt Enable */
-
-#define SD_DMA_CCR_ALL_INT_EN                  0x00F00000
-#define SD_DMA_CCR_ALL_INT_DIS                 0x00000000
-/* Reserved [31:24] */
-
-/*SD DMA channel control registers -- CTR */
-
-/* Reserved [07:05] */
-#define SD_DMA_CTR_SW_REQ_EN                      0x10            /* [04:04] */
-#define SD_DMA_CTR_SW_REQ_DIS                     0x00
-
-/* Reserved [03:01] */
-#define SD_DMA_CTR_CH_EN                          0x01            /* [00:00] */
-#define SD_DMA_CTR_CH_DIS                         0x00            /* [00:00] */
-
-/*SD DMA channel status registers -- CSR */
-#define SD_DMA_CSR_DMA_REQ                        0x80            /* [07:07] */
-/* Reserved [06:04] */
-#define SD_DMA_CSR_FIFO_EMPTY_INT                 0x08            /* [03:03] */
-#define SD_DMA_CSR_FIFO_EMPTY_INT_WRITE_CLEAR     0x08            /* [03:03] */
-#define SD_DMA_CSR_AHB_BUS_ERR                    0x04            /* [02:02] */
-#define SD_DMA_CSR_AHB_BUS_ERR_WRITE_CLEAR        0x04            /* [02:02] */
-/* For USB use [01:01] */
-#define SD_DMA_CSR_TC                             0x01            /* [00:00] */
-#define SD_DMA_CSR_TC_WRITE_CLEAR                 0x01
-
-#define SD_DMA_CSR_ALL_SET_CLEAR                  0x0F
-
-/*SD DMA global control registers -- GCR */
-
-/* Reserved [31:25] */
-#define SD_DMA_GCR_MANUAL_FLUSH_EN             0x01000000      /* [24:24] */
-#define SD_DMA_GCR_MANUAL_FLUAH_DIS            0x00000000      /* [24:24] */
-/* Reserved [23:17] */
-#define SD_DMA_GCR_FLUSH_FIFO                  0x00010000      /* [16:16] */
-#define SD_DMA_GCR__FLUSH_SELF_CLEAR           0x00000000      /* [16:16] */
-/* Reserved [15:9] */
-#define SD_DMA_GCR_GINT_EN                     0x00000100      /* [08:08] */
-#define SD_DMA_GCR_GINT_DIS                    0x00000000      /* [08:08] */
-/* Reserved [07:01] */
-#define SD_DMA_GCR_GDMA_EN                     0x00000001      /* [00:00] */
-#define SD_DMA_GCR_GDMA_DIS                    0x00000000      /* [00:00] */
-
-/* SD DMA global status registers -- GSR */
-
-/* Reserved [31:17] */
-#define SD_DMA_GSR_FIFO_EMPTY                  0x00010000      /* [16:16] */
-/* Reserved [15:9] */
-#define SD_DMA_GSR_CH0_EN                      0x00000100      /* [08:08] */
-/* Reserved [7:1] */
-#define SD_DMA_GSR_CH0_AGGR_STATUS             0x00000001      /* [00:00] */
-
-/* SD DMA global purpose registers -- GPR */
-/* For USB use */
-
-#endif	/* __WMT_SDMMC_H */
-
-
-
-
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_secure.h b/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_secure.h
deleted file mode 100755
index c56ff49a..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_secure.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*++
-linux/arch/arm/mach-wmt/include/mach/wmt_secure.h
-
-Copyright (c) 2013  WonderMedia Technologies, Inc.
-
-This program is free software: you can redistribute it and/or modify it under the
-terms of the GNU General Public License as published by the Free Software Foundation,
-either version 2 of the License, or (at your option) any later version.
-
-This program is distributed in the hope that it will be useful, but WITHOUT
-ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-PARTICULAR PURPOSE.  See the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License along with
-this program.  If not, see <http://www.gnu.org/licenses/>.
-
-WonderMedia Technologies, Inc.
-10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
---*/
-
-#ifndef WMT_ARCH_WMT_SECURE_H
-#define WMT_ARCH_WMT_SECURE_H
-
-/* Monitor error code */
-#define  API_HAL_RET_VALUE_NS2S_CONVERSION_ERROR	0xFFFFFFFE
-#define  API_HAL_RET_VALUE_SERVICE_UNKNWON		0xFFFFFFFF
-
-/* HAL API error codes */
-#define  API_HAL_RET_VALUE_OK		0x00
-#define  API_HAL_RET_VALUE_FAIL		0x01
-
-/* Secure HAL API flags */
-#define FLAG_START_CRITICAL		0x4
-#define FLAG_IRQFIQ_MASK		0x3
-#define FLAG_IRQ_ENABLE			0x2
-#define FLAG_FIQ_ENABLE			0x1
-#define NO_FLAG				0x0
-
-/* Maximum Secure memory storage size */
-#define WMT_SECURE_RAM_STORAGE	(88 * SZ_1K)
-
-/* Secure low power HAL API index */
-#define WMT4_HAL_SAVESECURERAM_INDEX	0x1a
-#define WMT4_HAL_SAVEHW_INDEX		0x1b
-#define WMT4_HAL_SAVEALL_INDEX		0x1c
-#define WMT4_HAL_SAVEGIC_INDEX		0x1d
-
-/* Secure Monitor mode APIs */
-#define WMT_SMC_CMD_PL310CTRL           41
-#define WMT_SMC_CMD_PL310AUX            42
-#define WMT_SMC_CMD_PL310FILTER_START   43
-#define WMT_SMC_CMD_PL310FILTER_END     44
-#define WMT_SMC_CMD_PL310TAG_LATENCY    45
-#define WMT_SMC_CMD_PL310DATA_LATENCY   46
-#define WMT_SMC_CMD_PL310DEBUG          47
-#define WMT_SMC_CMD_PL310PREFETCH       48
-#define WMT_SMC_CMD_PL310POWER          49
-
-#define WMT_SMC_CMD_LOGBUFOK            50
-#define WMT_SMC_CMD_PRINTK_RET          51
-#define WMT_SMC_CMD_LOGBUF_ADDR         52
-
-#define WMT_SMC_CMD_IRQOK               53
-#define WMT_SMC_CMD_IRQ_RET             54
-
-#define WMT_SMC_CMD_DEVICE_SUSPEND      55
-#define WMT_SMC_CMD_DEVICE_RESUME       56
-
-#define WMT_SMC_CMD_SECURE_GIC_CTL      57
-
-#define WMT_SMC_CMD_SECURE_SUSPEND      58
-
-
-
-
-#define GIC_ENABLE     (1 << 0)
-#define GIC_DISABLE    (1 << 1)
-#define GIC_SUSPEND    (1 << 2)
-#define GIC_RESUME     (1 << 3)
-
-
-/* Secure PPA(Primary Protected Application) APIs */
-#define WMT4_PPA_L2_POR_INDEX		0x23
-#define WMT4_PPA_CPU_ACTRL_SMP_INDEX	0x25
-
-#ifndef __ASSEMBLER__
-
-extern u32 wmt_secure_dispatcher(u32 idx, u32 flag, u32 nargs,
-				u32 arg1, u32 arg2, u32 arg3, u32 arg4);
-
-extern phys_addr_t wmt_secure_ram_mempool_base(void);
-extern unsigned int wmt_smc(u32 fn, u32 arg);
-
-#endif /* __ASSEMBLER__ */
-#endif /* WMT_ARCH_WMT_SECURE_H */
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_sf.h b/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_sf.h
deleted file mode 100755
index 7d2130a4..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_sf.h
+++ /dev/null
@@ -1,138 +0,0 @@
-/*++
-linux/include/asm-arm/arch-wmt/wmt_sf.h
-
-Copyright (c) 2008  WonderMedia Technologies, Inc.
-
-This program is free software: you can redistribute it and/or modify it under the
-terms of the GNU General Public License as published by the Free Software Foundation,
-either version 2 of the License, or (at your option) any later version.
-
-This program is distributed in the hope that it will be useful, but WITHOUT
-ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-PARTICULAR PURPOSE.  See the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License along with
-this program.  If not, see <http://www.gnu.org/licenses/>.
-
-WonderMedia Technologies, Inc.
-10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
---*/
-
-/* Be sure that virtual mapping is defined right */
-#ifndef __ASM_ARCH_HARDWARE_H
-#error "You must include hardware.h, not wmt_sf.h"
-#endif
-
-#ifndef __WMT_SF1_H__
-#define __WMT_SF1_H__
-
-
-/******************************************************************************
- * memory use macro
- ******************************************************************************/
-#define MEM8(addr)		(*(volatile char *)(addr))
-#define MEM32(addr)		(MEM16(addr+2)<<16 | MEM16(addr))
-#define MEM16(addr)		(MEM8(addr+1)<<8 | MEM8(addr))
-
-#define SF_BASE_ADDR SF_MEM_CTRL_CFG_BASE_ADDR
-
-
-/*Chip select 0-1 configuration register, 0x0 & 0x8 */
-#define SF_START_ADDR          0xFF800000 /* [36:16] */
-#define SF_MEM_SIZE_8M         0x00000800 /* [11:8]  */
-
-/*SPI interface configuration register, 0x40 */
-#define SF_PDWN_DELY           0x0  /* [31:28] */
-#define SF_RES_DELY            0x0  /* [27:24] */
-#define SF_CS_DELY             0x0  /* [18:16] */
-#define SF_PROG_CMD_MOD_EN     0x40 /* [6:6] */
-#define SF_PROG_CMD_MOD_DIS    0x0  /* [6:6] */
-#define SF_USR_WR_CMD_MOD_EN   0x20 /* [5:5] */
-#define SF_USR_WR_CMD_MOD_DIS  0x0  /* [5:5] */
-#define SF_USR_RD_CMD_MOD_EN   0x10 /* [4:4] */
-#define SF_USR_RD_CMD_MOD_DIS  0x0  /* [4:4] */
-#define SF_ADDR_WIDTH_24       0x0  /* [0:0] */
-#define SF_ADDR_WIDTH_32       0x1  /* [0:0] */
-/*SPI flash read/write control register, 0x50 */
-#define SF_ID_RD               0x10 /* [4:4] */
-#define SF_STATUS_RD           0x0  /* [4:4] */
-#define SF_RD_SPD_FAST         0x1  /* [0:0] */
-#define SF_RD_SPD_NOR          0x0  /* [0:0] */
-
-/*SPI flash write enable control register, 0x60 */
-#define SF_CS1_WR_EN           0x2  /* [1:1] */
-#define SF_CS1_WR_DIS          0x0  /* [1:1] */
-#define SF_CS0_WR_EN           0x1  /* [0:0] */
-#define SF_CS0_WR_DIS          0x0  /* [0:0] */
-
-/*SPI flash erase control register, 0x70 */
-#define SF_SEC_ER_EN           0x8000 /* [15:15] */
-#define SF_SEC_ER_DIS          0x0  /* [15:15] */
-#define SF_CHIP_ER_EN          0x1  /* [0:0] */
-#define SF_CHIP_ER_DIS         0x0  /* [0:0] */
-
-/*SPI flash erase start address register, 0x74 */
-#define SF_ER_START_ADDR       0x0  /* [31:16] */
-#define CHIP_ER_CS1            0x2  /* [1:1] */
-#define CHIP_ER_CS0            0x1  /* [0:0] */
-
-/*SPI flash error status register, 0x80 */
-#define SF_WR_PROT_ERR         0x20 /* [5:5] */
-#define SF_MEM_REGION_ERR      0x10 /* [4:4] */
-#define SF_PWR_DWN_ACC_ERR     0x8  /* [3:3] */
-#define SF_PCMD_OP_ERR         0x4  /* [2:2] */
-#define SF_PCMD_ACC_ERR        0x2  /* [1:1] */
-#define SF_MASLOCK_ERR         0x1  /* [0:0] */
-/*SPI power down control register, 0x180 & 0x190 */
-#define PWR_DWN_EN             0x1  /* [0:0] */
-#define PWR_DWN_DIS            0x0  /* [0:0] */
-/*SPI programmable command mode control register, 0x200 */
-#define SF_TX_DATA_SIZE        0x0  /* MACRO [30:24] */
-#define SF_RX_DATA_SIZE        0x0  /* MACRO [22:16] */
-#define SF_CMD_CS1             0x2  /* MACRO [1:1] */
-#define SF_CMD_CS0             0x0  /* MACRO [1:1] */
-#define SF_CMD_EN              0x1  /* [0:0] */
-#define SF_CMD_DIS             0x0  /* [0:0] */
-/*SPI user command value register, 0x210 */
-#define SF_USR_WR_CMD          0x0  /* MACRO [23:16] */
-#define SF_USR_RD_CMD          0x0  /* MACRO [7:0] */
-
-
-#define CHIP_SEL_0_CFG_ADDR		(SF_BASE_ADDR + 0x00)
-#define CHIP_SEL_1_CFG_ADDR		(SF_BASE_ADDR + 0x08)
-#define SPI_INTF_CFG_ADDR		(SF_BASE_ADDR + 0x40)
-#define SPI_RD_WR_CTR_ADDR		(SF_BASE_ADDR + 0x50)
-#define SPI_WR_EN_CTR_ADDR		(SF_BASE_ADDR + 0x60)
-#define SPI_ER_CTR_ADDR			(SF_BASE_ADDR + 0x70)
-#define SPI_ER_START_ADDR_ADDR	(SF_BASE_ADDR + 0x74)
-#define SPI_ERROR_STATUS_ADDR	(SF_BASE_ADDR + 0x80)
-#define SPI_MEM_0_SR_ACC_ADDR	(SF_BASE_ADDR + 0x100)
-#define SPI_MEM_1_SR_ACC_ADDR	(SF_BASE_ADDR + 0x110)
-#define SPI_PDWN_CTR_0_ADDR		(SF_BASE_ADDR + 0x180)
-#define SPI_PDWN_CTR_1_ADDR		(SF_BASE_ADDR + 0x190)
-#define SPI_PROG_CMD_CTR_ADDR	(SF_BASE_ADDR + 0x200)
-#define SPI_USER_CMD_VAL_ADDR	(SF_BASE_ADDR + 0x210)
-#define SPI_PROG_CMD_WBF_ADDR	(SF_BASE_ADDR + 0x300)
-#define SPI_PROG_CMD_RBF_ADDR	(SF_BASE_ADDR + 0x380)
-
-#define	CHIP_SEL_0_CFG_M		(REG32_VAL(CHIP_SEL_0_CFG_ADDR))
-#define	CHIP_SEL_1_CFG_M		(REG32_VAL(CHIP_SEL_1_CFG_ADDR))
-#define	SPI_INTF_CFG_M			(REG32_VAL(SPI_INTF_CFG_ADDR))
-#define	SPI_RD_WR_CTR_M			(REG32_VAL(SPI_RD_WR_CTR_ADDR))
-#define	SPI_WR_EN_CTR_M			(REG32_VAL(SPI_WR_EN_CTR_ADDR))
-#define	SPI_ER_CTR_M			(REG32_VAL(SPI_ER_CTR_ADDR))
-#define	SPI_ER_START_ADDR_M		(REG32_VAL(SPI_ER_START_ADDR_ADDR))
-#define	SPI_ERROR_STATUS_M		(REG32_VAL(SPI_ERROR_STATUS_ADDR))
-#define	SPI_MEM_0_SR_ACC_M		(REG32_VAL(SPI_MEM_0_SR_ACC_ADDR))
-#define	SPI_MEM_1_SR_ACC_M		(REG32_VAL(SPI_MEM_1_SR_ACC_ADDR))
-#define	SPI_PDWN_CTR_0_M		(REG32_VAL(SPI_PDWN_CTR_0_ADDR))
-#define	SPI_PDWN_CTR_1_M		(REG32_VAL(SPI_PDWN_CTR_1_ADDR))
-#define	SPI_PROG_CMD_CTR_M		(REG32_VAL(SPI_PROG_CMD_CTR_ADDR))
-#define	SPI_USER_CMD_VAL_M		(REG32_VAL(SPI_USER_CMD_VAL_ADDR))
-#define	SPI_PROG_CMD_WBF_M		(REG32_VAL(SPI_PROG_CMD_WBF_ADDR))
-#define	SPI_PROG_CMD_RBF_M		(REG32_VAL(SPI_PROG_CMD_RBF_ADDR))
-
-#endif	/* __WMT_SF1_H__ */
-
-
-
-
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_uart.h b/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_uart.h
deleted file mode 100755
index a25b2a87..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/include/mach/wmt_uart.h
+++ /dev/null
@@ -1,447 +0,0 @@
-/*++
-linux/include/asm-arm/arch-wmt/wmt_uart.h
-
-Copyright (c) 2008  WonderMedia Technologies, Inc.
-
-This program is free software: you can redistribute it and/or modify it under the
-terms of the GNU General Public License as published by the Free Software Foundation,
-either version 2 of the License, or (at your option) any later version.
-
-This program is distributed in the hope that it will be useful, but WITHOUT
-ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-PARTICULAR PURPOSE.  See the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License along with
-this program.  If not, see <http://www.gnu.org/licenses/>.
-
-WonderMedia Technologies, Inc.
-10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
---*/
-
-/* Be sure that virtual mapping is defined right */
-#ifndef __ASM_ARCH_HARDWARE_H
-#error "You must include hardware.h, not vt8500_uart.h"
-#endif
-
-#ifndef __WMT_UART_H
-#define __WMT_UART_H
-#include <linux/serial_core.h>
-
-/*
- * Baud Rate Speed Calculation
- *
- * BR = Baud Rate
- *
- * BRD = Baud Rate Divisor
- *
- * UCLK = UART clock
- *
- * UCLK = APB_INPUT_CLOCK / (URDIV + 1), URDIV = UART clock divisor
- *
- * URDIV = (APB_INPUT_CLOCK / 12MHz) - 1
- *
- * BR = UCLK / (13 * (BRD + 1))
- *
- * BRD = (UCLK / (13 * BR)) - 1
- *
- * Note: UCLK *MUST* be equal to 12MHz.
- */
-
-/*
- *   UART 0 : System Debug RS-232 (DB-9)
- */
-#define UART0_URTDR_ADDR    (UART0_BASE_ADDR + 0x0000)
-#define UART0_URRDR_ADDR    (UART0_BASE_ADDR + 0x0004)
-#define UART0_URDIV_ADDR    (UART0_BASE_ADDR + 0x0008)
-#define UART0_URLCR_ADDR    (UART0_BASE_ADDR + 0x000C)
-#define UART0_URICR_ADDR    (UART0_BASE_ADDR + 0x0010)
-#define UART0_URIER_ADDR    (UART0_BASE_ADDR + 0x0014)
-#define UART0_URISR_ADDR    (UART0_BASE_ADDR + 0x0018)
-#define UART0_URUSR_ADDR    (UART0_BASE_ADDR + 0x001C)
-#define UART0_URFCR_ADDR    (UART0_BASE_ADDR + 0x0020)
-#define UART0_URFIDX_ADDR   (UART0_BASE_ADDR + 0x0024)
-#define UART0_URBKR_ADDR    (UART0_BASE_ADDR + 0x0028)
-#define UART0_URTOD_ADDR    (UART0_BASE_ADDR + 0x002C)
-#define UART0_URTXF_ADDR    (UART0_BASE_ADDR + 0x1000)
-#define UART0_URRXF_ADDR    (UART0_BASE_ADDR + 0x1020)
-
-#define UART0_URTDR_REG     REG32_PTR(UART0_URTDR_ADDR)     /* RW, Transmit data register */
-#define UART0_URRDR_REG     REG32_PTR(UART0_URRDR_ADDR)     /* RO, Receive data register */
-#define UART0_URDIV_REG     REG32_PTR(UART0_URDIV_ADDR)     /* RW, Baud rate divisor */
-#define UART0_URLCR_REG     REG32_PTR(UART0_URLCR_ADDR)     /* RW, Line control register */
-#define UART0_URICR_REG     REG32_PTR(UART0_URICR_ADDR)     /* RW, IrDA control register */
-#define UART0_URIER_REG     REG32_PTR(UART0_URIER_ADDR)     /* RW, Interrupt enable register */
-#define UART0_URISR_REG     REG32_PTR(UART0_URISR_ADDR)     /* RO, Interrupt status register */
-#define UART0_URUSR_REG     REG32_PTR(UART0_URUSR_ADDR)     /* RO, UART status register */
-#define UART0_URFCR_REG     REG32_PTR(UART0_URFCR_ADDR)     /* RW, FIFO control register */
-#define UART0_URFIDX_REG    REG32_PTR(UART0_URFIDX_ADDR)    /* RO, FIFO index register */
-#define UART0_URTOD_REG     REG32_PTR(UART0_URTOD_ADDR)     /* WR, UART clock divisor Register */
-#define UART0_URBKR_REG     REG32_PTR(UART0_URBKR_ADDR)     /* RW, Break count-value register */
-
-#define UART0_URTDR_VAL     REG32_VAL(UART0_URTDR_ADDR)
-#define UART0_URRDR_VAL     REG32_VAL(UART0_URRDR_ADDR)
-#define UART0_URDIV_VAL     REG32_VAL(UART0_URDIV_ADDR)
-#define UART0_URLCR_VAL     REG32_VAL(UART0_URLCR_ADDR)
-#define UART0_URICR_VAL     REG32_VAL(UART0_URICR_ADDR)
-#define UART0_URIER_VAL     REG32_VAL(UART0_URIER_ADDR)
-#define UART0_URISR_VAL     REG32_VAL(UART0_URISR_ADDR)
-#define UART0_URUSR_VAL     REG32_VAL(UART0_URUSR_ADDR)
-#define UART0_URFCR_VAL     REG32_VAL(UART0_URFCR_ADDR)
-#define UART0_URFIDX_VAL    REG32_VAL(UART0_URFIDX_ADDR)
-#define UART0_URTOD_VAL     REG32_VAL(UART0_URTOD_ADDR)
-#define UART0_URBKR_VAL     REG32_VAL(UART0_URBKR_ADDR)
-
-/*
- *   UART 1 : Hardware Loopback
- */
-#define UART1_URTDR_ADDR    (UART1_BASE_ADDR + 0x0000)
-#define UART1_URRDR_ADDR    (UART1_BASE_ADDR + 0x0004)
-#define UART1_URDIV_ADDR    (UART1_BASE_ADDR + 0x0008)
-#define UART1_URLCR_ADDR    (UART1_BASE_ADDR + 0x000C)
-#define UART1_URICR_ADDR    (UART1_BASE_ADDR + 0x0010)
-#define UART1_URIER_ADDR    (UART1_BASE_ADDR + 0x0014)
-#define UART1_URISR_ADDR    (UART1_BASE_ADDR + 0x0018)
-#define UART1_URUSR_ADDR    (UART1_BASE_ADDR + 0x001C)
-#define UART1_URFCR_ADDR    (UART1_BASE_ADDR + 0x0020)
-#define UART1_URFIDX_ADDR   (UART1_BASE_ADDR + 0x0024)
-#define UART1_URBKR_ADDR    (UART1_BASE_ADDR + 0x0028)
-#define UART1_URTOD_ADDR    (UART1_BASE_ADDR + 0x002C)
-#define UART1_URTXF_ADDR    (UART1_BASE_ADDR + 0x1000)
-#define UART1_URRXF_ADDR    (UART1_BASE_ADDR + 0x1020)
-
-#define UART1_URTDR_REG     REG32_PTR(UART1_URTDR_ADDR)     /* RW, Transmit data register */
-#define UART1_URRDR_REG     REG32_PTR(UART1_URRDR_ADDR)     /* RO, Receive data register */
-#define UART1_URDIV_REG     REG32_PTR(UART1_URDIV_ADDR)     /* RW, Baud rate divisor */
-#define UART1_URLCR_REG     REG32_PTR(UART1_URLCR_ADDR)     /* RW, Line control register */
-#define UART1_URICR_REG     REG32_PTR(UART1_URICR_ADDR)     /* RW, IrDA control register */
-#define UART1_URIER_REG     REG32_PTR(UART1_URIER_ADDR)     /* RW, Interrupt enable register */
-#define UART1_URISR_REG     REG32_PTR(UART1_URISR_ADDR)     /* RO, Interrupt status register */
-#define UART1_URUSR_REG     REG32_PTR(UART1_URUSR_ADDR)     /* RO, UART status register */
-#define UART1_URFCR_REG     REG32_PTR(UART1_URFCR_ADDR)     /* RW, FIFO control register */
-#define UART1_URFIDX_REG    REG32_PTR(UART1_URFIDX_ADDR)    /* RO, FIFO index register */
-#define UART1_URTOD_REG     REG32_PTR(UART1_URTOD_ADDR)     /* WR, UART clock divisor Register */
-#define UART1_URBKR_REG     REG32_PTR(UART1_URBKR_ADDR)     /* RW, Break count-value register */
-
-#define UART1_URTDR_VAL     REG32_VAL(UART1_URTDR_ADDR)
-#define UART1_URRDR_VAL     REG32_VAL(UART1_URRDR_ADDR)
-#define UART1_URDIV_VAL     REG32_VAL(UART1_URDIV_ADDR)
-#define UART1_URLCR_VAL     REG32_VAL(UART1_URLCR_ADDR)
-#define UART1_URICR_VAL     REG32_VAL(UART1_URICR_ADDR)
-#define UART1_URIER_VAL     REG32_VAL(UART1_URIER_ADDR)
-#define UART1_URISR_VAL     REG32_VAL(UART1_URISR_ADDR)
-#define UART1_URUSR_VAL     REG32_VAL(UART1_URUSR_ADDR)
-#define UART1_URFCR_VAL     REG32_VAL(UART1_URFCR_ADDR)
-#define UART1_URFIDX_VAL    REG32_VAL(UART1_URFIDX_ADDR)
-#define UART1_URTOD_VAL     REG32_VAL(UART1_URTOD_ADDR)
-#define UART1_URBKR_VAL     REG32_VAL(UART1_URBKR_ADDR)
-
-/*
- *   UART 2 : External DB-9 connector
- */
-#define UART2_URTDR_ADDR    (UART2_BASE_ADDR + 0x0000)
-#define UART2_URRDR_ADDR    (UART2_BASE_ADDR + 0x0004)
-#define UART2_URDIV_ADDR    (UART2_BASE_ADDR + 0x0008)
-#define UART2_URLCR_ADDR    (UART2_BASE_ADDR + 0x000C)
-#define UART2_URICR_ADDR    (UART2_BASE_ADDR + 0x0010)
-#define UART2_URIER_ADDR    (UART2_BASE_ADDR + 0x0014)
-#define UART2_URISR_ADDR    (UART2_BASE_ADDR + 0x0018)
-#define UART2_URUSR_ADDR    (UART2_BASE_ADDR + 0x001C)
-#define UART2_URFCR_ADDR    (UART2_BASE_ADDR + 0x0020)
-#define UART2_URFIDX_ADDR   (UART2_BASE_ADDR + 0x0024)
-#define UART2_URBKR_ADDR    (UART2_BASE_ADDR + 0x0028)
-#define UART2_URTOD_ADDR    (UART2_BASE_ADDR + 0x002C)
-#define UART2_URTXF_ADDR    (UART2_BASE_ADDR + 0x1000)
-#define UART2_URRXF_ADDR    (UART2_BASE_ADDR + 0x1020)
-
-#define UART2_URTDR_REG     REG32_PTR(UART2_URTDR_ADDR)     /* RW, Transmit data register */
-#define UART2_URRDR_REG     REG32_PTR(UART2_URRDR_ADDR)     /* RO, Receive data register */
-#define UART2_URDIV_REG     REG32_PTR(UART2_URDIV_ADDR)     /* RW, Baud rate divisor */
-#define UART2_URLCR_REG     REG32_PTR(UART2_URLCR_ADDR)     /* RW, Line control register */
-#define UART2_URICR_REG     REG32_PTR(UART2_URICR_ADDR)     /* RW, IrDA control register */
-#define UART2_URIER_REG     REG32_PTR(UART2_URIER_ADDR)     /* RW, Interrupt enable register */
-#define UART2_URISR_REG     REG32_PTR(UART2_URISR_ADDR)     /* RO, Interrupt status register */
-#define UART2_URUSR_REG     REG32_PTR(UART2_URUSR_ADDR)     /* RO, UART status register */
-#define UART2_URFCR_REG     REG32_PTR(UART2_URFCR_ADDR)     /* RW, FIFO control register */
-#define UART2_URFIDX_REG    REG32_PTR(UART2_URFIDX_ADDR)    /* RO, FIFO index register */
-#define UART2_URTOD_REG     REG32_PTR(UART2_URTOD_ADDR)     /* WR, UART clock divisor Register */
-#define UART2_URBKR_REG     REG32_PTR(UART2_URBKR_ADDR)     /* RW, Break count-value register */
-
-#define UART2_URTDR_VAL     REG32_VAL(UART2_URTDR_ADDR)
-#define UART2_URRDR_VAL     REG32_VAL(UART2_URRDR_ADDR)
-#define UART2_URDIV_VAL     REG32_VAL(UART2_URDIV_ADDR)
-#define UART2_URLCR_VAL     REG32_VAL(UART2_URLCR_ADDR)
-#define UART2_URICR_VAL     REG32_VAL(UART2_URICR_ADDR)
-#define UART2_URIER_VAL     REG32_VAL(UART2_URIER_ADDR)
-#define UART2_URISR_VAL     REG32_VAL(UART2_URISR_ADDR)
-#define UART2_URUSR_VAL     REG32_VAL(UART2_URUSR_ADDR)
-#define UART2_URFCR_VAL     REG32_VAL(UART2_URFCR_ADDR)
-#define UART2_URFIDX_VAL    REG32_VAL(UART2_URFIDX_ADDR)
-#define UART2_URTOD_VAL     REG32_VAL(UART2_URTOD_ADDR)
-#define UART2_URBKR_VAL     REG32_VAL(UART2_URBKR_ADDR)
-
-/*
- *   UART 3 : IR Sensor
- */
-
-#define UART3_URTDR_ADDR    (UART3_BASE_ADDR + 0x0000)
-#define UART3_URRDR_ADDR    (UART3_BASE_ADDR + 0x0004)
-#define UART3_URBRD_ADDR    (UART3_BASE_ADDR + 0x0008)
-#define UART3_URLCR_ADDR    (UART3_BASE_ADDR + 0x000C)
-#define UART3_URICR_ADDR    (UART3_BASE_ADDR + 0x0010)
-#define UART3_URIER_ADDR    (UART3_BASE_ADDR + 0x0014)
-#define UART3_URISR_ADDR    (UART3_BASE_ADDR + 0x0018)
-#define UART3_URUSR_ADDR    (UART3_BASE_ADDR + 0x001C)
-#define UART3_URFCR_ADDR    (UART3_BASE_ADDR + 0x0020)
-#define UART3_URFIDX_ADDR   (UART3_BASE_ADDR + 0x0024)
-#define UART3_URBKR_ADDR    (UART3_BASE_ADDR + 0x0028)
-#define UART3_URDIV_ADDR    (UART3_BASE_ADDR + 0x002C)
-#define UART3_URTXF_ADDR    (UART3_BASE_ADDR + 0x0030)
-#define UART3_URRXF_ADDR    (UART3_BASE_ADDR + 0x0040)
-
-#define UART3_URTDR_REG     REG32_PTR(UART3_URTDR_ADDR)     /* RW, Transmit data register */
-#define UART3_URRDR_REG     REG32_PTR(UART3_URRDR_ADDR)     /* RO, Receive data register */
-#define UART3_URBRD_REG     REG32_PTR(UART3_URBRD_ADDR)     /* RW, Baud rate divisor */
-#define UART3_URLCR_REG     REG32_PTR(UART3_URLCR_ADDR)     /* RW, Line control register */
-#define UART3_URICR_REG     REG32_PTR(UART3_URICR_ADDR)     /* RW, IrDA control register */
-#define UART3_URIER_REG     REG32_PTR(UART3_URIER_ADDR)     /* RW, Interrupt enable register */
-#define UART3_URISR_REG     REG32_PTR(UART3_URISR_ADDR)     /* RO, Interrupt status register */
-#define UART3_URUSR_REG     REG32_PTR(UART3_URUSR_ADDR)     /* RO, UART status register */
-#define UART3_URFCR_REG     REG32_PTR(UART3_URFCR_ADDR)     /* RW, FIFO control register */
-#define UART3_URFIDX_REG    REG32_PTR(UART3_URFIDX_ADDR)    /* RO, FIFO index register */
-#define UART3_URDIV_REG     REG32_PTR(UART3_URDIV_ADDR)     /* WR, UART clock divisor Register */
-#define UART3_URBKR_REG     REG32_PTR(UART3_URBKR_ADDR)     /* RW, Break count-value register */
-
-#define UART3_URTDR_VAL     REG32_VAL(UART3_URTDR_ADDR)
-#define UART3_URRDR_VAL     REG32_VAL(UART3_URRDR_ADDR)
-#define UART3_URBRD_VAL     REG32_VAL(UART3_URBRD_ADDR)
-#define UART3_URLCR_VAL     REG32_VAL(UART3_URLCR_ADDR)
-#define UART3_URICR_VAL     REG32_VAL(UART3_URICR_ADDR)
-#define UART3_URIER_VAL     REG32_VAL(UART3_URIER_ADDR)
-#define UART3_URISR_VAL     REG32_VAL(UART3_URISR_ADDR)
-#define UART3_URUSR_VAL     REG32_VAL(UART3_URUSR_ADDR)
-#define UART3_URFCR_VAL     REG32_VAL(UART3_URFCR_ADDR)
-#define UART3_URFIDX_VAL    REG32_VAL(UART3_URFIDX_ADDR)
-#define UART3_URDIV_VAL     REG32_VAL(UART3_URDIV_ADDR)
-#define UART3_URBKR_VAL     REG32_VAL(UART3_URBKR_ADDR)
-
-
-/*
- * UART Line Control Register Bit Definitions
- */
-#define URLCR_TXEN      BIT0    /* Transmit operation enabled           */
-#define URLCR_RXEN      BIT1    /* Receive operation enabled            */
-#define URLCR_DLEN      BIT2    /* Data length 0:7-bit 1:8-bit          */
-#define URLCR_STBLEN    BIT3    /* Stop bit length 0:1-bit 1:2-bit      */
-#define URLCR_PTYEN     BIT4    /* Parity bit  0:inactive 1:active      */
-#define URLCR_PTYMODE   BIT5    /* Parity mode 0:evev 1:odd             */
-/* Request to send. A software controlled RTS modem signal, used when IrDA is disableda */
-#define URLCR_RTS       BIT6
-#define URLCR_LPBEN     BIT7    /* Loopback mode 0:inactive 1:active    */
-#define URLCR_DMAEN     BIT8    /* DMA enable. 0:inactive 1:active      */
-#define URLCR_BKINIT    BIT9    /* Bluetooth break signal initiation.   */
-#define URLCR_PSLVERR   BIT10   /* Support AMBA3 APB Error response signal.*/
-#define URLCR_RCTSSW    BIT11   /* RTS CTS software handle mode   */
-
-
-/* Bit[10:31] are reserved. */
-
-/*
- * UART Status Register Bit Definitions
- */
-#define URUSR_TXON      BIT0    /* Transmission is active               */
-#define URUSR_TXDBSY    BIT1    /* TX data is being loaded to TX port from either URTDR or TX FIFO */
-#define URUSR_RXON      BIT2    /* Reception is active                  */
-#define URUSR_RXDRDY    BIT3    /* RX data is ready in either URRDR or RX FIFO */
-#define URUSR_CTS       BIT4    /* Status of CTS signal                 */
-#define URUSR_MASK      ((1 << 5) - 1)  /* Mask for useful bits         */
-/* Bit[5:31] are reserved. */
-
-/*
- * UART Interrupt Enable Register Bit Definitions
- */
-#define URIER_ETXDE     BIT0    /* Enable for TX data register empty    */
-#define URIER_ERXDF     BIT1    /* Enable for RX data register full     */
-#define URIER_ETXFAE    BIT2    /* Enable for TX FIFO almost empty      */
-#define URIER_ETXFE     BIT3    /* Enable for TX FIFO empty             */
-#define URIER_ERXFAF    BIT4    /* Enable for RX FIFO almost full       */
-#define URIER_ERXFF     BIT5    /* Enable for RX FIFO full              */
-#define URIER_ETXDUDR   BIT6    /* Enable for TX underrun               */
-#define URIER_ERXDOVR   BIT7    /* Enable for RX overrun                */
-#define URIER_EPER      BIT8    /* Enable for parity error              */
-#define URIER_EFER      BIT9    /* Enable for frame error               */
-#define URIER_EMODM     BIT10   /* Enable for modem control signal      */
-#define URIER_ERXTOUT   BIT11   /* Enable for receive time out          */
-#define URIER_EBK       BIT12   /* Enable for break signal done         */
-/* Bit[13:31] are reserved. */
-
-/*
- * UART Interrupt Status Register Bit Definitions
- */
-#define URISR_TXDE      BIT0    /* TX data register empty               */
-#define URISR_RXDF      BIT1    /* RX data register full                */
-#define URISR_TXFAE     BIT2    /* TX FIFO almost empty                 */
-#define URISR_TXFE      BIT3    /* TX FIFO empty                        */
-#define URISR_RXFAF     BIT4    /* RX FIFO almost full                  */
-#define URISR_RXFF      BIT5    /* RX FIFO full                         */
-#define URISR_TXDUDR    BIT6    /* TX underrun                          */
-#define URISR_RXDOVR    BIT7    /* RX overrun                           */
-#define URISR_PER       BIT8    /* Parity error                         */
-#define URISR_FER       BIT9    /* Frame error                          */
-
-/* Toggle clear to send modem control signal. Used when IrDA is disabled*/
-#define URISR_TCTS      BIT10
-#define URISR_RXTOUT    BIT11   /* Receive time out                     */
-#define URISR_BKDONE    BIT12   /* Break signal done                    */
-#define URISR_MASK      ((1 << 13) - 1) /* Mask for useful bits         */
-/* Bit[13:31] are reserved. */
-
-/*
- * IrDA Mode Control Register Description
- */
-#define URICR_IREN      BIT0    /* Set "1" to enable IrDA               */
-/* Bit[1:31] are reserved. */
-
-/*
- * UART FIFO Control Register Description
- */
-#define URFCR_FIFOEN            BIT0
-#define URFCR_TRAIL				BIT1
-/* Bit[1:3] are reserved. */
-
-/*
- * Macros for setting threshold value to TX or RX FIFO level setting.
- */
-#define URFCR_FLVMASK           0xf                           /* FIFO threshold Level Mask */
-#define URFCR_TXFLV(x)          (((x) & URFCR_FLVMASK) << 4)  /* TX FIFO threshold */
-#define URFCR_RXFLV(x)          (((x) & URFCR_FLVMASK) << 8)  /* RX FIFO threshold */
-/* Bit[12:31] are reserved. */
-
-/*
- * UART Baud Rate Divisor Register Description.
- */
-#define URBRD_BRDMASK           0x3ff                         /* Bit[0:9] are baud rate divisor */
-#define URBRD_BRD(x)            ((x) & URBRD_BRDMASK)
-/* Bit[10:31] are reserved. */
-
-/*
- * UART FIFO Index Register Description.
- */
-#define URFIDX_IDXMASK          0x1f
-/*
- * Macros for getting URFIDX value to TX or RX FIFO index.
- */                           /* FIFO index Mask */
-#define URFIDX_TXFIDX(x)        ((x) & URFIDX_IDXMASK)        /* Get TX FIFO remaing entries */
-/* Bit[5:7] are reserved. */
-
-#define URFIDX_RXFIDX(x)        (((x) >> 8) & URFIDX_IDXMASK) /* Get RX FIFO remaing entries */
-/* Bit[13:31] are reserved. */
-
-/*
- * UART Break Counter Value Register Description.
- */
-#define URBKR_BCVMASK           0x0fff                        /* Bit[0:11] are break counter value */
-#define URBKR_BCV(x)            ((x) & URBKR_BCVMASK)
-/* Bit[12:31] are reserved. */
-
-#define URFCR_TXFRST            0x4		/* TX Fifo Reset */
-#define URFCR_RXFRST            0x8		/* Rx Fifo Reset */
-
-/*
- * UART clock divisor Register Description.
- */
-#define URDIV_DIVMASK           0xf0000                            /* Bit[16:19] are UART clock divisor */
-#define URDIV_DIV(x)            (((x) >> 16) & URDIV_DIVMASK)
-/* Bit[4:31] are reserved. */
-
-/*
- * UART module registers offset, add by Harry temporary.
- */
-#define URTDR                   0x0000
-#define URRDR                   0x0004
-#define URDIV                   0x0008
-#define URLCR                   0x000C
-#define URICR                   0x0010
-#define URIER                   0x0014
-#define URISR                   0x0018
-#define URUSR                   0x001C
-#define URFCR                   0x0020
-#define URFIDX                  0x0024
-#define URBKR                   0x0028
-#define URTOD                   0x002C
-#define URTXF                   0x01000
-#define URRXF                   0x01020
-
-/*
- * URBRD_BRD value simple examples.
- */
-#define BRD_921600BPS           0x10000
-#define BRD_460800BPS           0x10001
-#define BRD_230400BPS           0x10003
-#define BRD_115200BPS           0x10007
-#define BRD_76800BPS            0x1000B
-#define BRD_57600BPS            0x1000F
-#define BRD_38400BPS            0x10017
-#define BRD_28800BPS            0x1001F
-
-
-/*
- * URBKR_BCV value simple examples.
- *
- * Simply calculated by (baud_rate * 0.004096)
- * then take the integer.
- */
-#define BCV_921600BPS           3775
-#define BCV_460800BPS           1887
-#define BCV_230400BPS           944
-#define BCV_115200BPS           472
-#define BCV_76800BPS            315
-#define BCV_57600BPS            236
-#define BCV_38400BPS            157
-#define BCV_28800BPS            118
-
-/*
- * URDIV_DIV value simple examples.
- *
- * Followings generate UCLK = 12MHZ
- */
-#define DIV_192MHZ              15
-#define DIV_180MHZ              14
-#define DIV_168MHZ              13
-#define DIV_156MHZ              12
-#define DIV_144MHZ              11
-#define DIV_132MHZ              10
-#define DIV_120MHZ              9
-#define DIV_108MHZ              8
-#define DIV_96MHZ               7
-#define DIV_84MHZ               6
-#define DIV_72MHZ               5
-#define DIV_60MHZ               4
-#define DIV_48MHZ               3
-#define DIV_36MHZ               2
-#define DIV_24MHZ               1
-#define DIV_12MHZ               0
-
-/*
- * Data mask used in RX FIFO or URRDR.
- */
-#define RX_DATAMASK             0xff                    /* Bit[0:7] are reception data */
-#define RX_PERMASK              0x01ff                  /* Bit[0:8] */
-#define RX_FERMASK              0x03ff                  /* Bit[0:9] */
-
-
-struct wmt_port_fns {
-	void	(*set_mctrl)(struct uart_port *, u_int);
-	u_int	(*get_mctrl)(struct uart_port *);
-	void	(*pm)(struct uart_port *, u_int, u_int);
-	int	(*set_wake)(struct uart_port *, u_int);
-};
-
-#if defined(CONFIG_SERIAL_WMT)
-void wmt_register_uart_fns(struct wmt_port_fns *fns);
-void wmt_register_uart(int idx, int port);
-#else
-#define wmt_register_uart_fns(fns) do { } while (0)
-#define wmt_register_uart(idx, port) do { } while (0)
-#endif
-
-
-#endif /* __WMT_UART_H */
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/irq.c b/ANDROID_3.4.5/arch/arm/mach-wmt/irq.c
deleted file mode 100755
index 925b4b0a..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/irq.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/*++
-linux/arch/arm/mach-wmt/irq.c
-
-IRQ settings for WMT
-
-Copyright (c) 2009 WonderMedia Technologies, Inc.
-
-This program is free software: you can redistribute it and/or modify it under the
-terms of the GNU General Public License as published by the Free Software Foundation,
-either version 2 of the License, or (at your option) any later version.
-
-This program is distributed in the hope that it will be useful, but WITHOUT
-ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-PARTICULAR PURPOSE.  See the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License along with
-this program.  If not, see <http://www.gnu.org/licenses/>.
-
-WonderMedia Technologies, Inc.
-10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
---*/
-
-#include <linux/kernel.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <linux/of.h>
-#include <asm/hardware/gic.h>
-
-#include <mach/wmt_secure.h>
-
-extern int wmt_getsyspara(char *varname, unsigned char *varval, int *varlen);
-/*
- * Follows are handlers for normal irq_chip
- */
-static void wmt_mask_irq(struct irq_data *data)
-{
-
-}
-
-static void wmt_unmask_irq(struct irq_data *data)
-{
-
-}
-
-static void wmt_ack_irq(struct irq_data *data)
-{
-
-}
-
-#ifdef CONFIG_OF
-static const struct of_device_id wmt_dt_gic_match[] __initconst = {
-	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init },
-	{ }
-};
-#endif
-
-void wmt_irq_stub()
-{
-       asm volatile ( "cpsie i" );
-	wmt_smc(WMT_SMC_CMD_IRQ_RET, 0);
-}
-
-void __init wmt_init_irq(void)
-{
-	gic_arch_extn.irq_ack = wmt_ack_irq;
-	gic_arch_extn.irq_mask = wmt_mask_irq;
-	gic_arch_extn.irq_unmask = wmt_unmask_irq;
-
-	if (!of_have_populated_dt())
-		gic_init(0, 29, (void __iomem *)WMT_GIC_DIST_BASE, (void __iomem *)WMT_GIC_CPU_BASE);
-#ifdef CONFIG_OF
-	else
-		of_irq_init(wmt_dt_gic_match);
-#endif
-	unsigned char buf[40];
-	int varlen=40;
-	unsigned int cpu_trustzone_enabled = 0;
-
-	if (wmt_getsyspara("wmt.secure.param",buf,&varlen) == 0)
-		sscanf(buf,"%d",&cpu_trustzone_enabled);
-	if(cpu_trustzone_enabled != 1)
-		cpu_trustzone_enabled = 0;
-	if(cpu_trustzone_enabled != 0)
-		wmt_smc(WMT_SMC_CMD_IRQOK, (unsigned int)wmt_irq_stub);
-}
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/platsmp.c b/ANDROID_3.4.5/arch/arm/mach-wmt/platsmp.c
deleted file mode 100755
index 4f781017..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/platsmp.c
+++ /dev/null
@@ -1,202 +0,0 @@
-/*++
-	linux/arch/arm/mach-wmt/platsmp.c
-
-	Copyright (c) 2013  WonderMedia Technologies, Inc.
-
-	Copyright (C) 2002 ARM Ltd.
-	All Rights Reserved
-
-	This program is free software: you can redistribute it and/or modify it under the
-	terms of the GNU General Public License as published by the Free Software Foundation,
-	either version 2 of the License, or (at your option) any later version.
-
-	This program is distributed in the hope that it will be useful, but WITHOUT
-	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-	PARTICULAR PURPOSE.  See the GNU General Public License for more details.
-	You should have received a copy of the GNU General Public License along with
-	this program.  If not, see <http://www.gnu.org/licenses/>.
-
-	WonderMedia Technologies, Inc.
-	10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
---*/
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/delay.h>
-#include <linux/device.h>
-#include <linux/jiffies.h>
-#include <linux/smp.h>
-#include <linux/io.h>
-
-#include <linux/syscore_ops.h>
-
-#include <asm/cacheflush.h>
-#include <asm/hardware/gic.h>
-#include <asm/smp_plat.h>
-#include <asm/smp_scu.h>
-
-#include <mach/hardware.h>
-
-extern void wmt_secondary_startup(void);
-
-#define CPU1_BOOT_REG		HSP7_ADDR
-/*
- * control for which core is the next to come out of the secondary
- * boot "holding pen"
- */
-
-volatile int __cpuinitdata pen_release = -1;
-
-/*
- * Write pen_release in a way that is guaranteed to be visible to all
- * observers, irrespective of whether they're taking part in coherency
- * or not.  This is necessary for the hotplug code to work reliably.
- */
-static void write_pen_release(int val)
-{
-	pen_release = val;
-	smp_wmb();
-	__cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
-	outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
-}
-
-static void __iomem *scu_base_addr(void)
-{
-	return (void __iomem *)(MPCORE_PRIVATE_MEM);
-}
-
-static DEFINE_SPINLOCK(boot_lock);
-
-void __cpuinit platform_secondary_init(unsigned int cpu)
-{
-	/*
-	 * if any interrupts are already enabled for the primary
-	 * core (e.g. timer irq), then they will not have been enabled
-	 * for us: do so
-	 */
-	gic_secondary_init(0);
-
-	/*
-	 * let the primary processor know we're out of the
-	 * pen, then head off into the C entry point
-	 */
-	write_pen_release(-1);
-
-	/*
-	 * Synchronise with the boot thread.
-	 */
-	spin_lock(&boot_lock);
-	spin_unlock(&boot_lock);
-}
-
-int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
-{
-	unsigned long timeout;
-
-	/*
-	 * Set synchronisation state between this boot processor
-	 * and the secondary one
-	 */
-	spin_lock(&boot_lock);
-
-	/*
-	 * This is really belt and braces; we hold unintended secondary
-	 * CPUs in the holding pen until we're ready for them.  However,
-	 * since we haven't sent them a soft interrupt, they shouldn't
-	 * be there.
-	 */
-	write_pen_release(cpu_logical_map(cpu));
-
-	/*
-	 * Send the secondary CPU a soft interrupt, thereby causing
-	 * the boot monitor to read the system wide flags register,
-	 * and branch to the address found there.
-	 */
-
-	timeout = jiffies + (1 * HZ);
-	while (time_before(jiffies, timeout)) {
-		smp_rmb();
-
-		__raw_writel(virt_to_phys(wmt_secondary_startup),
-			CPU1_BOOT_REG);
-		gic_raise_softirq(cpumask_of(cpu), 1);
-
-		if (pen_release == -1)
-			break;
-
-		udelay(10);
-	}
-
-	/*
-	 * now the secondary core is starting up let it run its
-	 * calibrations, then wait for it to finish
-	 */
-	spin_unlock(&boot_lock);
-
-	return pen_release != -1 ? -ENOSYS : 0;
-}
-
-/*
- * Initialise the CPU possible map early - this describes the CPUs
- * which may be present or become present in the system.
- */
-
-void __init smp_init_cpus(void)
-{
-	void __iomem *scu_base = scu_base_addr();
-	unsigned int i, ncores;
-
-	ncores = scu_base ? scu_get_core_count(scu_base) : 1;
-
-	/* sanity check */
-	if (ncores > nr_cpu_ids) {
-		pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
-			ncores, nr_cpu_ids);
-		ncores = nr_cpu_ids;
-	}
-
-	for (i = 0; i < ncores; i++)
-		set_cpu_possible(i, true);
-
-	set_smp_cross_call(gic_raise_softirq);
-}
-
-void __init platform_smp_prepare_cpus(unsigned int max_cpus)
-{
-	*(volatile unsigned int *)MPCORE_PRIVATE_MEM |= BIT5 | BIT6;
-	scu_enable(scu_base_addr());
-
-	/*
-	 * Write the address of secondary startup into the
-	 * system-wide flags register. The boot monitor waits
-	 * until it receives a soft interrupt, and then the
-	 * secondary CPU branches to this address.
-	 */
-	__raw_writel(virt_to_phys(wmt_secondary_startup),
-			CPU1_BOOT_REG);
-}
-
-static int wmt_pm_suspend(void)
-{
-	return 0;
-}
-
-static void wmt_pm_resume(void)
-{
-#ifdef CONFIG_SMP
-	*(volatile unsigned int *)MPCORE_PRIVATE_MEM |= BIT5 | BIT6;
-	scu_enable(scu_base_addr());
-#endif
-	return;
-}
-
-static struct syscore_ops wmt_pm_syscore_ops = {
-	.suspend	= wmt_pm_suspend,
-	.resume		= wmt_pm_resume,
-};
-
-static __init int wmt_pm_syscore_init(void)
-{
-	register_syscore_ops(&wmt_pm_syscore_ops);
-	return 0;
-}
-arch_initcall(wmt_pm_syscore_init);
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/pm.c b/ANDROID_3.4.5/arch/arm/mach-wmt/pm.c
deleted file mode 100755
index af516e30..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/pm.c
+++ /dev/null
@@ -1,2212 +0,0 @@
-/*++
-linux/arch/arm/mach-wmt/pm.c
-
-Copyright (c) 2008  WonderMedia Technologies, Inc.
-
-This program is free software: you can redistribute it and/or modify it under the
-terms of the GNU General Public License as published by the Free Software Foundation,
-either version 2 of the License, or (at your option) any later version.
-
-This program is distributed in the hope that it will be useful, but WITHOUT
-ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-PARTICULAR PURPOSE.  See the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License along with
-this program.  If not, see <http://www.gnu.org/licenses/>.
-
-WonderMedia Technologies, Inc.
-10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
---*/
-#include <linux/init.h>
-#include <linux/suspend.h>
-#include <linux/errno.h>
-#include <linux/time.h>
-#include <linux/sysctl.h>
-#include <linux/interrupt.h>
-#include <linux/vmalloc.h>
-#include <linux/delay.h>
-#include <linux/module.h>
-#include <linux/timer.h>
-#include <linux/fs.h>
-#include <linux/init.h>
-#include <linux/proc_fs.h>
-#include <linux/cpufreq.h>
-#include <linux/reboot.h>
-#include <mach/hardware.h>
-#include <asm/memory.h>
-#include <asm/system.h>
-#include <asm/leds.h>
-#include <asm/io.h>
-#include <linux/rtc.h>
-
-#include <asm/cacheflush.h>
-#include <asm/hardware/cache-l2x0.h>
-
-#include <mach/wmt_secure.h>
-
-#include <linux/gpio.h>
-#include <mach/wmt_iomux.h>
-
-
-
-
-
-//#define CONFIG_KBDC_WAKEUP
-//#define KB_WAKEUP_SUPPORT
-//#define MOUSE_WAKEUP_SUPPORT
-
-#define	SOFT_POWER_SUPPORT
-#define	RTC_WAKEUP_SUPPORT
-//#ifdef CONFIG_RMTCTL_WonderMedia //define if CIR menuconfig enable
-#define CIR_WAKEUP_SUPPORT
-//#endif
-#define KEYPAD_POWER_SUPPORT
-#define PMWT_C_WAKEUP(src, type)  ((type & PMWT_TYPEMASK) << (((src - 24) & PMWT_WAKEUPMASK) * 4))
-
-enum wakeup_intr_tri_src_e {
-	WKS_T_WK0         = 0,    /* General Purpose Wakeup Source 0          */
-	WKS_T_WK2,                /* General Purpose Wakeup Source 1          */
-	WKS_T_WK3,                /* General Purpose Wakeup Source 2          */
-	WKS_T_WK4,                /* General Purpose Wakeup Source 3          */
-	WKS_T_SUS0,               /* General Purpose Wakeup Source 4          */
-	WKS_T_SUS1,               /* General Purpose Wakeup Source 5          */
-	WKS_T_USBATTA0,           /* USBATTA0          */
-	WKS_T_CIRIN,              /* CIRIN          */	
-	WKS_T_USBOC0,			    /* WKS_USBOC0 as wakeup            */
-	WKS_T_USBOC1,    			/* WKS_USBOC0 as wakeup            */
-	WKS_T_USBOC2,    			/* WKS_USBOC0 as wakeup            */
-	WKS_T_USBOC3,    			/* WKS_USBOC0 as wakeup            */		
-	WKS_T_UHC,    			/* UHC interrupt as wakeup                  */
-	WKS_T_UDC,    			/* WKS_UDC interrupt as wakeup              */	
-	WKS_T_CIR,    			/* CIR interrupt as wakeupr                 */
-	WKS_T_USBSW0,    			/* USBSW0 interrupt as wakeupr          */
-	WKS_T_SD3			= 18,   /* SD3 interrupt as wakeupr                 */	
-	WKS_T_DCDET		= 19,   /* DCDET interrupt as wakeupr               */	
-	WKS_T_SD2			= 20,   /* SD2 interrupt as wakeupr                 */	
-	WKS_T_HDMICEC		= 21,   /* HDMICEC interrupt as wakeupr             */	
-	WKS_T_SD0			= 22,   /* SD0 interrupt as wakeupr                 */
-	WKS_T_WK5			= 23,   /* Wakeup event number                      */	
-	WKS_T_PWRBTN		= 24,   /* PWRBTN as wakeup            */
-	WKS_T_RTC			= 25,   /* RTC as wakeup            */	
-	CA9MP_RST		= 26,   /* CA9MP_RST            */	
-	SOFT_RST		= 27,   /* SOFT_RST            */	
-	CORE0_WD_RST	= 28,   /* CORE0_WD_RST            */	
-	CORE1_WD_RST	= 29    /* CORE1_WD_RST            */	
-};
-
-static struct wakeup_source *wmt_ws;
-
-static struct workqueue_struct *wakeup_queue;
-static struct delayed_work wakeupwork;
-
-static struct {
-	bool have_switch;
-	unsigned int gpio_no;
-	unsigned int wakeup_source;
-}hall_switch;
-
-
-#define DRIVER_NAME	"PMC"
-#if defined(CONFIG_PM_RTC_IS_GMT) && defined(RTC_WAKEUP_SUPPORT)
-#include <linux/rtc.h>
-#endif
-
-/*
- *  Debug macros
- */
-#ifdef DEBUG
-#  define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## args)
-#else
-#  define DPRINTK(fmt, args...)
-#endif
-
-/*
- * For saving discontinuous registers during hibernation.
- */
-#define SAVE(x)		(saved[SAVED_##x] = (x##_VAL))
-#define RESTORE(x)	((x##_VAL) = saved[SAVED_##x])
-
-enum {
-	SAVED_SP = 0,
-	SAVED_OSTW, SAVED_OSTI,
-	SAVED_PMCEL, SAVED_PMCEU,
-	SAVED_PMCE2, SAVED_PMCE3,
-	/* SAVED_ATAUDMA, */
-	SAVED_SIZE
-};
-
-struct apm_dev_s {
-    char id;
-};
-
-
-extern unsigned int wmt_read_oscr(void);
-extern void wmt_read_rtc(unsigned int *date, unsigned int *time);
-extern void wmt_serial_set_reg(void);
-
-/* Hibernation entry table physical address */
-#define LOADER_ADDR												0xffff0000
-#define HIBERNATION_ENTER_EXIT_CODE_BASE_ADDR	0xFFFFFFC0
-#define DO_POWER_ON_SLEEP			            (HIBERNATION_ENTER_EXIT_CODE_BASE_ADDR + 0x00)
-#define DO_POWER_OFF_SUSPEND			        (HIBERNATION_ENTER_EXIT_CODE_BASE_ADDR + 0x04)
-#define DO_WM_IO_SET							        (HIBERNATION_ENTER_EXIT_CODE_BASE_ADDR + 0x34)
-
-static unsigned int exec_at = (unsigned int)-1;
-
-/*from = 4 high memory*/
-static void (*theKernel)(int from);
-//static void (*theKernel_io)(int from);
-
-#if defined(SOFT_POWER_SUPPORT) && defined(CONFIG_PROC_FS)
-//static struct proc_dir_entry *proc_softpower;
-static unsigned int softpower_data;
-#endif
-
-static long rtc2sys;
-
-struct work_struct	PMC_shutdown;
-struct work_struct	PMC_sync;
-
-
-extern int wmt_getsyspara(char *varname, char *varval, int *varlen);
-static int power_on_debounce_value = 100;  /*power button debounce time when power on state*/
-static int resume_debounce_value = 2000;	/*power button debounce time when press button to resume system*/
-static int power_up_debounce_value = 2000; /*power button debounce time when press button to power up*/
-#define min_debounce_value 0
-#define max_debounce_value 4000
-
-char hotplug_path[256] = "/sbin/hotplug";
-static int sync_counter = 0;
-static unsigned int time1, time2;
-
-#define REG_VAL(addr) (*((volatile unsigned int *)(addr)))
-
-
-#ifdef KEYPAD_POWER_SUPPORT
-#include <linux/input.h>
-#define KPAD_POWER_FUNCTION_NUM  1
-#define power_button_timeout (HZ/10)
-static struct input_dev *kpadPower_dev;
-static unsigned int kpadPower_codes[KPAD_POWER_FUNCTION_NUM] = {
-        [0] = KEY_POWER
-};
-static unsigned int powerKey_is_pressed;
-static unsigned int pressed_jiffies;
-static struct timer_list   kpadPower_timer;
-static spinlock_t kpadPower_lock;
-#endif
-
-#ifdef CONFIG_BATTERY_WMT
-static unsigned int battery_used;
-#endif
-
-#ifdef CONFIG_CACHE_L2X0
-unsigned int l2x0_onoff;
-unsigned int l2x0_aux;
-unsigned int l2x0_prefetch_ctrl;
-unsigned int en_static_address_filtering = 0;
-unsigned int address_filtering_start = 0xD8000000;
-unsigned int address_filtering_end = 0xD9000000;
-static volatile unsigned int l2x0_base;
-unsigned int cpu_trustzone_enabled = 0;
-#endif
-
-//gri
-static unsigned int var_fake_power_button=0;
-static unsigned int var_wake_type2=0;
-static unsigned int var_wake_type=0;
-static unsigned int var_wake_param=0;
-static unsigned int var_wake_en=0;
-static unsigned int var_1st_flag=0;
-
-volatile unsigned int Wake_up_sts_mask = 0;// all static we add pwbn
-static	unsigned int dynamic_wakeup = 0;
-static	unsigned int dynamic_pmc_intr = 0;
-
-static unsigned int pmlock_1st_flag=0;
-static unsigned int pmlock_intr_1st_flag=0;
-
-spinlock_t	wmt_pm_lock;
-spinlock_t	wmt_pm_intr_lock;
-
-unsigned int WMT_WAKE_UP_EVENT;//for printing wakeup event
-
-/* wmt_pwrbtn_debounce_value()
- *
- * Entry to set the power button debounce value, the time unit is ms.
- */
-static void wmt_pwrbtn_debounce_value(unsigned int time)
-{
-	volatile unsigned long debounce_value = 0 ;
-	unsigned long pmpb_value = 0;
-
-	/*add a delay to wait pmc & rtc  sync*/
-	udelay(130);
-	
-	/*Debounce value unit is 1024 * RTC period ,RTC is 32KHz so the unit is ~ 32ms*/
-	if (time % 32)
-		debounce_value = (time / 32) + 1;
-	else
-		debounce_value = (time / 32);
-
-	pmpb_value = PMPB_VAL;
-	pmpb_value &= ~ PMPB_DEBOUNCE(0xff);
-	pmpb_value |= PMPB_DEBOUNCE(debounce_value);
-
-	PMPB_VAL = pmpb_value;
-	//udelay(100);
-	DPRINTK("[%s] PMPB_VAL = 0x%.8X \n",__func__,PMPB_VAL);
-}
-
-/* wmt_power_up_debounce_value()
- *
- * Entry to set the power button debounce value, the time unit is ms.
- */
-void wmt_power_up_debounce_value(void) {
-
-	//printk("[%s] power_up_debounce_value = %d \n",__func__,power_up_debounce_value);
-	wmt_pwrbtn_debounce_value(power_up_debounce_value);
-
-}
-
-static void run_sync(struct work_struct *work)
-{
-	int ret;
-  char *argv[] = { "/system/etc/wmt/script/force.sh", "PMC", NULL };
-	char *envp_shutdown[] =
-	{ "HOME=/", "PATH=/sbin:/bin:/usr/sbin:/usr/bin", "", NULL };
-
-	wmt_pwrbtn_debounce_value(power_up_debounce_value);
-	DPRINTK("[%s] start\n",__func__);
-	ret = call_usermodehelper(argv[0], argv, envp_shutdown, 0);
-	DPRINTK("[%s] sync end\n",__func__);
-}
-
-static void run_shutdown(struct work_struct *work)
-{
-	int ret;
-    char *argv[] = { hotplug_path, "PMC", NULL };
-	char *envp_shutdown[] =
-		{ "HOME=/", "PATH=/sbin:/bin:/usr/sbin:/usr/bin", "ACTION=shutdown", NULL };
-	DPRINTK("[%s] \n",__func__);
-   
-	wmt_pwrbtn_debounce_value(power_up_debounce_value);
-	ret = call_usermodehelper(argv[0], argv, envp_shutdown, 0);
-}
-
-//kevin add support wakeup3/wakeup0 to wakeup ap
-#include <mach/viatel.h>
-irqreturn_t viatelcom_irq_cp_wake_ap(int irq, void *data);
-extern int gpio_viatel_4wire[4];
-
-void pmc_enable_wakeup_isr(enum wakeup_src_e wakeup_event, unsigned int type)
-{	  
-	  unsigned long	pm_lock_flags;
-	  unsigned int	wakeup_event_bit, wakeup_event_type;
-	  unsigned int wakeup_event_temp;
-	  
-	  if (type > 4)
-		type = 4;
-	  
-	  if (! pmlock_intr_1st_flag) {
-	    pmlock_intr_1st_flag = 1;
-	    spin_lock_init(&wmt_pm_intr_lock);
-	  }
-
-	  spin_lock_irqsave(&wmt_pm_intr_lock, pm_lock_flags);	  
-	  switch (wakeup_event) {
-		  case WKS_WK0:
-			wakeup_event_bit = (INT_TRG_EN_VAL | (1 << WKS_T_WK0));
-			wakeup_event_type = ((INT_TYPE0_VAL & (~(0xf << (WKS_T_WK0 << 2)))) | (type << (WKS_T_WK0 << 2)));
-			do {
-				INT_TYPE0_VAL = wakeup_event_type;
-			} while(INT_TYPE0_VAL != wakeup_event_type);
-			break;
-		  case WKS_WK2:
-			wakeup_event_bit = (INT_TRG_EN_VAL | (1 << WKS_T_WK2));
-			wakeup_event_type = ((INT_TYPE0_VAL & (~(0xf << (WKS_T_WK2 << 2)))) | (type << (WKS_T_WK2 << 2)));
-			do {
-				INT_TYPE0_VAL = wakeup_event_type;
-			} while(INT_TYPE0_VAL != wakeup_event_type);
-			break;
-		  case WKS_WK3:
-			wakeup_event_bit = (INT_TRG_EN_VAL | (1 << WKS_T_WK3));
-			wakeup_event_type = ((INT_TYPE0_VAL & (~(0xf << (WKS_T_WK3 << 2)))) | (type << (WKS_T_WK3 << 2)));
-			do {
-				INT_TYPE0_VAL = wakeup_event_type;
-			} while(INT_TYPE0_VAL != wakeup_event_type);
-			break;		
-		  case WKS_WK4:
-			wakeup_event_bit = (INT_TRG_EN_VAL | (1 << WKS_T_WK4));
-			wakeup_event_type = ((INT_TYPE0_VAL & (~(0xf << (WKS_T_WK4 << 2)))) | (type << (WKS_T_WK4 << 2)));
-			do {
-				INT_TYPE0_VAL = wakeup_event_type;
-			} while(INT_TYPE0_VAL != wakeup_event_type);
-			break;
-		  case WKS_SUS0:
-			wakeup_event_bit = (INT_TRG_EN_VAL | (1 << WKS_T_SUS0));
-			wakeup_event_type = ((INT_TYPE0_VAL & (~(0xf << (WKS_T_SUS0 << 2)))) | (type << (WKS_T_SUS0 << 2)));
-			do {
-				INT_TYPE0_VAL = wakeup_event_type;
-			} while(INT_TYPE0_VAL != wakeup_event_type);
-			break;
-		  case WKS_SUS1:
-			wakeup_event_bit = (INT_TRG_EN_VAL | (1 << WKS_T_SUS1));
-			wakeup_event_type = ((INT_TYPE0_VAL & (~(0xf << (WKS_T_SUS1 << 2)))) | (type << (WKS_T_SUS1 << 2)));
-			do {
-				INT_TYPE0_VAL = wakeup_event_type;
-			} while(INT_TYPE0_VAL != wakeup_event_type);
-			break;
-		  case WKS_USBATTA0:
-			wakeup_event_bit = (INT_TRG_EN_VAL | (1 << WKS_T_USBATTA0));
-			wakeup_event_type = ((INT_TYPE0_VAL & (~(0xf << (WKS_T_USBATTA0 << 2)))) | (type << (WKS_T_USBATTA0 << 2)));
-			do {
-				INT_TYPE0_VAL = wakeup_event_type;
-			} while(INT_TYPE0_VAL != wakeup_event_type);
-			break;
-		  case WKS_CIRIN:
-			wakeup_event_bit = (INT_TRG_EN_VAL | (1 << WKS_T_CIRIN));
-			wakeup_event_type = ((INT_TYPE0_VAL & (~(0xf << (WKS_T_CIRIN << 2)))) | (type << (WKS_T_CIRIN << 2)));
-			do {
-				INT_TYPE0_VAL = wakeup_event_type;
-			} while(INT_TYPE0_VAL != wakeup_event_type);
-			break;
-		  case WKS_PWRBTN:
-			wakeup_event_bit = (INT_TRG_EN_VAL | (1 << WKS_T_PWRBTN));
-			break;
-		  case WKS_RTC:
-			wakeup_event_bit = (INT_TRG_EN_VAL | (1 << WKS_T_RTC));
-			break;
-		  case WKS_USBOC0:
-			wakeup_event_bit = (INT_TRG_EN_VAL | (1 << WKS_T_USBOC0));
-			wakeup_event_temp = WKS_USBOC0 - WKS_USBOC0;
-			wakeup_event_type = ((INT_TYPE2_VAL & (~(0xf << (wakeup_event_temp << 2)))) | (type << (wakeup_event_temp << 2)));
-			do {
-				INT_TYPE2_VAL = wakeup_event_type;
-			} while(INT_TYPE2_VAL != wakeup_event_type);
-			break;
-		  case WKS_USBOC1:
-			wakeup_event_bit = (INT_TRG_EN_VAL | (1 << WKS_T_USBOC1));
-			wakeup_event_temp = WKS_USBOC1 - WKS_USBOC0;
-			wakeup_event_type = ((INT_TYPE2_VAL & (~(0xf << (wakeup_event_temp << 2)))) | (type << (wakeup_event_temp << 2)));
-			do {
-				INT_TYPE2_VAL = wakeup_event_type;
-			} while(INT_TYPE2_VAL != wakeup_event_type);
-			break;
-		  case WKS_USBOC2:
-			wakeup_event_bit = (INT_TRG_EN_VAL | (1 << WKS_T_USBOC2));
-			wakeup_event_temp = WKS_USBOC2 - WKS_USBOC0;
-			wakeup_event_type = ((INT_TYPE2_VAL & (~(0xf << (wakeup_event_temp << 2)))) | (type << (wakeup_event_temp << 2)));
-			do {
-				INT_TYPE2_VAL = wakeup_event_type;
-			} while(INT_TYPE2_VAL != wakeup_event_type);
-			break;
-		  case WKS_USBOC3:
-			wakeup_event_bit = (INT_TRG_EN_VAL | (1 << WKS_T_USBOC3));
-			wakeup_event_temp = WKS_USBOC3 - WKS_USBOC0;
-			wakeup_event_type = ((INT_TYPE2_VAL & (~(0xf << (wakeup_event_temp << 2)))) | (type << (wakeup_event_temp << 2)));
-			do {
-				INT_TYPE2_VAL = wakeup_event_type;
-			} while(INT_TYPE2_VAL != wakeup_event_type);
-			break;
-		  case WKS_UHC:
-			wakeup_event_bit = (INT_TRG_EN_VAL | (1 << WKS_T_UHC));
-			wakeup_event_temp = WKS_UHC - WKS_USBOC0;
-			wakeup_event_type = ((INT_TYPE2_VAL & (~(0xf << (wakeup_event_temp << 2)))) | (type << (wakeup_event_temp << 2)));
-			do {
-				INT_TYPE2_VAL = wakeup_event_type;
-			} while(INT_TYPE2_VAL != wakeup_event_type);
-			break;	
-		  case WKS_UDC:
-			wakeup_event_bit = (INT_TRG_EN_VAL | (1 << WKS_T_UDC));
-			wakeup_event_temp = WKS_UDC - WKS_USBOC0;
-			wakeup_event_type = ((INT_TYPE2_VAL & (~(0xf << (wakeup_event_temp << 2)))) | (type << (wakeup_event_temp << 2)));
-			do {
-				INT_TYPE2_VAL = wakeup_event_type;
-			} while(INT_TYPE2_VAL != wakeup_event_type);
-			break;
-		  case WKS_CIR:
-			wakeup_event_bit = (INT_TRG_EN_VAL | (1 << WKS_T_CIR));
-			wakeup_event_temp = WKS_CIR - WKS_USBOC0;
-			wakeup_event_type = ((INT_TYPE2_VAL & (~(0xf << (wakeup_event_temp << 2)))) | (type << (wakeup_event_temp << 2)));
-			do {
-				INT_TYPE2_VAL = wakeup_event_type;
-			} while(INT_TYPE2_VAL != wakeup_event_type);
-			break;
-		  case WKS_USBSW0:
-			wakeup_event_bit = (INT_TRG_EN_VAL | (1 << WKS_T_USBSW0));
-			wakeup_event_temp = WKS_USBSW0 - WKS_USBOC0;
-			wakeup_event_type = ((INT_TYPE2_VAL & (~(0xf << (wakeup_event_temp << 2)))) | (type << (wakeup_event_temp << 2)));
-			do {
-				INT_TYPE2_VAL = wakeup_event_type;
-			} while(INT_TYPE2_VAL != wakeup_event_type);
-			break;
-		  case WKS_SD3:
-			wakeup_event_bit = (INT_TRG_EN_VAL | (1 << WKS_T_SD3));
-			wakeup_event_temp = WKS_SD3 - WKS_SD3 + 2;
-			wakeup_event_type = ((INT_TYPE1_VAL & (~(0xf << (wakeup_event_temp << 2)))) | (type << (wakeup_event_temp << 2)));
-			do {
-				INT_TYPE1_VAL = wakeup_event_type;
-			} while(INT_TYPE1_VAL != wakeup_event_type);
-			break;
-		  case WKS_DCDET:
-			wakeup_event_bit = (INT_TRG_EN_VAL | (1 << WKS_T_DCDET));
-			wakeup_event_temp = WKS_DCDET - WKS_SD3 + 2;
-			wakeup_event_type = ((INT_TYPE1_VAL & (~(0xf << (wakeup_event_temp << 2)))) | (type << (wakeup_event_temp << 2)));
-			do {
-				INT_TYPE1_VAL = wakeup_event_type;
-			} while(INT_TYPE1_VAL != wakeup_event_type);
-			break;
-		  case WKS_SD2:
-			wakeup_event_bit = (INT_TRG_EN_VAL | (1 << WKS_T_SD2));
-			wakeup_event_temp = WKS_SD2 - WKS_SD3 + 2;
-			wakeup_event_type = ((INT_TYPE1_VAL & (~(0xf << (wakeup_event_temp << 2)))) | (type << (wakeup_event_temp << 2)));
-			do {
-				INT_TYPE1_VAL = wakeup_event_type;
-			} while(INT_TYPE1_VAL != wakeup_event_type);
-			break;
-		  case WKS_HDMICEC:
-			wakeup_event_bit = (INT_TRG_EN_VAL | (1 << WKS_T_HDMICEC));
-			wakeup_event_temp = WKS_HDMICEC - WKS_SD3 + 2;
-			wakeup_event_type = ((INT_TYPE1_VAL & (~(0xf << (wakeup_event_temp << 2)))) | (type << (wakeup_event_temp << 2)));
-			do {
-				INT_TYPE1_VAL = wakeup_event_type;
-			} while(INT_TYPE1_VAL != wakeup_event_type);
-			break;
-		  case WKS_SD0:
-			wakeup_event_bit = (INT_TRG_EN_VAL | (1 << WKS_T_SD0));
-			wakeup_event_temp = WKS_SD0 - WKS_SD3 + 2;
-			wakeup_event_type = ((INT_TYPE1_VAL & (~(0xf << (wakeup_event_temp << 2)))) | (type << (wakeup_event_temp << 2)));
-			do {
-				INT_TYPE1_VAL = wakeup_event_type;
-			} while(INT_TYPE1_VAL != wakeup_event_type);
-			break;
-		  case WKS_WK5:
-			wakeup_event_bit = (INT_TRG_EN_VAL | (1 << WKS_T_WK5));
-			wakeup_event_temp = WKS_WK5 - WKS_SD3 + 2;
-			wakeup_event_type = ((INT_TYPE1_VAL & (~(0xf << (wakeup_event_temp << 2)))) | (type << (wakeup_event_temp << 2)));
-			do {
-				INT_TYPE1_VAL = wakeup_event_type;
-			} while(INT_TYPE1_VAL != wakeup_event_type);
-			break;
-		  default:
-			goto pmc_enable_wakeup_isr_error;
-			break;
-	  }	  
-	  
-	  while (PMCIS_VAL & (1 << wakeup_event)) {
-		PMCIS_VAL = (1 << wakeup_event);
-	  }	  
-	  
-	  do {
-		INT_TRG_EN_VAL = wakeup_event_bit;
-	  } while(INT_TRG_EN_VAL != wakeup_event_bit);	  
-	  dynamic_pmc_intr = INT_TRG_EN_VAL;
-
-pmc_enable_wakeup_isr_error:	  
-	  spin_unlock_irqrestore(&wmt_pm_intr_lock, pm_lock_flags);
-
-}
-EXPORT_SYMBOL(pmc_enable_wakeup_isr);
-
-void pmc_disable_wakeup_isr(enum wakeup_src_e wakeup_event)
-{
-
-	  unsigned long	pm_lock_flags;
-	  unsigned int	wakeup_event_bit;
-	  	  
-	  if (! pmlock_intr_1st_flag) {
-	    pmlock_intr_1st_flag = 1;
-	    spin_lock_init(&wmt_pm_intr_lock);
-	  }
-
-	  spin_lock_irqsave(&wmt_pm_intr_lock, pm_lock_flags);		  
-	  switch (wakeup_event) {
-		  case WKS_WK0:
-			wakeup_event_bit = (INT_TRG_EN_VAL & (~(1 << WKS_T_WK0)));
-			break;
-		  case WKS_WK2:
-			wakeup_event_bit = (INT_TRG_EN_VAL & (~(1 << WKS_T_WK2)));
-			break;
-		  case WKS_WK3:
-			wakeup_event_bit = (INT_TRG_EN_VAL & (~(1 << WKS_T_WK3)));
-			break;		
-		  case WKS_WK4:
-			wakeup_event_bit = (INT_TRG_EN_VAL & (~(1 << WKS_T_WK4)));
-			break;
-		  case WKS_SUS0:
-			wakeup_event_bit = (INT_TRG_EN_VAL & (~(1 << WKS_T_SUS0)));
-			break;
-		  case WKS_SUS1:
-			wakeup_event_bit = (INT_TRG_EN_VAL & (~(1 << WKS_T_SUS1)));
-			break;
-		  case WKS_USBATTA0:
-			wakeup_event_bit = (INT_TRG_EN_VAL & (~(1 << WKS_T_USBATTA0)));
-			break;
-		  case WKS_CIRIN:
-			wakeup_event_bit = (INT_TRG_EN_VAL & (~(1 << WKS_T_CIRIN)));
-			break;
-		  case WKS_PWRBTN:
-			wakeup_event_bit = (INT_TRG_EN_VAL & (~(1 << WKS_T_PWRBTN)));
-			break;
-		  case WKS_RTC:
-			wakeup_event_bit = (INT_TRG_EN_VAL & (~(1 << WKS_T_RTC)));
-			break;
-		  case WKS_USBOC0:
-			wakeup_event_bit = (INT_TRG_EN_VAL & (~(1 << WKS_T_USBOC0)));
-			break;
-		  case WKS_USBOC1:
-			wakeup_event_bit = (INT_TRG_EN_VAL & (~(1 << WKS_T_USBOC1)));
-			break;
-		  case WKS_USBOC2:
-			wakeup_event_bit = (INT_TRG_EN_VAL & (~(1 << WKS_T_USBOC2)));
-			break;
-		  case WKS_USBOC3:
-			wakeup_event_bit = (INT_TRG_EN_VAL & (~(1 << WKS_T_USBOC3)));
-			break;
-		  case WKS_UHC:
-			wakeup_event_bit = (INT_TRG_EN_VAL & (~(1 << WKS_T_UHC)));
-			break;	
-		  case WKS_UDC:
-			wakeup_event_bit = (INT_TRG_EN_VAL & (~(1 << WKS_T_UDC)));
-			break;
-		  case WKS_CIR:
-			wakeup_event_bit = (INT_TRG_EN_VAL & (~(1 << WKS_T_CIR)));
-			break;
-		  case WKS_USBSW0:
-			wakeup_event_bit = (INT_TRG_EN_VAL & (~(1 << WKS_T_USBSW0)));
-			break;
-		  case WKS_SD3:
-			wakeup_event_bit = (INT_TRG_EN_VAL & (~(1 << WKS_T_SD3)));
-			break;
-		  case WKS_DCDET:
-			wakeup_event_bit = (INT_TRG_EN_VAL & (~(1 << WKS_T_DCDET)));
-			break;
-		  case WKS_SD2:
-			wakeup_event_bit = (INT_TRG_EN_VAL & (~(1 << WKS_T_SD2)));
-			break;
-		  case WKS_HDMICEC:
-			wakeup_event_bit = (INT_TRG_EN_VAL & (~(1 << WKS_T_HDMICEC)));
-			break;
-		  case WKS_SD0:
-			wakeup_event_bit = (INT_TRG_EN_VAL & (~(1 << WKS_T_SD0)));
-			break;
-		  case WKS_WK5:
-			wakeup_event_bit = (INT_TRG_EN_VAL & (~(1 << WKS_T_WK5)));
-			break;
-		  default:
-			goto pmc_disable_wakeup_isr_error;
-			break;
-	  }	  
-	  
-	  do {
-		INT_TRG_EN_VAL = wakeup_event_bit;
-	  } while(INT_TRG_EN_VAL != wakeup_event_bit);	  	  	 
-	  dynamic_pmc_intr = INT_TRG_EN_VAL;
-
-pmc_disable_wakeup_isr_error:	  
-	  spin_unlock_irqrestore(&wmt_pm_intr_lock, pm_lock_flags);
-  
-}
-EXPORT_SYMBOL(pmc_disable_wakeup_isr);
-
-void pmc_clear_intr_status(enum wakeup_src_e wakeup_event)
-{
-	  unsigned long	pm_lock_flags;
-	  unsigned int	wakeup_event_bit;
-	  	  
-	  if (! pmlock_intr_1st_flag) {
-	    pmlock_intr_1st_flag = 1;
-	    spin_lock_init(&wmt_pm_intr_lock);
-	  }
-
-	  wakeup_event_bit = (1 << wakeup_event);
-	  
-	  spin_lock_irqsave(&wmt_pm_intr_lock, pm_lock_flags);	
-	  
-	  while (PMCIS_VAL & wakeup_event_bit) {
-		PMCIS_VAL = wakeup_event_bit;
-	  }
-
-	  spin_unlock_irqrestore(&wmt_pm_intr_lock, pm_lock_flags);
-}
-EXPORT_SYMBOL(pmc_clear_intr_status);
-
-void pmc_clear_wakeup_status(enum wakeup_src_e wakeup_event)
-{
-	  unsigned long	pm_lock_flags;
-	  unsigned int	wakeup_event_bit;
-	  	  
-	  if (! pmlock_1st_flag) {
-	    pmlock_1st_flag = 1;
-	    spin_lock_init(&wmt_pm_lock);
-	  }
-
-	  wakeup_event_bit = (1 << wakeup_event);
-	  
-	  spin_lock_irqsave(&wmt_pm_lock, pm_lock_flags);	
-	  
-	  while (PMWS_VAL & wakeup_event_bit) {
-		PMWS_VAL = wakeup_event_bit;
-	  }
-
-	  spin_unlock_irqrestore(&wmt_pm_lock, pm_lock_flags);
-}
-EXPORT_SYMBOL(pmc_clear_wakeup_status);
-
-void pmc_enable_wakeup_event(enum wakeup_src_e wakeup_event, unsigned int type)
-{
-	  unsigned int which_bit;
-	  unsigned ori_type = 0;
-	  unsigned long	pm_lock_flags;	
-
-	  if ((wakeup_event > WKS_CIRIN) && (wakeup_event < WKS_PWRBTN))
-	    return;
-		
-	  if ((wakeup_event > WKS_USBSW0) && (wakeup_event < WKS_SD3))
-	    return;		
-	  
-	  if (type > 4)
-	    return;
-	  
-	  if (! pmlock_1st_flag) {
-	    pmlock_1st_flag = 1;
-	    spin_lock_init(&wmt_pm_lock);
-	  }
-
-	  which_bit = (1 << wakeup_event);
-	  
-	  spin_lock_irqsave(&wmt_pm_lock, pm_lock_flags);
-	  if (which_bit < 0x100) {
-
-		ori_type = PMWT_VAL;
-		ori_type &= (~(0xf << (wakeup_event << 2)));
-	    ori_type |= (type << (wakeup_event << 2));
-		do {
-			PMWT_VAL = ori_type; 
-		} while(PMWT_VAL != ori_type);
-	  } else if (which_bit >= 0x1000000) {
-	    unsigned int temp;
-	
-	    temp = wakeup_event - 24;
-
-		ori_type = PMWTC_VAL;
-	    ori_type &= (~(0xf << (temp << 2)));
-	    ori_type |= (type << (temp << 2));
-		do {
-			PMWTC_VAL = ori_type;
-		} while(PMWTC_VAL != ori_type);
-	  } else if (which_bit >= 0x10000) {
-	    unsigned int temp;
-	    temp = wakeup_event - 16;
-
-		ori_type = WK_EVT_TYPE_VAL;
-	    ori_type &= (~(0xf << (temp << 2)));
-	    ori_type |= (type << (temp << 2));
-		do {
-			WK_EVT_TYPE_VAL = ori_type;
-		} while(WK_EVT_TYPE_VAL != ori_type);		
-	  }
-	  dynamic_wakeup |= (1 << wakeup_event);
- 
-	  spin_unlock_irqrestore(&wmt_pm_lock, pm_lock_flags);	  
-}
-EXPORT_SYMBOL(pmc_enable_wakeup_event);
-
-void pmc_disable_wakeup_event(enum wakeup_src_e wakeup_event)
-{
-	  
-	  if (! pmlock_1st_flag) {
-	    pmlock_1st_flag = 1;
-	    spin_lock_init(&wmt_pm_lock);
-	  }
-
-	  dynamic_wakeup &= (~(1 << wakeup_event));
-		
-}
-EXPORT_SYMBOL(pmc_disable_wakeup_event);
-
-
-static void wakeup_func(struct work_struct *work)
-{	
-	struct file *fp;
-	mm_segment_t fs;
-	loff_t pos=0;
-	unsigned long flags;
-	char buf[3];
-	
-	fp = filp_open("/sys/class/backlight/pwm-backlight.0/brightness", O_RDWR, 0777);
-
-	if (IS_ERR(fp)) {
-        printk(KERN_ERR"open file error\n");
-        return;
-    }
-	
-	fs = get_fs();
-    set_fs(KERNEL_DS);
-	vfs_read(fp, buf, sizeof(buf), &pos);
-	filp_close(fp, NULL);
-    set_fs(fs);
-	//printk(KERN_ERR"%s buf %s\n",__FUNCTION__,buf);
-	if(gpio_get_value(hall_switch.gpio_no)){
-		if(strncmp(buf,"0",1))
-		{
-			return;
-		}
-			
-	}
-	else{		
-		if(!strncmp(buf,"0",1))
-		{
-			return;
-		}
-	}
-
-#ifdef KEYPAD_POWER_SUPPORT
-			if(kpadPower_dev) {
-	
-				spin_lock_irqsave(&kpadPower_lock, flags);
-				if(!powerKey_is_pressed) {
-					powerKey_is_pressed = 1; 
-					input_report_key(kpadPower_dev, KEY_POWER, 1); //power key is pressed
-					input_sync(kpadPower_dev);
-					pressed_jiffies = jiffies;
-					wmt_pwrbtn_debounce_value(power_up_debounce_value);
-					DPRINTK("\n[%s]power key pressed -->\n",__func__);
-					time1 = jiffies_to_msecs(jiffies);
-					__pm_wakeup_event(wmt_ws, (MSEC_PER_SEC >> 4));
-				}
-				//disable_irq(IRQ_PMC_WAKEUP);
-				spin_unlock_irqrestore(&kpadPower_lock, flags);
-				mod_timer(&kpadPower_timer, jiffies + power_button_timeout);
-			}
-	#endif
-}
-
-static irqreturn_t pmc_wakeup_isr(int this_irq, void *dev_id)
-{
-	unsigned int status_i;
-	unsigned long flags;
-
-	status_i = PMCIS_VAL;
-
-	rmb();
-
-
-    //kevin add for wakeup3 to wakeup ap
-	if(status_i & (gpio_viatel_4wire[GPIO_VIATEL_USB_MDM_WAKE_AP]==149?BIT0:BIT2)){
-		//printk("call viatelcom_irq_cp_wake_ap\n");
-		viatelcom_irq_cp_wake_ap(this_irq,dev_id);
-		PMCIS_VAL |= (gpio_viatel_4wire[GPIO_VIATEL_USB_MDM_WAKE_AP]==149?BIT0:BIT2);
-		
-	}
-
-	/*
-	 * TODO : wakeup event and  interrupt event share the same interrupt
-	 * source IRQ_PMC. we should make a mechanism like 'request_irq' to
-	 * register interrupt event callback function, and call the right
-	 * function here.
-	 */
-	/* DCDET interrupt */
-	//if (status_i & BIT27) {
-	//	extern void dcdet_isr_callback(void);
-	//	dcdet_isr_callback();
-	//	PMCIS_VAL |= BIT0;
-	//}
-
-	if(hall_switch.have_switch && (status_i & (1<<(hall_switch.wakeup_source)))){
-		//printk(KERN_ERR"call wakeup0\n");
-		queue_delayed_work(wakeup_queue, &wakeupwork, msecs_to_jiffies(50));
-		pmc_clear_intr_status(hall_switch.wakeup_source);
-	}
-	
-	if (status_i & BIT14) {
-		
-			pmc_clear_intr_status(WKS_PWRBTN);
-	#ifdef KEYPAD_POWER_SUPPORT
-		if(kpadPower_dev) {
-
-			spin_lock_irqsave(&kpadPower_lock, flags);
-			if(!powerKey_is_pressed) {
-				powerKey_is_pressed = 1; 
-				input_report_key(kpadPower_dev, KEY_POWER, 1); //power key is pressed
-				input_sync(kpadPower_dev);
-				pressed_jiffies = jiffies;
-				wmt_pwrbtn_debounce_value(power_up_debounce_value);
-				DPRINTK("\n[%s]power key pressed -->\n",__func__);
-				time1 = jiffies_to_msecs(jiffies);
-				__pm_wakeup_event(wmt_ws, (MSEC_PER_SEC >> 4));
-			}
-			//disable_irq(IRQ_PMC_WAKEUP);
-			spin_unlock_irqrestore(&kpadPower_lock, flags);
-			mod_timer(&kpadPower_timer, jiffies + power_button_timeout);
-		}
-	#endif
-		
-	#if defined(SOFT_POWER_SUPPORT) && defined(CONFIG_PROC_FS)
-		softpower_data = 1;
-	#endif
-
-	}
-	
-	return IRQ_HANDLED;		
-}
-
-extern int PM_device_PostSuspend(void);
-extern int PM_device_PreResume(void);
-
-void check_pmc_busy(void)
-{
-	while (PMCS2_VAL&0x3F0038)
-	;
-}
-void save_plla_speed(unsigned int *plla_div)
-{
-	plla_div[0] = PMARM_VAL;/*arm_div*/
-	check_pmc_busy();
-	plla_div[1]= PML2C_VAL;;/*l2c_div*/
-	check_pmc_busy();
-	plla_div[2] = PML2CTAG_VAL;/*l2c_tag_div*/
-	check_pmc_busy();
-	plla_div[3] = PML2CDATA_VAL;/*l2c_data_div*/
-	check_pmc_busy();
-	plla_div[4] = PML2CAXI_VAL;/*axi_l2c_div*/
-	check_pmc_busy();
-	plla_div[5] = PMDBGAPB_VAL;/*dbg_apb_div*/
-	check_pmc_busy();
-	plla_div[6] = PMPMA_VAL;
-	check_pmc_busy();
-	
-}
-
-void save_pllb_speed(unsigned int *pllb_div)
-{
-	check_pmc_busy();
-	pllb_div[0] = PMPWM_VAL;
-	check_pmc_busy();
-	pllb_div[1] = PMSDMMC_VAL;
-	check_pmc_busy();
-	pllb_div[2] = PMSDMMC1_VAL;
-	check_pmc_busy();
-	pllb_div[3] = PMSDMMC2_VAL;
-	check_pmc_busy();
-	pllb_div[4] = PMI2C0_VAL;
-	check_pmc_busy();
-	pllb_div[5] = PMI2C1_VAL;
-	check_pmc_busy();
-	pllb_div[6] = PMI2C2_VAL;
-	check_pmc_busy();
-	pllb_div[7] = PMI2C3_VAL;
-	check_pmc_busy();
-	pllb_div[8] = PMI2C4_VAL;
-	check_pmc_busy();
-	pllb_div[9] = PMSF_VAL;
-	check_pmc_busy();
-	pllb_div[10] = PMSPI_VAL;
-	check_pmc_busy();
-	pllb_div[11] = PMSPI1_VAL;
-	check_pmc_busy();
-	pllb_div[12] = PMNAND_VAL;
-	check_pmc_busy();
-	pllb_div[13] = PMNA12_VAL;
-	check_pmc_busy();
-	pllb_div[14] = PMADC_VAL;
-	check_pmc_busy();
-	pllb_div[15] = PMCSI0_VAL;
-	check_pmc_busy();
-	pllb_div[16] = PMCSI1_VAL;
-	check_pmc_busy();
-	pllb_div[17] = PMMALI_VAL;
-	check_pmc_busy();
-	pllb_div[18] = PMPAXI_VAL;
-	check_pmc_busy();
-	pllb_div[19] = PMSE_VAL;
-	check_pmc_busy();
-	pllb_div[20] = PMPCM0_VAL;
-	check_pmc_busy();
-	pllb_div[21] = PMPCM1_VAL;
-	check_pmc_busy();
-	pllb_div[22] = PMAHB_VAL;
-	check_pmc_busy();
-	pllb_div[23] = PMAPB0_VAL;
-	check_pmc_busy();
-	pllb_div[24] = PMPMB_VAL;
-	check_pmc_busy();
-
-}
-
-void save_plld_speed(unsigned int *plld_div)
-{
-	check_pmc_busy();
-	plld_div[0] = PMWMTVDU_VAL;/*vdu_div*/
-	check_pmc_busy();
-	plld_div[1]= PMCNMVDU_VAL;;/*cnm_div*/
-	check_pmc_busy();
-	plld_div[2] = PMWMTNA_VAL;/*na_vdu_div*/
-	check_pmc_busy();
-	plld_div[3] = PMCNMNA_VAL;/*na_cnm_div*/
-	check_pmc_busy();	
-}
-
-
-void restore_plla_speed(unsigned int *plla_div)
-{
-
-	auto_pll_divisor(DEV_ARM, SET_PLLDIV, 2, 300);
-	PMARM_VAL = plla_div[0];/*arm_div*/
-	wmb();
-	check_pmc_busy();
-	PML2C_VAL = plla_div[1];/*l2c_div*/
-	wmb();
-	check_pmc_busy();
-	PML2CTAG_VAL = plla_div[2];/*l2c_tag_div*/
-	wmb();
-	check_pmc_busy();
-	PML2CDATA_VAL = plla_div[3];/*l2c_data_div*/
-	wmb();
-	check_pmc_busy();
-	PML2CAXI_VAL = plla_div[4];/*l2c_axi_div*/
-	wmb();
-	check_pmc_busy();
-	PMDBGAPB_VAL = plla_div[5];/*dbg_apb_div*/
-	wmb();
-	check_pmc_busy();	
-	PMPMA_VAL = plla_div[6];
-	wmb();
-	check_pmc_busy();
-}
-
-void restore_pllb_speed(unsigned int *pllb_div)
-{
-	check_pmc_busy();
-	PMPWM_VAL = pllb_div[0];
-	wmb();
-	check_pmc_busy();
-#if 0	
-	PMSDMMC_VAL = pllb_div[1];
-	wmb();
-	check_pmc_busy();
-	PMSDMMC1_VAL = pllb_div[2];
-	wmb();
-	check_pmc_busy();
-	PMSDMMC2_VAL = pllb_div[3];
-	wmb();
-	check_pmc_busy();
-#endif	
-	PMI2C0_VAL = pllb_div[4];
-	wmb();
-	check_pmc_busy();
-	PMI2C1_VAL = pllb_div[5];
-	wmb();
-	check_pmc_busy();
-	PMI2C2_VAL = pllb_div[6];
-	wmb();
-	check_pmc_busy();
-	PMI2C3_VAL = pllb_div[7];
-	wmb();
-	check_pmc_busy();
-	PMI2C4_VAL = pllb_div[8];
-	wmb();
-	check_pmc_busy();
-	PMSF_VAL = pllb_div[9];
-	wmb();
-	check_pmc_busy();
-	PMSPI_VAL = pllb_div[10];
-	wmb();
-	check_pmc_busy();
-	PMSPI1_VAL = pllb_div[11];
-	wmb();
-	check_pmc_busy();
-	PMNAND_VAL = pllb_div[12];
-	wmb();
-	check_pmc_busy();
-	PMNA12_VAL = pllb_div[13];
-	wmb();
-	check_pmc_busy();
-	PMADC_VAL = pllb_div[14];
-	wmb();
-	check_pmc_busy();
-	PMCSI0_VAL = pllb_div[15];
-	wmb();
-	check_pmc_busy();
-	PMCSI1_VAL = pllb_div[16];
-	wmb();
-	check_pmc_busy();
-	PMMALI_VAL = pllb_div[17];
-	wmb();
-	check_pmc_busy();
-	PMPAXI_VAL = pllb_div[18];
-	wmb();
-	check_pmc_busy();
-	PMSE_VAL = pllb_div[19];
-	wmb();
-	check_pmc_busy();
-	PMPCM0_VAL = pllb_div[20];
-	wmb();
-	check_pmc_busy();
-	PMPCM1_VAL = pllb_div[21];
-	wmb();
-	check_pmc_busy();
-	PMAHB_VAL = pllb_div[22];
-	wmb();
-	check_pmc_busy();
-	PMAPB0_VAL = pllb_div[23];
-	wmb();
-	check_pmc_busy();
-	PMPMB_VAL = pllb_div[24];
-	wmb();
-	check_pmc_busy();
-
-}
-
-void restore_plld_speed(unsigned int *plld_div)
-{
-	check_pmc_busy();
-	PMWMTVDU_VAL = plld_div[0]; /*vdu_div*/
-	wmb();
-	check_pmc_busy();
-	PMCNMVDU_VAL = plld_div[1]; /*cnm_div*/
-	wmb();
-	check_pmc_busy();
-	PMWMTNA_VAL = plld_div[2]; /*na_vdu_div*/
-	wmb();
-	check_pmc_busy();
-	PMCNMNA_VAL = plld_div[3]; /*na_cnm_div*/
-	wmb();
-	check_pmc_busy();
-}
-
-
-/* wmt_pm_standby()
- *
- * Entry to the power-on sleep hibernation mode.
- */
-static void wmt_pm_standby(void)
-{
-	volatile unsigned int hib_phy_addr = 0,base = 0;    
-
-#ifdef CONFIG_CACHE_L2X0
-	__u32 power_ctrl;
-	
-	if( l2x0_onoff == 1)
-	{
-		outer_cache.flush_all();
-		outer_cache.disable();
-		outer_cache.inv_all();
-	}
-#endif
-
-	/* Get standby virtual address entry point */    
-	base = (unsigned int)ioremap_nocache(LOADER_ADDR, 0x10000);
-
-	exec_at = base + (DO_POWER_ON_SLEEP - LOADER_ADDR);
-	hib_phy_addr = *(unsigned int *) exec_at;
-	exec_at = base + (hib_phy_addr - LOADER_ADDR);
-
-	//led_light(3);
-	theKernel = (void (*)(int))exec_at;		/* set rom address */
-	theKernel(4);					        /* jump to rom */
-	//led_light(3);
-
-	iounmap((void __iomem *)base);
-
-#ifdef CONFIG_CACHE_L2X0
-	if( l2x0_onoff == 1)
-	{
-		if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1))
-		{
-			if(cpu_trustzone_enabled == 0)
-			{
-				/* l2x0 controller is disabled */
-				writel_relaxed(l2x0_aux, l2x0_base + L2X0_AUX_CTRL);
-
-				if( en_static_address_filtering == 1 )
-				{
-					writel_relaxed(address_filtering_end, l2x0_base + 0xC04);
-					writel_relaxed((address_filtering_start | 0x01), l2x0_base + 0xC00);
-				}
-
-				writel_relaxed(0x110, l2x0_base + L2X0_TAG_LATENCY_CTRL);
-				writel_relaxed(0x110, l2x0_base + L2X0_DATA_LATENCY_CTRL);
-				power_ctrl = readl_relaxed(l2x0_base + L2X0_POWER_CTRL) | L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN;
-				writel_relaxed(power_ctrl, l2x0_base + L2X0_POWER_CTRL);
-
-				writel_relaxed(l2x0_prefetch_ctrl, l2x0_base + L2X0_PREFETCH_CTRL);
-
-				outer_cache.inv_all();
-
-				/* enable L2X0 */
-				writel_relaxed(1, l2x0_base + L2X0_CTRL);
-			}
-			else
-			{
-				/* l2x0 controller is disabled */
-				wmt_smc(WMT_SMC_CMD_PL310AUX, l2x0_aux);
-				
-				if( en_static_address_filtering == 1 )
-				{
-					wmt_smc(WMT_SMC_CMD_PL310FILTER_END, address_filtering_end);
-					wmt_smc(WMT_SMC_CMD_PL310FILTER_START, (address_filtering_start | 0x01));
-				}
-
-				wmt_smc(WMT_SMC_CMD_PL310TAG_LATENCY, 0x110);
-				wmt_smc(WMT_SMC_CMD_PL310DATA_LATENCY, 0x110);
-				power_ctrl = readl_relaxed(l2x0_base + L2X0_POWER_CTRL) | L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN;
-				wmt_smc(WMT_SMC_CMD_PL310POWER, power_ctrl);
-
-				wmt_smc(WMT_SMC_CMD_PL310PREFETCH, l2x0_prefetch_ctrl);
-
-				outer_cache.inv_all();
-
-				/* enable L2X0 */
-				wmt_smc(WMT_SMC_CMD_PL310CTRL, 1);
-			}
-		
-		}
-	
-	}
-#endif
-}
-
-extern void wmt_assem_suspend(void);
-extern void wmt_assem_secure_suspend(void);
-
-extern char use_dvfs;
-/* wmt_pm_suspend()
- *
- * Entry to the power-off suspend hibernation mode.
- */
-
-static void wmt_pm_suspend(void)
-{
-	unsigned int saved[SAVED_SIZE];
-	int result;
-	unsigned int plla_div[7];
-	
-	unsigned int pllb_div[25];
-
-	unsigned int plld_div[4];
-
-
-#ifdef CONFIG_CACHE_L2X0
-	__u32 power_ctrl;
-#endif
-
-/* FIXME */
-#if 1
-	result = PM_device_PostSuspend();
-	if (result)
-		printk("PM_device_PostSuspend fail\n");
-#endif
-
-#ifdef CONFIG_CACHE_L2X0
-	if( l2x0_onoff == 1)
-	{
-		outer_cache.flush_all();
-		outer_cache.disable();
-		outer_cache.inv_all();
-	}
-#endif
-
-	SAVE(OSTW);	                /* save vital registers */
-	SAVE(OSTI);	    
-	SAVE(PMCEL);	            /* save clock gating */
-	SAVE(PMCEU);
-	SAVE(PMCE2);
-	SAVE(PMCE3);
-
-	*(volatile unsigned int *)0xfe018008 |= 0x03030303; //scu output pm	
-
-	//for single core
-#ifndef CONFIG_SMP	
-	HSP7_VAL = 0xffffffb8;
-	while(HSP7_VAL != 0xffffffb8);
-	asm("sev" : : "r" (0));	
-#endif		
-	save_plld_speed(plld_div); /*save plld clock register*/
-
-	save_pllb_speed(pllb_div); /*save pllb clock register*/
-	if (!use_dvfs)
-		save_plla_speed(plla_div);
-	//led_light(2);	
-
-	if(cpu_trustzone_enabled == 1)	
-		wmt_assem_secure_suspend();
-	else
-		wmt_assem_suspend();
-
-	RESTORE(PMCE3);
-	RESTORE(PMCE2);
-	RESTORE(PMCEU);             /* restore clock gating */
-	RESTORE(PMCEL);             
-	RESTORE(OSTI);              /* restore vital registers */
-	RESTORE(OSTW);
-	wmt_serial_set_reg();
-
-	if (!use_dvfs)
-		restore_plla_speed(plla_div);	/* restore plla clock register */
-
-	restore_pllb_speed(pllb_div);	/* restore pllb clock register */
-	
-	restore_plld_speed(plld_div);	/* restore plld clock register */
-
-	PMPB_VAL |= 1;				/* enable soft power */
-	
-	//* ((volatile unsigned int *)0xfe140054) = 0x0;
-
-#ifdef CONFIG_CACHE_L2X0
-	if( l2x0_onoff == 1)
-	{
-		if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1))
-		{
-			if(cpu_trustzone_enabled == 0)
-			{
-				/* l2x0 controller is disabled */
-				writel_relaxed(l2x0_aux, l2x0_base + L2X0_AUX_CTRL);
-			
-				if( en_static_address_filtering == 1 )
-				{
-					writel_relaxed(address_filtering_end, l2x0_base + 0xC04);
-					writel_relaxed((address_filtering_start | 0x01), l2x0_base + 0xC00);
-				}
-
-				writel_relaxed(0x110, l2x0_base + L2X0_TAG_LATENCY_CTRL);
-				writel_relaxed(0x110, l2x0_base + L2X0_DATA_LATENCY_CTRL);
-				power_ctrl = readl_relaxed(l2x0_base + L2X0_POWER_CTRL) | L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN;
-				writel_relaxed(power_ctrl, l2x0_base + L2X0_POWER_CTRL);
-
-				writel_relaxed(l2x0_prefetch_ctrl, l2x0_base + L2X0_PREFETCH_CTRL);
-
-	  			outer_cache.inv_all(); 
-
-				/* enable L2X0 */
-				writel_relaxed(1, l2x0_base + L2X0_CTRL);
-			}
-			else
-			{
-				/* l2x0 controller is disabled */
-				wmt_smc(WMT_SMC_CMD_PL310AUX, l2x0_aux);
-			
-				if( en_static_address_filtering == 1 )
-				{
-					wmt_smc(WMT_SMC_CMD_PL310FILTER_END, address_filtering_end);
-					wmt_smc(WMT_SMC_CMD_PL310FILTER_START, (address_filtering_start | 0x01));
-				}
-
-				wmt_smc(WMT_SMC_CMD_PL310TAG_LATENCY, 0x110);
-				wmt_smc(WMT_SMC_CMD_PL310DATA_LATENCY, 0x110);
-				power_ctrl = readl_relaxed(l2x0_base + L2X0_POWER_CTRL) | L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN;
-				wmt_smc(WMT_SMC_CMD_PL310POWER, power_ctrl);
-
-				wmt_smc(WMT_SMC_CMD_PL310PREFETCH, l2x0_prefetch_ctrl);
-
-	  			outer_cache.inv_all(); 
-
-				/* enable L2X0 */
-				wmt_smc(WMT_SMC_CMD_PL310CTRL, 1);
-			}
-		}
-	}
-#endif
-
-	result = PM_device_PreResume();
-	if (result != 0)
-		printk("PM_device_PreResume fail\n");
-}
-
-/* wmt_pm_enter()
- *
- * To Finally enter the sleep state.
- *
- * Note: Only support PM_SUSPEND_STANDBY and PM_SUSPEND_MEM
- */
-int wmt_trigger_resume_kpad = 0;
-int wmt_trigger_resume_notify = 0;
-
-void wmt_resume_kpad(void)
-{
-	DPRINTK(KERN_ALERT "\n[%s]power key pressed\n",__func__);
-	powerKey_is_pressed = 1; 
-	input_report_key(kpadPower_dev, KEY_POWER, 1); /*power key is pressed*/
-	input_sync(kpadPower_dev);
-	pressed_jiffies = jiffies;
-	mod_timer(&kpadPower_timer, jiffies + power_button_timeout);
-}
-
-void wmt_resume_notify(void)
-{
-	input_report_key(kpadPower_dev, KEY_POWER, 1); /*power key is pressed*/
-	input_sync(kpadPower_dev);
-	input_report_key(kpadPower_dev, KEY_POWER, 0); //power key is released
-	input_sync(kpadPower_dev);		
-}
-
-static int wmt_pm_enter(suspend_state_t state)
-{
-	unsigned int status, status_i;
-//	unsigned int wakeup_notify;
-
-	int notify_framwork = 0;
-	
-	if (!((state == PM_SUSPEND_STANDBY) || (state == PM_SUSPEND_MEM))) {
-		printk(KERN_ALERT "%s, Only support PM_SUSPEND_STANDBY and PM_SUSPEND_MEM\n", DRIVER_NAME);
-		return -EINVAL;
-	}
-
-	/* only enable fiq in normal operation */
-	//local_fiq_disable();
-	//local_irq_disable();
-	/* disable system OS timer */
-	OSTC_VAL &= ~OSTC_ENABLE;
-  
-	
-	/* FIXME, 2009/09/15 */
-	//PMCDS_VAL = PMCDS_VAL;
-	
-	WMT_WAKE_UP_EVENT = 0;
-	/*set power button debounce value*/
-	wmt_pwrbtn_debounce_value(resume_debounce_value);
-
-	/*
-	 * We use pm_standby as apm_standby for power-on hibernation.
-	 * but we still suspend memory in both case.
-	 */
-
-	if (state == PM_SUSPEND_STANDBY)
-		wmt_pm_standby();    /* Go to standby mode*/
-	else
-		wmt_pm_suspend();    /* Go to suspend mode*/
-
-	/*set power button debounce value*/
-	wmt_pwrbtn_debounce_value(power_on_debounce_value);
-
-	/*
-	 * Clean wakeup source
-	 */
-
-	status = PMWS_VAL;
-	status_i = PMCIS_VAL;
-	WMT_WAKE_UP_EVENT = (PMWS_VAL & (WK_TRG_EN_VAL | 0x4000));//wmt_pm_enter
-	status = (status & Wake_up_sts_mask);
-	
-	PMCIS_VAL = PMCIS_VAL;	
-	
-	//notify_framwork=1;
-
-#ifdef KEYPAD_POWER_SUPPORT	
-	if (status & (1 << WKS_PWRBTN)) {
-		wmt_trigger_resume_kpad = 1;	
-	}
-#endif	
-
-	if (status & (1 << WKS_WK5)){  
-		DPRINTK(KERN_ALERT "\n[%s]WK5 event\n",__func__);
-		if (var_fake_power_button & (1 << WKS_WK5))
-			notify_framwork=1;
-	}
-
-	if (status & (1 << WKS_SD0)){  
-		DPRINTK(KERN_ALERT "\n[%s]SD0 event\n",__func__);
-		if (var_fake_power_button & (1 << WKS_SD0))
-			notify_framwork=1; 
-	}
-
-	if (status & (1 << WKS_HDMICEC)){  
-		DPRINTK(KERN_ALERT "\n[%s]HDMICEC event\n",__func__);
-		if (var_fake_power_button & (1 << WKS_HDMICEC))
-			notify_framwork=1;
-	}
-	
-	if (status & (1 << WKS_SD2)){  
-		DPRINTK(KERN_ALERT "\n[%s]SD2 event\n",__func__);
-		if (var_fake_power_button & (1 << WKS_SD2))
-			notify_framwork=1;
-	}		
-
-	if (status & (1 << WKS_DCDET)){  
-		DPRINTK(KERN_ALERT "\n[%s]DCDET event\n",__func__);
-		if (var_fake_power_button & (1 << WKS_DCDET))
-			notify_framwork=1;
-	}			
-
-	if (status & (1 << WKS_SD3)){  
-		DPRINTK(KERN_ALERT "\n[%s]SD3 event\n",__func__);
-		if (var_fake_power_button & (1 << WKS_SD3))
-			notify_framwork=1; 
-	}
-
-	if (status & (1 << WKS_USBSW0)){  
-		DPRINTK(KERN_ALERT "\n[%s]USBSW0 event\n",__func__);
-		if (var_fake_power_button & (1 << WKS_USBSW0))
-			notify_framwork=1;
-	}
-
-#ifdef CIR_WAKEUP_SUPPORT   
-	if (status & (1 << WKS_CIR)){  
-		DPRINTK(KERN_ALERT "\n[%s]CIR event\n",__func__);
-		if (var_fake_power_button & (1 << WKS_CIR))
-			notify_framwork=1;
-	}
-#endif		
-
-#ifdef CONFIG_USB_GADGET_WMT
-/*UDC wake up source*/
-	if (status & (1 << WKS_UDC)){
-		DPRINTK(KERN_ALERT "\n[%s]UDC event\n",__func__);
-		if (var_fake_power_button & (1 << WKS_UDC))
-			notify_framwork=1;
-	}
-#endif
-
-#ifdef CONFIG_USB   
-//UHC  
-	if (status & (1 << WKS_UHC)){
-		DPRINTK(KERN_ALERT "\n[%s]UHC event\n",__func__);
-		if (var_fake_power_button & (1 << WKS_UHC))
-			notify_framwork=1;
-	}
-	
-	if (status & (1 << WKS_USBOC3)){
-		DPRINTK(KERN_ALERT "\n[%s]USBOC3 event\n",__func__);
-		if (var_fake_power_button & (1 << WKS_USBOC3))
-			notify_framwork=1;
-	}
-
-	if (status & (1 << WKS_USBOC2)){
-		DPRINTK(KERN_ALERT "\n[%s]USBOC2 event\n",__func__);
-		if (var_fake_power_button & (1 << WKS_USBOC2))
-			notify_framwork=1;
-	}
-
-	if (status & (1 << WKS_USBOC1)){
-		DPRINTK(KERN_ALERT "\n[%s]USBOC1 event\n",__func__);
-		if (var_fake_power_button & (1 << WKS_USBOC1))
-			notify_framwork=1;
-	}
-
-	if (status & (1 << WKS_USBOC0)){
-		DPRINTK(KERN_ALERT "\n[%s]USBOC0 event\n",__func__);
-		if (var_fake_power_button & (1 << WKS_USBOC0))
-			notify_framwork=1;
-	}		
-#endif
-	
-#ifdef RTC_WAKEUP_SUPPORT
-	if (status & (1 << WKS_RTC)){
-		DPRINTK(KERN_ALERT "\n[%s]RTC event\n",__func__);
-		if (var_fake_power_button & (1 << WKS_RTC))
-			notify_framwork=1;
-	}
-#endif
-
-	if (status & (1 << WKS_CIRIN)){
-		DPRINTK(KERN_ALERT "\n[%s]CIRIN event\n",__func__);
-		if (var_fake_power_button & (1 << WKS_CIRIN))
-			notify_framwork=1;
-	}
-
-#ifdef CONFIG_USB_GADGET_WMT	
-	/*UDC2 wake up source*/
-	if (status & (1 << WKS_USBATTA0)){
-		DPRINTK(KERN_ALERT "\n[%s]UDCATTA0 event\n",__func__);
-		if (var_fake_power_button & (1 << WKS_USBATTA0))
-			notify_framwork=1;
-	}
-#endif
-
-	if(status & (1 << WKS_SUS1)){
-		DPRINTK(KERN_ALERT "\n[%s]SUS1 event\n",__func__);
-		if (var_fake_power_button & (1 << WKS_SUS1))
-			notify_framwork=1;
-	}
-
-	if(status & (1 << WKS_SUS0)){
-		DPRINTK(KERN_ALERT "\n[%s]SUS0 event\n",__func__);
-		if (var_fake_power_button & (1 << WKS_SUS0))
-			notify_framwork=1;
-	}
-	
-	if(status & (1 << WKS_WK4)){
-		DPRINTK(KERN_ALERT "\n[%s]WK4 event\n",__func__);
-		if (var_fake_power_button & (1 << WKS_WK4))
-			notify_framwork=1;
-	}
-
-	if (status & (1 << WKS_WK3)){  
-		DPRINTK(KERN_ALERT "\n[%s]WK3 event\n",__func__);
-		if (var_fake_power_button & (1 << WKS_WK3))
-			notify_framwork=1;	
-	}
-	
-	if (status & (1 << WKS_WK2)){  
-		DPRINTK(KERN_ALERT "\n[%s]WK2 event\n",__func__);
-		if (var_fake_power_button & (1 << WKS_WK2))
-			notify_framwork=1;
-	}		
-	
-	if (status & (1 << WKS_WK0)){  		
-		DPRINTK(KERN_ALERT "\n[%s]WK0 event\n",__func__);
-		if (var_fake_power_button & (1 << WKS_WK0))
-			notify_framwork=1;	
-	}
-
-	if (notify_framwork) {
-		wmt_trigger_resume_notify = 1;
-	}
-
-#ifdef RTC_WAKEUP_SUPPORT
-	RTAS_VAL = 0x0;       	/* Disable RTC alarm */
-#endif
-
-	/*
-	 * Force to do once CPR for system.
-	 */
-	OSM1_VAL = wmt_read_oscr() + LATCH;
-	OSTC_VAL |= OSTC_ENABLE;
-
-	//udelay(200);  /* delay for resume not complete */
-	
-	/*
-	 * disable trigger wakeup event
-	 */
-	do {
-		WK_TRG_EN_VAL = 0x4000;
-	} while(WK_TRG_EN_VAL != 0x4000);
-
-	return 0;
-}
-
-
-/* wmt_pm_prepare()
- *
- * Called after processes are frozen, but before we shut down devices.
- */
-static int wmt_pm_prepare(void)
-{
-	unsigned int date, time;
-	struct timeval tv;
-
-	/*
-	 * Estimate time zone so that wmt_pm_finish can update the GMT time
-	 */
-
-	rtc2sys = 0;
-    
-	if ((*(volatile unsigned int *)SYSTEM_CFG_CTRL_BASE_ADDR)>0x34260102) {        
-		wmt_read_rtc(&date, &time);
-	}
-
-	do_gettimeofday(&tv);
-
-	rtc2sys = mktime(RTCD_YEAR(date) + ((RTCD_CENT(date) * 100) + 2000),
-						RTCD_MON(date),
-						RTCD_MDAY(date),
-						RTCT_HOUR(time),
-						RTCT_MIN(time),
-						RTCT_SEC(time));
-	rtc2sys = rtc2sys-tv.tv_sec;
-	if (rtc2sys > 0)
-		rtc2sys += 10;
-	else
-		rtc2sys -= 10;
-	rtc2sys = rtc2sys/60/60;
-	rtc2sys = rtc2sys*60*60;
-
-	return 0;
-}
-
-/* wmt_pm_finish()
- *
- * Called after devices are re-setup, but before processes are thawed.
- */
-static void wmt_pm_finish(void)
-{
-	unsigned int date, time;
-	struct timespec tv;
-
-#if 0
-	struct rtc_time tm;
-	unsigned long tmp = 0;
-	struct timeval tv1;
-#endif
-	/* FIXME:
-	 * There are a warning when call iounmap here,
-	 * please iounmap the mapped virtual ram later */
-	// iounmap((void *)exec_at);
-
-	/*
-	 * Update kernel time spec.
-	 */
-	if ((*(volatile unsigned int *)SYSTEM_CFG_CTRL_BASE_ADDR)>0x34260102) {        
-		wmt_read_rtc(&date, &time);
-	}
-
-	tv.tv_nsec = 0;
-	tv.tv_sec = mktime(RTCD_YEAR(date) + ((RTCD_CENT(date) * 100) + 2000),
-						RTCD_MON(date),
-						RTCD_MDAY(date),
-						RTCT_HOUR(time),
-						RTCT_MIN(time),
-						RTCT_SEC(time));
-	/* RTC stores local time, adjust GMT time, tv */
-	tv.tv_sec = tv.tv_sec-rtc2sys;
-	do_settimeofday(&tv);
-
-}
-
-static int wmt_pm_valid(suspend_state_t state)
-{
-	switch (state) {
-	case PM_SUSPEND_STANDBY:
-	case PM_SUSPEND_MEM:
-		return 1;
-	default:
-		return 0;
-	}
-}
-
-static struct platform_suspend_ops wmt_pm_ops = {
-	.valid			= wmt_pm_valid,
-	.prepare        = wmt_pm_prepare,
-	.enter          = wmt_pm_enter,
-	.finish         = wmt_pm_finish,
-};
-
-#if 0
-#if defined(SOFT_POWER_SUPPORT) && defined(CONFIG_PROC_FS)
-
-static int procfile_read(char *page, char **start, off_t off, int count, int *eof, void *data)
-{
-	int len = 0;
-	len = sprintf(page, "%d\n", softpower_data);
-	return len;
-}
-
-
-static int procfile_write(struct file *file, const char *buffer, unsigned long count, void *data)
-{
-	char *endp;
-
-	softpower_data = simple_strtoul(buffer, &endp, 0);
-
-	if (softpower_data != 0)
-		softpower_data = 1;
-
-/*	printk("%s: %s, softpower_data=[0x%X]\n", DRIVER_NAME, __FUNCTION__, softpower_data );*/
-/*	printk("%s: return [%d]\n", DRIVER_NAME, (count + endp - buffer ) );*/
-
-	return (count + endp - buffer);
-}
-
-#endif	/* defined(SOFT_POWER_SUPPORT) && defined(CONFIG_PROC_FS)*/
-#endif
-
-#ifdef KEYPAD_POWER_SUPPORT
-static inline void kpadPower_timeout(unsigned long fcontext)
-{
-
-	struct input_dev *dev = (struct input_dev *) fcontext;
-	//printk("-------------------------> kpadPower time out\n");
-	time2 = jiffies_to_msecs(jiffies);
-	if ((time2 - time1) > 2000 && sync_counter > 4) { //2000 msec
-		schedule_work(&PMC_sync);
-		//DPRINTK("1[%s]dannier count=%d jiffies=%lu, %d\n",__func__, sync_counter, jiffies,jiffies_to_msecs(jiffies));
-	} //else
-		//DPRINTK("0[%s]dannier count=%d jiffies=%lu, %d\n",__func__, sync_counter, jiffies,jiffies_to_msecs(jiffies));
-	DPRINTK(KERN_ALERT "\n[%s]kpadPower time out GPIO_ID_GPIO_VAL = %x\n",__func__,GPIO_ID_GPIO_VAL);
-	if(!kpadPower_dev)
-		return;
-
-	spin_lock_irq(&kpadPower_lock);
-
-	if(!(PMPB_VAL & BIT24)) {
-		input_report_key(dev, KEY_POWER, 0); //power key is released
-		input_sync(dev);
-		powerKey_is_pressed = 0;
-		wmt_pwrbtn_debounce_value(power_on_debounce_value);
-		DPRINTK("[%s]power key released\n",__func__);
-		sync_counter = 0;
-	}else {
-		DPRINTK("[%s]power key not released\n",__func__);
-		mod_timer(&kpadPower_timer, jiffies + power_button_timeout);
-		sync_counter++;
-	}
-
-	spin_unlock_irq(&kpadPower_lock);
-
-}
-#endif
-
-static int wmt_wakeup_pm_notify(struct notifier_block *nb, unsigned long event,
-	void *dummy)
-{
-	unsigned long	pm_lock_flags;
-	
-	spin_lock_irqsave(&wmt_pm_lock, pm_lock_flags);	
-	if (event == PM_SUSPEND_PREPARE) {
-		dynamic_pmc_intr = INT_TRG_EN_VAL;
-		do {
-			INT_TRG_EN_VAL = 0;
-		} while (INT_TRG_EN_VAL != 0);	
-				
-		PMWS_VAL = PMWS_VAL;
-				
-		do {
-			WK_TRG_EN_VAL = (Wake_up_sts_mask | dynamic_wakeup);
-		} while (WK_TRG_EN_VAL != (Wake_up_sts_mask | dynamic_wakeup));		
-		
-	} else if (event == PM_POST_SUSPEND) {		
-		do {
-			INT_TRG_EN_VAL = dynamic_pmc_intr;
-		} while (INT_TRG_EN_VAL != dynamic_pmc_intr);
-		
-		do {
-			WK_TRG_EN_VAL = 0x4000;
-		} while (WK_TRG_EN_VAL != 0x4000);				
-		
-	}
-	spin_unlock_irqrestore(&wmt_pm_lock, pm_lock_flags);
-	return NOTIFY_OK;
-}
-
-static struct notifier_block wmt_pmc_pm_notify = {
-	.notifier_call = wmt_wakeup_pm_notify,
-};
-#ifdef CONFIG_HIBERNATION
-static int wmt_hibernation_begin(void)
-{
-	printk("\n!!! %s:Enter\n",__FUNCTION__);
-	disable_hlt();
-	return 0;
-}
-unsigned int saved[SAVED_SIZE];
-unsigned int plla_div[7];
-unsigned int pllb_div[25];
-unsigned int plld_div[4];
-#ifdef CONFIG_CACHE_L2X0
-	__u32 power_cntrl;
-#endif
-
-static int wmt_hibernation_pre_snapshot(void)
-{
-	int result;
-#ifdef CONFIG_CACHE_L2X0
-	volatile unsigned int l2x0_base;
-#endif
-	printk("\n!!! %s:Enter\n",__FUNCTION__);
-#if 1
-	result = PM_device_PostSuspend();
-	if (result)
-		printk("\n %s : PM_device_PostSuspend fail\n", __FUNCTION__);
-#endif
-#ifdef CONFIG_CACHE_L2X0
-	if( l2x0_onoff == 1)
-	{
-		l2x0_base = (volatile unsigned int) ioremap(0xD9000000, SZ_4K);
-		outer_cache.flush_all();
-		outer_cache.disable();
-		outer_cache.inv_all();
-	}
-#endif	
-	SAVE(OSTW);	                /* save vital registers */
-	SAVE(OSTI);	    
-	SAVE(PMCEL);	            /* save clock gating */
-	SAVE(PMCEU);
-	SAVE(PMCE2);
-	SAVE(PMCE3);
-	//for single core, sev to make cpu1 out of  wfe.
-	#ifndef CONFIG_SMP	
-		HSP7_VAL = 0xffffffb8;
-		while(HSP7_VAL != 0xffffffb8);
-		asm("sev" : : "r" (0)); 
-	#endif
-	save_plld_speed(plld_div); /*save plld clock register*/
-	save_pllb_speed(pllb_div); /*save pllb clock register*/
-	if (!use_dvfs)
-		save_plla_speed(plla_div);
-	return 0;
-}
-static void wmt_hibernation_leave(void)
-{
-int result;
-#ifdef CONFIG_CACHE_L2X0
-		volatile unsigned int l2x0_base;
-#endif
-	printk("\n!!! %s:Enter\n",__FUNCTION__);
-	RESTORE(PMCE3);
-	RESTORE(PMCE2);
-	RESTORE(PMCEU);             /* restore clock gating */
-	RESTORE(PMCEL);             
-	RESTORE(OSTI);              /* restore vital registers */
-	RESTORE(OSTW);
-	wmt_serial_set_reg();
-	if (!use_dvfs)
-		restore_plla_speed(plla_div);	/* restore plla clock register */
-	restore_pllb_speed(pllb_div);	/* restore pllb clock register */
-	restore_plld_speed(plld_div);	/* restore plld clock register */
-	PMPB_VAL |= 1;				/* enable soft power */
-#ifdef CONFIG_CACHE_L2X0
-	if( l2x0_onoff == 1)
-	{
-		l2x0_base = (volatile unsigned int) ioremap(0xD9000000, SZ_4K);
-		if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1))
-		{
-			writel_relaxed(l2x0_aux, l2x0_base + L2X0_AUX_CTRL);
-			if( en_static_address_filtering == 1 )
-			{
-				writel_relaxed(address_filtering_end, l2x0_base + 0xC04);
-				writel_relaxed((address_filtering_start | 0x01), l2x0_base + 0xC00);
-			}
-			writel_relaxed(0x110, l2x0_base + L2X0_TAG_LATENCY_CTRL);
-			writel_relaxed(0x110, l2x0_base + L2X0_DATA_LATENCY_CTRL);
-			power_cntrl = readl_relaxed(l2x0_base + L2X0_POWER_CTRL) | L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN;
-			writel_relaxed(power_cntrl, l2x0_base + L2X0_POWER_CTRL);
-			writel_relaxed(l2x0_prefetch_ctrl, l2x0_base + L2X0_PREFETCH_CTRL);
-  			outer_cache.inv_all(); 
-			writel_relaxed(1, l2x0_base + L2X0_CTRL);
-		}
-		iounmap((void __iomem *)l2x0_base);
-	}
-#endif
-	result = PM_device_PreResume();
-	if (!result)
-		printk("PM_device_PreResume fail\n");
-}
-static void wmt_hibernation_finish(void)
-{
-	extern int env_cache_flush(void);
-	int ret;
-	printk("\n!!! %s:Enter\n",__FUNCTION__);
-	ret = env_cache_flush();
-	if(!ret)
-		printk("env_cache_flush success.\n");
-}
-static void wmt_hibernation_end(void)
-{
-	printk("\n!!! %s:Enter\n",__FUNCTION__);
-	enable_hlt();
-}
-static int wmt_hibernation_prepare(void)
-{
-	printk("\n!!! %s:Enter\n",__FUNCTION__);
-	return 0;
-}
-static int wmt_hibernation_enter(void)
-{
-	int std_stress_test = 0;
-	int ret;
-	char buf_env[80];
-	int varlen = sizeof(buf_env);
-	printk("\n!!! %s:Enter\n",__FUNCTION__);
-	ret = wmt_getsyspara("wmt.std.stress", buf_env, &varlen);
-	if (ret == 0)
-		sscanf(buf_env, "%d", &std_stress_test);
-	if(std_stress_test) {
-		printk(KERN_CRIT "\n Do STD Stress Test \n");
-		machine_restart(NULL);
-	}else{
-		printk(KERN_CRIT "\n No Stress Test \n");
-		machine_power_off();
-	}
-	return 0;
-}
-static int wmt_hibernation_pre_restore(void)
-{
-	printk("\n!!! %s:Enter\n",__FUNCTION__);
-	return 0;
-}
-static void wmt_hibernation_restore_cleanup(void)
-{
-	printk("\n!!! %s:Enter\n",__FUNCTION__);
-}
-static const struct platform_hibernation_ops wmt_hibernation_ops = {
-	.begin			= wmt_hibernation_begin,
-	.end			= wmt_hibernation_end,
-	.pre_snapshot		= wmt_hibernation_pre_snapshot,
-	.finish			= wmt_hibernation_finish,
-	.prepare		= wmt_hibernation_prepare,
-	.enter			= wmt_hibernation_enter,
-	.leave			= wmt_hibernation_leave,
-	.pre_restore		= wmt_hibernation_pre_restore,
-	.restore_cleanup	= wmt_hibernation_restore_cleanup,
-};
-#endif
-/*
- * Initialize power management interface
- */
-static int __init wmt_pm_init(void)
-{
-	struct apm_dev_s *pm_dev;
-	char buf[256];
-	char varname[] = "wmt.pwbn.param";
-	int varlen = 256;
-	char wake_buf[100];
-	char wake_varname[] = "wmt.pmc.param";
-	int wake_varlen = 100;
-#ifdef CONFIG_BATTERY_WMT
-	char bat_varname[] = "wmt.io.bat";
-#endif
-
-#ifdef KEYPAD_POWER_SUPPORT
-	int i;
-
-	kpadPower_dev = input_allocate_device();
-	if(kpadPower_dev) {
-		//Initial the static variable
-		spin_lock_init(&kpadPower_lock);
-		powerKey_is_pressed = 0;
-		pressed_jiffies = 0;
-		init_timer(&kpadPower_timer);
-		kpadPower_timer.function = kpadPower_timeout;
-		kpadPower_timer.data = (unsigned long)kpadPower_dev;
-
-		/* Register an input event device. */
-		set_bit(EV_KEY,kpadPower_dev->evbit);
-		for (i = 0; i < KPAD_POWER_FUNCTION_NUM; i++)
-		set_bit(kpadPower_codes[i], kpadPower_dev->keybit);
-
-		kpadPower_dev->name = "kpadPower",
-		kpadPower_dev->phys = "kpadPower",
-
-
-		kpadPower_dev->keycode = kpadPower_codes;
-		kpadPower_dev->keycodesize = sizeof(unsigned int);
-		kpadPower_dev->keycodemax = KPAD_POWER_FUNCTION_NUM;
-
-		/*
-		* For better view of /proc/bus/input/devices
-		*/
-		kpadPower_dev->id.bustype = 0;
-		kpadPower_dev->id.vendor  = 0;
-		kpadPower_dev->id.product = 0;
-		kpadPower_dev->id.version = 0;
-		input_register_device(kpadPower_dev);
-	} else
-		printk("[wmt_pm_init]Error: No memory for registering Kpad Power\n");
-#endif
-
-	register_pm_notifier(&wmt_pmc_pm_notify);
-
-//gri
-	if (! pmlock_1st_flag) {
-	  pmlock_1st_flag = 1;
-	  spin_lock_init(&wmt_pm_lock);
-	}
-	if (! pmlock_intr_1st_flag) {
-	  pmlock_intr_1st_flag = 1;
-	  spin_lock_init(&wmt_pm_intr_lock);
-	}
-	
-	if (wmt_getsyspara(wake_varname, wake_buf, &wake_varlen) == 0) {
-		sscanf(wake_buf,"%x:%x:%x:%x:%x",
-						&var_wake_en,
-						&var_wake_param,
-						&var_wake_type,
-						&var_wake_type2,
-						&var_fake_power_button);		
-	}
-	else {
-		var_wake_en = 1;
-		var_wake_param = 0x0040C080;	//cir rtc pwrbtn dcdet(cirin)
-		var_wake_type =  0x40000000;
-		var_wake_type2 = 0x0;
-		var_fake_power_button = 0x00400080;
-	}
-	
-	Wake_up_sts_mask = (var_wake_param | BIT14); // add power button 
-	
-	var_1st_flag = 1;
-	
-	printk("[%s] var define var_wake_en=%x var_wake_param=%x var_wake_type=%x var_wake_type2=%x var_fake_power_button=%x\n",
-	__func__, var_wake_en, var_wake_param, var_wake_type, var_wake_type2, var_fake_power_button);
-
-#if 0//test pmc_enable_wakeup_event
-	do {
-		WK_EVT_TYPE_VAL = 0x33333333;
-	}	while (WK_EVT_TYPE_VAL != 0x33333333);
-	
-	{
-		unsigned int i_temp, en_temp, en_type;
-		i_temp = 0;
-		en_type = 0;
-		do {
-			en_temp = (var_wake_param & (1 << i_temp));
-			if (en_temp) {
-				if (en_temp < 0x100)
-					en_type = ((var_wake_type >> (i_temp << 2)) & 0xf);
-				else if(en_temp >= 0x1000000)
-					en_type = ((var_wake_type2 >> ((i_temp - 24) << 2)) & 0xf);
-				else if(en_temp == 0x200000)
-					en_type = ((var_wake_type >> 24) & 0xf);
-				else
-					en_type = 3;
-				printk("en_temp 0x%x en_type 0x%x\n",i_temp,en_type);
-				pmc_enable_wakeup_event(i_temp, en_type);
-			}
-			i_temp++;
-		} while (i_temp < 32);
-	}
-#else
-	{
-		unsigned int i_temp;
-		do {
-			PMWT_VAL = var_wake_type;
-		}	while(PMWT_VAL != var_wake_type);
-		do {
-			PMWTC_VAL = var_wake_type2;
-		}	while(PMWTC_VAL != var_wake_type2);	
-		
-		if (var_wake_param & BIT21)
-			i_temp = 0x33433333;
-		else
-			i_temp = 0x33333333;
-		do {
-			WK_EVT_TYPE_VAL = i_temp;				
-		}	while(WK_EVT_TYPE_VAL != i_temp);		
-	}
-#endif	
-
-	printk("[%s] WK_TRG_EN_VAL=0x%x PMWT_VAL=0x%x PMWTC_VAL=0x%x WK_EVT_TYPE_VAL=0x%x\n",
-	__func__, WK_TRG_EN_VAL, PMWT_VAL, PMWTC_VAL, WK_EVT_TYPE_VAL);
-
-#ifdef CONFIG_BATTERY_WMT
-	if (wmt_getsyspara(bat_varname, buf, &varlen) == 0) {
-		sscanf(buf,"%x", &battery_used);
-	}
-	printk("[%s] battery_used = %x\n",__func__, battery_used);
-#endif
-
-#ifdef CONFIG_CACHE_L2X0
-	if(wmt_getsyspara("wmt.l2c.param",buf,&varlen) == 0)
-		sscanf(buf,"%d:%x:%x:%d:%x:%x",&l2x0_onoff, &l2x0_aux, &l2x0_prefetch_ctrl, &en_static_address_filtering, &address_filtering_start, &address_filtering_end);
-        if( l2x0_onoff == 1)
-                l2x0_base = (volatile unsigned int) ioremap(0xD9000000, SZ_4K);
-
-	if (wmt_getsyspara("wmt.secure.param",buf,&varlen) == 0)
-		sscanf(buf,"%d",&cpu_trustzone_enabled);
-	if(cpu_trustzone_enabled != 1)
-		cpu_trustzone_enabled = 0;
-#endif
-
-	/* Press power button (either hard-power or soft-power) will trigger a power button wakeup interrupt*/
-	/* Press reset button will not trigger any PMC wakeup interrupt*/
-	/* Hence, force write clear all PMC wakeup interrupts before request PMC wakeup IRQ*/
-
-	//move to wload
-	//PMWS_VAL = PMWS_VAL;
-	//PMCIS_VAL = PMCIS_VAL;
-
-	INIT_WORK(&PMC_shutdown, run_shutdown);
-	INIT_WORK(&PMC_sync, run_sync);
-
-	/*
-	 *  set interrupt service routine
-	 */
-//	if (request_irq(IRQ_PMC_WAKEUP, &pmc_wakeup_isr,  IRQF_DISABLED, "pmc", &pm_dev) < 0)
-	if (request_irq(IRQ_PMC_WAKEUP, &pmc_wakeup_isr, IRQF_SHARED, "pmc", &pm_dev) < 0)
-		printk(KERN_ALERT "%s: [Wondermedia_pm_init] Failed to register pmc wakeup irq \n"
-               , DRIVER_NAME);
-			   
-	 irq_set_irq_wake(IRQ_PMC_WAKEUP, 1);
-	 
-#ifndef CONFIG_SKIP_DRIVER_MSG
-	/*
-	 * Plan to remove it to recude core size in the future.
-	 */
-	printk(KERN_INFO "%s: WonderMedia Power Management driver\n", DRIVER_NAME);
-#endif
-
-	/*
-	 * Setup PM core driver into kernel.
-	 */
-	suspend_set_ops(&wmt_pm_ops);
-
-#ifdef CONFIG_HIBERNATION
-	hibernation_set_ops(&wmt_hibernation_ops);//support hibernation platform mode
-#endif /* CONFIG_HIBERNATION */
-#if defined(SOFT_POWER_SUPPORT) && defined(CONFIG_PROC_FS)
-
-	/* Power button is configured as soft power*/
-	printk("%s: Power button is configured as soft power\n", DRIVER_NAME);
-	PMPB_VAL |= PMPB_SOFTPWR;
-
-#if 0
-	/* Create proc entry*/
-	proc_softpower = create_proc_entry("softpower", 0644, &proc_root);
-	proc_softpower->data = &softpower_data;
-	proc_softpower->read_proc = procfile_read;
-	proc_softpower->write_proc =  procfile_write;
-#endif 
-
-#else
-	/* Power button is configured as hard power*/
-	printk("%s: Power button is configured as hard power\n", DRIVER_NAME);
-	PMPB_VAL = 0;
-
-#endif	/* defined(SOFT_POWER_SUPPORT) && defined(CONFIG_PROC_FS)*/
-
-		/*read power button debounce value*/
-	if (wmt_getsyspara(varname, buf, &varlen) == 0){
-			sscanf(buf,"%d:%d:%d",
-						&power_on_debounce_value,
-						&resume_debounce_value,
-						&power_up_debounce_value);
-
-		if (power_on_debounce_value < min_debounce_value)
-			power_on_debounce_value = min_debounce_value;
-		if (power_on_debounce_value > max_debounce_value)
-			power_on_debounce_value = max_debounce_value;
-
-		if (resume_debounce_value < min_debounce_value)
-			resume_debounce_value = min_debounce_value;
-		if (resume_debounce_value > max_debounce_value)
-			resume_debounce_value = max_debounce_value;
-
-		if (power_up_debounce_value < min_debounce_value)
-			power_up_debounce_value = min_debounce_value;
-		if (power_up_debounce_value > max_debounce_value)
-			power_up_debounce_value = max_debounce_value;
-	}
-
-
-	/*set power button debounce value*/
-	printk("[%s] power_on = %d resume = %d power_up = %d\n",
-	__func__,power_on_debounce_value, resume_debounce_value, power_up_debounce_value);
-	wmt_pwrbtn_debounce_value(power_on_debounce_value);
-
-	wmt_ws = wakeup_source_register("wmt_pwbn");
-
-	//enable power button intr
-	pmc_enable_wakeup_isr(WKS_PWRBTN, 0);
-
-	memset(buf ,0, sizeof(buf));
-	varlen = sizeof(buf);
-	if ((wmt_getsyspara("wmt.gpo.hall_switch", buf, &varlen) == 0)) {
-		int ret = sscanf(buf, "%d:%d",
-					   &hall_switch.gpio_no,
-					   &hall_switch.wakeup_source
-				       );
-		
-		//printk(KERN_ERR"hall_switch gpiono:%d ws:%d\n",hall_switch.gpio_no,hall_switch.wakeup_source);
-		ret = gpio_request(hall_switch.gpio_no, "hall_switch"); 
-		if(ret < 0) {
-			printk(KERN_ERR"gpio request fail for hall_switch\n");
-			goto hswitch_done;
-		}
-		
-		gpio_direction_input(hall_switch.gpio_no);
-		wmt_gpio_setpull(hall_switch.gpio_no, WMT_GPIO_PULL_UP);
-	
-		pmc_enable_wakeup_isr(hall_switch.wakeup_source,4);
-		wakeup_queue=create_workqueue("wakeup0");
-		INIT_DELAYED_WORK(&wakeupwork, wakeup_func);
-		hall_switch.have_switch = 1;
-	}
-
-hswitch_done:
-
-	
-	
-	return 0;
-}
-
-late_initcall(wmt_pm_init);
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/pm_cpai.c b/ANDROID_3.4.5/arch/arm/mach-wmt/pm_cpai.c
deleted file mode 100755
index e2576aa4..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/pm_cpai.c
+++ /dev/null
@@ -1,165 +0,0 @@
-/*++
-linux/arch/arm/mach-wmt/board.c
-
-Copyright (c) 2012 WonderMedia Technologies, Inc.
-
-This program is free software: you can redistribute it and/or modify it under the
-terms of the GNU General Public License as published by the Free Software Foundation,
-either version 2 of the License, or (at your option) any later version.
-
-This program is distributed in the hope that it will be useful, but WITHOUT
-ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-PARTICULAR PURPOSE.  See the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License along with
-this program.  If not, see <http://www.gnu.org/licenses/>.
-
-WonderMedia Technologies, Inc.
-10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
---*/
-#define fail -1
-#include <mach/hardware.h>
-#include <mach/irqs.h>
-#include <linux/sysctl.h>
-
-extern unsigned int wmt_i2c0_speed_mode;
-extern unsigned int wmt_i2c1_speed_mode;
-
-#if 0
-static int PM_USB_PostSuspend(void)
-{
-	return 0;
-}
-
-
-static int PM_USB_PreResume(void)
-{
-	unsigned int tmp32;
-	unsigned char tmp8;
-
-	/* EHCI PCI configuration seting */
-	/* set bus master */
-	*(volatile unsigned char*) 0xd8007804 = 0x17;
-	tmp8 = *(volatile unsigned char*) 0xd8007804;
-	if (tmp8 != 0x17) {
-		printk("PM_USB_init : 0xd8007104 = %02x\n", tmp8);
-		return fail;
-	}
-
-	/* set interrupt line */
-	*(volatile unsigned char*) 0xd800783c = 0x2b;
-	tmp8 = *(volatile unsigned char*) 0xd800783c;
-	if (tmp8 != 0x2b) {
-		printk("PM_USB_init : 0xd800713c = %02x\n", tmp8);
-		return fail;
-	}
-
-	/* enable AHB master cut data to 16/8/4 DW align */
-	tmp32 = *(volatile unsigned char*) 0xd800784c;
-	tmp32 &= 0xfffdffff;
-	*(volatile unsigned char*) 0xd800784c = tmp32;
-	tmp32 = *(volatile unsigned char*) 0xd800784c;
-	if ((tmp32&0x00020000) != 0x00000000)
-		printk("[EHCI] Programming EHCI PCI Configuration Offset Address : 4ch fail! \n");
-
-
-	/* UHCI PCI configuration setting */
-	/* set bus master */
-	*(volatile unsigned char*) 0xd8007a04 = 0x07;
-	tmp8 = *(volatile unsigned char*) 0xd8007a04;
-	if (tmp8 != 0x07) {
-		printk("PM_USB_init : 0xd8007304 = %02x\n", tmp8);
-		return fail;
-	}
-
-	/* set interrupt line */
-	*(volatile unsigned char*) 0xd8007a3c = 0x2b;
-	tmp8 = *(volatile unsigned char*) 0xd8007a3c;
-	if (tmp8 != 0x2b) {
-		printk("PM_USB_init : 0xd800733c = %02x\n", tmp8);
-		return fail;
-	}
-
-	return 0;
-}
-#endif
-
-#if 0
-static char MACVeeRom[32] = {0xFF};
-static void PM_MAC_PreResume(void)
-{
-	int i = 0;
-	*((volatile unsigned char*)0xd8004104) = 0x4;
-
-	/* restore VEE */
-	for (i = 0; i < 8; i++)
-		*(volatile unsigned long *)(0xd800415C + i*4) = *((int *)MACVeeRom + i);
-
-	/* reload VEE */
-	*(volatile unsigned char*)0xd800417C |= 0x01;
-
-	/* reload */
-	*(volatile unsigned char*)0xd8004074 |= 0xa0;
-
-	/* check reload VEE complete */
-	while ((*(volatile unsigned char*)0xd800417C & 0x02) != 0x02);
-
-	return;
-}
-static void PM_MAC_PostSuspend(void)
-{
-	int i = 0;
-
-	/*save VEE*/
-	for (i = 0; i < 32; i++)
-		MACVeeRom[i] = *((volatile unsigned char*)0xd800415C + i);
-
-	return;
-}
-#endif
-
-
-inline unsigned int wmt_read_oscr(void);
-static u32 cyc_mark = 0;
-#define PRIVATE_TIMER_CTRL (MPCORE_PRIVATE_MEM + 0x600)
-#define PRIVATE_TIMER_INTSTAT (MPCORE_PRIVATE_MEM + 0x60C)
-#define GIC_PEN_CLR (0xFE019280)
-
-static void wmt_timer_postsuspend(void)
-{
-	cyc_mark = wmt_read_oscr();
-	if (REG32_VAL(PRIVATE_TIMER_INTSTAT)) {
-		REG32_VAL(PRIVATE_TIMER_INTSTAT) = 0x1;
-		REG32_VAL(GIC_PEN_CLR) = 0x20000000;
-	}
-}
-
-static void wmt_timer_preresume(void)
-{
-	// set saved counter value
-	OSCR_VAL = cyc_mark;
-}
-
-int PM_device_PreResume(void)
-{
-	int result;
-	/* PM_MAC_PreResume(); */
-    wmt_timer_preresume();
-
-	/*
-	result = PM_USB_PreResume();
-	if (!result)
-		goto FAIL;
-	*/
-
-	return 0;
-/* FAIL: */
-	return result;
-}
-
-
-int PM_device_PostSuspend(void)
-{
-	/* PM_MAC_PostSuspend(); */
-	wmt_timer_postsuspend();
-	return 0;
-}
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/pwm.c b/ANDROID_3.4.5/arch/arm/mach-wmt/pwm.c
deleted file mode 100755
index 8a466259..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/pwm.c
+++ /dev/null
@@ -1,272 +0,0 @@
-/*
- * arch/arm/mach-wm8880/pwm.c
- *
- *  Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/slab.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/pwm.h>
-#include <linux/delay.h>
-
-#include <asm/div64.h>
-#include "wmt_clk.h"
-
-#include <mach/hardware.h>
-
-/* TODO only support pwm0 for lcd backlight now. */
-#define WM8880_NR_PWMS 2
-
-static DEFINE_MUTEX(pwm_lock);
-static LIST_HEAD(pwm_list);
-
-struct pwm_device {
-	struct list_head	node;
-	struct platform_device	*pdev;
-
-	const char	*label;
-
-	void __iomem	*regbase;
-
-	unsigned int	use_count;
-	unsigned int	pwm_id;
-};
-
-#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
-static inline void pwm_busy_wait(void __iomem *reg, u8 bitmask)
-{
-	int loops = msecs_to_loops(10);
-	while ((readb(reg) & bitmask) && --loops)
-		cpu_relax();
-
-	if (unlikely(!loops))
-		pr_warning("Waiting for status bits 0x%x to clear timed out\n",
-			   bitmask);
-}
-
-int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
-{
-	unsigned long long c;
-	unsigned long period_cycles, prescale, pv, dc;
-
-	//printk("%s: duty_ns %d, period_ns %d\n", __func__, duty_ns, period_ns);
-	if (pwm == NULL || period_ns == 0 || duty_ns > period_ns)
-		return -EINVAL;
-
-	c = auto_pll_divisor(DEV_PWM,GET_FREQ,0,0);
-	c = c * period_ns;
-	do_div(c, 1000000000);
-	period_cycles = c;
-
-	if (period_cycles < 1)
-		period_cycles = 1;
-	prescale = (period_cycles - 1) / 4096;
-	pv = period_cycles / (prescale + 1) - 1;
-	if (pv > 4095)
-		pv = 4095;
-
-	if (prescale > 1023)
-		return -EINVAL;
-
-	c = (unsigned long long)pv * duty_ns;
-	do_div(c, period_ns);
-	dc = c;
-
-	//printk("%s: prescale %ld, period %ld, duty %ld\n", __func__, prescale, pv, dc);
-	pwm_busy_wait(pwm->regbase + 0x40 + pwm->pwm_id, (1 << 1));
-	writel(prescale, pwm->regbase + 0x4 + (pwm->pwm_id << 4));
-
-	pwm_busy_wait(pwm->regbase + 0x40 + pwm->pwm_id, (1 << 2));
-	writel(pv, pwm->regbase + 0x8 + (pwm->pwm_id << 4));
-
-	pwm_busy_wait(pwm->regbase + 0x40 + pwm->pwm_id, (1 << 3));
-	writel(dc, pwm->regbase + 0xc + (pwm->pwm_id << 4));
-
-	return 0;
-}
-EXPORT_SYMBOL(pwm_config);
-
-int pwm_enable(struct pwm_device *pwm)
-{
-	pwm_busy_wait(pwm->regbase + 0x40 + pwm->pwm_id, (1 << 0));
-	writel(5, pwm->regbase + (pwm->pwm_id << 4));
-	return 0;
-}
-EXPORT_SYMBOL(pwm_enable);
-
-void pwm_disable(struct pwm_device *pwm)
-{
-	pwm_busy_wait(pwm->regbase + 0x40 + pwm->pwm_id, (1 << 0));
-	writel(0, pwm->regbase + (pwm->pwm_id << 4));
-}
-EXPORT_SYMBOL(pwm_disable);
-
-struct pwm_device *pwm_request(int pwm_id, const char *label)
-{
-	struct pwm_device *pwm;
-	int found = 0;
-
-	mutex_lock(&pwm_lock);
-
-	list_for_each_entry(pwm, &pwm_list, node) {
-		if (pwm->pwm_id == pwm_id) {
-			found = 1;
-			break;
-		}
-	}
-
-	if (found) {
-		if (pwm->use_count == 0) {
-			pwm->use_count++;
-			pwm->label = label;
-		} else {
-			pwm = ERR_PTR(-EBUSY);
-		}
-	} else {
-		pwm = ERR_PTR(-ENOENT);
-	}
-
-	mutex_unlock(&pwm_lock);
-	return pwm;
-}
-EXPORT_SYMBOL(pwm_request);
-
-void pwm_free(struct pwm_device *pwm)
-{
-	mutex_lock(&pwm_lock);
-
-	if (pwm->use_count) {
-		pwm->use_count--;
-		pwm->label = NULL;
-	} else {
-		pr_warning("PWM device already freed\n");
-	}
-
-	mutex_unlock(&pwm_lock);
-}
-EXPORT_SYMBOL(pwm_free);
-
-static inline void __add_pwm(struct pwm_device *pwm)
-{
-	mutex_lock(&pwm_lock);
-	list_add_tail(&pwm->node, &pwm_list);
-	mutex_unlock(&pwm_lock);
-}
-
-static int __devinit pwm_probe(struct platform_device *pdev)
-{
-	struct pwm_device *pwms;
-	struct resource *r;
-	int ret = 0;
-	int i;
-
-	pwms = kzalloc(sizeof(struct pwm_device) * WM8880_NR_PWMS, GFP_KERNEL);
-	if (pwms == NULL) {
-		dev_err(&pdev->dev, "failed to allocate memory\n");
-		return -ENOMEM;
-	}
-
-	for (i = 0; i < WM8880_NR_PWMS; i++) {
-		pwms[i].use_count = 0;
-		pwms[i].pwm_id = i;
-		pwms[i].pdev = pdev;
-	}
-
-	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (r == NULL) {
-		dev_err(&pdev->dev, "no memory resource defined\n");
-		ret = -ENODEV;
-		goto err_free;
-	}
-
-	r = request_mem_region(r->start, resource_size(r), pdev->name);
-	if (r == NULL) {
-		dev_err(&pdev->dev, "failed to request memory resource\n");
-		ret = -EBUSY;
-		goto err_free;
-	}
-
-	pwms[0].regbase = ioremap(r->start, resource_size(r));
-	if (pwms[0].regbase == NULL) {
-		dev_err(&pdev->dev, "failed to ioremap() registers\n");
-		ret = -ENODEV;
-		goto err_free_mem;
-	}
-
-	for (i = 1; i < WM8880_NR_PWMS; i++)
-		pwms[i].regbase = pwms[0].regbase;
-
-	for (i = 0; i < WM8880_NR_PWMS; i++)
-		__add_pwm(&pwms[i]);
-
-	auto_pll_divisor(DEV_PWM,CLK_ENABLE,0,0);
-	platform_set_drvdata(pdev, pwms);
-	return 0;
-
-err_free_mem:
-	release_mem_region(r->start, resource_size(r));
-err_free:
-	kfree(pwms);
-	return ret;
-}
-
-static int __devexit pwm_remove(struct platform_device *pdev)
-{
-	struct pwm_device *pwms;
-	struct resource *r;
-	int i;
-
-	pwms = platform_get_drvdata(pdev);
-	if (pwms == NULL)
-		return -ENODEV;
-
-	mutex_lock(&pwm_lock);
-
-	for (i = 0; i < WM8880_NR_PWMS; i++)
-		list_del(&pwms[i].node);
-	mutex_unlock(&pwm_lock);
-
-	iounmap(pwms[0].regbase);
-
-	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	release_mem_region(r->start, resource_size(r));
-
-	kfree(pwms);
-	return 0;
-}
-
-static struct platform_driver pwm_driver = {
-	.driver		= {
-		.name	= "wm8880-pwm",
-		.owner	= THIS_MODULE,
-	},
-	.probe		= pwm_probe,
-	.remove		= __devexit_p(pwm_remove),
-};
-
-static int __init pwm_init(void)
-{
-	return platform_driver_register(&pwm_driver);
-}
-arch_initcall(pwm_init);
-
-static void __exit pwm_exit(void)
-{
-	platform_driver_unregister(&pwm_driver);
-}
-module_exit(pwm_exit);
-
-MODULE_LICENSE("GPL");
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/sleep.S b/ANDROID_3.4.5/arch/arm/mach-wmt/sleep.S
deleted file mode 100755
index 07d52325..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/sleep.S
+++ /dev/null
@@ -1,457 +0,0 @@
-/*++
-linux/arch/arm/mach-wmt/sleep.s
-
-Copyright (c) 2008  WonderMedia Technologies, Inc.
-
-This program is free software: you can redistribute it and/or modify it under the
-terms of the GNU General Public License as published by the Free Software Foundation,
-either version 2 of the License, or (at your option) any later version.
-
-This program is distributed in the hope that it will be useful, but WITHOUT
-ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-PARTICULAR PURPOSE.  See the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License along with
-this program.  If not, see <http://www.gnu.org/licenses/>.
-
-WonderMedia Technologies, Inc.
-10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
---*/
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-#include <mach/wmt_secure.h>
-
-
-
-/*
- * Registers access definitions
- */
-/* Standard definitions of mode bits and interrupt (I & F) flags in PSRs */
-#define	MODE_USR	0x10
-#define MODE_FIQ	0x11
-#define MODE_IRQ	0x12
-#define MODE_SVC	0x13
-#define MODE_ABT	0x17
-#define MODE_UND	0x1B
-#define MODE_SYS	0x1F
-
-#define I_BIT		0x80
-#define F_BIT		0x40
-
-#define DO_POWER_OFF_SUSPEND	0xFFFFFFC4
-
-	.arm
-	.arch_extension sec
-
-	.text
-
-ENTRY(wmt_assem_suspend)
-//suspend
-	mrs	r3, cpsr
-	bic r3, r3, #0x1f
-	orr r3, r3, #MODE_SVC
-	msr	cpsr_c, r3			@ ensure we are in SVC mode
-	mov	r2, sp                                  @ using svc stack pointer as the global one
-
-	mrs	r3, cpsr
-	bic r3, r3, #0x1f
-	orr r3, r3, #MODE_FIQ
-	msr	cpsr_c, r3			@ store FIQ bank registers
-	mrs	r3, spsr
-	stmfd	r2!, {r3, r8 - r14}
-
-	mrs	r3, cpsr
-	bic r3, r3, #0x1f
-	orr r3, r3, #MODE_IRQ
-	msr	cpsr_c, r3			@ store IRQ bank registers
-	mrs	r3, spsr
-	stmfd	r2!, {r3, r13, r14}
-
-	mrs	r3, cpsr
-	bic r3, r3, #0x1f
-	orr r3, r3, #MODE_UND
-	msr	cpsr_c, r3			@ store UND bank registers
-	mrs	r3, spsr
-	stmfd	r2!, {r3, r13, r14}
-
-	mrs	r3, cpsr
-	bic r3, r3, #0x1f
-	orr r3, r3, #MODE_ABT
-	msr	cpsr_c, r3			@ store ABT bank registers
-	mrs	r3, spsr
-	stmfd	r2!, {r3, r13, r14}
-
-	mrs	r3, cpsr
-	bic r3, r3, #0x1f
-	orr r3, r3, #MODE_SYS
-	msr	cpsr_c, r3                       @ store SYS bank registers
-	mrs	r3, spsr
-	stmfd	r2!, {r3 - r14}
-
-	mrs	r3, cpsr
-	bic r3, r3, #0x1f
-	orr r3, r3, #MODE_SVC
-	msr     cpsr_c, r3		@ come back to SVC mode
-	mov	sp, r2			                @ restore the updated and used stack pointer
-
-	ldr r2, =0xfe000000
-	
-	mrs	r0, cpsr
-	mrs	r1, spsr
-	stmfd   sp!, {r0, r1, r4 - r12, lr}            	@ save current mode (SVC) registers on stack
-
-	mrc	p15, 0, r4, c13, c0, 0	@ FCSE/PID
-	mrc	p15, 0, r5, c13, c0, 1	@ Context ID
-	mrc	p15, 0, r6, c13, c0, 3	@ User r/o thread ID
-	
-	stmfd	sp!, {r4 - r6}
-	mrc	p15, 0, r6, c3, c0, 0	@ Domain ID
-	mrc	p15, 0, r7, c2, c0, 0	@ TTB 0
-	mrc	p15, 0, r8, c2, c0, 1	@ TTB 1
-	mrc	p15, 0, r9, c1, c0, 0	@ Control register
-	mrc	p15, 0, r10, c1, c0, 1	@ Auxiliary control register
-	mrc	p15, 0, r11, c1, c0, 2	@ Co-processor access control
-	stmfd	sp!, {r6 - r11}
-
-	ldr r1, =0x130000
-	add r5, r2, r1
-
-	/* Store physcial address of stack to HSP2_REG */
-	ldr	r1, =0xc0000000				@ PAGE_OFFSET, define in memory.h
-	mov	r0, sp
-	sub	r0, r0, r1                              @ __virt_to_phys(x)	((x) - PAGE_OFFSET + PHYS_OFFSET)
-	str	r0, [r5, #0x34]				@ save sp to HSPR2
-
-	/* Flush all data */
-
-	dmb					@ ensure ordering with previous memory accesses
-	mrc	p15, 1, r0, c0, c0, 1		@ read clidr
-	ands	r3, r0, #0x7000000		@ extract loc from clidr
-	mov	r3, r3, lsr #23			@ left align loc bit field
-	beq	finished			@ if loc is 0, then no need to clean
-	mov	r10, #0				@ start clean at cache level 0
-loop1:
-	add	r2, r10, r10, lsr #1		@ work out 3x current cache level
-	mov	r1, r0, lsr r2			@ extract cache type bits from clidr
-	and	r1, r1, #7			@ mask of the bits for current cache only
-	cmp	r1, #2				@ see what cache we have at this level
-	blt	skip				@ skip if no cache, or just i-cache
-	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
-	isb					@ isb to sych the new cssr&csidr
-	mrc	p15, 1, r1, c0, c0, 0		@ read the new csidr
-	and	r2, r1, #7			@ extract the length of the cache lines
-	add	r2, r2, #4			@ add 4 (line length offset)
-	ldr	r4, =0x3ff
-	ands	r4, r4, r1, lsr #3		@ find maximum number on the way size
-	clz	r5, r4				@ find bit position of way size increment
-	ldr	r7, =0x7fff
-	ands	r7, r7, r1, lsr #13		@ extract max number of the index size
-loop2:
-	mov	r9, r4				@ create working copy of max way size
-loop3:
- ARM(	orr	r11, r10, r9, lsl r5	)	@ factor way and cache number into r11
- THUMB(	lsl	r6, r9, r5		)
- THUMB(	orr	r11, r10, r6		)	@ factor way and cache number into r11
- ARM(	orr	r11, r11, r7, lsl r2	)	@ factor index number into r11
- THUMB(	lsl	r6, r7, r2		)
- THUMB(	orr	r11, r11, r6		)	@ factor index number into r11
-	mcr	p15, 0, r11, c7, c14, 2		@ clean & invalidate by set/way
-	subs	r9, r9, #1			@ decrement the way
-	bge	loop3
-	subs	r7, r7, #1			@ decrement the index
-	bge	loop2
-skip:
-	add	r10, r10, #2			@ increment cache number
-	cmp	r3, r10
-	bgt	loop1
-finished:
-	mov	r10, #0				@ swith back to cache level 0
-	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
-
-
-	
-	dsb
-	isb
-
-
-	/* Save physical entry address */
-	ldr     r1, =DO_POWER_OFF_SUSPEND
-	
-	/* Turn off MMU and disable caches */
-	mrc	p15, 0, r0, c1, c0, 0	                @ read control reg
-	bic	r0, r0, #0x05		                @ clear D-cache, turn off MMU
-	bic	r0, r0, #0x1000		                @ clear I-cache
-	mcr	p15, 0, r0, c1, c0, 0                   @ turn off ...
-	nop
-	//mov     pc, r1
-	blx		r1
-	nop
-	nop
-	nop
-	nop
-	
-
-	ldmia   sp!, {r0, r1, r4 - r12, lr}
-
-	msr	cpsr, r0
-	msr	spsr, r1
-
-	mov	r1, r2
-
-	mov	r2, sp	                                @ using svc stack pointer as the global one
-
-	mrs	r3, cpsr
-	bic r3, r3, #0x1f
-	orr r3, r3, #MODE_SYS
-	msr	cpsr_c, r3
-	ldmia	r2!, {r3 - r14}
-	msr	spsr, r3
-
-	mrs	r3, cpsr
-	bic r3, r3, #0x1f
-	orr r3, r3, #MODE_ABT
-	msr	cpsr_c, r3			@ restore ABT bank registers
-	ldmia	r2!, {r3, r13, r14}
-	msr	spsr, r3
-
-	mrs	r3, cpsr
-	bic r3, r3, #0x1f
-	orr r3, r3, #MODE_UND
-	msr	cpsr_c, r3			@ restore UND bank registers
-	ldmia	r2!, {r3, r13, r14}
-	msr	spsr, r3
-
-	mrs	r3, cpsr
-	bic r3, r3, #0x1f
-	orr r3, r3, #MODE_IRQ
-	msr	cpsr_c, r3			@ restore IRQ bank registers
-	ldmia	r2!, {r3, r13, r14}
-	msr	spsr, r3
-
-	mrs	r3, cpsr
-	bic r3, r3, #0x1f
-	orr r3, r3, #MODE_FIQ
-	msr	cpsr_c, r3			@ restore FIQ bank registers
-	ldmia	r2!, {r3, r8 - r14}
-	msr	spsr, r3
-
-	mrs	r3, cpsr
-	bic r3, r3, #0x1f
-	orr r3, r3, #MODE_SVC
-	msr	cpsr_c,  r3 		@ ensure we are in SVC mode
-	mov	sp, r2
-
-
-	mov	pc, lr					@ return to caller, saved when get into suspend
-      nop     	
-      nop     	
-      nop     
-      nop      	
-
-ENDPROC(wmt_assem_suspend)
-
-
-ENTRY(wmt_assem_secure_suspend)
-//suspend
-	mrs	r3, cpsr
-	bic r3, r3, #0x1f
-	orr r3, r3, #MODE_SVC
-	msr	cpsr_c, r3			@ ensure we are in SVC mode
-	mov	r2, sp              @ using svc stack pointer as the global one
-
-	mrs	r3, cpsr
-	bic r3, r3, #0x1f
-	orr r3, r3, #MODE_FIQ
-	msr	cpsr_c, r3			@ store FIQ bank registers
-	mrs	r3, spsr
-	stmfd	r2!, {r3, r8 - r14}
-
-	mrs	r3, cpsr
-	bic r3, r3, #0x1f
-	orr r3, r3, #MODE_IRQ
-	msr	cpsr_c, r3			@ store IRQ bank registers
-	mrs	r3, spsr
-	stmfd	r2!, {r3, r13, r14}
-
-	mrs	r3, cpsr
-	bic r3, r3, #0x1f
-	orr r3, r3, #MODE_UND
-	msr	cpsr_c, r3			@ store UND bank registers
-	mrs	r3, spsr
-	stmfd	r2!, {r3, r13, r14}
-
-	mrs	r3, cpsr
-	bic r3, r3, #0x1f
-	orr r3, r3, #MODE_ABT
-	msr	cpsr_c, r3			@ store ABT bank registers
-	mrs	r3, spsr
-	stmfd	r2!, {r3, r13, r14}
-
-	mrs	r3, cpsr
-	bic r3, r3, #0x1f
-	orr r3, r3, #MODE_SYS
-	msr	cpsr_c, r3          @ store SYS bank registers
-	mrs	r3, spsr
-	stmfd	r2!, {r3 - r14}
-
-	mrs	r3, cpsr
-	bic r3, r3, #0x1f
-	orr r3, r3, #MODE_SVC
-	msr     cpsr_c, r3		@ come back to SVC mode
-	mov	sp, r2			    @ restore the updated and used stack pointer
-
-	ldr r2, =0xfe000000
-	
-	mrs	r0, cpsr
-	mrs	r1, spsr
-	stmfd   sp!, {r0, r1, r4 - r12, lr}            	@ save current mode (SVC) registers on stack
-
-	mrc	p15, 0, r4, c13, c0, 0	@ FCSE/PID
-	mrc	p15, 0, r5, c13, c0, 1	@ Context ID
-	mrc	p15, 0, r6, c13, c0, 3	@ User r/o thread ID
-	
-	stmfd	sp!, {r4 - r6}
-	mrc	p15, 0, r6, c3, c0, 0	@ Domain ID
-	mrc	p15, 0, r7, c2, c0, 0	@ TTB 0
-	mrc	p15, 0, r8, c2, c0, 1	@ TTB 1
-	mrc	p15, 0, r9, c1, c0, 0	@ Control register
-	mrc	p15, 0, r10, c1, c0, 1	@ Auxiliary control register
-	mrc	p15, 0, r11, c1, c0, 2	@ Co-processor access control
-	stmfd	sp!, {r6 - r11}
-
-	ldr r1, =0x130000
-	add r5, r2, r1
-
-	/* Store physcial address of stack to HSP1_REG */
-	ldr	r1, =0xc0000000				@ PAGE_OFFSET, define in memory.h
-	mov	r0, sp
-	sub	r0, r0, r1                              @ __virt_to_phys(x)	((x) - PAGE_OFFSET + PHYS_OFFSET)
-	str	r0, [r5, #0x34]				@ save sp to HSPR1
-
-
-	/* Flush all data */
-	dmb					@ ensure ordering with previous memory accesses
-	mrc	p15, 1, r0, c0, c0, 1		@ read clidr
-	ands	r3, r0, #0x7000000		@ extract loc from clidr
-	mov	r3, r3, lsr #23			@ left align loc bit field
-	beq	sec_finished			@ if loc is 0, then no need to clean
-	mov	r10, #0				@ start clean at cache level 0
-sec_loop1:
-	add	r2, r10, r10, lsr #1		@ work out 3x current cache level
-	mov	r1, r0, lsr r2			@ extract cache type bits from clidr
-	and	r1, r1, #7			@ mask of the bits for current cache only
-	cmp	r1, #2				@ see what cache we have at this level
-	blt	sec_skip				@ skip if no cache, or just i-cache
-	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
-	isb					@ isb to sych the new cssr&csidr
-	mrc	p15, 1, r1, c0, c0, 0		@ read the new csidr
-	and	r2, r1, #7			@ extract the length of the cache lines
-	add	r2, r2, #4			@ add 4 (line length offset)
-	ldr	r4, =0x3ff
-	ands	r4, r4, r1, lsr #3		@ find maximum number on the way size
-	clz	r5, r4				@ find bit position of way size increment
-	ldr	r7, =0x7fff
-	ands	r7, r7, r1, lsr #13		@ extract max number of the index size
-sec_loop2:
-	mov	r9, r4				@ create working copy of max way size
-sec_loop3:
- ARM(	orr	r11, r10, r9, lsl r5	)	@ factor way and cache number into r11
- THUMB(	lsl	r6, r9, r5		)
- THUMB(	orr	r11, r10, r6		)	@ factor way and cache number into r11
- ARM(	orr	r11, r11, r7, lsl r2	)	@ factor index number into r11
- THUMB(	lsl	r6, r7, r2		)
- THUMB(	orr	r11, r11, r6		)	@ factor index number into r11
-	mcr	p15, 0, r11, c7, c14, 2		@ clean & invalidate by set/way
-	subs	r9, r9, #1			@ decrement the way
-	bge	sec_loop3
-	subs	r7, r7, #1			@ decrement the index
-	bge	sec_loop2
-sec_skip:
-	add	r10, r10, #2			@ increment cache number
-	cmp	r3, r10
-	bgt	sec_loop1
-sec_finished:
-	mov	r10, #0						@ swith back to cache level 0
-	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
-
-
-	
-	dsb
-	isb
-
-
-	
-	/* Turn off MMU and disable caches */
-	mrc	p15, 0, r0, c1, c0, 0	            @ read control reg
-	bic	r0, r0, #0x05		                @ clear D-cache, turn off MMU
-	bic	r0, r0, #0x1000		                @ clear I-cache
-	mcr	p15, 0, r0, c1, c0, 0               @ turn off ...
-	nop
-	//mov     pc, r1
-	//blx		r1
-	ldr     r0, =WMT_SMC_CMD_SECURE_SUSPEND
-	dsb
-	smc	#0                                  @switch to monitor mode
-	nop
-	nop
-	nop
-	nop
-	
-
-	ldmia   sp!, {r0, r1, r4 - r12, lr}
-
-	msr	cpsr, r0
-	msr	spsr, r1
-
-	mov	r1, r2
-
-	mov	r2, sp	                                @ using svc stack pointer as the global one
-
-	mrs	r3, cpsr
-	bic r3, r3, #0x1f
-	orr r3, r3, #MODE_SYS
-	msr	cpsr_c, r3
-	ldmia	r2!, {r3 - r14}
-	msr	spsr, r3
-
-	mrs	r3, cpsr
-	bic r3, r3, #0x1f
-	orr r3, r3, #MODE_ABT
-	msr	cpsr_c, r3			@ restore ABT bank registers
-	ldmia	r2!, {r3, r13, r14}
-	msr	spsr, r3
-
-	mrs	r3, cpsr
-	bic r3, r3, #0x1f
-	orr r3, r3, #MODE_UND
-	msr	cpsr_c, r3			@ restore UND bank registers
-	ldmia	r2!, {r3, r13, r14}
-	msr	spsr, r3
-
-	mrs	r3, cpsr
-	bic r3, r3, #0x1f
-	orr r3, r3, #MODE_IRQ
-	msr	cpsr_c, r3			@ restore IRQ bank registers
-	ldmia	r2!, {r3, r13, r14}
-	msr	spsr, r3
-
-	mrs	r3, cpsr
-	bic r3, r3, #0x1f
-	orr r3, r3, #MODE_FIQ
-	msr	cpsr_c, r3			@ restore FIQ bank registers
-	ldmia	r2!, {r3, r8 - r14}
-	msr	spsr, r3
-
-	mrs	r3, cpsr
-	bic r3, r3, #0x1f
-	orr r3, r3, #MODE_SVC
-	msr	cpsr_c,  r3 		@ ensure we are in SVC mode
-	mov	sp, r2
-
-
-	mov	pc, lr					@ return to caller, saved when get into suspend
-      nop     	
-      nop     	
-      nop     
-      nop      	
-
-ENDPROC(wmt_assem_secure_suspend)
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/wmt_clk.h b/ANDROID_3.4.5/arch/arm/mach-wmt/wmt_clk.h
deleted file mode 100755
index 6160f0a9..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/wmt_clk.h
+++ /dev/null
@@ -1,166 +0,0 @@
-/*++
-linux/arch/arm/mach-wmt/wmt_clk.h
-
-Copyright (c) 2008  WonderMedia Technologies, Inc.
-
-This program is free software: you can redistribute it and/or modify it under the
-terms of the GNU General Public License as published by the Free Software Foundation,
-either version 2 of the License, or (at your option) any later version.
-
-This program is distributed in the hope that it will be useful, but WITHOUT
-ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-PARTICULAR PURPOSE.  See the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License along with
-this program.  If not, see <http://www.gnu.org/licenses/>.
-
-WonderMedia Technologies, Inc.
-10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
---*/
-#ifndef _WMT_CLK_H_
-#define _WMT_CLK_H_
-
-/*
- *   WMT_CLK register struct
- *
- */
-
-enum dev_id {
- DEV_SDMMC0 = 0, /* PMC lower register offset PMC OFFSET + 0x250*/
- DEV_SDMMC1 = 1,
- DEV_SDMMC2 = 2,
- /*DEV_SDMMC3 = 3,
- DEV_ETHMAC = 4,*/
- DEV_C24MOUT = 6,/*DEV_ETHPHY = 6,*/
- DEV_RTC = 7,
- DEV_I2C0 = 8,
- DEV_I2C1 = 9,
- DEV_I2C2 = 10,
- DEV_GPIO = 11,
- DEV_I2C3 = 12,
- /*DEV_KEYPAD = 14,*/
- DEV_CNMVDU = 15,/*DEV_EBM = 15,*/
- DEV_PAXI = 16,
- DEV_PWM = 17,
- DEV_ADC = 18,
- DEV_I2C4 = 19,
- DEV_SCC = 21,
- DEV_SYS = 22,
- DEV_AMP = 24,
- DEV_MALI = 26,
- DEV_PCM0 = 27,
- DEV_PCM1 = 28,
- DEV_PERM = 30,
- DEV_MBOX = 31,
- 
-
- DEV_DDRMC = 32, /* PMC upper register offset 0xd8130254 */
- DEV_ARF   = 32+3,
- DEV_ARFP  = 32+4,
- DEV_DMA   = 32+5,
- DEV_PDMA  = 32+6,
- /*DEV_VDMA  = 32+7,*/
- DEV_UHDC  = 32+9,
- DEV_AHBB  = 32+13,
- DEV_NAND  = 32+16,
- /*DEV_NOR   = 32+17,*/
- DEV_SPI0  = 32+19,
- DEV_SPI1  = 32+20,
- DEV_SF    = 32+23,
- DEV_UART0 = 32+24,
- DEV_UART1 = 32+25,
- DEV_UART2 = 32+26,
- DEV_UART3 = 32+27,
- DEV_CSI0 = 32+28,/*DEV_UART4 = 32+28,*/
- DEV_CSI1 = 32+29,/*DEV_UART5 = 32+29,*/
-
- DEV_WMTNA   = 64,/*DEV_NA0   = 64,*/ /* PMC upper register offset 0xd8130258 */
- /*DEV_NA0REF= 64+1,*/
- DEV_CNMNA = 64+2,
- DEV_JDEC  = 64+3,
- DEV_MSVD  = 64+4,
- DEV_VP8DEC= 64+5,
- DEV_SAE   = 64+6,
- DEV_HDCE  = 64+7,
- DEV_H264  = 64+8,
- DEV_JENC  = 64+9,
- DEV_LVDS  = 64+14,
- DEV_CIR   = 64+15,
- DEV_NA12  = 64+16,
- DEV_VPU   = 64+17,
- DEV_VPP   = 64+18,
- DEV_VID   = 64+19,
- DEV_WMTVDU  = 64+20,/*DEV_VDU   = 64+20,*/
- DEV_SCL444U = 64+21,
- DEV_HDMII2C = 64+22,
- DEV_HDMI  = 64+23,
- DEV_GOVW  = 64+24,
- DEV_GOVRHD= 64+25,
- DEV_GE    = 64+26,
- DEV_DISP  = 64+27,
- DEV_DVO   = 64+29,
- DEV_HDMILVDS = 64+30,
- DEV_SDTV  = 64+31,
- 
- DEV_I2S   = 96+2, /* PMC upper register offset 0xd8130258 */
- /*DEV_ROT,			
- DEV_XD,*/
-
-
- DEV_ARM, /* number >= 128 has no clk_en to enable clk */
- DEV_AHB,
- DEV_APB,
- DEV_L2C,
- DEV_L2CAXI,
- DEV_L2CPAXI,
- DEV_AT,
- DEV_PERI,
- DEV_TRACE,
- DEV_DBG,
-};
-
-enum clk_cmd {
-CLK_DISABLE = 0,
-GET_FREQ,
-CLK_ENABLE,
-SET_DIV,
-SET_PLL,
-SET_PLLDIV,
-GET_CPUTIMER
-};
-
-enum power_cmd {
-DEV_PWRON = 0,
-DEV_PWROFF,
-DEV_PWRSTS,
-};
-
-struct plla_param {
-unsigned int plla_clk;
-unsigned int arm_div;
-unsigned int l2c_div;
-unsigned int l2c_tag_div;
-unsigned int l2c_data_div;
-unsigned int axi_div;
-unsigned int tb_index;
-};
-
-struct pll_map {
-unsigned int freq;
-unsigned int pll;
-};
-
-enum wmt_mmfreq_type {
-	WMT_MMFREQ_HDMI_PLUG = 0x01,
-	WMT_MMFREQ_MIRACAST = 0x02,
-	WMT_MMFREQ_MULTI_VD = 0x04
-};
-
-extern int auto_pll_divisor(enum dev_id dev, enum clk_cmd cmd, int unit, int freq);
-extern int manu_pll_divisor(enum dev_id dev, int DIVF, int DIVR, int DIVQ, int dev_div);
-extern int set_plla_divisor(struct plla_param *plla_env);
-extern int wmt_power_dev(enum dev_id dev, enum power_cmd cmd);
-extern void wmt_resume_mmfreq(void);
-extern void wmt_suspend_mmfreq(void);
-extern void wmt_set_mmfreq(int num);
-extern void wmt_enable_mmfreq(enum wmt_mmfreq_type type, int enable);
-#endif /* __WMT_CLK_H__*/
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/wmt_clock.c b/ANDROID_3.4.5/arch/arm/mach-wmt/wmt_clock.c
deleted file mode 100755
index 1c8fff9e..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/wmt_clock.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/*++
-	linux/arch/arm/mach-wmt/wmt_clock.c
-
-	Copyright (c) 2013  WonderMedia Technologies, Inc.
-
-	This program is free software: you can redistribute it and/or modify it under the
-	terms of the GNU General Public License as published by the Free Software Foundation,
-	either version 2 of the License, or (at your option) any later version.
-
-	This program is distributed in the hope that it will be useful, but WITHOUT
-	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-	PARTICULAR PURPOSE.  See the GNU General Public License for more details.
-	You should have received a copy of the GNU General Public License along with
-	this program.  If not, see <http://www.gnu.org/licenses/>.
-
-	WonderMedia Technologies, Inc.
-	10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
---*/
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/slab.h>
-#include <linux/module.h>
-#include <linux/cpufreq.h>
-#include <linux/delay.h>
-#include <linux/clkdev.h>
-#include <linux/clk-private.h>
-#include <linux/clk-provider.h>
-#include <mach/hardware.h>
-
-//#define DEBUG
-#ifdef DEBUG
-#define fq_dbg(fmt, args...) \
-		printk(KERN_ERR "[%s]_%d_%d: " fmt, __func__ , __LINE__, smp_processor_id(), ## args)
-#define fq_trace() printk(KERN_ERR "trace in %s %d\n", __func__, __LINE__)
-#else
-#define fq_dbg(fmt, args...)
-#define fq_trace()
-#endif
-
-#define DEV_NAME  "smp_twd"
-
-static struct clk_lookup twd_lookup = {
-	.dev_id = DEV_NAME,
-};
-
-static int wmt_twd_clk_enable(struct clk_hw *hw)
-{
-	return 0;
-}
-
-static void wmt_twd_clk_disable(struct clk_hw *hw)
-{
-	return ;
-}
-
-static int wmt_twd_clk_is_enabled(struct clk_hw *hw)
-{
-	return true;
-}
-
-static unsigned long 
-wmt_twd_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
-{
-	int freq = 0;
-
-	/* return the ARM CPU clock rate */
-	freq = auto_pll_divisor(DEV_ARM, GET_CPUTIMER, 0, 0) / 2;
-
-	if (freq < 0)
-		freq = 0;
-
-	return freq;
-}
-
-static struct clk_ops wmt_twd_clk_ops = {
-	.enable		 = wmt_twd_clk_enable,
-	.disable	 = wmt_twd_clk_disable,
-	.is_enabled	 = wmt_twd_clk_is_enabled,
-	.recalc_rate = wmt_twd_clk_recalc_rate,
-};
-
-static int wmt3498_register_twd_clk(struct clk_ops *ops, struct clk_lookup *cl)
-{
-	struct clk_hw *hw = NULL;
-
-	clkdev_add(cl);
-
-	/* register twd clk here */
-	hw = kzalloc(sizeof(*hw), GFP_KERNEL);
-	if (!hw) {
-		printk(KERN_ERR "Register smp_twd clock failed!\n");
-		return -ENOMEM;
-	}
-
-	cl->clk = clk_register(NULL, DEV_NAME, ops, hw, NULL, 0, CLK_IS_ROOT);
-
-	if (!cl->clk) {
-		printk(KERN_ERR "Register smp_twd clock failed!\n");
-		kfree(hw);
-		return -ENOMEM;
-	}
-
-	return 0;    
-}
-
-static void wmt3498_register_clocks(void)
-{
-	wmt3498_register_twd_clk(&wmt_twd_clk_ops, &twd_lookup);
-
-	return ;
-}
-
-static int wmt3498_setup_twd_clk(void)
-{
-	return 0;
-}
-
-static void wmt3498_setup_clocks(void)
-{
-	wmt3498_setup_twd_clk();
-
-	return ;
-}
-
-/* this func should be called in machine early_init or io_map */
-void wmt3498_init_clocks(void)
-{
-	wmt3498_register_clocks();
-	wmt3498_setup_clocks();
-
-	return ;
-}
-
-/* updates twd frequency when the cpu frequency changes. */
-static int wmt_twd_cpufreq_transition(struct notifier_block *nb,
-										unsigned long state, void *data)
-{
-	struct clk *wmt_twd_clk = twd_lookup.clk;
-	struct cpufreq_freqs *freqs = data;	
-
-	if (!wmt_twd_clk)
-		goto out;
-
-	if (state == CPUFREQ_POSTCHANGE || state == CPUFREQ_RESUMECHANGE) {
-		// only boot-cpu do clk rate update
-		if (freqs->cpu == 0) {
-			wmt_twd_clk->rate = auto_pll_divisor(DEV_ARM, GET_CPUTIMER, 0, 0) / 2;
-			wmt_twd_clk->new_rate = wmt_twd_clk->rate;
-		}
-	}
-
-out:
-	return NOTIFY_OK;
-}
-
-static struct notifier_block wmt_twd_cpufreq_nb = {
-	.notifier_call = wmt_twd_cpufreq_transition,
-	.priority = 10, /* higher than twd */
-};
-
-static int wmt_twd_cpufreq_init(void)
-{
-	return cpufreq_register_notifier(&wmt_twd_cpufreq_nb, CPUFREQ_TRANSITION_NOTIFIER);
-}
-core_initcall(wmt_twd_cpufreq_init);
-
-MODULE_AUTHOR("WonderMedia Technologies, Inc");
-MODULE_DESCRIPTION("WMT Common Clock Driver");
-MODULE_LICENSE("Dual BSD/GPL");
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/wmt_cpuidle.c b/ANDROID_3.4.5/arch/arm/mach-wmt/wmt_cpuidle.c
deleted file mode 100755
index e4aaf194..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/wmt_cpuidle.c
+++ /dev/null
@@ -1,133 +0,0 @@
-/*++
-linux/arch/arm/mach-wmt/wmt_cpuidle.c
-
-Copyright (c) 2008  WonderMedia Technologies, Inc.
-
-This program is free software: you can redistribute it and/or modify it under the
-terms of the GNU General Public License as published by the Free Software Foundation,
-either version 2 of the License, or (at your option) any later version.
-
-This program is distributed in the hope that it will be useful, but WITHOUT
-ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-PARTICULAR PURPOSE.  See the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License along with
-this program.  If not, see <http://www.gnu.org/licenses/>.
-
-WonderMedia Technologies, Inc.
-10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
---*/
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/cpuidle.h>
-#include <linux/module.h>
-#include <linux/io.h>
-#include <linux/export.h>
-#include <asm/proc-fns.h>
-#include <asm/cpuidle.h>
-
-//#define DEBUG
-#ifdef  DEBUG
-static int dbg_mask = 0;
-module_param(dbg_mask, int, S_IRUGO | S_IWUSR);
-#define id_dbg(fmt, args...) \
-        do {\
-            if (dbg_mask) \
-                printk(KERN_ERR "[%s]_%d: " fmt, __func__ , __LINE__, ## args);\
-        } while(0)
-#define id_trace() \
-        do {\
-            if (dbg_mask) \
-                printk(KERN_ERR "trace in %s %d\n", __func__, __LINE__);\
-        } while(0)
-#else
-#define id_dbg(fmt, args...)
-#define id_trace()
-#endif
-
-#define WMT_CPU_IDLE_MAX_STATES	    2
-extern int wmt_setsyspara(char *varname, unsigned char *varval);
-extern int wmt_getsyspara(char *varname, unsigned char *varval, int *varlenex);
-
-/* Actual code that puts the SoC in different idle states */
-static int wmt_enter_idle(struct cpuidle_device *dev, 
-                            struct cpuidle_driver *drv, int index)
-{
-	cpu_do_idle();
-
-	return index;
-}
-
-static struct cpuidle_driver wmt_cpuidle_driver = {
-	.name =         "wmt_cpuidle",
-	.owner =        THIS_MODULE,
-	.en_core_tk_irqen	= 1,
-	/* ARM Wait for interrupt state */
-	.states[0]		= ARM_CPUIDLE_WFI_STATE,
-	/* Wait for interrupt and DDR self refresh state */
-    .states[1]		= {
-		.enter			= wmt_enter_idle,
-		.exit_latency		= 10,
-		.target_residency	= 100000,
-		.flags			= CPUIDLE_FLAG_TIME_VALID,
-		.name			= "ZAC_OFF",
-		.desc			= "WFI and disable ZAC clock",
-	},
-	.state_count = WMT_CPU_IDLE_MAX_STATES,
-};
-
-static int __init wmt_cpuidle_check_env(void)
-{
-    int ret = 0;
-    int varlen = 128;
-    unsigned int drv_en = 0;
-    unsigned char buf[128] = {0};
-
-    /* uboot env name is: wmt.cpuidle.param/wmt.dvfs.param */
-    ret = wmt_getsyspara("wmt.cpuidle.param", buf, &varlen);                                                                    
-    if (ret) {
-        printk(KERN_INFO "Can not find uboot env wmt.cpuidle.param\n");
-        ret = -ENODATA;
-        goto out;
-    }
-    id_dbg("wmt.cpuidle.param:%s\n", buf);
-
-    sscanf(buf, "%d", &drv_en);
-    if (!drv_en) {
-        printk(KERN_INFO "wmt cpuidle driver disaled\n");
-        ret = -ENODEV;
-        goto out;
-    }
-
-out:
-    return ret;
-}
-
-static DEFINE_PER_CPU(struct cpuidle_device, wmt_cpuidle_device);
-static int __init wmt_cpuidle_driver_init(void)
-{
-    struct cpuidle_device *device = NULL;
-
-    if (wmt_cpuidle_check_env()) {
-        printk(KERN_WARNING "wmt_cpuidle check env failed!\n");
-        return -EINVAL;
-    }
-
-    device = &per_cpu(wmt_cpuidle_device, smp_processor_id());
-	device->state_count = WMT_CPU_IDLE_MAX_STATES;
-
-	cpuidle_register_driver(&wmt_cpuidle_driver);
-	if (cpuidle_register_device(device)) {
-		printk(KERN_ERR "wmt_cpuidle_driver_init: Failed registering\n");
-		return -EIO;
-	}
-
-    printk(KERN_INFO "WMT cpuidle driver register\n");
-    return 0;
-}
-module_init(wmt_cpuidle_driver_init);
-
-MODULE_AUTHOR("WonderMedia Technologies, Inc");
-MODULE_DESCRIPTION("WMT CPU idle driver");
-MODULE_LICENSE("Dual BSD/GPL");
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/wmt_misc.c b/ANDROID_3.4.5/arch/arm/mach-wmt/wmt_misc.c
deleted file mode 100755
index 1e93c905..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/wmt_misc.c
+++ /dev/null
@@ -1,300 +0,0 @@
-#include <linux/module.h>

-#include <linux/kernel.h>

-#include <linux/delay.h> // for msleep

-#include <mach/hardware.h>//for REG32_VAL

-#include <linux/gpio.h>

-#include <mach/wmt_iomux.h>

-#include <asm/atomic.h> // for atomic_inc atomis_dec added by rubbitxiao

-#include <linux/etherdevice.h>

-

-//added begin by rubbit

-extern int wmt_getsyspara(char *varname, unsigned char *varval, int *varlen);

-extern int wmt_setsyspara(char *varname, char *varval);                      

-

-//#define WMT_PIN_GP2_SUSGPIO1  19

-

-#define WIFI_POWER_PIN WMT_PIN_GP62_SUSGPIO1

-

-//if you use API in the file ,you should #include <mach/wmt_misc.h>

-

-void detect_wifi_module(void * pbool)

-{

-	int retval = -1;

-	int varlen = 127;

-	char buf[200] = {0};

-	char *wifi;

-	char *bt;

-	char *gps;

-	char *tmp;

-

-	printk("detect_wifi_module\n");

-  retval = wmt_getsyspara("wmt.wifi.bluetooth.gps", buf, &varlen);

-  if(!retval)

-	{

-		//sscanf(buf, "%s:%s:%s",wifi,bt,gps);

-		if(strlen(buf) == 0) {

-			printk("uboot enviroment variant(wmt.wifi.bluetooth.gp) is not connect\n");

-			*(bool*)pbool = false;

-			return ;

-		}

-		tmp = buf;

-		printk("buf:%s\n",buf);

-		wifi = strsep(&tmp,":");

-		bt = strsep(&tmp,":");

-		gps = strsep(&tmp,":");

-		

-		printk("wifi:%s, bt:%s, gps:%s\n",wifi,bt,gps);

-

-		if(!strncmp(wifi,"mtk_6620",8)) {

-			*(bool*)pbool = true;

-			printk("detect mtk_6620 modules:%d\n",*(bool*)pbool);

-		} else {

-			*(bool*)pbool = false;

-			printk("wifi_module:%s---%d\n",wifi,*(bool*)pbool);

-		}

-		return ;

-	}

-	printk("have not set uboot enviroment variant:wmt.wifi.bluetooth.gps\n");

-	return;

-}

-

-int bt_is_mtk6622 = -1;

-

-int is_mtk6622(void)

-{

-	if(bt_is_mtk6622==-1){

-		int retval = -1;

-		int varlen = 127;

-		char buf[200] = {0};

-		retval = wmt_getsyspara("wmt.bt.param", buf, &varlen);

-		bt_is_mtk6622 = 0;

-		if(!retval)

-		{

-			if(!strcmp(buf,"mtk_6622"))

-				bt_is_mtk6622 = 1;

-		}

-	}

-	return bt_is_mtk6622;

-}

-

-

-int bt_is_rda5991 = -1;

-

-int is_rda5991(void)

-{

-	if(bt_is_rda5991==-1){

-		int retval = -1;

-		int varlen = 127;

-		char buf[200] = {0};

-		retval = wmt_getsyspara("wmt.bt.param", buf, &varlen);

-		bt_is_rda5991 = 0;

-		if(!retval)

-		{

-			if(!strcmp(buf,"rda_5991"))

-				bt_is_rda5991 = 1;

-		}

-	}

-	return bt_is_rda5991;

-}

-                     

-                                                                             

-                                                                            

-struct wifi_gpio {                                                           

-	int name;                                                                  

-	int active;

-	int delay;

-	int skip;                                                                                                                  

-};                                                                           

-

-enum LEVEL {

-	LOW = 0,

-	HIGH,

-};

-

-                                                                        

-static struct wifi_gpio l_wifi_gpio = {                                      

-	.name = WIFI_POWER_PIN,                                                                 

-	.active = 0,

-	.delay = 0,

-	.skip = 0x0,                                                               

-};                                                                           

-                                                                             

-

-int wifi_power_pin(int gpioNum, unsigned int active, int open)

-{

-		int ret = 0;

-

-

-		if(open){

-				ret = gpio_request(gpioNum, "wifi power pin");

-				if(ret < 0) {

-						printk("reques gpio:%x failed!!! for wifi\n",gpioNum);

-						return -1;

-				}else{

-						printk("request gpio:%d for wifi success!!!\n", gpioNum);

-				}

-				

-				if(active)

-					gpio_direction_output(gpioNum, HIGH);

-				else

-					gpio_direction_output(gpioNum, LOW);

-					

-				printk("power on wifi\n");

-		} else {

-				if(active)

-					gpio_direction_output(gpioNum, LOW);

-				else

-					gpio_direction_output(gpioNum, HIGH);

-						

-				printk("power down wifi\n");

-				gpio_free(gpioNum);

-				printk("release gpio\n");

-		}

-}

-                                                                        

-

-atomic_t gVwifiPower = ATOMIC_INIT(0);

-

-/*

-*

-*		wmt.gpo.wifi format is the following:

-*   gpionum : active level : delay

-*   

-*   if mdelay is not set, then use l_wifi_gpio.delay as a open delay

-*   if mdelay is set, then use medlay as a open delay, althrough l_wifi_gpio.delay 

-*   is specified by uboot var, if l_wifi_gpio.delay is not specified by uboot var,

-*   which have a default value of 1000ms

-*/

-                                                                             

-void wifi_power_ctrl_comm(int open,int mdelay)                                               

-{  

-	int ret=0;                                                                          

-	int varlen = 127;                                                          

-    int retval;                                                              

-    char buf[200]={0};                                                       

-	printk("wifi_power_ctrl %d, delay:%d\n",open,l_wifi_gpio.delay);                                       

-

-

-//	if(!open){

-//		//wait 200 ms for drv to stop                                                  

-//		msleep(200);                                                          

-//	}                           

-	

-  if(open)

-  {

-  	if( atomic_inc_return(&gVwifiPower) > 1 )

-  	{

-  			printk("gVwifiPower:%d\n",atomic_read(&gVwifiPower));

-  			return;

-  	}

-  	

-  }else

-  {

-  	if(atomic_read(&gVwifiPower)<=0){

-		printk("power off before power on\n");

-		return;

-  	}

-  	if(atomic_dec_return(&gVwifiPower) > 0 )

-  	{

-  		printk("gVwifiPower:%d\n",atomic_read(&gVwifiPower));  		

-  		return;

-  	}

-  }                                                                            

-/*

-*  setenv wmt.gpo.wifi 9c:1:0

-*/                                                       

-  retval = wmt_getsyspara("wmt.gpo.wifi", buf, &varlen);                   

-  if(!retval)                                                              

-	{                                                                          

-		sscanf(buf, "%x:%x:%d", &(l_wifi_gpio.name), &(l_wifi_gpio.active), &(l_wifi_gpio.delay));    			                                                			                                                                                                                                               

-		printk("wifi power up:%s\n", buf);   

-		printk("name:0x%x,active:0x%x,open delay:%d\n", l_wifi_gpio.name,l_wifi_gpio.active,l_wifi_gpio.delay);         

-//		l_wifi_gpio.skip = 0x01;                         

-	}else{

-		printk("use default wifi gpio: susgpio1\n");

-		printk("name:0x%x,active:0x%x,open delay:%d\n", l_wifi_gpio.name,l_wifi_gpio.active,l_wifi_gpio.delay); 

-//		l_wifi_gpio.skip = 0x01;                                  

-	}                                                                          

-

-next:                   

-  //excute_gpio_op(open);

-  wifi_power_pin(l_wifi_gpio.name, l_wifi_gpio.active, open);                                                    

-	if(open){

-		//wait 1 sec to hw init                                                  

-		if(mdelay)

-				msleep(mdelay);                                                            

-		else	                                                                  

-				msleep(l_wifi_gpio.delay);                                                            

-	}                                                                          

-		                                                                         

-} 

-void wifi_power_ctrl(int open) 

-{

-	wifi_power_ctrl_comm(open,1000);//unit is msec

-	//wifi_power_ctrl_comm(open,0x0);//unit is msec

-}

-

-/*

-* wifi mac uboot variant:

-* wmt.wifi.mac xx:xx:xx:xx:xx:xx

-*/

-static int is_dir_exit(const char* filename)

-{

-	struct file *filep = NULL;

-	filep = filp_open(filename, O_RDONLY, 0);

-	if(IS_ERR(filep)){

-		printk("file %s do not exit\n",filename);

-		return 0x00;

-	}

-	filp_close(filep, 0);

-	return 1;

-}

-static  int  get_wifi_mac(const char * mac_name,unsigned char *buf_mac)

-{

-	unsigned char buf[200];

-	int varlen =127;

-	int retval;

-	memset(buf,0,sizeof(buf));

-  	retval = wmt_getsyspara(mac_name, buf, &varlen);                   

-  	if(!retval)                                                              

-	{                                                                          

-		sscanf(buf, "%x:%x:%x:%x:%x:%x", &(buf_mac[0]),&(buf_mac[1]),&(buf_mac[2]),

-			&(buf_mac[3]),&(buf_mac[4]),&(buf_mac[5]));

-		printk("wifi mac:%s\n", buf);   

-		return 0x0;

-	}else{

-		printk("uboot variant:%s do not exit\n",mac_name);

-		random_ether_addr(buf_mac);

-		buf_mac[0] = 0x00;//prevent multi broadcast address

-		sprintf(buf,"%x:%x:%x:%x:%x:%x",buf_mac[0],buf_mac[1],buf_mac[2],

-			buf_mac[3],buf_mac[4],buf_mac[5]);

-		wmt_setsyspara(mac_name, buf);

-		return 0x01;

-	}

-}

-int generate_wifi_mac(unsigned char *buf_mac)

-{

-	if(is_dir_exit("/system")){//means we do not generate mac address when firmware installing

-		return get_wifi_mac("wmt.wifi.mac",buf_mac);

-	}

-	return -1;

-}

-

-int irq_int_status(void)

-{

-	unsigned long flags;

-	flags = arch_local_save_flags();

-	if(arch_irqs_disabled_flags(flags)){	

-		printk("irq interruption disabled\n");

-	}else{

-		printk("irq interruption enabled\n");

-	}

-	

-}

-

-EXPORT_SYMBOL(generate_wifi_mac);

-EXPORT_SYMBOL(is_mtk6622);

-EXPORT_SYMBOL(is_rda5991);

-EXPORT_SYMBOL(wifi_power_ctrl);

-EXPORT_SYMBOL(wifi_power_ctrl_comm);

-EXPORT_SYMBOL(irq_int_status);

diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/wmt_reset.c b/ANDROID_3.4.5/arch/arm/mach-wmt/wmt_reset.c
deleted file mode 100755
index 57b5c2b3..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/wmt_reset.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/*++
-linux/arch/arm/mach-wmt/wmt_reset.c
-
-Copyright (c) 2008  WonderMedia Technologies, Inc.
-
-This program is free software: you can redistribute it and/or modify it under the
-terms of the GNU General Public License as published by the Free Software Foundation,
-either version 2 of the License, or (at your option) any later version.
-
-This program is distributed in the hope that it will be useful, but WITHOUT
-ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-PARTICULAR PURPOSE.  See the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License along with
-this program.  If not, see <http://www.gnu.org/licenses/>.
-
-WonderMedia Technologies, Inc.
-10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
---*/
-#include <linux/module.h>
-#include <mach/hardware.h>
-#include <asm/system.h>
-#include <asm/cacheflush.h>
-
-extern void setup_mm_for_reboot(void);
-extern void call_with_stack(void (*fn)(void *), void *arg, void *sp);
-
-/*
- * A temporary stack to use for CPU reset. This is static so that we
- * don't clobber it with the identity mapping. When running with this
- * stack, any references to the current task *will not work* so you
- * should really do as little as possible before jumping to your reset
- * code.
- */
-static u64 soft_restart_stack[16];
-
-void check_busy(void) {
-	unsigned int tmp, tmp1 = 0x1000000;
-	while (tmp1) {
-		tmp = PMCS2_VAL;
-		if (!(tmp & 0x7F0038))
-			break;
-
-		tmp1--;
-		if (!tmp1)
-			printk("wait PLL divisor ready fail -- check busy halted\n");
-	}
-}
-
-static void wmt__soft_restart(void *addr)
-{
-	unsigned int tmp;
-	//phys_reset_t phys_reset;
-
-	/* Take out a flat memory mapping. */
-	setup_mm_for_reboot();
-
-	/* Clean and invalidate caches */
-	flush_cache_all();
-
-	/* Turn off caching */
-	cpu_proc_fin();
-
-	/* Push out any further dirty data, and ensure cache is empty */
-	flush_cache_all();
-
-	/* Switch to the identity mapping. */
-	/*phys_reset = (phys_reset_t)(unsigned long)virt_to_phys(cpu_reset);
-	phys_reset((unsigned long)addr);*/
-
-	check_busy();
-	PMPMC_VAL = 0x00170003;
-
-	check_busy();
-	tmp = (STRAP_STATUS_VAL>>12)&3;
-
-	check_busy();
-	PMARM_VAL = 2;
-
-	check_busy();
-	tmp = (STRAP_STATUS_VAL>>12)&3;
-	if (tmp == 2)
-		PMPMA_VAL = 0x00520101;//996
-	else if (tmp == 1)
-		PMPMA_VAL = 0x00420101;//804
-	else //if (tmp == 0)
-		PMPMA_VAL = 0x00420102;//402
-	check_busy();
-
-	/* Use on-chip reset capability */
-	PMSR_VAL = PMSR_SWR;
-
-	/* Should never get here. */
-	BUG();
-}
-
-void wmt_soft_restart(unsigned long addr)
-{
-	u64 *stack = soft_restart_stack + ARRAY_SIZE(soft_restart_stack);
-
-	/* Disable interrupts first */
-	local_irq_disable();
-	local_fiq_disable();
-
-	/* Disable the L2 if we're the last man standing. */
-	if (num_online_cpus() == 1)
-		outer_disable();
-
-	/* Change to the new stack and continue with the reset. */
-	call_with_stack(wmt__soft_restart, (void *)addr, (void *)stack);
-
-	/* Should never get here. */
-	BUG();
-}
-
-void wmt_restart(char mode, const char *cmd)
-{
-	wmt_soft_restart(mode);
-	
-	/* Should never get here. */
-	BUG();
-}
-EXPORT_SYMBOL(wmt_restart);
\ No newline at end of file
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/wmt_secure_wait_wake.c b/ANDROID_3.4.5/arch/arm/mach-wmt/wmt_secure_wait_wake.c
deleted file mode 100755
index 7f52cb43..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/wmt_secure_wait_wake.c
+++ /dev/null
@@ -1,92 +0,0 @@
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/wait.h>
-#include <linux/workqueue.h>
-#include <linux/sched.h>
-
-#include <mach/wmt_secure.h>
-#include <mach/wmt_env.h>
-
-#define WMT_SMC_CMD_WW_BASE    60
-#define WMT_SMC_CMD_WAIT_STUB  (WMT_SMC_CMD_WW_BASE + 1)
-#define WMT_SMC_CMD_WAKE_STUB  (WMT_SMC_CMD_WW_BASE + 2)
-#define WMT_SMC_CMD_WAKE_BEGIN (WMT_SMC_CMD_WW_BASE + 3)
-#define WMT_SMC_CMD_WAKE_DONE  (WMT_SMC_CMD_WW_BASE + 4)
-#define WMT_SMC_CMD_WW_TEST    (WMT_SMC_CMD_WW_BASE + 5)
-
-DECLARE_WAIT_QUEUE_HEAD(wmt_smc_wait);
-static int smc_done = 0;
-
-static void wmt_smc_wait_stub(void)
-{
-	wait_event_interruptible(wmt_smc_wait, smc_done);
-	smc_done = 0;
-	wmt_smc(WMT_SMC_CMD_WAKE_DONE, 0);
-}
-
-static void wmt_smc_wake_stub(void)
-{
-	/* irq already been disabled in secure world */
-	smc_done = 1;
-	wake_up_interruptible(&wmt_smc_wait);
-	wmt_smc(WMT_SMC_CMD_WAKE_BEGIN, 0);
-}
-
-static void wmt_setup_wait_stub(u32 wait_stub)
-{
-	wmt_smc(WMT_SMC_CMD_WAIT_STUB, wait_stub);
-}
-
-static void wmt_setup_wake_stub(u32 wake_stub)
-{
-	wmt_smc(WMT_SMC_CMD_WAKE_STUB, wake_stub);
-}
-
-static int __init wmt_check_secure_env(void)
-{
-    int ret = 0;
-    int varlen = 128;
-    unsigned int sec_en = 0;
-    unsigned char buf[128] = {0};
-
-    /* uboot env name is: wmt.secure.param */
-    ret = wmt_getsyspara("wmt.secure.param", buf, &varlen);                                                                    
-    if (ret) {
-        ret = -ENODATA;
-        goto out;
-    }
-
-    sscanf(buf, "%d", &sec_en);
-    if (sec_en != 1) {
-        printk(KERN_INFO "wmt security extension disaled\n");
-        ret = -ENODEV;
-        goto out;
-    }
-
-out:
-    return ret;
-}
-static int __init wmt_secure_wait_wake_init(void)
-{
-	/* if secure os disabled, we do not setup stubs */
-	if (wmt_check_secure_env())
-		return -EINVAL;
-
-	wmt_setup_wait_stub((u32)wmt_smc_wait_stub);
-	wmt_setup_wake_stub((u32)wmt_smc_wake_stub);
-
-	return 0;
-}
-module_init(wmt_secure_wait_wake_init);
-
-static void __exit wmt_secure_wait_wake_exit(void)
-{
-	return ;
-}
-module_exit(wmt_secure_wait_wake_exit);
-
-MODULE_AUTHOR("WonderMedia Technologies, Inc");
-MODULE_DESCRIPTION("WMT Secure Wait & Wake Implementation");
-MODULE_LICENSE("Dual BSD/GPL");
diff --git a/ANDROID_3.4.5/arch/arm/mach-wmt/wmt_smc.c b/ANDROID_3.4.5/arch/arm/mach-wmt/wmt_smc.c
deleted file mode 100755
index 64257bd9..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-wmt/wmt_smc.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/*++
-	linux/arch/arm/mach-wmt/wmt_clock.c
-
-	Copyright (c) 2013  WonderMedia Technologies, Inc.
-
-	This program is free software: you can redistribute it and/or modify it under the
-	terms of the GNU General Public License as published by the Free Software Foundation,
-	either version 2 of the License, or (at your option) any later version.
-
-	This program is distributed in the hope that it will be useful, but WITHOUT
-	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-	PARTICULAR PURPOSE.  See the GNU General Public License for more details.
-	You should have received a copy of the GNU General Public License along with
-	this program.  If not, see <http://www.gnu.org/licenses/>.
-
-	WonderMedia Technologies, Inc.
-	10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
---*/
-
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/module.h>
-#include <linux/fs.h>
-#include <linux/platform_device.h>
-#include <linux/debugfs.h>
-#include <linux/cdev.h>
-#include <linux/uaccess.h>
-#include <linux/sched.h>
-#include <linux/list.h>
-#include <linux/mutex.h>
-#include <linux/io.h>
-#include <linux/interrupt.h>
-#include <linux/wait.h>
-#include <linux/linkage.h>
-
-
-
-
-#ifdef CONFIG_OTZONE_ASYNC_NOTIFY_SUPPORT
-#include <linux/smp.h>
-#endif
-
-struct smc_cdata {
-    unsigned int fn;
-    unsigned int arg;
-    unsigned int ret;
-};
-
-
-
-/**
- * @brief 
- *
- * @param otz_smc handler for secondary cores
- *
- * @return 
- */
-
-static u32 wmt_smc1(u32 fn, u32 arg)
-{
-	register u32 r0 asm("r0") = fn;
-	register u32 r1 asm("r1") = arg;
-	
-	do {
-	asm volatile(
-		".arch_extension sec\n\t"
-		__asmeq("%0", "r0")
-		__asmeq("%1", "r0")
-		__asmeq("%2", "r1")
-		"smc    #0  @ switch to secure world\n"
-		: "=r" (r0)
-		: "r" (r0), "r" (r1));
-	} while (0);
-
-	return r0;
-}
-
-
-static void wmt_secondary_smc_handler(void *info)
-{
-	struct smc_cdata *cd = (struct smc_cdata *)info;
-	rmb();
-
-	cd->ret = wmt_smc1(cd->fn, cd->arg);
-	wmb();
-}
-
-
-/**
- * @brief 
- *
- * @param This function takes care of posting the smc to the 
- *        primary core
- *
- * @return 
- */
-static unsigned int post_otz_smc(int cpu_id, u32 fn, u32 arg)
-{
-	struct smc_cdata cd;
-
-	
-	cd.fn = fn;
-	cd.arg  = arg;
-	wmb();
-
-	smp_call_function_single(0, wmt_secondary_smc_handler, 
-				 (void *)&cd, 1);
-	rmb();
-
-	return cd.ret;
-}
-
-
-/**
- * @brief 
- *
- * @param otz_smc wrapper to handle the multi core case
- *
- * @return 
- */
-unsigned int wmt_smc(u32 fn, u32 arg)
-{
-	int cpu_id = smp_processor_id();
-	unsigned int ret;
-	
-	if (cpu_id != 0) {
-		mb();
-		ret = post_otz_smc(cpu_id, fn, arg); /* post it to primary */
-	} else {
-		ret = wmt_smc1(fn, arg); /* called directly on primary core */
-	}
-
-	return ret;
-}
-
-
-MODULE_AUTHOR("WonderMedia Technologies, Inc");
-MODULE_DESCRIPTION("WMT SMC Function");
-MODULE_LICENSE("Dual BSD/GPL");