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authorKevin2014-11-15 09:58:27 +0800
committerKevin2014-11-15 09:58:27 +0800
commit392e8802486cb573b916e746010e141a75f507e6 (patch)
tree50029aca02c81f087b90336e670b44e510782330 /ANDROID_3.4.5/arch/arm/mach-sa1100/include/mach/memory.h
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init android origin source code
Diffstat (limited to 'ANDROID_3.4.5/arch/arm/mach-sa1100/include/mach/memory.h')
-rw-r--r--ANDROID_3.4.5/arch/arm/mach-sa1100/include/mach/memory.h41
1 files changed, 41 insertions, 0 deletions
diff --git a/ANDROID_3.4.5/arch/arm/mach-sa1100/include/mach/memory.h b/ANDROID_3.4.5/arch/arm/mach-sa1100/include/mach/memory.h
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+++ b/ANDROID_3.4.5/arch/arm/mach-sa1100/include/mach/memory.h
@@ -0,0 +1,41 @@
+/*
+ * arch/arm/mach-sa1100/include/mach/memory.h
+ *
+ * Copyright (C) 1999-2000 Nicolas Pitre <nico@fluxnic.net>
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#include <asm/sizes.h>
+
+/*
+ * Physical DRAM offset is 0xc0000000 on the SA1100
+ */
+#define PLAT_PHYS_OFFSET UL(0xc0000000)
+
+/*
+ * Because of the wide memory address space between physical RAM banks on the
+ * SA1100, it's much convenient to use Linux's SparseMEM support to implement
+ * our memory map representation. Assuming all memory nodes have equal access
+ * characteristics, we then have generic discontiguous memory support.
+ *
+ * The sparsemem banks are matched with the physical memory bank addresses
+ * which are incidentally the same as virtual addresses.
+ *
+ * node 0: 0xc0000000 - 0xc7ffffff
+ * node 1: 0xc8000000 - 0xcfffffff
+ * node 2: 0xd0000000 - 0xd7ffffff
+ * node 3: 0xd8000000 - 0xdfffffff
+ */
+#define MAX_PHYSMEM_BITS 32
+#define SECTION_SIZE_BITS 27
+
+/*
+ * Cache flushing area - SA1100 zero bank
+ */
+#define FLUSH_BASE_PHYS 0xe0000000
+#define FLUSH_BASE 0xf5000000
+#define FLUSH_BASE_MINICACHE 0xf5100000
+
+#endif