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author | Kevin | 2014-11-15 09:58:27 +0800 |
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committer | Kevin | 2014-11-15 09:58:27 +0800 |
commit | 392e8802486cb573b916e746010e141a75f507e6 (patch) | |
tree | 50029aca02c81f087b90336e670b44e510782330 /ANDROID_3.4.5/arch/arm/mach-pnx4008/include/mach/irq.h | |
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init android origin source code
Diffstat (limited to 'ANDROID_3.4.5/arch/arm/mach-pnx4008/include/mach/irq.h')
-rw-r--r-- | ANDROID_3.4.5/arch/arm/mach-pnx4008/include/mach/irq.h | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/ANDROID_3.4.5/arch/arm/mach-pnx4008/include/mach/irq.h b/ANDROID_3.4.5/arch/arm/mach-pnx4008/include/mach/irq.h new file mode 100644 index 00000000..2a690ca3 --- /dev/null +++ b/ANDROID_3.4.5/arch/arm/mach-pnx4008/include/mach/irq.h @@ -0,0 +1,42 @@ +/* + * arch/arm/mach-pnx4008/include/mach/irq.h + * + * PNX4008 IRQ controller driver - header file + * this one is used in entry-arnv.S as well so it cannot contain C code + * + * Copyright (c) 2005 Philips Semiconductors + * Copyright (c) 2005 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#ifndef __PNX4008_IRQ_H__ +#define __PNX4008_IRQ_H__ + +#define MIC_VA_BASE IO_ADDRESS(PNX4008_INTCTRLMIC_BASE) +#define SIC1_VA_BASE IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE) +#define SIC2_VA_BASE IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE) + +/* Manual: Chapter 20, page 195 */ + +#define INTC_BIT(irq) (1<< ((irq) & 0x1F)) + +#define INTC_ER(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x0 + (((irq)&(0x3<<5))<<9))) +#define INTC_RSR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x4 + (((irq)&(0x3<<5))<<9))) +#define INTC_SR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x8 + (((irq)&(0x3<<5))<<9))) +#define INTC_APR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0xC + (((irq)&(0x3<<5))<<9))) +#define INTC_ATR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x10 + (((irq)&(0x3<<5))<<9))) +#define INTC_ITR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x14 + (((irq)&(0x3<<5))<<9))) + +#define START_INT_REG_BIT(irq) (1<<((irq)&0x1F)) + +#define START_INT_ER_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x20 + (((irq)&(0x1<<5))>>1))) +#define START_INT_RSR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x24 + (((irq)&(0x1<<5))>>1))) +#define START_INT_SR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x28 + (((irq)&(0x1<<5))>>1))) +#define START_INT_APR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x2C + (((irq)&(0x1<<5))>>1))) + +extern void __init pnx4008_init_irq(void); + +#endif /* __PNX4008_IRQ_H__ */ |