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| author | Srikant Patnaik | 2015-01-11 12:28:04 +0530 |
|---|---|---|
| committer | Srikant Patnaik | 2015-01-11 12:28:04 +0530 |
| commit | 871480933a1c28f8a9fed4c4d34d06c439a7a422 (patch) | |
| tree | 8718f573808810c2a1e8cb8fb6ac469093ca2784 /ANDROID_3.4.5/arch/arm/mach-orion5x/include/mach/bridge-regs.h | |
| parent | 9d40ac5867b9aefe0722bc1f110b965ff294d30d (diff) | |
| download | FOSSEE-netbook-kernel-source-871480933a1c28f8a9fed4c4d34d06c439a7a422.tar.gz FOSSEE-netbook-kernel-source-871480933a1c28f8a9fed4c4d34d06c439a7a422.tar.bz2 FOSSEE-netbook-kernel-source-871480933a1c28f8a9fed4c4d34d06c439a7a422.zip | |
Moved, renamed, and deleted files
The original directory structure was scattered and unorganized.
Changes are basically to make it look like kernel structure.
Diffstat (limited to 'ANDROID_3.4.5/arch/arm/mach-orion5x/include/mach/bridge-regs.h')
| -rw-r--r-- | ANDROID_3.4.5/arch/arm/mach-orion5x/include/mach/bridge-regs.h | 39 |
1 files changed, 0 insertions, 39 deletions
diff --git a/ANDROID_3.4.5/arch/arm/mach-orion5x/include/mach/bridge-regs.h b/ANDROID_3.4.5/arch/arm/mach-orion5x/include/mach/bridge-regs.h deleted file mode 100644 index 11a3c1e9..00000000 --- a/ANDROID_3.4.5/arch/arm/mach-orion5x/include/mach/bridge-regs.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * arch/arm/mach-orion5x/include/mach/bridge-regs.h - * - * Orion CPU Bridge Registers - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_BRIDGE_REGS_H -#define __ASM_ARCH_BRIDGE_REGS_H - -#include <mach/orion5x.h> - -#define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE | 0x100) - -#define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE | 0x104) - -#define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x108) -#define WDT_RESET_OUT_EN 0x0002 - -#define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE | 0x10c) - -#define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE | 0x110) - -#define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE | 0x11C) - -#define WDT_INT_REQ 0x0008 - -#define BRIDGE_INT_TIMER1_CLR (~0x0004) - -#define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE | 0x200) - -#define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x204) - -#define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE | 0x300) -#define TIMER_PHYS_BASE (ORION5X_BRIDGE_PHYS_BASE | 0x300) -#endif |