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authorSrikant Patnaik2015-01-11 12:28:04 +0530
committerSrikant Patnaik2015-01-11 12:28:04 +0530
commit871480933a1c28f8a9fed4c4d34d06c439a7a422 (patch)
tree8718f573808810c2a1e8cb8fb6ac469093ca2784 /ANDROID_3.4.5/arch/arm/mach-bcmring/include/mach/entry-macro.S
parent9d40ac5867b9aefe0722bc1f110b965ff294d30d (diff)
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Moved, renamed, and deleted files
The original directory structure was scattered and unorganized. Changes are basically to make it look like kernel structure.
Diffstat (limited to 'ANDROID_3.4.5/arch/arm/mach-bcmring/include/mach/entry-macro.S')
-rw-r--r--ANDROID_3.4.5/arch/arm/mach-bcmring/include/mach/entry-macro.S76
1 files changed, 0 insertions, 76 deletions
diff --git a/ANDROID_3.4.5/arch/arm/mach-bcmring/include/mach/entry-macro.S b/ANDROID_3.4.5/arch/arm/mach-bcmring/include/mach/entry-macro.S
deleted file mode 100644
index 2f316f0e..00000000
--- a/ANDROID_3.4.5/arch/arm/mach-bcmring/include/mach/entry-macro.S
+++ /dev/null
@@ -1,76 +0,0 @@
-/*****************************************************************************
-* Copyright 2006 - 2008 Broadcom Corporation. All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/*
- *
- * Low-level IRQ helper macros for BCMRing-based platforms
- *
- */
-#include <mach/irqs.h>
-#include <mach/hardware.h>
-#include <mach/csp/mm_io.h>
-
- .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
- ldr \base, =(MM_IO_BASE_INTC0)
- ldr \irqstat, [\base, #0] @ get status
- ldr \irqnr, [\base, #0x10] @ mask with enable register
- ands \irqstat, \irqstat, \irqnr
- mov \irqnr, #IRQ_INTC0_START
- cmp \irqstat, #0
- bne 1001f
-
- ldr \base, =(MM_IO_BASE_INTC1)
- ldr \irqstat, [\base, #0] @ get status
- ldr \irqnr, [\base, #0x10] @ mask with enable register
- ands \irqstat, \irqstat, \irqnr
- mov \irqnr, #IRQ_INTC1_START
- cmp \irqstat, #0
- bne 1001f
-
- ldr \base, =(MM_IO_BASE_SINTC)
- ldr \irqstat, [\base, #0] @ get status
- ldr \irqnr, [\base, #0x10] @ mask with enable register
- ands \irqstat, \irqstat, \irqnr
- mov \irqnr, #0xffffffff @ code meaning no interrupt bits set
- cmp \irqstat, #0
- beq 1002f
-
- mov \irqnr, #IRQ_SINTC_START @ something is set, so fixup return value
-
-1001:
- movs \tmp, \irqstat, lsl #16
- movne \irqstat, \tmp
- addeq \irqnr, \irqnr, #16
-
- movs \tmp, \irqstat, lsl #8
- movne \irqstat, \tmp
- addeq \irqnr, \irqnr, #8
-
- movs \tmp, \irqstat, lsl #4
- movne \irqstat, \tmp
- addeq \irqnr, \irqnr, #4
-
- movs \tmp, \irqstat, lsl #2
- movne \irqstat, \tmp
- addeq \irqnr, \irqnr, #2
-
- movs \tmp, \irqstat, lsl #1
- addeq \irqnr, \irqnr, #1
- orrs \base, \base, #1
-
-1002: @ irqnr will be set to 0xffffffff if no irq bits are set
- .endm
-
- .macro get_irqnr_preamble, base, tmp
- .endm