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author | Kevin | 2014-11-15 09:58:27 +0800 |
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committer | Kevin | 2014-11-15 09:58:27 +0800 |
commit | 392e8802486cb573b916e746010e141a75f507e6 (patch) | |
tree | 50029aca02c81f087b90336e670b44e510782330 /ANDROID_3.4.5/arch/alpha/include/asm/auxvec.h | |
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init android origin source code
Diffstat (limited to 'ANDROID_3.4.5/arch/alpha/include/asm/auxvec.h')
-rw-r--r-- | ANDROID_3.4.5/arch/alpha/include/asm/auxvec.h | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/ANDROID_3.4.5/arch/alpha/include/asm/auxvec.h b/ANDROID_3.4.5/arch/alpha/include/asm/auxvec.h new file mode 100644 index 00000000..a3a579df --- /dev/null +++ b/ANDROID_3.4.5/arch/alpha/include/asm/auxvec.h @@ -0,0 +1,26 @@ +#ifndef __ASM_ALPHA_AUXVEC_H +#define __ASM_ALPHA_AUXVEC_H + +/* Reserve these numbers for any future use of a VDSO. */ +#if 0 +#define AT_SYSINFO 32 +#define AT_SYSINFO_EHDR 33 +#endif + +/* More complete cache descriptions than AT_[DIU]CACHEBSIZE. If the + value is -1, then the cache doesn't exist. Otherwise: + + bit 0-3: Cache set-associativity; 0 means fully associative. + bit 4-7: Log2 of cacheline size. + bit 8-31: Size of the entire cache >> 8. + bit 32-63: Reserved. +*/ + +#define AT_L1I_CACHESHAPE 34 +#define AT_L1D_CACHESHAPE 35 +#define AT_L2_CACHESHAPE 36 +#define AT_L3_CACHESHAPE 37 + +#define AT_VECTOR_SIZE_ARCH 4 /* entries in ARCH_DLINFO */ + +#endif /* __ASM_ALPHA_AUXVEC_H */ |