CD4020

15 files changed, 941 insertions, 0 deletions

diff --git a/library/SubcircuitLibrary/CD4020/CD4020-cache.lib b/library/SubcircuitLibrary/CD4020/CD4020-cache.lib
new file mode 100644
index 00000000..e31a0f39
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4020/CD4020-cache.lib
@@ -0,0 +1,50 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# DC
+#
+DEF DC v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 w
+X - 2 0 -450 300 U 50 50 1 1 w
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# tff
+#
+DEF tff X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "tff" 0 100 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -350 450 350 -350 0 1 0 N
+X t 1 -550 300 200 R 50 50 1 1 I
+X clk 2 -550 0 200 R 50 50 1 1 I C
+X Q 3 550 300 200 L 50 50 1 1 O
+X reset 4 0 -550 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/CD4020/CD4020.cir b/library/SubcircuitLibrary/CD4020/CD4020.cir
new file mode 100644
index 00000000..f5ec12b2
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4020/CD4020.cir
@@ -0,0 +1,25 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD4020\CD4020.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 5/19/2025 7:29:56 PM
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1  vdd clk q1 rst tff		
+X2  vdd q1 q2 rst tff		
+X3  vdd q2 q3 rst tff		
+X4  vdd q3 q4 rst tff		
+X5  vdd q4 q5 rst tff		
+X6  vdd q5 q6 rst tff		
+X7  vdd q6 q7 rst tff		
+X8  vdd q7 q8 rst tff		
+X9  vdd q8 q9 rst tff		
+X10  vdd q9 q10 rst tff		
+X11  vdd q10 q11 rst tff		
+X12  vdd q11 q12 rst tff		
+v1  vdd GND 5v		
+X13  vdd q12 q13 rst tff		
+X14  vdd q13 q14 rst tff		
+
+.end
diff --git a/library/SubcircuitLibrary/CD4020/CD4020.cir.out b/library/SubcircuitLibrary/CD4020/CD4020.cir.out
new file mode 100644
index 00000000..86441caf
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4020/CD4020.cir.out
@@ -0,0 +1,27 @@
+* c:\fossee\esim\library\subcircuitlibrary\cd4020\cd4020.cir
+
+.include tff.sub
+x1 vdd clk q1 rst tff
+x2 vdd q1 q2 rst tff
+x3 vdd q2 q3 rst tff
+x4 vdd q3 q4 rst tff
+x5 vdd q4 q5 rst tff
+x6 vdd q5 q6 rst tff
+x7 vdd q6 q7 rst tff
+x8 vdd q7 q8 rst tff
+x9 vdd q8 q9 rst tff
+x10 vdd q9 q10 rst tff
+x11 vdd q10 q11 rst tff
+x12 vdd q11 q12 rst tff
+v1  vdd gnd 5v
+x13 vdd q12 q13 rst tff
+x14 vdd q13 q14 rst tff
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/CD4020/CD4020.pro b/library/SubcircuitLibrary/CD4020/CD4020.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4020/CD4020.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/CD4020/CD4020.sch b/library/SubcircuitLibrary/CD4020/CD4020.sch
new file mode 100644
index 00000000..59e6d8dc
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4020/CD4020.sch
@@ -0,0 +1,347 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:CD4040-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L tff X1
+U 1 1 682B38DE
+P 1900 2900
+F 0 "X1" H 1900 2900 60  0000 C CNN
+F 1 "tff" H 1900 3000 60  0000 C CNN
+F 2 "" H 1900 2900 60  0001 C CNN
+F 3 "" H 1900 2900 60  0001 C CNN
+	1    1900 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L tff X2
+U 1 1 682B38DF
+P 3250 2900
+F 0 "X2" H 3250 2900 60  0000 C CNN
+F 1 "tff" H 3250 3000 60  0000 C CNN
+F 2 "" H 3250 2900 60  0001 C CNN
+F 3 "" H 3250 2900 60  0001 C CNN
+	1    3250 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L tff X3
+U 1 1 682B38E0
+P 4550 2900
+F 0 "X3" H 4550 2900 60  0000 C CNN
+F 1 "tff" H 4550 3000 60  0000 C CNN
+F 2 "" H 4550 2900 60  0001 C CNN
+F 3 "" H 4550 2900 60  0001 C CNN
+	1    4550 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L tff X4
+U 1 1 682B38E1
+P 5900 2900
+F 0 "X4" H 5900 2900 60  0000 C CNN
+F 1 "tff" H 5900 3000 60  0000 C CNN
+F 2 "" H 5900 2900 60  0001 C CNN
+F 3 "" H 5900 2900 60  0001 C CNN
+	1    5900 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L tff X5
+U 1 1 682B38E2
+P 7250 2900
+F 0 "X5" H 7250 2900 60  0000 C CNN
+F 1 "tff" H 7250 3000 60  0000 C CNN
+F 2 "" H 7250 2900 60  0001 C CNN
+F 3 "" H 7250 2900 60  0001 C CNN
+	1    7250 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L tff X6
+U 1 1 682B38E3
+P 8700 2900
+F 0 "X6" H 8700 2900 60  0000 C CNN
+F 1 "tff" H 8700 3000 60  0000 C CNN
+F 2 "" H 8700 2900 60  0001 C CNN
+F 3 "" H 8700 2900 60  0001 C CNN
+	1    8700 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L tff X7
+U 1 1 682B38E4
+P 10050 2900
+F 0 "X7" H 10050 2900 60  0000 C CNN
+F 1 "tff" H 10050 3000 60  0000 C CNN
+F 2 "" H 10050 2900 60  0001 C CNN
+F 3 "" H 10050 2900 60  0001 C CNN
+	1    10050 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L tff X8
+U 1 1 682B38E5
+P 11400 2900
+F 0 "X8" H 11400 2900 60  0000 C CNN
+F 1 "tff" H 11400 3000 60  0000 C CNN
+F 2 "" H 11400 2900 60  0001 C CNN
+F 3 "" H 11400 2900 60  0001 C CNN
+	1    11400 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L tff X9
+U 1 1 682B38E6
+P 12850 2900
+F 0 "X9" H 12850 2900 60  0000 C CNN
+F 1 "tff" H 12850 3000 60  0000 C CNN
+F 2 "" H 12850 2900 60  0001 C CNN
+F 3 "" H 12850 2900 60  0001 C CNN
+	1    12850 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L tff X10
+U 1 1 682B38E7
+P 14350 2900
+F 0 "X10" H 14350 2900 60  0000 C CNN
+F 1 "tff" H 14350 3000 60  0000 C CNN
+F 2 "" H 14350 2900 60  0001 C CNN
+F 3 "" H 14350 2900 60  0001 C CNN
+	1    14350 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L tff X11
+U 1 1 682B38E8
+P 15850 2900
+F 0 "X11" H 15850 2900 60  0000 C CNN
+F 1 "tff" H 15850 3000 60  0000 C CNN
+F 2 "" H 15850 2900 60  0001 C CNN
+F 3 "" H 15850 2900 60  0001 C CNN
+	1    15850 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L tff X12
+U 1 1 682B38E9
+P 17300 2900
+F 0 "X12" H 17300 2900 60  0000 C CNN
+F 1 "tff" H 17300 3000 60  0000 C CNN
+F 2 "" H 17300 2900 60  0001 C CNN
+F 3 "" H 17300 2900 60  0001 C CNN
+	1    17300 2900
+	1    0    0    -1  
+$EndComp
+Text GLabel 1350 2600 1    60   Input ~ 0
+vdd
+Text GLabel 2700 2600 1    60   Input ~ 0
+vdd
+Text GLabel 4000 2600 1    60   Input ~ 0
+vdd
+Text GLabel 5350 2600 1    60   Input ~ 0
+vdd
+Text GLabel 6700 2600 1    60   Input ~ 0
+vdd
+Text GLabel 8150 2600 1    60   Input ~ 0
+vdd
+Text GLabel 9500 2600 1    60   Input ~ 0
+vdd
+Text GLabel 10850 2600 1    60   Input ~ 0
+vdd
+Text GLabel 12300 2600 1    60   Input ~ 0
+vdd
+Text GLabel 13800 2600 1    60   Input ~ 0
+vdd
+Text GLabel 15300 2600 1    60   Input ~ 0
+vdd
+Text GLabel 16750 2600 1    60   Input ~ 0
+vdd
+Text GLabel 1350 2900 0    60   Input ~ 0
+clk
+Text GLabel 1900 3450 0    60   Input ~ 0
+rst
+Text GLabel 3250 3450 0    60   Input ~ 0
+rst
+Text GLabel 4550 3450 0    60   Input ~ 0
+rst
+Text GLabel 5900 3450 0    60   Input ~ 0
+rst
+Text GLabel 7250 3450 0    60   Input ~ 0
+rst
+Text GLabel 8700 3450 0    60   Input ~ 0
+rst
+Text GLabel 10050 3450 0    60   Input ~ 0
+rst
+Text GLabel 11400 3450 0    60   Input ~ 0
+rst
+Text GLabel 12850 3450 0    60   Input ~ 0
+rst
+Text GLabel 14350 3450 0    60   Input ~ 0
+rst
+Text GLabel 15850 3450 0    60   Input ~ 0
+rst
+Text GLabel 17300 3450 0    60   Input ~ 0
+rst
+Text GLabel 2450 2600 1    60   Input ~ 0
+q1
+Text GLabel 2700 2900 0    60   Input ~ 0
+q1
+Text GLabel 3800 2600 1    60   Input ~ 0
+q2
+Text GLabel 4000 2900 0    60   Input ~ 0
+q2
+Text GLabel 5100 2600 1    60   Input ~ 0
+q3
+Text GLabel 5350 2900 0    60   Input ~ 0
+q3
+Text GLabel 6450 2600 1    60   Input ~ 0
+q4
+Text GLabel 6700 2900 0    60   Input ~ 0
+q4
+Text GLabel 7800 2600 1    60   Input ~ 0
+q5
+Text GLabel 8150 2900 0    60   Input ~ 0
+q5
+Text GLabel 9250 2600 1    60   Input ~ 0
+q6
+Text GLabel 9500 2900 0    60   Input ~ 0
+q6
+Text GLabel 10600 2600 1    60   Input ~ 0
+q7
+Text GLabel 10850 2900 0    60   Input ~ 0
+q7
+Text GLabel 11950 2600 1    60   Input ~ 0
+q8
+Text GLabel 12300 2900 0    60   Input ~ 0
+q8
+Text GLabel 13400 2600 1    60   Input ~ 0
+q9
+Text GLabel 13800 2900 0    60   Input ~ 0
+q9
+Text GLabel 14900 2600 1    60   Input ~ 0
+q10
+Text GLabel 15300 2900 0    60   Input ~ 0
+q10
+Text GLabel 16400 2600 1    60   Input ~ 0
+q11
+Text GLabel 16750 2900 0    60   Input ~ 0
+q11
+Text GLabel 17850 2600 1    60   Input ~ 0
+q12
+$Comp
+L DC v1
+U 1 1 682B38EA
+P 7500 5000
+F 0 "v1" H 7300 5100 60  0000 C CNN
+F 1 "5v" H 7300 4950 60  0000 C CNN
+F 2 "R1" H 7200 5000 60  0000 C CNN
+F 3 "" H 7500 5000 60  0000 C CNN
+	1    7500 5000
+	1    0    0    -1  
+$EndComp
+Text GLabel 7500 4550 1    60   Input ~ 0
+vdd
+$Comp
+L GND #PWR1
+U 1 1 682B38EB
+P 7500 5450
+F 0 "#PWR1" H 7500 5200 50  0001 C CNN
+F 1 "GND" H 7500 5300 50  0000 C CNN
+F 2 "" H 7500 5450 50  0001 C CNN
+F 3 "" H 7500 5450 50  0001 C CNN
+	1    7500 5450
+	1    0    0    -1  
+$EndComp
+$Comp
+L tff X13
+U 1 1 682B3B08
+P 18750 2900
+F 0 "X13" H 18750 2900 60  0000 C CNN
+F 1 "tff" H 18750 3000 60  0000 C CNN
+F 2 "" H 18750 2900 60  0001 C CNN
+F 3 "" H 18750 2900 60  0001 C CNN
+	1    18750 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L tff X14
+U 1 1 682B3B0E
+P 20200 2900
+F 0 "X14" H 20200 2900 60  0000 C CNN
+F 1 "tff" H 20200 3000 60  0000 C CNN
+F 2 "" H 20200 2900 60  0001 C CNN
+F 3 "" H 20200 2900 60  0001 C CNN
+	1    20200 2900
+	1    0    0    -1  
+$EndComp
+Text GLabel 18200 2600 1    60   Input ~ 0
+vdd
+Text GLabel 19650 2600 1    60   Input ~ 0
+vdd
+Text GLabel 18750 3450 0    60   Input ~ 0
+rst
+Text GLabel 20200 3450 0    60   Input ~ 0
+rst
+Text GLabel 18200 2900 0    60   Input ~ 0
+q12
+Text GLabel 19300 2600 1    60   Input ~ 0
+q13
+Text GLabel 19650 2900 0    60   Input ~ 0
+q13
+Text GLabel 20750 2600 1    60   Input ~ 0
+q14
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/CD4020/CD4020.sub b/library/SubcircuitLibrary/CD4020/CD4020.sub
new file mode 100644
index 00000000..5dd18575
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4020/CD4020.sub
@@ -0,0 +1,18 @@
+.subckt CD4020 q12 q13 q14 q6 q5 q7 q4 ? q1 clk rst q9 q8 q10 q11 ?
+.include tff.sub
+x1 vdd clk q1 rst tff
+x2 vdd q1 q2 rst tff
+x3 vdd q2 q3 rst tff
+x4 vdd q3 q4 rst tff
+x5 vdd q4 q5 rst tff
+x6 vdd q5 q6 rst tff
+x7 vdd q6 q7 rst tff
+x8 vdd q7 q8 rst tff
+x9 vdd q8 q9 rst tff
+x10 vdd q9 q10 rst tff
+x11 vdd q10 q11 rst tff
+x12 vdd q11 q12 rst tff
+v1  vdd gnd 5v
+x13 vdd q12 q13 rst tff
+x14 vdd q13 q14 rst tff
+.ends
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4020/CD4020_Previous_Values.xml b/library/SubcircuitLibrary/CD4020/CD4020_Previous_Values.xml
new file mode 100644
index 00000000..55686a60
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4020/CD4020_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source><v1 name="Source type">5v</v1></source><model /><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\tff</field></x1><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\tff</field></x2><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\tff</field></x3><x4><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\tff</field></x4><x5><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\tff</field></x5><x6><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\tff</field></x6><x7><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\tff</field></x7><x8><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\tff</field></x8><x9><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\tff</field></x9><x10><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\tff</field></x10><x11><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\tff</field></x11><x12><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\tff</field></x12><x13><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\tff</field></x13><x14><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\tff</field></x14></subcircuit></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4020/analysis b/library/SubcircuitLibrary/CD4020/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4020/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4020/tff-cache.lib b/library/SubcircuitLibrary/CD4020/tff-cache.lib
new file mode 100644
index 00000000..7a72fdc7
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4020/tff-cache.lib
@@ -0,0 +1,83 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# GND
+#
+DEF GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_4
+#
+DEF adc_bridge_4 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_4" 0 300 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -350 350 350 -200 0 1 0 N
+X IN1 1 -550 200 200 R 50 50 1 1 I
+X IN2 2 -550 100 200 R 50 50 1 1 I
+X IN3 3 -550 0 200 R 50 50 1 1 I
+X IN4 4 -550 -100 200 R 50 50 1 1 I
+X OUT1 5 550 200 200 L 50 50 1 1 O
+X OUT2 6 550 100 200 L 50 50 1 1 O
+X OUT3 7 550 0 200 L 50 50 1 1 O
+X OUT4 8 550 -100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_tff
+#
+DEF d_tff U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_tff" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S 350 450 -350 -400 0 1 0 N
+X T 1 -550 350 200 R 50 50 1 1 I
+X Clk 2 -550 -300 200 R 50 50 1 1 I C
+X Set 3 0 650 200 D 50 50 1 1 I
+X Reset 4 0 -600 200 U 50 50 1 1 I
+X Out 5 550 350 200 L 50 50 1 1 O
+X Nout 6 550 -300 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_1
+#
+DEF dac_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/CD4020/tff.cir b/library/SubcircuitLibrary/CD4020/tff.cir
new file mode 100644
index 00000000..3443d1e3
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4020/tff.cir
@@ -0,0 +1,15 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\tff\tff.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 5/3/2025 3:33:18 PM
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U3  Net-_U1-Pad5_ Net-_U2-Pad2_ Net-_U1-Pad7_ Net-_U1-Pad8_ a1 Net-_U3-Pad6_ d_tff		
+U1  t clk GND reset Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ adc_bridge_4		
+U5  a1 q dac_bridge_1		
+U4  Net-_U3-Pad6_ qb dac_bridge_1		
+U2  Net-_U1-Pad6_ Net-_U2-Pad2_ d_inverter		
+
+.end
diff --git a/library/SubcircuitLibrary/CD4020/tff.cir.out b/library/SubcircuitLibrary/CD4020/tff.cir.out
new file mode 100644
index 00000000..8f3c42f5
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4020/tff.cir.out
@@ -0,0 +1,31 @@
+* c:\fossee\esim\library\subcircuitlibrary\tff\tff.cir
+
+* u3  net-_u1-pad5_ net-_u2-pad2_ net-_u1-pad7_ net-_u1-pad8_ a1 net-_u3-pad6_ d_tff
+* u1  t clk gnd reset net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ adc_bridge_4
+* u5  a1 q dac_bridge_1
+* u4  net-_u3-pad6_ qb dac_bridge_1
+* u2  net-_u1-pad6_ net-_u2-pad2_ d_inverter
+a1 net-_u1-pad5_ net-_u2-pad2_ net-_u1-pad7_ net-_u1-pad8_ a1 net-_u3-pad6_ u3
+a2 [t clk gnd reset ] [net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ ] u1
+a3 [a1 ] [q ] u5
+a4 [net-_u3-pad6_ ] [qb ] u4
+a5 net-_u1-pad6_ net-_u2-pad2_ u2
+* Schematic Name:                             d_tff, NgSpice Name: d_tff
+.model u3 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_4, NgSpice Name: adc_bridge
+.model u1 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u5 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u4 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/CD4020/tff.pro b/library/SubcircuitLibrary/CD4020/tff.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4020/tff.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/CD4020/tff.sch b/library/SubcircuitLibrary/CD4020/tff.sch
new file mode 100644
index 00000000..ef3e1e1a
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4020/tff.sch
@@ -0,0 +1,179 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:asw-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_tff U3
+U 1 1 6815E4DD
+P 8150 2800
+F 0 "U3" H 8150 2800 60  0000 C CNN
+F 1 "d_tff" H 8150 2950 60  0000 C CNN
+F 2 "" H 8150 2800 60  0000 C CNN
+F 3 "" H 8150 2800 60  0000 C CNN
+	1    8150 2800
+	1    0    0    -1  
+$EndComp
+$Comp
+L adc_bridge_4 U1
+U 1 1 6815E4DE
+P 5050 2800
+F 0 "U1" H 5050 2800 60  0000 C CNN
+F 1 "adc_bridge_4" H 5050 3100 60  0000 C CNN
+F 2 "" H 5050 2800 60  0000 C CNN
+F 3 "" H 5050 2800 60  0000 C CNN
+	1    5050 2800
+	1    0    0    -1  
+$EndComp
+$Comp
+L dac_bridge_1 U5
+U 1 1 6815E4DF
+P 9350 2500
+F 0 "U5" H 9350 2500 60  0000 C CNN
+F 1 "dac_bridge_1" H 9350 2650 60  0000 C CNN
+F 2 "" H 9350 2500 60  0000 C CNN
+F 3 "" H 9350 2500 60  0000 C CNN
+	1    9350 2500
+	1    0    0    -1  
+$EndComp
+$Comp
+L dac_bridge_1 U4
+U 1 1 6815E4E0
+P 9300 3150
+F 0 "U4" H 9300 3150 60  0000 C CNN
+F 1 "dac_bridge_1" H 9300 3300 60  0000 C CNN
+F 2 "" H 9300 3150 60  0000 C CNN
+F 3 "" H 9300 3150 60  0000 C CNN
+	1    9300 3150
+	1    0    0    -1  
+$EndComp
+Text GLabel 9900 2450 2    60   Input ~ 0
+q
+Text GLabel 9850 3100 2    60   Input ~ 0
+qb
+Text GLabel 4500 2600 1    60   Input ~ 0
+t
+Text GLabel 4500 2700 0    60   Input ~ 0
+clk
+Text GLabel 4500 2900 0    60   Input ~ 0
+reset
+$Comp
+L GND #PWR1
+U 1 1 6815E4E1
+P 4500 2800
+F 0 "#PWR1" H 4500 2550 50  0001 C CNN
+F 1 "GND" H 4500 2650 50  0000 C CNN
+F 2 "" H 4500 2800 50  0001 C CNN
+F 3 "" H 4500 2800 50  0001 C CNN
+	1    4500 2800
+	0    1    1    0   
+$EndComp
+Text GLabel 8700 2400 1    60   Input ~ 0
+a1
+Wire Wire Line
+	7250 3400 8150 3400
+Wire Wire Line
+	7250 2900 7250 3400
+Wire Wire Line
+	7600 2700 7600 3100
+Wire Wire Line
+	7250 2700 7600 2700
+Wire Wire Line
+	7600 2600 7600 2450
+Wire Wire Line
+	8700 2450 8750 2450
+Wire Wire Line
+	5600 2600 6400 2600
+Wire Wire Line
+	6400 2600 6400 2650
+Wire Wire Line
+	7300 2600 7600 2600
+Wire Wire Line
+	5600 2700 6400 2700
+Wire Wire Line
+	6400 2700 6400 2750
+Wire Wire Line
+	7250 2750 7250 2700
+Wire Wire Line
+	5600 2800 5850 2800
+Wire Wire Line
+	5850 2800 5850 1750
+Wire Wire Line
+	5850 1750 8150 1750
+Wire Wire Line
+	8150 1750 8150 2150
+Wire Wire Line
+	5600 2900 7250 2900
+Wire Wire Line
+	8700 2450 8700 2400
+Wire Wire Line
+	6400 2650 7300 2650
+Wire Wire Line
+	7300 2650 7300 2600
+$Comp
+L d_inverter U2
+U 1 1 6815E4E2
+P 6850 2750
+F 0 "U2" H 6850 2650 60  0000 C CNN
+F 1 "d_inverter" H 6850 2900 60  0000 C CNN
+F 2 "" H 6900 2700 60  0000 C CNN
+F 3 "" H 6900 2700 60  0000 C CNN
+	1    6850 2750
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	6400 2750 6550 2750
+Wire Wire Line
+	7150 2750 7250 2750
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/CD4020/tff.sub b/library/SubcircuitLibrary/CD4020/tff.sub
new file mode 100644
index 00000000..a70ce9cb
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4020/tff.sub
@@ -0,0 +1,17 @@
+.subckt tff t clk q reset
+a1 net-_u1-pad5_ net-_u2-pad2_ net-_u1-pad7_ net-_u1-pad8_ a1 net-_u3-pad6_ u3
+a2 [t clk gnd reset ] [net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ ] u1
+a3 [a1 ] [q ] u5
+a4 [net-_u3-pad6_ ] [qb ] u4
+a5 net-_u1-pad6_ net-_u2-pad2_ u2
+* Schematic Name:                             d_tff, NgSpice Name: d_tff
+.model u3 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_4, NgSpice Name: adc_bridge
+.model u1 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u5 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u4 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+.ends tff
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4020/tff_Previous_Values.xml b/library/SubcircuitLibrary/CD4020/tff_Previous_Values.xml
new file mode 100644
index 00000000..a1f30af7
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4020/tff_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u3 name="type">d_tff<field1 name="Enter Clk Delay (default=1.0e-9)" /><field2 name="Enter Set Delay (default=1.0e-9)" /><field3 name="Enter Reset Delay (default=1.0)" /><field4 name="Enter IC (default=0)" /><field5 name="Enter value for T Load (default=1.0e-12)" /><field6 name="Enter value for Clk Load (default=1.0e-12)" /><field7 name="Enter value for Set Load (default=1.0e-12)" /><field8 name="Enter value for Reset Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /><field10 name="Enter Fall Delay (default=1.0e-9)" /></u3><u1 name="type">adc_bridge<field11 name="Enter value for in_low (default=1.0)" /><field12 name="Enter value for in_high (default=2.0)" /><field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /></u1><u5 name="type">dac_bridge<field15 name="Enter value for out_low (default=0.0)" /><field16 name="Enter value for out_high (default=5.0)" /><field17 name="Enter value for out_undef (default=0.5)" /><field18 name="Enter value for input load (default=1.0e-12)" /><field19 name="Enter the Rise Time (default=1.0e-9)" /><field20 name="Enter the Fall Time (default=1.0e-9)" /></u5><u4 name="type">dac_bridge<field21 name="Enter value for out_low (default=0.0)" /><field22 name="Enter value for out_high (default=5.0)" /><field23 name="Enter value for out_undef (default=0.5)" /><field24 name="Enter value for input load (default=1.0e-12)" /><field25 name="Enter the Rise Time (default=1.0e-9)" /><field26 name="Enter the Fall Time (default=1.0e-9)" /></u4><u2 name="type">d_inverter<field27 name="Enter Rise Delay (default=1.0e-9)" /><field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /></u2></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file